1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 31 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 32 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 33 * PSMI 1.5 extensions are supported in Solaris Nevada. 34 * PSMI 1.6 extensions are supported in Solaris Nevada. 35 */ 36 #define PSMI_1_6 37 38 #include <sys/processor.h> 39 #include <sys/time.h> 40 #include <sys/psm.h> 41 #include <sys/smp_impldefs.h> 42 #include <sys/cram.h> 43 #include <sys/acpi/acpi.h> 44 #include <sys/acpica.h> 45 #include <sys/psm_common.h> 46 #include <sys/apic.h> 47 #include <sys/pit.h> 48 #include <sys/ddi.h> 49 #include <sys/sunddi.h> 50 #include <sys/ddi_impldefs.h> 51 #include <sys/pci.h> 52 #include <sys/promif.h> 53 #include <sys/x86_archext.h> 54 #include <sys/cpc_impl.h> 55 #include <sys/uadmin.h> 56 #include <sys/panic.h> 57 #include <sys/debug.h> 58 #include <sys/archsystm.h> 59 #include <sys/trap.h> 60 #include <sys/machsystm.h> 61 #include <sys/sysmacros.h> 62 #include <sys/cpuvar.h> 63 #include <sys/rm_platter.h> 64 #include <sys/privregs.h> 65 #include <sys/note.h> 66 #include <sys/pci_intr_lib.h> 67 #include <sys/spl.h> 68 #include <sys/clock.h> 69 #include <sys/dditypes.h> 70 #include <sys/sunddi.h> 71 72 /* 73 * Local Function Prototypes 74 */ 75 static void apic_init_intr(); 76 static void apic_ret(); 77 static int get_apic_cmd1(); 78 static int get_apic_pri(); 79 static void apic_nmi_intr(caddr_t arg, struct regs *rp); 80 81 /* 82 * standard MP entries 83 */ 84 static int apic_probe(); 85 static int apic_clkinit(); 86 static int apic_getclkirq(int ipl); 87 static uint_t apic_calibrate(volatile uint32_t *addr, 88 uint16_t *pit_ticks_adj); 89 static hrtime_t apic_gettime(); 90 static hrtime_t apic_gethrtime(); 91 static void apic_init(); 92 static void apic_picinit(void); 93 static int apic_cpu_start(processorid_t, caddr_t); 94 static int apic_post_cpu_start(void); 95 static void apic_send_ipi(int cpun, int ipl); 96 static void apic_set_idlecpu(processorid_t cpun); 97 static void apic_unset_idlecpu(processorid_t cpun); 98 static int apic_intr_enter(int ipl, int *vect); 99 static void apic_setspl(int ipl); 100 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 101 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 102 static void apic_shutdown(int cmd, int fcn); 103 static void apic_preshutdown(int cmd, int fcn); 104 static int apic_disable_intr(processorid_t cpun); 105 static void apic_enable_intr(processorid_t cpun); 106 static processorid_t apic_get_next_processorid(processorid_t cpun); 107 static int apic_get_ipivect(int ipl, int type); 108 static void apic_timer_reprogram(hrtime_t time); 109 static void apic_timer_enable(void); 110 static void apic_timer_disable(void); 111 static void apic_post_cyclic_setup(void *arg); 112 113 static int apic_oneshot = 0; 114 int apic_oneshot_enable = 1; /* to allow disabling one-shot capability */ 115 116 /* Now the ones for Dynamic Interrupt distribution */ 117 int apic_enable_dynamic_migration = 0; 118 119 120 /* 121 * These variables are frequently accessed in apic_intr_enter(), 122 * apic_intr_exit and apic_setspl, so group them together 123 */ 124 volatile uint32_t *apicadr = NULL; /* virtual addr of local APIC */ 125 int apic_setspl_delay = 1; /* apic_setspl - delay enable */ 126 int apic_clkvect; 127 128 /* vector at which error interrupts come in */ 129 int apic_errvect; 130 int apic_enable_error_intr = 1; 131 int apic_error_display_delay = 100; 132 133 /* vector at which performance counter overflow interrupts come in */ 134 int apic_cpcovf_vect; 135 int apic_enable_cpcovf_intr = 1; 136 137 /* 138 * The following vector assignments influence the value of ipltopri and 139 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 140 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 141 * we care to do so in future. Note some IPLs which are rarely used 142 * will share the vector ranges and heavily used IPLs (5 and 6) have 143 * a wide range. 144 * 145 * This array is used to initialize apic_ipls[] (in apic_init()). 146 * 147 * IPL Vector range. as passed to intr_enter 148 * 0 none. 149 * 1,2,3 0x20-0x2f 0x0-0xf 150 * 4 0x30-0x3f 0x10-0x1f 151 * 5 0x40-0x5f 0x20-0x3f 152 * 6 0x60-0x7f 0x40-0x5f 153 * 7,8,9 0x80-0x8f 0x60-0x6f 154 * 10 0x90-0x9f 0x70-0x7f 155 * 11 0xa0-0xaf 0x80-0x8f 156 * ... ... 157 * 15 0xe0-0xef 0xc0-0xcf 158 * 15 0xf0-0xff 0xd0-0xdf 159 */ 160 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 161 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 162 }; 163 /* 164 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 165 * NOTE that this is vector as passed into intr_enter which is 166 * programmed vector - 0x20 (APIC_BASE_VECT) 167 */ 168 169 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 170 /* The taskpri to be programmed into apic to mask given ipl */ 171 172 #if defined(__amd64) 173 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */ 174 #endif 175 176 /* 177 * Correlation of the hardware vector to the IPL in use, initialized 178 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 179 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 180 * connected to errata-stricken IOAPICs 181 */ 182 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 183 184 /* 185 * Patchable global variables. 186 */ 187 int apic_forceload = 0; 188 189 int apic_coarse_hrtime = 1; /* 0 - use accurate slow gethrtime() */ 190 /* 1 - use gettime() for performance */ 191 int apic_flat_model = 0; /* 0 - clustered. 1 - flat */ 192 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 193 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 194 int apic_panic_on_nmi = 0; 195 int apic_panic_on_apic_error = 0; 196 197 int apic_verbose = 0; 198 199 /* minimum number of timer ticks to program to */ 200 int apic_min_timer_ticks = 1; 201 /* 202 * Local static data 203 */ 204 static struct psm_ops apic_ops = { 205 apic_probe, 206 207 apic_init, 208 apic_picinit, 209 apic_intr_enter, 210 apic_intr_exit, 211 apic_setspl, 212 apic_addspl, 213 apic_delspl, 214 apic_disable_intr, 215 apic_enable_intr, 216 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 217 (void (*)(int))NULL, /* psm_set_softintr */ 218 219 apic_set_idlecpu, 220 apic_unset_idlecpu, 221 222 apic_clkinit, 223 apic_getclkirq, 224 (void (*)(void))NULL, /* psm_hrtimeinit */ 225 apic_gethrtime, 226 227 apic_get_next_processorid, 228 apic_cpu_start, 229 apic_post_cpu_start, 230 apic_shutdown, 231 apic_get_ipivect, 232 apic_send_ipi, 233 234 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 235 (void (*)(int, char *))NULL, /* psm_notify_error */ 236 (void (*)(int))NULL, /* psm_notify_func */ 237 apic_timer_reprogram, 238 apic_timer_enable, 239 apic_timer_disable, 240 apic_post_cyclic_setup, 241 apic_preshutdown, 242 apic_intr_ops, /* Advanced DDI Interrupt framework */ 243 apic_state, /* save, restore apic state for S3 */ 244 }; 245 246 247 static struct psm_info apic_psm_info = { 248 PSM_INFO_VER01_6, /* version */ 249 PSM_OWN_EXCLUSIVE, /* ownership */ 250 (struct psm_ops *)&apic_ops, /* operation */ 251 APIC_PCPLUSMP_NAME, /* machine name */ 252 "pcplusmp v1.4 compatible %I%", 253 }; 254 255 static void *apic_hdlp; 256 257 #ifdef DEBUG 258 int apic_debug = 0; 259 int apic_restrict_vector = 0; 260 261 int apic_debug_msgbuf[APIC_DEBUG_MSGBUFSIZE]; 262 int apic_debug_msgbufindex = 0; 263 264 #endif /* DEBUG */ 265 266 apic_cpus_info_t *apic_cpus; 267 268 cpuset_t apic_cpumask; 269 uint_t apic_picinit_called; 270 271 /* Flag to indicate that we need to shut down all processors */ 272 static uint_t apic_shutdown_processors; 273 274 uint_t apic_nsec_per_intr = 0; 275 276 /* 277 * apic_let_idle_redistribute can have the following values: 278 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute. 279 * apic_redistribute_lock prevents multiple idle cpus from redistributing 280 */ 281 int apic_num_idle_redistributions = 0; 282 static int apic_let_idle_redistribute = 0; 283 static uint_t apic_nticks = 0; 284 static uint_t apic_skipped_redistribute = 0; 285 286 /* to gather intr data and redistribute */ 287 static void apic_redistribute_compute(void); 288 289 static uint_t last_count_read = 0; 290 static lock_t apic_gethrtime_lock; 291 volatile int apic_hrtime_stamp = 0; 292 volatile hrtime_t apic_nsec_since_boot = 0; 293 static uint_t apic_hertz_count; 294 295 uint64_t apic_ticks_per_SFnsecs; /* # of ticks in SF nsecs */ 296 297 static hrtime_t apic_nsec_max; 298 299 static hrtime_t apic_last_hrtime = 0; 300 int apic_hrtime_error = 0; 301 int apic_remote_hrterr = 0; 302 int apic_num_nmis = 0; 303 int apic_apic_error = 0; 304 int apic_num_apic_errors = 0; 305 int apic_num_cksum_errors = 0; 306 307 int apic_error = 0; 308 static int apic_cmos_ssb_set = 0; 309 310 /* use to make sure only one cpu handles the nmi */ 311 static lock_t apic_nmi_lock; 312 /* use to make sure only one cpu handles the error interrupt */ 313 static lock_t apic_error_lock; 314 315 static struct { 316 uchar_t cntl; 317 uchar_t data; 318 } aspen_bmc[] = { 319 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 320 { CC_SMS_WR_NEXT, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 321 { CC_SMS_WR_NEXT, 0x84 }, /* DataByte 1: SMS/OS no log */ 322 { CC_SMS_WR_NEXT, 0x2 }, /* DataByte 2: Power Down */ 323 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 3: no pre-timeout */ 324 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 4: timer expir. */ 325 { CC_SMS_WR_NEXT, 0xa }, /* DataByte 5: init countdown */ 326 { CC_SMS_WR_END, 0x0 }, /* DataByte 6: init countdown */ 327 328 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 329 { CC_SMS_WR_END, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 330 }; 331 332 static struct { 333 int port; 334 uchar_t data; 335 } sitka_bmc[] = { 336 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 337 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 338 { SMS_DATA_REGISTER, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 339 { SMS_DATA_REGISTER, 0x84 }, /* DataByte 1: SMS/OS no log */ 340 { SMS_DATA_REGISTER, 0x2 }, /* DataByte 2: Power Down */ 341 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 3: no pre-timeout */ 342 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 4: timer expir. */ 343 { SMS_DATA_REGISTER, 0xa }, /* DataByte 5: init countdown */ 344 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 345 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 6: init countdown */ 346 347 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 348 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 349 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 350 { SMS_DATA_REGISTER, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 351 }; 352 353 /* Patchable global variables. */ 354 int apic_kmdb_on_nmi = 0; /* 0 - no, 1 - yes enter kmdb */ 355 uint32_t apic_divide_reg_init = 0; /* 0 - divide by 2 */ 356 357 /* 358 * This is the loadable module wrapper 359 */ 360 361 int 362 _init(void) 363 { 364 if (apic_coarse_hrtime) 365 apic_ops.psm_gethrtime = &apic_gettime; 366 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 367 } 368 369 int 370 _fini(void) 371 { 372 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 373 } 374 375 int 376 _info(struct modinfo *modinfop) 377 { 378 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 379 } 380 381 382 static int 383 apic_probe() 384 { 385 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 386 } 387 388 void 389 apic_init() 390 { 391 int i; 392 int j = 1; 393 394 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 395 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 396 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 397 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 398 /* get to highest vector at the same ipl */ 399 continue; 400 for (; j <= apic_vectortoipl[i]; j++) { 401 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 402 APIC_BASE_VECT; 403 } 404 } 405 for (; j < MAXIPL + 1; j++) 406 /* fill up any empty ipltopri slots */ 407 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 408 apic_init_common(); 409 #if defined(__amd64) 410 /* 411 * Make cpu-specific interrupt info point to cr8pri vector 412 */ 413 for (i = 0; i <= MAXIPL; i++) 414 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT; 415 CPU->cpu_pri_data = apic_cr8pri; 416 #endif /* __amd64 */ 417 } 418 419 /* 420 * handler for APIC Error interrupt. Just print a warning and continue 421 */ 422 static int 423 apic_error_intr() 424 { 425 uint_t error0, error1, error; 426 uint_t i; 427 428 /* 429 * We need to write before read as per 7.4.17 of system prog manual. 430 * We do both and or the results to be safe 431 */ 432 error0 = apicadr[APIC_ERROR_STATUS]; 433 apicadr[APIC_ERROR_STATUS] = 0; 434 error1 = apicadr[APIC_ERROR_STATUS]; 435 error = error0 | error1; 436 437 /* 438 * Clear the APIC error status (do this on all cpus that enter here) 439 * (two writes are required due to the semantics of accessing the 440 * error status register.) 441 */ 442 apicadr[APIC_ERROR_STATUS] = 0; 443 apicadr[APIC_ERROR_STATUS] = 0; 444 445 /* 446 * Prevent more than 1 CPU from handling error interrupt causing 447 * double printing (interleave of characters from multiple 448 * CPU's when using prom_printf) 449 */ 450 if (lock_try(&apic_error_lock) == 0) 451 return (error ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 452 if (error) { 453 #if DEBUG 454 if (apic_debug) 455 debug_enter("pcplusmp: APIC Error interrupt received"); 456 #endif /* DEBUG */ 457 if (apic_panic_on_apic_error) 458 cmn_err(CE_PANIC, 459 "APIC Error interrupt on CPU %d. Status = %x\n", 460 psm_get_cpu_id(), error); 461 else { 462 if ((error & ~APIC_CS_ERRORS) == 0) { 463 /* cksum error only */ 464 apic_error |= APIC_ERR_APIC_ERROR; 465 apic_apic_error |= error; 466 apic_num_apic_errors++; 467 apic_num_cksum_errors++; 468 } else { 469 /* 470 * prom_printf is the best shot we have of 471 * something which is problem free from 472 * high level/NMI type of interrupts 473 */ 474 prom_printf("APIC Error interrupt on CPU %d. " 475 "Status 0 = %x, Status 1 = %x\n", 476 psm_get_cpu_id(), error0, error1); 477 apic_error |= APIC_ERR_APIC_ERROR; 478 apic_apic_error |= error; 479 apic_num_apic_errors++; 480 for (i = 0; i < apic_error_display_delay; i++) { 481 tenmicrosec(); 482 } 483 /* 484 * provide more delay next time limited to 485 * roughly 1 clock tick time 486 */ 487 if (apic_error_display_delay < 500) 488 apic_error_display_delay *= 2; 489 } 490 } 491 lock_clear(&apic_error_lock); 492 return (DDI_INTR_CLAIMED); 493 } else { 494 lock_clear(&apic_error_lock); 495 return (DDI_INTR_UNCLAIMED); 496 } 497 /* NOTREACHED */ 498 } 499 500 /* 501 * Turn off the mask bit in the performance counter Local Vector Table entry. 502 */ 503 static void 504 apic_cpcovf_mask_clear(void) 505 { 506 apicadr[APIC_PCINT_VECT] &= ~APIC_LVT_MASK; 507 } 508 509 static void 510 apic_init_intr() 511 { 512 processorid_t cpun = psm_get_cpu_id(); 513 514 #if defined(__amd64) 515 setcr8((ulong_t)(APIC_MASK_ALL >> APIC_IPL_SHIFT)); 516 #else 517 apicadr[APIC_TASK_REG] = APIC_MASK_ALL; 518 #endif 519 520 if (apic_flat_model) 521 apicadr[APIC_FORMAT_REG] = APIC_FLAT_MODEL; 522 else 523 apicadr[APIC_FORMAT_REG] = APIC_CLUSTER_MODEL; 524 apicadr[APIC_DEST_REG] = AV_HIGH_ORDER >> cpun; 525 526 /* need to enable APIC before unmasking NMI */ 527 apicadr[APIC_SPUR_INT_REG] = AV_UNIT_ENABLE | APIC_SPUR_INTR; 528 529 apicadr[APIC_LOCAL_TIMER] = AV_MASK; 530 apicadr[APIC_INT_VECT0] = AV_MASK; /* local intr reg 0 */ 531 apicadr[APIC_INT_VECT1] = AV_NMI; /* enable NMI */ 532 533 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) 534 return; 535 536 /* Enable performance counter overflow interrupt */ 537 538 if ((x86_feature & X86_MSR) != X86_MSR) 539 apic_enable_cpcovf_intr = 0; 540 if (apic_enable_cpcovf_intr) { 541 if (apic_cpcovf_vect == 0) { 542 int ipl = APIC_PCINT_IPL; 543 int irq = apic_get_ipivect(ipl, -1); 544 545 ASSERT(irq != -1); 546 apic_cpcovf_vect = apic_irq_table[irq]->airq_vector; 547 ASSERT(apic_cpcovf_vect); 548 (void) add_avintr(NULL, ipl, 549 (avfunc)kcpc_hw_overflow_intr, 550 "apic pcint", irq, NULL, NULL, NULL, NULL); 551 kcpc_hw_overflow_intr_installed = 1; 552 kcpc_hw_enable_cpc_intr = apic_cpcovf_mask_clear; 553 } 554 apicadr[APIC_PCINT_VECT] = apic_cpcovf_vect; 555 } 556 557 /* Enable error interrupt */ 558 559 if (apic_enable_error_intr) { 560 if (apic_errvect == 0) { 561 int ipl = 0xf; /* get highest priority intr */ 562 int irq = apic_get_ipivect(ipl, -1); 563 564 ASSERT(irq != -1); 565 apic_errvect = apic_irq_table[irq]->airq_vector; 566 ASSERT(apic_errvect); 567 /* 568 * Not PSMI compliant, but we are going to merge 569 * with ON anyway 570 */ 571 (void) add_avintr((void *)NULL, ipl, 572 (avfunc)apic_error_intr, "apic error intr", 573 irq, NULL, NULL, NULL, NULL); 574 } 575 apicadr[APIC_ERR_VECT] = apic_errvect; 576 apicadr[APIC_ERROR_STATUS] = 0; 577 apicadr[APIC_ERROR_STATUS] = 0; 578 } 579 } 580 581 static void 582 apic_disable_local_apic() 583 { 584 apicadr[APIC_TASK_REG] = APIC_MASK_ALL; 585 apicadr[APIC_LOCAL_TIMER] = AV_MASK; 586 apicadr[APIC_INT_VECT0] = AV_MASK; /* local intr reg 0 */ 587 apicadr[APIC_INT_VECT1] = AV_MASK; /* disable NMI */ 588 apicadr[APIC_ERR_VECT] = AV_MASK; /* and error interrupt */ 589 apicadr[APIC_PCINT_VECT] = AV_MASK; /* and perf counter intr */ 590 apicadr[APIC_SPUR_INT_REG] = APIC_SPUR_INTR; 591 } 592 593 static void 594 apic_picinit(void) 595 { 596 int i, j; 597 uint_t isr; 598 599 /* 600 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 601 * bit on without clearing it with EOI. Since softint 602 * uses vector 0x20 to interrupt itself, so softint will 603 * not work on this machine. In order to fix this problem 604 * a check is made to verify all the isr bits are clear. 605 * If not, EOIs are issued to clear the bits. 606 */ 607 for (i = 7; i >= 1; i--) { 608 if ((isr = apicadr[APIC_ISR_REG + (i * 4)]) != 0) 609 for (j = 0; ((j < 32) && (isr != 0)); j++) 610 if (isr & (1 << j)) { 611 apicadr[APIC_EOI_REG] = 0; 612 isr &= ~(1 << j); 613 apic_error |= APIC_ERR_BOOT_EOI; 614 } 615 } 616 617 /* set a flag so we know we have run apic_picinit() */ 618 apic_picinit_called = 1; 619 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 620 LOCK_INIT_CLEAR(&apic_ioapic_lock); 621 LOCK_INIT_CLEAR(&apic_error_lock); 622 623 picsetup(); /* initialise the 8259 */ 624 625 /* add nmi handler - least priority nmi handler */ 626 LOCK_INIT_CLEAR(&apic_nmi_lock); 627 628 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 629 "pcplusmp NMI handler", (caddr_t)NULL)) 630 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 631 632 apic_init_intr(); 633 634 /* enable apic mode if imcr present */ 635 if (apic_imcrp) { 636 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 637 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 638 } 639 640 ioapic_init_intr(IOAPIC_MASK); 641 } 642 643 644 /*ARGSUSED1*/ 645 static int 646 apic_cpu_start(processorid_t cpun, caddr_t arg) 647 { 648 int loop_count; 649 uint32_t vector; 650 uint_t cpu_id; 651 ulong_t iflag; 652 653 cpu_id = apic_cpus[cpun].aci_local_id; 654 655 apic_cmos_ssb_set = 1; 656 657 /* 658 * Interrupts on BSP cpu will be disabled during these startup 659 * steps in order to avoid unwanted side effects from 660 * executing interrupt handlers on a problematic BIOS. 661 */ 662 663 iflag = intr_clear(); 664 outb(CMOS_ADDR, SSB); 665 outb(CMOS_DATA, BIOS_SHUTDOWN); 666 667 while (get_apic_cmd1() & AV_PENDING) 668 apic_ret(); 669 670 /* for integrated - make sure there is one INIT IPI in buffer */ 671 /* for external - it will wake up the cpu */ 672 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 673 apicadr[APIC_INT_CMD1] = AV_ASSERT | AV_RESET; 674 675 /* If only 1 CPU is installed, PENDING bit will not go low */ 676 for (loop_count = 0x1000; loop_count; loop_count--) 677 if (get_apic_cmd1() & AV_PENDING) 678 apic_ret(); 679 else 680 break; 681 682 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 683 apicadr[APIC_INT_CMD1] = AV_DEASSERT | AV_RESET; 684 685 drv_usecwait(20000); /* 20 milli sec */ 686 687 if (apic_cpus[cpun].aci_local_ver >= APIC_INTEGRATED_VERS) { 688 /* integrated apic */ 689 690 vector = (rm_platter_pa >> MMU_PAGESHIFT) & 691 (APIC_VECTOR_MASK | APIC_IPL_MASK); 692 693 /* to offset the INIT IPI queue up in the buffer */ 694 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 695 apicadr[APIC_INT_CMD1] = vector | AV_STARTUP; 696 697 drv_usecwait(200); /* 20 micro sec */ 698 699 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 700 apicadr[APIC_INT_CMD1] = vector | AV_STARTUP; 701 702 drv_usecwait(200); /* 20 micro sec */ 703 } 704 intr_restore(iflag); 705 return (0); 706 } 707 708 709 #ifdef DEBUG 710 int apic_break_on_cpu = 9; 711 int apic_stretch_interrupts = 0; 712 int apic_stretch_ISR = 1 << 3; /* IPL of 3 matches nothing now */ 713 714 void 715 apic_break() 716 { 717 } 718 #endif /* DEBUG */ 719 720 /* 721 * platform_intr_enter 722 * 723 * Called at the beginning of the interrupt service routine to 724 * mask all level equal to and below the interrupt priority 725 * of the interrupting vector. An EOI should be given to 726 * the interrupt controller to enable other HW interrupts. 727 * 728 * Return -1 for spurious interrupts 729 * 730 */ 731 /*ARGSUSED*/ 732 static int 733 apic_intr_enter(int ipl, int *vectorp) 734 { 735 uchar_t vector; 736 int nipl; 737 int irq; 738 ulong_t iflag; 739 apic_cpus_info_t *cpu_infop; 740 741 /* 742 * The real vector delivered is (*vectorp + 0x20), but our caller 743 * subtracts 0x20 from the vector before passing it to us. 744 * (That's why APIC_BASE_VECT is 0x20.) 745 */ 746 vector = (uchar_t)*vectorp; 747 748 /* if interrupted by the clock, increment apic_nsec_since_boot */ 749 if (vector == apic_clkvect) { 750 if (!apic_oneshot) { 751 /* NOTE: this is not MT aware */ 752 apic_hrtime_stamp++; 753 apic_nsec_since_boot += apic_nsec_per_intr; 754 apic_hrtime_stamp++; 755 last_count_read = apic_hertz_count; 756 apic_redistribute_compute(); 757 } 758 759 /* We will avoid all the book keeping overhead for clock */ 760 nipl = apic_ipls[vector]; 761 762 #if defined(__amd64) 763 setcr8((ulong_t)apic_cr8pri[nipl]); 764 #else 765 apicadr[APIC_TASK_REG] = apic_ipltopri[nipl]; 766 #endif 767 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 768 apicadr[APIC_EOI_REG] = 0; 769 return (nipl); 770 } 771 772 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 773 774 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 775 cpu_infop->aci_spur_cnt++; 776 return (APIC_INT_SPURIOUS); 777 } 778 779 /* Check if the vector we got is really what we need */ 780 if (apic_revector_pending) { 781 /* 782 * Disable interrupts for the duration of 783 * the vector translation to prevent a self-race for 784 * the apic_revector_lock. This cannot be done 785 * in apic_xlate_vector because it is recursive and 786 * we want the vector translation to be atomic with 787 * respect to other (higher-priority) interrupts. 788 */ 789 iflag = intr_clear(); 790 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 791 APIC_BASE_VECT; 792 intr_restore(iflag); 793 } 794 795 nipl = apic_ipls[vector]; 796 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 797 798 #if defined(__amd64) 799 setcr8((ulong_t)apic_cr8pri[nipl]); 800 #else 801 apicadr[APIC_TASK_REG] = apic_ipltopri[nipl]; 802 #endif 803 804 cpu_infop->aci_current[nipl] = (uchar_t)irq; 805 cpu_infop->aci_curipl = (uchar_t)nipl; 806 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 807 808 /* 809 * apic_level_intr could have been assimilated into the irq struct. 810 * but, having it as a character array is more efficient in terms of 811 * cache usage. So, we leave it as is. 812 */ 813 if (!apic_level_intr[irq]) 814 apicadr[APIC_EOI_REG] = 0; 815 816 #ifdef DEBUG 817 APIC_DEBUG_BUF_PUT(vector); 818 APIC_DEBUG_BUF_PUT(irq); 819 APIC_DEBUG_BUF_PUT(nipl); 820 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 821 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 822 drv_usecwait(apic_stretch_interrupts); 823 824 if (apic_break_on_cpu == psm_get_cpu_id()) 825 apic_break(); 826 #endif /* DEBUG */ 827 return (nipl); 828 } 829 830 void 831 apic_intr_exit(int prev_ipl, int irq) 832 { 833 apic_cpus_info_t *cpu_infop; 834 835 #if defined(__amd64) 836 setcr8((ulong_t)apic_cr8pri[prev_ipl]); 837 #else 838 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl]; 839 #endif 840 841 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 842 if (apic_level_intr[irq]) 843 apicadr[APIC_EOI_REG] = 0; 844 845 cpu_infop->aci_curipl = (uchar_t)prev_ipl; 846 /* ISR above current pri could not be in progress */ 847 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; 848 } 849 850 intr_exit_fn_t 851 psm_intr_exit_fn(void) 852 { 853 return (apic_intr_exit); 854 } 855 856 /* 857 * Mask all interrupts below or equal to the given IPL 858 */ 859 static void 860 apic_setspl(int ipl) 861 { 862 863 #if defined(__amd64) 864 setcr8((ulong_t)apic_cr8pri[ipl]); 865 #else 866 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl]; 867 #endif 868 869 /* interrupts at ipl above this cannot be in progress */ 870 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 871 /* 872 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 873 * have enough time to come in before the priority is raised again 874 * during the idle() loop. 875 */ 876 if (apic_setspl_delay) 877 (void) get_apic_pri(); 878 } 879 880 /* 881 * generates an interprocessor interrupt to another CPU 882 */ 883 static void 884 apic_send_ipi(int cpun, int ipl) 885 { 886 int vector; 887 ulong_t flag; 888 889 vector = apic_resv_vector[ipl]; 890 891 flag = intr_clear(); 892 893 while (get_apic_cmd1() & AV_PENDING) 894 apic_ret(); 895 896 apicadr[APIC_INT_CMD2] = 897 apic_cpus[cpun].aci_local_id << APIC_ICR_ID_BIT_OFFSET; 898 apicadr[APIC_INT_CMD1] = vector; 899 900 intr_restore(flag); 901 } 902 903 904 /*ARGSUSED*/ 905 static void 906 apic_set_idlecpu(processorid_t cpun) 907 { 908 } 909 910 /*ARGSUSED*/ 911 static void 912 apic_unset_idlecpu(processorid_t cpun) 913 { 914 } 915 916 917 static void 918 apic_ret() 919 { 920 } 921 922 static int 923 get_apic_cmd1() 924 { 925 return (apicadr[APIC_INT_CMD1]); 926 } 927 928 static int 929 get_apic_pri() 930 { 931 #if defined(__amd64) 932 return ((int)getcr8()); 933 #else 934 return (apicadr[APIC_TASK_REG]); 935 #endif 936 } 937 938 /* 939 * If apic_coarse_time == 1, then apic_gettime() is used instead of 940 * apic_gethrtime(). This is used for performance instead of accuracy. 941 */ 942 943 static hrtime_t 944 apic_gettime() 945 { 946 int old_hrtime_stamp; 947 hrtime_t temp; 948 949 /* 950 * In one-shot mode, we do not keep time, so if anyone 951 * calls psm_gettime() directly, we vector over to 952 * gethrtime(). 953 * one-shot mode MUST NOT be enabled if this psm is the source of 954 * hrtime. 955 */ 956 957 if (apic_oneshot) 958 return (gethrtime()); 959 960 961 gettime_again: 962 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 963 apic_ret(); 964 965 temp = apic_nsec_since_boot; 966 967 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 968 goto gettime_again; 969 } 970 return (temp); 971 } 972 973 /* 974 * Here we return the number of nanoseconds since booting. Note every 975 * clock interrupt increments apic_nsec_since_boot by the appropriate 976 * amount. 977 */ 978 static hrtime_t 979 apic_gethrtime() 980 { 981 int curr_timeval, countval, elapsed_ticks; 982 int old_hrtime_stamp, status; 983 hrtime_t temp; 984 uchar_t cpun; 985 ulong_t oflags; 986 987 /* 988 * In one-shot mode, we do not keep time, so if anyone 989 * calls psm_gethrtime() directly, we vector over to 990 * gethrtime(). 991 * one-shot mode MUST NOT be enabled if this psm is the source of 992 * hrtime. 993 */ 994 995 if (apic_oneshot) 996 return (gethrtime()); 997 998 oflags = intr_clear(); /* prevent migration */ 999 1000 cpun = (uchar_t)((uint_t)apicadr[APIC_LID_REG] >> APIC_ID_BIT_OFFSET); 1001 1002 lock_set(&apic_gethrtime_lock); 1003 1004 gethrtime_again: 1005 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 1006 apic_ret(); 1007 1008 /* 1009 * Check to see which CPU we are on. Note the time is kept on 1010 * the local APIC of CPU 0. If on CPU 0, simply read the current 1011 * counter. If on another CPU, issue a remote read command to CPU 0. 1012 */ 1013 if (cpun == apic_cpus[0].aci_local_id) { 1014 countval = apicadr[APIC_CURR_COUNT]; 1015 } else { 1016 while (get_apic_cmd1() & AV_PENDING) 1017 apic_ret(); 1018 1019 apicadr[APIC_INT_CMD2] = 1020 apic_cpus[0].aci_local_id << APIC_ICR_ID_BIT_OFFSET; 1021 apicadr[APIC_INT_CMD1] = APIC_CURR_ADD|AV_REMOTE; 1022 1023 while ((status = get_apic_cmd1()) & AV_READ_PENDING) 1024 apic_ret(); 1025 1026 if (status & AV_REMOTE_STATUS) /* 1 = valid */ 1027 countval = apicadr[APIC_REMOTE_READ]; 1028 else { /* 0 = invalid */ 1029 apic_remote_hrterr++; 1030 /* 1031 * return last hrtime right now, will need more 1032 * testing if change to retry 1033 */ 1034 temp = apic_last_hrtime; 1035 1036 lock_clear(&apic_gethrtime_lock); 1037 1038 intr_restore(oflags); 1039 1040 return (temp); 1041 } 1042 } 1043 if (countval > last_count_read) 1044 countval = 0; 1045 else 1046 last_count_read = countval; 1047 1048 elapsed_ticks = apic_hertz_count - countval; 1049 1050 curr_timeval = APIC_TICKS_TO_NSECS(elapsed_ticks); 1051 temp = apic_nsec_since_boot + curr_timeval; 1052 1053 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 1054 /* we might have clobbered last_count_read. Restore it */ 1055 last_count_read = apic_hertz_count; 1056 goto gethrtime_again; 1057 } 1058 1059 if (temp < apic_last_hrtime) { 1060 /* return last hrtime if error occurs */ 1061 apic_hrtime_error++; 1062 temp = apic_last_hrtime; 1063 } 1064 else 1065 apic_last_hrtime = temp; 1066 1067 lock_clear(&apic_gethrtime_lock); 1068 intr_restore(oflags); 1069 1070 return (temp); 1071 } 1072 1073 /* apic NMI handler */ 1074 /*ARGSUSED*/ 1075 static void 1076 apic_nmi_intr(caddr_t arg, struct regs *rp) 1077 { 1078 if (apic_shutdown_processors) { 1079 apic_disable_local_apic(); 1080 return; 1081 } 1082 1083 apic_error |= APIC_ERR_NMI; 1084 1085 if (!lock_try(&apic_nmi_lock)) 1086 return; 1087 apic_num_nmis++; 1088 1089 if (apic_kmdb_on_nmi && psm_debugger()) { 1090 debug_enter("NMI received: entering kmdb\n"); 1091 } else if (apic_panic_on_nmi) { 1092 /* Keep panic from entering kmdb. */ 1093 nopanicdebug = 1; 1094 panic("NMI received\n"); 1095 } else { 1096 /* 1097 * prom_printf is the best shot we have of something which is 1098 * problem free from high level/NMI type of interrupts 1099 */ 1100 prom_printf("NMI received\n"); 1101 } 1102 1103 lock_clear(&apic_nmi_lock); 1104 } 1105 1106 /*ARGSUSED*/ 1107 static int 1108 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 1109 { 1110 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 1111 } 1112 1113 static int 1114 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 1115 { 1116 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 1117 } 1118 1119 static int 1120 apic_post_cpu_start() 1121 { 1122 int cpun; 1123 1124 splx(ipltospl(LOCK_LEVEL)); 1125 apic_init_intr(); 1126 1127 /* 1128 * since some systems don't enable the internal cache on the non-boot 1129 * cpus, so we have to enable them here 1130 */ 1131 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 1132 1133 while (get_apic_cmd1() & AV_PENDING) 1134 apic_ret(); 1135 1136 cpun = psm_get_cpu_id(); 1137 apic_cpus[cpun].aci_status = APIC_CPU_ONLINE; 1138 1139 apicadr[APIC_DIVIDE_REG] = apic_divide_reg_init; 1140 return (PSM_SUCCESS); 1141 } 1142 1143 processorid_t 1144 apic_get_next_processorid(processorid_t cpu_id) 1145 { 1146 1147 int i; 1148 1149 if (cpu_id == -1) 1150 return ((processorid_t)0); 1151 1152 for (i = cpu_id + 1; i < NCPU; i++) { 1153 if (CPU_IN_SET(apic_cpumask, i)) 1154 return (i); 1155 } 1156 1157 return ((processorid_t)-1); 1158 } 1159 1160 1161 /* 1162 * type == -1 indicates it is an internal request. Do not change 1163 * resv_vector for these requests 1164 */ 1165 static int 1166 apic_get_ipivect(int ipl, int type) 1167 { 1168 uchar_t vector; 1169 int irq; 1170 1171 if (irq = apic_allocate_irq(APIC_VECTOR(ipl))) { 1172 if (vector = apic_allocate_vector(ipl, irq, 1)) { 1173 apic_irq_table[irq]->airq_mps_intr_index = 1174 RESERVE_INDEX; 1175 apic_irq_table[irq]->airq_vector = vector; 1176 if (type != -1) { 1177 apic_resv_vector[ipl] = vector; 1178 } 1179 return (irq); 1180 } 1181 } 1182 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 1183 return (-1); /* shouldn't happen */ 1184 } 1185 1186 static int 1187 apic_getclkirq(int ipl) 1188 { 1189 int irq; 1190 1191 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 1192 return (-1); 1193 /* 1194 * Note the vector in apic_clkvect for per clock handling. 1195 */ 1196 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 1197 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 1198 apic_clkvect)); 1199 return (irq); 1200 } 1201 1202 1203 /* 1204 * Return the number of APIC clock ticks elapsed for 8245 to decrement 1205 * (APIC_TIME_COUNT + pit_ticks_adj) ticks. 1206 */ 1207 static uint_t 1208 apic_calibrate(volatile uint32_t *addr, uint16_t *pit_ticks_adj) 1209 { 1210 uint8_t pit_tick_lo; 1211 uint16_t pit_tick, target_pit_tick; 1212 uint32_t start_apic_tick, end_apic_tick; 1213 ulong_t iflag; 1214 1215 addr += APIC_CURR_COUNT; 1216 1217 iflag = intr_clear(); 1218 1219 do { 1220 pit_tick_lo = inb(PITCTR0_PORT); 1221 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1222 } while (pit_tick < APIC_TIME_MIN || 1223 pit_tick_lo <= APIC_LB_MIN || pit_tick_lo >= APIC_LB_MAX); 1224 1225 /* 1226 * Wait for the 8254 to decrement by 5 ticks to ensure 1227 * we didn't start in the middle of a tick. 1228 * Compare with 0x10 for the wrap around case. 1229 */ 1230 target_pit_tick = pit_tick - 5; 1231 do { 1232 pit_tick_lo = inb(PITCTR0_PORT); 1233 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1234 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 1235 1236 start_apic_tick = *addr; 1237 1238 /* 1239 * Wait for the 8254 to decrement by 1240 * (APIC_TIME_COUNT + pit_ticks_adj) ticks 1241 */ 1242 target_pit_tick = pit_tick - APIC_TIME_COUNT; 1243 do { 1244 pit_tick_lo = inb(PITCTR0_PORT); 1245 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1246 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 1247 1248 end_apic_tick = *addr; 1249 1250 *pit_ticks_adj = target_pit_tick - pit_tick; 1251 1252 intr_restore(iflag); 1253 1254 return (start_apic_tick - end_apic_tick); 1255 } 1256 1257 /* 1258 * Initialise the APIC timer on the local APIC of CPU 0 to the desired 1259 * frequency. Note at this stage in the boot sequence, the boot processor 1260 * is the only active processor. 1261 * hertz value of 0 indicates a one-shot mode request. In this case 1262 * the function returns the resolution (in nanoseconds) for the hardware 1263 * timer interrupt. If one-shot mode capability is not available, 1264 * the return value will be 0. apic_enable_oneshot is a global switch 1265 * for disabling the functionality. 1266 * A non-zero positive value for hertz indicates a periodic mode request. 1267 * In this case the hardware will be programmed to generate clock interrupts 1268 * at hertz frequency and returns the resolution of interrupts in 1269 * nanosecond. 1270 */ 1271 1272 static int 1273 apic_clkinit(int hertz) 1274 { 1275 uint_t apic_ticks = 0; 1276 uint_t pit_ticks; 1277 int ret; 1278 uint16_t pit_ticks_adj; 1279 static int firsttime = 1; 1280 1281 if (firsttime) { 1282 /* first time calibrate on CPU0 only */ 1283 1284 apicadr[APIC_DIVIDE_REG] = apic_divide_reg_init; 1285 apicadr[APIC_INIT_COUNT] = APIC_MAXVAL; 1286 apic_ticks = apic_calibrate(apicadr, &pit_ticks_adj); 1287 1288 /* total number of PIT ticks corresponding to apic_ticks */ 1289 pit_ticks = APIC_TIME_COUNT + pit_ticks_adj; 1290 1291 /* 1292 * Determine the number of nanoseconds per APIC clock tick 1293 * and then determine how many APIC ticks to interrupt at the 1294 * desired frequency 1295 * apic_ticks / (pitticks / PIT_HZ) = apic_ticks_per_s 1296 * (apic_ticks * PIT_HZ) / pitticks = apic_ticks_per_s 1297 * apic_ticks_per_ns = (apic_ticks * PIT_HZ) / (pitticks * 10^9) 1298 * pic_ticks_per_SFns = 1299 * (SF * apic_ticks * PIT_HZ) / (pitticks * 10^9) 1300 */ 1301 apic_ticks_per_SFnsecs = 1302 ((SF * apic_ticks * PIT_HZ) / 1303 ((uint64_t)pit_ticks * NANOSEC)); 1304 1305 /* the interval timer initial count is 32 bit max */ 1306 apic_nsec_max = APIC_TICKS_TO_NSECS(APIC_MAXVAL); 1307 firsttime = 0; 1308 } 1309 1310 if (hertz != 0) { 1311 /* periodic */ 1312 apic_nsec_per_intr = NANOSEC / hertz; 1313 apic_hertz_count = APIC_NSECS_TO_TICKS(apic_nsec_per_intr); 1314 } 1315 1316 apic_int_busy_mark = (apic_int_busy_mark * 1317 apic_sample_factor_redistribution) / 100; 1318 apic_int_free_mark = (apic_int_free_mark * 1319 apic_sample_factor_redistribution) / 100; 1320 apic_diff_for_redistribution = (apic_diff_for_redistribution * 1321 apic_sample_factor_redistribution) / 100; 1322 1323 if (hertz == 0) { 1324 /* requested one_shot */ 1325 if (!tsc_gethrtime_enable || !apic_oneshot_enable) 1326 return (0); 1327 apic_oneshot = 1; 1328 ret = (int)APIC_TICKS_TO_NSECS(1); 1329 } else { 1330 /* program the local APIC to interrupt at the given frequency */ 1331 apicadr[APIC_INIT_COUNT] = apic_hertz_count; 1332 apicadr[APIC_LOCAL_TIMER] = 1333 (apic_clkvect + APIC_BASE_VECT) | AV_TIME; 1334 apic_oneshot = 0; 1335 ret = NANOSEC / hertz; 1336 } 1337 1338 return (ret); 1339 1340 } 1341 1342 /* 1343 * apic_preshutdown: 1344 * Called early in shutdown whilst we can still access filesystems to do 1345 * things like loading modules which will be required to complete shutdown 1346 * after filesystems are all unmounted. 1347 */ 1348 static void 1349 apic_preshutdown(int cmd, int fcn) 1350 { 1351 APIC_VERBOSE_POWEROFF(("apic_preshutdown(%d,%d); m=%d a=%d\n", 1352 cmd, fcn, apic_poweroff_method, apic_enable_acpi)); 1353 1354 if ((cmd != A_SHUTDOWN) || (fcn != AD_POWEROFF)) { 1355 return; 1356 } 1357 } 1358 1359 static void 1360 apic_shutdown(int cmd, int fcn) 1361 { 1362 int restarts, attempts; 1363 int i; 1364 uchar_t byte; 1365 ulong_t iflag; 1366 1367 /* Send NMI to all CPUs except self to do per processor shutdown */ 1368 iflag = intr_clear(); 1369 while (get_apic_cmd1() & AV_PENDING) 1370 apic_ret(); 1371 apic_shutdown_processors = 1; 1372 apicadr[APIC_INT_CMD1] = AV_NMI | AV_LEVEL | AV_SH_ALL_EXCSELF; 1373 1374 /* restore cmos shutdown byte before reboot */ 1375 if (apic_cmos_ssb_set) { 1376 outb(CMOS_ADDR, SSB); 1377 outb(CMOS_DATA, 0); 1378 } 1379 1380 ioapic_disable_redirection(); 1381 1382 /* disable apic mode if imcr present */ 1383 if (apic_imcrp) { 1384 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 1385 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_PIC); 1386 } 1387 1388 apic_disable_local_apic(); 1389 1390 intr_restore(iflag); 1391 1392 /* remainder of function is for shutdown cases only */ 1393 if (cmd != A_SHUTDOWN) 1394 return; 1395 1396 /* 1397 * Switch system back into Legacy-Mode if using ACPI and 1398 * not powering-off. Some BIOSes need to remain in ACPI-mode 1399 * for power-off to succeed (Dell Dimension 4600) 1400 */ 1401 if (apic_enable_acpi && (fcn != AD_POWEROFF)) 1402 (void) AcpiDisable(); 1403 1404 /* remainder of function is for shutdown+poweroff case only */ 1405 if (fcn != AD_POWEROFF) 1406 return; 1407 1408 switch (apic_poweroff_method) { 1409 case APIC_POWEROFF_VIA_RTC: 1410 1411 /* select the extended NVRAM bank in the RTC */ 1412 outb(CMOS_ADDR, RTC_REGA); 1413 byte = inb(CMOS_DATA); 1414 outb(CMOS_DATA, (byte | EXT_BANK)); 1415 1416 outb(CMOS_ADDR, PFR_REG); 1417 1418 /* for Predator must toggle the PAB bit */ 1419 byte = inb(CMOS_DATA); 1420 1421 /* 1422 * clear power active bar, wakeup alarm and 1423 * kickstart 1424 */ 1425 byte &= ~(PAB_CBIT | WF_FLAG | KS_FLAG); 1426 outb(CMOS_DATA, byte); 1427 1428 /* delay before next write */ 1429 drv_usecwait(1000); 1430 1431 /* for S40 the following would suffice */ 1432 byte = inb(CMOS_DATA); 1433 1434 /* power active bar control bit */ 1435 byte |= PAB_CBIT; 1436 outb(CMOS_DATA, byte); 1437 1438 break; 1439 1440 case APIC_POWEROFF_VIA_ASPEN_BMC: 1441 restarts = 0; 1442 restart_aspen_bmc: 1443 if (++restarts == 3) 1444 break; 1445 attempts = 0; 1446 do { 1447 byte = inb(MISMIC_FLAG_REGISTER); 1448 byte &= MISMIC_BUSY_MASK; 1449 if (byte != 0) { 1450 drv_usecwait(1000); 1451 if (attempts >= 3) 1452 goto restart_aspen_bmc; 1453 ++attempts; 1454 } 1455 } while (byte != 0); 1456 outb(MISMIC_CNTL_REGISTER, CC_SMS_GET_STATUS); 1457 byte = inb(MISMIC_FLAG_REGISTER); 1458 byte |= 0x1; 1459 outb(MISMIC_FLAG_REGISTER, byte); 1460 i = 0; 1461 for (; i < (sizeof (aspen_bmc)/sizeof (aspen_bmc[0])); 1462 i++) { 1463 attempts = 0; 1464 do { 1465 byte = inb(MISMIC_FLAG_REGISTER); 1466 byte &= MISMIC_BUSY_MASK; 1467 if (byte != 0) { 1468 drv_usecwait(1000); 1469 if (attempts >= 3) 1470 goto restart_aspen_bmc; 1471 ++attempts; 1472 } 1473 } while (byte != 0); 1474 outb(MISMIC_CNTL_REGISTER, aspen_bmc[i].cntl); 1475 outb(MISMIC_DATA_REGISTER, aspen_bmc[i].data); 1476 byte = inb(MISMIC_FLAG_REGISTER); 1477 byte |= 0x1; 1478 outb(MISMIC_FLAG_REGISTER, byte); 1479 } 1480 break; 1481 1482 case APIC_POWEROFF_VIA_SITKA_BMC: 1483 restarts = 0; 1484 restart_sitka_bmc: 1485 if (++restarts == 3) 1486 break; 1487 attempts = 0; 1488 do { 1489 byte = inb(SMS_STATUS_REGISTER); 1490 byte &= SMS_STATE_MASK; 1491 if ((byte == SMS_READ_STATE) || 1492 (byte == SMS_WRITE_STATE)) { 1493 drv_usecwait(1000); 1494 if (attempts >= 3) 1495 goto restart_sitka_bmc; 1496 ++attempts; 1497 } 1498 } while ((byte == SMS_READ_STATE) || 1499 (byte == SMS_WRITE_STATE)); 1500 outb(SMS_COMMAND_REGISTER, SMS_GET_STATUS); 1501 i = 0; 1502 for (; i < (sizeof (sitka_bmc)/sizeof (sitka_bmc[0])); 1503 i++) { 1504 attempts = 0; 1505 do { 1506 byte = inb(SMS_STATUS_REGISTER); 1507 byte &= SMS_IBF_MASK; 1508 if (byte != 0) { 1509 drv_usecwait(1000); 1510 if (attempts >= 3) 1511 goto restart_sitka_bmc; 1512 ++attempts; 1513 } 1514 } while (byte != 0); 1515 outb(sitka_bmc[i].port, sitka_bmc[i].data); 1516 } 1517 break; 1518 1519 case APIC_POWEROFF_NONE: 1520 1521 /* If no APIC direct method, we will try using ACPI */ 1522 if (apic_enable_acpi) { 1523 if (acpi_poweroff() == 1) 1524 return; 1525 } else 1526 return; 1527 1528 break; 1529 } 1530 /* 1531 * Wait a limited time here for power to go off. 1532 * If the power does not go off, then there was a 1533 * problem and we should continue to the halt which 1534 * prints a message for the user to press a key to 1535 * reboot. 1536 */ 1537 drv_usecwait(7000000); /* wait seven seconds */ 1538 1539 } 1540 1541 /* 1542 * Try and disable all interrupts. We just assign interrupts to other 1543 * processors based on policy. If any were bound by user request, we 1544 * let them continue and return failure. We do not bother to check 1545 * for cache affinity while rebinding. 1546 */ 1547 1548 static int 1549 apic_disable_intr(processorid_t cpun) 1550 { 1551 int bind_cpu = 0, i, hardbound = 0; 1552 apic_irq_t *irq_ptr; 1553 ulong_t iflag; 1554 1555 iflag = intr_clear(); 1556 lock_set(&apic_ioapic_lock); 1557 1558 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1559 if (apic_reprogram_info[i].done == B_FALSE) { 1560 if (apic_reprogram_info[i].bindcpu == cpun) { 1561 /* 1562 * CPU is busy -- it's the target of 1563 * a pending reprogramming attempt 1564 */ 1565 lock_clear(&apic_ioapic_lock); 1566 intr_restore(iflag); 1567 return (PSM_FAILURE); 1568 } 1569 } 1570 } 1571 1572 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 1573 1574 apic_cpus[cpun].aci_curipl = 0; 1575 1576 i = apic_min_device_irq; 1577 for (; i <= apic_max_device_irq; i++) { 1578 /* 1579 * If there are bound interrupts on this cpu, then 1580 * rebind them to other processors. 1581 */ 1582 if ((irq_ptr = apic_irq_table[i]) != NULL) { 1583 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 1584 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 1585 ((irq_ptr->airq_temp_cpu & ~IRQ_USER_BOUND) < 1586 apic_nproc)); 1587 1588 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 1589 hardbound = 1; 1590 continue; 1591 } 1592 1593 if (irq_ptr->airq_temp_cpu == cpun) { 1594 do { 1595 bind_cpu = apic_next_bind_cpu++; 1596 if (bind_cpu >= apic_nproc) { 1597 apic_next_bind_cpu = 1; 1598 bind_cpu = 0; 1599 1600 } 1601 } while (apic_rebind_all(irq_ptr, bind_cpu)); 1602 } 1603 } 1604 } 1605 1606 lock_clear(&apic_ioapic_lock); 1607 intr_restore(iflag); 1608 1609 if (hardbound) { 1610 cmn_err(CE_WARN, "Could not disable interrupts on %d" 1611 "due to user bound interrupts", cpun); 1612 return (PSM_FAILURE); 1613 } 1614 else 1615 return (PSM_SUCCESS); 1616 } 1617 1618 static void 1619 apic_enable_intr(processorid_t cpun) 1620 { 1621 int i; 1622 apic_irq_t *irq_ptr; 1623 ulong_t iflag; 1624 1625 iflag = intr_clear(); 1626 lock_set(&apic_ioapic_lock); 1627 1628 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 1629 1630 i = apic_min_device_irq; 1631 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 1632 if ((irq_ptr = apic_irq_table[i]) != NULL) { 1633 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 1634 (void) apic_rebind_all(irq_ptr, 1635 irq_ptr->airq_cpu); 1636 } 1637 } 1638 } 1639 1640 lock_clear(&apic_ioapic_lock); 1641 intr_restore(iflag); 1642 } 1643 1644 1645 /* 1646 * This function will reprogram the timer. 1647 * 1648 * When in oneshot mode the argument is the absolute time in future to 1649 * generate the interrupt at. 1650 * 1651 * When in periodic mode, the argument is the interval at which the 1652 * interrupts should be generated. There is no need to support the periodic 1653 * mode timer change at this time. 1654 */ 1655 static void 1656 apic_timer_reprogram(hrtime_t time) 1657 { 1658 hrtime_t now; 1659 uint_t ticks; 1660 int64_t delta; 1661 1662 /* 1663 * We should be called from high PIL context (CBE_HIGH_PIL), 1664 * so kpreempt is disabled. 1665 */ 1666 1667 if (!apic_oneshot) { 1668 /* time is the interval for periodic mode */ 1669 ticks = APIC_NSECS_TO_TICKS(time); 1670 } else { 1671 /* one shot mode */ 1672 1673 now = gethrtime(); 1674 delta = time - now; 1675 1676 if (delta <= 0) { 1677 /* 1678 * requested to generate an interrupt in the past 1679 * generate an interrupt as soon as possible 1680 */ 1681 ticks = apic_min_timer_ticks; 1682 } else if (delta > apic_nsec_max) { 1683 /* 1684 * requested to generate an interrupt at a time 1685 * further than what we are capable of. Set to max 1686 * the hardware can handle 1687 */ 1688 1689 ticks = APIC_MAXVAL; 1690 #ifdef DEBUG 1691 cmn_err(CE_CONT, "apic_timer_reprogram, request at" 1692 " %lld too far in future, current time" 1693 " %lld \n", time, now); 1694 #endif 1695 } else 1696 ticks = APIC_NSECS_TO_TICKS(delta); 1697 } 1698 1699 if (ticks < apic_min_timer_ticks) 1700 ticks = apic_min_timer_ticks; 1701 1702 apicadr[APIC_INIT_COUNT] = ticks; 1703 1704 } 1705 1706 /* 1707 * This function will enable timer interrupts. 1708 */ 1709 static void 1710 apic_timer_enable(void) 1711 { 1712 /* 1713 * We should be Called from high PIL context (CBE_HIGH_PIL), 1714 * so kpreempt is disabled. 1715 */ 1716 1717 if (!apic_oneshot) 1718 apicadr[APIC_LOCAL_TIMER] = 1719 (apic_clkvect + APIC_BASE_VECT) | AV_TIME; 1720 else { 1721 /* one shot */ 1722 apicadr[APIC_LOCAL_TIMER] = (apic_clkvect + APIC_BASE_VECT); 1723 } 1724 } 1725 1726 /* 1727 * This function will disable timer interrupts. 1728 */ 1729 static void 1730 apic_timer_disable(void) 1731 { 1732 /* 1733 * We should be Called from high PIL context (CBE_HIGH_PIL), 1734 * so kpreempt is disabled. 1735 */ 1736 1737 apicadr[APIC_LOCAL_TIMER] = (apic_clkvect + APIC_BASE_VECT) | AV_MASK; 1738 } 1739 1740 1741 ddi_periodic_t apic_periodic_id; 1742 1743 /* 1744 * If this module needs a periodic handler for the interrupt distribution, it 1745 * can be added here. The argument to the periodic handler is not currently 1746 * used, but is reserved for future. 1747 */ 1748 static void 1749 apic_post_cyclic_setup(void *arg) 1750 { 1751 _NOTE(ARGUNUSED(arg)) 1752 /* cpu_lock is held */ 1753 /* set up a periodic handler for intr redistribution */ 1754 1755 /* 1756 * In peridoc mode intr redistribution processing is done in 1757 * apic_intr_enter during clk intr processing 1758 */ 1759 if (!apic_oneshot) 1760 return; 1761 /* 1762 * Register a periodical handler for the redistribution processing. 1763 * On X86, CY_LOW_LEVEL is mapped to the level 2 interrupt, so 1764 * DDI_IPL_2 should be passed to ddi_periodic_add() here. 1765 */ 1766 apic_periodic_id = ddi_periodic_add( 1767 (void (*)(void *))apic_redistribute_compute, NULL, 1768 apic_redistribute_sample_interval, DDI_IPL_2); 1769 } 1770 1771 static void 1772 apic_redistribute_compute(void) 1773 { 1774 int i, j, max_busy; 1775 1776 if (apic_enable_dynamic_migration) { 1777 if (++apic_nticks == apic_sample_factor_redistribution) { 1778 /* 1779 * Time to call apic_intr_redistribute(). 1780 * reset apic_nticks. This will cause max_busy 1781 * to be calculated below and if it is more than 1782 * apic_int_busy, we will do the whole thing 1783 */ 1784 apic_nticks = 0; 1785 } 1786 max_busy = 0; 1787 for (i = 0; i < apic_nproc; i++) { 1788 1789 /* 1790 * Check if curipl is non zero & if ISR is in 1791 * progress 1792 */ 1793 if (((j = apic_cpus[i].aci_curipl) != 0) && 1794 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 1795 1796 int irq; 1797 apic_cpus[i].aci_busy++; 1798 irq = apic_cpus[i].aci_current[j]; 1799 apic_irq_table[irq]->airq_busy++; 1800 } 1801 1802 if (!apic_nticks && 1803 (apic_cpus[i].aci_busy > max_busy)) 1804 max_busy = apic_cpus[i].aci_busy; 1805 } 1806 if (!apic_nticks) { 1807 if (max_busy > apic_int_busy_mark) { 1808 /* 1809 * We could make the following check be 1810 * skipped > 1 in which case, we get a 1811 * redistribution at half the busy mark (due to 1812 * double interval). Need to be able to collect 1813 * more empirical data to decide if that is a 1814 * good strategy. Punt for now. 1815 */ 1816 if (apic_skipped_redistribute) { 1817 apic_cleanup_busy(); 1818 apic_skipped_redistribute = 0; 1819 } else { 1820 apic_intr_redistribute(); 1821 } 1822 } else 1823 apic_skipped_redistribute++; 1824 } 1825 } 1826 } 1827 1828 1829 /* 1830 * The following functions are in the platform specific file so that they 1831 * can be different functions depending on whether we are running on 1832 * bare metal or a hypervisor. 1833 */ 1834 1835 /* 1836 * map an apic for memory-mapped access 1837 */ 1838 uint32_t * 1839 mapin_apic(uint32_t addr, size_t len, int flags) 1840 { 1841 /*LINTED: pointer cast may result in improper alignment */ 1842 return ((uint32_t *)psm_map_phys(addr, len, flags)); 1843 } 1844 1845 uint32_t * 1846 mapin_ioapic(uint32_t addr, size_t len, int flags) 1847 { 1848 return (mapin_apic(addr, len, flags)); 1849 } 1850 1851 /* 1852 * unmap an apic 1853 */ 1854 void 1855 mapout_apic(caddr_t addr, size_t len) 1856 { 1857 psm_unmap_phys(addr, len); 1858 } 1859 1860 void 1861 mapout_ioapic(caddr_t addr, size_t len) 1862 { 1863 mapout_apic(addr, len); 1864 } 1865 1866 /* 1867 * Check to make sure there are enough irq slots 1868 */ 1869 int 1870 apic_check_free_irqs(int count) 1871 { 1872 int i, avail; 1873 1874 avail = 0; 1875 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 1876 if ((apic_irq_table[i] == NULL) || 1877 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 1878 if (++avail >= count) 1879 return (PSM_SUCCESS); 1880 } 1881 } 1882 return (PSM_FAILURE); 1883 } 1884 1885 /* 1886 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 1887 */ 1888 int 1889 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 1890 int behavior) 1891 { 1892 int rcount, i; 1893 uchar_t start, irqno, cpu; 1894 major_t major; 1895 apic_irq_t *irqptr; 1896 1897 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 1898 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 1899 (void *)dip, inum, pri, count, behavior)); 1900 1901 if (count > 1) { 1902 if (behavior == DDI_INTR_ALLOC_STRICT && 1903 (apic_multi_msi_enable == 0 || count > apic_multi_msi_max)) 1904 return (0); 1905 1906 if (apic_multi_msi_enable == 0) 1907 count = 1; 1908 else if (count > apic_multi_msi_max) 1909 count = apic_multi_msi_max; 1910 } 1911 1912 if ((rcount = apic_navail_vector(dip, pri)) > count) 1913 rcount = count; 1914 else if (rcount == 0 || (rcount < count && 1915 behavior == DDI_INTR_ALLOC_STRICT)) 1916 return (0); 1917 1918 /* if not ISP2, then round it down */ 1919 if (!ISP2(rcount)) 1920 rcount = 1 << (highbit(rcount) - 1); 1921 1922 mutex_enter(&airq_mutex); 1923 1924 for (start = 0; rcount > 0; rcount >>= 1) { 1925 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 1926 behavior == DDI_INTR_ALLOC_STRICT) 1927 break; 1928 } 1929 1930 if (start == 0) { 1931 /* no vector available */ 1932 mutex_exit(&airq_mutex); 1933 return (0); 1934 } 1935 1936 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1937 /* not enough free irq slots available */ 1938 mutex_exit(&airq_mutex); 1939 return (0); 1940 } 1941 1942 major = (dip != NULL) ? ddi_name_to_major(ddi_get_name(dip)) : 0; 1943 for (i = 0; i < rcount; i++) { 1944 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1945 (uchar_t)-1) { 1946 /* 1947 * shouldn't happen because of the 1948 * apic_check_free_irqs() check earlier 1949 */ 1950 mutex_exit(&airq_mutex); 1951 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1952 "apic_allocate_irq failed\n")); 1953 return (i); 1954 } 1955 apic_max_device_irq = max(irqno, apic_max_device_irq); 1956 apic_min_device_irq = min(irqno, apic_min_device_irq); 1957 irqptr = apic_irq_table[irqno]; 1958 #ifdef DEBUG 1959 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 1960 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1961 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 1962 #endif 1963 apic_vector_to_irq[start + i] = (uchar_t)irqno; 1964 1965 irqptr->airq_vector = (uchar_t)(start + i); 1966 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 1967 irqptr->airq_intin_no = (uchar_t)rcount; 1968 irqptr->airq_ipl = pri; 1969 irqptr->airq_vector = start + i; 1970 irqptr->airq_origirq = (uchar_t)(inum + i); 1971 irqptr->airq_share_id = 0; 1972 irqptr->airq_mps_intr_index = MSI_INDEX; 1973 irqptr->airq_dip = dip; 1974 irqptr->airq_major = major; 1975 if (i == 0) /* they all bound to the same cpu */ 1976 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 1977 0xff, 0xff); 1978 else 1979 irqptr->airq_cpu = cpu; 1980 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 1981 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 1982 (void *)irqptr->airq_dip, irqptr->airq_vector, 1983 irqptr->airq_origirq, pri)); 1984 } 1985 mutex_exit(&airq_mutex); 1986 return (rcount); 1987 } 1988 1989 /* 1990 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 1991 */ 1992 int 1993 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 1994 int behavior) 1995 { 1996 int rcount, i; 1997 major_t major; 1998 1999 if (count > 1) { 2000 if (behavior == DDI_INTR_ALLOC_STRICT) { 2001 if (count > apic_msix_max) 2002 return (0); 2003 } else if (count > apic_msix_max) 2004 count = apic_msix_max; 2005 } 2006 2007 mutex_enter(&airq_mutex); 2008 2009 if ((rcount = apic_navail_vector(dip, pri)) > count) 2010 rcount = count; 2011 else if (rcount == 0 || (rcount < count && 2012 behavior == DDI_INTR_ALLOC_STRICT)) { 2013 rcount = 0; 2014 goto out; 2015 } 2016 2017 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 2018 /* not enough free irq slots available */ 2019 rcount = 0; 2020 goto out; 2021 } 2022 2023 major = (dip != NULL) ? ddi_name_to_major(ddi_get_name(dip)) : 0; 2024 for (i = 0; i < rcount; i++) { 2025 uchar_t vector, irqno; 2026 apic_irq_t *irqptr; 2027 2028 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 2029 (uchar_t)-1) { 2030 /* 2031 * shouldn't happen because of the 2032 * apic_check_free_irqs() check earlier 2033 */ 2034 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 2035 "apic_allocate_irq failed\n")); 2036 rcount = i; 2037 goto out; 2038 } 2039 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 2040 /* 2041 * shouldn't happen because of the 2042 * apic_navail_vector() call earlier 2043 */ 2044 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 2045 "apic_allocate_vector failed\n")); 2046 rcount = i; 2047 goto out; 2048 } 2049 apic_max_device_irq = max(irqno, apic_max_device_irq); 2050 apic_min_device_irq = min(irqno, apic_min_device_irq); 2051 irqptr = apic_irq_table[irqno]; 2052 irqptr->airq_vector = (uchar_t)vector; 2053 irqptr->airq_ipl = pri; 2054 irqptr->airq_origirq = (uchar_t)(inum + i); 2055 irqptr->airq_share_id = 0; 2056 irqptr->airq_mps_intr_index = MSIX_INDEX; 2057 irqptr->airq_dip = dip; 2058 irqptr->airq_major = major; 2059 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 2060 } 2061 out: 2062 mutex_exit(&airq_mutex); 2063 return (rcount); 2064 } 2065 2066 /* 2067 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 2068 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 2069 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 2070 * requests and allocated only when pri is set. 2071 */ 2072 uchar_t 2073 apic_allocate_vector(int ipl, int irq, int pri) 2074 { 2075 int lowest, highest, i; 2076 2077 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 2078 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 2079 2080 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 2081 lowest -= APIC_VECTOR_PER_IPL; 2082 2083 #ifdef DEBUG 2084 if (apic_restrict_vector) /* for testing shared interrupt logic */ 2085 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 2086 #endif /* DEBUG */ 2087 if (pri == 0) 2088 highest -= APIC_HI_PRI_VECTS; 2089 2090 for (i = lowest; i < highest; i++) { 2091 if (APIC_CHECK_RESERVE_VECTORS(i)) 2092 continue; 2093 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 2094 apic_vector_to_irq[i] = (uchar_t)irq; 2095 return (i); 2096 } 2097 } 2098 2099 return (0); 2100 } 2101 2102 /* Mark vector as not being used by any irq */ 2103 void 2104 apic_free_vector(uchar_t vector) 2105 { 2106 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 2107 } 2108 2109 uint32_t 2110 ioapic_read(int ioapic_ix, uint32_t reg) 2111 { 2112 volatile uint32_t *ioapic; 2113 2114 ioapic = apicioadr[ioapic_ix]; 2115 ioapic[APIC_IO_REG] = reg; 2116 return (ioapic[APIC_IO_DATA]); 2117 } 2118 2119 void 2120 ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value) 2121 { 2122 volatile uint32_t *ioapic; 2123 2124 ioapic = apicioadr[ioapic_ix]; 2125 ioapic[APIC_IO_REG] = reg; 2126 ioapic[APIC_IO_DATA] = value; 2127 } 2128 2129 static processorid_t 2130 apic_find_cpu(int flag) 2131 { 2132 processorid_t acid = 0; 2133 int i; 2134 2135 /* Find the first CPU with the passed-in flag set */ 2136 for (i = 0; i < apic_nproc; i++) { 2137 if (apic_cpus[i].aci_status & flag) { 2138 acid = i; 2139 break; 2140 } 2141 } 2142 2143 ASSERT((apic_cpus[acid].aci_status & flag) != 0); 2144 return (acid); 2145 } 2146 2147 /* 2148 * Call rebind to do the actual programming. 2149 * Must be called with interrupts disabled and apic_ioapic_lock held 2150 * 'p' is polymorphic -- if this function is called to process a deferred 2151 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 2152 * the irq pointer is retrieved. If not doing deferred reprogramming, 2153 * p is of the type 'apic_irq_t *'. 2154 * 2155 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 2156 * and it protects apic_find_cpu() from a race in which a CPU can be taken 2157 * offline after a cpu is selected, but before apic_rebind is called to 2158 * bind interrupts to it. 2159 */ 2160 int 2161 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 2162 { 2163 apic_irq_t *irqptr; 2164 struct ioapic_reprogram_data *drep = NULL; 2165 int rv; 2166 2167 if (deferred) { 2168 drep = (struct ioapic_reprogram_data *)p; 2169 ASSERT(drep != NULL); 2170 irqptr = drep->irqp; 2171 } else 2172 irqptr = (apic_irq_t *)p; 2173 2174 ASSERT(irqptr != NULL); 2175 2176 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 2177 if (rv) { 2178 /* 2179 * CPU is not up or interrupts are disabled. Fall back to 2180 * the first available CPU 2181 */ 2182 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 2183 drep); 2184 } 2185 2186 return (rv); 2187 } 2188 2189 2190 uchar_t 2191 apic_modify_vector(uchar_t vector, int irq) 2192 { 2193 apic_vector_to_irq[vector] = (uchar_t)irq; 2194 return (vector); 2195 } 2196 2197 char * 2198 apic_get_apic_type() 2199 { 2200 return (apic_psm_info.p_mach_idstring); 2201 } 2202