1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NXGE_NXGE_RXDMA_H 28 #define _SYS_NXGE_NXGE_RXDMA_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/nxge/nxge_rxdma_hw.h> 35 #include <npi_rxdma.h> 36 37 #define RXDMA_CK_DIV_DEFAULT 7500 /* 25 usec */ 38 /* 39 * Hardware RDC designer: 8 cache lines during Atlas bringup. 40 */ 41 #define RXDMA_RED_LESS_BYTES (8 * 64) /* 8 cache line */ 42 #define RXDMA_RED_LESS_ENTRIES (RXDMA_RED_LESS_BYTES/8) 43 #define RXDMA_RED_WINDOW_DEFAULT 0 44 #define RXDMA_RED_THRES_DEFAULT 0 45 46 #define RXDMA_RCR_PTHRES_DEFAULT 0x20 47 #define RXDMA_RCR_TO_DEFAULT 0x8 48 49 /* 50 * hardware workarounds: kick 16 (was 8 before) 51 */ 52 #define NXGE_RXDMA_POST_BATCH 16 53 54 #define RXBUF_START_ADDR(a, index, bsize) ((a & (index * bsize)) 55 #define RXBUF_OFFSET_FROM_START(a, start) (start - a) 56 #define RXBUF_64B_ALIGNED 64 57 58 #define NXGE_RXBUF_EXTRA 34 59 /* 60 * Receive buffer thresholds and buffer types 61 */ 62 #define NXGE_RX_BCOPY_SCALE 8 /* use 1/8 as lowest granularity */ 63 typedef enum { 64 NXGE_RX_COPY_ALL = 0, /* do bcopy on every packet */ 65 NXGE_RX_COPY_1, /* bcopy on 1/8 of buffer posted */ 66 NXGE_RX_COPY_2, /* bcopy on 2/8 of buffer posted */ 67 NXGE_RX_COPY_3, /* bcopy on 3/8 of buffer posted */ 68 NXGE_RX_COPY_4, /* bcopy on 4/8 of buffer posted */ 69 NXGE_RX_COPY_5, /* bcopy on 5/8 of buffer posted */ 70 NXGE_RX_COPY_6, /* bcopy on 6/8 of buffer posted */ 71 NXGE_RX_COPY_7, /* bcopy on 7/8 of buffer posted */ 72 NXGE_RX_COPY_NONE /* don't do bcopy at all */ 73 } nxge_rxbuf_threshold_t; 74 75 typedef enum { 76 NXGE_RBR_TYPE0 = RCR_PKTBUFSZ_0, /* bcopy buffer size 0 (small) */ 77 NXGE_RBR_TYPE1 = RCR_PKTBUFSZ_1, /* bcopy buffer size 1 (medium) */ 78 NXGE_RBR_TYPE2 = RCR_PKTBUFSZ_2 /* bcopy buffer size 2 (large) */ 79 } nxge_rxbuf_type_t; 80 81 typedef struct _rdc_errlog { 82 rdmc_par_err_log_t pre_par; 83 rdmc_par_err_log_t sha_par; 84 uint8_t compl_err_type; 85 } rdc_errlog_t; 86 87 /* 88 * Receive Statistics. 89 */ 90 typedef struct _nxge_rx_ring_stats_t { 91 uint64_t ipackets; 92 uint64_t ibytes; 93 uint32_t ierrors; 94 uint32_t multircv; 95 uint32_t brdcstrcv; 96 uint32_t norcvbuf; 97 98 uint32_t rx_inits; 99 uint32_t rx_jumbo_pkts; 100 uint32_t rx_multi_pkts; 101 uint32_t rx_mtu_pkts; 102 uint32_t rx_no_buf; 103 104 /* 105 * Receive buffer management statistics. 106 */ 107 uint32_t rx_new_pages; 108 uint32_t rx_new_mtu_pgs; 109 uint32_t rx_new_nxt_pgs; 110 uint32_t rx_reused_pgs; 111 uint32_t rx_mtu_drops; 112 uint32_t rx_nxt_drops; 113 114 /* 115 * Error event stats. 116 */ 117 uint32_t rx_rbr_tmout; 118 uint32_t pkt_too_long_err; 119 uint32_t l2_err; 120 uint32_t l4_cksum_err; 121 uint32_t fflp_soft_err; 122 uint32_t zcp_soft_err; 123 uint32_t rcr_unknown_err; 124 uint32_t dcf_err; 125 uint32_t rbr_tmout; 126 uint32_t rsp_cnt_err; 127 uint32_t byte_en_err; 128 uint32_t byte_en_bus; 129 uint32_t rsp_dat_err; 130 uint32_t rcr_ack_err; 131 uint32_t dc_fifo_err; 132 uint32_t rcr_sha_par; 133 uint32_t rbr_pre_par; 134 uint32_t port_drop_pkt; 135 uint32_t wred_drop; 136 uint32_t rbr_pre_empty; 137 uint32_t rcr_shadow_full; 138 uint32_t config_err; 139 uint32_t rcrincon; 140 uint32_t rcrfull; 141 uint32_t rbr_empty; 142 uint32_t rbrfull; 143 uint32_t rbrlogpage; 144 uint32_t cfiglogpage; 145 uint32_t rcrto; 146 uint32_t rcrthres; 147 uint32_t mex; 148 rdc_errlog_t errlog; 149 } nxge_rx_ring_stats_t, *p_nxge_rx_ring_stats_t; 150 151 typedef struct _nxge_rdc_sys_stats { 152 uint32_t pre_par; 153 uint32_t sha_par; 154 uint32_t id_mismatch; 155 uint32_t ipp_eop_err; 156 uint32_t zcp_eop_err; 157 } nxge_rdc_sys_stats_t, *p_nxge_rdc_sys_stats_t; 158 159 /* 160 * Software reserved buffer offset 161 */ 162 typedef struct _nxge_rxbuf_off_hdr_t { 163 uint32_t index; 164 } nxge_rxbuf_off_hdr_t, *p_nxge_rxbuf_off_hdr_t; 165 166 167 typedef struct _rx_msg_t { 168 nxge_os_dma_common_t buf_dma; 169 nxge_os_mutex_t lock; 170 struct _nxge_t *nxgep; 171 struct _rx_rbr_ring_t *rx_rbr_p; 172 boolean_t spare_in_use; 173 boolean_t free; 174 uint32_t ref_cnt; 175 #ifdef RXBUFF_USE_SEPARATE_UP_CNTR 176 uint32_t pass_up_cnt; 177 boolean_t release; 178 #endif 179 nxge_os_frtn_t freeb; 180 size_t bytes_arrived; 181 size_t bytes_expected; 182 size_t block_size; 183 uint32_t block_index; 184 uint32_t pkt_buf_size; 185 uint32_t pkt_buf_size_code; 186 uint32_t max_pkt_bufs; 187 uint32_t cur_usage_cnt; 188 uint32_t max_usage_cnt; 189 uchar_t *buffer; 190 uint32_t pri; 191 uint32_t shifted_addr; 192 boolean_t use_buf_pool; 193 p_mblk_t rx_mblk_p; 194 boolean_t rx_use_bcopy; 195 } rx_msg_t, *p_rx_msg_t; 196 197 typedef struct _rx_dma_handle_t { 198 nxge_os_dma_handle_t dma_handle; /* DMA handle */ 199 nxge_os_acc_handle_t acc_handle; /* DMA memory handle */ 200 npi_handle_t npi_handle; 201 } rx_dma_handle_t, *p_rx_dma_handle_t; 202 203 204 /* Receive Completion Ring */ 205 typedef struct _rx_rcr_ring_t { 206 nxge_os_dma_common_t rcr_desc; 207 208 struct _nxge_t *nxgep; 209 210 p_nxge_rx_ring_stats_t rdc_stats; 211 212 int poll_flag; /* 1 if polling mode */ 213 214 rcrcfig_a_t rcr_cfga; 215 rcrcfig_b_t rcr_cfgb; 216 217 nxge_os_mutex_t lock; 218 uint16_t index; 219 uint16_t rdc; 220 boolean_t full_hdr_flag; /* 1: 18 bytes header */ 221 uint16_t sw_priv_hdr_len; /* 0 - 192 bytes (SW) */ 222 uint32_t comp_size; /* # of RCR entries */ 223 uint64_t rcr_addr; 224 uint_t comp_wrap_mask; 225 uint_t comp_rd_index; 226 uint_t comp_wt_index; 227 228 p_rcr_entry_t rcr_desc_first_p; 229 p_rcr_entry_t rcr_desc_first_pp; 230 p_rcr_entry_t rcr_desc_last_p; 231 p_rcr_entry_t rcr_desc_last_pp; 232 233 p_rcr_entry_t rcr_desc_rd_head_p; /* software next read */ 234 p_rcr_entry_t rcr_desc_rd_head_pp; 235 236 uint64_t rcr_tail_pp; 237 uint64_t rcr_head_pp; 238 struct _rx_rbr_ring_t *rx_rbr_p; 239 uint32_t intr_timeout; 240 uint32_t intr_threshold; 241 uint64_t max_receive_pkts; 242 mac_ring_handle_t rcr_mac_handle; 243 uint64_t rcr_gen_num; 244 uint32_t rcvd_pkt_bytes; /* Received bytes of a packet */ 245 p_nxge_ldv_t ldvp; 246 p_nxge_ldg_t ldgp; 247 } rx_rcr_ring_t, *p_rx_rcr_ring_t; 248 249 250 251 /* Buffer index information */ 252 typedef struct _rxbuf_index_info_t { 253 uint32_t buf_index; 254 uint32_t start_index; 255 uint32_t buf_size; 256 uint64_t dvma_addr; 257 uint64_t kaddr; 258 } rxbuf_index_info_t, *p_rxbuf_index_info_t; 259 260 /* 261 * Buffer index information 262 */ 263 typedef struct _rxring_info_t { 264 uint32_t hint[RCR_N_PKTBUF_SZ]; 265 uint32_t block_size_mask; 266 uint16_t max_iterations; 267 rxbuf_index_info_t buffer[NXGE_DMA_BLOCK]; 268 } rxring_info_t, *p_rxring_info_t; 269 270 271 typedef enum { 272 RBR_POSTING = 1, /* We may post rx buffers. */ 273 RBR_UNMAPPING, /* We are in the process of unmapping. */ 274 RBR_UNMAPPED /* The ring is unmapped. */ 275 } rbr_state_t; 276 277 278 /* Receive Buffer Block Ring */ 279 typedef struct _rx_rbr_ring_t { 280 nxge_os_dma_common_t rbr_desc; 281 p_rx_msg_t *rx_msg_ring; 282 p_nxge_dma_common_t *dma_bufp; 283 rbr_cfig_a_t rbr_cfga; 284 rbr_cfig_b_t rbr_cfgb; 285 rbr_kick_t rbr_kick; 286 log_page_vld_t page_valid; 287 log_page_mask_t page_mask_1; 288 log_page_mask_t page_mask_2; 289 log_page_value_t page_value_1; 290 log_page_value_t page_value_2; 291 log_page_relo_t page_reloc_1; 292 log_page_relo_t page_reloc_2; 293 log_page_hdl_t page_hdl; 294 295 boolean_t cfg_set; 296 297 nxge_os_mutex_t lock; 298 nxge_os_mutex_t post_lock; 299 uint16_t index; 300 struct _nxge_t *nxgep; 301 uint16_t rdc; 302 uint16_t rdc_grp_id; 303 uint_t rbr_max_size; 304 uint64_t rbr_addr; 305 uint_t rbr_wrap_mask; 306 uint_t rbb_max; 307 uint_t rbb_added; 308 uint_t block_size; 309 uint_t num_blocks; 310 uint_t tnblocks; 311 uint_t pkt_buf_size0; 312 uint_t pkt_buf_size0_bytes; 313 uint_t npi_pkt_buf_size0; 314 uint_t pkt_buf_size1; 315 uint_t pkt_buf_size1_bytes; 316 uint_t npi_pkt_buf_size1; 317 uint_t pkt_buf_size2; 318 uint_t pkt_buf_size2_bytes; 319 uint_t npi_pkt_buf_size2; 320 321 uint32_t *rbr_desc_vp; 322 323 p_rx_rcr_ring_t rx_rcr_p; 324 325 uint_t rbr_wr_index; 326 uint_t rbr_rd_index; 327 328 rxring_info_t *ring_info; 329 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 330 uint64_t hv_rx_buf_base_ioaddr_pp; 331 uint64_t hv_rx_buf_ioaddr_size; 332 uint64_t hv_rx_cntl_base_ioaddr_pp; 333 uint64_t hv_rx_cntl_ioaddr_size; 334 boolean_t hv_set; 335 #endif 336 uint_t rbr_consumed; 337 uint_t rbr_threshold_hi; 338 uint_t rbr_threshold_lo; 339 nxge_rxbuf_type_t rbr_bufsize_type; 340 boolean_t rbr_use_bcopy; 341 342 /* 343 * <rbr_ref_cnt> is a count of those receive buffers which 344 * have been loaned to the kernel. We will not free this 345 * ring until the reference count reaches zero (0). 346 */ 347 uint32_t rbr_ref_cnt; 348 rbr_state_t rbr_state; /* POSTING, etc */ 349 /* 350 * Receive buffer allocation types: 351 * ddi_dma_mem_alloc(), contig_mem_alloc(), kmem_alloc() 352 */ 353 buf_alloc_type_t rbr_alloc_type; 354 } rx_rbr_ring_t, *p_rx_rbr_ring_t; 355 356 /* Receive Mailbox */ 357 typedef struct _rx_mbox_t { 358 nxge_os_dma_common_t rx_mbox; 359 rxdma_cfig1_t rx_cfg1; 360 rxdma_cfig2_t rx_cfg2; 361 uint64_t mbox_addr; 362 boolean_t cfg_set; 363 364 nxge_os_mutex_t lock; 365 uint16_t index; 366 struct _nxge_t *nxgep; 367 uint16_t rdc; 368 } rx_mbox_t, *p_rx_mbox_t; 369 370 371 typedef struct _rx_rbr_rings_t { 372 p_rx_rbr_ring_t *rbr_rings; 373 uint32_t ndmas; 374 boolean_t rxbuf_allocated; 375 } rx_rbr_rings_t, *p_rx_rbr_rings_t; 376 377 typedef struct _rx_rcr_rings_t { 378 p_rx_rcr_ring_t *rcr_rings; 379 uint32_t ndmas; 380 boolean_t cntl_buf_allocated; 381 } rx_rcr_rings_t, *p_rx_rcr_rings_t; 382 383 typedef struct _rx_mbox_areas_t { 384 p_rx_mbox_t *rxmbox_areas; 385 uint32_t ndmas; 386 boolean_t mbox_allocated; 387 } rx_mbox_areas_t, *p_rx_mbox_areas_t; 388 389 /* 390 * Global register definitions per chip and they are initialized 391 * using the function zero control registers. 392 * . 393 */ 394 395 typedef struct _rxdma_globals { 396 boolean_t mode32; 397 uint16_t rxdma_ck_div_cnt; 398 uint16_t rxdma_red_ran_init; 399 uint32_t rxdma_eing_timeout; 400 } rxdma_globals_t, *p_rxdma_globals; 401 402 403 /* 404 * Receive DMA Prototypes. 405 */ 406 nxge_status_t nxge_init_rxdma_channels(p_nxge_t); 407 void nxge_uninit_rxdma_channels(p_nxge_t); 408 409 nxge_status_t nxge_init_rxdma_channel(p_nxge_t, int); 410 void nxge_uninit_rxdma_channel(p_nxge_t, int); 411 412 nxge_status_t nxge_init_rxdma_channel_rcrflush(p_nxge_t, uint8_t); 413 nxge_status_t nxge_reset_rxdma_channel(p_nxge_t, uint16_t); 414 nxge_status_t nxge_init_rxdma_channel_cntl_stat(p_nxge_t, 415 uint16_t, p_rx_dma_ctl_stat_t); 416 nxge_status_t nxge_enable_rxdma_channel(p_nxge_t, 417 uint16_t, p_rx_rbr_ring_t, p_rx_rcr_ring_t, 418 p_rx_mbox_t); 419 nxge_status_t nxge_init_rxdma_channel_event_mask(p_nxge_t, 420 uint16_t, p_rx_dma_ent_msk_t); 421 422 nxge_status_t nxge_rxdma_hw_mode(p_nxge_t, boolean_t); 423 void nxge_hw_start_rx(p_nxge_t); 424 void nxge_fixup_rxdma_rings(p_nxge_t); 425 nxge_status_t nxge_dump_rxdma_channel(p_nxge_t, uint8_t); 426 427 void nxge_rxdma_fix_channel(p_nxge_t, uint16_t); 428 429 mblk_t *nxge_rx_poll(void *, int); 430 int nxge_enable_poll(void *); 431 int nxge_disable_poll(void *); 432 433 void nxge_rxdma_regs_dump_channels(p_nxge_t); 434 nxge_status_t nxge_rxdma_handle_sys_errors(p_nxge_t); 435 void nxge_rxdma_inject_err(p_nxge_t, uint32_t, uint8_t); 436 437 extern nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 438 extern nxge_status_t nxge_alloc_rxb(p_nxge_t nxgep, int channel); 439 extern void nxge_free_rxb(p_nxge_t nxgep, int channel); 440 441 int nxge_get_rxring_index(p_nxge_t, int, int); 442 443 #ifdef __cplusplus 444 } 445 #endif 446 447 #endif /* _SYS_NXGE_NXGE_RXDMA_H */ 448