1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_IMPL_H 27 #define _SYS_NXGE_NXGE_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * NIU HV API version definitions. 37 */ 38 #define NIU_MAJOR_VER 1 39 #define NIU_MINOR_VER 1 40 41 /* 42 * NIU HV API v1.0 definitions 43 */ 44 #define N2NIU_RX_LP_CONF 0x142 45 #define N2NIU_RX_LP_INFO 0x143 46 #define N2NIU_TX_LP_CONF 0x144 47 #define N2NIU_TX_LP_INFO 0x145 48 49 #ifndef _ASM 50 51 #include <sys/types.h> 52 #include <sys/byteorder.h> 53 #include <sys/debug.h> 54 #include <sys/stropts.h> 55 #include <sys/stream.h> 56 #include <sys/strlog.h> 57 #ifndef COSIM 58 #include <sys/strsubr.h> 59 #endif 60 #include <sys/cmn_err.h> 61 #include <sys/vtrace.h> 62 #include <sys/kmem.h> 63 #include <sys/ddi.h> 64 #include <sys/sunddi.h> 65 #include <sys/strsun.h> 66 #include <sys/stat.h> 67 #include <sys/cpu.h> 68 #include <sys/kstat.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <sys/dlpi.h> 72 #include <inet/nd.h> 73 #include <netinet/in.h> 74 #include <sys/ethernet.h> 75 #include <sys/vlan.h> 76 #include <sys/pci.h> 77 #include <sys/taskq.h> 78 #include <sys/atomic.h> 79 80 #include <sys/nxge/nxge_defs.h> 81 #include <sys/nxge/nxge_hw.h> 82 #include <sys/nxge/nxge_mac.h> 83 #include <sys/nxge/nxge_mii.h> 84 #include <sys/nxge/nxge_fm.h> 85 #if !defined(IODIAG) 86 #include <sys/netlb.h> 87 #endif 88 89 #include <sys/ddi_intr.h> 90 91 #if defined(_KERNEL) 92 #include <sys/mac.h> 93 #include <sys/mac_impl.h> 94 #include <sys/mac_ether.h> 95 #endif 96 97 #if defined(sun4v) 98 #include <sys/hypervisor_api.h> 99 #include <sys/machsystm.h> 100 #include <sys/hsvc.h> 101 #endif 102 103 /* 104 * Handy macros (taken from bge driver) 105 */ 106 #define RBR_SIZE 4 107 #define DMA_COMMON_CHANNEL(area) ((area.dma_channel)) 108 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 109 #define DMA_COMMON_VPTR_INDEX(area, index) \ 110 (((char *)(area.kaddrp)) + \ 111 (index * RBR_SIZE)) 112 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 113 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 114 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 115 #define DMA_COMMON_IOADDR_INDEX(area, index) \ 116 ((area.dma_cookie.dmac_laddress) + \ 117 (index * RBR_SIZE)) 118 119 #define DMA_NPI_HANDLE(area) ((area.npi_handle) 120 121 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 122 (area).offset, (area).alength, \ 123 (flag))) 124 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 125 ((void) ddi_dma_sync((area).dma_handle,\ 126 (area.offset + bufoffset), len, \ 127 (flag))) 128 129 #define DMA_COMMON_SYNC_RBR_DESC(area, index, flag) \ 130 ((void) ddi_dma_sync((area).dma_handle,\ 131 (index * RBR_SIZE), RBR_SIZE, \ 132 (flag))) 133 134 #define DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag) \ 135 ((void) ddi_dma_sync((area).dma_handle,\ 136 (index * RBR_SIZE), count * RBR_SIZE, \ 137 (flag))) 138 #define DMA_COMMON_SYNC_ENTRY(area, index, flag) \ 139 ((void) ddi_dma_sync((area).dma_handle,\ 140 (index * (area).block_size), \ 141 (area).block_size, \ 142 (flag))) 143 144 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 145 #define NEXT_ENTRY_PTR(ptr, first, last) \ 146 ((ptr == last) ? first : (ptr + 1)) 147 148 /* 149 * NPI related macros 150 */ 151 #define NXGE_DEV_NPI_HANDLE(nxgep) (nxgep->npi_handle) 152 153 #define NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah) 154 #define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap) 155 156 #define NPI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_handle.regh = ah) 157 #define NPI_ADD_HANDLE_SET(nxgep, ap) \ 158 nxgep->npi_handle.is_vraddr = B_FALSE; \ 159 nxgep->npi_handle.function.instance = nxgep->instance; \ 160 nxgep->npi_handle.function.function = nxgep->function_num; \ 161 nxgep->npi_handle.nxgep = (void *) nxgep; \ 162 nxgep->npi_handle.regp = ap; 163 164 #define NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah) 165 #define NPI_REG_ADD_HANDLE_SET(nxgep, ap) \ 166 nxgep->npi_reg_handle.is_vraddr = B_FALSE; \ 167 nxgep->npi_handle.function.instance = nxgep->instance; \ 168 nxgep->npi_handle.function.function = nxgep->function_num; \ 169 nxgep->npi_reg_handle.nxgep = (void *) nxgep; \ 170 nxgep->npi_reg_handle.regp = ap; 171 172 #define NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah) 173 #define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap) 174 175 #define NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah) 176 #define NPI_VREG_ADD_HANDLE_SET(nxgep, ap) \ 177 nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \ 178 nxgep->npi_handle.function.instance = nxgep->instance; \ 179 nxgep->npi_handle.function.function = nxgep->function_num; \ 180 nxgep->npi_vreg_handle.nxgep = (void *) nxgep; \ 181 nxgep->npi_vreg_handle.regp = ap; 182 183 #define NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah) 184 #define NPI_V2REG_ADD_HANDLE_SET(nxgep, ap) \ 185 nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \ 186 nxgep->npi_handle.function.instance = nxgep->instance; \ 187 nxgep->npi_handle.function.function = nxgep->function_num; \ 188 nxgep->npi_v2reg_handle.nxgep = (void *) nxgep; \ 189 nxgep->npi_v2reg_handle.regp = ap; 190 191 #define NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh) 192 #define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp) 193 #define NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh) 194 #define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp) 195 #define NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh) 196 #define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp) 197 #define NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh) 198 #define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp) 199 #define NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh) 200 #define NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp) 201 #define NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh) 202 #define NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp) 203 204 #define NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah) 205 #define NPI_DMA_ACC_HANDLE_GET(dmap) (dmap->npi_handle.regh) 206 207 /* 208 * DMA handles. 209 */ 210 #define NXGE_DESC_D_HANDLE_GET(desc) (desc.dma_handle) 211 #define NXGE_DESC_D_IOADD_GET(desc) (desc.dma_cookie.dmac_laddress) 212 #define NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress) 213 #define NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress) 214 215 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 216 #define LDV2_ON_1(ldv, vector) ((vector >> (ldv - 64)) & 0x1) 217 #define LDV2_ON_2(ldv, vector) (((vector >> 5) >> (ldv - 64)) & 0x1) 218 219 typedef uint32_t nxge_status_t; 220 221 typedef enum { 222 IDLE, 223 PROGRESS, 224 CONFIGURED 225 } dev_func_shared_t; 226 227 typedef enum { 228 DVMA, 229 DMA, 230 SDMA 231 } dma_method_t; 232 233 typedef enum { 234 BKSIZE_4K, 235 BKSIZE_8K, 236 BKSIZE_16K, 237 BKSIZE_32K 238 } nxge_rx_block_size_t; 239 240 #ifdef TX_ONE_BUF 241 #define TX_BCOPY_MAX 1514 242 #else 243 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 244 #define TX_BCOPY_MAX 4096 245 #define TX_BCOPY_SIZE 4096 246 #else 247 #define TX_BCOPY_MAX 2048 248 #define TX_BCOPY_SIZE 2048 249 #endif 250 #endif 251 252 #define TX_STREAM_MIN 512 253 #define TX_FASTDVMA_MIN 1024 254 255 #define NXGE_ERROR_SHOW_MAX 0 256 257 /* 258 * Defaults 259 */ 260 #define NXGE_RDC_RCR_THRESHOLD 8 261 #define NXGE_RDC_RCR_TIMEOUT 16 262 263 #define NXGE_RDC_RCR_THRESHOLD_MAX 1024 264 #define NXGE_RDC_RCR_TIMEOUT_MAX 64 265 #define NXGE_RDC_RCR_THRESHOLD_MIN 1 266 #define NXGE_RDC_RCR_TIMEOUT_MIN 1 267 #define NXGE_RCR_FULL_HEADER 1 268 269 #define NXGE_IS_VLAN_PACKET(ptr) \ 270 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 271 htons(VLAN_ETHERTYPE)) 272 273 typedef enum { 274 NONE, 275 SMALL, 276 MEDIUM, 277 LARGE 278 } dma_size_t; 279 280 typedef enum { 281 USE_NONE, 282 USE_BCOPY, 283 USE_DVMA, 284 USE_DMA, 285 USE_SDMA 286 } dma_type_t; 287 288 typedef enum { 289 NOT_IN_USE, 290 HDR_BUF, 291 MTU_BUF, 292 RE_ASSEMBLY_BUF, 293 FREE_BUF 294 } rx_page_state_t; 295 296 struct _nxge_block_mv_t { 297 uint32_t msg_type; 298 dma_type_t dma_type; 299 }; 300 301 typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t; 302 303 typedef enum { 304 NEPTUNE, /* 4 ports */ 305 NEPTUNE_2, /* 2 ports */ 306 N2_NIU /* N2/NIU 2 ports */ 307 } niu_type_t; 308 309 typedef enum { 310 CFG_DEFAULT = 0, /* default cfg */ 311 CFG_EQUAL, /* Equal */ 312 CFG_FAIR, /* Equal */ 313 CFG_CLASSIFY, 314 CFG_L2_CLASSIFY, 315 CFG_L3_CLASSIFY, 316 CFG_L3_DISTRIBUTE, 317 CFG_L3_WEB, 318 CFG_L3_TCAM, 319 CFG_NOT_SPECIFIED, 320 CFG_CUSTOM /* Custom */ 321 } cfg_type_t; 322 323 typedef enum { 324 NO_MSG = 0x0, /* No message output or storage. */ 325 CONSOLE = 0x1, /* Messages are go to the console. */ 326 BUFFER = 0x2, /* Messages are go to the system buffer. */ 327 CON_BUF = 0x3, /* Messages are go to the console and */ 328 /* system buffer. */ 329 VERBOSE = 0x4 /* Messages are go out only in VERBOSE node. */ 330 } out_msg_t, *p_out_msg_t; 331 332 typedef enum { 333 DBG_NO_MSG = 0x0, /* No message output or storage. */ 334 DBG_CONSOLE = 0x1, /* Messages are go to the console. */ 335 DBG_BUFFER = 0x2, /* Messages are go to the system buffer. */ 336 DBG_CON_BUF = 0x3, /* Messages are go to the console and */ 337 /* system buffer. */ 338 STR_LOG = 4 /* Sessage sent to streams logging driver. */ 339 } out_dbgmsg_t, *p_out_dbgmsg_t; 340 341 342 343 #if defined(_KERNEL) || defined(COSIM) 344 345 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 346 typedef struct ether_header ether_header_t, *p_ether_header_t; 347 typedef queue_t *p_queue_t; 348 349 #if !defined(IODIAG) 350 typedef mblk_t *p_mblk_t; 351 #endif 352 353 /* 354 * Common DMA data elements. 355 */ 356 struct _nxge_dma_common_t { 357 uint16_t dma_channel; 358 void *kaddrp; 359 void *first_kaddrp; 360 void *last_kaddrp; 361 void *ioaddr_pp; 362 void *first_ioaddr_pp; 363 void *last_ioaddr_pp; 364 ddi_dma_cookie_t dma_cookie; 365 uint32_t ncookies; 366 367 nxge_block_mv_t msg_dma_flags; 368 ddi_dma_handle_t dma_handle; 369 nxge_os_acc_handle_t acc_handle; 370 npi_handle_t npi_handle; 371 372 size_t block_size; 373 uint32_t nblocks; 374 size_t alength; 375 uint_t offset; 376 uint_t dma_chunk_index; 377 void *orig_ioaddr_pp; 378 uint64_t orig_vatopa; 379 void *orig_kaddrp; 380 size_t orig_alength; 381 boolean_t contig_alloc_type; 382 }; 383 384 typedef struct _nxge_t nxge_t, *p_nxge_t; 385 typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t; 386 387 typedef struct _nxge_dma_pool_t { 388 p_nxge_dma_common_t *dma_buf_pool_p; 389 uint32_t ndmas; 390 uint32_t *num_chunks; 391 boolean_t buf_allocated; 392 } nxge_dma_pool_t, *p_nxge_dma_pool_t; 393 394 /* 395 * Each logical device (69): 396 * - LDG # 397 * - flag bits 398 * - masks. 399 * - interrupt handler function. 400 * 401 * Generic system interrupt handler with two arguments: 402 * (nxge_sys_intr_t) 403 * Per device instance data structure 404 * Logical group data structure. 405 * 406 * Logical device interrupt handler with two arguments: 407 * (nxge_ldv_intr_t) 408 * Per device instance data structure 409 * Logical device number 410 */ 411 typedef struct _nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t; 412 typedef struct _nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t; 413 typedef uint_t (*nxge_sys_intr_t)(void *arg1, void *arg2); 414 typedef uint_t (*nxge_ldv_intr_t)(void *arg1, void *arg2); 415 416 /* 417 * Each logical device Group (64) needs to have the following 418 * configurations: 419 * - timer counter (6 bits) 420 * - timer resolution (20 bits, number of system clocks) 421 * - system data (7 bits) 422 */ 423 struct _nxge_ldg_t { 424 uint8_t ldg; /* logical group number */ 425 uint8_t vldg_index; 426 boolean_t arm; 427 boolean_t interrupted; 428 uint16_t ldg_timer; /* counter */ 429 uint8_t func; 430 uint8_t vector; 431 uint8_t intdata; 432 uint8_t nldvs; 433 p_nxge_ldv_t ldvp; 434 nxge_sys_intr_t sys_intr_handler; 435 uint_t (*ih_cb_func)(caddr_t, caddr_t); 436 p_nxge_t nxgep; 437 }; 438 439 struct _nxge_ldv_t { 440 uint8_t ldg_assigned; 441 uint8_t ldv; 442 boolean_t is_rxdma; 443 boolean_t is_txdma; 444 boolean_t is_mif; 445 boolean_t is_mac; 446 boolean_t is_syserr; 447 boolean_t use_timer; 448 uint8_t channel; 449 uint8_t vdma_index; 450 uint8_t func; 451 p_nxge_ldg_t ldgp; 452 uint8_t ldv_flags; 453 boolean_t is_leve; 454 boolean_t is_edge; 455 uint8_t ldv_ldf_masks; 456 nxge_ldv_intr_t ldv_intr_handler; 457 uint_t (*ih_cb_func)(caddr_t, caddr_t); 458 p_nxge_t nxgep; 459 }; 460 #endif 461 462 typedef struct _nxge_logical_page_t { 463 uint16_t dma; 464 uint16_t page; 465 boolean_t valid; 466 uint64_t mask; 467 uint64_t value; 468 uint64_t reloc; 469 uint32_t handle; 470 } nxge_logical_page_t, *p_nxge_logical_page_t; 471 472 /* 473 * (Internal) return values from ioctl subroutines. 474 */ 475 enum nxge_ioc_reply { 476 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 477 IOC_DONE, /* OK, reply sent */ 478 IOC_ACK, /* OK, just send ACK */ 479 IOC_REPLY, /* OK, just send reply */ 480 IOC_RESTART_ACK, /* OK, restart & ACK */ 481 IOC_RESTART_REPLY /* OK, restart & reply */ 482 }; 483 484 typedef struct _pci_cfg_t { 485 uint16_t vendorid; 486 uint16_t devid; 487 uint16_t command; 488 uint16_t status; 489 uint8_t revid; 490 uint8_t res0; 491 uint16_t junk1; 492 uint8_t cache_line; 493 uint8_t latency; 494 uint8_t header; 495 uint8_t bist; 496 uint32_t base; 497 uint32_t base14; 498 uint32_t base18; 499 uint32_t base1c; 500 uint32_t base20; 501 uint32_t base24; 502 uint32_t base28; 503 uint32_t base2c; 504 uint32_t base30; 505 uint32_t res1[2]; 506 uint8_t int_line; 507 uint8_t int_pin; 508 uint8_t min_gnt; 509 uint8_t max_lat; 510 } pci_cfg_t, *p_pci_cfg_t; 511 512 #if defined(_KERNEL) || defined(COSIM) 513 514 typedef struct _dev_regs_t { 515 nxge_os_acc_handle_t nxge_pciregh; /* PCI config DDI IO handle */ 516 p_pci_cfg_t nxge_pciregp; /* mapped PCI registers */ 517 518 nxge_os_acc_handle_t nxge_regh; /* device DDI IO (BAR 0) */ 519 void *nxge_regp; /* mapped device registers */ 520 521 nxge_os_acc_handle_t nxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 522 void *nxge_msix_regp; /* MSI/X register */ 523 524 nxge_os_acc_handle_t nxge_vir_regh; /* virtualization (BAR 4) */ 525 unsigned char *nxge_vir_regp; /* virtualization register */ 526 527 nxge_os_acc_handle_t nxge_vir2_regh; /* second virtualization */ 528 unsigned char *nxge_vir2_regp; /* second virtualization */ 529 530 nxge_os_acc_handle_t nxge_romh; /* fcode rom handle */ 531 unsigned char *nxge_romp; /* fcode pointer */ 532 } dev_regs_t, *p_dev_regs_t; 533 534 535 typedef struct _nxge_mac_addr_t { 536 ether_addr_t addr; 537 uint_t flags; 538 } nxge_mac_addr_t; 539 540 /* 541 * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac) 542 * for each XMAC port and supports 1 unique MAC and 7 alternate MACs 543 * for each BMAC port. The number of MACs assigned by the factory is 544 * different and is as follows, 545 * BMAC port: num_factory_mmac = num_mmac = 7 546 * XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15 547 * XMAC port on a 4-port NIC: num_factory_mmac = 7 548 * So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses 549 * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac. 550 * 551 * total_factory_macs is the total number of factory MACs, including 552 * the unique MAC, assigned to a Neptune based NIC card, it is 32. 553 */ 554 typedef struct _nxge_mmac_t { 555 uint8_t total_factory_macs; 556 uint8_t num_mmac; 557 uint8_t num_factory_mmac; 558 nxge_mac_addr_t mac_pool[XMAC_MAX_ADDR_ENTRY]; 559 ether_addr_t factory_mac_pool[XMAC_MAX_ADDR_ENTRY]; 560 uint8_t naddrfree; /* number of alt mac addr available */ 561 } nxge_mmac_t; 562 563 /* 564 * mmac stats structure 565 */ 566 typedef struct _nxge_mmac_stats_t { 567 uint8_t mmac_max_cnt; 568 uint8_t mmac_avail_cnt; 569 struct ether_addr mmac_avail_pool[16]; 570 } nxge_mmac_stats_t, *p_nxge_mmac_stats_t; 571 572 #define NXGE_MAX_MMAC_ADDRS 32 573 #define NXGE_NUM_MMAC_ADDRS 8 574 #define NXGE_NUM_OF_PORTS_QUAD 4 575 #define NXGE_NUM_OF_PORTS_DUAL 2 576 577 #define NXGE_QGC_LP_BM_STR "501-7606" 578 #define NXGE_2XGF_LP_BM_STR "501-7283" 579 #define NXGE_QGC_PEM_BM_STR "501-7765" 580 #define NXGE_2XGF_PEM_BM_STR "501-7626" 581 #define NXGE_EROM_LEN 1048576 582 583 #endif 584 585 #include <sys/nxge/nxge_common_impl.h> 586 #include <sys/nxge/nxge_common.h> 587 #include <sys/nxge/nxge_txc.h> 588 #include <sys/nxge/nxge_rxdma.h> 589 #include <sys/nxge/nxge_txdma.h> 590 #include <sys/nxge/nxge_fflp.h> 591 #include <sys/nxge/nxge_ipp.h> 592 #include <sys/nxge/nxge_zcp.h> 593 #include <sys/nxge/nxge_fzc.h> 594 #include <sys/nxge/nxge_flow.h> 595 #include <sys/nxge/nxge_virtual.h> 596 597 #include <npi_espc.h> 598 #include <npi_vir.h> 599 600 #include <sys/nxge/nxge.h> 601 602 #include <sys/modctl.h> 603 #include <sys/pattr.h> 604 605 extern int secpolicy_net_config(const cred_t *, boolean_t); 606 extern void nxge_fm_report_error(p_nxge_t, uint8_t, 607 uint8_t, nxge_fm_ereport_id_t); 608 extern int fm_check_acc_handle(ddi_acc_handle_t); 609 extern int fm_check_dma_handle(ddi_dma_handle_t); 610 611 /* nxge_classify.c */ 612 nxge_status_t nxge_classify_init(p_nxge_t); 613 nxge_status_t nxge_classify_uninit(p_nxge_t); 614 nxge_status_t nxge_set_hw_classify_config(p_nxge_t); 615 nxge_status_t nxge_classify_exit_sw(p_nxge_t); 616 617 /* nxge_fflp.c */ 618 void nxge_put_tcam(p_nxge_t, p_mblk_t); 619 void nxge_get_tcam(p_nxge_t, p_mblk_t); 620 nxge_status_t nxge_classify_init_hw(p_nxge_t); 621 nxge_status_t nxge_classify_init_sw(p_nxge_t); 622 nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t); 623 nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t, 624 uint32_t); 625 626 nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t, 627 tcam_class_t, 628 uint32_t *); 629 630 nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t, 631 uint32_t); 632 633 nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t, 634 uint32_t); 635 636 uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t); 637 nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *); 638 nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t); 639 nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t); 640 641 nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t); 642 nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t); 643 644 nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t); 645 nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t); 646 647 nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t); 648 nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t); 649 650 nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t); 651 652 nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t); 653 654 nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t); 655 656 void nxge_handle_tcam_fragment_bug(p_nxge_t); 657 nxge_status_t nxge_fflp_hw_reset(p_nxge_t); 658 nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t); 659 nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t); 660 661 /* nxge_kstats.c */ 662 void nxge_init_statsp(p_nxge_t); 663 void nxge_setup_kstats(p_nxge_t); 664 void nxge_destroy_kstats(p_nxge_t); 665 int nxge_port_kstat_update(kstat_t *, int); 666 void nxge_save_cntrs(p_nxge_t); 667 668 int nxge_m_stat(void *arg, uint_t, uint64_t *); 669 670 /* nxge_hw.c */ 671 void 672 nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 673 void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 674 void nxge_global_reset(p_nxge_t); 675 uint_t nxge_intr(void *, void *); 676 void nxge_intr_enable(p_nxge_t); 677 void nxge_intr_disable(p_nxge_t); 678 void nxge_hw_blank(void *arg, time_t, uint_t); 679 void nxge_hw_id_init(p_nxge_t); 680 void nxge_hw_init_niu_common(p_nxge_t); 681 void nxge_intr_hw_enable(p_nxge_t); 682 void nxge_intr_hw_disable(p_nxge_t); 683 void nxge_hw_stop(p_nxge_t); 684 void nxge_global_reset(p_nxge_t); 685 void nxge_check_hw_state(p_nxge_t); 686 687 void nxge_rxdma_channel_put64(nxge_os_acc_handle_t, 688 void *, uint32_t, uint16_t, 689 uint64_t); 690 uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *, 691 uint32_t, uint16_t); 692 693 694 void nxge_get32(p_nxge_t, p_mblk_t); 695 void nxge_put32(p_nxge_t, p_mblk_t); 696 697 void nxge_hw_set_mac_modes(p_nxge_t); 698 699 /* nxge_send.c. */ 700 uint_t nxge_reschedule(caddr_t); 701 702 /* nxge_rxdma.c */ 703 nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t, 704 uint8_t, uint8_t); 705 706 nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t, 707 uint8_t, uint8_t); 708 nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t, 709 uint16_t); 710 nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t, 711 uint16_t, uint8_t); 712 713 /* nxge_ndd.c */ 714 void nxge_get_param_soft_properties(p_nxge_t); 715 void nxge_copy_hw_default_to_param(p_nxge_t); 716 void nxge_copy_param_hw_to_config(p_nxge_t); 717 void nxge_setup_param(p_nxge_t); 718 void nxge_init_param(p_nxge_t); 719 void nxge_destroy_param(p_nxge_t); 720 boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t); 721 boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t); 722 boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t); 723 724 boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t); 725 726 int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t); 727 int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 728 int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 729 int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t); 730 int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 731 int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t); 732 long nxge_strtol(char *, char **, int); 733 boolean_t nxge_param_get_instance(queue_t *, mblk_t *); 734 void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 735 boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 736 void nxge_nd_free(caddr_t *); 737 int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t); 738 739 void nxge_set_lb_normal(p_nxge_t); 740 boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t); 741 742 /* nxge_virtual.c */ 743 nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *); 744 void nxge_common_lock_get(p_nxge_t); 745 void nxge_common_lock_free(p_nxge_t); 746 747 nxge_status_t nxge_get_config_properties(p_nxge_t); 748 void nxge_get_xcvr_properties(p_nxge_t); 749 void nxge_init_vlan_config(p_nxge_t); 750 void nxge_init_mac_config(p_nxge_t); 751 752 753 void nxge_init_logical_devs(p_nxge_t); 754 int nxge_init_ldg_intrs(p_nxge_t); 755 756 void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t, 757 uint32_t); 758 759 void nxge_init_fzc_txdma_channels(p_nxge_t); 760 761 nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t, 762 p_tx_ring_t, p_tx_mbox_t); 763 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 764 765 nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t, 766 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 767 768 nxge_status_t nxge_init_fzc_rdc_tbl(p_nxge_t); 769 nxge_status_t nxge_init_fzc_rx_common(p_nxge_t); 770 nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t); 771 772 nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t, 773 uint16_t, p_rx_rbr_ring_t); 774 nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t, 775 uint16_t, p_rx_rcr_ring_t); 776 777 nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t, 778 uint16_t, p_rx_rbr_ring_t); 779 780 781 nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t, 782 uint16_t, p_tx_ring_t); 783 784 nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t, 785 p_tx_ring_t); 786 787 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 788 789 void nxge_init_fzc_ldg_num(p_nxge_t); 790 void nxge_init_fzc_sys_int_data(p_nxge_t); 791 void nxge_init_fzc_ldg_int_timer(p_nxge_t); 792 nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on); 793 794 /* MAC functions */ 795 nxge_status_t nxge_mac_init(p_nxge_t); 796 nxge_status_t nxge_link_init(p_nxge_t); 797 nxge_status_t nxge_xif_init(p_nxge_t); 798 nxge_status_t nxge_pcs_init(p_nxge_t); 799 nxge_status_t nxge_serdes_init(p_nxge_t); 800 nxge_status_t nxge_n2_serdes_init(p_nxge_t); 801 nxge_status_t nxge_neptune_serdes_init(p_nxge_t); 802 nxge_status_t nxge_xcvr_find(p_nxge_t); 803 nxge_status_t nxge_get_xcvr_type(p_nxge_t); 804 nxge_status_t nxge_xcvr_init(p_nxge_t); 805 nxge_status_t nxge_tx_mac_init(p_nxge_t); 806 nxge_status_t nxge_rx_mac_init(p_nxge_t); 807 nxge_status_t nxge_tx_mac_enable(p_nxge_t); 808 nxge_status_t nxge_tx_mac_disable(p_nxge_t); 809 nxge_status_t nxge_rx_mac_enable(p_nxge_t); 810 nxge_status_t nxge_rx_mac_disable(p_nxge_t); 811 nxge_status_t nxge_tx_mac_reset(p_nxge_t); 812 nxge_status_t nxge_rx_mac_reset(p_nxge_t); 813 nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t); 814 nxge_status_t nxge_mii_xcvr_init(p_nxge_t); 815 nxge_status_t nxge_mii_read(p_nxge_t, uint8_t, 816 uint8_t, uint16_t *); 817 nxge_status_t nxge_mii_write(p_nxge_t, uint8_t, 818 uint8_t, uint16_t); 819 nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t, 820 uint16_t, uint16_t *); 821 nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t, 822 uint8_t, uint16_t, uint16_t); 823 nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t, 824 mii_bmsr_t, nxge_link_state_t *); 825 nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *); 826 nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *); 827 nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *); 828 nxge_status_t nxge_check_mii_link(p_nxge_t); 829 nxge_status_t nxge_check_10g_link(p_nxge_t); 830 nxge_status_t nxge_check_serdes_link(p_nxge_t); 831 nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *); 832 void nxge_link_is_down(p_nxge_t); 833 void nxge_link_is_up(p_nxge_t); 834 nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t); 835 uint32_t crc32_mchash(p_ether_addr_t); 836 nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t); 837 nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t); 838 nxge_status_t nxge_10g_link_led_on(p_nxge_t); 839 nxge_status_t nxge_10g_link_led_off(p_nxge_t); 840 boolean_t nxge_is_valid_local_mac(ether_addr_st); 841 842 /* espc (sprom) prototypes */ 843 nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t); 844 nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *); 845 nxge_status_t nxge_espc_num_ports_get(p_nxge_t); 846 nxge_status_t nxge_espc_phy_type_get(p_nxge_t); 847 void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *); 848 nxge_status_t nxge_vpd_info_get(p_nxge_t); 849 850 851 void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...); 852 853 uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t, 854 uint64_t, uint64_t); 855 #pragma weak hv_niu_rx_logical_page_conf 856 857 uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t, 858 uint64_t *, uint64_t *); 859 #pragma weak hv_niu_rx_logical_page_info 860 861 uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t, 862 uint64_t, uint64_t); 863 #pragma weak hv_niu_tx_logical_page_conf 864 865 uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t, 866 uint64_t *, uint64_t *); 867 #pragma weak hv_niu_tx_logical_page_info 868 869 #ifdef NXGE_DEBUG 870 char *nxge_dump_packet(char *, int); 871 #endif 872 873 #endif /* !_ASM */ 874 875 #ifdef __cplusplus 876 } 877 #endif 878 879 #endif /* _SYS_NXGE_NXGE_IMPL_H */ 880