1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_IMPL_H 27 #define _SYS_NXGE_NXGE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * NIU HV API version definitions. 35 */ 36 #define NIU_MAJOR_VER 1 37 #define NIU_MINOR_VER 1 38 39 /* 40 * NIU HV API v1.0 definitions 41 */ 42 #define N2NIU_RX_LP_CONF 0x142 43 #define N2NIU_RX_LP_INFO 0x143 44 #define N2NIU_TX_LP_CONF 0x144 45 #define N2NIU_TX_LP_INFO 0x145 46 47 #ifndef _ASM 48 49 #include <sys/types.h> 50 #include <sys/byteorder.h> 51 #include <sys/debug.h> 52 #include <sys/stropts.h> 53 #include <sys/stream.h> 54 #include <sys/strlog.h> 55 #include <sys/strsubr.h> 56 #include <sys/cmn_err.h> 57 #include <sys/vtrace.h> 58 #include <sys/kmem.h> 59 #include <sys/ddi.h> 60 #include <sys/sunddi.h> 61 #include <sys/strsun.h> 62 #include <sys/stat.h> 63 #include <sys/cpu.h> 64 #include <sys/kstat.h> 65 #include <inet/common.h> 66 #include <inet/ip.h> 67 #include <sys/dlpi.h> 68 #include <inet/nd.h> 69 #include <netinet/in.h> 70 #include <sys/ethernet.h> 71 #include <sys/vlan.h> 72 #include <sys/pci.h> 73 #include <sys/taskq.h> 74 #include <sys/atomic.h> 75 76 #include <sys/nxge/nxge_defs.h> 77 #include <sys/nxge/nxge_hw.h> 78 #include <sys/nxge/nxge_mac.h> 79 #include <sys/nxge/nxge_mii.h> 80 #include <sys/nxge/nxge_fm.h> 81 #include <sys/netlb.h> 82 83 #include <sys/ddi_intr.h> 84 #include <sys/mac.h> 85 #include <sys/mac_impl.h> 86 #include <sys/mac_ether.h> 87 88 #if defined(sun4v) 89 #include <sys/hypervisor_api.h> 90 #include <sys/machsystm.h> 91 #include <sys/hsvc.h> 92 #endif 93 94 #include <sys/dld.h> 95 96 /* 97 * Handy macros (taken from bge driver) 98 */ 99 #define RBR_SIZE 4 100 #define DMA_COMMON_CHANNEL(area) ((area.dma_channel)) 101 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 102 #define DMA_COMMON_VPTR_INDEX(area, index) \ 103 (((char *)(area.kaddrp)) + \ 104 (index * RBR_SIZE)) 105 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 106 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 107 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 108 #define DMA_COMMON_IOADDR_INDEX(area, index) \ 109 ((area.dma_cookie.dmac_laddress) + \ 110 (index * RBR_SIZE)) 111 112 #define DMA_NPI_HANDLE(area) ((area.npi_handle) 113 114 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 115 (area).offset, (area).alength, \ 116 (flag))) 117 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 118 ((void) ddi_dma_sync((area).dma_handle,\ 119 (area.offset + bufoffset), len, \ 120 (flag))) 121 122 #define DMA_COMMON_SYNC_RBR_DESC(area, index, flag) \ 123 ((void) ddi_dma_sync((area).dma_handle,\ 124 (index * RBR_SIZE), RBR_SIZE, \ 125 (flag))) 126 127 #define DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag) \ 128 ((void) ddi_dma_sync((area).dma_handle,\ 129 (index * RBR_SIZE), count * RBR_SIZE, \ 130 (flag))) 131 #define DMA_COMMON_SYNC_ENTRY(area, index, flag) \ 132 ((void) ddi_dma_sync((area).dma_handle,\ 133 (index * (area).block_size), \ 134 (area).block_size, \ 135 (flag))) 136 137 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 138 #define NEXT_ENTRY_PTR(ptr, first, last) \ 139 ((ptr == last) ? first : (ptr + 1)) 140 141 /* 142 * NPI related macros 143 */ 144 #define NXGE_DEV_NPI_HANDLE(nxgep) (nxgep->npi_handle) 145 146 #define NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah) 147 #define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap) 148 149 #define NPI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_handle.regh = ah) 150 #define NPI_ADD_HANDLE_SET(nxgep, ap) \ 151 nxgep->npi_handle.is_vraddr = B_FALSE; \ 152 nxgep->npi_handle.function.instance = nxgep->instance; \ 153 nxgep->npi_handle.function.function = nxgep->function_num; \ 154 nxgep->npi_handle.nxgep = (void *) nxgep; \ 155 nxgep->npi_handle.regp = ap; 156 157 #define NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah) 158 #define NPI_REG_ADD_HANDLE_SET(nxgep, ap) \ 159 nxgep->npi_reg_handle.is_vraddr = B_FALSE; \ 160 nxgep->npi_handle.function.instance = nxgep->instance; \ 161 nxgep->npi_handle.function.function = nxgep->function_num; \ 162 nxgep->npi_reg_handle.nxgep = (void *) nxgep; \ 163 nxgep->npi_reg_handle.regp = ap; 164 165 #define NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah) 166 #define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap) 167 168 #define NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah) 169 #define NPI_VREG_ADD_HANDLE_SET(nxgep, ap) \ 170 nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \ 171 nxgep->npi_handle.function.instance = nxgep->instance; \ 172 nxgep->npi_handle.function.function = nxgep->function_num; \ 173 nxgep->npi_vreg_handle.nxgep = (void *) nxgep; \ 174 nxgep->npi_vreg_handle.regp = ap; 175 176 #define NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah) 177 #define NPI_V2REG_ADD_HANDLE_SET(nxgep, ap) \ 178 nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \ 179 nxgep->npi_handle.function.instance = nxgep->instance; \ 180 nxgep->npi_handle.function.function = nxgep->function_num; \ 181 nxgep->npi_v2reg_handle.nxgep = (void *) nxgep; \ 182 nxgep->npi_v2reg_handle.regp = ap; 183 184 #define NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh) 185 #define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp) 186 #define NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh) 187 #define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp) 188 #define NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh) 189 #define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp) 190 #define NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh) 191 #define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp) 192 #define NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh) 193 #define NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp) 194 #define NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh) 195 #define NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp) 196 197 #define NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah) 198 #define NPI_DMA_ACC_HANDLE_GET(dmap) (dmap->npi_handle.regh) 199 200 /* 201 * DMA handles. 202 */ 203 #define NXGE_DESC_D_HANDLE_GET(desc) (desc.dma_handle) 204 #define NXGE_DESC_D_IOADD_GET(desc) (desc.dma_cookie.dmac_laddress) 205 #define NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress) 206 #define NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress) 207 208 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 209 #define LDV2_ON_1(ldv, vector) ((vector >> (ldv - 64)) & 0x1) 210 #define LDV2_ON_2(ldv, vector) (((vector >> 5) >> (ldv - 64)) & 0x1) 211 212 typedef uint32_t nxge_status_t; 213 214 typedef enum { 215 IDLE, 216 PROGRESS, 217 CONFIGURED 218 } dev_func_shared_t; 219 220 typedef enum { 221 DVMA, 222 DMA, 223 SDMA 224 } dma_method_t; 225 226 typedef enum { 227 BKSIZE_4K, 228 BKSIZE_8K, 229 BKSIZE_16K, 230 BKSIZE_32K 231 } nxge_rx_block_size_t; 232 233 #ifdef TX_ONE_BUF 234 #define TX_BCOPY_MAX 1514 235 #else 236 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 237 #define TX_BCOPY_MAX 4096 238 #define TX_BCOPY_SIZE 4096 239 #else 240 #define TX_BCOPY_MAX 2048 241 #define TX_BCOPY_SIZE 2048 242 #endif 243 #endif 244 245 #define TX_STREAM_MIN 512 246 #define TX_FASTDVMA_MIN 1024 247 248 /* 249 * Send repeated FMA ereports or display messages about some non-fatal 250 * hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times 251 */ 252 #define NXGE_ERROR_SHOW_MAX 2 253 254 255 /* 256 * Defaults 257 */ 258 #define NXGE_RDC_RCR_THRESHOLD 8 259 #define NXGE_RDC_RCR_TIMEOUT 16 260 261 #define NXGE_RDC_RCR_THRESHOLD_MAX 1024 262 #define NXGE_RDC_RCR_TIMEOUT_MAX 64 263 #define NXGE_RDC_RCR_THRESHOLD_MIN 1 264 #define NXGE_RDC_RCR_TIMEOUT_MIN 1 265 #define NXGE_RCR_FULL_HEADER 1 266 267 #define NXGE_IS_VLAN_PACKET(ptr) \ 268 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 269 htons(VLAN_ETHERTYPE)) 270 271 typedef enum { 272 NONE, 273 SMALL, 274 MEDIUM, 275 LARGE 276 } dma_size_t; 277 278 typedef enum { 279 USE_NONE, 280 USE_BCOPY, 281 USE_DVMA, 282 USE_DMA, 283 USE_SDMA 284 } dma_type_t; 285 286 typedef enum { 287 NOT_IN_USE, 288 HDR_BUF, 289 MTU_BUF, 290 RE_ASSEMBLY_BUF, 291 FREE_BUF 292 } rx_page_state_t; 293 294 struct _nxge_block_mv_t { 295 uint32_t msg_type; 296 dma_type_t dma_type; 297 }; 298 299 typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t; 300 301 typedef enum { 302 NIU_TYPE_NONE = 0, 303 304 /* QGC NIC */ 305 NEPTUNE_4_1GC = 306 (NXGE_PORT_1G_COPPER | 307 (NXGE_PORT_1G_COPPER << 4) | 308 (NXGE_PORT_1G_COPPER << 8) | 309 (NXGE_PORT_1G_COPPER << 12)), 310 311 /* Huron: 2 fiber XAUI cards */ 312 NEPTUNE_2_10GF = 313 (NXGE_PORT_10G_FIBRE | 314 (NXGE_PORT_10G_FIBRE << 4) | 315 (NXGE_PORT_NONE << 8) | 316 (NXGE_PORT_NONE << 12)), 317 318 /* Huron: port0 is a TN1010 copper XAUI */ 319 NEPTUNE_1_TN1010 = 320 (NXGE_PORT_TN1010 | 321 (NXGE_PORT_NONE << 4) | 322 (NXGE_PORT_NONE << 8) | 323 (NXGE_PORT_NONE << 12)), 324 325 /* Huron: port1 is a TN1010 copper XAUI */ 326 NEPTUNE_1_NONE_1_TN1010 = 327 (NXGE_PORT_NONE | 328 (NXGE_PORT_TN1010 << 4) | 329 (NXGE_PORT_NONE << 8) | 330 (NXGE_PORT_NONE << 12)), 331 332 /* Huron: 2 TN1010 copper XAUI cards */ 333 NEPTUNE_2_TN1010 = 334 (NXGE_PORT_TN1010 | 335 (NXGE_PORT_TN1010 << 4) | 336 (NXGE_PORT_NONE << 8) | 337 (NXGE_PORT_NONE << 12)), 338 339 /* Huron: port0 is fiber XAUI, port1 is copper XAUI */ 340 NEPTUNE_1_10GF_1_TN1010 = 341 (NXGE_PORT_10G_FIBRE | 342 (NXGE_PORT_TN1010 << 4) | 343 (NXGE_PORT_NONE << 8) | 344 (NXGE_PORT_NONE << 12)), 345 346 /* Huron: port0 is copper XAUI, port1 is fiber XAUI */ 347 NEPTUNE_1_TN1010_1_10GF = 348 (NXGE_PORT_TN1010 | 349 (NXGE_PORT_10G_FIBRE << 4) | 350 (NXGE_PORT_NONE << 8) | 351 (NXGE_PORT_NONE << 12)), 352 353 /* Maramba: port0 and port1 are fiber XAUIs */ 354 NEPTUNE_2_10GF_2_1GC = 355 (NXGE_PORT_10G_FIBRE | 356 (NXGE_PORT_10G_FIBRE << 4) | 357 (NXGE_PORT_1G_COPPER << 8) | 358 (NXGE_PORT_1G_COPPER << 12)), 359 360 /* Maramba: port0 and port1 are copper TN1010 XAUIs */ 361 NEPTUNE_2_TN1010_2_1GC = 362 (NXGE_PORT_TN1010 | 363 (NXGE_PORT_TN1010 << 4) | 364 (NXGE_PORT_1G_COPPER << 8) | 365 (NXGE_PORT_1G_COPPER << 12)), 366 367 /* Maramba: port0 is copper XAUI, port1 is Fiber XAUI */ 368 NEPTUNE_1_TN1010_1_10GF_2_1GC = 369 (NXGE_PORT_TN1010 | 370 (NXGE_PORT_10G_FIBRE << 4) | 371 (NXGE_PORT_1G_COPPER << 8) | 372 (NXGE_PORT_1G_COPPER << 12)), 373 374 /* Maramba: port0 is fiber XAUI, port1 is copper XAUI */ 375 NEPTUNE_1_10GF_1_TN1010_2_1GC = 376 (NXGE_PORT_10G_FIBRE | 377 (NXGE_PORT_TN1010 << 4) | 378 (NXGE_PORT_1G_COPPER << 8) | 379 (NXGE_PORT_1G_COPPER << 12)), 380 381 /* Maramba: port0 is fiber XAUI */ 382 NEPTUNE_1_10GF_3_1GC = 383 (NXGE_PORT_10G_FIBRE | 384 (NXGE_PORT_1G_COPPER << 4) | 385 (NXGE_PORT_1G_COPPER << 8) | 386 (NXGE_PORT_1G_COPPER << 12)), 387 388 /* Maramba: port0 is TN1010 copper XAUI */ 389 NEPTUNE_1_TN1010_3_1GC = 390 (NXGE_PORT_TN1010 | 391 (NXGE_PORT_1G_COPPER << 4) | 392 (NXGE_PORT_1G_COPPER << 8) | 393 (NXGE_PORT_1G_COPPER << 12)), 394 395 /* Maramba: port1 is fiber XAUI */ 396 NEPTUNE_1_1GC_1_10GF_2_1GC = 397 (NXGE_PORT_1G_COPPER | 398 (NXGE_PORT_10G_FIBRE << 4) | 399 (NXGE_PORT_1G_COPPER << 8) | 400 (NXGE_PORT_1G_COPPER << 12)), 401 402 /* Maramba: port1 is TN1010 copper XAUI */ 403 NEPTUNE_1_1GC_1_TN1010_2_1GC = 404 (NXGE_PORT_1G_COPPER | 405 (NXGE_PORT_TN1010 << 4) | 406 (NXGE_PORT_1G_COPPER << 8) | 407 (NXGE_PORT_1G_COPPER << 12)), 408 409 NEPTUNE_2_1GRF = 410 (NXGE_PORT_NONE | 411 (NXGE_PORT_NONE << 4) | 412 (NXGE_PORT_1G_RGMII_FIBER << 8) | 413 (NXGE_PORT_1G_RGMII_FIBER << 12)), 414 415 NEPTUNE_2_10GF_2_1GRF = 416 (NXGE_PORT_10G_FIBRE | 417 (NXGE_PORT_10G_FIBRE << 4) | 418 (NXGE_PORT_1G_RGMII_FIBER << 8) | 419 (NXGE_PORT_1G_RGMII_FIBER << 12)), 420 421 N2_NIU = 422 (NXGE_PORT_RSVD | 423 (NXGE_PORT_RSVD << 4) | 424 (NXGE_PORT_RSVD << 8) | 425 (NXGE_PORT_RSVD << 12)) 426 427 } niu_type_t; 428 429 /* 430 * P_NEPTUNE_GENERIC: 431 * The cover-all case for Neptune (as opposed to NIU) where we do not 432 * care the exact platform as we do not do anything that is platform 433 * specific. 434 * P_NEPTUNE_ATLAS_2PORT: 435 * Dual Port Fiber Neptune based NIC (2XGF) 436 * P_NEPTUNE_ATLAS_4PORT: 437 * Quad Port Copper Neptune based NIC (QGC) 438 * P_NEPTUNE_NIU: 439 * This is NIU. Could be Huron, Glendale, Monza or any other NIU based 440 * platform. 441 */ 442 typedef enum { 443 P_NEPTUNE_NONE, 444 P_NEPTUNE_GENERIC, 445 P_NEPTUNE_ATLAS_2PORT, 446 P_NEPTUNE_ATLAS_4PORT, 447 P_NEPTUNE_MARAMBA_P0, 448 P_NEPTUNE_MARAMBA_P1, 449 P_NEPTUNE_ALONSO, 450 P_NEPTUNE_ROCK, 451 P_NEPTUNE_NIU 452 } platform_type_t; 453 454 #define NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \ 455 (((nxgep->platform_type) == P_NEPTUNE_ATLAS_2PORT) || \ 456 ((nxgep->platform_type) == P_NEPTUNE_ATLAS_4PORT) || \ 457 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 458 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1) || \ 459 ((nxgep->platform_type) == P_NEPTUNE_GENERIC) || \ 460 ((nxgep->platform_type) == P_NEPTUNE_ALONSO) || \ 461 ((nxgep->platform_type) == P_NEPTUNE_ROCK)) 462 463 #define NXGE_IS_XAUI_PLATFORM(nxgep) \ 464 (((nxgep->platform_type) == P_NEPTUNE_NIU) || \ 465 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \ 466 ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1)) 467 468 469 typedef enum { 470 CFG_DEFAULT = 0, /* default cfg */ 471 CFG_EQUAL, /* Equal */ 472 CFG_FAIR, /* Equal */ 473 CFG_CLASSIFY, 474 CFG_L2_CLASSIFY, 475 CFG_L3_CLASSIFY, 476 CFG_L3_DISTRIBUTE, 477 CFG_L3_WEB, 478 CFG_L3_TCAM, 479 CFG_NOT_SPECIFIED, 480 CFG_CUSTOM /* Custom */ 481 } cfg_type_t; 482 483 typedef enum { 484 NO_MSG = 0x0, /* No message output or storage. */ 485 CONSOLE = 0x1, /* Messages are go to the console. */ 486 BUFFER = 0x2, /* Messages are go to the system buffer. */ 487 CON_BUF = 0x3, /* Messages are go to the console and */ 488 /* system buffer. */ 489 VERBOSE = 0x4 /* Messages are go out only in VERBOSE node. */ 490 } out_msg_t, *p_out_msg_t; 491 492 typedef enum { 493 DBG_NO_MSG = 0x0, /* No message output or storage. */ 494 DBG_CONSOLE = 0x1, /* Messages are go to the console. */ 495 DBG_BUFFER = 0x2, /* Messages are go to the system buffer. */ 496 DBG_CON_BUF = 0x3, /* Messages are go to the console and */ 497 /* system buffer. */ 498 STR_LOG = 4 /* Sessage sent to streams logging driver. */ 499 } out_dbgmsg_t, *p_out_dbgmsg_t; 500 501 typedef enum { 502 DDI_MEM_ALLOC, /* default (use ddi_dma_mem_alloc) */ 503 KMEM_ALLOC, /* use kmem_alloc(). */ 504 CONTIG_MEM_ALLOC /* use contig_mem_alloc() (N2/NIU only) */ 505 } buf_alloc_type_t; 506 507 #define BUF_ALLOCATED 0x00000001 508 #define BUF_ALLOCATED_WAIT_FREE 0x00000002 509 510 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 511 typedef struct ether_header ether_header_t, *p_ether_header_t; 512 typedef queue_t *p_queue_t; 513 typedef mblk_t *p_mblk_t; 514 515 /* 516 * Generic phy table to support different phy types. 517 * 518 * The argument for check_link is nxgep, which is passed to check_link 519 * as an argument to the timer routine. 520 */ 521 typedef struct _nxge_xcvr_table { 522 nxge_status_t (*serdes_init) (); /* Serdes init routine */ 523 nxge_status_t (*xcvr_init) (); /* xcvr init routine */ 524 nxge_status_t (*link_intr_stop) (); /* Link intr disable routine */ 525 nxge_status_t (*link_intr_start) (); /* Link intr enable routine */ 526 nxge_status_t (*check_link) (); /* Link check routine */ 527 528 uint32_t xcvr_inuse; 529 } nxge_xcvr_table_t, *p_nxge_xcvr_table_t; 530 531 /* 532 * Common DMA data elements. 533 */ 534 typedef struct _nxge_dma_pool_t nxge_dma_pool_t, *p_nxge_dma_pool_t; 535 536 struct _nxge_dma_common_t { 537 uint16_t dma_channel; 538 void *kaddrp; 539 void *last_kaddrp; 540 void *ioaddr_pp; 541 void *first_ioaddr_pp; 542 void *last_ioaddr_pp; 543 ddi_dma_cookie_t dma_cookie; 544 uint32_t ncookies; 545 546 ddi_dma_handle_t dma_handle; 547 nxge_os_acc_handle_t acc_handle; 548 npi_handle_t npi_handle; 549 550 size_t block_size; 551 uint32_t nblocks; 552 size_t alength; 553 uint_t offset; 554 uint_t dma_chunk_index; 555 void *orig_ioaddr_pp; 556 uint64_t orig_vatopa; 557 void *orig_kaddrp; 558 size_t orig_alength; 559 boolean_t contig_alloc_type; 560 /* 561 * Receive buffers may be allocated using 562 * kmem_alloc(). The buffer free function 563 * depends on its allocation function. 564 */ 565 boolean_t kmem_alloc_type; 566 uint32_t buf_alloc_state; 567 buf_alloc_type_t buf_alloc_type; 568 p_nxge_dma_pool_t rx_buf_pool_p; 569 }; 570 571 typedef struct _nxge_t nxge_t, *p_nxge_t; 572 typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t; 573 574 struct _nxge_dma_pool_t { 575 p_nxge_dma_common_t *dma_buf_pool_p; 576 uint32_t ndmas; 577 uint32_t *num_chunks; 578 boolean_t buf_allocated; 579 }; 580 581 /* 582 * Each logical device (69): 583 * - LDG # 584 * - flag bits 585 * - masks. 586 * - interrupt handler function. 587 * 588 * Generic system interrupt handler with two arguments: 589 * (nxge_sys_intr_t) 590 * Per device instance data structure 591 * Logical group data structure. 592 * 593 * Logical device interrupt handler with two arguments: 594 * (nxge_ldv_intr_t) 595 * Per device instance data structure 596 * Logical device number 597 */ 598 typedef struct _nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t; 599 typedef struct _nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t; 600 typedef uint_t (*nxge_sys_intr_t)(void *arg1, void *arg2); 601 typedef uint_t (*nxge_ldv_intr_t)(void *arg1, void *arg2); 602 603 /* 604 * Each logical device Group (64) needs to have the following 605 * configurations: 606 * - timer counter (6 bits) 607 * - timer resolution (20 bits, number of system clocks) 608 * - system data (7 bits) 609 */ 610 struct _nxge_ldg_t { 611 uint8_t ldg; /* logical group number */ 612 uint8_t vldg_index; 613 boolean_t arm; 614 boolean_t interrupted; 615 uint16_t ldg_timer; /* counter */ 616 uint8_t func; 617 uint8_t vector; 618 uint8_t intdata; 619 uint8_t nldvs; 620 p_nxge_ldv_t ldvp; 621 nxge_sys_intr_t sys_intr_handler; 622 p_nxge_t nxgep; 623 }; 624 625 struct _nxge_ldv_t { 626 uint8_t ldg_assigned; 627 uint8_t ldv; 628 boolean_t is_rxdma; 629 boolean_t is_txdma; 630 boolean_t is_mif; 631 boolean_t is_mac; 632 boolean_t is_syserr; 633 boolean_t use_timer; 634 uint8_t channel; 635 uint8_t vdma_index; 636 uint8_t func; 637 p_nxge_ldg_t ldgp; 638 uint8_t ldv_flags; 639 uint8_t ldv_ldf_masks; 640 nxge_ldv_intr_t ldv_intr_handler; 641 p_nxge_t nxgep; 642 }; 643 644 typedef struct _nxge_logical_page_t { 645 uint16_t dma; 646 uint16_t page; 647 boolean_t valid; 648 uint64_t mask; 649 uint64_t value; 650 uint64_t reloc; 651 uint32_t handle; 652 } nxge_logical_page_t, *p_nxge_logical_page_t; 653 654 /* 655 * (Internal) return values from ioctl subroutines. 656 */ 657 enum nxge_ioc_reply { 658 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 659 IOC_DONE, /* OK, reply sent */ 660 IOC_ACK, /* OK, just send ACK */ 661 IOC_REPLY, /* OK, just send reply */ 662 IOC_RESTART_ACK, /* OK, restart & ACK */ 663 IOC_RESTART_REPLY /* OK, restart & reply */ 664 }; 665 666 typedef struct _pci_cfg_t { 667 uint16_t vendorid; 668 uint16_t devid; 669 uint16_t command; 670 uint16_t status; 671 uint8_t revid; 672 uint8_t res0; 673 uint16_t junk1; 674 uint8_t cache_line; 675 uint8_t latency; 676 uint8_t header; 677 uint8_t bist; 678 uint32_t base; 679 uint32_t base14; 680 uint32_t base18; 681 uint32_t base1c; 682 uint32_t base20; 683 uint32_t base24; 684 uint32_t base28; 685 uint32_t base2c; 686 uint32_t base30; 687 uint32_t res1[2]; 688 uint8_t int_line; 689 uint8_t int_pin; 690 uint8_t min_gnt; 691 uint8_t max_lat; 692 } pci_cfg_t, *p_pci_cfg_t; 693 694 typedef struct _dev_regs_t { 695 nxge_os_acc_handle_t nxge_pciregh; /* PCI config DDI IO handle */ 696 p_pci_cfg_t nxge_pciregp; /* mapped PCI registers */ 697 698 nxge_os_acc_handle_t nxge_regh; /* device DDI IO (BAR 0) */ 699 void *nxge_regp; /* mapped device registers */ 700 701 nxge_os_acc_handle_t nxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 702 void *nxge_msix_regp; /* MSI/X register */ 703 704 nxge_os_acc_handle_t nxge_vir_regh; /* virtualization (BAR 4) */ 705 unsigned char *nxge_vir_regp; /* virtualization register */ 706 707 nxge_os_acc_handle_t nxge_vir2_regh; /* second virtualization */ 708 unsigned char *nxge_vir2_regp; /* second virtualization */ 709 710 nxge_os_acc_handle_t nxge_romh; /* fcode rom handle */ 711 unsigned char *nxge_romp; /* fcode pointer */ 712 } dev_regs_t, *p_dev_regs_t; 713 714 715 typedef struct _nxge_mac_addr_t { 716 ether_addr_t addr; 717 uint_t flags; 718 } nxge_mac_addr_t; 719 720 /* 721 * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac) 722 * for each XMAC port and supports 1 unique MAC and 7 alternate MACs 723 * for each BMAC port. The number of MACs assigned by the factory is 724 * different and is as follows, 725 * BMAC port: num_factory_mmac = num_mmac = 7 726 * XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15 727 * XMAC port on a 4-port NIC: num_factory_mmac = 7 728 * So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses 729 * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac. 730 * 731 * total_factory_macs is the total number of factory MACs, including 732 * the unique MAC, assigned to a Neptune based NIC card, it is 32. 733 */ 734 typedef struct _nxge_mmac_t { 735 uint8_t total_factory_macs; 736 uint8_t num_mmac; 737 uint8_t num_factory_mmac; 738 nxge_mac_addr_t mac_pool[XMAC_MAX_ADDR_ENTRY]; 739 ether_addr_t factory_mac_pool[XMAC_MAX_ADDR_ENTRY]; 740 uint8_t naddrfree; /* number of alt mac addr available */ 741 } nxge_mmac_t; 742 743 /* 744 * mmac stats structure 745 */ 746 typedef struct _nxge_mmac_stats_t { 747 uint8_t mmac_max_cnt; 748 uint8_t mmac_avail_cnt; 749 struct ether_addr mmac_avail_pool[16]; 750 } nxge_mmac_stats_t, *p_nxge_mmac_stats_t; 751 752 #define NXGE_MAX_MMAC_ADDRS 32 753 #define NXGE_NUM_MMAC_ADDRS 8 754 #define NXGE_NUM_OF_PORTS_QUAD 4 755 #define NXGE_NUM_OF_PORTS_DUAL 2 756 757 #define NXGE_QGC_LP_BM_STR "501-7606" 758 #define NXGE_2XGF_LP_BM_STR "501-7283" 759 #define NXGE_QGC_PEM_BM_STR "501-7765" 760 #define NXGE_2XGF_PEM_BM_STR "501-7626" 761 #define NXGE_ALONSO_BM_STR "373-0202-01" 762 #define NXGE_ALONSO_MODEL_STR "SUNW,CP3220" 763 #define NXGE_RFEM_BM_STR "501-7961-01" 764 #define NXGE_RFEM_MODEL_STR "SUNW,pcie-rfem" 765 #define NXGE_ARTM_BM_STR "375-3544-01" 766 #define NXGE_ARTM_MODEL_STR "SUNW,pcie-artm" 767 /* ROCK OBP creates a compatible property for ROCK */ 768 #define NXGE_ROCK_COMPATIBLE "SUNW,rock-pciex108e,abcd" 769 #define NXGE_EROM_LEN 1048576 770 771 #include <sys/nxge/nxge_common_impl.h> 772 #include <sys/nxge/nxge_common.h> 773 #include <sys/nxge/nxge_txc.h> 774 #include <sys/nxge/nxge_rxdma.h> 775 #include <sys/nxge/nxge_txdma.h> 776 #include <sys/nxge/nxge_fflp.h> 777 #include <sys/nxge/nxge_ipp.h> 778 #include <sys/nxge/nxge_zcp.h> 779 #include <sys/nxge/nxge_fzc.h> 780 #include <sys/nxge/nxge_flow.h> 781 #include <sys/nxge/nxge_virtual.h> 782 783 #include <npi_espc.h> 784 #include <npi_vir.h> 785 786 #include <sys/nxge/nxge.h> 787 788 #include <sys/modctl.h> 789 #include <sys/pattr.h> 790 791 extern int secpolicy_net_config(const cred_t *, boolean_t); 792 extern void nxge_fm_report_error(p_nxge_t, uint8_t, 793 uint8_t, nxge_fm_ereport_id_t); 794 extern int fm_check_acc_handle(ddi_acc_handle_t); 795 extern int fm_check_dma_handle(ddi_dma_handle_t); 796 797 /* nxge_classify.c */ 798 nxge_status_t nxge_classify_init(p_nxge_t); 799 nxge_status_t nxge_classify_uninit(p_nxge_t); 800 nxge_status_t nxge_set_hw_classify_config(p_nxge_t); 801 nxge_status_t nxge_classify_exit_sw(p_nxge_t); 802 803 /* nxge_fflp.c */ 804 void nxge_put_tcam(p_nxge_t, p_mblk_t); 805 void nxge_get_tcam(p_nxge_t, p_mblk_t); 806 nxge_status_t nxge_classify_init_hw(p_nxge_t); 807 nxge_status_t nxge_classify_init_sw(p_nxge_t); 808 nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t); 809 nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t, 810 uint32_t); 811 812 nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t, 813 tcam_class_t, 814 uint32_t *); 815 816 nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t, 817 uint32_t); 818 819 nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t, 820 uint32_t); 821 822 uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t); 823 nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *); 824 nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t); 825 nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t); 826 827 nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t); 828 nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t); 829 830 nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t); 831 nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t); 832 833 nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t); 834 nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t); 835 836 nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t); 837 838 nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t); 839 840 nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t); 841 842 void nxge_handle_tcam_fragment_bug(p_nxge_t); 843 nxge_status_t nxge_fflp_hw_reset(p_nxge_t); 844 nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t); 845 nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t); 846 847 /* nxge_kstats.c */ 848 void nxge_init_statsp(p_nxge_t); 849 void nxge_setup_kstats(p_nxge_t); 850 void nxge_setup_rdc_kstats(p_nxge_t, int); 851 void nxge_setup_tdc_kstats(p_nxge_t, int); 852 void nxge_destroy_kstats(p_nxge_t); 853 int nxge_port_kstat_update(kstat_t *, int); 854 void nxge_save_cntrs(p_nxge_t); 855 856 int nxge_m_stat(void *arg, uint_t, uint64_t *); 857 858 /* nxge_hw.c */ 859 void 860 nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 861 void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 862 nxge_status_t nxge_global_reset(p_nxge_t); 863 uint_t nxge_intr(void *, void *); 864 void nxge_intr_enable(p_nxge_t); 865 void nxge_intr_disable(p_nxge_t); 866 void nxge_hw_blank(void *arg, time_t, uint_t); 867 void nxge_hw_id_init(p_nxge_t); 868 void nxge_hw_init_niu_common(p_nxge_t); 869 void nxge_intr_hw_enable(p_nxge_t); 870 void nxge_intr_hw_disable(p_nxge_t); 871 void nxge_hw_stop(p_nxge_t); 872 void nxge_check_hw_state(p_nxge_t); 873 874 void nxge_rxdma_channel_put64(nxge_os_acc_handle_t, 875 void *, uint32_t, uint16_t, 876 uint64_t); 877 uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *, 878 uint32_t, uint16_t); 879 880 881 void nxge_get32(p_nxge_t, p_mblk_t); 882 void nxge_put32(p_nxge_t, p_mblk_t); 883 884 void nxge_hw_set_mac_modes(p_nxge_t); 885 886 /* nxge_send.c. */ 887 uint_t nxge_reschedule(caddr_t); 888 889 /* nxge_rxdma.c */ 890 nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t, 891 uint8_t, uint8_t); 892 893 nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t, 894 uint8_t, uint8_t); 895 nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t, 896 uint16_t); 897 nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t, 898 uint16_t, uint8_t); 899 900 /* nxge_ndd.c */ 901 void nxge_get_param_soft_properties(p_nxge_t); 902 void nxge_copy_hw_default_to_param(p_nxge_t); 903 void nxge_copy_param_hw_to_config(p_nxge_t); 904 void nxge_setup_param(p_nxge_t); 905 void nxge_init_param(p_nxge_t); 906 void nxge_destroy_param(p_nxge_t); 907 boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t); 908 boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t); 909 boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t); 910 911 boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t); 912 913 int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t); 914 int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 915 int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 916 int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t); 917 int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 918 int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t); 919 long nxge_strtol(char *, char **, int); 920 boolean_t nxge_param_get_instance(queue_t *, mblk_t *); 921 void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 922 boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 923 void nxge_nd_free(caddr_t *); 924 int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t); 925 926 nxge_status_t nxge_set_lb_normal(p_nxge_t); 927 boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t); 928 boolean_t nxge_param_link_update(p_nxge_t); 929 int nxge_param_set_ip_opt(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t); 930 int nxge_dld_get_ip_opt(p_nxge_t, caddr_t); 931 int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 932 mblk_t *, char *, caddr_t); 933 int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 934 mblk_t *, char *, caddr_t); 935 936 937 /* nxge_virtual.c */ 938 nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *); 939 void nxge_common_lock_get(p_nxge_t); 940 void nxge_common_lock_free(p_nxge_t); 941 942 nxge_status_t nxge_get_config_properties(p_nxge_t); 943 void nxge_get_xcvr_properties(p_nxge_t); 944 void nxge_init_vlan_config(p_nxge_t); 945 void nxge_init_mac_config(p_nxge_t); 946 947 948 void nxge_init_logical_devs(p_nxge_t); 949 int nxge_init_ldg_intrs(p_nxge_t); 950 951 void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t, 952 uint32_t); 953 954 void nxge_init_fzc_txdma_channels(p_nxge_t); 955 956 nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t, 957 p_tx_ring_t, p_tx_mbox_t); 958 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 959 960 nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t); 961 962 nxge_status_t nxge_init_fzc_rx_common(p_nxge_t); 963 nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t); 964 965 nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t, 966 uint16_t, p_rx_rbr_ring_t); 967 nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t, 968 uint16_t, p_rx_rcr_ring_t); 969 970 nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t, 971 uint16_t, p_rx_rbr_ring_t); 972 973 974 nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t, 975 uint16_t, p_tx_ring_t); 976 977 nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t, 978 p_tx_ring_t); 979 980 nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t); 981 982 void nxge_init_fzc_ldg_num(p_nxge_t); 983 void nxge_init_fzc_sys_int_data(p_nxge_t); 984 void nxge_init_fzc_ldg_int_timer(p_nxge_t); 985 nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on); 986 987 /* MAC functions */ 988 nxge_status_t nxge_mac_init(p_nxge_t); 989 nxge_status_t nxge_link_init(p_nxge_t); 990 nxge_status_t nxge_xif_init(p_nxge_t); 991 nxge_status_t nxge_pcs_init(p_nxge_t); 992 nxge_status_t nxge_mac_ctrl_init(p_nxge_t); 993 nxge_status_t nxge_serdes_init(p_nxge_t); 994 nxge_status_t nxge_serdes_reset(p_nxge_t); 995 nxge_status_t nxge_xcvr_find(p_nxge_t); 996 nxge_status_t nxge_get_xcvr_type(p_nxge_t); 997 nxge_status_t nxge_setup_xcvr_table(p_nxge_t); 998 nxge_status_t nxge_xcvr_init(p_nxge_t); 999 nxge_status_t nxge_tx_mac_init(p_nxge_t); 1000 nxge_status_t nxge_rx_mac_init(p_nxge_t); 1001 nxge_status_t nxge_tx_mac_enable(p_nxge_t); 1002 nxge_status_t nxge_tx_mac_disable(p_nxge_t); 1003 nxge_status_t nxge_rx_mac_enable(p_nxge_t); 1004 nxge_status_t nxge_rx_mac_disable(p_nxge_t); 1005 nxge_status_t nxge_tx_mac_reset(p_nxge_t); 1006 nxge_status_t nxge_rx_mac_reset(p_nxge_t); 1007 nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t); 1008 nxge_status_t nxge_mii_xcvr_init(p_nxge_t); 1009 nxge_status_t nxge_mii_xcvr_fiber_init(p_nxge_t); 1010 nxge_status_t nxge_mii_read(p_nxge_t, uint8_t, 1011 uint8_t, uint16_t *); 1012 nxge_status_t nxge_mii_write(p_nxge_t, uint8_t, 1013 uint8_t, uint16_t); 1014 nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t, 1015 uint16_t, uint16_t *); 1016 nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t, 1017 uint8_t, uint16_t, uint16_t); 1018 nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t, 1019 mii_bmsr_t, nxge_link_state_t *); 1020 void nxge_pcs_check(p_nxge_t, uint8_t portn, nxge_link_state_t *); 1021 nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *); 1022 nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *); 1023 nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *); 1024 nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *); 1025 nxge_status_t nxge_check_tn1010_link(p_nxge_t); 1026 void nxge_link_is_down(p_nxge_t); 1027 void nxge_link_is_up(p_nxge_t); 1028 nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t); 1029 uint32_t crc32_mchash(p_ether_addr_t); 1030 nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t); 1031 nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t); 1032 nxge_status_t nxge_10g_link_led_on(p_nxge_t); 1033 nxge_status_t nxge_10g_link_led_off(p_nxge_t); 1034 nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t); 1035 boolean_t nxge_is_valid_local_mac(ether_addr_st); 1036 nxge_status_t nxge_mac_set_framesize(p_nxge_t); 1037 1038 /* espc (sprom) prototypes */ 1039 nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t); 1040 nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *); 1041 nxge_status_t nxge_espc_num_ports_get(p_nxge_t); 1042 nxge_status_t nxge_espc_phy_type_get(p_nxge_t); 1043 nxge_status_t nxge_espc_verify_chksum(p_nxge_t); 1044 void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *); 1045 void nxge_vpd_info_get(p_nxge_t); 1046 1047 1048 void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...); 1049 int nxge_get_nports(p_nxge_t); 1050 1051 void nxge_free_buf(buf_alloc_type_t, uint64_t, uint32_t); 1052 1053 uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t, 1054 uint64_t, uint64_t); 1055 #pragma weak hv_niu_rx_logical_page_conf 1056 1057 uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t, 1058 uint64_t *, uint64_t *); 1059 #pragma weak hv_niu_rx_logical_page_info 1060 1061 uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t, 1062 uint64_t, uint64_t); 1063 #pragma weak hv_niu_tx_logical_page_conf 1064 1065 uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t, 1066 uint64_t *, uint64_t *); 1067 #pragma weak hv_niu_tx_logical_page_info 1068 1069 uint64_t hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie); 1070 #pragma weak hv_niu_vr_assign 1071 1072 uint64_t hv_niu_vr_unassign(uint32_t cookie); 1073 #pragma weak hv_niu_vr_unassign 1074 1075 uint64_t hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, 1076 uint64_t *size); 1077 #pragma weak hv_niu_vr_getinfo 1078 1079 uint64_t hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map); 1080 #pragma weak hv_niu_vr_get_rxmap 1081 1082 uint64_t hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map); 1083 #pragma weak hv_niu_vr_get_txmap 1084 1085 uint64_t hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, 1086 uint64_t *vchidx); 1087 #pragma weak hv_niu_rx_dma_assign 1088 1089 uint64_t hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t chidx); 1090 #pragma weak hv_niu_rx_dma_unassign 1091 1092 uint64_t hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, 1093 uint64_t *vchidx); 1094 #pragma weak hv_niu_tx_dma_assign 1095 1096 uint64_t hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx); 1097 #pragma weak hv_niu_tx_dma_unassign 1098 1099 uint64_t hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, 1100 uint64_t pgidx, uint64_t raddr, uint64_t size); 1101 #pragma weak hv_niu_vrrx_logical_page_conf 1102 1103 uint64_t hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, 1104 uint64_t pgidx, uint64_t *raddr, uint64_t *size); 1105 #pragma weak hv_niu_vrrx_logical_page_info 1106 1107 uint64_t hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, 1108 uint64_t pgidx, uint64_t raddr, uint64_t size); 1109 #pragma weak hv_niu_vrtx_logical_page_conf 1110 1111 uint64_t hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, 1112 uint64_t pgidx, uint64_t *raddr, uint64_t *size); 1113 #pragma weak hv_niu_vrtx_logical_page_info 1114 1115 // 1116 // NIU-specific interrupt API 1117 // 1118 uint64_t hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t v_chidx, 1119 uint64_t *group, uint64_t *logdev); 1120 #pragma weak hv_niu_vrrx_getinfo 1121 1122 uint64_t hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t v_chidx, 1123 uint64_t *group, uint64_t *logdev); 1124 #pragma weak hv_niu_vrtx_getinfo 1125 1126 uint64_t hv_niu_vrrx_to_logical_dev(uint32_t cookie, uint64_t v_chidx, 1127 uint64_t *ldn); 1128 #pragma weak hv_niu_vrrx_to_logical_dev 1129 1130 uint64_t hv_niu_vrtx_to_logical_dev(uint32_t cookie, uint64_t v_chidx, 1131 uint64_t *ldn); 1132 #pragma weak hv_niu_vrtx_to_logical_dev 1133 1134 #ifdef NXGE_DEBUG 1135 char *nxge_dump_packet(char *, int); 1136 #endif 1137 1138 #endif /* !_ASM */ 1139 1140 #ifdef __cplusplus 1141 } 1142 #endif 1143 1144 #endif /* _SYS_NXGE_NXGE_IMPL_H */ 1145