1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_DEFS_H 27 #define _SYS_NXGE_NXGE_DEFS_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * Block Address Assignment (24-bit base address) 35 * (bits [23:20]: block [19]: set to 1 for FZC ) 36 */ 37 #define PIO 0x000000 38 #define FZC_PIO 0x080000 39 #define RESERVED_1 0x100000 40 #define FZC_MAC 0x180000 41 #define RESERVED_2 0x200000 42 #define FZC_IPP 0x280000 43 #define FFLP 0x300000 44 #define FZC_FFLP 0x380000 45 #define PIO_VADDR 0x400000 46 #define RESERVED_3 0x480000 47 #define ZCP 0x500000 48 #define FZC_ZCP 0x580000 49 #define DMC 0x600000 50 #define FZC_DMC 0x680000 51 #define TXC 0x700000 52 #define FZC_TXC 0x780000 53 #define PIO_LDSV 0x800000 54 #define RESERVED_4 0x880000 55 #define PIO_LDGIM 0x900000 56 #define RESERVED_5 0x980000 57 #define PIO_IMASK0 0xa00000 58 #define RESERVED_6 0xa80000 59 #define PIO_IMASK1 0xb00000 60 #define RESERVED_7_START 0xb80000 61 #define RESERVED_7_END 0xc00000 62 #define FZC_PROM 0xc80000 63 #define RESERVED_8 0xd00000 64 #define FZC_PIM 0xd80000 65 #define RESERVED_9_START 0xe00000 66 #define RESERVED_9_END 0xf80000 67 68 /* PIO (0x000000) */ 69 70 71 /* FZC_PIO (0x080000) */ 72 #define LDGITMRES (FZC_PIO + 0x00008) /* timer resolution */ 73 #define SID (FZC_PIO + 0x10200) /* 64 LDG, INT data */ 74 #define LDG_NUM (FZC_PIO + 0x20000) /* 69 LDs */ 75 76 77 78 /* FZC_IPP (0x280000) */ 79 80 81 /* FFLP (0x300000), Header Parser */ 82 83 /* PIO_VADDR (0x400000), PIO Virtaul DMA Address */ 84 /* ?? how to access DMA via PIO_VADDR? */ 85 #define VADDR (PIO_VADDR + 0x00000) /* ?? not for driver */ 86 87 88 /* ZCP (0x500000), Neptune Only */ 89 90 91 /* FZC_ZCP (0x580000), Neptune Only */ 92 93 94 /* DMC (0x600000), register offset (32 DMA channels) */ 95 96 /* Transmit Ring Register Offset (32 Channels) */ 97 #define TX_RNG_CFIG (DMC + 0x40000) 98 #define TX_RING_HDH (DMC + 0x40008) 99 #define TX_RING_HDL (DMC + 0x40010) 100 #define TX_RING_KICK (DMC + 0x40018) 101 /* Transmit Operations (32 Channels) */ 102 #define TX_ENT_MSK (DMC + 0x40020) 103 #define TX_CS (DMC + 0x40028) 104 #define TXDMA_MBH (DMC + 0x40030) 105 #define TXDMA_MBL (DMC + 0x40038) 106 #define TX_DMA_PRE_ST (DMC + 0x40040) 107 #define TX_RNG_ERR_LOGH (DMC + 0x40048) 108 #define TX_RNG_ERR_LOGL (DMC + 0x40050) 109 #if OLD 110 #define SH_TX_RNG_ERR_LOGH (DMC + 0x40058) 111 #define SH_TX_RNG_ERR_LOGL (DMC + 0x40060) 112 #endif 113 114 /* FZC_DMC RED Initial Random Value register offset (global) */ 115 #define RED_RAN_INIT (FZC_DMC + 0x00068) 116 117 #define RX_ADDR_MD (FZC_DMC + 0x00070) 118 119 /* FZC_DMC Ethernet Timeout Countue register offset (global) */ 120 #define EING_TIMEOUT (FZC_DMC + 0x00078) 121 122 /* RDC Table */ 123 #define RDC_TBL (FZC_DMC + 0x10000) /* 256 * 8 */ 124 125 /* FZC_DMC partitioning support register offset (32 channels) */ 126 127 #define TX_LOG_PAGE_VLD (FZC_DMC + 0x40000) 128 #define TX_LOG_MASK1 (FZC_DMC + 0x40008) 129 #define TX_LOG_VAL1 (FZC_DMC + 0x40010) 130 #define TX_LOG_MASK2 (FZC_DMC + 0x40018) 131 #define TX_LOG_VAL2 (FZC_DMC + 0x40020) 132 #define TX_LOG_PAGE_RELO1 (FZC_DMC + 0x40028) 133 #define TX_LOG_PAGE_RELO2 (FZC_DMC + 0x40030) 134 #define TX_LOG_PAGE_HDL (FZC_DMC + 0x40038) 135 136 #define TX_ADDR_MOD (FZC_DMC + 0x41000) /* only one? */ 137 138 139 /* FZC_DMC RED Parameters register offset (32 channels) */ 140 #define RDC_RED_PARA1 (FZC_DMC + 0x30000) 141 #define RDC_RED_PARA2 (FZC_DMC + 0x30008) 142 /* FZC_DMC RED Discard Cound Register offset (32 channels) */ 143 #define RED_DIS_CNT (FZC_DMC + 0x30010) 144 145 #if OLD /* This has been moved to TXC */ 146 /* Transmit Ring Scheduler (per port) */ 147 #define TX_DMA_MAP0 (FZC_DMC + 0x50000) 148 #define TX_DMA_MAP1 (FZC_DMC + 0x50008) 149 #define TX_DMA_MAP2 (FZC_DMC + 0x50010) 150 #define TX_DMA_MAP3 (FZC_DMC + 0x50018) 151 #endif 152 153 /* Transmit Ring Scheduler: DRR Weight (32 Channels) */ 154 #define DRR_WT (FZC_DMC + 0x51000) 155 #if OLD 156 #define TXRNG_USE (FZC_DMC + 0x51008) 157 #endif 158 159 /* TXC (0x700000)?? */ 160 161 162 /* FZC_TXC (0x780000)?? */ 163 164 165 /* 166 * PIO_LDSV (0x800000) 167 * Logical Device State Vector 0, 1, 2. 168 * (69 logical devices, 8192 apart, partitioning control) 169 */ 170 #define LDSV0 (PIO_LDSV + 0x00000) /* RO (64 - 69) */ 171 #define LDSV1 (PIO_LDSV + 0x00008) /* RO (32 - 63) */ 172 #define LDSV2 (PIO_LDSV + 0x00010) /* RO ( 0 - 31) */ 173 174 /* 175 * PIO_LDGIM (0x900000) 176 * Logical Device Group Interrupt Management (64 groups). 177 * (count 64, step 8192) 178 */ 179 #define LDGIMGN (PIO_LDGIMGN + 0x00000) /* RW */ 180 181 /* 182 * PIO_IMASK0 (0xA000000) 183 * 184 * Logical Device Masks 0, 1. 185 * (64 logical devices, 8192 apart, partitioning control) 186 */ 187 #define LD_IM0 (PIO_IMASK0 + 0x00000) /* RW ( 0 - 63) */ 188 189 /* 190 * PIO_IMASK0 (0xB000000) 191 * 192 * Logical Device Masks 0, 1. 193 * (5 logical devices, 8192 apart, partitioning control) 194 */ 195 #define LD_IM1 (PIO_IMASK1 + 0x00000) /* RW (64 - 69) */ 196 197 198 /* DMC/TMC CSR size */ 199 #define DMA_CSR_SLL 9 /* Used to calculate VR addresses */ 200 #define DMA_CSR_SIZE (1 << DMA_CSR_SLL) /* 512 */ 201 #define DMA_CSR_MASK 0xff /* Used to calculate VR addresses */ 202 /* 203 * That is, each DMA CSR set must fit into a 512 byte space. 204 * If you subtract DMC (0x60000) from each DMA register definition, 205 * what you have left over is currently less than 255 (0xff) 206 */ 207 #define DMA_CSR_MIN_PAGE_SIZE (2 * DMA_CSR_SIZE) /* 1024 */ 208 /* 209 * There are 2 subpages per page in a VR. 210 */ 211 #define VDMA_CSR_SIZE (8 * DMA_CSR_MIN_PAGE_SIZE) /* 0x2000 */ 212 /* 213 * There are 8 pages in a VR. 214 */ 215 216 /* 217 * Define the Default RBR, RCR 218 */ 219 #define RBR_DEFAULT_MAX_BLKS 8192 /* each entry (16 blockaddr/64B) */ 220 #define RBR_NBLK_PER_LINE 16 /* 16 block addresses per 64 B line */ 221 #define RBR_DEFAULT_MAX_LEN (RBR_DEFAULT_MAX_BLKS) 222 #define RBR_DEFAULT_MIN_LEN 1 223 #define RCR_DEFAULT_MAX 8192 224 225 #define SW_OFFSET_NO_OFFSET 0 226 #define SW_OFFSET_64 1 /* 64 bytes */ 227 #define SW_OFFSET_128 2 /* 128 bytes */ 228 #define SW_OFFSET_INVALID 3 229 230 #define TDC_DEFAULT_MAX 8192 231 /* 232 * RBR block descriptor is 32 bits (bits [43:12] 233 */ 234 #define RBR_BKADDR_SHIFT 12 235 236 237 #define RCR_DEFAULT_MAX_BLKS 4096 /* each entry (8 blockaddr/64B) */ 238 #define RCR_NBLK_PER_LINE 8 /* 8 block addresses per 64 B line */ 239 #define RCR_DEFAULT_MAX_LEN (RCR_DEFAULT_MAX_BLKS) 240 #define RCR_DEFAULT_MIN_LEN 1 241 242 /* DMA Channels. */ 243 #define NXGE_MAX_DMCS (NXGE_MAX_RDCS + NXGE_MAX_TDCS) 244 #define NXGE_MAX_RDCS 16 245 #define NXGE_MAX_TDCS 24 246 #define NXGE_MAX_TDCS_NIU 16 247 /* 248 * original mapping from Hypervisor 249 */ 250 #ifdef ORIGINAL 251 #define NXGE_N2_RXDMA_START_LDG 0 252 #define NXGE_N2_TXDMA_START_LDG 16 253 #define NXGE_N2_MIF_LDG 32 254 #define NXGE_N2_MAC_0_LDG 33 255 #define NXGE_N2_MAC_1_LDG 34 256 #define NXGE_N2_SYS_ERROR_LDG 35 257 #endif 258 259 #define NXGE_N2_RXDMA_START_LDG 19 260 #define NXGE_N2_TXDMA_START_LDG 27 261 #define NXGE_N2_MIF_LDG 17 262 #define NXGE_N2_MAC_0_LDG 16 263 #define NXGE_N2_MAC_1_LDG 35 264 #define NXGE_N2_SYS_ERROR_LDG 18 265 #define NXGE_N2_LDG_GAP 17 266 267 #define NXGE_MAX_RDC_GRPS 8 268 269 /* 270 * Max. ports per Neptune and NIU 271 */ 272 #define NXGE_MAX_PORTS 4 273 #define NXGE_PORTS_NEPTUNE 4 274 #define NXGE_PORTS_NIU 2 275 276 /* 277 * Virtualization Regions. 278 */ 279 #define NXGE_MAX_VRS 8 280 281 /* Max. RDC table groups */ 282 #define NXGE_MAX_RDC_GROUPS 8 283 #define NXGE_MAX_RDCS 16 284 #define NXGE_MAX_DMAS 32 285 286 #define NXGE_MAX_MACS_XMACS 16 287 #define NXGE_MAX_MACS_BMACS 8 288 #define NXGE_MAX_MACS (NXGE_MAX_PORTS * NXGE_MAX_MACS_XMACS) 289 290 #define NXGE_MAX_VLANS 4096 291 #define VLAN_ETHERTYPE (0x8100) 292 293 294 /* Scaling factor for RBR (receive block ring) */ 295 #define RBR_SCALE_1 0 296 #define RBR_SCALE_2 1 297 #define RBR_SCALE_3 2 298 #define RBR_SCALE_4 3 299 #define RBR_SCALE_5 4 300 #define RBR_SCALE_6 5 301 #define RBR_SCALE_7 6 302 #define RBR_SCALE_8 7 303 304 305 #define MAX_PORTS_PER_NXGE 4 306 #define MAX_MACS 32 307 308 #define TX_GATHER_POINTER_SZ 8 309 #define TX_GP_PER_BLOCK 8 310 #define TX_DEFAULT_MAX_GPS 1024 /* Max. # of gather pointers */ 311 #define TX_DEFAULT_JUMBO_MAX_GPS 4096 /* Max. # of gather pointers */ 312 #define TX_DEFAULT_MAX_LEN (TX_DEFAULT_MAX_GPS/TX_GP_PER_BLOCK) 313 #define TX_DEFAULT_JUMBO_MAX_LEN (TX_DEFAULT_JUMBO_MAX_GPS/TX_GP_PER_BLOCK) 314 315 #define TX_RING_THRESHOLD (TX_DEFAULT_MAX_GPS/4) 316 #define TX_RING_JUMBO_THRESHOLD (TX_DEFAULT_JUMBO_MAX_GPS/4) 317 318 #define TRANSMIT_HEADER_SIZE 16 /* 16 B frame header */ 319 320 #define TX_DESC_SAD_SHIFT 0 321 #define TX_DESC_SAD_MASK 0x00000FFFFFFFFFFFULL /* start address */ 322 #define TX_DESC_TR_LEN_SHIFT 44 323 #define TX_DESC_TR_LEN_MASK 0x00FFF00000000000ULL /* Transfer Length */ 324 #define TX_DESC_NUM_PTR_SHIFT 58 325 #define TX_DESC_NUM_PTR_MASK 0x2C00000000000000ULL /* gather pointers */ 326 #define TX_DESC_MASK_SHIFT 62 327 #define TX_DESC_MASK_MASK 0x4000000000000000ULL /* Mark bit */ 328 #define TX_DESC_SOP_SHIF 63 329 #define TX_DESC_NUM_MASK 0x8000000000000000ULL /* Start of packet */ 330 331 #define TCAM_FLOW_KEY_MAX_CLASS 12 332 #define TCAM_L3_MAX_USER_CLASS 4 333 #define TCAM_NIU_TCAM_MAX_ENTRY 128 334 #define TCAM_NXGE_TCAM_MAX_ENTRY 256 335 336 337 338 /* TCAM entry formats */ 339 #define TCAM_IPV4_5TUPLE_FORMAT 0x00 340 #define TCAM_IPV6_5TUPLE_FORMAT 0x01 341 #define TCAM_ETHERTYPE_FORMAT 0x02 342 343 344 /* TCAM */ 345 #define TCAM_SELECT_IPV6 0x01 346 #define TCAM_LOOKUP 0x04 347 #define TCAM_DISCARD 0x08 348 349 /* FLOW Key */ 350 #define FLOW_L4_1_34_BYTES 0x10 351 #define FLOW_L4_1_78_BYTES 0x11 352 #define FLOW_L4_0_12_BYTES (0x10 << 2) 353 #define FLOW_L4_0_56_BYTES (0x11 << 2) 354 #define FLOW_PROTO_NEXT 0x10 355 #define FLOW_IPDA 0x20 356 #define FLOW_IPSA 0x40 357 #define FLOW_VLAN 0x80 358 #define FLOW_L2DA 0x100 359 #define FLOW_PORT 0x200 360 361 /* TCAM */ 362 #define MAX_EFRAME 11 363 364 #define TCAM_USE_L2RDC_FLOW_LOOKUP 0x00 365 #define TCAM_USE_OFFSET_DONE 0x01 366 #define TCAM_OVERRIDE_L2_FLOW_LOOKUP 0x02 367 #define TCAM_OVERRIDE_L2_USE_OFFSET 0x03 368 369 /* 370 * FCRAM (Hashing): 371 * 1. IPv4 exact match 372 * 2. IPv6 exact match 373 * 3. IPv4 Optimistic match 374 * 4. IPv6 Optimistic match 375 * 376 */ 377 #define FCRAM_IPV4_EXT_MATCH 0x00 378 #define FCRAM_IPV6_EXT_MATCH 0x01 379 #define FCRAM_IPV4_OPTI_MATCH 0x02 380 #define FCRAM_IPV6_OPTI_MATCH 0x03 381 382 383 #define NXGE_HASH_MAX_ENTRY 256 384 385 386 #define MAC_ADDR_LENGTH 6 387 388 /* convert values */ 389 #define NXGE_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK)) 390 #define NXGE_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT)) 391 392 /* 393 * Locate the DMA channel start offset (PIO_VADDR) 394 * (DMA virtual address space of the PIO block) 395 */ 396 #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) 397 #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE) 398 399 /* 400 * PIO access using the DMC block directly (DMC) 401 */ 402 #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) 403 #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) 404 405 /* 406 * Number of logical pages. 407 */ 408 #define NXGE_MAX_LOGICAL_PAGES 2 409 410 #ifdef SOLARIS 411 #ifndef i386 412 #define _BIT_FIELDS_BIG_ENDIAN _BIT_FIELDS_HTOL 413 #else 414 #define _BIT_FIELDS_LITTLE_ENDIAN _BIT_FIELDS_LTOH 415 #endif 416 #else 417 #define _BIT_FIELDS_LITTLE_ENDIAN _LITTLE_ENDIAN_BITFIELD 418 #endif 419 420 #define MAX_PIO_RETRIES 32 421 422 #define IS_PORT_NUM_VALID(portn)\ 423 (portn < 4) 424 425 /* 426 * The following macros expect unsigned input values. 427 */ 428 #define TXDMA_CHANNEL_VALID(cn) (cn < NXGE_MAX_TDCS) 429 #define TXDMA_PAGE_VALID(pn) (pn < NXGE_MAX_LOGICAL_PAGES) 430 #define TXDMA_FUNC_VALID(fn) (fn < MAX_PORTS_PER_NXGE) 431 #define FUNC_VALID(n) (n < MAX_PORTS_PER_NXGE) 432 433 /* 434 * DMA channel binding definitions. 435 */ 436 #define VIR_PAGE_INDEX_MAX 8 437 #define VIR_SUB_REGIONS 2 438 #define VIR_DMA_BIND 1 439 440 #define SUBREGION_VALID(n) (n < VIR_SUB_REGIONS) 441 #define VIR_PAGE_INDEX_VALID(n) (n < VIR_PAGE_INDEX_MAX) 442 #define VRXDMA_CHANNEL_VALID(n) (n < NXGE_MAX_RDCS) 443 444 /* 445 * Logical device definitions. 446 */ 447 #define NXGE_INT_MAX_LD 69 448 #define NXGE_INT_MAX_LDG 64 449 450 #define NXGE_RDMA_LD_START 0 451 #define NXGE_TDMA_LD_START 32 452 #define NXGE_MIF_LD 63 453 #define NXGE_MAC_LD_PORT0 64 454 #define NXGE_MAC_LD_PORT1 65 455 #define NXGE_MAC_LD_PORT2 66 456 #define NXGE_MAC_LD_PORT3 67 457 #define NXGE_SYS_ERROR_LD 68 458 459 #define LDG_VALID(n) (n < NXGE_INT_MAX_LDG) 460 #define LD_VALID(n) (n < NXGE_INT_MAX_LD) 461 #define LD_RXDMA_LD_VALID(n) (n < NXGE_MAX_RDCS) 462 #define LD_TXDMA_LD_VALID(n) (n >= NXGE_MAX_RDCS && \ 463 ((n - NXGE_MAX_RDCS) < NXGE_MAX_TDCS))) 464 #define LD_MAC_VALID(n) (IS_PORT_NUM_VALID(n)) 465 466 #define LD_TIMER_MAX 0x3f 467 #define LD_INTTIMER_VALID(n) (n <= LD_TIMER_MAX) 468 469 /* System Interrupt Data */ 470 #define SID_VECTOR_MAX 0x1f 471 #define SID_VECTOR_VALID(n) (n <= SID_VECTOR_MAX) 472 473 #define NXGE_COMPILE_32 474 475 #ifdef __cplusplus 476 } 477 #endif 478 479 #endif /* _SYS_NXGE_NXGE_DEFS_H */ 480