1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if defined(_KERNEL) || defined(COSIM) 36 #include <nxge_mac.h> 37 #include <nxge_ipp.h> 38 #include <nxge_fflp.h> 39 #endif 40 41 /* 42 * NXGE diagnostics IOCTLS. 43 */ 44 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 45 46 #define NXGE_GET64 (NXGE_IOC|1) 47 #define NXGE_PUT64 (NXGE_IOC|2) 48 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 49 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 50 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 51 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 52 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 53 #define NXGE_RESET_MAC (NXGE_IOC|8) 54 55 #define NXGE_GET_MII (NXGE_IOC|11) 56 #define NXGE_PUT_MII (NXGE_IOC|12) 57 #define NXGE_RTRACE (NXGE_IOC|13) 58 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 59 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 60 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 61 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 62 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 63 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 64 #define NXGE_RDUMP (NXGE_IOC|26) 65 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 66 #define NXGE_PIO_TEST (NXGE_IOC|28) 67 68 #define NXGE_GET_TCAM (NXGE_IOC|29) 69 #define NXGE_PUT_TCAM (NXGE_IOC|30) 70 #define NXGE_INJECT_ERR (NXGE_IOC|40) 71 72 #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM) 73 #define NXGE_OK 0 74 #define NXGE_ERROR 0x40000000 75 #define NXGE_DDI_FAILED 0x20000000 76 #define NXGE_GET_PORT_NUM(n) n 77 78 /* 79 * Definitions for module_info. 80 */ 81 #define NXGE_IDNUM (0) /* module ID number */ 82 #define NXGE_DRIVER_NAME "nxge" /* module name */ 83 84 #define NXGE_MINPSZ (0) /* min packet size */ 85 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 86 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 87 #define NXGE_LOWAT (1) /* lo-water mark */ 88 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 89 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 90 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 91 #define NXGE_LOWAT_MIN (1) 92 93 #ifndef D_HOTPLUG 94 #define D_HOTPLUG 0x00 95 #endif 96 97 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 98 99 #define NXGE_CHECK_TIMER (5000) 100 101 typedef enum { 102 param_instance, 103 param_main_instance, 104 param_function_number, 105 param_partition_id, 106 param_read_write_mode, 107 param_fw_version, 108 param_port_mode, 109 param_niu_cfg_type, 110 param_tx_quick_cfg, 111 param_rx_quick_cfg, 112 param_master_cfg_enable, 113 param_master_cfg_value, 114 115 param_autoneg, 116 param_anar_10gfdx, 117 param_anar_10ghdx, 118 param_anar_1000fdx, 119 param_anar_1000hdx, 120 param_anar_100T4, 121 param_anar_100fdx, 122 param_anar_100hdx, 123 param_anar_10fdx, 124 param_anar_10hdx, 125 126 param_anar_asmpause, 127 param_anar_pause, 128 param_use_int_xcvr, 129 param_enable_ipg0, 130 param_ipg0, 131 param_ipg1, 132 param_ipg2, 133 param_accept_jumbo, 134 param_txdma_weight, 135 param_txdma_channels_begin, 136 137 param_txdma_channels, 138 param_txdma_info, 139 param_rxdma_channels_begin, 140 param_rxdma_channels, 141 param_rxdma_drr_weight, 142 param_rxdma_full_header, 143 param_rxdma_info, 144 param_rxdma_rbr_size, 145 param_rxdma_rcr_size, 146 param_default_port_rdc, 147 param_rxdma_intr_time, 148 param_rxdma_intr_pkts, 149 150 param_rdc_grps_start, 151 param_rx_rdc_grps, 152 param_default_grp0_rdc, 153 param_default_grp1_rdc, 154 param_default_grp2_rdc, 155 param_default_grp3_rdc, 156 param_default_grp4_rdc, 157 param_default_grp5_rdc, 158 param_default_grp6_rdc, 159 param_default_grp7_rdc, 160 161 param_info_rdc_groups, 162 param_start_ldg, 163 param_max_ldg, 164 param_mac_2rdc_grp, 165 param_vlan_2rdc_grp, 166 param_fcram_part_cfg, 167 param_fcram_access_ratio, 168 param_tcam_access_ratio, 169 param_tcam_enable, 170 param_hash_lookup_enable, 171 param_llc_snap_enable, 172 173 param_h1_init_value, 174 param_h2_init_value, 175 param_class_cfg_ether_usr1, 176 param_class_cfg_ether_usr2, 177 param_class_cfg_ip_usr4, 178 param_class_cfg_ip_usr5, 179 param_class_cfg_ip_usr6, 180 param_class_cfg_ip_usr7, 181 param_class_opt_ip_usr4, 182 param_class_opt_ip_usr5, 183 param_class_opt_ip_usr6, 184 param_class_opt_ip_usr7, 185 param_class_opt_ipv4_tcp, 186 param_class_opt_ipv4_udp, 187 param_class_opt_ipv4_ah, 188 param_class_opt_ipv4_sctp, 189 param_class_opt_ipv6_tcp, 190 param_class_opt_ipv6_udp, 191 param_class_opt_ipv6_ah, 192 param_class_opt_ipv6_sctp, 193 param_nxge_debug_flag, 194 param_npi_debug_flag, 195 param_dump_rdc, 196 param_dump_tdc, 197 param_dump_mac_regs, 198 param_dump_ipp_regs, 199 param_dump_fflp_regs, 200 param_dump_vlan_table, 201 param_dump_rdc_table, 202 param_dump_ptrs, 203 param_end 204 } nxge_param_index_t; 205 206 207 /* 208 * Named Dispatch Parameter Management Structure 209 */ 210 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 211 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 212 MBLKP, char *, caddr_t, cred_t *); 213 214 #define NXGE_PARAM_READ 0x00000001ULL 215 #define NXGE_PARAM_WRITE 0x00000002ULL 216 #define NXGE_PARAM_SHARED 0x00000004ULL 217 #define NXGE_PARAM_PRIV 0x00000008ULL 218 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 219 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 220 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 221 222 #define NXGE_PARAM_RXDMA 0x00000010ULL 223 #define NXGE_PARAM_TXDMA 0x00000020ULL 224 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 225 #define NXGE_PARAM_MAC 0x00000080ULL 226 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 227 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 228 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 229 230 #define NXGE_PARAM_CMPLX 0x00010000ULL 231 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 232 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 233 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 234 235 #define NXGE_PARAM_READ_PROP 0x00100000ULL 236 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 237 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 238 #define NXGE_PARAM_PROP_STR 0x00800000ULL 239 240 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 241 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 242 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 243 #define NXGE_PARAM_BASE_STR 0x40000000ULL 244 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 245 246 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 247 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 248 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 249 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 250 251 typedef struct _nxge_param_t { 252 int (*getf)(); 253 int (*setf)(); /* null for read only */ 254 uint64_t type; /* R/W/ Common/Port/ .... */ 255 uint64_t minimum; 256 uint64_t maximum; 257 uint64_t value; /* for array params, pointer to value array */ 258 uint64_t old_value; /* for array params, pointer to old_value array */ 259 char *fcode_name; 260 char *name; 261 } nxge_param_t, *p_nxge_param_t; 262 263 264 265 typedef enum { 266 nxge_lb_normal, 267 nxge_lb_ext10g, 268 nxge_lb_ext1000, 269 nxge_lb_ext100, 270 nxge_lb_ext10, 271 nxge_lb_phy10g, 272 nxge_lb_phy1000, 273 nxge_lb_phy, 274 nxge_lb_serdes10g, 275 nxge_lb_serdes1000, 276 nxge_lb_serdes, 277 nxge_lb_mac10g, 278 nxge_lb_mac1000, 279 nxge_lb_mac 280 } nxge_lb_t; 281 282 enum nxge_mac_state { 283 NXGE_MAC_STOPPED = 0, 284 NXGE_MAC_STARTED 285 }; 286 287 /* 288 * Private DLPI full dlsap address format. 289 */ 290 typedef struct _nxge_dladdr_t { 291 ether_addr_st dl_phys; 292 uint16_t dl_sap; 293 } nxge_dladdr_t, *p_nxge_dladdr_t; 294 295 typedef struct _mc_addr_t { 296 ether_addr_st multcast_addr; 297 uint_t mc_addr_cnt; 298 } mc_addr_t, *p_mc_addr_t; 299 300 typedef struct _mc_bucket_t { 301 p_mc_addr_t addr_list; 302 uint_t list_size; 303 } mc_bucket_t, *p_mc_bucket_t; 304 305 typedef struct _mc_table_t { 306 p_mc_bucket_t bucket_list; 307 uint_t buckets_used; 308 } mc_table_t, *p_mc_table_t; 309 310 typedef struct _filter_t { 311 uint32_t all_phys_cnt; 312 uint32_t all_multicast_cnt; 313 uint32_t all_sap_cnt; 314 } filter_t, *p_filter_t; 315 316 #if defined(_KERNEL) || defined(COSIM) 317 318 319 typedef struct _nxge_port_stats_t { 320 /* 321 * Overall structure size 322 */ 323 size_t stats_size; 324 325 /* 326 * Link Input/Output stats 327 */ 328 uint64_t ipackets; 329 uint64_t ierrors; 330 uint64_t opackets; 331 uint64_t oerrors; 332 uint64_t collisions; 333 334 /* 335 * MIB II variables 336 */ 337 uint64_t rbytes; /* # bytes received */ 338 uint64_t obytes; /* # bytes transmitted */ 339 uint32_t multircv; /* # multicast packets received */ 340 uint32_t multixmt; /* # multicast packets for xmit */ 341 uint32_t brdcstrcv; /* # broadcast packets received */ 342 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 343 uint32_t norcvbuf; /* # rcv packets discarded */ 344 uint32_t noxmtbuf; /* # xmit packets discarded */ 345 346 /* 347 * Lets the user know the MTU currently in use by 348 * the physical MAC port. 349 */ 350 nxge_lb_t lb_mode; 351 uint32_t qos_mode; 352 uint32_t trunk_mode; 353 uint32_t poll_mode; 354 355 /* 356 * Tx Statistics. 357 */ 358 uint32_t tx_inits; 359 uint32_t tx_starts; 360 uint32_t tx_nocanput; 361 uint32_t tx_msgdup_fail; 362 uint32_t tx_allocb_fail; 363 uint32_t tx_no_desc; 364 uint32_t tx_dma_bind_fail; 365 uint32_t tx_uflo; 366 uint32_t tx_hdr_pkts; 367 uint32_t tx_ddi_pkts; 368 uint32_t tx_dvma_pkts; 369 370 uint32_t tx_max_pend; 371 372 /* 373 * Rx Statistics. 374 */ 375 uint32_t rx_inits; 376 uint32_t rx_hdr_pkts; 377 uint32_t rx_mtu_pkts; 378 uint32_t rx_split_pkts; 379 uint32_t rx_no_buf; 380 uint32_t rx_no_comp_wb; 381 uint32_t rx_ov_flow; 382 uint32_t rx_len_mm; 383 uint32_t rx_tag_err; 384 uint32_t rx_nocanput; 385 uint32_t rx_msgdup_fail; 386 uint32_t rx_allocb_fail; 387 388 /* 389 * Receive buffer management statistics. 390 */ 391 uint32_t rx_new_pages; 392 uint32_t rx_new_hdr_pgs; 393 uint32_t rx_new_mtu_pgs; 394 uint32_t rx_new_nxt_pgs; 395 uint32_t rx_reused_pgs; 396 uint32_t rx_hdr_drops; 397 uint32_t rx_mtu_drops; 398 uint32_t rx_nxt_drops; 399 400 /* 401 * Receive flow statistics 402 */ 403 uint32_t rx_rel_flow; 404 uint32_t rx_rel_bit; 405 406 uint32_t rx_pkts_dropped; 407 408 /* 409 * PCI-E Bus Statistics. 410 */ 411 uint32_t pci_bus_speed; 412 uint32_t pci_err; 413 uint32_t pci_rta_err; 414 uint32_t pci_rma_err; 415 uint32_t pci_parity_err; 416 uint32_t pci_bad_ack_err; 417 uint32_t pci_drto_err; 418 uint32_t pci_dmawz_err; 419 uint32_t pci_dmarz_err; 420 421 uint32_t rx_taskq_waits; 422 423 uint32_t tx_jumbo_pkts; 424 425 /* 426 * Some statistics added to support bringup, these 427 * should be removed. 428 */ 429 uint32_t user_defined; 430 } nxge_port_stats_t, *p_nxge_port_stats_t; 431 432 433 typedef struct _nxge_stats_t { 434 /* 435 * Overall structure size 436 */ 437 size_t stats_size; 438 439 kstat_t *ksp; 440 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 441 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 442 kstat_t *rdc_sys_ksp; 443 kstat_t *fflp_ksp[1]; 444 kstat_t *ipp_ksp; 445 kstat_t *txc_ksp; 446 kstat_t *mac_ksp; 447 kstat_t *zcp_ksp; 448 kstat_t *port_ksp; 449 kstat_t *mmac_ksp; 450 451 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 452 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 453 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 454 455 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 456 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 457 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 458 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 459 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 460 461 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 462 nxge_txc_stats_t txc_stats; /* per port TX stats */ 463 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 464 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 465 nxge_port_stats_t port_stats; /* fflp stats */ 466 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 467 468 } nxge_stats_t, *p_nxge_stats_t; 469 470 471 472 typedef struct _nxge_intr_t { 473 boolean_t intr_registered; /* interrupts are registered */ 474 boolean_t intr_enabled; /* interrupts are enabled */ 475 boolean_t niu_msi_enable; /* debug or configurable? */ 476 uint8_t nldevs; /* # of logical devices */ 477 int intr_types; /* interrupt types supported */ 478 int intr_type; /* interrupt type to add */ 479 int max_int_cnt; /* max MSIX/INT HW supports */ 480 int start_inum; /* start inum (in sequence?) */ 481 int msi_intx_cnt; /* # msi/intx ints returned */ 482 int intr_added; /* # ints actually needed */ 483 int intr_cap; /* interrupt capabilities */ 484 size_t intr_size; /* size of array to allocate */ 485 ddi_intr_handle_t *htable; /* For array of interrupts */ 486 /* Add interrupt number for each interrupt vector */ 487 int pri; 488 } nxge_intr_t, *p_nxge_intr_t; 489 490 typedef struct _nxge_ldgv_t { 491 uint8_t ndma_ldvs; 492 uint8_t nldvs; 493 uint8_t start_ldg; 494 uint8_t start_ldg_tx; 495 uint8_t start_ldg_rx; 496 uint8_t maxldgs; 497 uint8_t maxldvs; 498 uint8_t ldg_intrs; 499 boolean_t own_sys_err; 500 boolean_t own_max_ldv; 501 uint32_t tmres; 502 p_nxge_ldg_t ldgp; 503 p_nxge_ldv_t ldvp; 504 p_nxge_ldv_t ldvp_syserr; 505 } nxge_ldgv_t, *p_nxge_ldgv_t; 506 507 /* 508 * Neptune Device instance state information. 509 * 510 * Each instance is dynamically allocated on first attach. 511 */ 512 struct _nxge_t { 513 dev_info_t *dip; /* device instance */ 514 dev_info_t *p_dip; /* Parent's device instance */ 515 int instance; /* instance number */ 516 int function_num; /* device function number */ 517 int nports; /* # of ports on this device */ 518 int board_ver; /* Board Version */ 519 int partition_id; /* partition ID */ 520 int use_partition; /* partition is enabled */ 521 uint32_t drv_state; /* driver state bit flags */ 522 uint64_t nxge_debug_level; /* driver state bit flags */ 523 kmutex_t genlock[1]; 524 enum nxge_mac_state nxge_mac_state; 525 ddi_softintr_t resched_id; /* reschedule callback */ 526 boolean_t resched_needed; 527 boolean_t resched_running; 528 529 p_dev_regs_t dev_regs; 530 npi_handle_t npi_handle; 531 npi_handle_t npi_pci_handle; 532 npi_handle_t npi_reg_handle; 533 npi_handle_t npi_msi_handle; 534 npi_handle_t npi_vreg_handle; 535 npi_handle_t npi_v2reg_handle; 536 537 nxge_xcvr_table_t xcvr; 538 boolean_t hot_swappable_phy; 539 boolean_t phy_absent; 540 uint32_t xcvr_addr; 541 uint16_t chip_id; 542 nxge_mac_t mac; 543 nxge_ipp_t ipp; 544 nxge_txc_t txc; 545 nxge_classify_t classifier; 546 547 mac_handle_t mach; /* mac module handle */ 548 p_nxge_stats_t statsp; 549 uint32_t param_count; 550 p_nxge_param_t param_arr; 551 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 552 niu_type_t niu_type; 553 platform_type_t platform_type; 554 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 555 uint8_t nrdc; 556 uint8_t def_rdc; 557 uint8_t rdc[NXGE_MAX_RDCS]; 558 uint8_t ntdc; 559 uint8_t tdc[NXGE_MAX_TDCS]; 560 561 nxge_intr_t nxge_intr_type; 562 nxge_dma_pt_cfg_t pt_config; 563 nxge_class_pt_cfg_t class_config; 564 565 /* Logical device and group data structures. */ 566 p_nxge_ldgv_t ldgvp; 567 568 npi_vpd_info_t vpd_info; 569 caddr_t param_list; /* Parameter list */ 570 571 ether_addr_st factaddr; /* factory mac address */ 572 ether_addr_st ouraddr; /* individual address */ 573 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 574 575 ddi_iblock_cookie_t interrupt_cookie; 576 577 /* 578 * Blocks of memory may be pre-allocated by the 579 * partition manager or the driver. They may include 580 * blocks for configuration and buffers. The idea is 581 * to preallocate big blocks of contiguous areas in 582 * system memory (i.e. with IOMMU). These blocks then 583 * will be broken up to a fixed number of blocks with 584 * each block having the same block size (4K, 8K, 16K or 585 * 32K) in the case of buffer blocks. For systems that 586 * do not support DVMA, more than one big block will be 587 * allocated. 588 */ 589 uint32_t rx_default_block_size; 590 nxge_rx_block_size_t rx_bksize_code; 591 592 p_nxge_dma_pool_t rx_buf_pool_p; 593 p_nxge_dma_pool_t rx_cntl_pool_p; 594 595 p_nxge_dma_pool_t tx_buf_pool_p; 596 p_nxge_dma_pool_t tx_cntl_pool_p; 597 598 /* Receive buffer block ring and completion ring. */ 599 p_rx_rbr_rings_t rx_rbr_rings; 600 p_rx_rcr_rings_t rx_rcr_rings; 601 p_rx_mbox_areas_t rx_mbox_areas_p; 602 603 p_rx_tx_params_t rx_params; 604 uint32_t start_rdc; 605 uint32_t max_rdcs; 606 uint32_t rdc_mask; 607 608 /* Transmit descriptors rings */ 609 p_tx_rings_t tx_rings; 610 p_tx_mbox_areas_t tx_mbox_areas_p; 611 612 uint32_t start_tdc; 613 uint32_t max_tdcs; 614 uint32_t tdc_mask; 615 616 p_rx_tx_params_t tx_params; 617 618 ddi_dma_handle_t dmasparehandle; 619 620 ulong_t sys_page_sz; 621 ulong_t sys_page_mask; 622 int suspended; 623 624 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 625 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 626 627 kmutex_t mif_lock; /* Lock to protect the list. */ 628 629 void (*mii_read)(); 630 void (*mii_write)(); 631 void (*mii_poll)(); 632 filter_t filter; /* Current instance filter */ 633 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 634 krwlock_t filter_lock; /* Lock to protect filters. */ 635 636 ulong_t sys_burst_sz; 637 638 uint8_t cache_line; 639 640 timeout_id_t nxge_link_poll_timerid; 641 timeout_id_t nxge_timerid; 642 643 uint_t need_periodic_reclaim; 644 timeout_id_t reclaim_timer; 645 646 uint8_t msg_min; 647 uint8_t crc_size; 648 649 boolean_t hard_props_read; 650 651 boolean_t nxge_htraffic; 652 uint32_t nxge_ncpus; 653 uint32_t nxge_cpumask; 654 uint16_t intr_timeout; 655 uint16_t intr_threshold; 656 uchar_t nxge_rxmode; 657 uint32_t active_threads; 658 659 rtrace_t rtrace; 660 int fm_capabilities; /* FMA capabilities */ 661 662 uint32_t nxge_port_rbr_size; 663 uint32_t nxge_port_rcr_size; 664 uint32_t nxge_port_tx_ring_size; 665 nxge_mmac_t nxge_mmac_info; 666 #if defined(sun4v) 667 boolean_t niu_hsvc_available; 668 hsvc_info_t niu_hsvc; 669 uint64_t niu_min_ver; 670 #endif 671 boolean_t link_notify; 672 673 kmutex_t poll_lock; 674 kcondvar_t poll_cv; 675 link_mon_enable_t poll_state; 676 #define NXGE_MAGIC 0x3ab434e3 677 uint32_t nxge_magic; 678 }; 679 680 /* 681 * Driver state flags. 682 */ 683 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 684 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 685 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 686 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 687 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 688 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 689 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 690 691 #define STOP_POLL_THRESH 9 692 #define START_POLL_THRESH 2 693 694 typedef struct _nxge_port_kstat_t { 695 /* 696 * Transciever state informations. 697 */ 698 kstat_named_t xcvr_inits; 699 kstat_named_t xcvr_inuse; 700 kstat_named_t xcvr_addr; 701 kstat_named_t xcvr_id; 702 kstat_named_t cap_autoneg; 703 kstat_named_t cap_10gfdx; 704 kstat_named_t cap_10ghdx; 705 kstat_named_t cap_1000fdx; 706 kstat_named_t cap_1000hdx; 707 kstat_named_t cap_100T4; 708 kstat_named_t cap_100fdx; 709 kstat_named_t cap_100hdx; 710 kstat_named_t cap_10fdx; 711 kstat_named_t cap_10hdx; 712 kstat_named_t cap_asmpause; 713 kstat_named_t cap_pause; 714 715 /* 716 * Link partner capabilities. 717 */ 718 kstat_named_t lp_cap_autoneg; 719 kstat_named_t lp_cap_10gfdx; 720 kstat_named_t lp_cap_10ghdx; 721 kstat_named_t lp_cap_1000fdx; 722 kstat_named_t lp_cap_1000hdx; 723 kstat_named_t lp_cap_100T4; 724 kstat_named_t lp_cap_100fdx; 725 kstat_named_t lp_cap_100hdx; 726 kstat_named_t lp_cap_10fdx; 727 kstat_named_t lp_cap_10hdx; 728 kstat_named_t lp_cap_asmpause; 729 kstat_named_t lp_cap_pause; 730 731 /* 732 * Shared link setup. 733 */ 734 kstat_named_t link_T4; 735 kstat_named_t link_speed; 736 kstat_named_t link_duplex; 737 kstat_named_t link_asmpause; 738 kstat_named_t link_pause; 739 kstat_named_t link_up; 740 741 /* 742 * Lets the user know the MTU currently in use by 743 * the physical MAC port. 744 */ 745 kstat_named_t mac_mtu; 746 kstat_named_t lb_mode; 747 kstat_named_t qos_mode; 748 kstat_named_t trunk_mode; 749 750 /* 751 * Misc MAC statistics. 752 */ 753 kstat_named_t ifspeed; 754 kstat_named_t promisc; 755 kstat_named_t rev_id; 756 757 /* 758 * Some statistics added to support bringup, these 759 * should be removed. 760 */ 761 kstat_named_t user_defined; 762 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 763 764 typedef struct _nxge_rdc_kstat { 765 /* 766 * Receive DMA channel statistics. 767 */ 768 kstat_named_t ipackets; 769 kstat_named_t rbytes; 770 kstat_named_t errors; 771 kstat_named_t dcf_err; 772 kstat_named_t rcr_ack_err; 773 774 kstat_named_t dc_fifoflow_err; 775 kstat_named_t rcr_sha_par_err; 776 kstat_named_t rbr_pre_par_err; 777 kstat_named_t wred_drop; 778 kstat_named_t rbr_pre_emty; 779 780 kstat_named_t rcr_shadow_full; 781 kstat_named_t rbr_tmout; 782 kstat_named_t rsp_cnt_err; 783 kstat_named_t byte_en_bus; 784 kstat_named_t rsp_dat_err; 785 786 kstat_named_t compl_l2_err; 787 kstat_named_t compl_l4_cksum_err; 788 kstat_named_t compl_zcp_soft_err; 789 kstat_named_t compl_fflp_soft_err; 790 kstat_named_t config_err; 791 792 kstat_named_t rcrincon; 793 kstat_named_t rcrfull; 794 kstat_named_t rbr_empty; 795 kstat_named_t rbrfull; 796 kstat_named_t rbrlogpage; 797 798 kstat_named_t cfiglogpage; 799 kstat_named_t port_drop_pkt; 800 kstat_named_t rcr_to; 801 kstat_named_t rcr_thresh; 802 kstat_named_t rcr_mex; 803 kstat_named_t id_mismatch; 804 kstat_named_t zcp_eop_err; 805 kstat_named_t ipp_eop_err; 806 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 807 808 typedef struct _nxge_rdc_sys_kstat { 809 /* 810 * Receive DMA system statistics. 811 */ 812 kstat_named_t pre_par; 813 kstat_named_t sha_par; 814 kstat_named_t id_mismatch; 815 kstat_named_t ipp_eop_err; 816 kstat_named_t zcp_eop_err; 817 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 818 819 typedef struct _nxge_tdc_kstat { 820 /* 821 * Transmit DMA channel statistics. 822 */ 823 kstat_named_t opackets; 824 kstat_named_t obytes; 825 kstat_named_t oerrors; 826 kstat_named_t tx_inits; 827 kstat_named_t tx_no_buf; 828 829 kstat_named_t mbox_err; 830 kstat_named_t pkt_size_err; 831 kstat_named_t tx_ring_oflow; 832 kstat_named_t pref_buf_ecc_err; 833 kstat_named_t nack_pref; 834 kstat_named_t nack_pkt_rd; 835 kstat_named_t conf_part_err; 836 kstat_named_t pkt_prt_err; 837 kstat_named_t reset_fail; 838 /* used to in the common (per port) counter */ 839 840 kstat_named_t tx_starts; 841 kstat_named_t tx_nocanput; 842 kstat_named_t tx_msgdup_fail; 843 kstat_named_t tx_allocb_fail; 844 kstat_named_t tx_no_desc; 845 kstat_named_t tx_dma_bind_fail; 846 kstat_named_t tx_uflo; 847 kstat_named_t tx_hdr_pkts; 848 kstat_named_t tx_ddi_pkts; 849 kstat_named_t tx_dvma_pkts; 850 kstat_named_t tx_max_pend; 851 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 852 853 typedef struct _nxge_txc_kstat { 854 /* 855 * Transmit port TXC block statistics. 856 */ 857 kstat_named_t pkt_stuffed; 858 kstat_named_t pkt_xmit; 859 kstat_named_t ro_correct_err; 860 kstat_named_t ro_uncorrect_err; 861 kstat_named_t sf_correct_err; 862 kstat_named_t sf_uncorrect_err; 863 kstat_named_t address_failed; 864 kstat_named_t dma_failed; 865 kstat_named_t length_failed; 866 kstat_named_t pkt_assy_dead; 867 kstat_named_t reorder_err; 868 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 869 870 typedef struct _nxge_ipp_kstat { 871 /* 872 * Receive port IPP block statistics. 873 */ 874 kstat_named_t eop_miss; 875 kstat_named_t sop_miss; 876 kstat_named_t dfifo_ue; 877 kstat_named_t ecc_err_cnt; 878 kstat_named_t pfifo_perr; 879 kstat_named_t pfifo_over; 880 kstat_named_t pfifo_und; 881 kstat_named_t bad_cs_cnt; 882 kstat_named_t pkt_dis_cnt; 883 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 884 885 typedef struct _nxge_zcp_kstat { 886 /* 887 * ZCP statistics. 888 */ 889 kstat_named_t errors; 890 kstat_named_t inits; 891 kstat_named_t rrfifo_underrun; 892 kstat_named_t rrfifo_overrun; 893 kstat_named_t rspfifo_uncorr_err; 894 kstat_named_t buffer_overflow; 895 kstat_named_t stat_tbl_perr; 896 kstat_named_t dyn_tbl_perr; 897 kstat_named_t buf_tbl_perr; 898 kstat_named_t tt_program_err; 899 kstat_named_t rsp_tt_index_err; 900 kstat_named_t slv_tt_index_err; 901 kstat_named_t zcp_tt_index_err; 902 kstat_named_t access_fail; 903 kstat_named_t cfifo_ecc; 904 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 905 906 typedef struct _nxge_mac_kstat { 907 /* 908 * Transmit MAC statistics. 909 */ 910 kstat_named_t tx_frame_cnt; 911 kstat_named_t tx_underflow_err; 912 kstat_named_t tx_overflow_err; 913 kstat_named_t tx_maxpktsize_err; 914 kstat_named_t tx_fifo_xfr_err; 915 kstat_named_t tx_byte_cnt; 916 917 /* 918 * Receive MAC statistics. 919 */ 920 kstat_named_t rx_frame_cnt; 921 kstat_named_t rx_underflow_err; 922 kstat_named_t rx_overflow_err; 923 kstat_named_t rx_len_err_cnt; 924 kstat_named_t rx_crc_err_cnt; 925 kstat_named_t rx_viol_err_cnt; 926 kstat_named_t rx_byte_cnt; 927 kstat_named_t rx_hist1_cnt; 928 kstat_named_t rx_hist2_cnt; 929 kstat_named_t rx_hist3_cnt; 930 kstat_named_t rx_hist4_cnt; 931 kstat_named_t rx_hist5_cnt; 932 kstat_named_t rx_hist6_cnt; 933 kstat_named_t rx_broadcast_cnt; 934 kstat_named_t rx_mult_cnt; 935 kstat_named_t rx_frag_cnt; 936 kstat_named_t rx_frame_align_err_cnt; 937 kstat_named_t rx_linkfault_err_cnt; 938 kstat_named_t rx_local_fault_err_cnt; 939 kstat_named_t rx_remote_fault_err_cnt; 940 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 941 942 typedef struct _nxge_xmac_kstat { 943 /* 944 * XMAC statistics. 945 */ 946 kstat_named_t tx_frame_cnt; 947 kstat_named_t tx_underflow_err; 948 kstat_named_t tx_maxpktsize_err; 949 kstat_named_t tx_overflow_err; 950 kstat_named_t tx_fifo_xfr_err; 951 kstat_named_t tx_byte_cnt; 952 kstat_named_t rx_frame_cnt; 953 kstat_named_t rx_underflow_err; 954 kstat_named_t rx_overflow_err; 955 kstat_named_t rx_crc_err_cnt; 956 kstat_named_t rx_len_err_cnt; 957 kstat_named_t rx_viol_err_cnt; 958 kstat_named_t rx_byte_cnt; 959 kstat_named_t rx_hist1_cnt; 960 kstat_named_t rx_hist2_cnt; 961 kstat_named_t rx_hist3_cnt; 962 kstat_named_t rx_hist4_cnt; 963 kstat_named_t rx_hist5_cnt; 964 kstat_named_t rx_hist6_cnt; 965 kstat_named_t rx_hist7_cnt; 966 kstat_named_t rx_broadcast_cnt; 967 kstat_named_t rx_mult_cnt; 968 kstat_named_t rx_frag_cnt; 969 kstat_named_t rx_frame_align_err_cnt; 970 kstat_named_t rx_linkfault_err_cnt; 971 kstat_named_t rx_remote_fault_err_cnt; 972 kstat_named_t rx_local_fault_err_cnt; 973 kstat_named_t rx_pause_cnt; 974 kstat_named_t xpcs_deskew_err_cnt; 975 kstat_named_t xpcs_ln0_symbol_err_cnt; 976 kstat_named_t xpcs_ln1_symbol_err_cnt; 977 kstat_named_t xpcs_ln2_symbol_err_cnt; 978 kstat_named_t xpcs_ln3_symbol_err_cnt; 979 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 980 981 typedef struct _nxge_bmac_kstat { 982 /* 983 * BMAC statistics. 984 */ 985 kstat_named_t tx_frame_cnt; 986 kstat_named_t tx_underrun_err; 987 kstat_named_t tx_max_pkt_err; 988 kstat_named_t tx_byte_cnt; 989 kstat_named_t rx_frame_cnt; 990 kstat_named_t rx_byte_cnt; 991 kstat_named_t rx_overflow_err; 992 kstat_named_t rx_align_err_cnt; 993 kstat_named_t rx_crc_err_cnt; 994 kstat_named_t rx_len_err_cnt; 995 kstat_named_t rx_viol_err_cnt; 996 kstat_named_t rx_pause_cnt; 997 kstat_named_t tx_pause_state; 998 kstat_named_t tx_nopause_state; 999 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 1000 1001 1002 typedef struct _nxge_fflp_kstat { 1003 /* 1004 * FFLP statistics. 1005 */ 1006 1007 kstat_named_t fflp_tcam_ecc_err; 1008 kstat_named_t fflp_tcam_perr; 1009 kstat_named_t fflp_vlan_perr; 1010 kstat_named_t fflp_hasht_lookup_err; 1011 kstat_named_t fflp_access_fail; 1012 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 1013 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1014 1015 typedef struct _nxge_mmac_kstat { 1016 kstat_named_t mmac_max_addr_cnt; 1017 kstat_named_t mmac_avail_addr_cnt; 1018 kstat_named_t mmac_addr1; 1019 kstat_named_t mmac_addr2; 1020 kstat_named_t mmac_addr3; 1021 kstat_named_t mmac_addr4; 1022 kstat_named_t mmac_addr5; 1023 kstat_named_t mmac_addr6; 1024 kstat_named_t mmac_addr7; 1025 kstat_named_t mmac_addr8; 1026 kstat_named_t mmac_addr9; 1027 kstat_named_t mmac_addr10; 1028 kstat_named_t mmac_addr11; 1029 kstat_named_t mmac_addr12; 1030 kstat_named_t mmac_addr13; 1031 kstat_named_t mmac_addr14; 1032 kstat_named_t mmac_addr15; 1033 kstat_named_t mmac_addr16; 1034 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1035 1036 #endif /* _KERNEL */ 1037 1038 /* 1039 * Prototype definitions. 1040 */ 1041 nxge_status_t nxge_init(p_nxge_t); 1042 void nxge_uninit(p_nxge_t); 1043 void nxge_get64(p_nxge_t, p_mblk_t); 1044 void nxge_put64(p_nxge_t, p_mblk_t); 1045 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1046 1047 #ifndef COSIM 1048 typedef void (*fptrv_t)(); 1049 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1050 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1051 #endif 1052 #endif 1053 1054 #ifdef __cplusplus 1055 } 1056 #endif 1057 1058 #endif /* _SYS_NXGE_NXGE_H */ 1059