1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #ifndef _SYS_DDI_INTR_IMPL_H 26 #define _SYS_DDI_INTR_IMPL_H 27 28 /* 29 * Sun DDI interrupt implementation specific definitions 30 */ 31 32 #include <sys/list.h> 33 #include <sys/ksynch.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #ifdef _KERNEL 40 41 /* 42 * Typedef for interrupt ops 43 */ 44 typedef enum { 45 DDI_INTROP_SUPPORTED_TYPES = 1, /* 1 get supported interrupts types */ 46 DDI_INTROP_NINTRS, /* 2 get num of interrupts supported */ 47 DDI_INTROP_ALLOC, /* 3 allocate interrupt handle */ 48 DDI_INTROP_GETPRI, /* 4 get priority */ 49 DDI_INTROP_SETPRI, /* 5 set priority */ 50 DDI_INTROP_ADDISR, /* 6 add interrupt handler */ 51 DDI_INTROP_DUPVEC, /* 7 duplicate interrupt handler */ 52 DDI_INTROP_ENABLE, /* 8 enable interrupt */ 53 DDI_INTROP_BLOCKENABLE, /* 9 block enable interrupts */ 54 DDI_INTROP_BLOCKDISABLE, /* 10 block disable interrupts */ 55 DDI_INTROP_DISABLE, /* 11 disable interrupt */ 56 DDI_INTROP_REMISR, /* 12 remove interrupt handler */ 57 DDI_INTROP_FREE, /* 13 free interrupt handle */ 58 DDI_INTROP_GETCAP, /* 14 get capacity */ 59 DDI_INTROP_SETCAP, /* 15 set capacity */ 60 DDI_INTROP_SETMASK, /* 16 set mask */ 61 DDI_INTROP_CLRMASK, /* 17 clear mask */ 62 DDI_INTROP_GETPENDING, /* 18 get pending interrupt */ 63 DDI_INTROP_NAVAIL, /* 19 get num of available interrupts */ 64 DDI_INTROP_GETPOOL, /* 20 get resource management pool */ 65 DDI_INTROP_GETTARGET, /* 21 get target for a given intr(s) */ 66 DDI_INTROP_SETTARGET /* 22 set target for a given intr(s) */ 67 } ddi_intr_op_t; 68 69 /* Version number used in the handles */ 70 #define DDI_INTR_VERSION_1 1 71 #define DDI_INTR_VERSION DDI_INTR_VERSION_1 72 73 /* 74 * One such data structure is allocated per ddi_intr_handle_t 75 * This is the incore copy of the regular interrupt info. 76 */ 77 typedef struct ddi_intr_handle_impl { 78 dev_info_t *ih_dip; /* dip associated with handle */ 79 uint16_t ih_type; /* interrupt type being used */ 80 ushort_t ih_inum; /* interrupt number */ 81 uint32_t ih_vector; /* vector number */ 82 uint16_t ih_ver; /* Version */ 83 uint_t ih_state; /* interrupt handle state */ 84 uint_t ih_cap; /* interrupt capabilities */ 85 uint_t ih_pri; /* priority - bus dependent */ 86 krwlock_t ih_rwlock; /* read/write lock per handle */ 87 88 uint_t (*ih_cb_func)(caddr_t, caddr_t); 89 void *ih_cb_arg1; 90 void *ih_cb_arg2; 91 92 /* 93 * The following 3 members are used to support MSI-X specific features 94 */ 95 uint_t ih_flags; /* Misc flags */ 96 uint_t ih_dup_cnt; /* # of dupped msi-x vectors */ 97 struct ddi_intr_handle_impl *ih_main; 98 /* pntr to the main vector */ 99 /* 100 * The next set of members are for 'scratch' purpose only. 101 * The DDI interrupt framework uses them internally and their 102 * interpretation is left to the framework. For now, 103 * scratch1 - used to send NINTRs information 104 * to various nexus drivers. 105 * scratch2 - used to send 'behavior' flag 106 * information to the nexus drivers 107 * from ddi_intr_alloc(). It is also 108 * used to send 'h_array' to the nexus drivers 109 * for ddi_intr_block_enable/disable() on x86. 110 * private - On X86 it usually carries a pointer to 111 * ihdl_plat_t. Not used on SPARC platforms. 112 */ 113 void *ih_private; /* Platform specific data */ 114 uint_t ih_scratch1; /* Scratch1: #interrupts */ 115 void *ih_scratch2; /* Scratch2: flag/h_array */ 116 117 /* 118 * The ih_target field may not reflect the actual target that is 119 * currently being used for the given interrupt. This field is just a 120 * snapshot taken either during ddi_intr_add_handler() or 121 * get/set_intr_affinity() calls. 122 */ 123 processorid_t ih_target; /* Target ID */ 124 } ddi_intr_handle_impl_t; 125 126 /* values for ih_state (strictly for interrupt handle) */ 127 #define DDI_IHDL_STATE_ALLOC 0x01 /* Allocated. ddi_intr_alloc() called */ 128 #define DDI_IHDL_STATE_ADDED 0x02 /* Added interrupt handler */ 129 /* ddi_intr_add_handler() called */ 130 #define DDI_IHDL_STATE_ENABLE 0x04 /* Enabled. ddi_intr_enable() called */ 131 132 #define DDI_INTR_IS_MSI_OR_MSIX(type) \ 133 ((type) == DDI_INTR_TYPE_MSI || (type) == DDI_INTR_TYPE_MSIX) 134 135 #define DDI_INTR_BEHAVIOR_FLAG_VALID(f) \ 136 (((f) == DDI_INTR_ALLOC_NORMAL) || ((f) == DDI_INTR_ALLOC_STRICT)) 137 138 #define DDI_INTR_TYPE_FLAG_VALID(t) \ 139 (((t) == DDI_INTR_TYPE_FIXED) || \ 140 ((t) == DDI_INTR_TYPE_MSI) || \ 141 ((t) == DDI_INTR_TYPE_MSIX)) 142 143 /* values for ih_flags */ 144 #define DDI_INTR_MSIX_DUP 0x01 /* MSI-X vector which has been dupped */ 145 146 /* Maximum number of MSI resources to allocate */ 147 #define DDI_MAX_MSI_ALLOC 2 148 149 /* Default number of MSI-X resources to allocate */ 150 #define DDI_DEFAULT_MSIX_ALLOC 2 151 152 #define DDI_MSIX_ALLOC_DIVIDER 32 153 #define DDI_MIN_MSIX_ALLOC 8 154 #define DDI_MAX_MSIX_ALLOC 2048 155 156 struct av_softinfo; 157 158 /* 159 * One such data structure is allocated per ddi_soft_intr_handle 160 * This is the incore copy of the softint info. 161 */ 162 typedef struct ddi_softint_hdl_impl { 163 dev_info_t *ih_dip; /* dip associated with handle */ 164 uint_t ih_pri; /* priority - bus dependent */ 165 krwlock_t ih_rwlock; /* read/write lock per handle */ 166 struct av_softinfo *ih_pending; /* whether softint is pending */ 167 168 uint_t (*ih_cb_func)(caddr_t, caddr_t); 169 /* cb function for soft ints */ 170 void *ih_cb_arg1; /* arg1 of callback function */ 171 void *ih_cb_arg2; /* arg2 passed to "trigger" */ 172 173 /* 174 * The next member is for 'scratch' purpose only. 175 * The DDI interrupt framework uses it internally and its 176 * interpretation is left to the framework. 177 * private - used by the DDI framework to pass back 178 * and forth 'softid' information on SPARC 179 * side only. Not used on X86 platform. 180 */ 181 void *ih_private; /* Platform specific data */ 182 } ddi_softint_hdl_impl_t; 183 184 /* Softint internal implementation defines */ 185 #define DDI_SOFT_INTR_PRI_M 4 186 #define DDI_SOFT_INTR_PRI_H 6 187 188 /* 189 * One such data structure is allocated for MSI-X enabled 190 * device. If no MSI-X is enabled then it is NULL 191 */ 192 typedef struct ddi_intr_msix { 193 /* MSI-X Table related information */ 194 ddi_acc_handle_t msix_tbl_hdl; /* MSI-X table handle */ 195 uint32_t *msix_tbl_addr; /* MSI-X table addr */ 196 uint32_t msix_tbl_offset; /* MSI-X table offset */ 197 198 /* MSI-X PBA Table related information */ 199 ddi_acc_handle_t msix_pba_hdl; /* MSI-X PBA handle */ 200 uint32_t *msix_pba_addr; /* MSI-X PBA addr */ 201 uint32_t msix_pba_offset; /* MSI-X PBA offset */ 202 203 ddi_device_acc_attr_t msix_dev_attr; /* MSI-X device attr */ 204 } ddi_intr_msix_t; 205 206 /* 207 * Interrupt Resource Management (IRM). 208 */ 209 210 #define DDI_IRM_POLICY_LARGE 1 211 #define DDI_IRM_POLICY_EVEN 2 212 213 #define DDI_IRM_POLICY_VALID(p) (((p) == DDI_IRM_POLICY_LARGE) || \ 214 ((p) == DDI_IRM_POLICY_EVEN)) 215 216 #define DDI_IRM_FLAG_ACTIVE 0x1 /* Pool is active */ 217 #define DDI_IRM_FLAG_QUEUED 0x2 /* Pool is queued */ 218 #define DDI_IRM_FLAG_WAITERS 0x4 /* Pool has waiters */ 219 #define DDI_IRM_FLAG_EXIT 0x8 /* Balance thread must exit */ 220 #define DDI_IRM_FLAG_NEW 0x10 /* Request is new */ 221 #define DDI_IRM_FLAG_CALLBACK 0x20 /* Request has callback */ 222 223 /* 224 * One such data structure for each supply of interrupt vectors. 225 * Contains information about the size and policies defining the 226 * supply, and a list of associated device-specific requests. 227 */ 228 typedef struct ddi_irm_pool { 229 int ipool_flags; /* Status flags of the pool */ 230 int ipool_types; /* Types of interrupts */ 231 int ipool_policy; /* Rebalancing policy */ 232 uint_t ipool_totsz; /* Total size of the pool */ 233 uint_t ipool_defsz; /* Default allocation size */ 234 uint_t ipool_minno; /* Minimum number consumed */ 235 uint_t ipool_reqno; /* Total number requested */ 236 uint_t ipool_resno; /* Total number reserved */ 237 kmutex_t ipool_lock; /* Protects all pool usage */ 238 kmutex_t ipool_navail_lock; /* Protects 'navail' of reqs */ 239 kcondvar_t ipool_cv; /* Condition variable */ 240 kthread_t *ipool_thread; /* Balancing thread */ 241 dev_info_t *ipool_owner; /* Device that created pool */ 242 list_t ipool_req_list; /* All requests in pool */ 243 list_t ipool_scratch_list; /* Requests being reduced */ 244 list_node_t ipool_link; /* Links in global pool list */ 245 } ddi_irm_pool_t; 246 247 /* 248 * One such data structure for each dip's devinfo_intr_t. 249 * Contains information about vectors requested from IRM. 250 */ 251 typedef struct ddi_irm_req { 252 int ireq_flags; /* Flags for request */ 253 int ireq_type; /* Type requested */ 254 uint_t ireq_nreq; /* Number requested */ 255 uint_t ireq_navail; /* Number available */ 256 uint_t ireq_scratch; /* Scratch value */ 257 dev_info_t *ireq_dip; /* Requesting device */ 258 ddi_irm_pool_t *ireq_pool_p; /* Supplying pool */ 259 list_node_t ireq_link; /* Request list link */ 260 list_node_t ireq_scratch_link; /* Scratch list link */ 261 } ddi_irm_req_t; 262 263 /* 264 * This structure is used to pass parameters to ndi_create_irm(), 265 * and describes the operating parameters of an IRM pool. 266 */ 267 typedef struct ddi_irm_params { 268 int iparams_types; /* Types of interrupts in pool */ 269 uint_t iparams_total; /* Total size of the pool */ 270 } ddi_irm_params_t; 271 272 /* 273 * One such data structure is allocated for each dip. 274 * It has interrupt related information that can be 275 * stored/retrieved for convenience. 276 */ 277 typedef struct devinfo_intr { 278 /* These three fields show what the device is capable of */ 279 uint_t devi_intr_sup_types; /* Intrs supported by device */ 280 281 ddi_intr_msix_t *devi_msix_p; /* MSI-X info, if supported */ 282 283 /* Next three fields show current status for the device */ 284 uint_t devi_intr_curr_type; /* Interrupt type being used */ 285 uint_t devi_intr_sup_nintrs; /* #intr supported */ 286 uint_t devi_intr_curr_nintrs; /* #intr currently being used */ 287 /* 288 * #intr currently being enabled 289 * (for MSI block enable, the valuse is either 1 or 0.) 290 */ 291 uint_t devi_intr_curr_nenables; 292 293 ddi_intr_handle_t *devi_intr_handle_p; /* Hdl for legacy intr APIs */ 294 295 #if defined(__i386) || defined(__amd64) 296 /* Save the PCI config space handle */ 297 ddi_acc_handle_t devi_cfg_handle; 298 int devi_cap_ptr; /* MSI or MSI-X cap pointer */ 299 #endif 300 301 ddi_irm_req_t *devi_irm_req_p; /* IRM request information */ 302 } devinfo_intr_t; 303 304 #define NEXUS_HAS_INTR_OP(dip) \ 305 ((DEVI(dip)->devi_ops->devo_bus_ops) && \ 306 (DEVI(dip)->devi_ops->devo_bus_ops->busops_rev >= BUSO_REV_9) && \ 307 (DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op)) 308 309 int i_ddi_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t op, 310 ddi_intr_handle_impl_t *hdlp, void *result); 311 312 int i_ddi_add_softint(ddi_softint_hdl_impl_t *); 313 void i_ddi_remove_softint(ddi_softint_hdl_impl_t *); 314 int i_ddi_trigger_softint(ddi_softint_hdl_impl_t *, void *); 315 int i_ddi_set_softint_pri(ddi_softint_hdl_impl_t *, uint_t); 316 317 void i_ddi_intr_devi_init(dev_info_t *dip); 318 void i_ddi_intr_devi_fini(dev_info_t *dip); 319 320 uint_t i_ddi_intr_get_supported_types(dev_info_t *dip); 321 void i_ddi_intr_set_supported_types(dev_info_t *dip, int sup_type); 322 uint_t i_ddi_intr_get_current_type(dev_info_t *dip); 323 void i_ddi_intr_set_current_type(dev_info_t *dip, int intr_type); 324 uint_t i_ddi_intr_get_supported_nintrs(dev_info_t *dip, int intr_type); 325 void i_ddi_intr_set_supported_nintrs(dev_info_t *dip, int nintrs); 326 uint_t i_ddi_intr_get_current_nintrs(dev_info_t *dip); 327 void i_ddi_intr_set_current_nintrs(dev_info_t *dip, int nintrs); 328 uint_t i_ddi_intr_get_current_nenables(dev_info_t *dip); 329 void i_ddi_intr_set_current_nenables(dev_info_t *dip, int nintrs); 330 uint_t i_ddi_intr_get_current_navail(dev_info_t *dip, int intr_type); 331 uint_t i_ddi_intr_get_limit(dev_info_t *dip, int intr_type, 332 ddi_irm_pool_t *pool_p); 333 334 ddi_irm_pool_t *i_ddi_intr_get_pool(dev_info_t *dip, int intr_type); 335 336 void irm_init(void); 337 int i_ddi_irm_insert(dev_info_t *dip, int intr_type, int count); 338 int i_ddi_irm_modify(dev_info_t *dip, int nreq); 339 int i_ddi_irm_remove(dev_info_t *dip); 340 void i_ddi_irm_set_cb(dev_info_t *dip, boolean_t cb_flag); 341 int i_ddi_irm_supported(dev_info_t *dip, int type); 342 343 ddi_intr_handle_t i_ddi_get_intr_handle(dev_info_t *dip, int inum); 344 void i_ddi_set_intr_handle(dev_info_t *dip, int inum, ddi_intr_handle_t hdl); 345 346 ddi_intr_msix_t *i_ddi_get_msix(dev_info_t *dip); 347 void i_ddi_set_msix(dev_info_t *dip, ddi_intr_msix_t *msix_p); 348 349 #if defined(__i386) || defined(__amd64) 350 ddi_acc_handle_t i_ddi_get_pci_config_handle(dev_info_t *dip); 351 void i_ddi_set_pci_config_handle(dev_info_t *dip, ddi_acc_handle_t handle); 352 int i_ddi_get_msi_msix_cap_ptr(dev_info_t *dip); 353 void i_ddi_set_msi_msix_cap_ptr(dev_info_t *dip, int cap_ptr); 354 #endif 355 356 int32_t i_ddi_get_intr_weight(dev_info_t *); 357 int32_t i_ddi_set_intr_weight(dev_info_t *, int32_t); 358 359 void i_ddi_alloc_intr_phdl(ddi_intr_handle_impl_t *); 360 void i_ddi_free_intr_phdl(ddi_intr_handle_impl_t *); 361 362 #define DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, func, arg1, arg2) \ 363 hdlp->ih_cb_func = func; \ 364 hdlp->ih_cb_arg1 = arg1; \ 365 hdlp->ih_cb_arg2 = arg2; 366 367 #ifdef DEBUG 368 #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) \ 369 if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && \ 370 (hdlp->ih_flags & DDI_INTR_MSIX_DUP)) { \ 371 ASSERT(hdlp->ih_dip == hdlp->ih_main->ih_dip); \ 372 ASSERT(hdlp->ih_type == hdlp->ih_main->ih_type); \ 373 ASSERT(hdlp->ih_vector == hdlp->ih_main->ih_vector); \ 374 ASSERT(hdlp->ih_ver == hdlp->ih_main->ih_ver); \ 375 ASSERT(hdlp->ih_cap == hdlp->ih_main->ih_cap); \ 376 ASSERT(hdlp->ih_pri == hdlp->ih_main->ih_pri); \ 377 } 378 #else 379 #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) 380 #endif 381 382 #else /* _KERNEL */ 383 384 typedef struct devinfo_intr devinfo_intr_t; 385 386 #endif /* _KERNEL */ 387 388 /* 389 * Used only by old DDI interrupt interfaces. 390 */ 391 392 /* 393 * This structure represents one interrupt possible from the given 394 * device. It is used in an array for devices with multiple interrupts. 395 */ 396 struct intrspec { 397 uint_t intrspec_pri; /* interrupt priority */ 398 uint_t intrspec_vec; /* vector # (0 if none) */ 399 uint_t (*intrspec_func)(); /* function to call for interrupt, */ 400 /* If (uint_t (*)()) 0, none. */ 401 /* If (uint_t (*)()) 1, then */ 402 }; 403 404 #ifdef _KERNEL 405 406 /* 407 * Figure out how many FIXED nintrs are supported 408 */ 409 int i_ddi_get_intx_nintrs(dev_info_t *dip); 410 411 /* 412 * NOTE: 413 * The following 4 busops entry points are obsoleted with version 414 * 9 or greater. Use i_ddi_intr_op interface in place of these 415 * obsolete interfaces. 416 * 417 * Remove these busops entry points and all related data structures 418 * in future minor/major solaris release. 419 */ 420 typedef enum {DDI_INTR_CTLOPS_NONE} ddi_intr_ctlop_t; 421 422 /* 423 * Interrupt get/set affinity functions 424 */ 425 int get_intr_affinity(ddi_intr_handle_t h, processorid_t *tgt_p); 426 int set_intr_affinity(ddi_intr_handle_t h, processorid_t tgt); 427 428 /* The following are obsolete interfaces */ 429 ddi_intrspec_t i_ddi_get_intrspec(dev_info_t *dip, dev_info_t *rdip, 430 uint_t inumber); 431 432 int i_ddi_add_intrspec(dev_info_t *dip, dev_info_t *rdip, 433 ddi_intrspec_t intrspec, ddi_iblock_cookie_t *iblock_cookiep, 434 ddi_idevice_cookie_t *idevice_cookiep, 435 uint_t (*int_handler)(caddr_t int_handler_arg), 436 caddr_t int_handler_arg, int kind); 437 438 void i_ddi_remove_intrspec(dev_info_t *dip, dev_info_t *rdip, 439 ddi_intrspec_t intrspec, ddi_iblock_cookie_t iblock_cookie); 440 441 int i_ddi_intr_ctlops(dev_info_t *dip, dev_info_t *rdip, 442 ddi_intr_ctlop_t op, void *arg, void *val); 443 444 #endif /* _KERNEL */ 445 446 #ifdef __cplusplus 447 } 448 #endif 449 450 #endif /* _SYS_DDI_INTR_IMPL_H */ 451