1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_AGPDEFS_H 28 #define _SYS_AGPDEFS_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * This AGP memory type is required by some hardware like i810 video 36 * card, which need physical contiguous pages to setup hardware cursor. 37 * Usually, several tens of kilo bytes are needed in this case. 38 * We use DDI DMA interfaces to allocate such memory in agpgart driver, 39 * and it can not be exported to user applications directly by calling mmap 40 * on agpgart driver. The typical usage scenario is as the following: 41 * Firstly, Xserver get the memory physical address by calling AGPIOC_ALLOCATE 42 * on agpgart driver. Secondly, Xserver use the physical address to mmap 43 * the memory to Xserver space area by xsvc driver. 44 * 45 */ 46 #define AGP_PHYSICAL 2 /* Only used for i810, HW curosr */ 47 48 #ifdef _KERNEL 49 50 /* AGP space units */ 51 #define AGP_PAGE_SHIFT 12 52 #define AGP_PAGE_SIZE (1 << AGP_PAGE_SHIFT) 53 #define AGP_PAGE_OFFSET (AGP_PAGE_SIZE - 1) 54 #define AGP_MB2PAGES(x) ((x) << 8) 55 #define AGP_PAGES2BYTES(x) ((x) << AGP_PAGE_SHIFT) 56 #define AGP_BYTES2PAGES(x) ((x) >> AGP_PAGE_SHIFT) 57 #define AGP_PAGES2KB(x) ((x) << 2) 58 #define AGP_ALIGNED(offset) (((offset) & AGP_PAGE_OFFSET) == 0) 59 60 /* stand pci register offset */ 61 #define PCI_CONF_CAP_MASK 0x10 62 #define PCI_CONF_CAPID_MASK 0xff 63 #define PCI_CONF_NCAPID_MASK 0xff00 64 65 #define INTEL_VENDOR_ID 0x8086 66 #define AMD_VENDOR_ID 0x1022 67 #define VENDOR_ID_MASK 0xffff 68 69 /* macros for device types */ 70 #define DEVICE_IS_I810 11 /* intel i810 series video card */ 71 #define DEVICE_IS_I830 12 /* intel i830, i845, i855 series */ 72 #define DEVICE_IS_AGP 21 /* external AGP video card */ 73 #define CHIP_IS_INTEL 10 /* intel agp bridge */ 74 #define CHIP_IS_AMD 20 /* amd agp bridge */ 75 76 /* AGP bridge device id */ 77 #define AMD_BR_8151 0x74541022 78 #define INTEL_BR_810 0x71208086 79 #define INTEL_BR_810DC 0x71228086 80 #define INTEL_BR_810E 0x71248086 81 #define INTEL_BR_815 0x11308086 /* include 815G/EG/P/EP */ 82 #define INTEL_BR_830M 0x35758086 83 #define INTEL_BR_845 0x25608086 /* include 845G/P */ 84 #define INTEL_BR_855GM 0x35808086 /* include 852GM/PM */ 85 #define INTEL_BR_855PM 0x33408086 86 #define INTEL_BR_865 0x25708086 87 #define INTEL_BR_915 0x25808086 88 #define INTEL_BR_915GM 0x25908086 89 #define INTEL_BR_945 0x27708086 90 #define INTEL_BR_945GM 0x27a08086 91 #define INTEL_BR_946GZ 0x29708086 92 #define INTEL_BR_965G1 0x29808086 93 #define INTEL_BR_965Q 0x29908086 94 #define INTEL_BR_965G2 0x29a08086 95 #define INTEL_BR_965GM 0x2a008086 96 #define INTEL_BR_965GME 0x2a108086 97 #define INTEL_BR_Q35 0x29b08086 98 #define INTEL_BR_G33 0x29c08086 99 #define INTEL_BR_Q33 0x29d08086 100 #define INTEL_BR_GM45 0x2a408086 101 #define INTEL_BR_EL 0x2e008086 102 #define INTEL_BR_Q45 0x2e108086 103 #define INTEL_BR_G45 0x2e208086 104 105 /* AGP common register offset in pci configuration space */ 106 #define AGP_CONF_MISC 0x51 /* one byte */ 107 #define AGP_CONF_CAPPTR 0x34 108 #define AGP_CONF_APERBASE 0x10 109 #define AGP_CONF_STATUS 0x04 /* CAP + 0x4 */ 110 #define AGP_CONF_COMMAND 0x08 /* CAP + 0x8 */ 111 112 /* AGP target register and mask defines */ 113 #define AGP_CONF_CONTROL 0x10 /* CAP + 0x10 */ 114 #define AGP_TARGET_BAR1 1 115 #define AGP_32_APERBASE_MASK 0xffc00000 /* 4M aligned */ 116 #define AGP_64_APERBASE_MASK 0xffffc00000LL /* 4M aligned */ 117 #define AGP_CONF_APERSIZE 0x14 /* CAP + 0x14 */ 118 #define AGP_CONF_ATTBASE 0x18 /* CAP + 0x18 */ 119 #define AGP_ATTBASE_MASK 0xfffff000 120 #define AGPCTRL_GTLBEN (0x1 << 7) 121 #define AGP_APER_TYPE_MASK 0x4 122 #define AGP_APER_SIZE_MASK 0xf00 123 #define AGP_APER_128M_MASK 0x3f 124 #define AGP_APER_4G_MASK 0xf00 125 #define AGP_APER_4M 0x3f 126 #define AGP_APER_8M 0x3e 127 #define AGP_APER_16M 0x3c 128 #define AGP_APER_32M 0x38 129 #define AGP_APER_64M 0x30 130 #define AGP_APER_128M 0x20 131 #define AGP_APER_256M 0xf00 132 #define AGP_APER_512M 0xe00 133 #define AGP_APER_1024M 0xc00 134 #define AGP_APER_2048M 0x800 135 #define AGP_APER_4G 0x000 136 #define AGP_MISC_APEN 0x2 137 138 /* AGP gart table definition */ 139 #define AGP_ENTRY_VALID 0x1 140 141 /* AGP term definitions */ 142 #define AGP_CAP_ID 0x2 143 #define AGP_CAP_OFF_DEF 0xa0 144 145 /* Intel integrated video card, chipset id */ 146 #define INTEL_IGD_810 0x71218086 147 #define INTEL_IGD_810DC 0x71238086 148 #define INTEL_IGD_810E 0x71258086 149 #define INTEL_IGD_815 0x11328086 150 #define INTEL_IGD_830M 0x35778086 151 #define INTEL_IGD_845G 0x25628086 152 #define INTEL_IGD_855GM 0x35828086 153 #define INTEL_IGD_865G 0x25728086 154 #define INTEL_IGD_915 0x25828086 155 #define INTEL_IGD_915GM 0x25928086 156 #define INTEL_IGD_945 0x27728086 157 #define INTEL_IGD_945GM 0x27a28086 158 #define INTEL_IGD_946GZ 0x29728086 159 #define INTEL_IGD_965G1 0x29828086 160 #define INTEL_IGD_965Q 0x29928086 161 #define INTEL_IGD_965G2 0x29a28086 162 #define INTEL_IGD_965GM 0x2a028086 163 #define INTEL_IGD_965GME 0x2a128086 164 #define INTEL_IGD_Q35 0x29b28086 165 #define INTEL_IGD_G33 0x29c28086 166 #define INTEL_IGD_Q33 0x29d28086 167 #define INTEL_IGD_GM45 0x2a428086 168 #define INTEL_IGD_EL 0x2e028086 169 #define INTEL_IGD_Q45 0x2e128086 170 #define INTEL_IGD_G45 0x2e228086 171 172 /* register offsets in PCI config space */ 173 #define I8XX_CONF_GMADR 0x10 /* GMADR of i8xx series */ 174 #define I915_CONF_GMADR 0x18 /* GMADR of i915 series */ 175 /* (Mirror) GMCH Graphics Control Register (GGC, MGGC) */ 176 #define I8XX_CONF_GC 0x52 177 178 /* Intel integrated video card graphics mode mask */ 179 #define I8XX_GC_MODE_MASK 0x70 180 #define IX33_GC_MODE_MASK 0xf0 181 /* GTT Graphics Memory Size (9:8) in GMCH Graphics Control Register */ 182 #define IX33_GGMS_MASK 0x300 183 /* No VT mode, 1MB allocated for GTT */ 184 #define IX33_GGMS_1M 0x100 185 /* VT mode, 2MB allocated for GTT */ 186 #define IX33_GGMS_2M 0x200 187 188 /* Intel integrated video card GTT definition */ 189 #define GTT_PAGE_SHIFT 12 190 #define GTT_PAGE_SIZE (1 << GTT_PAGE_SHIFT) 191 #define GTT_PAGE_OFFSET (GTT_PAGE_SIZE - 1) 192 #define GTT_PTE_MASK (~GTT_PAGE_OFFSET) 193 #define GTT_PTE_VALID 0x1 194 #define GTT_TABLE_VALID 0x1 195 #define GTT_BASE_MASK 0xfffff000 196 #define GTT_MB_TO_PAGES(m) ((m) << 8) 197 #define GTT_POINTER_MASK 0xffffffff00000000 198 199 /* Intel i810 register offset */ 200 #define I810_POINTER_MASK 0xffffffffc0000000 201 #define I810_CONF_SMRAM 0x70 /* offset in PCI config space */ 202 #define I810_GMS_MASK 0xc0 /* smram register mask */ 203 /* 204 * GART and GTT entry format table 205 * 206 * AMD64 GART entry 207 * from bios and kernel develop guide for amd64 208 * ----------------------------- 209 * Bits Description | 210 * 0 valid | 211 * 1 coherent | 212 * 3:2 reserved | 213 * 11:4 physaddr[39:32] | 214 * 31:12 physaddr[31:12] | 215 * ----------------------------- 216 * Intel GTT entry 217 * Intel video programming manual 218 * ----------------------------- 219 * Bits descrition | 220 * 0 valid | 221 * 2:1 memory type | 222 * 29:12 PhysAddr[29:12] | 223 * 31:30 reserved | 224 * ----------------------------- 225 * AGP entry 226 * from AGP protocol 3.0 227 * ----------------------------- 228 * Bits descrition | 229 * 0 valid | 230 * 1 coherent | 231 * 3:2 reserved | 232 * 11:4 PhysAddr[39:32] | 233 * 31:12 PhysAddr[31:12] | 234 * 63:32 PhysAddr[71:40] | 235 * ----------------------------- 236 */ 237 238 /* 239 * gart and gtt table base register format 240 * 241 * AMD64 register format 242 * from bios and kernel develop guide for AMD64 243 * --------------------------------------------- 244 * Bits Description | 245 * 3:0 reserved | 246 * 31:4 physical addr 39:12 | 247 * ---------------------------------------------- 248 * INTEL AGPGART table base register format 249 * from AGP protocol 3.0 p142, only support 32 bits 250 * --------------------------------------------- 251 * Bits Description | 252 * 11:0 reserved | 253 * 31:12 physical addr 31:12 | 254 * 63:32 physical addr 63:32 | 255 * --------------------------------------------- 256 * INTEL i810 GTT table base register format 257 * _____________________________________________ 258 * Bits Description | 259 * 0 GTT table enable bit | 260 * 11:1 reserved | 261 * 31:12 physical addr 31:12 | 262 * --------------------------------------------- 263 */ 264 265 /* Intel agp bridge specific */ 266 #define AGP_INTEL_POINTER_MASK 0xffffffff00000000 267 268 /* Amd64 cpu gart device reigster offset */ 269 #define AMD64_APERTURE_CONTROL 0x90 270 #define AMD64_APERTURE_BASE 0x94 271 #define AMD64_GART_CACHE_CTL 0x9c 272 #define AMD64_GART_BASE 0x98 273 274 /* Amd64 cpu gart bits */ 275 #define AMD64_APERBASE_SHIFT 25 276 #define AMD64_APERBASE_MASK 0x00007fff 277 #define AMD64_GARTBASE_SHIFT 8 278 #define AMD64_GARTBASE_MASK 0xfffffff0 279 #define AMD64_POINTER_MASK 0xffffff0000000000 280 #define AMD64_INVALID_CACHE 0x1 281 #define AMD64_GART_SHIFT 12 282 #define AMD64_RESERVE_SHIFT 4 283 #define AMD64_APERSIZE_MASK 0xe 284 #define AMD64_GARTEN 0x1 285 #define AMD64_DISGARTCPU 0x10 286 #define AMD64_DISGARTIO 0x20 287 #define AMD64_ENTRY_VALID 0x1 288 289 /* Other common routines */ 290 #define MB2BYTES(m) ((m) << 20) 291 #define BYTES2MB(m) ((m) >> 20) 292 #define GIGA_MASK 0xC0000000 293 #define UI32_MASK 0xffffffffU 294 #define MAXAPERMEGAS 0x1000 /* Aper size no more than 4G */ 295 296 #endif /* _KERNEL */ 297 298 #ifdef __cplusplus 299 } 300 #endif 301 302 #endif /* _SYS_AGPDEFS_H */ 303