1 /* 2 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 #ifndef _SYS_AGPDEFS_H 7 #define _SYS_AGPDEFS_H 8 9 #pragma ident "%Z%%M% %I% %E% SMI" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /* 16 * This AGP memory type is required by some hadrware like i810 video 17 * card, which need physical contiguous pages to setup hardware cursor. 18 * Usually, several tens of kilo bytes are needed in this case. 19 * We use DDI DMA interfaces to allocate such memory in agpgart driver, 20 * and it can not be exported to user applications directly by calling mmap 21 * on agpgart driver. The typical usage scenario is as the following: 22 * Firstly, Xserver get the memory physical address by calling AGPIOC_ALLOCATE 23 * on agpgart driver. Secondly, Xserver use the physical address to mmap 24 * the memory to Xserver space area by xsvc driver. 25 * 26 */ 27 #define AGP_PHYSICAL 2 /* Only used for i810, HW curosr */ 28 29 #ifdef _KERNEL 30 31 /* AGP space units */ 32 #define AGP_PAGE_SHIFT 12 33 #define AGP_PAGE_SIZE (1 << AGP_PAGE_SHIFT) 34 #define AGP_PAGE_OFFSET (AGP_PAGE_SIZE - 1) 35 #define AGP_MB2PAGES(x) ((x) << 8) 36 #define AGP_PAGES2BYTES(x) ((x) << AGP_PAGE_SHIFT) 37 #define AGP_BYTES2PAGES(x) ((x) >> AGP_PAGE_SHIFT) 38 #define AGP_PAGES2KB(x) ((x) << 2) 39 #define AGP_ALIGNED(offset) (((offset) & AGP_PAGE_OFFSET) == 0) 40 41 /* stand pci register offset */ 42 #define PCI_CONF_CAP_MASK 0x10 43 #define PCI_CONF_CAPID_MASK 0xff 44 #define PCI_CONF_NCAPID_MASK 0xff00 45 46 #define INTEL_VENDOR_ID 0x8086 47 #define AMD_VENDOR_ID 0x1022 48 #define VENDOR_ID_MASK 0xffff 49 50 /* macros for device types */ 51 #define DEVICE_IS_I810 11 /* intel i810 series video card */ 52 #define DEVICE_IS_I830 12 /* intel i830, i845, i855 series */ 53 #define DEVICE_IS_AGP 21 /* external AGP video card */ 54 #define CHIP_IS_INTEL 10 /* intel agp bridge */ 55 #define CHIP_IS_AMD 20 /* amd agp bridge */ 56 57 /* AGP bridge device id */ 58 #define AMD_BR_8151 0x74541022 59 #define INTEL_BR_810 0x71208086 60 #define INTEL_BR_810DC 0x71228086 61 #define INTEL_BR_810E 0x71248086 62 #define INTEL_BR_815 0x11308086 /* include 815G/EG/P/EP */ 63 #define INTEL_BR_830M 0x35758086 64 #define INTEL_BR_845 0x25608086 /* include 845G/P */ 65 #define INTEL_BR_855GM 0x35808086 /* include 852GM/PM */ 66 #define INTEL_BR_855PM 0x33408086 67 #define INTEL_BR_865 0x25708086 68 69 /* AGP common register offset in pci configuration space */ 70 #define AGP_CONF_MISC 0x51 /* one byte */ 71 #define AGP_CONF_CAPPTR 0x34 72 #define AGP_CONF_APERBASE 0x10 73 #define AGP_CONF_STATUS 0x04 /* CAP + 0x4 */ 74 #define AGP_CONF_COMMAND 0x08 /* CAP + 0x8 */ 75 76 /* AGP target register and mask defines */ 77 #define AGP_CONF_CONTROL 0x10 /* CAP + 0x10 */ 78 #define AGP_TARGET_BAR1 1 79 #define AGP_32_APERBASE_MASK 0xffc00000 /* 4M aligned */ 80 #define AGP_64_APERBASE_MASK 0xffffc00000LL /* 4M aligned */ 81 #define AGP_CONF_APERSIZE 0x14 /* CAP + 0x14 */ 82 #define AGP_CONF_ATTBASE 0x18 /* CAP + 0x18 */ 83 #define AGP_ATTBASE_MASK 0xfffff000 84 #define AGPCTRL_GTLBEN (0x1 << 7) 85 #define AGP_APER_TYPE_MASK 0x4 86 #define AGP_APER_SIZE_MASK 0xf00 87 #define AGP_APER_128M_MASK 0x3f 88 #define AGP_APER_4G_MASK 0xf00 89 #define AGP_APER_4M 0x3f 90 #define AGP_APER_8M 0x3e 91 #define AGP_APER_16M 0x3c 92 #define AGP_APER_32M 0x38 93 #define AGP_APER_64M 0x30 94 #define AGP_APER_128M 0x20 95 #define AGP_APER_256M 0xf00 96 #define AGP_APER_512M 0xe00 97 #define AGP_APER_1024M 0xc00 98 #define AGP_APER_2048M 0x800 99 #define AGP_APER_4G 0x000 100 #define AGP_MISC_APEN 0x2 101 102 /* AGP gart table definition */ 103 #define AGP_ENTRY_VALID 0x1 104 105 /* AGP term definitions */ 106 #define AGP_CAP_ID 0x2 107 #define AGP_CAP_OFF_DEF 0xa0 108 109 /* Intel integrated video card, chipset id */ 110 #define INTEL_IGD_810 0x71218086 111 #define INTEL_IGD_810DC 0x71238086 112 #define INTEL_IGD_810E 0x71258086 113 #define INTEL_IGD_815 0x11328086 114 #define INTEL_IGD_830M 0x35778086 115 #define INTEL_IGD_845G 0x25628086 116 #define INTEL_IGD_855GM 0x35828086 117 #define INTEL_IGD_865G 0x25728086 118 #define I8XX_CONF_GMADR 0x10 /* offset in PCI config space */ 119 #define I8XX_CONF_GC 0x52 /* offset in PCI config space */ 120 121 /* Intel integrated video card graphics mode mask */ 122 #define I8XX_GC_MODE_MASK 0x70 123 #define I8XX_GC_MODE0 0x00 124 #define I8XX_GC_MODE1 0x10 125 #define I8XX_GC_MODE2 0x20 126 #define I8XX_GC_MODE3 0x30 127 #define I8XX_GC_MODE4 0x40 128 #define I8XX_GC_MODE5 0x50 129 130 /* Intel integrated video card GTT definition */ 131 #define GTT_PAGE_SHIFT 12 132 #define GTT_PAGE_SIZE (1 << GTT_PAGE_SHIFT) 133 #define GTT_PAGE_OFFSET (GTT_PAGE_SIZE - 1) 134 #define GTT_PTE_MASK (~GTT_PAGE_OFFSET) 135 #define GTT_PTE_VALID 0x1 136 #define GTT_TABLE_VALID 0x1 137 #define GTT_BASE_MASK 0xfffff000 138 #define GTT_MB_TO_PAGES(m) ((m) << 8) 139 #define GTT_POINTER_MASK 0xffffffff 140 141 /* Intel i810 register offset */ 142 #define I810_POINTER_MASK 0x3fffffff 143 #define I810_CONF_SMRAM 0x70 /* offset in PCI config space */ 144 #define I810_GMS_MASK 0xc0 /* smram register mask */ 145 /* 146 * GART and GTT entry format table 147 * 148 * AMD64 GART entry 149 * from bios and kernel develop guide for amd64 150 * ----------------------------- 151 * Bits Description | 152 * 0 valid | 153 * 1 coherent | 154 * 3:2 reserved | 155 * 11:4 physaddr[39:32] | 156 * 31:12 physaddr[31:12] | 157 * ----------------------------- 158 * Intel GTT entry 159 * Intel video programming manual 160 * ----------------------------- 161 * Bits descrition | 162 * 0 valid | 163 * 2:1 memory type | 164 * 29:12 PhysAddr[29:12] | 165 * 31:30 reserved | 166 * ----------------------------- 167 * AGP entry 168 * from AGP protocol 3.0 169 * ----------------------------- 170 * Bits descrition | 171 * 0 valid | 172 * 1 coherent | 173 * 3:2 reserved | 174 * 11:4 PhysAddr[39:32] | 175 * 31:12 PhysAddr[31:12] | 176 * 63:32 PhysAddr[71:40] | 177 * ----------------------------- 178 */ 179 180 /* 181 * gart and gtt table base register format 182 * 183 * AMD64 register format 184 * from bios and kernel develop guide for AMD64 185 * --------------------------------------------- 186 * Bits Description | 187 * 3:0 reserved | 188 * 31:4 physical addr 39:12 | 189 * ---------------------------------------------- 190 * INTEL AGPGART table base register format 191 * from AGP protocol 3.0 p142, only support 32 bits 192 * --------------------------------------------- 193 * Bits Description | 194 * 11:0 reserved | 195 * 31:12 physical addr 31:12 | 196 * 63:32 physical addr 63:32 | 197 * --------------------------------------------- 198 * INTEL i810 GTT table base register format 199 * _____________________________________________ 200 * Bits Description | 201 * 0 GTT table enable bit | 202 * 11:1 reserved | 203 * 31:12 physical addr 31:12 | 204 * --------------------------------------------- 205 */ 206 207 /* Intel agp bridge specific */ 208 #define AGP_INTEL_POINTER_MASK 0xffffffff 209 210 /* Amd64 cpu gart device reigster offset */ 211 #define AMD64_APERTURE_CONTROL 0x90 212 #define AMD64_APERTURE_BASE 0x94 213 #define AMD64_GART_CACHE_CTL 0x9c 214 #define AMD64_GART_BASE 0x98 215 216 /* Amd64 cpu gart bits */ 217 #define AMD64_APERBASE_SHIFT 25 218 #define AMD64_APERBASE_MASK 0x00007fff 219 #define AMD64_GARTBASE_SHIFT 8 220 #define AMD64_GARTBASE_MASK 0xfffffff0 221 #define AMD64_POINTER_MASK 0xffffffffff 222 #define AMD64_INVALID_CACHE 0x1 223 #define AMD64_GART_SHIFT 12 224 #define AMD64_RESERVE_SHIFT 4 225 #define AMD64_APERSIZE_MASK 0xe 226 #define AMD64_GARTEN 0x1 227 #define AMD64_DISGARTCPU 0x10 228 #define AMD64_DISGARTIO 0x20 229 #define AMD64_ENTRY_VALID 0x1 230 231 /* Other common routines */ 232 #define MB2BYTES(m) ((m) << 20) 233 #define BYTES2MB(m) ((m) >> 20) 234 #define GIGA_MASK 0xC0000000 235 #define UI32_MASK 0xffffffffU 236 #define MAXAPERMEGAS 0x1000 /* Aper size no more than 4G */ 237 238 #endif /* _KERNEL */ 239 240 #ifdef __cplusplus 241 } 242 #endif 243 244 #endif /* _SYS_AGPDEFS_H */ 245