1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 #ifndef _SYS_AGPDEFS_H 7 #define _SYS_AGPDEFS_H 8 9 #pragma ident "%Z%%M% %I% %E% SMI" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /* 16 * This AGP memory type is required by some hadrware like i810 video 17 * card, which need physical contiguous pages to setup hardware cursor. 18 * Usually, several tens of kilo bytes are needed in this case. 19 * We use DDI DMA interfaces to allocate such memory in agpgart driver, 20 * and it can not be exported to user applications directly by calling mmap 21 * on agpgart driver. The typical usage scenario is as the following: 22 * Firstly, Xserver get the memory physical address by calling AGPIOC_ALLOCATE 23 * on agpgart driver. Secondly, Xserver use the physical address to mmap 24 * the memory to Xserver space area by xsvc driver. 25 * 26 */ 27 #define AGP_PHYSICAL 2 /* Only used for i810, HW curosr */ 28 29 #ifdef _KERNEL 30 31 /* AGP space units */ 32 #define AGP_PAGE_SHIFT 12 33 #define AGP_PAGE_SIZE (1 << AGP_PAGE_SHIFT) 34 #define AGP_PAGE_OFFSET (AGP_PAGE_SIZE - 1) 35 #define AGP_MB2PAGES(x) ((x) << 8) 36 #define AGP_PAGES2BYTES(x) ((x) << AGP_PAGE_SHIFT) 37 #define AGP_BYTES2PAGES(x) ((x) >> AGP_PAGE_SHIFT) 38 #define AGP_PAGES2KB(x) ((x) << 2) 39 #define AGP_ALIGNED(offset) (((offset) & AGP_PAGE_OFFSET) == 0) 40 41 /* stand pci register offset */ 42 #define PCI_CONF_CAP_MASK 0x10 43 #define PCI_CONF_CAPID_MASK 0xff 44 #define PCI_CONF_NCAPID_MASK 0xff00 45 46 #define INTEL_VENDOR_ID 0x8086 47 #define AMD_VENDOR_ID 0x1022 48 #define VENDOR_ID_MASK 0xffff 49 50 /* macros for device types */ 51 #define DEVICE_IS_I810 11 /* intel i810 series video card */ 52 #define DEVICE_IS_I830 12 /* intel i830, i845, i855 series */ 53 #define DEVICE_IS_AGP 21 /* external AGP video card */ 54 #define CHIP_IS_INTEL 10 /* intel agp bridge */ 55 #define CHIP_IS_AMD 20 /* amd agp bridge */ 56 57 /* AGP bridge device id */ 58 #define AMD_BR_8151 0x74541022 59 #define INTEL_BR_810 0x71208086 60 #define INTEL_BR_810DC 0x71228086 61 #define INTEL_BR_810E 0x71248086 62 #define INTEL_BR_815 0x11308086 /* include 815G/EG/P/EP */ 63 #define INTEL_BR_830M 0x35758086 64 #define INTEL_BR_845 0x25608086 /* include 845G/P */ 65 #define INTEL_BR_855GM 0x35808086 /* include 852GM/PM */ 66 #define INTEL_BR_855PM 0x33408086 67 #define INTEL_BR_865 0x25708086 68 #define INTEL_BR_910 0x25808086 69 #define INTEL_BR_910M 0x25908086 70 #define INTEL_BR_945 0x27708086 71 #define INTEL_BR_945GM 0x27a08086 72 73 /* AGP common register offset in pci configuration space */ 74 #define AGP_CONF_MISC 0x51 /* one byte */ 75 #define AGP_CONF_CAPPTR 0x34 76 #define AGP_CONF_APERBASE 0x10 77 #define AGP_CONF_STATUS 0x04 /* CAP + 0x4 */ 78 #define AGP_CONF_COMMAND 0x08 /* CAP + 0x8 */ 79 80 /* AGP target register and mask defines */ 81 #define AGP_CONF_CONTROL 0x10 /* CAP + 0x10 */ 82 #define AGP_TARGET_BAR1 1 83 #define AGP_32_APERBASE_MASK 0xffc00000 /* 4M aligned */ 84 #define AGP_64_APERBASE_MASK 0xffffc00000LL /* 4M aligned */ 85 #define AGP_CONF_APERSIZE 0x14 /* CAP + 0x14 */ 86 #define AGP_CONF_ATTBASE 0x18 /* CAP + 0x18 */ 87 #define AGP_ATTBASE_MASK 0xfffff000 88 #define AGPCTRL_GTLBEN (0x1 << 7) 89 #define AGP_APER_TYPE_MASK 0x4 90 #define AGP_APER_SIZE_MASK 0xf00 91 #define AGP_APER_128M_MASK 0x3f 92 #define AGP_APER_4G_MASK 0xf00 93 #define AGP_APER_4M 0x3f 94 #define AGP_APER_8M 0x3e 95 #define AGP_APER_16M 0x3c 96 #define AGP_APER_32M 0x38 97 #define AGP_APER_64M 0x30 98 #define AGP_APER_128M 0x20 99 #define AGP_APER_256M 0xf00 100 #define AGP_APER_512M 0xe00 101 #define AGP_APER_1024M 0xc00 102 #define AGP_APER_2048M 0x800 103 #define AGP_APER_4G 0x000 104 #define AGP_MISC_APEN 0x2 105 106 /* AGP gart table definition */ 107 #define AGP_ENTRY_VALID 0x1 108 109 /* AGP term definitions */ 110 #define AGP_CAP_ID 0x2 111 #define AGP_CAP_OFF_DEF 0xa0 112 113 /* Intel integrated video card, chipset id */ 114 #define INTEL_IGD_810 0x71218086 115 #define INTEL_IGD_810DC 0x71238086 116 #define INTEL_IGD_810E 0x71258086 117 #define INTEL_IGD_815 0x11328086 118 #define INTEL_IGD_830M 0x35778086 119 #define INTEL_IGD_845G 0x25628086 120 #define INTEL_IGD_855GM 0x35828086 121 #define INTEL_IGD_865G 0x25728086 122 #define INTEL_IGD_910 0x25828086 123 #define INTEL_IGD_910M 0x25928086 124 #define INTEL_IGD_945 0x27728086 125 #define INTEL_IGD_945GM 0x27a28086 126 #define I8XX_CONF_GMADR 0x10 /* offset in PCI config space */ 127 #define I915_CONF_GMADR 0x18 /* offset in PCI config space */ 128 #define I8XX_CONF_GC 0x52 /* offset in PCI config space */ 129 130 /* Intel integrated video card graphics mode mask */ 131 #define I8XX_GC_MODE_MASK 0x70 132 #define I8XX_GC_MODE0 0x00 133 #define I8XX_GC_MODE1 0x10 134 #define I8XX_GC_MODE2 0x20 135 #define I8XX_GC_MODE3 0x30 136 #define I8XX_GC_MODE4 0x40 137 #define I8XX_GC_MODE5 0x50 138 139 /* Intel integrated video card GTT definition */ 140 #define GTT_PAGE_SHIFT 12 141 #define GTT_PAGE_SIZE (1 << GTT_PAGE_SHIFT) 142 #define GTT_PAGE_OFFSET (GTT_PAGE_SIZE - 1) 143 #define GTT_PTE_MASK (~GTT_PAGE_OFFSET) 144 #define GTT_PTE_VALID 0x1 145 #define GTT_TABLE_VALID 0x1 146 #define GTT_BASE_MASK 0xfffff000 147 #define GTT_MB_TO_PAGES(m) ((m) << 8) 148 #define GTT_POINTER_MASK 0xffffffff 149 150 /* Intel i810 register offset */ 151 #define I810_POINTER_MASK 0x3fffffff 152 #define I810_CONF_SMRAM 0x70 /* offset in PCI config space */ 153 #define I810_GMS_MASK 0xc0 /* smram register mask */ 154 /* 155 * GART and GTT entry format table 156 * 157 * AMD64 GART entry 158 * from bios and kernel develop guide for amd64 159 * ----------------------------- 160 * Bits Description | 161 * 0 valid | 162 * 1 coherent | 163 * 3:2 reserved | 164 * 11:4 physaddr[39:32] | 165 * 31:12 physaddr[31:12] | 166 * ----------------------------- 167 * Intel GTT entry 168 * Intel video programming manual 169 * ----------------------------- 170 * Bits descrition | 171 * 0 valid | 172 * 2:1 memory type | 173 * 29:12 PhysAddr[29:12] | 174 * 31:30 reserved | 175 * ----------------------------- 176 * AGP entry 177 * from AGP protocol 3.0 178 * ----------------------------- 179 * Bits descrition | 180 * 0 valid | 181 * 1 coherent | 182 * 3:2 reserved | 183 * 11:4 PhysAddr[39:32] | 184 * 31:12 PhysAddr[31:12] | 185 * 63:32 PhysAddr[71:40] | 186 * ----------------------------- 187 */ 188 189 /* 190 * gart and gtt table base register format 191 * 192 * AMD64 register format 193 * from bios and kernel develop guide for AMD64 194 * --------------------------------------------- 195 * Bits Description | 196 * 3:0 reserved | 197 * 31:4 physical addr 39:12 | 198 * ---------------------------------------------- 199 * INTEL AGPGART table base register format 200 * from AGP protocol 3.0 p142, only support 32 bits 201 * --------------------------------------------- 202 * Bits Description | 203 * 11:0 reserved | 204 * 31:12 physical addr 31:12 | 205 * 63:32 physical addr 63:32 | 206 * --------------------------------------------- 207 * INTEL i810 GTT table base register format 208 * _____________________________________________ 209 * Bits Description | 210 * 0 GTT table enable bit | 211 * 11:1 reserved | 212 * 31:12 physical addr 31:12 | 213 * --------------------------------------------- 214 */ 215 216 /* Intel agp bridge specific */ 217 #define AGP_INTEL_POINTER_MASK 0xffffffff 218 219 /* Amd64 cpu gart device reigster offset */ 220 #define AMD64_APERTURE_CONTROL 0x90 221 #define AMD64_APERTURE_BASE 0x94 222 #define AMD64_GART_CACHE_CTL 0x9c 223 #define AMD64_GART_BASE 0x98 224 225 /* Amd64 cpu gart bits */ 226 #define AMD64_APERBASE_SHIFT 25 227 #define AMD64_APERBASE_MASK 0x00007fff 228 #define AMD64_GARTBASE_SHIFT 8 229 #define AMD64_GARTBASE_MASK 0xfffffff0 230 #define AMD64_POINTER_MASK 0xffffffffff 231 #define AMD64_INVALID_CACHE 0x1 232 #define AMD64_GART_SHIFT 12 233 #define AMD64_RESERVE_SHIFT 4 234 #define AMD64_APERSIZE_MASK 0xe 235 #define AMD64_GARTEN 0x1 236 #define AMD64_DISGARTCPU 0x10 237 #define AMD64_DISGARTIO 0x20 238 #define AMD64_ENTRY_VALID 0x1 239 240 /* Other common routines */ 241 #define MB2BYTES(m) ((m) << 20) 242 #define BYTES2MB(m) ((m) >> 20) 243 #define GIGA_MASK 0xC0000000 244 #define UI32_MASK 0xffffffffU 245 #define MAXAPERMEGAS 0x1000 /* Aper size no more than 4G */ 246 247 #endif /* _KERNEL */ 248 249 #ifdef __cplusplus 250 } 251 #endif 252 253 #endif /* _SYS_AGPDEFS_H */ 254