1 /* 2 * sfe_util.h: header to support the gem layer used by Masa Murayama 3 * 4 * Copyright (c) 2002-2007 Masayuki Murayama. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the author nor the names of its contributors may be 17 * used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 */ 33 #pragma ident "%Z%%M% %I% %E% SMI" /* sfe device driver */ 34 35 #ifndef _SFE_UTIL_H_ 36 #define _SFE_UTIL_H_ 37 #include <sys/mac.h> 38 #include <sys/mac_ether.h> 39 40 /* 41 * Useful macros and typedefs 42 */ 43 44 #define GEM_NAME_LEN 32 45 46 #define GEM_TX_TIMEOUT (drv_usectohz(5*1000000)) 47 #define GEM_TX_TIMEOUT_INTERVAL (drv_usectohz(1*1000000)) 48 #define GEM_LINK_WATCH_INTERVAL (drv_usectohz(1*1000000)) /* 1 sec */ 49 50 /* general return code */ 51 #define GEM_SUCCESS 0 52 #define GEM_FAILURE (-1) 53 54 /* return code of gem_tx_done */ 55 #define INTR_RESTART_TX 0x80000000 56 57 typedef int32_t seqnum_t; 58 59 /* 60 * I/O instructions 61 */ 62 #define OUTB(dp, p, v) \ 63 ddi_put8((dp)->regs_handle, \ 64 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 65 #define OUTW(dp, p, v) \ 66 ddi_put16((dp)->regs_handle, \ 67 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 68 #define OUTL(dp, p, v) \ 69 ddi_put32((dp)->regs_handle, \ 70 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 71 #define INB(dp, p) \ 72 ddi_get8((dp)->regs_handle, \ 73 (void *)(((caddr_t)(dp)->base_addr) + (p))) 74 #define INW(dp, p) \ 75 ddi_get16((dp)->regs_handle, \ 76 (void *)(((caddr_t)(dp)->base_addr) + (p))) 77 #define INL(dp, p) \ 78 ddi_get32((dp)->regs_handle, \ 79 (void *)(((caddr_t)(dp)->base_addr) + (p))) 80 81 struct gem_stats { 82 uint32_t intr; 83 84 uint32_t crc; 85 uint32_t errrcv; 86 uint32_t overflow; 87 uint32_t frame; 88 uint32_t missed; 89 uint32_t runt; 90 uint32_t frame_too_long; 91 uint32_t norcvbuf; 92 uint32_t sqe; 93 94 uint32_t collisions; 95 uint32_t first_coll; 96 uint32_t multi_coll; 97 uint32_t excoll; 98 uint32_t xmit_internal_err; 99 uint32_t nocarrier; 100 uint32_t defer; 101 uint32_t errxmt; 102 uint32_t underflow; 103 uint32_t xmtlatecoll; 104 uint32_t noxmtbuf; 105 uint32_t jabber; 106 107 uint64_t rbytes; 108 uint64_t obytes; 109 uint64_t rpackets; 110 uint64_t opackets; 111 uint32_t rbcast; 112 uint32_t obcast; 113 uint32_t rmcast; 114 uint32_t omcast; 115 uint32_t rcv_internal_err; 116 }; 117 118 #define GEM_MAXTXSEGS 4 119 #define GEM_MAXRXSEGS 1 120 121 #define GEM_MAXTXFRAGS 8 122 #define GEM_MAXRXFRAGS 4 123 124 /* TX buffer management */ 125 struct txbuf { 126 struct txbuf *txb_next; 127 128 /* pointer to original mblk */ 129 mblk_t *txb_mp; 130 131 /* dma mapping for current packet */ 132 ddi_dma_cookie_t txb_dmacookie[GEM_MAXTXFRAGS]; 133 uint_t txb_nfrags; 134 135 /* bounce buffer management */ 136 ddi_dma_handle_t txb_bdh; 137 ddi_acc_handle_t txb_bah; 138 caddr_t txb_buf; /* vaddr of bounce buffer */ 139 uint64_t txb_buf_dma; /* paddr of bounce buffer */ 140 141 /* timeout management */ 142 clock_t txb_stime; 143 144 /* Hardware descriptor info */ 145 seqnum_t txb_desc; 146 int txb_ndescs; 147 uint64_t txb_flag; 148 }; 149 150 151 /* RX buffer management */ 152 struct rxbuf { 153 /* Hardware independant section */ 154 struct rxbuf *rxb_next; 155 struct gem_dev *rxb_devp; 156 157 /* dma mapping management */ 158 ddi_dma_handle_t rxb_dh; 159 caddr_t rxb_buf; 160 size_t rxb_buf_len; 161 ddi_dma_cookie_t rxb_dmacookie[GEM_MAXRXFRAGS]; 162 uint_t rxb_nfrags; 163 164 /* bounce buffer management */ 165 ddi_acc_handle_t rxb_bah; 166 }; 167 168 struct mcast_addr { 169 struct ether_addr addr; 170 uint32_t hash; 171 }; 172 173 #define GEM_MAXMC 64 174 #define GEM_MCALLOC (sizeof (struct mcast_addr) * GEM_MAXMC) 175 176 #define SUB(x, y) ((seqnum_t)((x) - (y))) 177 #define SLOT(seqnum, size) (((unsigned int)(seqnum)) & ((size)-1)) 178 179 /* 180 * mac soft state 181 */ 182 struct gem_dev { 183 dev_info_t *dip; 184 mac_handle_t mh; 185 char name[GEM_NAME_LEN]; 186 void *base_addr; 187 ddi_acc_handle_t regs_handle; 188 ddi_iblock_cookie_t iblock_cookie; 189 190 /* MAC address information */ 191 struct ether_addr cur_addr; 192 struct ether_addr dev_addr; 193 194 /* Descriptor rings, io area */ 195 ddi_dma_handle_t desc_dma_handle; 196 ddi_acc_handle_t desc_acc_handle; 197 caddr_t rx_ring; 198 caddr_t tx_ring; 199 caddr_t io_area; 200 /* caddr_t rx_buf; */ 201 202 uint64_t rx_ring_dma; 203 uint64_t tx_ring_dma; 204 uint64_t io_area_dma; 205 206 /* RX slot ring management */ 207 kmutex_t intrlock; 208 boolean_t intr_busy; 209 seqnum_t rx_active_head; 210 seqnum_t rx_active_tail; 211 mac_resource_handle_t mac_rx_ring_ha; 212 /* Rx buffer management */ 213 struct rxbuf *rx_buf_head; 214 struct rxbuf *rx_buf_tail; 215 struct rxbuf *rx_buf_freelist; 216 int rx_buf_allocated; 217 int rx_buf_freecnt; 218 int rx_buf_len; 219 220 /* TX descriptor ring management */ 221 seqnum_t tx_desc_head; 222 seqnum_t tx_desc_tail; 223 seqnum_t tx_desc_intr; 224 225 /* TX buffur ring management */ 226 kmutex_t xmitlock; 227 kcondvar_t tx_drain_cv; 228 seqnum_t tx_active_head; 229 seqnum_t tx_active_tail; 230 seqnum_t tx_softq_head; 231 seqnum_t tx_softq_tail; 232 seqnum_t tx_free_head; 233 seqnum_t tx_free_tail; 234 235 /* TX buffer resource management */ 236 struct txbuf *tx_buf; 237 seqnum_t tx_slots_base; 238 239 /* TX state management */ 240 int tx_busy; 241 int tx_reclaim_busy; 242 boolean_t tx_blocked; 243 244 /* NIC state */ 245 volatile boolean_t mac_active; /* tx and rx are running */ 246 volatile int nic_state; /* logical driver state */ 247 #define NIC_STATE_STOPPED 0 248 #define NIC_STATE_INITIALIZED 1 249 #define NIC_STATE_ONLINE 2 250 volatile boolean_t mac_suspended; 251 252 /* robustness: timer and watchdog */ 253 volatile timeout_id_t timeout_id; 254 255 256 /* MII management */ 257 boolean_t anadv_autoneg:1; 258 boolean_t anadv_1000fdx:1; 259 boolean_t anadv_1000hdx:1; 260 boolean_t anadv_100t4:1; 261 boolean_t anadv_100fdx:1; 262 boolean_t anadv_100hdx:1; 263 boolean_t anadv_10fdx:1; 264 boolean_t anadv_10hdx:1; 265 boolean_t anadv_flow_control:2; 266 boolean_t mii_advert_ro:1; 267 268 boolean_t full_duplex:1; 269 int speed:3; 270 #define GEM_SPD_10 0 271 #define GEM_SPD_100 1 272 #define GEM_SPD_1000 2 273 unsigned int flow_control:2; 274 #define FLOW_CONTROL_NONE 0 275 #define FLOW_CONTROL_SYMMETRIC 1 276 #define FLOW_CONTROL_TX_PAUSE 2 277 #define FLOW_CONTROL_RX_PAUSE 3 278 279 boolean_t mii_supress_msg:1; 280 281 uint32_t mii_phy_id; 282 uint16_t mii_status; 283 uint16_t mii_advert; 284 uint16_t mii_lpable; 285 uint16_t mii_exp; 286 uint16_t mii_ctl1000; 287 uint16_t mii_stat1000; 288 uint16_t mii_xstatus; 289 int8_t mii_phy_addr; /* must be signed */ 290 291 uint8_t mii_state; 292 #define MII_STATE_UNKNOWN 0 293 #define MII_STATE_RESETTING 1 294 #define MII_STATE_AUTONEGOTIATING 2 295 #define MII_STATE_AN_DONE 3 296 #define MII_STATE_MEDIA_SETUP 4 297 #define MII_STATE_LINKUP 5 298 #define MII_STATE_LINKDOWN 6 299 300 clock_t mii_last_check; /* in tick */ 301 clock_t mii_timer; /* in tick */ 302 #define MII_RESET_TIMEOUT drv_usectohz(1000*1000) 303 #define MII_AN_TIMEOUT drv_usectohz(5000*1000) 304 #define MII_LINKDOWN_TIMEOUT drv_usectohz(10000*1000) 305 clock_t mii_interval; /* in tick */ 306 307 volatile timeout_id_t link_watcher_id; 308 309 ddi_softintr_t soft_id; 310 311 /* multcast list management */ 312 int16_t mc_count; 313 int16_t mc_count_req; 314 struct mcast_addr *mc_list; 315 uint32_t rxmode; 316 #define RXMODE_PROMISC 0x01 317 #define RXMODE_ALLMULTI_REQ 0x02 318 #define RXMODE_MULTI_OVF 0x04 319 #define RXMODE_ENABLE 0x08 320 #define RXMODE_ALLMULTI (RXMODE_ALLMULTI_REQ | RXMODE_MULTI_OVF) 321 #define RXMODE_BITS \ 322 "\020" \ 323 "\004ENABLE" \ 324 "\003MULTI_OVF" \ 325 "\002ALLMULTI_REQ" \ 326 "\001PROMISC" 327 328 /* statistcs */ 329 struct gem_stats stats; 330 331 /* pointer to local structure */ 332 void *private; 333 int priv_size; 334 335 /* polling mode */ 336 int poll_pkt_hiwat; /* max pkt count */ 337 int poll_pkt_delay; /* in number of packets */ 338 339 /* descriptor area */ 340 int tx_desc_size; 341 int rx_desc_size; 342 343 /* configuration */ 344 struct gem_conf { 345 /* name */ 346 char gc_name[GEM_NAME_LEN]; 347 348 /* specification on tx and rx dma engine */ 349 long gc_tx_buf_align; 350 int gc_tx_max_frags; 351 int gc_tx_max_descs_per_pkt; 352 int gc_tx_buf_size; 353 int gc_tx_buf_limit; 354 int gc_tx_desc_unit_shift; 355 int gc_tx_ring_size; 356 int gc_tx_ring_limit; 357 int gc_tx_copy_thresh; 358 boolean_t gc_tx_auto_pad; 359 boolean_t gc_tx_desc_write_oo; 360 361 long gc_rx_buf_align; 362 int gc_rx_max_frags; 363 int gc_rx_desc_unit_shift; 364 int gc_rx_ring_size; 365 int gc_rx_copy_thresh; 366 int gc_rx_buf_max; 367 int gc_rx_header_len; 368 369 int gc_io_area_size; 370 371 /* memory mapping attributes */ 372 struct ddi_device_acc_attr gc_dev_attr; 373 struct ddi_device_acc_attr gc_buf_attr; 374 struct ddi_device_acc_attr gc_desc_attr; 375 376 /* dma attributes */ 377 ddi_dma_attr_t gc_dma_attr_desc; 378 ddi_dma_attr_t gc_dma_attr_txbuf; 379 ddi_dma_attr_t gc_dma_attr_rxbuf; 380 381 /* tx time out parameters */ 382 clock_t gc_tx_timeout; 383 clock_t gc_tx_timeout_interval; 384 385 /* auto negotiation capability */ 386 int gc_flow_control; 387 388 /* MII mode */ 389 int gc_mii_mode; 390 #define GEM_MODE_100BASETX 0 391 #define GEM_MODE_1000BASET 1 392 #define GEM_MODE_1000BASETX 2 393 394 /* MII link state watch parameters */ 395 clock_t gc_mii_linkdown_timeout; 396 clock_t gc_mii_link_watch_interval; 397 clock_t gc_mii_reset_timeout; 398 399 clock_t gc_mii_an_watch_interval; 400 clock_t gc_mii_an_timeout; 401 clock_t gc_mii_an_wait; 402 clock_t gc_mii_an_delay; 403 404 /* MII configuration */ 405 int gc_mii_addr_min; 406 int gc_mii_linkdown_action; 407 int gc_mii_linkdown_timeout_action; 408 #define MII_ACTION_NONE 0 409 #define MII_ACTION_RESET 1 410 #define MII_ACTION_RSA 2 411 boolean_t gc_mii_dont_reset; 412 boolean_t gc_mii_an_oneshot; 413 boolean_t gc_mii_hw_link_detection; 414 boolean_t gc_mii_stop_mac_on_linkdown; 415 416 /* I/O methods */ 417 418 /* mac operation */ 419 int (*gc_attach_chip)(struct gem_dev *dp); 420 int (*gc_reset_chip)(struct gem_dev *dp); 421 int (*gc_init_chip)(struct gem_dev *dp); 422 int (*gc_start_chip)(struct gem_dev *dp); 423 int (*gc_stop_chip)(struct gem_dev *dp); 424 uint32_t (*gc_multicast_hash)(struct gem_dev *dp, uint8_t *); 425 int (*gc_set_rx_filter)(struct gem_dev *dp); 426 int (*gc_set_media)(struct gem_dev *dp); 427 int (*gc_get_stats)(struct gem_dev *dp); 428 uint_t (*gc_interrupt)(struct gem_dev *dp); 429 430 /* descriptor operation */ 431 int (*gc_tx_desc_write)(struct gem_dev *dp, int slot, 432 ddi_dma_cookie_t *dmacookie, 433 int frags, uint64_t flag); 434 #define GEM_TXFLAG_INTR 0x00000001ull 435 #define GEM_TXFLAG_TCP 0x00000002ull 436 #define GEM_TXFLAG_TCP_SHIFT 1ull 437 #define GEM_TXFLAG_UDP 0x00000004ull 438 #define GEM_TXFLAG_UDP_SHIFT 2ull 439 #define GEM_TXFLAG_IPv4 0x00000008ull 440 #define GEM_TXFLAG_IPv4_SHIFT 3ull 441 #define GEM_TXFLAG_IPv6 0x00000010ull 442 #define GEM_TXFLAG_IPv6_SHIFT 4ull 443 #define GEM_TXFLAG_HEAD 0x00000020ull 444 #define GEM_TXFLAG_TAIL 0x00000040ull 445 #define GEM_TXFLAG_SWVTAG 0x00000080ull 446 #define GEM_TXFLAG_PRIVATE 0x0000ff00ull 447 #define GEM_TXFLAG_PRIVATE_SHIFT 8ull 448 #define GEM_TXFLAG_PRIVATE_MASK 0xffull 449 #define GEM_TXFLAG_VID 0x0fff0000ull 450 #define GEM_TXFLAG_VID_SHIFT 16ull 451 #define GEM_TXFLAG_VID_MASK 0xfffull 452 #define GEM_TXFLAG_CFI 0x10000000ull 453 #define GEM_TXFLAG_PRI 0xe0000000ull 454 #define GEM_TXFLAG_PRI_SHIFT 29ull 455 #define GEM_TXFLAG_PRI_MASK 0x7ull 456 #define GEM_TXFLAG_VTAG 0xffff0000ull 457 #define GEM_TXFLAG_VTAG_SHIFT 16ull 458 #define GEM_TXFLAG_HCKSTART 0x000000ff00000000ull 459 #define GEM_TXFLAG_HCKSTART_SHIFT 32ull 460 #define GEM_TXFLAG_HCKSTUFF 0x0000ff0000000000ull 461 #define GEM_TXFLAG_HCKSTUFF_SHIFT 40ull 462 463 void (*gc_tx_start) (struct gem_dev *dp, int slot, int frags); 464 void (*gc_rx_desc_write)(struct gem_dev *dp, int slot, 465 ddi_dma_cookie_t *dmacookie, int frags); 466 void (*gc_rx_start)(struct gem_dev *dp, int slot, int frags); 467 468 uint_t (*gc_tx_desc_stat) 469 (struct gem_dev *dp, int slot, int descs); 470 #define GEM_TX_DONE 0x00010000 471 #define GEM_TX_ERR 0x00020000 472 473 474 uint64_t (*gc_rx_desc_stat) 475 (struct gem_dev *dp, int slot, int frags); 476 477 #define GEM_RX_CKSUM 0xffff000000000000ull 478 #define GEM_RX_CKSUM_SHIFT 48 479 #define GEM_RX_PRI 0x0000e00000000000ull 480 #define GEM_RX_PRI_SHIFT 45 481 #define GEM_RX_CFI 0x0000100000000000ull 482 #define GEM_RX_VID 0x00000fff00000000ull 483 #define GEM_RX_VID_SHIFT 32 484 #define GEM_RX_VTAG 0x0000ffff00000000ull 485 #define GEM_RX_VTAG_SHIFT 32 486 487 #define GEM_RX_CKSUM_IPv6 0x00080000ul 488 #define GEM_RX_CKSUM_IPv6_SHIFT 19 489 #define GEM_RX_CKSUM_IPv4 0x00040000ul 490 #define GEM_RX_CKSUM_IPv4_SHIFT 18 491 #define GEM_RX_CKSUM_UDP 0x00020000ul 492 #define GEM_RX_CKSUM_UDP_SHIFT 17 493 #define GEM_RX_CKSUM_TCP 0x00010000ul 494 #define GEM_RX_CKSUM_TCP_SHIFT 16 495 #define GEM_RX_ERR 0x00008000ul 496 #define GEM_RX_DONE 0x00004000ul 497 #define GEM_RX_LEN 0x00003ffful /* 16KB - 1 */ 498 499 void (*gc_tx_desc_init)(struct gem_dev *dp, int slot); 500 void (*gc_rx_desc_init)(struct gem_dev *dp, int slot); 501 void (*gc_tx_desc_clean)(struct gem_dev *dp, int slot); 502 void (*gc_rx_desc_clean)(struct gem_dev *dp, int slot); 503 504 /* mii operations */ 505 int (*gc_mii_probe)(struct gem_dev *dp); 506 int (*gc_mii_init)(struct gem_dev *dp); 507 int (*gc_mii_config)(struct gem_dev *dp); 508 void (*gc_mii_sync)(struct gem_dev *dp); 509 uint16_t (*gc_mii_read)(struct gem_dev *dp, uint_t reg); 510 void (*gc_mii_write)(struct gem_dev *dp, 511 uint_t reg, uint16_t val); 512 void (*gc_mii_tune_phy)(struct gem_dev *dp); 513 514 /* packet in/out operation for copy-style */ 515 void (*gc_put_packet)(struct gem_dev *dp, 516 mblk_t *, void *, size_t); 517 mblk_t *(*gc_get_packet)(struct gem_dev *dp, 518 struct rxbuf *, size_t); 519 int gc_nports; 520 521 /* hw checksum */ 522 uint32_t gc_hck_rx_start; 523 } gc; 524 525 uint32_t misc_flag; 526 #define GEM_CTRL_PKT 0x00000200 527 #define GEM_SOFTINTR 0x00000100 528 #define GEM_POLL_RXONLY 0x00000080 529 #define GEM_VLAN_HARD 0x00000040 530 #define GEM_VLAN_SOFT 0x00000020 531 #define GEM_VLAN (GEM_VLAN_HARD | GEM_VLAN_SOFT) 532 #define GEM_CKSUM_HEADER_IPv4 0x00000010 533 #define GEM_CKSUM_PARTIAL 0x00000008 534 #define GEM_CKSUM_FULL_IPv6 0x00000004 535 #define GEM_CKSUM_FULL_IPv4 0x00000002 536 #define GEM_NOINTR 0x00000001 537 538 volatile timeout_id_t intr_watcher_id; 539 540 uint_t mtu; 541 542 /* performance tuning parameters */ 543 uint_t txthr; /* tx fifo threshoold */ 544 uint_t txmaxdma; /* tx max dma burst size */ 545 uint_t rxthr; /* rx fifo threshoold */ 546 uint_t rxmaxdma; /* tx max dma burst size */ 547 548 /* kstat stuff */ 549 kstat_t *ksp; 550 551 struct gem_dev *next; /* pointer to next port on the same device */ 552 553 /* ndd stuff */ 554 caddr_t nd_data_p; 555 caddr_t nd_arg_p; 556 557 #ifdef GEM_DEBUG_LEVEL 558 int tx_cnt; 559 #endif 560 }; 561 562 /* 563 * Exported functions 564 */ 565 boolean_t gem_get_mac_addr_conf(struct gem_dev *); 566 int gem_mii_probe_default(struct gem_dev *); 567 int gem_mii_config_default(struct gem_dev *); 568 boolean_t gem_mii_link_check(struct gem_dev *dp); 569 uint16_t gem_mii_read(struct gem_dev *, uint_t); 570 void gem_mii_write(struct gem_dev *, uint_t, uint16_t); 571 int gem_reclaim_txbuf(struct gem_dev *dp); 572 int gem_restart_nic(struct gem_dev *dp, uint_t flags); 573 #define GEM_RESTART_NOWAIT 0x00000002 574 #define GEM_RESTART_KEEP_BUF 0x00000001 575 boolean_t gem_tx_done(struct gem_dev *); 576 int gem_receive(struct gem_dev *); 577 int gem_receive_copy(struct gem_dev *); 578 struct gem_dev *gem_do_attach(dev_info_t *, int, 579 struct gem_conf *, void *, ddi_acc_handle_t *, void *, int); 580 581 mblk_t *gem_send_common(struct gem_dev *, mblk_t *, uint32_t); 582 #define GEM_SEND_COPY 0x00008000 583 #define GEM_SEND_CTRL 0x000000ff /* private flags for control packets */ 584 #define GEM_SEND_VTAG 0xffff0000 585 #define GEM_SEND_VTAG_SHIFT 16 586 587 mblk_t *gem_get_packet_default(struct gem_dev *, struct rxbuf *, size_t); 588 589 uint32_t gem_ether_crc_le(const uint8_t *addr, int len); 590 uint32_t gem_ether_crc_be(const uint8_t *addr, int len); 591 int gem_do_detach(dev_info_t *); 592 593 int gem_getlongprop_buf(dev_t dev, dev_info_t *dip, 594 int flags, char *name, void *buf, int *lenp); 595 int gem_getprop(dev_t dev, dev_info_t *dip, 596 int flags, char *name, int defvalue); 597 598 struct rxbuf *gem_get_rxbuf(struct gem_dev *, int); 599 600 void gem_rx_desc_dma_sync(struct gem_dev *, int, int, int); 601 void gem_tx_desc_dma_sync(struct gem_dev *, int, int, int); 602 603 int gem_resume(dev_info_t *); 604 int gem_suspend(dev_info_t *); 605 uint8_t gem_search_pci_cap(dev_info_t *dip, ddi_acc_handle_t, uint8_t); 606 int gem_pci_set_power_state(dev_info_t *, ddi_acc_handle_t, uint_t); 607 int gem_pci_regs_map_setup(dev_info_t *, uint32_t, uint32_t, 608 struct ddi_device_acc_attr *, caddr_t *, ddi_acc_handle_t *); 609 void gem_mod_init(struct dev_ops *, char *); 610 void gem_mod_fini(struct dev_ops *); 611 612 #define GEM_GET_DEV(dip) \ 613 ((struct gem_dev *)(ddi_get_driver_private(dip))) 614 #endif /* _SFE_UTIL_H_ */ 615