1 /* 2 * sfe.c : DP83815/DP83816/SiS900 Fast Ethernet MAC driver for Solaris 3 * 4 * Copyright (c) 2002-2008 Masayuki Murayama. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the author nor the names of its contributors may be 17 * used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 */ 33 34 /* 35 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 36 * Use is subject to license terms. 37 */ 38 39 /* 40 * System Header files. 41 */ 42 #include <sys/types.h> 43 #include <sys/conf.h> 44 #include <sys/debug.h> 45 #include <sys/kmem.h> 46 #include <sys/modctl.h> 47 #include <sys/errno.h> 48 #include <sys/ddi.h> 49 #include <sys/sunddi.h> 50 #include <sys/byteorder.h> 51 #include <sys/ethernet.h> 52 #include <sys/pci.h> 53 54 #include "sfe_mii.h" 55 #include "sfe_util.h" 56 #include "sfereg.h" 57 58 char ident[] = "sis900/dp83815 driver"; 59 60 /* Debugging support */ 61 #ifdef DEBUG_LEVEL 62 static int sfe_debug = DEBUG_LEVEL; 63 #if DEBUG_LEVEL > 4 64 #define CONS "^" 65 #else 66 #define CONS "!" 67 #endif 68 #define DPRINTF(n, args) if (sfe_debug > (n)) cmn_err args 69 #else 70 #define CONS "!" 71 #define DPRINTF(n, args) 72 #endif 73 74 /* 75 * Useful macros and typedefs 76 */ 77 #define ONESEC (drv_usectohz(1*1000000)) 78 #define ROUNDUP2(x, a) (((x) + (a) - 1) & ~((a) - 1)) 79 80 /* 81 * Our configuration 82 */ 83 #define MAXTXFRAGS 1 84 #define MAXRXFRAGS 1 85 86 #ifndef TX_BUF_SIZE 87 #define TX_BUF_SIZE 64 88 #endif 89 #ifndef TX_RING_SIZE 90 #if MAXTXFRAGS == 1 91 #define TX_RING_SIZE TX_BUF_SIZE 92 #else 93 #define TX_RING_SIZE (TX_BUF_SIZE * 4) 94 #endif 95 #endif 96 97 #ifndef RX_BUF_SIZE 98 #define RX_BUF_SIZE 256 99 #endif 100 #ifndef RX_RING_SIZE 101 #define RX_RING_SIZE RX_BUF_SIZE 102 #endif 103 104 #define OUR_INTR_BITS \ 105 (ISR_DPERR | ISR_SSERR | ISR_RMABT | ISR_RTABT | ISR_RXSOVR | \ 106 ISR_TXURN | ISR_TXDESC | ISR_TXERR | \ 107 ISR_RXORN | ISR_RXIDLE | ISR_RXOK | ISR_RXERR) 108 109 #define USE_MULTICAST_HASHTBL 110 111 static int sfe_tx_copy_thresh = 256; 112 static int sfe_rx_copy_thresh = 256; 113 114 /* special PHY registers for SIS900 */ 115 #define MII_CONFIG1 0x0010 116 #define MII_CONFIG2 0x0011 117 #define MII_MASK 0x0013 118 #define MII_RESV 0x0014 119 120 #define PHY_MASK 0xfffffff0 121 #define PHY_SIS900_INTERNAL 0x001d8000 122 #define PHY_ICS1893 0x0015f440 123 124 125 #define SFE_DESC_SIZE 16 /* including pads rounding up to power of 2 */ 126 127 /* 128 * Supported chips 129 */ 130 struct chip_info { 131 uint16_t venid; 132 uint16_t devid; 133 char *chip_name; 134 int chip_type; 135 #define CHIPTYPE_DP83815 0 136 #define CHIPTYPE_SIS900 1 137 }; 138 139 /* 140 * Chip dependent MAC state 141 */ 142 struct sfe_dev { 143 /* misc HW information */ 144 struct chip_info *chip; 145 uint32_t our_intr_bits; 146 uint32_t isr_pended; 147 uint32_t cr; 148 uint_t tx_drain_threshold; 149 uint_t tx_fill_threshold; 150 uint_t rx_drain_threshold; 151 uint_t rx_fill_threshold; 152 uint8_t revid; /* revision from PCI configuration */ 153 boolean_t (*get_mac_addr)(struct gem_dev *); 154 uint8_t mac_addr[ETHERADDRL]; 155 uint8_t bridge_revid; 156 }; 157 158 /* 159 * Hardware information 160 */ 161 struct chip_info sfe_chiptbl[] = { 162 { 0x1039, 0x0900, "SiS900", CHIPTYPE_SIS900, }, 163 { 0x100b, 0x0020, "DP83815/83816", CHIPTYPE_DP83815, }, 164 { 0x1039, 0x7016, "SiS7016", CHIPTYPE_SIS900, }, 165 }; 166 #define CHIPTABLESIZE (sizeof (sfe_chiptbl)/sizeof (struct chip_info)) 167 168 /* ======================================================== */ 169 170 /* mii operations */ 171 static void sfe_mii_sync_dp83815(struct gem_dev *); 172 static void sfe_mii_sync_sis900(struct gem_dev *); 173 static uint16_t sfe_mii_read_dp83815(struct gem_dev *, uint_t); 174 static uint16_t sfe_mii_read_sis900(struct gem_dev *, uint_t); 175 static void sfe_mii_write_dp83815(struct gem_dev *, uint_t, uint16_t); 176 static void sfe_mii_write_sis900(struct gem_dev *, uint_t, uint16_t); 177 static void sfe_set_eq_sis630(struct gem_dev *dp); 178 /* nic operations */ 179 static int sfe_reset_chip_sis900(struct gem_dev *); 180 static int sfe_reset_chip_dp83815(struct gem_dev *); 181 static int sfe_init_chip(struct gem_dev *); 182 static int sfe_start_chip(struct gem_dev *); 183 static int sfe_stop_chip(struct gem_dev *); 184 static int sfe_set_media(struct gem_dev *); 185 static int sfe_set_rx_filter_dp83815(struct gem_dev *); 186 static int sfe_set_rx_filter_sis900(struct gem_dev *); 187 static int sfe_get_stats(struct gem_dev *); 188 static int sfe_attach_chip(struct gem_dev *); 189 190 /* descriptor operations */ 191 static int sfe_tx_desc_write(struct gem_dev *dp, int slot, 192 ddi_dma_cookie_t *dmacookie, int frags, uint64_t flags); 193 static void sfe_tx_start(struct gem_dev *dp, int startslot, int nslot); 194 static void sfe_rx_desc_write(struct gem_dev *dp, int slot, 195 ddi_dma_cookie_t *dmacookie, int frags); 196 static uint_t sfe_tx_desc_stat(struct gem_dev *dp, int slot, int ndesc); 197 static uint64_t sfe_rx_desc_stat(struct gem_dev *dp, int slot, int ndesc); 198 199 static void sfe_tx_desc_init(struct gem_dev *dp, int slot); 200 static void sfe_rx_desc_init(struct gem_dev *dp, int slot); 201 static void sfe_tx_desc_clean(struct gem_dev *dp, int slot); 202 static void sfe_rx_desc_clean(struct gem_dev *dp, int slot); 203 204 /* interrupt handler */ 205 static uint_t sfe_interrupt(struct gem_dev *dp); 206 207 /* ======================================================== */ 208 209 /* mapping attributes */ 210 /* Data access requirements. */ 211 static struct ddi_device_acc_attr sfe_dev_attr = { 212 DDI_DEVICE_ATTR_V0, 213 DDI_STRUCTURE_LE_ACC, 214 DDI_STRICTORDER_ACC 215 }; 216 217 /* On sparc, Buffers should be native endian for speed */ 218 static struct ddi_device_acc_attr sfe_buf_attr = { 219 DDI_DEVICE_ATTR_V0, 220 DDI_NEVERSWAP_ACC, /* native endianness */ 221 DDI_STRICTORDER_ACC 222 }; 223 224 static ddi_dma_attr_t sfe_dma_attr_buf = { 225 DMA_ATTR_V0, /* dma_attr_version */ 226 0, /* dma_attr_addr_lo */ 227 0xffffffffull, /* dma_attr_addr_hi */ 228 0x00000fffull, /* dma_attr_count_max */ 229 0, /* patched later */ /* dma_attr_align */ 230 0x000003fc, /* dma_attr_burstsizes */ 231 1, /* dma_attr_minxfer */ 232 0x00000fffull, /* dma_attr_maxxfer */ 233 0xffffffffull, /* dma_attr_seg */ 234 0, /* patched later */ /* dma_attr_sgllen */ 235 1, /* dma_attr_granular */ 236 0 /* dma_attr_flags */ 237 }; 238 239 static ddi_dma_attr_t sfe_dma_attr_desc = { 240 DMA_ATTR_V0, /* dma_attr_version */ 241 16, /* dma_attr_addr_lo */ 242 0xffffffffull, /* dma_attr_addr_hi */ 243 0xffffffffull, /* dma_attr_count_max */ 244 16, /* dma_attr_align */ 245 0x000003fc, /* dma_attr_burstsizes */ 246 1, /* dma_attr_minxfer */ 247 0xffffffffull, /* dma_attr_maxxfer */ 248 0xffffffffull, /* dma_attr_seg */ 249 1, /* dma_attr_sgllen */ 250 1, /* dma_attr_granular */ 251 0 /* dma_attr_flags */ 252 }; 253 254 uint32_t sfe_use_pcimemspace = 0; 255 256 /* ======================================================== */ 257 /* 258 * HW manipulation routines 259 */ 260 /* ======================================================== */ 261 262 #define SFE_EEPROM_DELAY(dp) \ 263 { (void) INL(dp, EROMAR); (void) INL(dp, EROMAR); } 264 #define EE_CMD_READ 6 265 #define EE_CMD_SHIFT 6 266 267 static uint16_t 268 sfe_read_eeprom(struct gem_dev *dp, uint_t offset) 269 { 270 int eedi; 271 int i; 272 uint16_t ret; 273 274 /* ensure de-assert chip select */ 275 OUTL(dp, EROMAR, 0); 276 SFE_EEPROM_DELAY(dp); 277 OUTL(dp, EROMAR, EROMAR_EESK); 278 SFE_EEPROM_DELAY(dp); 279 280 /* assert chip select */ 281 offset |= EE_CMD_READ << EE_CMD_SHIFT; 282 283 for (i = 8; i >= 0; i--) { 284 /* make command */ 285 eedi = ((offset >> i) & 1) << EROMAR_EEDI_SHIFT; 286 287 /* send 1 bit */ 288 OUTL(dp, EROMAR, EROMAR_EECS | eedi); 289 SFE_EEPROM_DELAY(dp); 290 OUTL(dp, EROMAR, EROMAR_EECS | eedi | EROMAR_EESK); 291 SFE_EEPROM_DELAY(dp); 292 } 293 294 OUTL(dp, EROMAR, EROMAR_EECS); 295 296 ret = 0; 297 for (i = 0; i < 16; i++) { 298 /* Get 1 bit */ 299 OUTL(dp, EROMAR, EROMAR_EECS); 300 SFE_EEPROM_DELAY(dp); 301 OUTL(dp, EROMAR, EROMAR_EECS | EROMAR_EESK); 302 SFE_EEPROM_DELAY(dp); 303 304 ret = (ret << 1) | ((INL(dp, EROMAR) >> EROMAR_EEDO_SHIFT) & 1); 305 } 306 307 OUTL(dp, EROMAR, 0); 308 SFE_EEPROM_DELAY(dp); 309 310 return (ret); 311 } 312 #undef SFE_EEPROM_DELAY 313 314 static boolean_t 315 sfe_get_mac_addr_dp83815(struct gem_dev *dp) 316 { 317 uint8_t *mac; 318 uint_t val; 319 int i; 320 321 #define BITSET(p, ix, v) (p)[(ix)/8] |= ((v) ? 1 : 0) << ((ix) & 0x7) 322 323 DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__)); 324 325 mac = dp->dev_addr.ether_addr_octet; 326 327 /* first of all, clear MAC address buffer */ 328 bzero(mac, ETHERADDRL); 329 330 /* get bit 0 */ 331 val = sfe_read_eeprom(dp, 0x6); 332 BITSET(mac, 0, val & 1); 333 334 /* get bit 1 - 16 */ 335 val = sfe_read_eeprom(dp, 0x7); 336 for (i = 0; i < 16; i++) { 337 BITSET(mac, 1 + i, val & (1 << (15 - i))); 338 } 339 340 /* get bit 17 - 32 */ 341 val = sfe_read_eeprom(dp, 0x8); 342 for (i = 0; i < 16; i++) { 343 BITSET(mac, 17 + i, val & (1 << (15 - i))); 344 } 345 346 /* get bit 33 - 47 */ 347 val = sfe_read_eeprom(dp, 0x9); 348 for (i = 0; i < 15; i++) { 349 BITSET(mac, 33 + i, val & (1 << (15 - i))); 350 } 351 352 return (B_TRUE); 353 #undef BITSET 354 } 355 356 static boolean_t 357 sfe_get_mac_addr_sis900(struct gem_dev *dp) 358 { 359 uint_t val; 360 int i; 361 uint8_t *mac; 362 363 mac = dp->dev_addr.ether_addr_octet; 364 365 for (i = 0; i < ETHERADDRL/2; i++) { 366 val = sfe_read_eeprom(dp, 0x8 + i); 367 *mac++ = (uint8_t)val; 368 *mac++ = (uint8_t)(val >> 8); 369 } 370 371 return (B_TRUE); 372 } 373 374 static dev_info_t * 375 sfe_search_pci_dev_subr(dev_info_t *cur_node, int vendor_id, int device_id) 376 { 377 dev_info_t *child_id; 378 dev_info_t *ret; 379 int vid, did; 380 381 if (cur_node == NULL) { 382 return (NULL); 383 } 384 385 /* check brothers */ 386 do { 387 vid = ddi_prop_get_int(DDI_DEV_T_ANY, cur_node, 388 DDI_PROP_DONTPASS, "vendor-id", -1); 389 did = ddi_prop_get_int(DDI_DEV_T_ANY, cur_node, 390 DDI_PROP_DONTPASS, "device-id", -1); 391 392 if (vid == vendor_id && did == device_id) { 393 /* found */ 394 return (cur_node); 395 } 396 397 /* check children */ 398 if ((child_id = ddi_get_child(cur_node)) != NULL) { 399 if ((ret = sfe_search_pci_dev_subr(child_id, 400 vendor_id, device_id)) != NULL) { 401 return (ret); 402 } 403 } 404 405 } while ((cur_node = ddi_get_next_sibling(cur_node)) != NULL); 406 407 /* not found */ 408 return (NULL); 409 } 410 411 static dev_info_t * 412 sfe_search_pci_dev(int vendor_id, int device_id) 413 { 414 return (sfe_search_pci_dev_subr(ddi_root_node(), vendor_id, device_id)); 415 } 416 417 /* Avoid undefined symbol for non IA architectures */ 418 #pragma weak inb 419 #pragma weak outb 420 421 static boolean_t 422 sfe_get_mac_addr_sis630e(struct gem_dev *dp) 423 { 424 int i; 425 dev_info_t *isa_bridge; 426 ddi_acc_handle_t isa_handle; 427 int reg; 428 429 if (inb == NULL || outb == NULL) { 430 /* this is not IA architecture */ 431 return (B_FALSE); 432 } 433 434 if ((isa_bridge = sfe_search_pci_dev(0x1039, 0x8)) == NULL) { 435 cmn_err(CE_WARN, "%s: failed to find isa-bridge pci1039,8", 436 dp->name); 437 return (B_FALSE); 438 } 439 440 if (pci_config_setup(isa_bridge, &isa_handle) != DDI_SUCCESS) { 441 cmn_err(CE_WARN, "%s: ddi_regs_map_setup failed", 442 dp->name); 443 return (B_FALSE); 444 } 445 446 /* enable to access CMOS RAM */ 447 reg = pci_config_get8(isa_handle, 0x48); 448 pci_config_put8(isa_handle, 0x48, reg | 0x40); 449 450 for (i = 0; i < ETHERADDRL; i++) { 451 outb(0x70, 0x09 + i); 452 dp->dev_addr.ether_addr_octet[i] = inb(0x71); 453 } 454 455 /* disable to access CMOS RAM */ 456 pci_config_put8(isa_handle, 0x48, reg); 457 pci_config_teardown(&isa_handle); 458 459 return (B_TRUE); 460 } 461 462 static boolean_t 463 sfe_get_mac_addr_sis635(struct gem_dev *dp) 464 { 465 int i; 466 uint32_t rfcr; 467 uint16_t v; 468 struct sfe_dev *lp = dp->private; 469 470 DPRINTF(2, (CE_CONT, CONS "%s: %s: called", dp->name, __func__)); 471 rfcr = INL(dp, RFCR); 472 473 OUTL(dp, CR, lp->cr | CR_RELOAD); 474 OUTL(dp, CR, lp->cr); 475 476 /* disable packet filtering before reading filter */ 477 OUTL(dp, RFCR, rfcr & ~RFCR_RFEN); 478 479 /* load MAC addr from filter data register */ 480 for (i = 0; i < ETHERADDRL; i += 2) { 481 OUTL(dp, RFCR, 482 (RFADDR_MAC_SIS900 + (i/2)) << RFCR_RFADDR_SHIFT_SIS900); 483 v = INL(dp, RFDR); 484 dp->dev_addr.ether_addr_octet[i] = (uint8_t)v; 485 dp->dev_addr.ether_addr_octet[i+1] = (uint8_t)(v >> 8); 486 } 487 488 /* re-enable packet filtering */ 489 OUTL(dp, RFCR, rfcr | RFCR_RFEN); 490 491 return (B_TRUE); 492 } 493 494 static boolean_t 495 sfe_get_mac_addr_sis962(struct gem_dev *dp) 496 { 497 boolean_t ret; 498 int i; 499 500 ret = B_FALSE; 501 502 /* rise request signal to access EEPROM */ 503 OUTL(dp, MEAR, EROMAR_EEREQ); 504 for (i = 0; (INL(dp, MEAR) & EROMAR_EEGNT) == 0; i++) { 505 if (i > 200) { 506 /* failed to acquire eeprom */ 507 cmn_err(CE_NOTE, 508 CONS "%s: failed to access eeprom", dp->name); 509 goto x; 510 } 511 drv_usecwait(10); 512 } 513 ret = sfe_get_mac_addr_sis900(dp); 514 x: 515 /* release EEPROM */ 516 OUTL(dp, MEAR, EROMAR_EEDONE); 517 518 return (ret); 519 } 520 521 static int 522 sfe_reset_chip_sis900(struct gem_dev *dp) 523 { 524 int i; 525 uint32_t done; 526 uint32_t val; 527 struct sfe_dev *lp = dp->private; 528 529 DPRINTF(4, (CE_CONT, CONS "%s: %s called", dp->name, __func__)); 530 531 /* invalidate mac addr cache */ 532 bzero(lp->mac_addr, sizeof (lp->mac_addr)); 533 534 lp->cr = 0; 535 536 /* inhibit interrupt */ 537 OUTL(dp, IMR, 0); 538 lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits; 539 540 OUTL(dp, RFCR, 0); 541 542 OUTL(dp, CR, CR_RST | CR_TXR | CR_RXR); 543 drv_usecwait(10); 544 545 done = 0; 546 for (i = 0; done != (ISR_TXRCMP | ISR_RXRCMP); i++) { 547 if (i > 1000) { 548 cmn_err(CE_WARN, "%s: chip reset timeout", dp->name); 549 return (GEM_FAILURE); 550 } 551 done |= INL(dp, ISR) & (ISR_TXRCMP | ISR_RXRCMP); 552 drv_usecwait(10); 553 } 554 555 if (lp->revid == SIS630ET_900_REV) { 556 lp->cr |= CR_ACCESSMODE; 557 OUTL(dp, CR, lp->cr | INL(dp, CR)); 558 } 559 560 /* Configuration register: enable PCI parity */ 561 DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b", 562 dp->name, INL(dp, CFG), CFG_BITS_SIS900)); 563 val = 0; 564 if (lp->revid >= SIS635A_900_REV || 565 lp->revid == SIS900B_900_REV) { 566 /* what is this ? */ 567 val |= CFG_RND_CNT; 568 } 569 OUTL(dp, CFG, val); 570 DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b", dp->name, 571 INL(dp, CFG), CFG_BITS_SIS900)); 572 573 return (GEM_SUCCESS); 574 } 575 576 static int 577 sfe_reset_chip_dp83815(struct gem_dev *dp) 578 { 579 int i; 580 uint32_t val; 581 struct sfe_dev *lp = dp->private; 582 583 DPRINTF(4, (CE_CONT, CONS "%s: %s called", dp->name, __func__)); 584 585 /* invalidate mac addr cache */ 586 bzero(lp->mac_addr, sizeof (lp->mac_addr)); 587 588 lp->cr = 0; 589 590 /* inhibit interrupts */ 591 OUTL(dp, IMR, 0); 592 lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits; 593 594 OUTL(dp, RFCR, 0); 595 596 OUTL(dp, CR, CR_RST); 597 drv_usecwait(10); 598 599 for (i = 0; INL(dp, CR) & CR_RST; i++) { 600 if (i > 100) { 601 cmn_err(CE_WARN, "!%s: chip reset timeout", dp->name); 602 return (GEM_FAILURE); 603 } 604 drv_usecwait(10); 605 } 606 DPRINTF(0, (CE_CONT, "!%s: chip reset in %duS", dp->name, i*10)); 607 608 OUTL(dp, CCSR, CCSR_PMESTS); 609 OUTL(dp, CCSR, 0); 610 611 /* Configuration register: enable PCI parity */ 612 DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b", 613 dp->name, INL(dp, CFG), CFG_BITS_DP83815)); 614 val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG); 615 OUTL(dp, CFG, val | CFG_PAUSE_ADV); 616 DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b", dp->name, 617 INL(dp, CFG), CFG_BITS_DP83815)); 618 619 return (GEM_SUCCESS); 620 } 621 622 static int 623 sfe_init_chip(struct gem_dev *dp) 624 { 625 /* Configuration register: have been set up in sfe_chip_reset */ 626 627 /* PCI test control register: do nothing */ 628 629 /* Interrupt status register : do nothing */ 630 631 /* Interrupt mask register: clear, but leave lp->our_intr_bits */ 632 OUTL(dp, IMR, 0); 633 634 /* Enhanced PHY Access register (sis900): do nothing */ 635 636 /* Transmit Descriptor Pointer register: base addr of TX ring */ 637 OUTL(dp, TXDP, dp->tx_ring_dma); 638 639 /* Receive descriptor pointer register: base addr of RX ring */ 640 OUTL(dp, RXDP, dp->rx_ring_dma); 641 642 return (GEM_SUCCESS); 643 } 644 645 static uint_t 646 sfe_mcast_hash(struct gem_dev *dp, uint8_t *addr) 647 { 648 return (gem_ether_crc_be(addr, ETHERADDRL)); 649 } 650 651 #ifdef DEBUG_LEVEL 652 static void 653 sfe_rxfilter_dump(struct gem_dev *dp, int start, int end) 654 { 655 int i; 656 int j; 657 uint16_t ram[0x10]; 658 659 cmn_err(CE_CONT, "!%s: rx filter ram dump:", dp->name); 660 #define WORDS_PER_LINE 4 661 for (i = start; i < end; i += WORDS_PER_LINE*2) { 662 for (j = 0; j < WORDS_PER_LINE; j++) { 663 OUTL(dp, RFCR, RFADDR_MAC_DP83815 + i + j*2); 664 ram[j] = INL(dp, RFDR); 665 } 666 667 cmn_err(CE_CONT, "!0x%02x: 0x%04x 0x%04x 0x%04x 0x%04x", 668 i, ram[0], ram[1], ram[2], ram[3]); 669 } 670 671 #undef WORDS_PER_LINE 672 } 673 #endif 674 675 static uint_t sfe_rf_perfect_base_dp83815[] = { 676 RFADDR_PMATCH0_DP83815, 677 RFADDR_PMATCH1_DP83815, 678 RFADDR_PMATCH2_DP83815, 679 RFADDR_PMATCH3_DP83815, 680 }; 681 682 static int 683 sfe_set_rx_filter_dp83815(struct gem_dev *dp) 684 { 685 int i; 686 int j; 687 uint32_t mode; 688 uint8_t *mac = dp->cur_addr.ether_addr_octet; 689 uint16_t hash_tbl[32]; 690 struct sfe_dev *lp = dp->private; 691 692 DPRINTF(1, (CE_CONT, CONS "%s: %s: called, mc_count:%d, mode:0x%b", 693 dp->name, __func__, dp->mc_count, dp->rxmode, RXMODE_BITS)); 694 695 #if DEBUG_LEVEL > 0 696 for (i = 0; i < dp->mc_count; i++) { 697 cmn_err(CE_CONT, 698 "!%s: adding mcast(%d) %02x:%02x:%02x:%02x:%02x:%02x", 699 dp->name, i, 700 dp->mc_list[i].addr.ether_addr_octet[0], 701 dp->mc_list[i].addr.ether_addr_octet[1], 702 dp->mc_list[i].addr.ether_addr_octet[2], 703 dp->mc_list[i].addr.ether_addr_octet[3], 704 dp->mc_list[i].addr.ether_addr_octet[4], 705 dp->mc_list[i].addr.ether_addr_octet[5]); 706 } 707 #endif 708 if ((dp->rxmode & RXMODE_ENABLE) == 0) { 709 /* disable rx filter */ 710 OUTL(dp, RFCR, 0); 711 return (GEM_SUCCESS); 712 } 713 714 /* 715 * Set Receive filter control register 716 */ 717 if (dp->rxmode & RXMODE_PROMISC) { 718 /* all broadcast, all multicast, all physical */ 719 mode = RFCR_AAB | RFCR_AAM | RFCR_AAP; 720 } else if ((dp->rxmode & RXMODE_ALLMULTI) || dp->mc_count > 16*32/2) { 721 /* all broadcast, all multicast, physical for the chip */ 722 mode = RFCR_AAB | RFCR_AAM | RFCR_APM_DP83815; 723 } else if (dp->mc_count > 4) { 724 /* 725 * Use multicast hash table, 726 * accept all broadcast and physical for the chip. 727 */ 728 mode = RFCR_AAB | RFCR_MHEN_DP83815 | RFCR_APM_DP83815; 729 730 bzero(hash_tbl, sizeof (hash_tbl)); 731 for (i = 0; i < dp->mc_count; i++) { 732 j = dp->mc_list[i].hash >> (32 - 9); 733 hash_tbl[j / 16] |= 1 << (j % 16); 734 } 735 } else { 736 /* 737 * Use pattern mach filter for multicast address, 738 * accept all broadcast and physical for the chip 739 */ 740 /* need to enable corresponding pattern registers */ 741 mode = RFCR_AAB | RFCR_APM_DP83815 | 742 (((1 << dp->mc_count) - 1) << RFCR_APAT_SHIFT); 743 } 744 745 #if DEBUG_LEVEL > 1 746 cmn_err(CE_CONT, 747 "!%s: mac %02x:%02x:%02x:%02x:%02x:%02x" 748 " cache %02x:%02x:%02x:%02x:%02x:%02x", 749 dp->name, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], 750 lp->mac_addr[0], lp->mac_addr[1], 751 lp->mac_addr[2], lp->mac_addr[3], 752 lp->mac_addr[4], lp->mac_addr[5]); 753 #endif 754 if (bcmp(mac, lp->mac_addr, ETHERADDRL) != 0) { 755 /* 756 * XXX - need to *disable* rx filter to load mac address for 757 * the chip. otherwise, we cannot setup rxfilter correctly. 758 */ 759 /* setup perfect match register for my station address */ 760 for (i = 0; i < ETHERADDRL; i += 2) { 761 OUTL(dp, RFCR, RFADDR_MAC_DP83815 + i); 762 OUTL(dp, RFDR, (mac[i+1] << 8) | mac[i]); 763 } 764 765 bcopy(mac, lp->mac_addr, ETHERADDRL); 766 } 767 768 #if DEBUG_LEVEL > 3 769 /* clear pattern ram */ 770 for (j = 0x200; j < 0x380; j += 2) { 771 OUTL(dp, RFCR, j); 772 OUTL(dp, RFDR, 0); 773 } 774 #endif 775 if (mode & RFCR_APAT_DP83815) { 776 /* setup multicast address into pattern match registers */ 777 for (j = 0; j < dp->mc_count; j++) { 778 mac = &dp->mc_list[j].addr.ether_addr_octet[0]; 779 for (i = 0; i < ETHERADDRL; i += 2) { 780 OUTL(dp, RFCR, 781 sfe_rf_perfect_base_dp83815[j] + i*2); 782 OUTL(dp, RFDR, (mac[i+1] << 8) | mac[i]); 783 } 784 } 785 786 /* setup pattern count registers */ 787 OUTL(dp, RFCR, RFADDR_PCOUNT01_DP83815); 788 OUTL(dp, RFDR, (ETHERADDRL << 8) | ETHERADDRL); 789 OUTL(dp, RFCR, RFADDR_PCOUNT23_DP83815); 790 OUTL(dp, RFDR, (ETHERADDRL << 8) | ETHERADDRL); 791 } 792 793 if (mode & RFCR_MHEN_DP83815) { 794 /* Load Multicast hash table */ 795 for (i = 0; i < 32; i++) { 796 /* for DP83815, index is in byte */ 797 OUTL(dp, RFCR, RFADDR_MULTICAST_DP83815 + i*2); 798 OUTL(dp, RFDR, hash_tbl[i]); 799 } 800 } 801 #if DEBUG_LEVEL > 2 802 sfe_rxfilter_dump(dp, 0, 0x10); 803 sfe_rxfilter_dump(dp, 0x200, 0x380); 804 #endif 805 /* Set rx filter mode and enable rx filter */ 806 OUTL(dp, RFCR, RFCR_RFEN | mode); 807 808 return (GEM_SUCCESS); 809 } 810 811 static int 812 sfe_set_rx_filter_sis900(struct gem_dev *dp) 813 { 814 int i; 815 uint32_t mode; 816 uint16_t hash_tbl[16]; 817 uint8_t *mac = dp->cur_addr.ether_addr_octet; 818 int hash_size; 819 int hash_shift; 820 struct sfe_dev *lp = dp->private; 821 822 DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__)); 823 824 if ((dp->rxmode & RXMODE_ENABLE) == 0) { 825 /* disalbe rx filter */ 826 OUTL(dp, RFCR, 0); 827 return (GEM_SUCCESS); 828 } 829 830 /* 831 * determine hardware hash table size in word. 832 */ 833 hash_shift = 25; 834 if (lp->revid >= SIS635A_900_REV || lp->revid == SIS900B_900_REV) { 835 hash_shift = 24; 836 } 837 hash_size = (1 << (32 - hash_shift)) / 16; 838 bzero(hash_tbl, sizeof (hash_tbl)); 839 840 /* Set Receive filter control register */ 841 842 if (dp->rxmode & RXMODE_PROMISC) { 843 /* all broadcast, all multicast, all physical */ 844 mode = RFCR_AAB | RFCR_AAM | RFCR_AAP; 845 } else if ((dp->rxmode & RXMODE_ALLMULTI) || 846 dp->mc_count > hash_size*16/2) { 847 /* all broadcast, all multicast, physical for the chip */ 848 mode = RFCR_AAB | RFCR_AAM; 849 } else { 850 /* all broadcast, physical for the chip */ 851 mode = RFCR_AAB; 852 } 853 854 /* make hash table */ 855 for (i = 0; i < dp->mc_count; i++) { 856 uint_t h; 857 h = dp->mc_list[i].hash >> hash_shift; 858 hash_tbl[h / 16] |= 1 << (h % 16); 859 } 860 861 if (bcmp(mac, lp->mac_addr, ETHERADDRL) != 0) { 862 /* Disable Rx filter and load mac address */ 863 for (i = 0; i < ETHERADDRL/2; i++) { 864 /* For sis900, index is in word */ 865 OUTL(dp, RFCR, 866 (RFADDR_MAC_SIS900+i) << RFCR_RFADDR_SHIFT_SIS900); 867 OUTL(dp, RFDR, (mac[i*2+1] << 8) | mac[i*2]); 868 } 869 870 bcopy(mac, lp->mac_addr, ETHERADDRL); 871 } 872 873 /* Load Multicast hash table */ 874 for (i = 0; i < hash_size; i++) { 875 /* For sis900, index is in word */ 876 OUTL(dp, RFCR, 877 (RFADDR_MULTICAST_SIS900 + i) << RFCR_RFADDR_SHIFT_SIS900); 878 OUTL(dp, RFDR, hash_tbl[i]); 879 } 880 881 /* Load rx filter mode and enable rx filter */ 882 OUTL(dp, RFCR, RFCR_RFEN | mode); 883 884 return (GEM_SUCCESS); 885 } 886 887 static int 888 sfe_start_chip(struct gem_dev *dp) 889 { 890 struct sfe_dev *lp = dp->private; 891 892 DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__)); 893 894 /* 895 * setup interrupt mask, which shouldn't include ISR_TOK 896 * to improve performance. 897 */ 898 lp->our_intr_bits = OUR_INTR_BITS; 899 900 /* enable interrupt */ 901 if ((dp->misc_flag & GEM_NOINTR) == 0) { 902 OUTL(dp, IER, 1); 903 OUTL(dp, IMR, lp->our_intr_bits); 904 } 905 906 /* Kick RX */ 907 OUTL(dp, CR, lp->cr | CR_RXE); 908 909 return (GEM_SUCCESS); 910 } 911 912 /* 913 * Stop nic core gracefully. 914 */ 915 static int 916 sfe_stop_chip(struct gem_dev *dp) 917 { 918 struct sfe_dev *lp = dp->private; 919 uint32_t done; 920 int i; 921 uint32_t val; 922 923 DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__)); 924 925 /* 926 * Although we inhibit interrupt here, we don't clear soft copy of 927 * interrupt mask to avoid bogus interrupts. 928 */ 929 OUTL(dp, IMR, 0); 930 931 /* stop TX and RX immediately */ 932 OUTL(dp, CR, lp->cr | CR_TXR | CR_RXR); 933 934 done = 0; 935 for (i = 0; done != (ISR_RXRCMP | ISR_TXRCMP); i++) { 936 if (i > 1000) { 937 /* 938 * As gem layer will call sfe_reset_chip(), 939 * we don't neet to reset futher 940 */ 941 cmn_err(CE_NOTE, "!%s: %s: Tx/Rx reset timeout", 942 dp->name, __func__); 943 944 return (GEM_FAILURE); 945 } 946 val = INL(dp, ISR); 947 done |= val & (ISR_RXRCMP | ISR_TXRCMP); 948 lp->isr_pended |= val & lp->our_intr_bits; 949 drv_usecwait(10); 950 } 951 952 return (GEM_SUCCESS); 953 } 954 955 /* 956 * Setup media mode 957 */ 958 static uint_t 959 sfe_mxdma_value[] = { 512, 4, 8, 16, 32, 64, 128, 256, }; 960 961 static uint_t 962 sfe_encode_mxdma(uint_t burstsize) 963 { 964 int i; 965 966 if (burstsize > 256) { 967 /* choose 512 */ 968 return (0); 969 } 970 971 for (i = 1; i < 8; i++) { 972 if (burstsize <= sfe_mxdma_value[i]) { 973 break; 974 } 975 } 976 return (i); 977 } 978 979 static int 980 sfe_set_media(struct gem_dev *dp) 981 { 982 uint32_t txcfg; 983 uint32_t rxcfg; 984 uint32_t pcr; 985 uint32_t val; 986 uint32_t txmxdma; 987 uint32_t rxmxdma; 988 struct sfe_dev *lp = dp->private; 989 #ifdef DEBUG_LEVEL 990 extern int gem_speed_value[]; 991 #endif 992 DPRINTF(2, (CE_CONT, CONS "%s: %s: %s duplex, %d Mbps", 993 dp->name, __func__, 994 dp->full_duplex ? "full" : "half", gem_speed_value[dp->speed])); 995 996 /* initialize txcfg and rxcfg */ 997 txcfg = TXCFG_ATP; 998 if (dp->full_duplex) { 999 txcfg |= (TXCFG_CSI | TXCFG_HBI); 1000 } 1001 rxcfg = RXCFG_AEP | RXCFG_ARP; 1002 if (dp->full_duplex) { 1003 rxcfg |= RXCFG_ATX; 1004 } 1005 1006 /* select txmxdma and rxmxdma, maxmum burst length */ 1007 if (lp->chip->chip_type == CHIPTYPE_SIS900) { 1008 #ifdef DEBUG_SIS900_EDB 1009 val = CFG_EDB_MASTER; 1010 #else 1011 val = INL(dp, CFG) & CFG_EDB_MASTER; 1012 #endif 1013 if (val) { 1014 /* 1015 * sis900 built-in cores: 1016 * max burst length must be fixed to 64 1017 */ 1018 txmxdma = 64; 1019 rxmxdma = 64; 1020 } else { 1021 /* 1022 * sis900 pci chipset: 1023 * the vendor recommended to fix max burst length 1024 * to 512 1025 */ 1026 txmxdma = 512; 1027 rxmxdma = 512; 1028 } 1029 } else { 1030 /* 1031 * NS dp83815/816: 1032 * use user defined or default for tx/rx max burst length 1033 */ 1034 txmxdma = max(dp->txmaxdma, 256); 1035 rxmxdma = max(dp->rxmaxdma, 256); 1036 } 1037 1038 1039 /* tx high water mark */ 1040 lp->tx_drain_threshold = ROUNDUP2(dp->txthr, TXCFG_FIFO_UNIT); 1041 1042 /* determine tx_fill_threshold accroding drain threshold */ 1043 lp->tx_fill_threshold = 1044 TXFIFOSIZE - lp->tx_drain_threshold - TXCFG_FIFO_UNIT; 1045 1046 /* tune txmxdma not to exceed tx_fill_threshold */ 1047 for (; ; ) { 1048 /* normalize txmxdma requested */ 1049 val = sfe_encode_mxdma(txmxdma); 1050 txmxdma = sfe_mxdma_value[val]; 1051 1052 if (txmxdma <= lp->tx_fill_threshold) { 1053 break; 1054 } 1055 /* select new txmxdma */ 1056 txmxdma = txmxdma / 2; 1057 } 1058 txcfg |= val << TXCFG_MXDMA_SHIFT; 1059 1060 /* encode rxmxdma, maxmum burst length for rx */ 1061 val = sfe_encode_mxdma(rxmxdma); 1062 rxcfg |= val << RXCFG_MXDMA_SHIFT; 1063 rxmxdma = sfe_mxdma_value[val]; 1064 1065 /* receive starting threshold - it have only 5bit-wide field */ 1066 val = ROUNDUP2(max(dp->rxthr, ETHERMIN), RXCFG_FIFO_UNIT); 1067 lp->rx_drain_threshold = 1068 min(val, (RXCFG_DRTH >> RXCFG_DRTH_SHIFT) * RXCFG_FIFO_UNIT); 1069 1070 DPRINTF(0, (CE_CONT, 1071 "%s: %s: tx: drain:%d(rest %d) fill:%d mxdma:%d," 1072 " rx: drain:%d mxdma:%d", 1073 dp->name, __func__, 1074 lp->tx_drain_threshold, TXFIFOSIZE - lp->tx_drain_threshold, 1075 lp->tx_fill_threshold, txmxdma, 1076 lp->rx_drain_threshold, rxmxdma)); 1077 1078 ASSERT(lp->tx_drain_threshold < 64*TXCFG_FIFO_UNIT); 1079 ASSERT(lp->tx_fill_threshold < 64*TXCFG_FIFO_UNIT); 1080 ASSERT(lp->rx_drain_threshold < 32*RXCFG_FIFO_UNIT); 1081 1082 txcfg |= ((lp->tx_fill_threshold/TXCFG_FIFO_UNIT) << TXCFG_FLTH_SHIFT) 1083 | (lp->tx_drain_threshold/TXCFG_FIFO_UNIT); 1084 OUTL(dp, TXCFG, txcfg); 1085 1086 rxcfg |= ((lp->rx_drain_threshold/RXCFG_FIFO_UNIT) << RXCFG_DRTH_SHIFT); 1087 if (lp->chip->chip_type == CHIPTYPE_DP83815) { 1088 rxcfg |= RXCFG_ALP_DP83815; 1089 } 1090 OUTL(dp, RXCFG, rxcfg); 1091 1092 DPRINTF(0, (CE_CONT, CONS "%s: %s: txcfg:%b rxcfg:%b", 1093 dp->name, __func__, 1094 txcfg, TXCFG_BITS, rxcfg, RXCFG_BITS)); 1095 1096 /* Flow control */ 1097 if (lp->chip->chip_type == CHIPTYPE_DP83815) { 1098 pcr = INL(dp, PCR); 1099 switch (dp->flow_control) { 1100 case FLOW_CONTROL_SYMMETRIC: 1101 case FLOW_CONTROL_RX_PAUSE: 1102 OUTL(dp, PCR, pcr | PCR_PSEN | PCR_PS_MCAST); 1103 break; 1104 1105 default: 1106 OUTL(dp, PCR, 1107 pcr & ~(PCR_PSEN | PCR_PS_MCAST | PCR_PS_DA)); 1108 break; 1109 } 1110 DPRINTF(2, (CE_CONT, CONS "%s: PCR: %b", dp->name, 1111 INL(dp, PCR), PCR_BITS)); 1112 1113 } else if (lp->chip->chip_type == CHIPTYPE_SIS900) { 1114 switch (dp->flow_control) { 1115 case FLOW_CONTROL_SYMMETRIC: 1116 case FLOW_CONTROL_RX_PAUSE: 1117 OUTL(dp, FLOWCTL, FLOWCTL_FLOWEN); 1118 break; 1119 default: 1120 OUTL(dp, FLOWCTL, 0); 1121 break; 1122 } 1123 DPRINTF(2, (CE_CONT, CONS "%s: FLOWCTL: %b", 1124 dp->name, INL(dp, FLOWCTL), FLOWCTL_BITS)); 1125 } 1126 return (GEM_SUCCESS); 1127 } 1128 1129 static int 1130 sfe_get_stats(struct gem_dev *dp) 1131 { 1132 /* do nothing */ 1133 return (GEM_SUCCESS); 1134 } 1135 1136 /* 1137 * descriptor manipulations 1138 */ 1139 static int 1140 sfe_tx_desc_write(struct gem_dev *dp, int slot, 1141 ddi_dma_cookie_t *dmacookie, int frags, uint64_t flags) 1142 { 1143 uint32_t mark; 1144 struct sfe_desc *tdp; 1145 ddi_dma_cookie_t *dcp; 1146 uint32_t tmp0; 1147 #if DEBUG_LEVEL > 2 1148 int i; 1149 1150 cmn_err(CE_CONT, 1151 CONS "%s: time:%d %s seqnum: %d, slot %d, frags: %d flags: %llx", 1152 dp->name, ddi_get_lbolt(), __func__, 1153 dp->tx_desc_tail, slot, frags, flags); 1154 1155 for (i = 0; i < frags; i++) { 1156 cmn_err(CE_CONT, CONS "%d: addr: 0x%x, len: 0x%x", 1157 i, dmacookie[i].dmac_address, dmacookie[i].dmac_size); 1158 } 1159 #endif 1160 /* 1161 * write tx descriptor in reversed order. 1162 */ 1163 #if DEBUG_LEVEL > 3 1164 flags |= GEM_TXFLAG_INTR; 1165 #endif 1166 mark = (flags & GEM_TXFLAG_INTR) 1167 ? (CMDSTS_OWN | CMDSTS_INTR) : CMDSTS_OWN; 1168 1169 ASSERT(frags == 1); 1170 dcp = &dmacookie[0]; 1171 if (flags & GEM_TXFLAG_HEAD) { 1172 mark &= ~CMDSTS_OWN; 1173 } 1174 1175 tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot]; 1176 tmp0 = (uint32_t)dcp->dmac_address; 1177 mark |= (uint32_t)dcp->dmac_size; 1178 tdp->d_bufptr = LE_32(tmp0); 1179 tdp->d_cmdsts = LE_32(mark); 1180 1181 return (frags); 1182 } 1183 1184 static void 1185 sfe_tx_start(struct gem_dev *dp, int start_slot, int nslot) 1186 { 1187 uint_t tx_ring_size = dp->gc.gc_tx_ring_size; 1188 struct sfe_desc *tdp; 1189 struct sfe_dev *lp = dp->private; 1190 1191 if (nslot > 1) { 1192 gem_tx_desc_dma_sync(dp, 1193 SLOT(start_slot + 1, tx_ring_size), 1194 nslot - 1, DDI_DMA_SYNC_FORDEV); 1195 } 1196 1197 tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * start_slot]; 1198 tdp->d_cmdsts |= LE_32(CMDSTS_OWN); 1199 1200 gem_tx_desc_dma_sync(dp, start_slot, 1, DDI_DMA_SYNC_FORDEV); 1201 1202 /* 1203 * Let the Transmit Buffer Manager Fill state machine active. 1204 */ 1205 if (dp->mac_active) { 1206 OUTL(dp, CR, lp->cr | CR_TXE); 1207 } 1208 } 1209 1210 static void 1211 sfe_rx_desc_write(struct gem_dev *dp, int slot, 1212 ddi_dma_cookie_t *dmacookie, int frags) 1213 { 1214 struct sfe_desc *rdp; 1215 uint32_t tmp0; 1216 uint32_t tmp1; 1217 #if DEBUG_LEVEL > 2 1218 int i; 1219 1220 ASSERT(frags == 1); 1221 1222 cmn_err(CE_CONT, CONS 1223 "%s: %s seqnum: %d, slot %d, frags: %d", 1224 dp->name, __func__, dp->rx_active_tail, slot, frags); 1225 for (i = 0; i < frags; i++) { 1226 cmn_err(CE_CONT, CONS " frag: %d addr: 0x%llx, len: 0x%lx", 1227 i, dmacookie[i].dmac_address, dmacookie[i].dmac_size); 1228 } 1229 #endif 1230 /* for the last slot of the packet */ 1231 rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot]; 1232 1233 tmp0 = (uint32_t)dmacookie->dmac_address; 1234 tmp1 = CMDSTS_INTR | (uint32_t)dmacookie->dmac_size; 1235 rdp->d_bufptr = LE_32(tmp0); 1236 rdp->d_cmdsts = LE_32(tmp1); 1237 } 1238 1239 static uint_t 1240 sfe_tx_desc_stat(struct gem_dev *dp, int slot, int ndesc) 1241 { 1242 uint_t tx_ring_size = dp->gc.gc_tx_ring_size; 1243 struct sfe_desc *tdp; 1244 uint32_t status; 1245 int cols; 1246 struct sfe_dev *lp = dp->private; 1247 #ifdef DEBUG_LEVEL 1248 int i; 1249 clock_t delay; 1250 #endif 1251 /* check status of the last descriptor */ 1252 tdp = (void *) 1253 &dp->tx_ring[SFE_DESC_SIZE * SLOT(slot + ndesc - 1, tx_ring_size)]; 1254 1255 /* 1256 * Don't use LE_32() directly to refer tdp->d_cmdsts. 1257 * It is not atomic for big endian cpus. 1258 */ 1259 status = tdp->d_cmdsts; 1260 status = LE_32(status); 1261 1262 DPRINTF(2, (CE_CONT, CONS "%s: time:%ld %s: slot:%d, status:0x%b", 1263 dp->name, ddi_get_lbolt(), __func__, 1264 slot, status, TXSTAT_BITS)); 1265 1266 if (status & CMDSTS_OWN) { 1267 /* 1268 * not yet transmitted 1269 */ 1270 /* workaround for tx hang */ 1271 if (lp->chip->chip_type == CHIPTYPE_DP83815 && 1272 dp->mac_active) { 1273 OUTL(dp, CR, lp->cr | CR_TXE); 1274 } 1275 return (0); 1276 } 1277 1278 if (status & CMDSTS_MORE) { 1279 /* XXX - the hardware problem but don't panic the system */ 1280 /* avoid lint bug for %b format string including 32nd bit */ 1281 cmn_err(CE_NOTE, CONS 1282 "%s: tx status bits incorrect: slot:%d, status:0x%x", 1283 dp->name, slot, status); 1284 } 1285 1286 #if DEBUG_LEVEL > 3 1287 delay = (ddi_get_lbolt() - dp->tx_buf_head->txb_stime) * 10; 1288 if (delay >= 50) { 1289 DPRINTF(0, (CE_NOTE, "%s: tx deferred %d mS: slot %d", 1290 dp->name, delay, slot)); 1291 } 1292 #endif 1293 1294 #if DEBUG_LEVEL > 3 1295 for (i = 0; i < nfrag-1; i++) { 1296 uint32_t s; 1297 int n; 1298 1299 n = SLOT(slot + i, tx_ring_size); 1300 s = LE_32( 1301 ((struct sfe_desc *)((void *) 1302 &dp->tx_ring[SFE_DESC_SIZE * n]))->d_cmdsts); 1303 1304 ASSERT(s & CMDSTS_MORE); 1305 ASSERT((s & CMDSTS_OWN) == 0); 1306 } 1307 #endif 1308 1309 /* 1310 * collect statistics 1311 */ 1312 if ((status & CMDSTS_OK) == 0) { 1313 1314 /* failed to transmit the packet */ 1315 1316 DPRINTF(0, (CE_CONT, CONS "%s: Transmit error, Tx status %b", 1317 dp->name, status, TXSTAT_BITS)); 1318 1319 dp->stats.errxmt++; 1320 1321 if (status & CMDSTS_TFU) { 1322 dp->stats.underflow++; 1323 } else if (status & CMDSTS_CRS) { 1324 dp->stats.nocarrier++; 1325 } else if (status & CMDSTS_OWC) { 1326 dp->stats.xmtlatecoll++; 1327 } else if ((!dp->full_duplex) && (status & CMDSTS_EC)) { 1328 dp->stats.excoll++; 1329 dp->stats.collisions += 16; 1330 } else { 1331 dp->stats.xmit_internal_err++; 1332 } 1333 } else if (!dp->full_duplex) { 1334 cols = (status >> CMDSTS_CCNT_SHIFT) & CCNT_MASK; 1335 1336 if (cols > 0) { 1337 if (cols == 1) { 1338 dp->stats.first_coll++; 1339 } else /* (cols > 1) */ { 1340 dp->stats.multi_coll++; 1341 } 1342 dp->stats.collisions += cols; 1343 } else if (status & CMDSTS_TD) { 1344 dp->stats.defer++; 1345 } 1346 } 1347 return (GEM_TX_DONE); 1348 } 1349 1350 static uint64_t 1351 sfe_rx_desc_stat(struct gem_dev *dp, int slot, int ndesc) 1352 { 1353 struct sfe_desc *rdp; 1354 uint_t len; 1355 uint_t flag; 1356 uint32_t status; 1357 1358 flag = GEM_RX_DONE; 1359 1360 /* Dont read ISR because we cannot ack only to rx interrupt. */ 1361 1362 rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot]; 1363 1364 /* 1365 * Don't use LE_32() directly to refer rdp->d_cmdsts. 1366 * It is not atomic for big endian cpus. 1367 */ 1368 status = rdp->d_cmdsts; 1369 status = LE_32(status); 1370 1371 DPRINTF(2, (CE_CONT, CONS "%s: time:%ld %s: slot:%d, status:0x%b", 1372 dp->name, ddi_get_lbolt(), __func__, 1373 slot, status, RXSTAT_BITS)); 1374 1375 if ((status & CMDSTS_OWN) == 0) { 1376 /* 1377 * No more received packets because 1378 * this buffer is owned by NIC. 1379 */ 1380 return (0); 1381 } 1382 1383 #define RX_ERR_BITS \ 1384 (CMDSTS_RXA | CMDSTS_RXO | CMDSTS_LONG | CMDSTS_RUNT | \ 1385 CMDSTS_ISE | CMDSTS_CRCE | CMDSTS_FAE | CMDSTS_MORE) 1386 1387 if (status & RX_ERR_BITS) { 1388 /* 1389 * Packet with error received 1390 */ 1391 DPRINTF(0, (CE_CONT, CONS "%s: Corrupted packet " 1392 "received, buffer status: %b", 1393 dp->name, status, RXSTAT_BITS)); 1394 1395 /* collect statistics information */ 1396 dp->stats.errrcv++; 1397 1398 if (status & CMDSTS_RXO) { 1399 dp->stats.overflow++; 1400 } else if (status & (CMDSTS_LONG | CMDSTS_MORE)) { 1401 dp->stats.frame_too_long++; 1402 } else if (status & CMDSTS_RUNT) { 1403 dp->stats.runt++; 1404 } else if (status & (CMDSTS_ISE | CMDSTS_FAE)) { 1405 dp->stats.frame++; 1406 } else if (status & CMDSTS_CRCE) { 1407 dp->stats.crc++; 1408 } else { 1409 dp->stats.rcv_internal_err++; 1410 } 1411 1412 return (flag | GEM_RX_ERR); 1413 } 1414 1415 /* 1416 * this packet was received without errors 1417 */ 1418 if ((len = (status & CMDSTS_SIZE)) >= ETHERFCSL) { 1419 len -= ETHERFCSL; 1420 } 1421 1422 #if DEBUG_LEVEL > 10 1423 { 1424 int i; 1425 uint8_t *bp = dp->rx_buf_head->rxb_buf; 1426 1427 cmn_err(CE_CONT, CONS "%s: len:%d", dp->name, len); 1428 1429 for (i = 0; i < 60; i += 10) { 1430 cmn_err(CE_CONT, CONS 1431 "%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", 1432 bp[0], bp[1], bp[2], bp[3], bp[4], 1433 bp[5], bp[6], bp[7], bp[8], bp[9]); 1434 } 1435 bp += 10; 1436 } 1437 #endif 1438 return (flag | (len & GEM_RX_LEN)); 1439 } 1440 1441 static void 1442 sfe_tx_desc_init(struct gem_dev *dp, int slot) 1443 { 1444 uint_t tx_ring_size = dp->gc.gc_tx_ring_size; 1445 struct sfe_desc *tdp; 1446 uint32_t here; 1447 1448 tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot]; 1449 1450 /* don't clear d_link field, which have a valid pointer */ 1451 tdp->d_cmdsts = 0; 1452 1453 /* make a link to this from the previous descriptor */ 1454 here = ((uint32_t)dp->tx_ring_dma) + SFE_DESC_SIZE*slot; 1455 1456 tdp = (void *) 1457 &dp->tx_ring[SFE_DESC_SIZE * SLOT(slot - 1, tx_ring_size)]; 1458 tdp->d_link = LE_32(here); 1459 } 1460 1461 static void 1462 sfe_rx_desc_init(struct gem_dev *dp, int slot) 1463 { 1464 uint_t rx_ring_size = dp->gc.gc_rx_ring_size; 1465 struct sfe_desc *rdp; 1466 uint32_t here; 1467 1468 rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot]; 1469 1470 /* don't clear d_link field, which have a valid pointer */ 1471 rdp->d_cmdsts = LE_32(CMDSTS_OWN); 1472 1473 /* make a link to this from the previous descriptor */ 1474 here = ((uint32_t)dp->rx_ring_dma) + SFE_DESC_SIZE*slot; 1475 1476 rdp = (void *) 1477 &dp->rx_ring[SFE_DESC_SIZE * SLOT(slot - 1, rx_ring_size)]; 1478 rdp->d_link = LE_32(here); 1479 } 1480 1481 static void 1482 sfe_tx_desc_clean(struct gem_dev *dp, int slot) 1483 { 1484 struct sfe_desc *tdp; 1485 1486 tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot]; 1487 tdp->d_cmdsts = 0; 1488 } 1489 1490 static void 1491 sfe_rx_desc_clean(struct gem_dev *dp, int slot) 1492 { 1493 struct sfe_desc *rdp; 1494 1495 rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot]; 1496 rdp->d_cmdsts = LE_32(CMDSTS_OWN); 1497 } 1498 1499 /* 1500 * Device depend interrupt handler 1501 */ 1502 static uint_t 1503 sfe_interrupt(struct gem_dev *dp) 1504 { 1505 uint_t rx_ring_size = dp->gc.gc_rx_ring_size; 1506 uint32_t isr; 1507 uint32_t isr_bogus; 1508 uint_t flags = 0; 1509 boolean_t need_to_reset = B_FALSE; 1510 struct sfe_dev *lp = dp->private; 1511 1512 /* read reason and clear interrupt */ 1513 isr = INL(dp, ISR); 1514 1515 isr_bogus = lp->isr_pended; 1516 lp->isr_pended = 0; 1517 1518 if (((isr | isr_bogus) & lp->our_intr_bits) == 0) { 1519 /* we are not the interrupt source */ 1520 return (DDI_INTR_UNCLAIMED); 1521 } 1522 1523 DPRINTF(3, (CE_CONT, 1524 CONS "%s: time:%ld %s:called: isr:0x%b rx_active_head: %d", 1525 dp->name, ddi_get_lbolt(), __func__, 1526 isr, INTR_BITS, dp->rx_active_head)); 1527 1528 if (!dp->mac_active) { 1529 /* the device is going to stop */ 1530 lp->our_intr_bits = 0; 1531 return (DDI_INTR_CLAIMED); 1532 } 1533 1534 isr &= lp->our_intr_bits; 1535 1536 if (isr & (ISR_RXSOVR | ISR_RXORN | ISR_RXIDLE | ISR_RXERR | 1537 ISR_RXDESC | ISR_RXOK)) { 1538 (void) gem_receive(dp); 1539 1540 if (isr & (ISR_RXSOVR | ISR_RXORN)) { 1541 DPRINTF(0, (CE_CONT, 1542 CONS "%s: rx fifo overrun: isr %b", 1543 dp->name, isr, INTR_BITS)); 1544 /* no need restart rx */ 1545 dp->stats.overflow++; 1546 } 1547 1548 if (isr & ISR_RXIDLE) { 1549 DPRINTF(0, (CE_CONT, 1550 CONS "%s: rx buffer ran out: isr %b", 1551 dp->name, isr, INTR_BITS)); 1552 1553 dp->stats.norcvbuf++; 1554 1555 /* 1556 * Make RXDP points the head of receive 1557 * buffer list. 1558 */ 1559 OUTL(dp, RXDP, dp->rx_ring_dma + 1560 SFE_DESC_SIZE * 1561 SLOT(dp->rx_active_head, rx_ring_size)); 1562 1563 /* Restart the receive engine */ 1564 OUTL(dp, CR, lp->cr | CR_RXE); 1565 } 1566 } 1567 1568 if (isr & (ISR_TXURN | ISR_TXERR | ISR_TXDESC | 1569 ISR_TXIDLE | ISR_TXOK)) { 1570 /* need to reclaim tx buffers */ 1571 if (gem_tx_done(dp)) { 1572 flags |= INTR_RESTART_TX; 1573 } 1574 /* 1575 * XXX - tx error statistics will be counted in 1576 * sfe_tx_desc_stat() and no need to restart tx on errors. 1577 */ 1578 } 1579 1580 if (isr & (ISR_DPERR | ISR_SSERR | ISR_RMABT | ISR_RTABT)) { 1581 cmn_err(CE_WARN, "%s: ERROR interrupt: isr %b.", 1582 dp->name, isr, INTR_BITS); 1583 need_to_reset = B_TRUE; 1584 } 1585 reset: 1586 if (need_to_reset) { 1587 (void) gem_restart_nic(dp, GEM_RESTART_KEEP_BUF); 1588 flags |= INTR_RESTART_TX; 1589 } 1590 1591 DPRINTF(5, (CE_CONT, CONS "%s: %s: return: isr: %b", 1592 dp->name, __func__, isr, INTR_BITS)); 1593 1594 return (DDI_INTR_CLAIMED | flags); 1595 } 1596 1597 /* ======================================================== */ 1598 /* 1599 * HW depend MII routine 1600 */ 1601 /* ======================================================== */ 1602 1603 /* 1604 * MII routines for NS DP83815 1605 */ 1606 static void 1607 sfe_mii_sync_dp83815(struct gem_dev *dp) 1608 { 1609 /* do nothing */ 1610 } 1611 1612 static uint16_t 1613 sfe_mii_read_dp83815(struct gem_dev *dp, uint_t offset) 1614 { 1615 DPRINTF(4, (CE_CONT, CONS"%s: %s: offset 0x%x", 1616 dp->name, __func__, offset)); 1617 return ((uint16_t)INL(dp, MII_REGS_BASE + offset*4)); 1618 } 1619 1620 static void 1621 sfe_mii_write_dp83815(struct gem_dev *dp, uint_t offset, uint16_t val) 1622 { 1623 DPRINTF(4, (CE_CONT, CONS"%s: %s: offset 0x%x 0x%x", 1624 dp->name, __func__, offset, val)); 1625 OUTL(dp, MII_REGS_BASE + offset*4, val); 1626 } 1627 1628 static int 1629 sfe_mii_config_dp83815(struct gem_dev *dp) 1630 { 1631 uint32_t srr; 1632 1633 srr = INL(dp, SRR) & SRR_REV; 1634 1635 DPRINTF(0, (CE_CONT, CONS "%s: srr:0x%04x %04x %04x %04x %04x %04x", 1636 dp->name, srr, 1637 INW(dp, 0x00cc), /* PGSEL */ 1638 INW(dp, 0x00e4), /* PMDCSR */ 1639 INW(dp, 0x00fc), /* TSTDAT */ 1640 INW(dp, 0x00f4), /* DSPCFG */ 1641 INW(dp, 0x00f8))); /* SDCFG */ 1642 1643 if (srr == SRR_REV_DP83815CVNG) { 1644 /* 1645 * NS datasheet says that DP83815CVNG needs following 1646 * registers to be patched for optimizing its performance. 1647 * A report said that CRC errors on RX disappeared 1648 * with the patch. 1649 */ 1650 OUTW(dp, 0x00cc, 0x0001); /* PGSEL */ 1651 OUTW(dp, 0x00e4, 0x189c); /* PMDCSR */ 1652 OUTW(dp, 0x00fc, 0x0000); /* TSTDAT */ 1653 OUTW(dp, 0x00f4, 0x5040); /* DSPCFG */ 1654 OUTW(dp, 0x00f8, 0x008c); /* SDCFG */ 1655 OUTW(dp, 0x00cc, 0x0000); /* PGSEL */ 1656 1657 DPRINTF(0, (CE_CONT, 1658 CONS "%s: PHY patched %04x %04x %04x %04x %04x", 1659 dp->name, 1660 INW(dp, 0x00cc), /* PGSEL */ 1661 INW(dp, 0x00e4), /* PMDCSR */ 1662 INW(dp, 0x00fc), /* TSTDAT */ 1663 INW(dp, 0x00f4), /* DSPCFG */ 1664 INW(dp, 0x00f8))); /* SDCFG */ 1665 } else if (((srr ^ SRR_REV_DP83815DVNG) & 0xff00) == 0 || 1666 ((srr ^ SRR_REV_DP83816AVNG) & 0xff00) == 0) { 1667 /* 1668 * Additional packets for later chipset 1669 */ 1670 OUTW(dp, 0x00cc, 0x0001); /* PGSEL */ 1671 OUTW(dp, 0x00e4, 0x189c); /* PMDCSR */ 1672 OUTW(dp, 0x00cc, 0x0000); /* PGSEL */ 1673 1674 DPRINTF(0, (CE_CONT, 1675 CONS "%s: PHY patched %04x %04x", 1676 dp->name, 1677 INW(dp, 0x00cc), /* PGSEL */ 1678 INW(dp, 0x00e4))); /* PMDCSR */ 1679 } 1680 1681 return (gem_mii_config_default(dp)); 1682 } 1683 1684 static int 1685 sfe_mii_probe_dp83815(struct gem_dev *dp) 1686 { 1687 uint32_t val; 1688 1689 /* try external phy first */ 1690 DPRINTF(0, (CE_CONT, CONS "%s: %s: trying external phy", 1691 dp->name, __func__)); 1692 dp->mii_phy_addr = 0; 1693 dp->gc.gc_mii_sync = &sfe_mii_sync_sis900; 1694 dp->gc.gc_mii_read = &sfe_mii_read_sis900; 1695 dp->gc.gc_mii_write = &sfe_mii_write_sis900; 1696 1697 val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG); 1698 OUTL(dp, CFG, val | CFG_EXT_PHY | CFG_PHY_DIS); 1699 1700 if (gem_mii_probe_default(dp) == GEM_SUCCESS) { 1701 return (GEM_SUCCESS); 1702 } 1703 1704 /* switch to internal phy */ 1705 DPRINTF(0, (CE_CONT, CONS "%s: %s: switching to internal phy", 1706 dp->name, __func__)); 1707 dp->mii_phy_addr = -1; 1708 dp->gc.gc_mii_sync = &sfe_mii_sync_dp83815; 1709 dp->gc.gc_mii_read = &sfe_mii_read_dp83815; 1710 dp->gc.gc_mii_write = &sfe_mii_write_dp83815; 1711 1712 val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG); 1713 OUTL(dp, CFG, val | CFG_PAUSE_ADV | CFG_PHY_RST); 1714 drv_usecwait(100); /* keep to assert RST bit for a while */ 1715 OUTL(dp, CFG, val | CFG_PAUSE_ADV); 1716 1717 /* wait for PHY reset */ 1718 delay(drv_usectohz(10000)); 1719 1720 return (gem_mii_probe_default(dp)); 1721 } 1722 1723 static int 1724 sfe_mii_init_dp83815(struct gem_dev *dp) 1725 { 1726 uint32_t val; 1727 1728 val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG); 1729 1730 if (dp->mii_phy_addr == -1) { 1731 /* select internal phy */ 1732 OUTL(dp, CFG, val | CFG_PAUSE_ADV); 1733 } else { 1734 /* select external phy */ 1735 OUTL(dp, CFG, val | CFG_EXT_PHY | CFG_PHY_DIS); 1736 } 1737 1738 return (GEM_SUCCESS); 1739 } 1740 1741 /* 1742 * MII routines for SiS900 1743 */ 1744 #define MDIO_DELAY(dp) {(void) INL(dp, MEAR); (void) INL(dp, MEAR); } 1745 static void 1746 sfe_mii_sync_sis900(struct gem_dev *dp) 1747 { 1748 int i; 1749 1750 /* send 32 ONE's to make MII line idle */ 1751 for (i = 0; i < 32; i++) { 1752 OUTL(dp, MEAR, MEAR_MDDIR | MEAR_MDIO); 1753 MDIO_DELAY(dp); 1754 OUTL(dp, MEAR, MEAR_MDDIR | MEAR_MDIO | MEAR_MDC); 1755 MDIO_DELAY(dp); 1756 } 1757 } 1758 1759 static int 1760 sfe_mii_config_sis900(struct gem_dev *dp) 1761 { 1762 struct sfe_dev *lp = dp->private; 1763 1764 /* Do chip depend setup */ 1765 if ((dp->mii_phy_id & PHY_MASK) == PHY_ICS1893) { 1766 /* workaround for ICS1893 PHY */ 1767 gem_mii_write(dp, 0x0018, 0xD200); 1768 } 1769 1770 if (lp->revid == SIS630E_900_REV) { 1771 /* 1772 * SiS 630E has bugs on default values 1773 * of PHY registers 1774 */ 1775 gem_mii_write(dp, MII_AN_ADVERT, 0x05e1); 1776 gem_mii_write(dp, MII_CONFIG1, 0x0022); 1777 gem_mii_write(dp, MII_CONFIG2, 0xff00); 1778 gem_mii_write(dp, MII_MASK, 0xffc0); 1779 } 1780 sfe_set_eq_sis630(dp); 1781 1782 return (gem_mii_config_default(dp)); 1783 } 1784 1785 static uint16_t 1786 sfe_mii_read_sis900(struct gem_dev *dp, uint_t reg) 1787 { 1788 uint32_t cmd; 1789 uint16_t ret; 1790 int i; 1791 uint32_t data; 1792 1793 cmd = MII_READ_CMD(dp->mii_phy_addr, reg); 1794 1795 for (i = 31; i >= 18; i--) { 1796 data = ((cmd >> i) & 1) << MEAR_MDIO_SHIFT; 1797 OUTL(dp, MEAR, data | MEAR_MDDIR); 1798 MDIO_DELAY(dp); 1799 OUTL(dp, MEAR, data | MEAR_MDDIR | MEAR_MDC); 1800 MDIO_DELAY(dp); 1801 } 1802 1803 /* turn around cycle */ 1804 OUTL(dp, MEAR, 0); 1805 MDIO_DELAY(dp); 1806 1807 /* get response from PHY */ 1808 OUTL(dp, MEAR, MEAR_MDC); 1809 MDIO_DELAY(dp); 1810 1811 OUTL(dp, MEAR, 0); 1812 #if DEBUG_LEBEL > 0 1813 (void) INL(dp, MEAR); /* delay */ 1814 if (INL(dp, MEAR) & MEAR_MDIO) { 1815 cmn_err(CE_WARN, "%s: PHY@%d not responded", 1816 dp->name, dp->mii_phy_addr); 1817 } 1818 #else 1819 MDIO_DELAY(dp); 1820 #endif 1821 /* terminate response cycle */ 1822 OUTL(dp, MEAR, MEAR_MDC); 1823 MDIO_DELAY(dp); 1824 1825 ret = 0; /* to avoid lint errors */ 1826 for (i = 16; i > 0; i--) { 1827 OUTL(dp, MEAR, 0); 1828 (void) INL(dp, MEAR); /* delay */ 1829 ret = (ret << 1) | ((INL(dp, MEAR) >> MEAR_MDIO_SHIFT) & 1); 1830 OUTL(dp, MEAR, MEAR_MDC); 1831 MDIO_DELAY(dp); 1832 } 1833 1834 /* send two idle(Z) bits to terminate the read cycle */ 1835 for (i = 0; i < 2; i++) { 1836 OUTL(dp, MEAR, 0); 1837 MDIO_DELAY(dp); 1838 OUTL(dp, MEAR, MEAR_MDC); 1839 MDIO_DELAY(dp); 1840 } 1841 1842 return (ret); 1843 } 1844 1845 static void 1846 sfe_mii_write_sis900(struct gem_dev *dp, uint_t reg, uint16_t val) 1847 { 1848 uint32_t cmd; 1849 int i; 1850 uint32_t data; 1851 1852 cmd = MII_WRITE_CMD(dp->mii_phy_addr, reg, val); 1853 1854 for (i = 31; i >= 0; i--) { 1855 data = ((cmd >> i) & 1) << MEAR_MDIO_SHIFT; 1856 OUTL(dp, MEAR, data | MEAR_MDDIR); 1857 MDIO_DELAY(dp); 1858 OUTL(dp, MEAR, data | MEAR_MDDIR | MEAR_MDC); 1859 MDIO_DELAY(dp); 1860 } 1861 1862 /* send two idle(Z) bits to terminate the write cycle. */ 1863 for (i = 0; i < 2; i++) { 1864 OUTL(dp, MEAR, 0); 1865 MDIO_DELAY(dp); 1866 OUTL(dp, MEAR, MEAR_MDC); 1867 MDIO_DELAY(dp); 1868 } 1869 } 1870 #undef MDIO_DELAY 1871 1872 static void 1873 sfe_set_eq_sis630(struct gem_dev *dp) 1874 { 1875 uint16_t reg14h; 1876 uint16_t eq_value; 1877 uint16_t max_value; 1878 uint16_t min_value; 1879 int i; 1880 uint8_t rev; 1881 struct sfe_dev *lp = dp->private; 1882 1883 rev = lp->revid; 1884 1885 if (!(rev == SIS630E_900_REV || rev == SIS630EA1_900_REV || 1886 rev == SIS630A_900_REV || rev == SIS630ET_900_REV)) { 1887 /* it doesn't have a internal PHY */ 1888 return; 1889 } 1890 1891 if (dp->mii_state == MII_STATE_LINKUP) { 1892 reg14h = gem_mii_read(dp, MII_RESV); 1893 gem_mii_write(dp, MII_RESV, (0x2200 | reg14h) & 0xBFFF); 1894 1895 eq_value = (0x00f8 & gem_mii_read(dp, MII_RESV)) >> 3; 1896 max_value = min_value = eq_value; 1897 for (i = 1; i < 10; i++) { 1898 eq_value = (0x00f8 & gem_mii_read(dp, MII_RESV)) >> 3; 1899 max_value = max(eq_value, max_value); 1900 min_value = min(eq_value, min_value); 1901 } 1902 1903 /* for 630E, rule to determine the equalizer value */ 1904 if (rev == SIS630E_900_REV || rev == SIS630EA1_900_REV || 1905 rev == SIS630ET_900_REV) { 1906 if (max_value < 5) { 1907 eq_value = max_value; 1908 } else if (5 <= max_value && max_value < 15) { 1909 eq_value = 1910 max(max_value + 1, 1911 min_value + 2); 1912 } else if (15 <= max_value) { 1913 eq_value = 1914 max(max_value + 5, 1915 min_value + 6); 1916 } 1917 } 1918 /* for 630B0&B1, rule to determine the equalizer value */ 1919 else 1920 if (rev == SIS630A_900_REV && 1921 (lp->bridge_revid == SIS630B0 || 1922 lp->bridge_revid == SIS630B1)) { 1923 1924 if (max_value == 0) { 1925 eq_value = 3; 1926 } else { 1927 eq_value = (max_value + min_value + 1)/2; 1928 } 1929 } 1930 /* write equalizer value and setting */ 1931 reg14h = gem_mii_read(dp, MII_RESV) & ~0x02f8; 1932 reg14h |= 0x6000 | (eq_value << 3); 1933 gem_mii_write(dp, MII_RESV, reg14h); 1934 } else { 1935 reg14h = (gem_mii_read(dp, MII_RESV) & ~0x4000) | 0x2000; 1936 if (rev == SIS630A_900_REV && 1937 (lp->bridge_revid == SIS630B0 || 1938 lp->bridge_revid == SIS630B1)) { 1939 1940 reg14h |= 0x0200; 1941 } 1942 gem_mii_write(dp, MII_RESV, reg14h); 1943 } 1944 } 1945 1946 /* ======================================================== */ 1947 /* 1948 * OS depend (device driver) routine 1949 */ 1950 /* ======================================================== */ 1951 static void 1952 sfe_chipinfo_init_sis900(struct gem_dev *dp) 1953 { 1954 int rev; 1955 struct sfe_dev *lp = (struct sfe_dev *)dp->private; 1956 1957 rev = lp->revid; 1958 1959 if (rev == SIS630E_900_REV /* 0x81 */) { 1960 /* sis630E */ 1961 lp->get_mac_addr = &sfe_get_mac_addr_sis630e; 1962 } else if (rev > 0x81 && rev <= 0x90) { 1963 /* 630S, 630EA1, 630ET, 635A */ 1964 lp->get_mac_addr = &sfe_get_mac_addr_sis635; 1965 } else if (rev == SIS962_900_REV /* 0x91 */) { 1966 /* sis962 or later */ 1967 lp->get_mac_addr = &sfe_get_mac_addr_sis962; 1968 } else { 1969 /* sis900 */ 1970 lp->get_mac_addr = &sfe_get_mac_addr_sis900; 1971 } 1972 1973 lp->bridge_revid = 0; 1974 1975 if (rev == SIS630E_900_REV || rev == SIS630EA1_900_REV || 1976 rev == SIS630A_900_REV || rev == SIS630ET_900_REV) { 1977 /* 1978 * read host bridge revision 1979 */ 1980 dev_info_t *bridge; 1981 ddi_acc_handle_t bridge_handle; 1982 1983 if ((bridge = sfe_search_pci_dev(0x1039, 0x630)) == NULL) { 1984 cmn_err(CE_WARN, 1985 "%s: cannot find host bridge (pci1039,630)", 1986 dp->name); 1987 return; 1988 } 1989 1990 if (pci_config_setup(bridge, &bridge_handle) != DDI_SUCCESS) { 1991 cmn_err(CE_WARN, "%s: pci_config_setup failed", 1992 dp->name); 1993 return; 1994 } 1995 1996 lp->bridge_revid = 1997 pci_config_get8(bridge_handle, PCI_CONF_REVID); 1998 pci_config_teardown(&bridge_handle); 1999 } 2000 } 2001 2002 static int 2003 sfe_attach_chip(struct gem_dev *dp) 2004 { 2005 struct sfe_dev *lp = (struct sfe_dev *)dp->private; 2006 2007 DPRINTF(4, (CE_CONT, CONS "!%s: %s called", dp->name, __func__)); 2008 2009 /* setup chip-depend get_mac_address function */ 2010 if (lp->chip->chip_type == CHIPTYPE_SIS900) { 2011 sfe_chipinfo_init_sis900(dp); 2012 } else { 2013 lp->get_mac_addr = &sfe_get_mac_addr_dp83815; 2014 } 2015 2016 /* read MAC address */ 2017 if (!(lp->get_mac_addr)(dp)) { 2018 cmn_err(CE_WARN, 2019 "!%s: %s: failed to get factory mac address" 2020 " please specify a mac address in sfe.conf", 2021 dp->name, __func__); 2022 return (GEM_FAILURE); 2023 } 2024 2025 if (lp->chip->chip_type == CHIPTYPE_DP83815) { 2026 dp->mii_phy_addr = -1; /* no need to scan PHY */ 2027 dp->misc_flag |= GEM_VLAN_SOFT; 2028 dp->txthr += 4; /* VTAG_SIZE */ 2029 } 2030 dp->txthr = min(dp->txthr, TXFIFOSIZE - 2); 2031 2032 return (GEM_SUCCESS); 2033 } 2034 2035 static int 2036 sfeattach(dev_info_t *dip, ddi_attach_cmd_t cmd) 2037 { 2038 int unit; 2039 const char *drv_name; 2040 int i; 2041 ddi_acc_handle_t conf_handle; 2042 uint16_t vid; 2043 uint16_t did; 2044 uint8_t rev; 2045 #ifdef DEBUG_LEVEL 2046 uint32_t iline; 2047 uint8_t latim; 2048 #endif 2049 struct chip_info *p; 2050 struct gem_dev *dp; 2051 struct sfe_dev *lp; 2052 caddr_t base; 2053 ddi_acc_handle_t regs_ha; 2054 struct gem_conf *gcp; 2055 2056 unit = ddi_get_instance(dip); 2057 drv_name = ddi_driver_name(dip); 2058 2059 DPRINTF(3, (CE_CONT, CONS "%s%d: sfeattach: called", drv_name, unit)); 2060 2061 /* 2062 * Common codes after power-up 2063 */ 2064 if (pci_config_setup(dip, &conf_handle) != DDI_SUCCESS) { 2065 cmn_err(CE_WARN, "%s%d: ddi_regs_map_setup failed", 2066 drv_name, unit); 2067 goto err; 2068 } 2069 2070 vid = pci_config_get16(conf_handle, PCI_CONF_VENID); 2071 did = pci_config_get16(conf_handle, PCI_CONF_DEVID); 2072 rev = pci_config_get16(conf_handle, PCI_CONF_REVID); 2073 #ifdef DEBUG_LEVEL 2074 iline = pci_config_get32(conf_handle, PCI_CONF_ILINE); 2075 latim = pci_config_get8(conf_handle, PCI_CONF_LATENCY_TIMER); 2076 #endif 2077 #ifdef DEBUG_BUILT_IN_SIS900 2078 rev = SIS630E_900_REV; 2079 #endif 2080 for (i = 0, p = sfe_chiptbl; i < CHIPTABLESIZE; i++, p++) { 2081 if (p->venid == vid && p->devid == did) { 2082 /* found */ 2083 goto chip_found; 2084 } 2085 } 2086 2087 /* Not found */ 2088 cmn_err(CE_WARN, 2089 "%s%d: sfe_attach: wrong PCI venid/devid (0x%x, 0x%x)", 2090 drv_name, unit, vid, did); 2091 pci_config_teardown(&conf_handle); 2092 goto err; 2093 2094 chip_found: 2095 pci_config_put16(conf_handle, PCI_CONF_COMM, 2096 PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME | 2097 pci_config_get16(conf_handle, PCI_CONF_COMM)); 2098 2099 /* ensure D0 mode */ 2100 (void) gem_pci_set_power_state(dip, conf_handle, PCI_PMCSR_D0); 2101 2102 pci_config_teardown(&conf_handle); 2103 2104 switch (cmd) { 2105 case DDI_RESUME: 2106 return (gem_resume(dip)); 2107 2108 case DDI_ATTACH: 2109 2110 DPRINTF(0, (CE_CONT, 2111 CONS "%s%d: ilr 0x%08x, latency_timer:0x%02x", 2112 drv_name, unit, iline, latim)); 2113 2114 /* 2115 * Map in the device registers. 2116 */ 2117 if (gem_pci_regs_map_setup(dip, 2118 (sfe_use_pcimemspace && p->chip_type == CHIPTYPE_DP83815) 2119 ? PCI_ADDR_MEM32 : PCI_ADDR_IO, PCI_ADDR_MASK, 2120 &sfe_dev_attr, &base, ®s_ha) != DDI_SUCCESS) { 2121 cmn_err(CE_WARN, 2122 "%s%d: ddi_regs_map_setup failed", 2123 drv_name, unit); 2124 goto err; 2125 } 2126 2127 /* 2128 * construct gem configuration 2129 */ 2130 gcp = kmem_zalloc(sizeof (*gcp), KM_SLEEP); 2131 2132 /* name */ 2133 (void) sprintf(gcp->gc_name, "%s%d", drv_name, unit); 2134 2135 /* consistency on tx and rx */ 2136 gcp->gc_tx_buf_align = sizeof (uint8_t) - 1; 2137 gcp->gc_tx_max_frags = MAXTXFRAGS; 2138 gcp->gc_tx_max_descs_per_pkt = gcp->gc_tx_max_frags; 2139 gcp->gc_tx_desc_unit_shift = 4; /* 16 byte */ 2140 gcp->gc_tx_buf_size = TX_BUF_SIZE; 2141 gcp->gc_tx_buf_limit = gcp->gc_tx_buf_size; 2142 gcp->gc_tx_ring_size = TX_RING_SIZE; 2143 gcp->gc_tx_ring_limit = gcp->gc_tx_ring_size; 2144 gcp->gc_tx_auto_pad = B_TRUE; 2145 gcp->gc_tx_copy_thresh = sfe_tx_copy_thresh; 2146 gcp->gc_tx_desc_write_oo = B_TRUE; 2147 2148 gcp->gc_rx_buf_align = sizeof (uint8_t) - 1; 2149 gcp->gc_rx_max_frags = MAXRXFRAGS; 2150 gcp->gc_rx_desc_unit_shift = 4; 2151 gcp->gc_rx_ring_size = RX_RING_SIZE; 2152 gcp->gc_rx_buf_max = RX_BUF_SIZE; 2153 gcp->gc_rx_copy_thresh = sfe_rx_copy_thresh; 2154 2155 /* map attributes */ 2156 gcp->gc_dev_attr = sfe_dev_attr; 2157 gcp->gc_buf_attr = sfe_buf_attr; 2158 gcp->gc_desc_attr = sfe_buf_attr; 2159 2160 /* dma attributes */ 2161 gcp->gc_dma_attr_desc = sfe_dma_attr_desc; 2162 2163 gcp->gc_dma_attr_txbuf = sfe_dma_attr_buf; 2164 gcp->gc_dma_attr_txbuf.dma_attr_align = gcp->gc_tx_buf_align+1; 2165 gcp->gc_dma_attr_txbuf.dma_attr_sgllen = gcp->gc_tx_max_frags; 2166 2167 gcp->gc_dma_attr_rxbuf = sfe_dma_attr_buf; 2168 gcp->gc_dma_attr_rxbuf.dma_attr_align = gcp->gc_rx_buf_align+1; 2169 gcp->gc_dma_attr_rxbuf.dma_attr_sgllen = gcp->gc_rx_max_frags; 2170 2171 /* time out parameters */ 2172 gcp->gc_tx_timeout = 3*ONESEC; 2173 gcp->gc_tx_timeout_interval = ONESEC; 2174 if (p->chip_type == CHIPTYPE_DP83815) { 2175 /* workaround for tx hang */ 2176 gcp->gc_tx_timeout_interval = ONESEC/20; /* 50mS */ 2177 } 2178 2179 /* MII timeout parameters */ 2180 gcp->gc_mii_link_watch_interval = ONESEC; 2181 gcp->gc_mii_an_watch_interval = ONESEC/5; 2182 gcp->gc_mii_reset_timeout = MII_RESET_TIMEOUT; /* 1 sec */ 2183 gcp->gc_mii_an_timeout = MII_AN_TIMEOUT; /* 5 sec */ 2184 gcp->gc_mii_an_wait = 0; 2185 gcp->gc_mii_linkdown_timeout = MII_LINKDOWN_TIMEOUT; 2186 2187 /* setting for general PHY */ 2188 gcp->gc_mii_an_delay = 0; 2189 gcp->gc_mii_linkdown_action = MII_ACTION_RSA; 2190 gcp->gc_mii_linkdown_timeout_action = MII_ACTION_RESET; 2191 gcp->gc_mii_dont_reset = B_FALSE; 2192 2193 2194 /* I/O methods */ 2195 2196 /* mac operation */ 2197 gcp->gc_attach_chip = &sfe_attach_chip; 2198 if (p->chip_type == CHIPTYPE_DP83815) { 2199 gcp->gc_reset_chip = &sfe_reset_chip_dp83815; 2200 } else { 2201 gcp->gc_reset_chip = &sfe_reset_chip_sis900; 2202 } 2203 gcp->gc_init_chip = &sfe_init_chip; 2204 gcp->gc_start_chip = &sfe_start_chip; 2205 gcp->gc_stop_chip = &sfe_stop_chip; 2206 #ifdef USE_MULTICAST_HASHTBL 2207 gcp->gc_multicast_hash = &sfe_mcast_hash; 2208 #endif 2209 if (p->chip_type == CHIPTYPE_DP83815) { 2210 gcp->gc_set_rx_filter = &sfe_set_rx_filter_dp83815; 2211 } else { 2212 gcp->gc_set_rx_filter = &sfe_set_rx_filter_sis900; 2213 } 2214 gcp->gc_set_media = &sfe_set_media; 2215 gcp->gc_get_stats = &sfe_get_stats; 2216 gcp->gc_interrupt = &sfe_interrupt; 2217 2218 /* descriptor operation */ 2219 gcp->gc_tx_desc_write = &sfe_tx_desc_write; 2220 gcp->gc_tx_start = &sfe_tx_start; 2221 gcp->gc_rx_desc_write = &sfe_rx_desc_write; 2222 gcp->gc_rx_start = NULL; 2223 2224 gcp->gc_tx_desc_stat = &sfe_tx_desc_stat; 2225 gcp->gc_rx_desc_stat = &sfe_rx_desc_stat; 2226 gcp->gc_tx_desc_init = &sfe_tx_desc_init; 2227 gcp->gc_rx_desc_init = &sfe_rx_desc_init; 2228 gcp->gc_tx_desc_clean = &sfe_tx_desc_clean; 2229 gcp->gc_rx_desc_clean = &sfe_rx_desc_clean; 2230 2231 /* mii operations */ 2232 if (p->chip_type == CHIPTYPE_DP83815) { 2233 gcp->gc_mii_probe = &sfe_mii_probe_dp83815; 2234 gcp->gc_mii_init = &sfe_mii_init_dp83815; 2235 gcp->gc_mii_config = &sfe_mii_config_dp83815; 2236 gcp->gc_mii_sync = &sfe_mii_sync_dp83815; 2237 gcp->gc_mii_read = &sfe_mii_read_dp83815; 2238 gcp->gc_mii_write = &sfe_mii_write_dp83815; 2239 gcp->gc_mii_tune_phy = NULL; 2240 gcp->gc_flow_control = FLOW_CONTROL_NONE; 2241 } else { 2242 gcp->gc_mii_probe = &gem_mii_probe_default; 2243 gcp->gc_mii_init = NULL; 2244 gcp->gc_mii_config = &sfe_mii_config_sis900; 2245 gcp->gc_mii_sync = &sfe_mii_sync_sis900; 2246 gcp->gc_mii_read = &sfe_mii_read_sis900; 2247 gcp->gc_mii_write = &sfe_mii_write_sis900; 2248 gcp->gc_mii_tune_phy = &sfe_set_eq_sis630; 2249 gcp->gc_flow_control = FLOW_CONTROL_RX_PAUSE; 2250 } 2251 2252 lp = kmem_zalloc(sizeof (*lp), KM_SLEEP); 2253 lp->chip = p; 2254 lp->revid = rev; 2255 lp->our_intr_bits = 0; 2256 lp->isr_pended = 0; 2257 2258 cmn_err(CE_CONT, CONS "%s%d: chip:%s rev:0x%02x", 2259 drv_name, unit, p->chip_name, rev); 2260 2261 dp = gem_do_attach(dip, 0, gcp, base, ®s_ha, 2262 lp, sizeof (*lp)); 2263 kmem_free(gcp, sizeof (*gcp)); 2264 2265 if (dp == NULL) { 2266 goto err_freelp; 2267 } 2268 2269 return (DDI_SUCCESS); 2270 2271 err_freelp: 2272 kmem_free(lp, sizeof (struct sfe_dev)); 2273 err: 2274 return (DDI_FAILURE); 2275 } 2276 return (DDI_FAILURE); 2277 } 2278 2279 static int 2280 sfedetach(dev_info_t *dip, ddi_detach_cmd_t cmd) 2281 { 2282 switch (cmd) { 2283 case DDI_SUSPEND: 2284 return (gem_suspend(dip)); 2285 2286 case DDI_DETACH: 2287 return (gem_do_detach(dip)); 2288 } 2289 return (DDI_FAILURE); 2290 } 2291 2292 /* ======================================================== */ 2293 /* 2294 * OS depend (loadable streams driver) routine 2295 */ 2296 /* ======================================================== */ 2297 DDI_DEFINE_STREAM_OPS(sfe_ops, nulldev, nulldev, sfeattach, sfedetach, 2298 nodev, NULL, D_MP, NULL, ddi_quiesce_not_supported); 2299 2300 static struct modldrv modldrv = { 2301 &mod_driverops, /* Type of module. This one is a driver */ 2302 ident, 2303 &sfe_ops, /* driver ops */ 2304 }; 2305 2306 static struct modlinkage modlinkage = { 2307 MODREV_1, &modldrv, NULL 2308 }; 2309 2310 /* ======================================================== */ 2311 /* 2312 * Loadable module support 2313 */ 2314 /* ======================================================== */ 2315 int 2316 _init(void) 2317 { 2318 int status; 2319 2320 DPRINTF(2, (CE_CONT, CONS "sfe: _init: called")); 2321 gem_mod_init(&sfe_ops, "sfe"); 2322 status = mod_install(&modlinkage); 2323 if (status != DDI_SUCCESS) { 2324 gem_mod_fini(&sfe_ops); 2325 } 2326 return (status); 2327 } 2328 2329 /* 2330 * _fini : done 2331 */ 2332 int 2333 _fini(void) 2334 { 2335 int status; 2336 2337 DPRINTF(2, (CE_CONT, CONS "sfe: _fini: called")); 2338 status = mod_remove(&modlinkage); 2339 if (status == DDI_SUCCESS) { 2340 gem_mod_fini(&sfe_ops); 2341 } 2342 return (status); 2343 } 2344 2345 int 2346 _info(struct modinfo *modinfop) 2347 { 2348 return (mod_info(&modlinkage, modinfop)); 2349 } 2350