1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _RGE_HW_H 27 #define _RGE_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/types.h> 34 35 36 /* 37 * First section: 38 * Identification of the various Realtek GigE chips 39 */ 40 41 /* 42 * Driver support device 43 */ 44 #define VENDOR_ID_REALTECK 0x10EC 45 #define DEVICE_ID_8169 0x8169 /* PCI */ 46 #define DEVICE_ID_8110 0x8169 /* PCI */ 47 #define DEVICE_ID_8168 0x8168 /* PCI-E */ 48 #define DEVICE_ID_8111 0x8168 /* PCI-E */ 49 #define DEVICE_ID_8169SC 0x8167 /* PCI */ 50 #define DEVICE_ID_8110SC 0x8167 /* PCI */ 51 #define DEVICE_ID_8101E 0x8136 /* 10/100M PCI-E */ 52 53 #define RGE_REGISTER_MAX 0x0100 54 55 56 /* 57 * Second section: 58 * Offsets of important registers & definitions for bits therein 59 */ 60 /* 61 * MAC address register, initial value is autoloaded from the 62 * EEPROM EthernetID field 63 */ 64 #define ID_0_REG 0x0000 65 #define ID_1_REG 0x0001 66 #define ID_2_REG 0x0002 67 #define ID_3_REG 0x0003 68 #define ID_4_REG 0x0004 69 #define ID_5_REG 0x0005 70 71 /* 72 * Multicast register 73 */ 74 #define MULTICAST_0_REG 0x0008 75 #define MULTICAST_1_REG 0x0009 76 #define MULTICAST_2_REG 0x000a 77 #define MULTICAST_3_REG 0x000b 78 #define MULTICAST_4_REG 0x000c 79 #define MULTICAST_5_REG 0x000d 80 #define MULTICAST_6_REG 0x000e 81 #define MULTICAST_7_REG 0x000f 82 #define RGE_MCAST_NUM 8 /* total 8 registers: MAR0 - MAR7 */ 83 84 /* 85 * Dump Tally Counter Command register 86 */ 87 #define DUMP_COUNTER_REG_0 0x0010 88 #define DUMP_COUNTER_REG_RESV 0x00000037 89 #define DUMP_START 0x00000008 90 #define DUMP_COUNTER_REG_1 0x0014 91 92 /* 93 * Register for start address of transmit descriptors 94 */ 95 #define NORMAL_TX_RING_ADDR_LO_REG 0x0020 96 #define NORMAL_TX_RING_ADDR_HI_REG 0x0024 97 #define HIGH_TX_RING_ADDR_LO_REG 0x0028 98 #define HIGH_TX_RING_ADDR_HI_REG 0x002c 99 100 /* 101 * Commond register 102 */ 103 #define RT_COMMAND_REG 0x0037 104 #define RT_COMMAND_RESV 0xe3 105 #define RT_COMMAND_RESET 0x10 106 #define RT_COMMAND_RX_ENABLE 0x08 107 #define RT_COMMAND_TX_ENABLE 0x04 108 109 /* 110 * Transmit priority polling register 111 */ 112 #define TX_RINGS_POLL_REG 0x0038 113 #define HIGH_TX_RING_POLL 0x80 114 #define NORMAL_TX_RING_POLL 0x40 115 #define FORCE_SW_INT 0x01 116 117 /* 118 * Interrupt mask & status register 119 */ 120 #define INT_MASK_REG 0x003c 121 #define INT_STATUS_REG 0x003e 122 #define SYS_ERR_INT 0x8000 123 #define TIME_OUT_INT 0x4000 124 #define SW_INT 0x0100 125 #define NO_TXDESC_INT 0x0080 126 #define RX_FIFO_OVERFLOW_INT 0x0040 127 #define LINK_CHANGE_INT 0x0020 128 #define NO_RXDESC_INT 0x0010 129 #define TX_ERR_INT 0x0008 130 #define TX_OK_INT 0x0004 131 #define RX_ERR_INT 0x0002 132 #define RX_OK_INT 0x0001 133 134 #define INT_REG_RESV 0x3e00 135 #define INT_MASK_ALL 0xffff 136 #define INT_MASK_NONE 0x0000 137 #define RGE_RX_INT (RX_OK_INT | RX_ERR_INT | \ 138 NO_RXDESC_INT) 139 #define RGE_INT_MASK (RGE_RX_INT | LINK_CHANGE_INT) 140 141 /* 142 * Transmit configuration register 143 */ 144 #define TX_CONFIG_REG 0x0040 145 #define TX_CONFIG_REG_RESV 0x8070f8ff 146 #define HW_VERSION_ID_0 0x7c000000 147 #define INTER_FRAME_GAP_BITS 0x03080000 148 #define TX_INTERFRAME_GAP_802_3 0x03000000 149 #define HW_VERSION_ID_1 0x00800000 150 #define MAC_LOOPBACK_ENABLE 0x00060000 151 #define CRC_APPEND_ENABLE 0x00010000 152 #define TX_DMA_BURST_BITS 0x00000700 153 154 #define TX_DMA_BURST_UNLIMIT 0x00000700 155 #define TX_DMA_BURST_1024B 0x00000600 156 #define TX_DMA_BURST_512B 0x00000500 157 #define TX_DMA_BURST_256B 0x00000400 158 #define TX_DMA_BURST_128B 0x00000300 159 #define TX_DMA_BURST_64B 0x00000200 160 #define TX_DMA_BURST_32B 0x00000100 161 #define TX_DMA_BURST_16B 0x00000000 162 163 #define MAC_VER_8169 0x00000000 164 #define MAC_VER_8169S_D 0x00800000 165 #define MAC_VER_8169S_E 0x04000000 166 #define MAC_VER_8169SB 0x10000000 167 #define MAC_VER_8169SC 0x18000000 168 #define MAC_VER_8168 0x20000000 169 #define MAC_VER_8168B_B 0x30000000 170 #define MAC_VER_8168B_C 0x38000000 171 #define MAC_VER_8168B_D 0x3c000000 172 #define MAC_VER_8101E 0x34000000 173 #define MAC_VER_8101E_B 0x24800000 174 #define MAC_VER_8101E_C 0x34800000 175 176 #define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \ 177 TX_DMA_BURST_1024B) 178 /* 179 * Receive configuration register 180 */ 181 #define RX_CONFIG_REG 0x0044 182 #define RX_CONFIG_REG_RESV 0xfffe1880 183 #define RX_RER8_ENABLE 0x00010000 184 #define RX_FIFO_THRESHOLD_BITS 0x0000e000 185 #define RX_FIFO_THRESHOLD_NONE 0x0000e000 186 #define RX_FIFO_THRESHOLD_1024B 0x0000c000 187 #define RX_FIFO_THRESHOLD_512B 0x0000a000 188 #define RX_FIFO_THRESHOLD_256B 0x00008000 189 #define RX_FIFO_THRESHOLD_128B 0x00006000 190 #define RX_FIFO_THRESHOLD_64B 0x00004000 191 #define RX_DMA_BURST_BITS 0x00000700 192 #define RX_DMA_BURST_UNLIMITED 0x00000700 193 #define RX_DMA_BURST_1024B 0x00000600 194 #define RX_DMA_BURST_512B 0x00000500 195 #define RX_DMA_BURST_256B 0x00000400 196 #define RX_DMA_BURST_128B 0x00000300 197 #define RX_DMA_BURST_64B 0x00000200 198 #define RX_EEPROM_9356 0x00000040 199 #define RX_ACCEPT_ERR_PKT 0x00000020 200 #define RX_ACCEPT_RUNT_PKT 0x00000010 201 #define RX_ACCEPT_BROADCAST_PKT 0x000000008 202 #define RX_ACCEPT_MULTICAST_PKT 0x000000004 203 #define RX_ACCEPT_MAC_MATCH_PKT 0x000000002 204 #define RX_ACCEPT_ALL_PKT 0x000000001 205 206 #define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \ 207 RX_DMA_BURST_1024B | \ 208 RX_ACCEPT_BROADCAST_PKT | \ 209 RX_ACCEPT_MULTICAST_PKT | \ 210 RX_ACCEPT_MAC_MATCH_PKT) 211 212 /* 213 * Timer count register 214 */ 215 #define TIMER_COUNT_REG 0x0048 216 217 /* 218 * Missed packet counter: indicates the number of packets 219 * discarded due to Rx FIFO overflow 220 */ 221 #define RX_PKT_MISS_COUNT_REG 0x004c 222 223 /* 224 * 93c46(93c56) commond register: 225 */ 226 #define RT_93c46_COMMOND_REG 0x0050 227 #define RT_93c46_MODE_BITS 0xc0 228 #define RT_93c46_MODE_NORMAL 0x00 229 #define RT_93c46_MODE_AUTOLOAD 0x40 230 #define RT_93c46_MODE_PROGRAM 0x80 231 #define RT_93c46_MODE_CONFIG 0xc0 232 233 #define RT_93c46_EECS 0x08 234 #define RT_93c46_EESK 0x04 235 #define RT_93c46_EEDI 0x02 236 #define RT_93c46_EEDO 0x01 237 238 /* 239 * Configuration registers 240 */ 241 #define RT_CONFIG_0_REG 0x0051 242 #define RT_CONFIG_1_REG 0x0052 243 #define RT_CONFIG_2_REG 0x0053 244 #define RT_CONFIG_3_REG 0x0054 245 #define RT_CONFIG_4_REG 0x0055 246 #define RT_CONFIG_5_REG 0x0056 247 248 /* 249 * Config 5 Register Bits 250 */ 251 #define RT_UNI_WAKE_FRAME 0x10 252 #define RT_MUL_WAKE_FRAME 0x20 253 #define RT_BRO_WAKE_FRAME 0x40 254 255 /* 256 * Timer interrupt register 257 */ 258 #define TIMER_INT_REG 0x0058 259 #define TIMER_INT_NONE 0x00000000 260 261 /* 262 * PHY access register 263 */ 264 #define PHY_ACCESS_REG 0x0060 265 #define PHY_ACCESS_WR_FLAG 0x80000000 266 #define PHY_ACCESS_REG_BITS 0x001f0000 267 #define PHY_ACCESS_DATA_BITS 0x0000ffff 268 #define PHY_DATA_MASK 0xffff 269 #define PHY_REG_MASK 0x1f 270 #define PHY_REG_SHIFT 16 271 272 /* 273 * CSI data register (for PCIE chipset) 274 */ 275 #define RT_CSI_DATA_REG 0x0064 276 277 /* 278 * CSI access register (for PCIE chipset) 279 */ 280 #define RT_CSI_ACCESS_REG 0x0068 281 282 /* 283 * PHY status register 284 */ 285 #define PHY_STATUS_REG 0x006c 286 #define PHY_STATUS_TBI 0x80 287 #define PHY_STATUS_TX_FLOW 0x40 288 #define PHY_STATUS_RX_FLOW 0x20 289 #define PHY_STATUS_1000MF 0x10 290 #define PHY_STATUS_100M 0x08 291 #define PHY_STATUS_10M 0x04 292 #define PHY_STATUS_LINK_UP 0x02 293 #define PHY_STATUS_DUPLEX_FULL 0x01 294 295 #define RGE_SPEED_1000M 1000 296 #define RGE_SPEED_100M 100 297 #define RGE_SPEED_10M 10 298 #define RGE_SPEED_UNKNOWN 0 299 300 /* 301 * EPHY access register (for PCIE chipset) 302 */ 303 #define EPHY_ACCESS_REG 0x0080 304 #define EPHY_ACCESS_WR_FLAG 0x80000000 305 #define EPHY_ACCESS_REG_BITS 0x001f0000 306 #define EPHY_ACCESS_DATA_BITS 0x0000ffff 307 #define EPHY_DATA_MASK 0xffff 308 #define EPHY_REG_MASK 0x1f 309 #define EPHY_REG_SHIFT 16 310 311 /* 312 * Receive packet maximum size register 313 * -- the maximum rx size supported is (16K - 1) bytes 314 */ 315 #define RX_MAX_PKTSIZE_REG 0x00da 316 #define RX_PKTSIZE_JUMBO 0x1bfa /* 7K bytes */ 317 #define RX_PKTSIZE_STD 0x05fa /* 1530 bytes */ 318 #define RX_PKTSIZE_STD_8101E 0x3fff 319 320 /* 321 * C+ command register 322 */ 323 #define CPLUS_COMMAND_REG 0x00e0 324 #define CPLUS_RESERVE 0xfd87 325 #define CPLUS_BIT14 0x4000 326 #define CPLUS_BIG_ENDIAN 0x0400 327 #define RX_VLAN_DETAG 0x0040 328 #define RX_CKSM_OFFLOAD 0x0020 329 #define DUAL_PCI_CYCLE 0x0010 330 #define MUL_PCI_RW_ENABLE 0x0008 331 332 /* 333 * Receive descriptor start address 334 */ 335 #define RX_RING_ADDR_LO_REG 0x00e4 336 #define RX_RING_ADDR_HI_REG 0x00e8 337 338 /* 339 * Max transmit packet size register 340 */ 341 #define TX_MAX_PKTSIZE_REG 0x00ec 342 #define TX_MAX_PKTSIZE_REG_RESV 0xc0 343 #define TX_PKTSIZE_JUMBO 0x3b /* Realtek suggested value */ 344 #define TX_PKTSIZE_STD 0x32 /* document suggested value */ 345 #define TX_PKTSIZE_STD_8101E 0x3f 346 347 #define RESV_82_REG 0x0082 348 #define RESV_E2_REG 0x00e2 349 350 /* 351 * PHY registers 352 */ 353 /* 354 * Basic mode control register 355 */ 356 #define PHY_BMCR_REG 0x00 357 #define PHY_RESET 0x8000 358 #define PHY_LOOPBACK 0x4000 359 #define PHY_SPEED_0 0x2000 360 #define PHY_SPEED_1 0x0040 361 #define PHY_SPEED_BITS (PHY_SPEED_0 | PHY_SPEED_1) 362 #define PHY_SPEED_1000M PHY_SPEED_1 363 #define PHY_SPEED_100M PHY_SPEED_0 364 #define PHY_SPEED_10M 0x0000 365 #define PHY_SPEED_RES (PHY_SPEED_0 | PHY_SPEED_1) 366 #define PHY_AUTO_NEGO 0x1000 367 #define PHY_RESTART_ANTO_NEGO 0x0200 368 #define PHY_DUPLEX_FULL 0x0100 369 #define PHY_BMCR_CLEAR 0xff40 370 371 /* 372 * Basic mode status register 373 */ 374 #define PHY_BMSR_REG 0x01 375 #define PHY_100BASE_T4 0x8000 376 #define PHY_100BASE_TX_FULL 0x4000 377 #define PHY_100BASE_TX_HALF 0x2000 378 #define PHY_10BASE_T_FULL 0x1000 379 #define PHY_10BASE_T_HALF 0x0800 380 #define PHY_100BASE_T2_FULL 0x0400 381 #define PHY_100BASE_T2_HALF 0x0200 382 #define PHY_1000BASE_T_EXT 0x0100 383 #define PHY_AUTO_NEGO_END 0x0020 384 #define PHY_REMOTE_FAULT 0x0010 385 #define PHY_AUTO_NEGO_ABLE 0x0008 386 #define PHY_LINK_UP 0x0004 387 #define PHY_JABBER_DETECT 0x0002 388 #define PHY_EXT_ABLE 0x0001 389 390 /* 391 * PHY identifier register 392 */ 393 #define PHY_ID_REG_1 0x02 394 #define PHY_ID_REG_2 0x03 395 #define PHY_VER_MASK 0x000f 396 #define PHY_VER_S 0x0000 397 #define PHY_VER_SB 0x0010 398 399 /* 400 * Auto-negotiation advertising register 401 */ 402 #define PHY_ANAR_REG 0x04 403 #define ANAR_NEXT_PAGE 0x8000 404 #define ANAR_REMOTE_FAULT 0x2000 405 #define ANAR_ASY_PAUSE 0x0800 406 #define ANAR_PAUSE 0x0400 407 #define ANAR_100BASE_T4 0x0200 408 #define ANAR_100BASE_TX_FULL 0x0100 409 #define ANAR_100BASE_TX_HALF 0x0080 410 #define ANAR_10BASE_T_FULL 0x0040 411 #define ANAR_10BASE_T_HALF 0x0020 412 #define ANAR_RESV_BITS 0x501f 413 414 /* 415 * Auto-negotiation link partner ability register 416 */ 417 #define PHY_ANLPAR_REG 0x05 418 419 /* 420 * Auto-negotiation expansion register 421 */ 422 #define PHY_ANER_REG 0x06 423 424 /* 425 * Auto-negotiation next page transmit register 426 */ 427 #define PHY_ANNPTR_REG 0x07 428 429 /* 430 * Auto-negotiation next page receive register 431 */ 432 #define PHY_ANNPRR_REG 0x08 433 434 /* 435 * 1000Base-T control register 436 */ 437 #define PHY_GBCR_REG 0x09 438 #define GBCR_MODE_JITTER 0x2000 439 #define GBCR_MODE_MASTER 0x4000 440 #define GBCR_MODE_SLAVE 0x6000 441 #define GBCR_1000BASE_T_FULL 0x0200 442 #define GBCR_1000BASE_T_HALF 0x0100 443 #define GBCR_DEFAULT 0x273a 444 445 /* 446 * 1000Base-T status register 447 */ 448 #define PHY_GBSR_REG 0x0a 449 #define LP_1000BASE_T_FULL 0x0800 450 #define LP_1000BASE_T_HALF 0x0400 451 452 /* 453 * 1000Base-T extended status register 454 */ 455 #define PHY_GBESR_REG 0x0f 456 457 #define PHY_1F_REG 0x1f 458 #define PHY_1D_REG 0x1d 459 #define PHY_1C_REG 0x1c 460 #define PHY_1B_REG 0x1b 461 #define PHY_18_REG 0x18 462 #define PHY_15_REG 0x15 463 #define PHY_13_REG 0x13 464 #define PHY_12_REG 0x12 465 #define PHY_0E_REG 0x0e 466 #define PHY_0C_REG 0x0c 467 #define PHY_0B_REG 0x0b 468 469 /* 470 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 471 */ 472 473 #define MII_AN_LPNXTPG 8 474 #define MII_1000BASE_T_CONTROL 9 475 #define MII_1000BASE_T_STATUS 10 476 #define MII_IEEE_EXT_STATUS 15 477 478 /* 479 * New bits in the MII_CONTROL register 480 */ 481 #define MII_CONTROL_1000MB 0x0040 482 483 /* 484 * New bits in the MII_AN_ADVERT register 485 */ 486 #define MII_ABILITY_ASYM_PAUSE 0x0800 487 #define MII_ABILITY_PAUSE 0x0400 488 489 /* 490 * Values for the <selector> field of the MII_AN_ADVERT register 491 */ 492 #define MII_AN_SELECTOR_8023 0x0001 493 494 /* 495 * Bits in the MII_1000BASE_T_CONTROL register 496 * 497 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 498 * (otherwise, roles are automatically negotiated). When this bit is set, 499 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 500 */ 501 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 502 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 503 #define MII_1000BT_CTL_ADV_FDX 0x0200 504 #define MII_1000BT_CTL_ADV_HDX 0x0100 505 506 /* 507 * Vendor-specific MII registers 508 */ 509 #define MII_EXT_CONTROL MII_VENDOR(0) 510 #define MII_EXT_STATUS MII_VENDOR(1) 511 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 512 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 513 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 514 #define MII_AUX_CONTROL MII_VENDOR(8) 515 #define MII_AUX_STATUS MII_VENDOR(9) 516 #define MII_INTR_STATUS MII_VENDOR(10) 517 #define MII_INTR_MASK MII_VENDOR(11) 518 #define MII_HCD_STATUS MII_VENDOR(13) 519 520 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 521 522 /* 523 * Bits in the MII_AUX_STATUS register 524 */ 525 #define MII_AUX_STATUS_MODE_MASK 0x0700 526 #define MII_AUX_STATUS_MODE_1000_F 0x0700 527 #define MII_AUX_STATUS_MODE_1000_H 0x0600 528 #define MII_AUX_STATUS_MODE_100_F 0x0500 529 #define MII_AUX_STATUS_MODE_100_4 0x0400 530 #define MII_AUX_STATUS_MODE_100_H 0x0300 531 #define MII_AUX_STATUS_MODE_10_F 0x0200 532 #define MII_AUX_STATUS_MODE_10_H 0x0100 533 #define MII_AUX_STATUS_MODE_NONE 0x0000 534 #define MII_AUX_STATUS_MODE_SHIFT 8 535 536 #define MII_AUX_STATUS_PAR_FAULT 0x0080 537 #define MII_AUX_STATUS_REM_FAULT 0x0040 538 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 539 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 540 541 #define MII_AUX_STATUS_LINKUP 0x0004 542 #define MII_AUX_STATUS_RX_PAUSE 0x0002 543 #define MII_AUX_STATUS_TX_PAUSE 0x0001 544 545 /* 546 * Third section: 547 * Hardware-defined data structures 548 * 549 * Note that the chip is naturally little-endian, so, for a little-endian 550 * host, the structures defined below match those descibed in the PRM. 551 * For big-endian hosts, some structures have to be swapped around. 552 */ 553 554 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 555 #error Host endianness not defined 556 #endif 557 558 /* 559 * Architectural constants: absolute maximum numbers of each type of ring 560 */ 561 562 #define RGE_SEND_SLOTS 1024 563 #define RGE_RECV_SLOTS 1024 564 #define RGE_BUFF_SIZE_STD 1536 /* 1536 bytes */ 565 #define RGE_BUFF_SIZE_JUMBO 7168 /* maximum 7K */ 566 #define RGE_JUMBO_SIZE 7014 567 #define RGE_JUMBO_MTU 7000 568 #define RGE_STATS_DUMP_SIZE 64 569 570 typedef struct rge_bd { 571 volatile uint32_t flags_len; 572 volatile uint32_t vlan_tag; 573 volatile uint32_t host_buf_addr; 574 volatile uint32_t host_buf_addr_hi; 575 } rge_bd_t; 576 577 #define BD_FLAG_HW_OWN 0x80000000 578 #define BD_FLAG_EOR 0x40000000 579 #define BD_FLAG_PKT_START 0x20000000 580 #define BD_FLAG_PKT_END 0x10000000 581 582 #define RBD_FLAG_MULTICAST 0x08000000 583 #define RBD_FLAG_UNICAST 0x04000000 584 #define RBD_FLAG_BROADCAST 0x02000000 585 #define RBD_FLAG_PKT_4096 0x00400000 586 #define RBD_FLAG_ERROR 0x00200000 587 #define RBD_FLAG_RUNT 0x00100000 588 #define RBD_FLAG_CRC_ERR 0x00080000 589 #define RBD_FLAG_PROTOCOL 0x00060000 590 #define RBD_FLAG_IP 0x00060000 591 #define RBD_FLAG_UDP 0x00040000 592 #define RBD_FLAG_TCP 0x00020000 593 #define RBD_FLAG_NONE_IP 0x00000000 594 #define RBD_IP_CKSUM_ERR 0x00010000 595 #define RBD_UDP_CKSUM_ERR 0x00008000 596 #define RBD_TCP_CKSUM_ERR 0x00004000 597 #define RBD_CKSUM_ERR 0x0001c000 598 #define RBD_FLAGS_MASK 0xffffc000 599 #define RBD_LEN_MASK 0x00003fff 600 601 #define RBD_VLAN_PKT 0x00010000 602 #define RBD_VLAN_TAG 0x0000ffff 603 604 605 #define SBD_FLAG_LARGE_SEND 0x08000000 606 #define SBD_FLAG_SEG_MAX 0x07ff0000 607 #define SBD_FLAG_IP_CKSUM 0x00040000 608 #define SBD_FLAG_UDP_CKSUM 0x00020000 609 #define SBD_FLAG_TCP_CKSUM 0x00010000 610 #define SBD_FLAG_TCP_UDP_CKSUM 0x00030000 611 #define SBD_LEN_MASK 0x0000ffff 612 613 #define SBD_VLAN_PKT 0x00020000 614 #define SBD_VLAN_TAG 0x0000ffff 615 616 #define SBD_FLAG_TX_PKT (BD_FLAG_HW_OWN | BD_FLAG_PKT_START | \ 617 BD_FLAG_PKT_END) 618 619 /* 620 * Chip VLAN TCI format 621 * bit0-3: VIDH The high 4 bits of a 12-bit VLAN ID 622 * bit4: CFI Canonical format indicator 623 * bit5-7: 3-bit 8-level priority 624 * bit8-15: The low 8 bits of a 12-bit VLAN ID 625 */ 626 #define TCI_OS2CHIP(tci) (((tci & 0xff) << 8) | (tci >> 8)) 627 #define TCI_CHIP2OS(tci) (((tci & 0xff00) >> 8) | (tci << 8)) 628 629 /* 630 * Hardware-defined Status Block 631 */ 632 typedef struct rge_hw_stats { 633 uint64_t xmt_ok; 634 uint64_t rcv_ok; 635 uint64_t xmt_err; 636 uint32_t rcv_err; 637 uint16_t in_discards; 638 uint16_t frame_err; 639 uint32_t xmt_1col; 640 uint32_t xmt_mcol; 641 uint64_t unicast_rcv; 642 uint64_t brdcst_rcv; 643 uint32_t multi_rcv; 644 uint16_t xmt_abt; 645 uint16_t xmt_undrn; 646 } rge_hw_stats_t; /* total 64 bytes */ 647 648 #ifdef __cplusplus 649 } 650 #endif 651 652 #endif /* _RGE_HW_H */ 653