1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #ifndef _SYS_PCIEB_H 26 #define _SYS_PCIEB_H 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 #if defined(DEBUG) 33 #define PCIEB_DEBUG pcieb_dbg 34 extern void pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...); 35 #else /* DEBUG */ 36 #define PCIEB_DEBUG 0 && 37 #endif /* DEBUG */ 38 39 typedef enum { /* same sequence as pcieb_debug_sym[] */ 40 /* 0 */ DBG_ATTACH, 41 /* 1 */ DBG_PWR, 42 /* 2 */ DBG_INTR 43 } pcieb_debug_bit_t; 44 45 /* 46 * Intel specific register offsets with bit definitions. 47 */ 48 #define PCIEB_PX_CAPABILITY_ID 0x44 49 #define PCIEB_BRIDGE_CONF 0x40 50 51 /* 52 * PCI/PCI-E Configuration register specific values. 53 */ 54 #define PX_PMODE 0x4000 /* PCI/PCIX Mode */ 55 #define PX_PFREQ_66 0x200 /* PCI clock frequency */ 56 #define PX_PFREQ_100 0x400 57 #define PX_PFREQ_133 0x600 58 #define PX_PMRE 0x80 /* Peer memory read enable */ 59 60 /* 61 * Downstream delayed transaction resource partitioning. 62 */ 63 #define PX_ODTP 0x40 /* Max. of two entries PX and PCI */ 64 65 /* 66 * Maximum upstream delayed transaction. 67 */ 68 #define PX_MDT_44 0x00 69 #define PX_MDT_11 0x01 70 #define PX_MDT_22 0x10 71 72 #define NUM_LOGICAL_SLOTS 32 73 #define PCIEB_RANGE_LEN 2 74 #define PCIEB_32BIT_IO 1 75 #define PCIEB_32bit_MEM 1 76 #define PCIEB_MEMGRAIN 0x100000 77 #define PCIEB_IOGRAIN 0x1000 78 79 #define PCIEB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8)) 80 #define PCIEB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo)) 81 #define PCIEB_32bit_MEMADDR(addr) (PCIEB_LADDR(0, ((uint16_t)(addr) & 0xFFF0))) 82 83 /* 84 * Intel 41210 PCIe-to-PCI Bridge has two Functions F0 and F2: 85 * VID: 0x8086 86 * DID: F0 = 0x340, F2 = 0x341 87 */ 88 #define PCIEB_IS_41210_F0(bus_dev_ven_id) (bus_dev_ven_id == 0x3408086) 89 #define PCIEB_IS_41210_F2(bus_dev_ven_id) (bus_dev_ven_id == 0x3418086) 90 #define PCIEB_IS_41210_BRIDGE(bus_dev_ven_id) \ 91 (PCIEB_IS_41210_F0(bus_dev_ven_id) || PCIEB_IS_41210_F2(bus_dev_ven_id)) 92 93 typedef struct { 94 dev_info_t *pcieb_dip; 95 96 /* Interrupt support */ 97 ddi_intr_handle_t *pcieb_htable; /* Intr Handlers */ 98 int pcieb_htable_size; /* htable size */ 99 int pcieb_intr_count; /* Num of Intr */ 100 uint_t pcieb_intr_priority; /* Intr Priority */ 101 int pcieb_intr_type; /* (MSI | FIXED) */ 102 int pcieb_isr_tab[4]; /* MSI source offset */ 103 104 int pcieb_init_flags; 105 kmutex_t pcieb_mutex; /* Soft state mutex */ 106 kmutex_t pcieb_intr_mutex; /* Intr handler mutex */ 107 kmutex_t pcieb_err_mutex; /* Error mutex */ 108 kmutex_t pcieb_peek_poke_mutex; /* Peekpoke mutex */ 109 110 /* FMA */ 111 boolean_t pcieb_no_aer_msi; 112 ddi_iblock_cookie_t pcieb_fm_ibc; 113 } pcieb_devstate_t; 114 115 /* 116 * soft state pointer 117 */ 118 extern void *pcieb_state; 119 120 /* soft state flags */ 121 #define PCIEB_SOFT_STATE_CLOSED 0x00 122 #define PCIEB_SOFT_STATE_OPEN 0x01 123 #define PCIEB_SOFT_STATE_OPEN_EXCL 0x02 124 125 /* init flags */ 126 #define PCIEB_INIT_MUTEX 0x01 127 #define PCIEB_INIT_HTABLE 0x02 128 #define PCIEB_INIT_ALLOC 0x04 129 #define PCIEB_INIT_HANDLER 0x08 130 #define PCIEB_INIT_ENABLE 0x10 131 #define PCIEB_INIT_BLOCK 0x20 132 #define PCIEB_INIT_FM 0x40 133 134 #define PCIEB_INTR_SRC_UNKNOWN 0x0 /* must be 0 */ 135 #define PCIEB_INTR_SRC_HP 0x1 136 #define PCIEB_INTR_SRC_PME 0x2 137 #define PCIEB_INTR_SRC_AER 0x4 138 139 /* 140 * Need to put vendor ids in a common file and not platform specific files 141 * as is done today. Until then putting this vendor id define here. 142 */ 143 #define NVIDIA_VENDOR_ID 0x10de /* Nvidia Vendor Id */ 144 145 #ifdef PCIEB_BCM 146 147 /* Workaround for address space limitation in Broadcom 5714/5715 */ 148 #define PCIEB_ADDR_LIMIT_LO 0ull 149 #define PCIEB_ADDR_LIMIT_HI ((1ull << 40) - 1) 150 151 #endif /* PCIEB_BCM */ 152 153 /* 154 * The following values are used to initialize the cache line size 155 * and latency timer registers for PCI, PCI-X and PCIe2PCI devices. 156 */ 157 #define PCIEB_CACHE_LINE_SIZE 0x10 /* 64 bytes in # of DWORDs */ 158 #define PCIEB_LATENCY_TIMER 0x40 /* 64 PCI cycles */ 159 160 extern void pcieb_set_pci_perf_parameters(dev_info_t *dip, 161 ddi_acc_handle_t config_handle); 162 extern void pcieb_plat_attach_workaround(dev_info_t *dip); 163 extern void pcieb_plat_intr_attach(pcieb_devstate_t *pcieb); 164 extern void pcieb_plat_initchild(dev_info_t *child); 165 extern void pcieb_plat_uninitchild(dev_info_t *child); 166 extern int pcieb_plat_ctlops(dev_info_t *rdip, ddi_ctl_enum_t ctlop, 167 void *arg); 168 extern int pcieb_plat_pcishpc_probe(dev_info_t *dip, 169 ddi_acc_handle_t config_handle); 170 extern int pcieb_plat_peekpoke(dev_info_t *dip, dev_info_t *rdip, 171 ddi_ctl_enum_t ctlop, void *arg, void *result); 172 extern void pcieb_set_prot_scan(dev_info_t *dip, ddi_acc_impl_t *hdlp); 173 extern int pcieb_plat_intr_ops(dev_info_t *dip, dev_info_t *rdip, 174 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 175 extern boolean_t pcieb_plat_msi_supported(dev_info_t *dip); 176 extern boolean_t pcieb_plat_pwr_disable(dev_info_t *dip); 177 178 #if defined(__i386) || defined(__amd64) 179 extern void pcieb_intel_error_workaround(dev_info_t *dip); 180 extern void pcieb_intel_serr_workaround(dev_info_t *dip, boolean_t mcheck); 181 extern void pcieb_intel_rber_workaround(dev_info_t *dip); 182 extern void pcieb_intel_sw_workaround(dev_info_t *dip); 183 extern void pcieb_intel_mps_workaround(dev_info_t *dip); 184 extern void pcieb_init_osc(dev_info_t *dip); 185 extern void pcieb_peekpoke_cb(dev_info_t *, ddi_fm_error_t *); 186 extern int pcishpc_init(dev_info_t *dip); 187 extern int pcishpc_uninit(dev_info_t *dip); 188 extern int pcishpc_intr(dev_info_t *dip); 189 #endif /* defined(__i386) || defined(__amd64) */ 190 191 #ifdef PX_PLX 192 extern void pcieb_attach_plx_workarounds(pcieb_devstate_t *pcieb); 193 extern int pcieb_init_plx_workarounds(pcieb_devstate_t *pcieb, 194 dev_info_t *child); 195 #endif /* PX_PLX */ 196 197 #ifdef __cplusplus 198 } 199 #endif 200 201 #endif /* _SYS_PCIEB_H */ 202