1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Common x86 and SPARC PCI-E to PCI bus bridge nexus driver 28 */ 29 30 #include <sys/sysmacros.h> 31 #include <sys/conf.h> 32 #include <sys/kmem.h> 33 #include <sys/debug.h> 34 #include <sys/modctl.h> 35 #include <sys/autoconf.h> 36 #include <sys/ddi_impldefs.h> 37 #include <sys/pci.h> 38 #include <sys/ddi.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/fm/util.h> 42 #include <sys/pci_cap.h> 43 #include <sys/pci_impl.h> 44 #include <sys/pcie_impl.h> 45 #include <sys/open.h> 46 #include <sys/stat.h> 47 #include <sys/file.h> 48 #include <sys/promif.h> /* prom_printf */ 49 #include <sys/disp.h> 50 #include <sys/pcie_pwr.h> 51 #include <sys/hotplug/pci/pcie_hp.h> 52 #include "pcieb.h" 53 #ifdef PX_PLX 54 #include <io/pciex/pcieb_plx.h> 55 #endif /* PX_PLX */ 56 57 /*LINTLIBRARY*/ 58 59 /* panic flag */ 60 int pcieb_die = PF_ERR_FATAL_FLAGS; 61 62 /* flag to turn on MSI support */ 63 int pcieb_enable_msi = 1; 64 65 #if defined(DEBUG) 66 uint_t pcieb_dbg_print = 0; 67 68 static char *pcieb_debug_sym [] = { /* same sequence as pcieb_debug_bit */ 69 /* 0 */ "attach", 70 /* 1 */ "pwr", 71 /* 2 */ "intr" 72 }; 73 #endif /* DEBUG */ 74 75 static int pcieb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, off_t, 76 off_t, caddr_t *); 77 static int pcieb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, void *, 78 void *); 79 static int pcieb_fm_init(pcieb_devstate_t *pcieb_p); 80 static void pcieb_fm_fini(pcieb_devstate_t *pcieb_p); 81 static int pcieb_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 82 ddi_iblock_cookie_t *ibc_p); 83 static int pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 84 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg, 85 ddi_dma_handle_t *handlep); 86 static int pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, 87 ddi_dma_handle_t handle, enum ddi_dma_ctlops cmd, off_t *offp, 88 size_t *lenp, caddr_t *objp, uint_t cache_flags); 89 static int pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, 90 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 91 92 static struct bus_ops pcieb_bus_ops = { 93 BUSO_REV, 94 pcieb_bus_map, 95 0, 96 0, 97 0, 98 i_ddi_map_fault, 99 ddi_dma_map, 100 pcieb_dma_allochdl, 101 ddi_dma_freehdl, 102 ddi_dma_bindhdl, 103 ddi_dma_unbindhdl, 104 ddi_dma_flush, 105 ddi_dma_win, 106 pcieb_dma_mctl, 107 pcieb_ctlops, 108 ddi_bus_prop_op, 109 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 110 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 111 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 112 ndi_post_event, /* (*bus_post_event)(); */ 113 NULL, /* (*bus_intr_ctl)(); */ 114 NULL, /* (*bus_config)(); */ 115 NULL, /* (*bus_unconfig)(); */ 116 pcieb_fm_init_child, /* (*bus_fm_init)(); */ 117 NULL, /* (*bus_fm_fini)(); */ 118 i_ndi_busop_access_enter, /* (*bus_fm_access_enter)(); */ 119 i_ndi_busop_access_exit, /* (*bus_fm_access_exit)(); */ 120 pcie_bus_power, /* (*bus_power)(); */ 121 pcieb_intr_ops, /* (*bus_intr_op)(); */ 122 pcie_hp_common_ops /* (*bus_hp_op)(); */ 123 }; 124 125 static int pcieb_open(dev_t *, int, int, cred_t *); 126 static int pcieb_close(dev_t, int, int, cred_t *); 127 static int pcieb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 128 static int pcieb_info(dev_info_t *, ddi_info_cmd_t, void *, void **); 129 static uint_t pcieb_intr_handler(caddr_t arg1, caddr_t arg2); 130 131 /* PM related functions */ 132 static int pcieb_pwr_setup(dev_info_t *dip); 133 static int pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p); 134 static void pcieb_pwr_teardown(dev_info_t *dip); 135 static int pcieb_pwr_disable(dev_info_t *dip); 136 137 /* Hotplug related functions */ 138 static void pcieb_id_props(pcieb_devstate_t *pcieb); 139 140 /* 141 * soft state pointer 142 */ 143 void *pcieb_state; 144 145 static struct cb_ops pcieb_cb_ops = { 146 pcieb_open, /* open */ 147 pcieb_close, /* close */ 148 nodev, /* strategy */ 149 nodev, /* print */ 150 nodev, /* dump */ 151 nodev, /* read */ 152 nodev, /* write */ 153 pcieb_ioctl, /* ioctl */ 154 nodev, /* devmap */ 155 nodev, /* mmap */ 156 nodev, /* segmap */ 157 nochpoll, /* poll */ 158 pcie_prop_op, /* cb_prop_op */ 159 NULL, /* streamtab */ 160 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 161 CB_REV, /* rev */ 162 nodev, /* int (*cb_aread)() */ 163 nodev /* int (*cb_awrite)() */ 164 }; 165 166 static int pcieb_probe(dev_info_t *); 167 static int pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 168 static int pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 169 170 static struct dev_ops pcieb_ops = { 171 DEVO_REV, /* devo_rev */ 172 0, /* refcnt */ 173 pcieb_info, /* info */ 174 nulldev, /* identify */ 175 pcieb_probe, /* probe */ 176 pcieb_attach, /* attach */ 177 pcieb_detach, /* detach */ 178 nulldev, /* reset */ 179 &pcieb_cb_ops, /* driver operations */ 180 &pcieb_bus_ops, /* bus operations */ 181 pcie_power, /* power */ 182 ddi_quiesce_not_needed, /* quiesce */ 183 }; 184 185 /* 186 * Module linkage information for the kernel. 187 */ 188 189 static struct modldrv modldrv = { 190 &mod_driverops, /* Type of module */ 191 "PCIe bridge/switch driver", 192 &pcieb_ops, /* driver ops */ 193 }; 194 195 static struct modlinkage modlinkage = { 196 MODREV_1, 197 (void *)&modldrv, 198 NULL 199 }; 200 201 /* 202 * forward function declarations: 203 */ 204 static void pcieb_uninitchild(dev_info_t *); 205 static int pcieb_initchild(dev_info_t *child); 206 static void pcieb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t); 207 static boolean_t pcieb_is_pcie_device_type(dev_info_t *dip); 208 209 /* interrupt related declarations */ 210 static int pcieb_msi_supported(dev_info_t *); 211 static int pcieb_intr_attach(pcieb_devstate_t *pcieb); 212 static int pcieb_intr_init(pcieb_devstate_t *pcieb_p, int intr_type); 213 static void pcieb_intr_fini(pcieb_devstate_t *pcieb_p); 214 215 int 216 _init(void) 217 { 218 int e; 219 220 if ((e = ddi_soft_state_init(&pcieb_state, sizeof (pcieb_devstate_t), 221 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 222 ddi_soft_state_fini(&pcieb_state); 223 return (e); 224 } 225 226 int 227 _fini(void) 228 { 229 int e; 230 231 if ((e = mod_remove(&modlinkage)) == 0) { 232 ddi_soft_state_fini(&pcieb_state); 233 } 234 return (e); 235 } 236 237 int 238 _info(struct modinfo *modinfop) 239 { 240 return (mod_info(&modlinkage, modinfop)); 241 } 242 243 /* ARGSUSED */ 244 static int 245 pcieb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 246 { 247 minor_t minor = getminor((dev_t)arg); 248 int instance = PCI_MINOR_NUM_TO_INSTANCE(minor); 249 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, instance); 250 int ret = DDI_SUCCESS; 251 252 switch (infocmd) { 253 case DDI_INFO_DEVT2INSTANCE: 254 *result = (void *)(intptr_t)instance; 255 break; 256 case DDI_INFO_DEVT2DEVINFO: 257 if (pcieb == NULL) { 258 ret = DDI_FAILURE; 259 break; 260 } 261 262 *result = (void *)pcieb->pcieb_dip; 263 break; 264 default: 265 ret = DDI_FAILURE; 266 break; 267 } 268 269 return (ret); 270 } 271 272 273 /*ARGSUSED*/ 274 static int 275 pcieb_probe(dev_info_t *devi) 276 { 277 return (DDI_PROBE_SUCCESS); 278 } 279 280 static int 281 pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 282 { 283 int instance; 284 char device_type[8]; 285 pcieb_devstate_t *pcieb; 286 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(devi); 287 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 288 289 switch (cmd) { 290 case DDI_RESUME: 291 (void) pcie_pwr_resume(devi); 292 return (DDI_SUCCESS); 293 294 default: 295 return (DDI_FAILURE); 296 297 case DDI_ATTACH: 298 break; 299 } 300 301 if (!(PCIE_IS_BDG(bus_p))) { 302 PCIEB_DEBUG(DBG_ATTACH, devi, "This is not a switch or" 303 " bridge\n"); 304 return (DDI_FAILURE); 305 } 306 307 /* 308 * If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config 309 * Space (PCIe Capability Link Control Register) is set, 310 * then do not bind the driver. 311 */ 312 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & PCIE_LINKCTL_LINK_DISABLE) 313 return (DDI_FAILURE); 314 315 /* 316 * Allocate and get soft state structure. 317 */ 318 instance = ddi_get_instance(devi); 319 if (ddi_soft_state_zalloc(pcieb_state, instance) != DDI_SUCCESS) 320 return (DDI_FAILURE); 321 pcieb = ddi_get_soft_state(pcieb_state, instance); 322 pcieb->pcieb_dip = devi; 323 324 if ((pcieb_fm_init(pcieb)) != DDI_SUCCESS) { 325 PCIEB_DEBUG(DBG_ATTACH, devi, "Failed in pcieb_fm_init\n"); 326 goto fail; 327 } 328 pcieb->pcieb_init_flags |= PCIEB_INIT_FM; 329 330 mutex_init(&pcieb->pcieb_mutex, NULL, MUTEX_DRIVER, NULL); 331 mutex_init(&pcieb->pcieb_err_mutex, NULL, MUTEX_DRIVER, 332 (void *)pcieb->pcieb_fm_ibc); 333 mutex_init(&pcieb->pcieb_peek_poke_mutex, NULL, MUTEX_DRIVER, 334 (void *)pcieb->pcieb_fm_ibc); 335 336 /* create special properties for device identification */ 337 pcieb_id_props(pcieb); 338 339 /* 340 * Power management setup. This also makes sure that switch/bridge 341 * is at D0 during attach. 342 */ 343 if (pwr_common_setup(devi) != DDI_SUCCESS) { 344 PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n"); 345 goto fail; 346 } 347 348 if (pcieb_pwr_setup(devi) != DDI_SUCCESS) { 349 PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n"); 350 goto fail; 351 } 352 353 /* 354 * Make sure the "device_type" property exists. 355 */ 356 if (pcieb_is_pcie_device_type(devi)) 357 (void) strcpy(device_type, "pciex"); 358 else 359 (void) strcpy(device_type, "pci"); 360 361 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 362 "device_type", device_type); 363 364 /* 365 * Check whether the "ranges" property is present. 366 * Otherwise create the ranges property by reading 367 * the configuration registers 368 */ 369 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS, 370 "ranges") == 0) { 371 pcieb_create_ranges_prop(devi, config_handle); 372 } 373 374 if (PCIE_IS_PCI_BDG(bus_p)) 375 pcieb_set_pci_perf_parameters(devi, config_handle); 376 377 #ifdef PX_PLX 378 pcieb_attach_plx_workarounds(pcieb); 379 #endif /* PX_PLX */ 380 381 if (pcie_init(devi, NULL) != DDI_SUCCESS) 382 goto fail; 383 384 /* 385 * Initialize interrupt handlers. Ignore return value. 386 */ 387 (void) pcieb_intr_attach(pcieb); 388 389 /* Do any platform specific workarounds needed at this time */ 390 pcieb_plat_attach_workaround(devi); 391 392 /* 393 * If this is a root port, determine and set the max payload size. 394 * Since this will involve scanning the fabric, all error enabling 395 * and sw workarounds should be in place before doing this. 396 */ 397 if (PCIE_IS_RP(bus_p)) 398 pcie_init_root_port_mps(devi); 399 400 ddi_report_dev(devi); 401 return (DDI_SUCCESS); 402 403 fail: 404 (void) pcieb_detach(devi, DDI_DETACH); 405 return (DDI_FAILURE); 406 } 407 408 static int 409 pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 410 { 411 pcieb_devstate_t *pcieb; 412 int error = DDI_SUCCESS; 413 414 switch (cmd) { 415 case DDI_SUSPEND: 416 error = pcie_pwr_suspend(devi); 417 return (error); 418 419 case DDI_DETACH: 420 break; 421 422 default: 423 return (DDI_FAILURE); 424 } 425 426 pcieb = ddi_get_soft_state(pcieb_state, ddi_get_instance(devi)); 427 428 /* remove interrupt handlers */ 429 pcieb_intr_fini(pcieb); 430 431 /* uninitialize inband PCI-E HPC if present */ 432 (void) pcie_uninit(devi); 433 434 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 435 436 (void) ndi_prop_remove(DDI_DEV_T_NONE, pcieb->pcieb_dip, 437 "pcie_ce_mask"); 438 439 if (pcieb->pcieb_init_flags & PCIEB_INIT_FM) 440 pcieb_fm_fini(pcieb); 441 442 pcieb_pwr_teardown(devi); 443 pwr_common_teardown(devi); 444 445 mutex_destroy(&pcieb->pcieb_peek_poke_mutex); 446 mutex_destroy(&pcieb->pcieb_err_mutex); 447 mutex_destroy(&pcieb->pcieb_mutex); 448 449 /* 450 * And finally free the per-pci soft state. 451 */ 452 ddi_soft_state_free(pcieb_state, ddi_get_instance(devi)); 453 454 return (DDI_SUCCESS); 455 } 456 457 static int 458 pcieb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 459 off_t offset, off_t len, caddr_t *vaddrp) 460 { 461 dev_info_t *pdip; 462 463 if (PCIE_IS_RP(PCIE_DIP2BUS(dip))) { 464 ddi_acc_impl_t *hdlp = 465 (ddi_acc_impl_t *)(mp->map_handlep)->ah_platform_private; 466 467 pcieb_set_prot_scan(dip, hdlp); 468 } 469 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 470 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip, rdip, mp, 471 offset, len, vaddrp)); 472 } 473 474 static int 475 pcieb_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop, 476 void *arg, void *result) 477 { 478 pci_regspec_t *drv_regp; 479 int reglen; 480 int rn; 481 int totreg; 482 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, 483 ddi_get_instance(dip)); 484 struct detachspec *ds; 485 struct attachspec *as; 486 487 switch (ctlop) { 488 case DDI_CTLOPS_REPORTDEV: 489 if (rdip == (dev_info_t *)0) 490 return (DDI_FAILURE); 491 cmn_err(CE_CONT, "?PCIE-device: %s@%s, %s%d\n", 492 ddi_node_name(rdip), ddi_get_name_addr(rdip), 493 ddi_driver_name(rdip), 494 ddi_get_instance(rdip)); 495 return (DDI_SUCCESS); 496 497 case DDI_CTLOPS_INITCHILD: 498 return (pcieb_initchild((dev_info_t *)arg)); 499 500 case DDI_CTLOPS_UNINITCHILD: 501 pcieb_uninitchild((dev_info_t *)arg); 502 return (DDI_SUCCESS); 503 504 case DDI_CTLOPS_SIDDEV: 505 return (DDI_SUCCESS); 506 507 case DDI_CTLOPS_REGSIZE: 508 case DDI_CTLOPS_NREGS: 509 if (rdip == (dev_info_t *)0) 510 return (DDI_FAILURE); 511 break; 512 513 case DDI_CTLOPS_PEEK: 514 case DDI_CTLOPS_POKE: 515 return (pcieb_plat_peekpoke(dip, rdip, ctlop, arg, result)); 516 case DDI_CTLOPS_ATTACH: 517 if (!pcie_is_child(dip, rdip)) 518 return (DDI_SUCCESS); 519 520 as = (struct attachspec *)arg; 521 switch (as->when) { 522 case DDI_PRE: 523 if (as->cmd == DDI_RESUME) { 524 pcie_clear_errors(rdip); 525 if (pcieb_plat_ctlops(rdip, ctlop, arg) != 526 DDI_SUCCESS) 527 return (DDI_FAILURE); 528 } 529 530 if (as->cmd == DDI_ATTACH) 531 return (pcie_pm_hold(dip)); 532 533 return (DDI_SUCCESS); 534 535 case DDI_POST: 536 if (as->cmd == DDI_ATTACH && 537 as->result != DDI_SUCCESS) { 538 /* 539 * Attach failed for the child device. The child 540 * driver may have made PM calls before the 541 * attach failed. pcie_pm_remove_child() should 542 * cleanup PM state and holds (if any) 543 * associated with the child device. 544 */ 545 return (pcie_pm_remove_child(dip, rdip)); 546 } 547 548 if (as->result == DDI_SUCCESS) { 549 pf_init(rdip, (void *)pcieb->pcieb_fm_ibc, 550 as->cmd); 551 552 (void) pcieb_plat_ctlops(rdip, ctlop, arg); 553 } 554 555 /* 556 * For empty hotplug-capable slots, we should explicitly 557 * disable the errors, so that we won't panic upon 558 * unsupported hotplug messages. 559 */ 560 if ((!ddi_prop_exists(DDI_DEV_T_ANY, rdip, 561 DDI_PROP_DONTPASS, "hotplug-capable")) || 562 ddi_get_child(rdip)) { 563 (void) pcie_postattach_child(rdip); 564 return (DDI_SUCCESS); 565 } 566 567 pcie_disable_errors(rdip); 568 569 return (DDI_SUCCESS); 570 default: 571 break; 572 } 573 return (DDI_SUCCESS); 574 575 case DDI_CTLOPS_DETACH: 576 if (!pcie_is_child(dip, rdip)) 577 return (DDI_SUCCESS); 578 579 ds = (struct detachspec *)arg; 580 switch (ds->when) { 581 case DDI_PRE: 582 pf_fini(rdip, ds->cmd); 583 return (DDI_SUCCESS); 584 585 case DDI_POST: 586 if (pcieb_plat_ctlops(rdip, ctlop, arg) != DDI_SUCCESS) 587 return (DDI_FAILURE); 588 if (ds->cmd == DDI_DETACH && 589 ds->result == DDI_SUCCESS) { 590 return (pcie_pm_remove_child(dip, rdip)); 591 } 592 return (DDI_SUCCESS); 593 default: 594 break; 595 } 596 return (DDI_SUCCESS); 597 default: 598 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 599 } 600 601 *(int *)result = 0; 602 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 603 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", (caddr_t)&drv_regp, 604 ®len) != DDI_SUCCESS) 605 return (DDI_FAILURE); 606 607 totreg = reglen / sizeof (pci_regspec_t); 608 if (ctlop == DDI_CTLOPS_NREGS) 609 *(int *)result = totreg; 610 else if (ctlop == DDI_CTLOPS_REGSIZE) { 611 rn = *(int *)arg; 612 if (rn >= totreg) { 613 kmem_free(drv_regp, reglen); 614 return (DDI_FAILURE); 615 } 616 617 *(off_t *)result = drv_regp[rn].pci_size_low | 618 ((uint64_t)drv_regp[rn].pci_size_hi << 32); 619 } 620 621 kmem_free(drv_regp, reglen); 622 return (DDI_SUCCESS); 623 } 624 625 /* 626 * name_child 627 * 628 * This function is called from init_child to name a node. It is 629 * also passed as a callback for node merging functions. 630 * 631 * return value: DDI_SUCCESS, DDI_FAILURE 632 */ 633 static int 634 pcieb_name_child(dev_info_t *child, char *name, int namelen) 635 { 636 pci_regspec_t *pci_rp; 637 uint_t device, func; 638 char **unit_addr; 639 uint_t n; 640 641 /* 642 * For .conf nodes, use unit-address property as name 643 */ 644 if (ndi_dev_is_persistent_node(child) == 0) { 645 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 646 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 647 DDI_PROP_SUCCESS) { 648 cmn_err(CE_WARN, 649 "cannot find unit-address in %s.conf", 650 ddi_driver_name(child)); 651 return (DDI_FAILURE); 652 } 653 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 654 cmn_err(CE_WARN, "unit-address property in %s.conf" 655 " not well-formed", ddi_driver_name(child)); 656 ddi_prop_free(unit_addr); 657 return (DDI_FAILURE); 658 } 659 (void) snprintf(name, namelen, "%s", *unit_addr); 660 ddi_prop_free(unit_addr); 661 return (DDI_SUCCESS); 662 } 663 664 /* 665 * Get the address portion of the node name based on 666 * the function and device number. 667 */ 668 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 669 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 670 return (DDI_FAILURE); 671 } 672 673 /* copy the device identifications */ 674 device = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 675 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 676 677 if (pcie_ari_is_enabled(ddi_get_parent(child)) 678 == PCIE_ARI_FORW_ENABLED) { 679 func = (device << 3) | func; 680 device = 0; 681 } 682 683 if (func != 0) 684 (void) snprintf(name, namelen, "%x,%x", device, func); 685 else 686 (void) snprintf(name, namelen, "%x", device); 687 688 ddi_prop_free(pci_rp); 689 return (DDI_SUCCESS); 690 } 691 692 static int 693 pcieb_initchild(dev_info_t *child) 694 { 695 char name[MAXNAMELEN]; 696 int result = DDI_FAILURE; 697 pcieb_devstate_t *pcieb = 698 (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 699 ddi_get_instance(ddi_get_parent(child))); 700 701 /* 702 * Name the child 703 */ 704 if (pcieb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) { 705 result = DDI_FAILURE; 706 goto done; 707 } 708 ddi_set_name_addr(child, name); 709 710 /* 711 * Pseudo nodes indicate a prototype node with per-instance 712 * properties to be merged into the real h/w device node. 713 * The interpretation of the unit-address is DD[,F] 714 * where DD is the device id and F is the function. 715 */ 716 if (ndi_dev_is_persistent_node(child) == 0) { 717 extern int pci_allow_pseudo_children; 718 719 /* 720 * Try to merge the properties from this prototype 721 * node into real h/w nodes. 722 */ 723 if (ndi_merge_node(child, pcieb_name_child) != DDI_SUCCESS) { 724 /* 725 * Merged ok - return failure to remove the node. 726 */ 727 ddi_set_name_addr(child, NULL); 728 result = DDI_FAILURE; 729 goto done; 730 } 731 732 /* workaround for ddivs to run under PCI-E */ 733 if (pci_allow_pseudo_children) { 734 result = DDI_SUCCESS; 735 goto done; 736 } 737 738 /* 739 * The child was not merged into a h/w node, 740 * but there's not much we can do with it other 741 * than return failure to cause the node to be removed. 742 */ 743 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 744 ddi_driver_name(child), ddi_get_name_addr(child), 745 ddi_driver_name(child)); 746 ddi_set_name_addr(child, NULL); 747 result = DDI_NOT_WELL_FORMED; 748 goto done; 749 } 750 751 /* platform specific initchild */ 752 pcieb_plat_initchild(child); 753 754 if (pcie_pm_hold(pcieb->pcieb_dip) != DDI_SUCCESS) { 755 PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip, 756 "INITCHILD: px_pm_hold failed\n"); 757 result = DDI_FAILURE; 758 goto done; 759 } 760 /* Any return from here must call pcie_pm_release */ 761 762 /* 763 * If configuration registers were previously saved by 764 * child (before it entered D3), then let the child do the 765 * restore to set up the config regs as it'll first need to 766 * power the device out of D3. 767 */ 768 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 769 "config-regs-saved-by-child") == 1) { 770 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 771 "INITCHILD: config regs to be restored by child" 772 " for %s@%s\n", ddi_node_name(child), 773 ddi_get_name_addr(child)); 774 775 result = DDI_SUCCESS; 776 goto cleanup; 777 } 778 779 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 780 "INITCHILD: config regs setup for %s@%s\n", 781 ddi_node_name(child), ddi_get_name_addr(child)); 782 783 if (pcie_initchild(child) != DDI_SUCCESS) { 784 result = DDI_FAILURE; 785 goto cleanup; 786 } 787 788 #ifdef PX_PLX 789 if (pcieb_init_plx_workarounds(pcieb, child) == DDI_FAILURE) { 790 result = DDI_FAILURE; 791 goto cleanup; 792 } 793 #endif /* PX_PLX */ 794 795 result = DDI_SUCCESS; 796 cleanup: 797 pcie_pm_release(pcieb->pcieb_dip); 798 done: 799 return (result); 800 } 801 802 static void 803 pcieb_uninitchild(dev_info_t *dip) 804 { 805 806 pcie_uninitchild(dip); 807 808 pcieb_plat_uninitchild(dip); 809 810 ddi_set_name_addr(dip, NULL); 811 812 /* 813 * Strip the node to properly convert it back to prototype form 814 */ 815 ddi_remove_minor_node(dip, NULL); 816 817 ddi_prop_remove_all(dip); 818 } 819 820 static boolean_t 821 pcieb_is_pcie_device_type(dev_info_t *dip) 822 { 823 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 824 825 if (PCIE_IS_SW(bus_p) || PCIE_IS_RP(bus_p) || PCIE_IS_PCI2PCIE(bus_p)) 826 return (B_TRUE); 827 828 return (B_FALSE); 829 } 830 831 static int 832 pcieb_intr_attach(pcieb_devstate_t *pcieb) 833 { 834 int intr_types; 835 dev_info_t *dip = pcieb->pcieb_dip; 836 837 /* Allow platform specific code to do any initialization first */ 838 pcieb_plat_intr_attach(pcieb); 839 840 /* 841 * Initialize interrupt handlers. 842 * If both MSI and FIXED are supported, try to attach MSI first. 843 * If MSI fails for any reason, then try FIXED, but only allow one 844 * type to be attached. 845 */ 846 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 847 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_supported_types" 848 " failed\n"); 849 goto FAIL; 850 } 851 852 if ((intr_types & DDI_INTR_TYPE_MSI) && 853 (pcieb_msi_supported(dip) == DDI_SUCCESS)) { 854 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) 855 intr_types = DDI_INTR_TYPE_MSI; 856 else { 857 PCIEB_DEBUG(DBG_ATTACH, dip, "Unable to attach MSI" 858 " handler\n"); 859 } 860 } 861 862 if (intr_types != DDI_INTR_TYPE_MSI) { 863 /* 864 * MSIs are not supported or MSI initialization failed. For Root 865 * Ports mark this so error handling might try to fallback to 866 * some other mechanism if available (machinecheck etc.). 867 */ 868 if (PCIE_IS_RP(PCIE_DIP2UPBUS(dip))) 869 pcieb->pcieb_no_aer_msi = B_TRUE; 870 } 871 872 if (intr_types & DDI_INTR_TYPE_FIXED) { 873 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_FIXED) != 874 DDI_SUCCESS) { 875 PCIEB_DEBUG(DBG_ATTACH, dip, 876 "Unable to attach INTx handler\n"); 877 goto FAIL; 878 } 879 } 880 return (DDI_SUCCESS); 881 882 FAIL: 883 return (DDI_FAILURE); 884 } 885 886 /* 887 * This function initializes internally generated interrupts only. 888 * It does not affect any interrupts generated by downstream devices 889 * or the forwarding of them. 890 * 891 * Enable Device Specific Interrupts or Hotplug features here. 892 * Enabling features may change how many interrupts are requested 893 * by the device. If features are not enabled first, the 894 * device might not ask for any interrupts. 895 */ 896 897 static int 898 pcieb_intr_init(pcieb_devstate_t *pcieb, int intr_type) 899 { 900 dev_info_t *dip = pcieb->pcieb_dip; 901 int nintrs, request, count, x; 902 int intr_cap = 0; 903 int inum = 0; 904 int ret, hp_msi_off; 905 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 906 uint16_t vendorid = bus_p->bus_dev_ven_id & 0xFFFF; 907 boolean_t is_hp = B_FALSE; 908 boolean_t is_pme = B_FALSE; 909 910 PCIEB_DEBUG(DBG_ATTACH, dip, "pcieb_intr_init: Attaching %s handler\n", 911 (intr_type == DDI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 912 913 request = 0; 914 if (PCIE_IS_HOTPLUG_ENABLED(dip)) { 915 request++; 916 is_hp = B_TRUE; 917 } 918 919 /* 920 * Hotplug and PME share the same MSI vector. If hotplug is not 921 * supported check if MSI is needed for PME. 922 */ 923 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p) && 924 (vendorid == NVIDIA_VENDOR_ID)) { 925 is_pme = B_TRUE; 926 if (!is_hp) 927 request++; 928 } 929 930 /* 931 * Setup MSI if this device is a Rootport and has AER. Currently no 932 * SPARC Root Port supports fabric errors being reported through it. 933 */ 934 if (intr_type == DDI_INTR_TYPE_MSI) { 935 if (PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p)) 936 request++; 937 } 938 939 if (request == 0) 940 return (DDI_SUCCESS); 941 942 /* 943 * Get number of supported interrupts. 944 * 945 * Several Bridges/Switches will not have this property set, resulting 946 * in a FAILURE, if the device is not configured in a way that 947 * interrupts are needed. (eg. hotplugging) 948 */ 949 ret = ddi_intr_get_nintrs(dip, intr_type, &nintrs); 950 if ((ret != DDI_SUCCESS) || (nintrs == 0)) { 951 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_nintrs ret:%d" 952 " req:%d\n", ret, nintrs); 953 return (DDI_FAILURE); 954 } 955 956 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0x%x: ddi_intr_get_nintrs: nintrs %d", 957 " request %d\n", bus_p->bus_bdf, nintrs, request); 958 959 if (request > nintrs) 960 request = nintrs; 961 962 /* Allocate an array of interrupt handlers */ 963 pcieb->pcieb_htable_size = sizeof (ddi_intr_handle_t) * request; 964 pcieb->pcieb_htable = kmem_zalloc(pcieb->pcieb_htable_size, 965 KM_SLEEP); 966 pcieb->pcieb_init_flags |= PCIEB_INIT_HTABLE; 967 968 ret = ddi_intr_alloc(dip, pcieb->pcieb_htable, intr_type, inum, 969 request, &count, DDI_INTR_ALLOC_NORMAL); 970 if ((ret != DDI_SUCCESS) || (count == 0)) { 971 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_alloc() ret: %d ask: %d" 972 " actual: %d\n", ret, request, count); 973 goto FAIL; 974 } 975 pcieb->pcieb_init_flags |= PCIEB_INIT_ALLOC; 976 977 /* Save the actual number of interrupts allocated */ 978 pcieb->pcieb_intr_count = count; 979 if (count < request) { 980 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0%x: Requested Intr: %d" 981 " Received: %d\n", bus_p->bus_bdf, request, count); 982 } 983 984 /* 985 * NVidia (MCP55 and other) chipsets have a errata that if the number 986 * of requested MSI intrs is not allocated we have to fall back to INTx. 987 */ 988 if (intr_type == DDI_INTR_TYPE_MSI) { 989 if (PCIE_IS_RP(bus_p) && (vendorid == NVIDIA_VENDOR_ID)) { 990 if (request != count) 991 goto FAIL; 992 } 993 } 994 995 /* Get interrupt priority */ 996 ret = ddi_intr_get_pri(pcieb->pcieb_htable[0], 997 &pcieb->pcieb_intr_priority); 998 if (ret != DDI_SUCCESS) { 999 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_pri() ret: %d\n", 1000 ret); 1001 goto FAIL; 1002 } 1003 1004 if (pcieb->pcieb_intr_priority >= LOCK_LEVEL) { 1005 pcieb->pcieb_intr_priority = LOCK_LEVEL - 1; 1006 ret = ddi_intr_set_pri(pcieb->pcieb_htable[0], 1007 pcieb->pcieb_intr_priority); 1008 if (ret != DDI_SUCCESS) { 1009 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_set_pri() ret:" 1010 " %d\n", ret); 1011 1012 goto FAIL; 1013 } 1014 } 1015 1016 mutex_init(&pcieb->pcieb_intr_mutex, NULL, MUTEX_DRIVER, NULL); 1017 1018 pcieb->pcieb_init_flags |= PCIEB_INIT_MUTEX; 1019 1020 for (count = 0; count < pcieb->pcieb_intr_count; count++) { 1021 ret = ddi_intr_add_handler(pcieb->pcieb_htable[count], 1022 pcieb_intr_handler, (caddr_t)pcieb, 1023 (caddr_t)(uintptr_t)(inum + count)); 1024 1025 if (ret != DDI_SUCCESS) { 1026 PCIEB_DEBUG(DBG_ATTACH, dip, "Cannot add " 1027 "interrupt(%d)\n", ret); 1028 break; 1029 } 1030 } 1031 1032 /* If unsucessful, remove the added handlers */ 1033 if (ret != DDI_SUCCESS) { 1034 for (x = 0; x < count; x++) { 1035 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]); 1036 } 1037 goto FAIL; 1038 } 1039 1040 pcieb->pcieb_init_flags |= PCIEB_INIT_HANDLER; 1041 1042 (void) ddi_intr_get_cap(pcieb->pcieb_htable[0], &intr_cap); 1043 1044 /* 1045 * Get this intr lock because we are not quite ready to handle 1046 * interrupts immediately after enabling it. The MSI multi register 1047 * gets programmed in ddi_intr_enable after which we need to get the 1048 * MSI offsets for Hotplug/AER. 1049 */ 1050 mutex_enter(&pcieb->pcieb_intr_mutex); 1051 1052 if (intr_cap & DDI_INTR_FLAG_BLOCK) { 1053 (void) ddi_intr_block_enable(pcieb->pcieb_htable, 1054 pcieb->pcieb_intr_count); 1055 pcieb->pcieb_init_flags |= PCIEB_INIT_BLOCK; 1056 } else { 1057 for (count = 0; count < pcieb->pcieb_intr_count; count++) { 1058 (void) ddi_intr_enable(pcieb->pcieb_htable[count]); 1059 } 1060 } 1061 pcieb->pcieb_init_flags |= PCIEB_INIT_ENABLE; 1062 1063 /* Save the interrupt type */ 1064 pcieb->pcieb_intr_type = intr_type; 1065 1066 /* Get the MSI offset for hotplug/PME from the PCIe cap reg */ 1067 if (intr_type == DDI_INTR_TYPE_MSI) { 1068 hp_msi_off = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL, 1069 bus_p->bus_pcie_off, PCIE_PCIECAP) & 1070 PCIE_PCIECAP_INT_MSG_NUM; 1071 1072 if (hp_msi_off >= count) { 1073 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in PCIe " 1074 "cap > max allocated %d\n", hp_msi_off, count); 1075 mutex_exit(&pcieb->pcieb_intr_mutex); 1076 goto FAIL; 1077 } 1078 1079 if (is_hp) 1080 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_HP; 1081 1082 if (is_pme) 1083 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_PME; 1084 } else { 1085 /* INTx handles only Hotplug interrupts */ 1086 if (is_hp) 1087 pcieb->pcieb_isr_tab[0] |= PCIEB_INTR_SRC_HP; 1088 } 1089 1090 1091 /* 1092 * Get the MSI offset for errors from the AER Root Error status 1093 * register. 1094 */ 1095 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p)) { 1096 if (PCIE_HAS_AER(bus_p)) { 1097 int aer_msi_off; 1098 aer_msi_off = (PCI_XCAP_GET32(bus_p->bus_cfg_hdl, NULL, 1099 bus_p->bus_aer_off, PCIE_AER_RE_STS) >> 1100 PCIE_AER_RE_STS_MSG_NUM_SHIFT) & 1101 PCIE_AER_RE_STS_MSG_NUM_MASK; 1102 1103 if (aer_msi_off >= count) { 1104 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in" 1105 " AER cap > max allocated %d\n", 1106 aer_msi_off, count); 1107 mutex_exit(&pcieb->pcieb_intr_mutex); 1108 goto FAIL; 1109 } 1110 pcieb->pcieb_isr_tab[aer_msi_off] |= PCIEB_INTR_SRC_AER; 1111 } else { 1112 /* 1113 * This RP does not have AER. Fallback to the 1114 * SERR+Machinecheck approach if available. 1115 */ 1116 pcieb->pcieb_no_aer_msi = B_TRUE; 1117 } 1118 } 1119 1120 mutex_exit(&pcieb->pcieb_intr_mutex); 1121 return (DDI_SUCCESS); 1122 1123 FAIL: 1124 pcieb_intr_fini(pcieb); 1125 return (DDI_FAILURE); 1126 } 1127 1128 static void 1129 pcieb_intr_fini(pcieb_devstate_t *pcieb) 1130 { 1131 int x; 1132 int count = pcieb->pcieb_intr_count; 1133 int flags = pcieb->pcieb_init_flags; 1134 1135 if ((flags & PCIEB_INIT_ENABLE) && 1136 (flags & PCIEB_INIT_BLOCK)) { 1137 (void) ddi_intr_block_disable(pcieb->pcieb_htable, count); 1138 flags &= ~(PCIEB_INIT_ENABLE | 1139 PCIEB_INIT_BLOCK); 1140 } 1141 1142 if (flags & PCIEB_INIT_MUTEX) 1143 mutex_destroy(&pcieb->pcieb_intr_mutex); 1144 1145 for (x = 0; x < count; x++) { 1146 if (flags & PCIEB_INIT_ENABLE) 1147 (void) ddi_intr_disable(pcieb->pcieb_htable[x]); 1148 1149 if (flags & PCIEB_INIT_HANDLER) 1150 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]); 1151 1152 if (flags & PCIEB_INIT_ALLOC) 1153 (void) ddi_intr_free(pcieb->pcieb_htable[x]); 1154 } 1155 1156 flags &= ~(PCIEB_INIT_ENABLE | PCIEB_INIT_HANDLER | PCIEB_INIT_ALLOC | 1157 PCIEB_INIT_MUTEX); 1158 1159 if (flags & PCIEB_INIT_HTABLE) 1160 kmem_free(pcieb->pcieb_htable, pcieb->pcieb_htable_size); 1161 1162 flags &= ~PCIEB_INIT_HTABLE; 1163 1164 pcieb->pcieb_init_flags &= flags; 1165 } 1166 1167 /* 1168 * Checks if this device needs MSIs enabled or not. 1169 */ 1170 /*ARGSUSED*/ 1171 static int 1172 pcieb_msi_supported(dev_info_t *dip) 1173 { 1174 return ((pcieb_enable_msi && pcieb_plat_msi_supported(dip)) ? 1175 DDI_SUCCESS: DDI_FAILURE); 1176 } 1177 1178 /*ARGSUSED*/ 1179 static int 1180 pcieb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 1181 ddi_iblock_cookie_t *ibc) 1182 { 1183 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, 1184 ddi_get_instance(dip)); 1185 1186 ASSERT(ibc != NULL); 1187 *ibc = pcieb->pcieb_fm_ibc; 1188 1189 return (DEVI(dip)->devi_fmhdl->fh_cap | DDI_FM_ACCCHK_CAPABLE | 1190 DDI_FM_DMACHK_CAPABLE); 1191 } 1192 1193 static int 1194 pcieb_fm_init(pcieb_devstate_t *pcieb_p) 1195 { 1196 dev_info_t *dip = pcieb_p->pcieb_dip; 1197 int fm_cap = DDI_FM_EREPORT_CAPABLE; 1198 1199 /* 1200 * Request our capability level and get our parents capability 1201 * and ibc. 1202 */ 1203 ddi_fm_init(dip, &fm_cap, &pcieb_p->pcieb_fm_ibc); 1204 1205 return (DDI_SUCCESS); 1206 } 1207 1208 /* 1209 * Breakdown our FMA resources 1210 */ 1211 static void 1212 pcieb_fm_fini(pcieb_devstate_t *pcieb_p) 1213 { 1214 /* 1215 * Clean up allocated fm structures 1216 */ 1217 ddi_fm_fini(pcieb_p->pcieb_dip); 1218 } 1219 1220 static int 1221 pcieb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 1222 { 1223 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(*devp)); 1224 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst); 1225 int rv; 1226 1227 if (pcieb == NULL) 1228 return (ENXIO); 1229 1230 mutex_enter(&pcieb->pcieb_mutex); 1231 rv = pcie_open(pcieb->pcieb_dip, devp, flags, otyp, credp); 1232 mutex_exit(&pcieb->pcieb_mutex); 1233 1234 return (rv); 1235 } 1236 1237 static int 1238 pcieb_close(dev_t dev, int flags, int otyp, cred_t *credp) 1239 { 1240 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)); 1241 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst); 1242 int rv; 1243 1244 if (pcieb == NULL) 1245 return (ENXIO); 1246 1247 mutex_enter(&pcieb->pcieb_mutex); 1248 rv = pcie_close(pcieb->pcieb_dip, dev, flags, otyp, credp); 1249 mutex_exit(&pcieb->pcieb_mutex); 1250 1251 return (rv); 1252 } 1253 1254 static int 1255 pcieb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1256 int *rvalp) 1257 { 1258 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)); 1259 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst); 1260 int rv; 1261 1262 if (pcieb == NULL) 1263 return (ENXIO); 1264 1265 /* To handle devctl and hotplug related ioctls */ 1266 rv = pcie_ioctl(pcieb->pcieb_dip, dev, cmd, arg, mode, credp, rvalp); 1267 1268 return (rv); 1269 } 1270 1271 /* 1272 * Common interrupt handler for hotplug, PME and errors. 1273 */ 1274 static uint_t 1275 pcieb_intr_handler(caddr_t arg1, caddr_t arg2) 1276 { 1277 pcieb_devstate_t *pcieb_p = (pcieb_devstate_t *)arg1; 1278 dev_info_t *dip = pcieb_p->pcieb_dip; 1279 ddi_fm_error_t derr; 1280 int sts = 0; 1281 int ret = DDI_INTR_UNCLAIMED; 1282 int isrc; 1283 1284 if (!(pcieb_p->pcieb_init_flags & PCIEB_INIT_ENABLE)) 1285 goto FAIL; 1286 1287 mutex_enter(&pcieb_p->pcieb_intr_mutex); 1288 isrc = pcieb_p->pcieb_isr_tab[(int)(uintptr_t)arg2]; 1289 mutex_exit(&pcieb_p->pcieb_intr_mutex); 1290 1291 PCIEB_DEBUG(DBG_INTR, dip, "Received intr number %d\n", 1292 (int)(uintptr_t)arg2); 1293 1294 if (isrc == PCIEB_INTR_SRC_UNKNOWN) 1295 goto FAIL; 1296 1297 if (isrc & PCIEB_INTR_SRC_HP) 1298 ret = pcie_intr(dip); 1299 1300 if (isrc & PCIEB_INTR_SRC_PME) 1301 ret = DDI_INTR_CLAIMED; 1302 1303 /* AER Error */ 1304 if (isrc & PCIEB_INTR_SRC_AER) { 1305 /* 1306 * If MSI is shared with PME/hotplug then check Root Error 1307 * Status Reg before claiming it. For now it's ok since 1308 * we know we get 2 MSIs. 1309 */ 1310 ret = DDI_INTR_CLAIMED; 1311 bzero(&derr, sizeof (ddi_fm_error_t)); 1312 derr.fme_version = DDI_FME_VERSION; 1313 mutex_enter(&pcieb_p->pcieb_peek_poke_mutex); 1314 mutex_enter(&pcieb_p->pcieb_err_mutex); 1315 1316 if ((DEVI(dip)->devi_fmhdl->fh_cap) & DDI_FM_EREPORT_CAPABLE) 1317 sts = pf_scan_fabric(dip, &derr, NULL); 1318 1319 mutex_exit(&pcieb_p->pcieb_err_mutex); 1320 mutex_exit(&pcieb_p->pcieb_peek_poke_mutex); 1321 if (pcieb_die & sts) 1322 fm_panic("%s-%d: PCI(-X) Express Fatal Error. (0x%x)", 1323 ddi_driver_name(dip), ddi_get_instance(dip), sts); 1324 } 1325 FAIL: 1326 return (ret); 1327 } 1328 1329 /* 1330 * Some PCI-X to PCI-E bridges do not support full 64-bit addressing on the 1331 * PCI-X side of the bridge. We build a special version of this driver for 1332 * those bridges, which uses PCIEB_ADDR_LIMIT_LO and/or PCIEB_ADDR_LIMIT_HI 1333 * to define the range of values which the chip can handle. The code below 1334 * then clamps the DMA address range supplied by the driver, preventing the 1335 * PCI-E nexus driver from allocating any memory the bridge can't deal 1336 * with. 1337 */ 1338 static int 1339 pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 1340 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg, 1341 ddi_dma_handle_t *handlep) 1342 { 1343 int ret; 1344 #ifdef BCM_SW_WORKAROUNDS 1345 uint64_t lim; 1346 1347 /* 1348 * If the leaf device's limits are outside than what the Broadcom 1349 * bridge can handle, we need to clip the values passed up the chain. 1350 */ 1351 lim = attr_p->dma_attr_addr_lo; 1352 attr_p->dma_attr_addr_lo = MAX(lim, PCIEB_ADDR_LIMIT_LO); 1353 1354 lim = attr_p->dma_attr_addr_hi; 1355 attr_p->dma_attr_addr_hi = MIN(lim, PCIEB_ADDR_LIMIT_HI); 1356 1357 #endif /* BCM_SW_WORKAROUNDS */ 1358 1359 /* 1360 * This is a software workaround to fix the Broadcom 5714/5715 PCIe-PCI 1361 * bridge prefetch bug. Intercept the DMA alloc handle request and set 1362 * PX_DMAI_FLAGS_MAP_BUFZONE flag in the handle. If this flag is set, 1363 * the px nexus driver will allocate an extra page & make it valid one, 1364 * for any DVMA request that comes from any of the Broadcom bridge child 1365 * devices. 1366 */ 1367 if ((ret = ddi_dma_allochdl(dip, rdip, attr_p, waitfp, arg, 1368 handlep)) == DDI_SUCCESS) { 1369 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*handlep; 1370 #ifdef BCM_SW_WORKAROUNDS 1371 mp->dmai_inuse |= PX_DMAI_FLAGS_MAP_BUFZONE; 1372 #endif /* BCM_SW_WORKAROUNDS */ 1373 /* 1374 * For a given rdip, update mp->dmai_bdf with the bdf value 1375 * of pcieb's immediate child or secondary bus-id of the 1376 * PCIe2PCI bridge. 1377 */ 1378 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip); 1379 } 1380 1381 return (ret); 1382 } 1383 1384 /* 1385 * FDVMA feature is not supported for any child device of Broadcom 5714/5715 1386 * PCIe-PCI bridge due to prefetch bug. Return failure immediately, so that 1387 * these drivers will switch to regular DVMA path. 1388 */ 1389 /*ARGSUSED*/ 1390 static int 1391 pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 1392 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1393 uint_t cache_flags) 1394 { 1395 int ret; 1396 1397 #ifdef BCM_SW_WORKAROUNDS 1398 if (cmd == DDI_DMA_RESERVE) 1399 return (DDI_FAILURE); 1400 #endif /* BCM_SW_WORKAROUNDS */ 1401 1402 if (((ret = ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp, 1403 cache_flags)) == DDI_SUCCESS) && (cmd == DDI_DMA_RESERVE)) { 1404 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*objp; 1405 1406 /* 1407 * For a given rdip, update mp->dmai_bdf with the bdf value 1408 * of pcieb's immediate child or secondary bus-id of the 1409 * PCIe2PCI bridge. 1410 */ 1411 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip); 1412 } 1413 1414 return (ret); 1415 } 1416 1417 static int 1418 pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1419 ddi_intr_handle_impl_t *hdlp, void *result) 1420 { 1421 return (pcieb_plat_intr_ops(dip, rdip, intr_op, hdlp, result)); 1422 1423 } 1424 1425 /* 1426 * Power management related initialization specific to pcieb. 1427 * Called by pcieb_attach() 1428 */ 1429 static int 1430 pcieb_pwr_setup(dev_info_t *dip) 1431 { 1432 char *comp_array[5]; 1433 int i; 1434 ddi_acc_handle_t conf_hdl; 1435 uint16_t pmcap, cap_ptr; 1436 pcie_pwr_t *pwr_p; 1437 1438 /* Some platforms/devices may choose to disable PM */ 1439 if (pcieb_plat_pwr_disable(dip)) { 1440 (void) pcieb_pwr_disable(dip); 1441 return (DDI_SUCCESS); 1442 } 1443 1444 ASSERT(PCIE_PMINFO(dip)); 1445 pwr_p = PCIE_NEXUS_PMINFO(dip); 1446 ASSERT(pwr_p); 1447 1448 /* Code taken from pci_pci driver */ 1449 if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) { 1450 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup " 1451 "failed\n"); 1452 return (DDI_FAILURE); 1453 } 1454 conf_hdl = pwr_p->pwr_conf_hdl; 1455 1456 /* 1457 * Walk the capabilities searching for a PM entry. 1458 */ 1459 if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &cap_ptr)) == 1460 DDI_FAILURE) { 1461 PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. " 1462 " PCI PM data structure not found in config header\n"); 1463 pci_config_teardown(&conf_hdl); 1464 return (DDI_SUCCESS); 1465 } 1466 /* 1467 * Save offset to pmcsr for future references. 1468 */ 1469 pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR; 1470 pmcap = PCI_CAP_GET16(conf_hdl, NULL, cap_ptr, PCI_PMCAP); 1471 if (pmcap & PCI_PMCAP_D1) { 1472 PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n"); 1473 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1; 1474 } 1475 if (pmcap & PCI_PMCAP_D2) { 1476 PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n"); 1477 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2; 1478 } 1479 1480 i = 0; 1481 comp_array[i++] = "NAME=PCIe switch/bridge PM"; 1482 comp_array[i++] = "0=Power Off (D3)"; 1483 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2) 1484 comp_array[i++] = "1=D2"; 1485 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D1) 1486 comp_array[i++] = "2=D1"; 1487 comp_array[i++] = "3=Full Power D0"; 1488 1489 /* 1490 * Create pm-components property, if it does not exist already. 1491 */ 1492 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1493 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) { 1494 PCIEB_DEBUG(DBG_PWR, dip, "could not create pm-components " 1495 " prop\n"); 1496 pci_config_teardown(&conf_hdl); 1497 return (DDI_FAILURE); 1498 } 1499 return (pcieb_pwr_init_and_raise(dip, pwr_p)); 1500 } 1501 1502 /* 1503 * undo whatever is done in pcieb_pwr_setup. called by pcieb_detach() 1504 */ 1505 static void 1506 pcieb_pwr_teardown(dev_info_t *dip) 1507 { 1508 pcie_pwr_t *pwr_p; 1509 1510 if (!PCIE_PMINFO(dip) || !(pwr_p = PCIE_NEXUS_PMINFO(dip))) 1511 return; 1512 1513 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 1514 if (pwr_p->pwr_conf_hdl) 1515 pci_config_teardown(&pwr_p->pwr_conf_hdl); 1516 } 1517 1518 /* 1519 * Initializes the power level and raise the power to D0, if it is 1520 * not at D0. 1521 */ 1522 static int 1523 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p) 1524 { 1525 uint16_t pmcsr; 1526 int ret = DDI_SUCCESS; 1527 1528 /* 1529 * Intialize our power level from PMCSR. The common code initializes 1530 * this to UNKNOWN. There is no guarantee that we will be at full 1531 * power at attach. If we are not at D0, raise the power. 1532 */ 1533 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, pwr_p->pwr_pmcsr_offset); 1534 pmcsr &= PCI_PMCSR_STATE_MASK; 1535 switch (pmcsr) { 1536 case PCI_PMCSR_D0: 1537 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1538 break; 1539 1540 case PCI_PMCSR_D1: 1541 pwr_p->pwr_func_lvl = PM_LEVEL_D1; 1542 break; 1543 1544 case PCI_PMCSR_D2: 1545 pwr_p->pwr_func_lvl = PM_LEVEL_D2; 1546 break; 1547 1548 case PCI_PMCSR_D3HOT: 1549 pwr_p->pwr_func_lvl = PM_LEVEL_D3; 1550 break; 1551 1552 default: 1553 break; 1554 } 1555 1556 /* Raise the power to D0. */ 1557 if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 && 1558 ((ret = pm_raise_power(dip, 0, PM_LEVEL_D0)) != DDI_SUCCESS)) { 1559 /* 1560 * Read PMCSR again. If it is at D0, ignore the return 1561 * value from pm_raise_power. 1562 */ 1563 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, 1564 pwr_p->pwr_pmcsr_offset); 1565 if ((pmcsr & PCI_PMCSR_STATE_MASK) == PCI_PMCSR_D0) 1566 ret = DDI_SUCCESS; 1567 else { 1568 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: could not " 1569 "raise power to D0 \n"); 1570 } 1571 } 1572 if (ret == DDI_SUCCESS) 1573 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1574 return (ret); 1575 } 1576 1577 /* 1578 * Disable PM for x86 and PLX 8532 switch. 1579 * For PLX Transitioning one port on this switch to low power causes links 1580 * on other ports on the same station to die. Due to PLX erratum #34, we 1581 * can't allow the downstream device go to non-D0 state. 1582 */ 1583 static int 1584 pcieb_pwr_disable(dev_info_t *dip) 1585 { 1586 pcie_pwr_t *pwr_p; 1587 1588 ASSERT(PCIE_PMINFO(dip)); 1589 pwr_p = PCIE_NEXUS_PMINFO(dip); 1590 ASSERT(pwr_p); 1591 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_disable: disabling PM\n"); 1592 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1593 pwr_p->pwr_flags = PCIE_NO_CHILD_PM; 1594 return (DDI_SUCCESS); 1595 } 1596 1597 #ifdef DEBUG 1598 int pcieb_dbg_intr_print = 0; 1599 void 1600 pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...) 1601 { 1602 va_list ap; 1603 1604 if (!pcieb_dbg_print) 1605 return; 1606 1607 if (dip) 1608 prom_printf("%s(%d): %s", ddi_driver_name(dip), 1609 ddi_get_instance(dip), pcieb_debug_sym[bit]); 1610 1611 va_start(ap, fmt); 1612 if (servicing_interrupt()) { 1613 if (pcieb_dbg_intr_print) 1614 prom_vprintf(fmt, ap); 1615 } else { 1616 prom_vprintf(fmt, ap); 1617 } 1618 1619 va_end(ap); 1620 } 1621 #endif 1622 1623 static void 1624 pcieb_id_props(pcieb_devstate_t *pcieb) 1625 { 1626 uint64_t serialid = 0; /* 40b field of EUI-64 serial no. register */ 1627 uint16_t cap_ptr; 1628 uint8_t fic = 0; /* 1 = first in chassis device */ 1629 pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip); 1630 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 1631 1632 /* 1633 * Identify first in chassis. In the special case of a Sun branded 1634 * PLX device, it obviously is first in chassis. Otherwise, in the 1635 * general case, look for an Expansion Slot Register and check its 1636 * first-in-chassis bit. 1637 */ 1638 #ifdef PX_PLX 1639 uint16_t vendor_id = bus_p->bus_dev_ven_id & 0xFFFF; 1640 uint16_t device_id = bus_p->bus_dev_ven_id >> 16; 1641 if ((vendor_id == PXB_VENDOR_SUN) && 1642 ((device_id == PXB_DEVICE_PLX_PCIX) || 1643 (device_id == PXB_DEVICE_PLX_PCIE))) { 1644 fic = 1; 1645 } 1646 #endif /* PX_PLX */ 1647 if ((fic == 0) && ((PCI_CAP_LOCATE(config_handle, 1648 PCI_CAP_ID_SLOT_ID, &cap_ptr)) != DDI_FAILURE)) { 1649 uint8_t esr = PCI_CAP_GET8(config_handle, NULL, 1650 cap_ptr, PCI_CAP_ID_REGS_OFF); 1651 if (PCI_CAPSLOT_FIC(esr)) 1652 fic = 1; 1653 } 1654 1655 if ((PCI_CAP_LOCATE(config_handle, 1656 PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap_ptr)) != DDI_FAILURE) { 1657 /* Serialid can be 0 thru a full 40b number */ 1658 serialid = PCI_XCAP_GET32(config_handle, NULL, 1659 cap_ptr, PCIE_SER_SID_UPPER_DW); 1660 serialid <<= 32; 1661 serialid |= PCI_XCAP_GET32(config_handle, NULL, 1662 cap_ptr, PCIE_SER_SID_LOWER_DW); 1663 } 1664 1665 if (fic) 1666 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1667 "first-in-chassis"); 1668 if (serialid) 1669 (void) ddi_prop_update_int64(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1670 "serialid#", serialid); 1671 } 1672 1673 static void 1674 pcieb_create_ranges_prop(dev_info_t *dip, 1675 ddi_acc_handle_t config_handle) 1676 { 1677 uint32_t base, limit; 1678 ppb_ranges_t ranges[PCIEB_RANGE_LEN]; 1679 uint8_t io_base_lo, io_limit_lo; 1680 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit; 1681 int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int); 1682 1683 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW); 1684 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW); 1685 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI); 1686 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI); 1687 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE); 1688 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT); 1689 1690 /* 1691 * Create ranges for IO space 1692 */ 1693 ranges[i].size_low = ranges[i].size_high = 0; 1694 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0; 1695 ranges[i].child_high = ranges[i].parent_high |= 1696 (PCI_REG_REL_M | PCI_ADDR_IO); 1697 base = PCIEB_16bit_IOADDR(io_base_lo); 1698 limit = PCIEB_16bit_IOADDR(io_limit_lo); 1699 1700 if ((io_base_lo & 0xf) == PCIEB_32BIT_IO) { 1701 base = PCIEB_LADDR(base, io_base_hi); 1702 } 1703 if ((io_limit_lo & 0xf) == PCIEB_32BIT_IO) { 1704 limit = PCIEB_LADDR(limit, io_limit_hi); 1705 } 1706 1707 if ((io_base_lo & PCIEB_32BIT_IO) && (io_limit_hi > 0)) { 1708 base = PCIEB_LADDR(base, io_base_hi); 1709 limit = PCIEB_LADDR(limit, io_limit_hi); 1710 } 1711 1712 /* 1713 * Create ranges for 32bit memory space 1714 */ 1715 base = PCIEB_32bit_MEMADDR(mem_base); 1716 limit = PCIEB_32bit_MEMADDR(mem_limit); 1717 ranges[i].size_low = ranges[i].size_high = 0; 1718 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0; 1719 ranges[i].child_high = ranges[i].parent_high |= 1720 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1721 ranges[i].child_low = ranges[i].parent_low = base; 1722 if (limit >= base) { 1723 ranges[i].size_low = limit - base + PCIEB_MEMGRAIN; 1724 i++; 1725 } 1726 1727 if (i) { 1728 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 1729 (int *)ranges, i * rangelen); 1730 } 1731 } 1732 1733 /* 1734 * For PCI and PCI-X devices including PCIe2PCI bridge, initialize 1735 * cache-line-size and latency timer configuration registers. 1736 */ 1737 void 1738 pcieb_set_pci_perf_parameters(dev_info_t *dip, ddi_acc_handle_t cfg_hdl) 1739 { 1740 uint_t n; 1741 1742 /* Initialize cache-line-size configuration register if needed */ 1743 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1744 "cache-line-size", 0) == 0) { 1745 pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ, 1746 PCIEB_CACHE_LINE_SIZE); 1747 n = pci_config_get8(cfg_hdl, PCI_CONF_CACHE_LINESZ); 1748 if (n != 0) { 1749 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1750 "cache-line-size", n); 1751 } 1752 } 1753 1754 /* Initialize latency timer configuration registers if needed */ 1755 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1756 "latency-timer", 0) == 0) { 1757 uchar_t min_gnt, latency_timer; 1758 uchar_t header_type; 1759 1760 /* Determine the configuration header type */ 1761 header_type = pci_config_get8(cfg_hdl, PCI_CONF_HEADER); 1762 1763 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 1764 latency_timer = PCIEB_LATENCY_TIMER; 1765 pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER, 1766 latency_timer); 1767 } else { 1768 min_gnt = pci_config_get8(cfg_hdl, PCI_CONF_MIN_G); 1769 latency_timer = min_gnt * 8; 1770 } 1771 1772 pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER, 1773 latency_timer); 1774 n = pci_config_get8(cfg_hdl, PCI_CONF_LATENCY_TIMER); 1775 if (n != 0) { 1776 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1777 "latency-timer", n); 1778 } 1779 } 1780 } 1781