1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * PCIC device/interrupt handler 29 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 30 * and Toshiba (and possibly other clones) PCMCIA adapter chip 31 * sets. It implements a subset of Socket Services as defined 32 * in the Solaris PCMCIA design documents 33 */ 34 35 /* 36 * currently defined "properties" 37 * 38 * clock-frequency bus clock frequency 39 * smi system management interrupt override 40 * need-mult-irq need status IRQ for each pair of sockets 41 * disable-audio don't route audio signal to speaker 42 */ 43 44 45 #include <sys/types.h> 46 #include <sys/inttypes.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/user.h> 50 #include <sys/buf.h> 51 #include <sys/file.h> 52 #include <sys/uio.h> 53 #include <sys/conf.h> 54 #include <sys/stat.h> 55 #include <sys/autoconf.h> 56 #include <sys/vtoc.h> 57 #include <sys/dkio.h> 58 #include <sys/ddi.h> 59 #include <sys/sunddi.h> 60 #include <sys/sunndi.h> 61 #include <sys/var.h> 62 #include <sys/callb.h> 63 #include <sys/open.h> 64 #include <sys/ddidmareq.h> 65 #include <sys/dma_engine.h> 66 #include <sys/kstat.h> 67 #include <sys/kmem.h> 68 #include <sys/modctl.h> 69 #include <sys/pci.h> 70 #include <sys/pci_impl.h> 71 72 #include <sys/pctypes.h> 73 #include <sys/pcmcia.h> 74 #include <sys/sservice.h> 75 76 #include <sys/note.h> 77 78 #include <sys/pcic_reg.h> 79 #include <sys/pcic_var.h> 80 81 #if defined(__i386) || defined(__amd64) 82 #include <sys/pci_cfgspace.h> 83 #endif 84 85 #if defined(__sparc) 86 #include <sys/pci/pci_nexus.h> 87 #endif 88 89 #include <sys/hotplug/hpcsvc.h> 90 #include "cardbus/cardbus.h" 91 92 #define SOFTC_SIZE (sizeof (anp_t)) 93 94 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 95 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 96 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 97 static uint_t pcic_intr(caddr_t, caddr_t); 98 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 99 static int pcic_probe(dev_info_t *); 100 101 static int pcic_open(dev_t *, int, int, cred_t *); 102 static int pcic_close(dev_t, int, int, cred_t *); 103 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 104 105 typedef struct pcm_regs pcm_regs_t; 106 107 static void pcic_init_assigned(dev_info_t *); 108 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 109 pci_regspec_t *, int); 110 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 111 112 /* 113 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 114 * are xlated into DMA ctlops. To make this nexus work on x86, we 115 * need to have the default ddi_dma_mctl ctlops in the bus_ops 116 * structure, just to pass the request to the parent. The correct 117 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 118 */ 119 static 120 struct bus_ops pcmciabus_ops = { 121 BUSO_REV, 122 pcmcia_bus_map, 123 NULL, 124 NULL, 125 NULL, 126 i_ddi_map_fault, 127 ddi_no_dma_map, 128 ddi_no_dma_allochdl, 129 ddi_no_dma_freehdl, 130 ddi_no_dma_bindhdl, 131 ddi_no_dma_unbindhdl, 132 ddi_no_dma_flush, 133 ddi_no_dma_win, 134 ddi_dma_mctl, 135 pcmcia_ctlops, 136 pcmcia_prop_op, 137 NULL, /* (*bus_get_eventcookie)(); */ 138 NULL, /* (*bus_add_eventcall)(); */ 139 NULL, /* (*bus_remove_eventcall)(); */ 140 NULL, /* (*bus_post_event)(); */ 141 NULL, /* (*bus_intr_ctl)(); */ 142 NULL, /* (*bus_config)(); */ 143 NULL, /* (*bus_unconfig)(); */ 144 NULL, /* (*bus_fm_init)(); */ 145 NULL, /* (*bus_fm_fini)(); */ 146 NULL, /* (*bus_enter)() */ 147 NULL, /* (*bus_exit)() */ 148 NULL, /* (*bus_power)() */ 149 pcmcia_intr_ops /* (*bus_intr_op)(); */ 150 }; 151 152 static struct cb_ops pcic_cbops = { 153 pcic_open, 154 pcic_close, 155 nodev, 156 nodev, 157 nodev, 158 nodev, 159 nodev, 160 pcic_ioctl, 161 nodev, 162 nodev, 163 nodev, 164 nochpoll, 165 ddi_prop_op, 166 NULL, 167 #ifdef CARDBUS 168 D_NEW | D_MP | D_HOTPLUG 169 #else 170 D_NEW | D_MP 171 #endif 172 }; 173 174 static struct dev_ops pcic_devops = { 175 DEVO_REV, 176 0, 177 pcic_getinfo, 178 nulldev, 179 pcic_probe, 180 pcic_attach, 181 pcic_detach, 182 nulldev, 183 &pcic_cbops, 184 &pcmciabus_ops, 185 NULL, 186 ddi_quiesce_not_supported, /* devo_quiesce */ 187 }; 188 189 void *pcic_soft_state_p = NULL; 190 static int pcic_maxinst = -1; 191 192 int pcic_do_insertion = 1; 193 int pcic_do_removal = 1; 194 195 struct irqmap { 196 int irq; 197 int count; 198 } pcic_irq_map[16]; 199 200 201 int pcic_debug = 0x0; 202 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 203 extern void cardbus_dump_pci_config(dev_info_t *dip); 204 extern void cardbus_dump_socket(dev_info_t *dip); 205 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 206 static void pcic_dump_debqueue(char *msg); 207 208 #if defined(PCIC_DEBUG) 209 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 210 211 #define pcic_mutex_enter(a) \ 212 { \ 213 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 214 mutex_enter(a); \ 215 }; 216 217 #define pcic_mutex_exit(a) \ 218 { \ 219 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 220 mutex_exit(a); \ 221 }; 222 223 #else 224 #define pcic_mutex_enter(a) mutex_enter(a) 225 #define pcic_mutex_exit(a) mutex_exit(a) 226 #endif 227 228 #define PCIC_VCC_3VLEVEL 1 229 #define PCIC_VCC_5VLEVEL 2 230 #define PCIC_VCC_12LEVEL 3 231 232 /* bit patterns to select voltage levels */ 233 int pcic_vpp_levels[13] = { 234 0, 0, 0, 235 1, /* 3.3V */ 236 0, 237 1, /* 5V */ 238 0, 0, 0, 0, 0, 0, 239 2 /* 12V */ 240 }; 241 242 uint8_t pcic_cbv_levels[13] = { 243 0, 0, 0, 244 3, /* 3.3V */ 245 0, 246 2, /* 5V */ 247 0, 0, 0, 0, 0, 0, 248 1 /* 12V */ 249 }; 250 251 struct power_entry pcic_power[4] = { 252 { 253 0, VCC|VPP1|VPP2 254 }, 255 { 256 33, /* 3.3Volt */ 257 VCC|VPP1|VPP2 258 }, 259 { 260 5*10, /* 5Volt */ 261 VCC|VPP1|VPP2 /* currently only know about this */ 262 }, 263 { 264 12*10, /* 12Volt */ 265 VPP1|VPP2 266 } 267 }; 268 269 /* 270 * Base used to allocate ranges of PCI memory on x86 systems 271 * Each instance gets a chunk above the base that is used to map 272 * in the memory and I/O windows for that device. 273 * Pages below the base are also allocated for the EXCA registers, 274 * one per instance. 275 */ 276 #define PCIC_PCI_MEMCHUNK 0x1000000 277 278 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 279 static int pcic_debounce_time = 200000; /* In micro-seconds */ 280 281 struct debounce { 282 pcic_socket_t *pcs; 283 clock_t expire; 284 struct debounce *next; 285 }; 286 287 static struct debounce *pcic_deb_queue = NULL; 288 static kmutex_t pcic_deb_mtx; 289 static kcondvar_t pcic_deb_cv; 290 static kthread_t *pcic_deb_threadid; 291 292 static inthandler_t *pcic_handlers; 293 294 static void pcic_setup_adapter(pcicdev_t *); 295 static int pcic_change(pcicdev_t *, int); 296 static int pcic_ll_reset(pcicdev_t *, int); 297 static void pcic_mswait(pcicdev_t *, int, int); 298 static boolean_t pcic_check_ready(pcicdev_t *, int); 299 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 300 static void pcic_ready_wait(pcicdev_t *, int); 301 extern int pcmcia_get_intr(dev_info_t *, int); 302 extern int pcmcia_return_intr(dev_info_t *, int); 303 extern void pcmcia_cb_suspended(int); 304 extern void pcmcia_cb_resumed(int); 305 306 static int pcic_callback(dev_info_t *, int (*)(), int); 307 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 308 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 309 static int pcic_get_page(dev_info_t *, get_page_t *); 310 static int pcic_get_socket(dev_info_t *, get_socket_t *); 311 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 312 static int pcic_get_window(dev_info_t *, get_window_t *); 313 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 314 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 315 static int pcic_reset_socket(dev_info_t *, int, int); 316 static int pcic_set_page(dev_info_t *, set_page_t *); 317 static int pcic_set_window(dev_info_t *, set_window_t *); 318 static int pcic_set_socket(dev_info_t *, set_socket_t *); 319 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 320 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 321 static void pcic_pm_detection(void *); 322 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 323 static int clext_reg_read(pcicdev_t *, int, uchar_t); 324 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 325 static int pcic_calc_speed(pcicdev_t *, uint32_t); 326 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 327 static int pcic_find_pci_type(pcicdev_t *); 328 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 329 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 330 static uint_t pcic_cd_softint(caddr_t, caddr_t); 331 static uint8_t pcic_getb(pcicdev_t *, int, int); 332 static void pcic_putb(pcicdev_t *, int, int, int8_t); 333 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 334 static uint_t pcic_softintr(caddr_t, caddr_t); 335 336 static void pcic_debounce(pcic_socket_t *); 337 static void pcic_do_resume(pcicdev_t *); 338 static void *pcic_add_debqueue(pcic_socket_t *, int); 339 static void pcic_rm_debqueue(void *); 340 static void pcic_deb_thread(); 341 342 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 343 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 344 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 345 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 346 static void pcic_cb_enable_intr(dev_info_t *); 347 static void pcic_cb_disable_intr(dev_info_t *); 348 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 349 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 350 351 static cb_nexus_cb_t pcic_cbnexus_ops = { 352 pcic_cb_enable_intr, 353 pcic_cb_disable_intr 354 }; 355 356 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 357 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 358 359 #if defined(__sparc) 360 static int pcic_fault(enum pci_fault_ops op, void *arg); 361 #endif 362 363 364 /* 365 * pcmcia interface operations structure 366 * this is the private interface that is exported to the nexus 367 */ 368 pcmcia_if_t pcic_if_ops = { 369 PCIF_MAGIC, 370 PCIF_VERSION, 371 pcic_callback, 372 pcic_get_adapter, 373 pcic_get_page, 374 pcic_get_socket, 375 pcic_get_status, 376 pcic_get_window, 377 pcic_inquire_adapter, 378 pcic_inquire_socket, 379 pcic_inquire_window, 380 pcic_reset_socket, 381 pcic_set_page, 382 pcic_set_window, 383 pcic_set_socket, 384 pcic_set_interrupt, 385 pcic_clear_interrupt, 386 NULL, 387 }; 388 389 /* 390 * chip type identification routines 391 * this list of functions is searched until one of them succeeds 392 * or all fail. i82365SL is assumed if failed. 393 */ 394 static int pcic_ci_cirrus(pcicdev_t *); 395 static int pcic_ci_vadem(pcicdev_t *); 396 static int pcic_ci_ricoh(pcicdev_t *); 397 398 int (*pcic_ci_funcs[])(pcicdev_t *) = { 399 pcic_ci_cirrus, 400 pcic_ci_vadem, 401 pcic_ci_ricoh, 402 NULL 403 }; 404 405 static struct modldrv modldrv = { 406 &mod_driverops, /* Type of module. This one is a driver */ 407 "PCIC PCMCIA adapter driver", /* Name of the module. */ 408 &pcic_devops, /* driver ops */ 409 }; 410 411 static struct modlinkage modlinkage = { 412 MODREV_1, (void *)&modldrv, NULL 413 }; 414 415 int 416 _init() 417 { 418 int stat; 419 420 /* Allocate soft state */ 421 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 422 SOFTC_SIZE, 2)) != DDI_SUCCESS) 423 return (stat); 424 425 if ((stat = mod_install(&modlinkage)) != 0) 426 ddi_soft_state_fini(&pcic_soft_state_p); 427 428 return (stat); 429 } 430 431 int 432 _fini() 433 { 434 int stat = 0; 435 436 if ((stat = mod_remove(&modlinkage)) != 0) 437 return (stat); 438 439 if (pcic_deb_threadid) { 440 mutex_enter(&pcic_deb_mtx); 441 pcic_deb_threadid = 0; 442 while (!pcic_deb_threadid) 443 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 444 pcic_deb_threadid = 0; 445 mutex_exit(&pcic_deb_mtx); 446 447 mutex_destroy(&pcic_deb_mtx); 448 cv_destroy(&pcic_deb_cv); 449 } 450 451 ddi_soft_state_fini(&pcic_soft_state_p); 452 453 return (stat); 454 } 455 456 int 457 _info(struct modinfo *modinfop) 458 { 459 return (mod_info(&modlinkage, modinfop)); 460 } 461 462 /* 463 * pcic_getinfo() 464 * provide instance/device information about driver 465 */ 466 /*ARGSUSED*/ 467 static int 468 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 469 { 470 anp_t *anp; 471 int error = DDI_SUCCESS; 472 minor_t minor; 473 474 switch (cmd) { 475 case DDI_INFO_DEVT2DEVINFO: 476 minor = getminor((dev_t)arg); 477 minor &= 0x7f; 478 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 479 *result = NULL; 480 else 481 *result = anp->an_dip; 482 break; 483 case DDI_INFO_DEVT2INSTANCE: 484 minor = getminor((dev_t)arg); 485 minor &= 0x7f; 486 *result = (void *)((long)minor); 487 break; 488 default: 489 error = DDI_FAILURE; 490 break; 491 } 492 return (error); 493 } 494 495 static int 496 pcic_probe(dev_info_t *dip) 497 { 498 int value; 499 ddi_device_acc_attr_t attr; 500 ddi_acc_handle_t handle; 501 uchar_t *index, *data; 502 503 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 504 return (DDI_PROBE_DONTCARE); 505 506 /* 507 * find a PCIC device (any vendor) 508 * while there can be up to 4 such devices in 509 * a system, we currently only look for 1 510 * per probe. There will be up to 2 chips per 511 * instance since they share I/O space 512 */ 513 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 514 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 515 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 516 517 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 518 (caddr_t *)&index, 519 PCIC_ISA_CONTROL_REG_OFFSET, 520 PCIC_ISA_CONTROL_REG_LENGTH, 521 &attr, &handle) != DDI_SUCCESS) 522 return (DDI_PROBE_FAILURE); 523 524 data = index + 1; 525 526 #if defined(PCIC_DEBUG) 527 if (pcic_debug) 528 cmn_err(CE_CONT, "pcic_probe: entered\n"); 529 if (pcic_debug) 530 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 531 #endif 532 ddi_put8(handle, index, PCIC_CHIP_REVISION); 533 ddi_put8(handle, data, 0); 534 value = ddi_get8(handle, data); 535 #if defined(PCIC_DEBUG) 536 if (pcic_debug) 537 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 538 #endif 539 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 540 (value & 0x30) == 0) { 541 /* 542 * we probably have a PCIC chip in the system 543 * do a little more checking. If we find one, 544 * reset everything in case of softboot 545 */ 546 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 547 ddi_put8(handle, data, 0); 548 value = ddi_get8(handle, data); 549 #if defined(PCIC_DEBUG) 550 if (pcic_debug) 551 cmn_err(CE_CONT, "\tzero test = %x\n", value); 552 #endif 553 /* should read back as zero */ 554 if (value == 0) { 555 /* 556 * we do have one and it is off the bus 557 */ 558 #if defined(PCIC_DEBUG) 559 if (pcic_debug) 560 cmn_err(CE_CONT, "pcic_probe: success\n"); 561 #endif 562 ddi_regs_map_free(&handle); 563 return (DDI_PROBE_SUCCESS); 564 } 565 } 566 #if defined(PCIC_DEBUG) 567 if (pcic_debug) 568 cmn_err(CE_CONT, "pcic_probe: failed\n"); 569 #endif 570 ddi_regs_map_free(&handle); 571 return (DDI_PROBE_FAILURE); 572 } 573 574 /* 575 * These are just defaults they can also be changed via a property in the 576 * conf file. 577 */ 578 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 579 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 580 static int pcic_do_pcmcia_sr = 1; 581 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 582 583 /* 584 * enable insertion/removal interrupt for 32bit cards 585 */ 586 static int 587 cardbus_enable_cd_intr(dev_info_t *dip) 588 { 589 ddi_acc_handle_t iohandle; 590 caddr_t ioaddr; 591 ddi_device_acc_attr_t attr; 592 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 593 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 594 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 595 (void) ddi_regs_map_setup(dip, 1, 596 (caddr_t *)&ioaddr, 597 0, 598 4096, 599 &attr, &iohandle); 600 601 /* CSC Interrupt: Card detect interrupt on */ 602 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 603 ddi_get32(iohandle, 604 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 605 606 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 607 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 608 609 ddi_regs_map_free(&iohandle); 610 return (1); 611 } 612 613 /* 614 * pcic_attach() 615 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 616 * to the system. This is a child of "sysbus" since that is where 617 * the hardware lives, but it provides services to the "pcmcia" 618 * nexus driver. It gives a pointer back via its private data 619 * structure which contains both the dip and socket services entry 620 * points 621 */ 622 static int 623 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 624 { 625 anp_t *pcic_nexus; 626 pcicdev_t *pcic; 627 int irqlevel, value; 628 int pci_cfrn, pci_ctrn; 629 int i, j, smi, actual; 630 char *typename; 631 char bus_type[16] = "(unknown)"; 632 int len = sizeof (bus_type); 633 ddi_device_acc_attr_t attr; 634 anp_t *anp = ddi_get_driver_private(dip); 635 uint_t pri; 636 637 #if defined(PCIC_DEBUG) 638 if (pcic_debug) { 639 cmn_err(CE_CONT, "pcic_attach: entered\n"); 640 } 641 #endif 642 switch (cmd) { 643 case DDI_ATTACH: 644 break; 645 case DDI_RESUME: 646 pcic = anp->an_private; 647 /* 648 * for now, this is a simulated resume. 649 * a real one may need different things. 650 */ 651 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 652 mutex_enter(&pcic->pc_lock); 653 /* should probe for new sockets showing up */ 654 pcic_setup_adapter(pcic); 655 pcic->pc_flags &= ~PCF_SUSPENDED; 656 mutex_exit(&pcic->pc_lock); 657 (void) pcmcia_begin_resume(dip); 658 659 pcic_do_resume(pcic); 660 #ifdef CARDBUS 661 cardbus_restore_children(ddi_get_child(dip)); 662 #endif 663 664 /* 665 * for complete implementation need END_RESUME (later) 666 */ 667 return (DDI_SUCCESS); 668 669 } 670 return (DDI_SUCCESS); 671 default: 672 return (DDI_FAILURE); 673 } 674 675 /* 676 * Allocate soft state associated with this instance. 677 */ 678 if (ddi_soft_state_zalloc(pcic_soft_state_p, 679 ddi_get_instance(dip)) != DDI_SUCCESS) { 680 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 681 ddi_get_instance(dip)); 682 return (DDI_FAILURE); 683 } 684 685 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 686 ddi_get_instance(dip)); 687 688 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 689 690 pcic->dip = dip; 691 pcic_nexus->an_dip = dip; 692 pcic_nexus->an_if = &pcic_if_ops; 693 pcic_nexus->an_private = pcic; 694 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 695 pcic->pc_power = pcic_power; 696 697 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 698 "pci-control-reg-number", pci_control_reg_num); 699 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 700 "pci-config-reg-number", pci_config_reg_num); 701 702 ddi_set_driver_private(dip, pcic_nexus); 703 704 /* 705 * pcic->pc_irq is really the IPL level we want to run at 706 * set the default values here and override from intr spec 707 */ 708 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 709 "interrupt-priorities", -1); 710 711 if (pcic->pc_irq == -1) { 712 int actual; 713 uint_t pri; 714 ddi_intr_handle_t hdl; 715 716 /* see if intrspec tells us different */ 717 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 718 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 719 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 720 pcic->pc_irq = pri; 721 else 722 pcic->pc_irq = LOCK_LEVEL + 1; 723 (void) ddi_intr_free(hdl); 724 } 725 } 726 pcic_nexus->an_ipl = pcic->pc_irq; 727 728 /* 729 * Check our parent bus type. We do different things based on which 730 * bus we're on. 731 */ 732 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 733 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 734 "device_type", (caddr_t)&bus_type[0], &len) != 735 DDI_PROP_SUCCESS) { 736 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 737 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 738 "bus-type", (caddr_t)&bus_type[0], &len) != 739 DDI_PROP_SUCCESS) { 740 741 cmn_err(CE_CONT, 742 "pcic%d: can't find parent bus type\n", 743 ddi_get_instance(dip)); 744 745 kmem_free(pcic, sizeof (pcicdev_t)); 746 ddi_soft_state_free(pcic_soft_state_p, 747 ddi_get_instance(dip)); 748 return (DDI_FAILURE); 749 } 750 } /* ddi_prop_op("device_type") */ 751 752 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 753 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) { 754 pcic->pc_flags = PCF_PCIBUS; 755 } else { 756 cmn_err(CE_WARN, "!pcic%d: non-pci mode (%s) not supported, " 757 "set BIOS to yenta mode if applicable\n", 758 ddi_get_instance(dip), bus_type); 759 kmem_free(pcic, sizeof (pcicdev_t)); 760 ddi_soft_state_free(pcic_soft_state_p, 761 ddi_get_instance(dip)); 762 return (DDI_FAILURE); 763 } 764 765 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 766 DDI_PROP_CANSLEEP, 767 "clock-frequency", 0)) == 0) { 768 if (pcic->pc_flags & PCF_PCIBUS) 769 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 770 else 771 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 772 } else { 773 /* 774 * OBP can declare the speed in Hz... 775 */ 776 if (pcic->bus_speed > 1000000) 777 pcic->bus_speed /= 1000000; 778 } /* ddi_prop_op("clock-frequency") */ 779 780 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 781 782 #ifdef PCIC_DEBUG 783 if (pcic_debug) { 784 cmn_err(CE_CONT, 785 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 786 ddi_get_instance(dip), 787 bus_type, pcic->bus_speed); 788 } 789 #endif 790 791 /* 792 * The reg properties on a PCI node are different than those 793 * on a non-PCI node. Handle that difference here. 794 * If it turns out to be a CardBus chip, we have even more 795 * differences. 796 */ 797 if (pcic->pc_flags & PCF_PCIBUS) { 798 int class_code; 799 #if defined(__i386) || defined(__amd64) 800 pcic->pc_base = 0x1000000; 801 pcic->pc_bound = (uint32_t)~0; 802 pcic->pc_iobase = 0x1000; 803 pcic->pc_iobound = 0xefff; 804 #elif defined(__sparc) 805 pcic->pc_base = 0x0; 806 pcic->pc_bound = (uint32_t)~0; 807 pcic->pc_iobase = 0x00000; 808 pcic->pc_iobound = 0xffff; 809 #endif 810 811 /* usually need to get at config space so map first */ 812 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 813 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 814 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 815 816 if (ddi_regs_map_setup(dip, pci_cfrn, 817 (caddr_t *)&pcic->cfgaddr, 818 PCIC_PCI_CONFIG_REG_OFFSET, 819 PCIC_PCI_CONFIG_REG_LENGTH, 820 &attr, 821 &pcic->cfg_handle) != 822 DDI_SUCCESS) { 823 cmn_err(CE_CONT, 824 "pcic%d: unable to map config space" 825 "regs\n", 826 ddi_get_instance(dip)); 827 828 kmem_free(pcic, sizeof (pcicdev_t)); 829 return (DDI_FAILURE); 830 } /* ddi_regs_map_setup */ 831 832 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 833 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 834 "class-code", -1); 835 #ifdef PCIC_DEBUG 836 if (pcic_debug) { 837 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 838 class_code); 839 } 840 #endif 841 842 switch (class_code) { 843 case PCIC_PCI_CARDBUS: 844 pcic->pc_flags |= PCF_CARDBUS; 845 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 846 /* 847 * Get access to the adapter registers on the 848 * PCI bus. A 4K memory page 849 */ 850 #if defined(PCIC_DEBUG) 851 pcic_err(dip, 8, "Is Cardbus device\n"); 852 if (pcic_debug) { 853 int nr; 854 long rs; 855 (void) ddi_dev_nregs(dip, &nr); 856 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 857 "cfghndl 0x%p nregs %d", 858 (void *)pcic->cfgaddr, 859 (void *)pcic->cfg_handle, nr); 860 861 (void) ddi_dev_regsize(dip, 862 PCIC_PCI_CONTROL_REG_NUM, &rs); 863 864 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 865 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 866 } 867 #endif 868 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 869 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 870 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 871 872 if (ddi_regs_map_setup(dip, pci_ctrn, 873 (caddr_t *)&pcic->ioaddr, 874 PCIC_PCI_CONTROL_REG_OFFSET, 875 PCIC_CB_CONTROL_REG_LENGTH, 876 &attr, &pcic->handle) != 877 DDI_SUCCESS) { 878 cmn_err(CE_CONT, 879 "pcic%d: unable to map PCI regs\n", 880 ddi_get_instance(dip)); 881 ddi_regs_map_free(&pcic->cfg_handle); 882 kmem_free(pcic, sizeof (pcicdev_t)); 883 return (DDI_FAILURE); 884 } /* ddi_regs_map_setup */ 885 886 /* 887 * Find out the chip type - If we're on a PCI bus, 888 * the adapter has that information in the PCI 889 * config space. 890 * Note that we call pcic_find_pci_type here since 891 * it needs a valid mapped pcic->handle to 892 * access some of the adapter registers in 893 * some cases. 894 */ 895 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 896 ddi_regs_map_free(&pcic->handle); 897 ddi_regs_map_free(&pcic->cfg_handle); 898 kmem_free(pcic, sizeof (pcicdev_t)); 899 cmn_err(CE_WARN, "pcic: %s: unsupported " 900 "bridge\n", ddi_get_name_addr(dip)); 901 return (DDI_FAILURE); 902 } 903 break; 904 905 default: 906 case PCIC_PCI_PCMCIA: 907 /* 908 * Get access to the adapter IO registers on the 909 * PCI bus config space. 910 */ 911 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 912 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 913 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 914 915 /* 916 * We need a default mapping to the adapter's IO 917 * control register space. For most adapters 918 * that are of class PCIC_PCI_PCMCIA (or of 919 * a default class) the control registers 920 * will be using the 82365-type control/data 921 * format. 922 */ 923 if (ddi_regs_map_setup(dip, pci_ctrn, 924 (caddr_t *)&pcic->ioaddr, 925 PCIC_PCI_CONTROL_REG_OFFSET, 926 PCIC_PCI_CONTROL_REG_LENGTH, 927 &attr, 928 &pcic->handle) != DDI_SUCCESS) { 929 cmn_err(CE_CONT, 930 "pcic%d: unable to map PCI regs\n", 931 ddi_get_instance(dip)); 932 ddi_regs_map_free(&pcic->cfg_handle); 933 kmem_free(pcic, sizeof (pcicdev_t)); 934 return (DDI_FAILURE); 935 } /* ddi_regs_map_setup */ 936 937 /* 938 * Find out the chip type - If we're on a PCI bus, 939 * the adapter has that information in the PCI 940 * config space. 941 * Note that we call pcic_find_pci_type here since 942 * it needs a valid mapped pcic->handle to 943 * access some of the adapter registers in 944 * some cases. 945 */ 946 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 947 ddi_regs_map_free(&pcic->handle); 948 ddi_regs_map_free(&pcic->cfg_handle); 949 kmem_free(pcic, sizeof (pcicdev_t)); 950 cmn_err(CE_WARN, "pcic: %s: unsupported " 951 "bridge\n", 952 ddi_get_name_addr(dip)); 953 return (DDI_FAILURE); 954 } 955 956 /* 957 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 958 * for extended registers even though they are 959 * not CardBus adapters. For those adapters, 960 * re-map pcic->handle to be large enough to 961 * encompass the Yenta registers. 962 */ 963 switch (pcic->pc_type) { 964 case PCIC_TI_PCI1031: 965 ddi_regs_map_free(&pcic->handle); 966 967 if (ddi_regs_map_setup(dip, 968 PCIC_PCI_CONTROL_REG_NUM, 969 (caddr_t *)&pcic->ioaddr, 970 PCIC_PCI_CONTROL_REG_OFFSET, 971 PCIC_CB_CONTROL_REG_LENGTH, 972 &attr, 973 &pcic->handle) != DDI_SUCCESS) { 974 cmn_err(CE_CONT, 975 "pcic%d: unable to map " 976 "PCI regs\n", 977 ddi_get_instance(dip)); 978 ddi_regs_map_free(&pcic->cfg_handle); 979 kmem_free(pcic, sizeof (pcicdev_t)); 980 return (DDI_FAILURE); 981 } /* ddi_regs_map_setup */ 982 break; 983 default: 984 break; 985 } /* switch (pcic->pc_type) */ 986 break; 987 } /* switch (class_code) */ 988 } else { 989 /* 990 * We're not on a PCI bus, so assume an ISA bus type 991 * register property. Get access to the adapter IO 992 * registers on a non-PCI bus. 993 */ 994 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 995 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 996 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 997 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 998 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 999 1000 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1001 (caddr_t *)&pcic->ioaddr, 1002 PCIC_ISA_CONTROL_REG_OFFSET, 1003 PCIC_ISA_CONTROL_REG_LENGTH, 1004 &attr, 1005 &pcic->handle) != DDI_SUCCESS) { 1006 cmn_err(CE_CONT, 1007 "pcic%d: unable to map ISA registers\n", 1008 ddi_get_instance(dip)); 1009 1010 kmem_free(pcic, sizeof (pcicdev_t)); 1011 return (DDI_FAILURE); 1012 } /* ddi_regs_map_setup */ 1013 1014 /* ISA bus is limited to 24-bits, but not first 640K */ 1015 pcic->pc_base = 0xd0000; 1016 pcic->pc_bound = (uint32_t)~0; 1017 pcic->pc_iobase = 0x1000; 1018 pcic->pc_iobound = 0xefff; 1019 } /* !PCF_PCIBUS */ 1020 1021 #ifdef PCIC_DEBUG 1022 if (pcic_debug) { 1023 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1024 pcic->pc_flags, pcic->pc_type); 1025 } 1026 #endif 1027 1028 /* 1029 * Setup various adapter registers for the PCI case. For the 1030 * non-PCI case, find out the chip type. 1031 */ 1032 if (pcic->pc_flags & PCF_PCIBUS) { 1033 int iline; 1034 #if defined(__sparc) 1035 iline = 0; 1036 #else 1037 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1038 #endif 1039 1040 /* set flags and socket counts based on chip type */ 1041 switch (pcic->pc_type) { 1042 uint32_t cfg; 1043 case PCIC_INTEL_i82092: 1044 cfg = ddi_get8(pcic->cfg_handle, 1045 pcic->cfgaddr + PCIC_82092_PCICON); 1046 /* we can only support 4 Socket version */ 1047 if (cfg & PCIC_82092_4_SOCKETS) { 1048 pcic->pc_numsockets = 4; 1049 pcic->pc_type = PCIC_INTEL_i82092; 1050 if (iline != 0xFF) 1051 pcic->pc_intr_mode = 1052 PCIC_INTR_MODE_PCI_1; 1053 else 1054 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1055 } else { 1056 cmn_err(CE_CONT, 1057 "pcic%d: Intel 82092 adapter " 1058 "in unsupported configuration: 0x%x", 1059 ddi_get_instance(pcic->dip), cfg); 1060 pcic->pc_numsockets = 0; 1061 } /* PCIC_82092_4_SOCKETS */ 1062 break; 1063 case PCIC_CL_PD6730: 1064 case PCIC_CL_PD6729: 1065 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1066 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1067 DDI_PROP_CANSLEEP, 1068 "interrupts", 0); 1069 /* if not interrupt pin then must use ISA style IRQs */ 1070 if (cfg == 0 || iline == 0xFF) 1071 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1072 else { 1073 /* 1074 * we have the option to use PCI interrupts. 1075 * this might not be optimal but in some cases 1076 * is the only thing possible (sparc case). 1077 * we now deterine what is possible. 1078 */ 1079 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1080 } 1081 pcic->pc_numsockets = 2; 1082 pcic->pc_flags |= PCF_IO_REMAP; 1083 break; 1084 case PCIC_TI_PCI1031: 1085 /* this chip doesn't do CardBus but looks like one */ 1086 pcic->pc_flags &= ~PCF_CARDBUS; 1087 /* FALLTHROUGH */ 1088 default: 1089 pcic->pc_flags |= PCF_IO_REMAP; 1090 /* FALLTHROUGH */ 1091 /* indicate feature even if not supported */ 1092 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1093 /* Not sure if these apply to all these chips */ 1094 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1095 pcic->pc_flags |= pcic_use_cbpwrctl; 1096 1097 pcic->pc_numsockets = 1; /* one per function */ 1098 if (iline != 0xFF) { 1099 uint8_t cfg; 1100 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1101 1102 cfg = ddi_get8(pcic->cfg_handle, 1103 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1104 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1105 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1106 PCIC_BRIDGE_CTL_REG), cfg); 1107 } 1108 else 1109 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1110 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1111 break; 1112 } 1113 } else { 1114 /* 1115 * We're not on a PCI bus so do some more 1116 * checking for adapter type here. 1117 * For the non-PCI bus case: 1118 * It could be any one of a number of different chips 1119 * If we can't determine anything else, it is assumed 1120 * to be an Intel 82365SL. The Cirrus Logic PD6710 1121 * has an extension register that provides unique 1122 * identification. Toshiba chip isn't detailed as yet. 1123 */ 1124 1125 /* Init the CL id mode */ 1126 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1127 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1128 1129 /* default to Intel i82365SL and then refine */ 1130 pcic->pc_type = PCIC_I82365SL; 1131 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1132 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1133 /* go until one succeeds or none left */ 1134 if (pcic_ci_funcs[value](pcic)) 1135 break; 1136 } 1137 1138 /* any chip specific flags get set here */ 1139 switch (pcic->pc_type) { 1140 case PCIC_CL_PD6722: 1141 pcic->pc_flags |= PCF_DMA; 1142 } 1143 1144 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1145 /* 1146 * look for total number of sockets. 1147 * basically check each possible socket for 1148 * presence like in probe 1149 */ 1150 1151 /* turn all windows off */ 1152 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1153 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1154 1155 /* 1156 * if a zero is read back, then this socket 1157 * might be present. It would be except for 1158 * some systems that map the secondary PCIC 1159 * chip space back to the first. 1160 */ 1161 if (value != 0) { 1162 /* definitely not so skip */ 1163 /* note: this is for Compaq support */ 1164 continue; 1165 } 1166 1167 /* further tests */ 1168 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1169 PCIC_REV_MASK; 1170 if (!(value >= PCIC_REV_LEVEL_LOW && 1171 value <= PCIC_REV_LEVEL_HI)) 1172 break; 1173 1174 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1175 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1176 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1177 1178 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1179 if (value != 0xaa || j != 0x55) 1180 break; 1181 1182 /* 1183 * at this point we know if we have hardware 1184 * of some type and not just the bus holding 1185 * a pattern for us. We still have to determine 1186 * the case where more than 2 sockets are 1187 * really the same due to peculiar mappings of 1188 * hardware. 1189 */ 1190 j = pcic->pc_numsockets++; 1191 pcic->pc_sockets[j].pcs_flags = 0; 1192 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1193 pcic->pc_sockets[j].pcs_socket = i; 1194 1195 /* put PC Card into RESET, just in case */ 1196 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1197 pcic_putb(pcic, i, PCIC_INTERRUPT, 1198 value & ~PCIC_RESET); 1199 } 1200 1201 #if defined(PCIC_DEBUG) 1202 if (pcic_debug) 1203 cmn_err(CE_CONT, "num sockets = %d\n", 1204 pcic->pc_numsockets); 1205 #endif 1206 if (pcic->pc_numsockets == 0) { 1207 ddi_regs_map_free(&pcic->handle); 1208 kmem_free(pcic, sizeof (pcicdev_t)); 1209 return (DDI_FAILURE); 1210 } 1211 1212 /* 1213 * need to think this through again in light of 1214 * Compaq not following the model that all the 1215 * chip vendors recommend. IBM 755 seems to be 1216 * afflicted as well. Basically, if the vendor 1217 * wired things wrong, socket 0 responds for socket 2 1218 * accesses, etc. 1219 */ 1220 if (pcic->pc_numsockets > 2) { 1221 int count = pcic->pc_numsockets / 4; 1222 for (i = 0; i < count; i++) { 1223 /* put pattern into socket 0 */ 1224 pcic_putb(pcic, i, 1225 PCIC_SYSMEM_0_STARTLOW, 0x11); 1226 1227 /* put pattern into socket 2 */ 1228 pcic_putb(pcic, i + 2, 1229 PCIC_SYSMEM_0_STARTLOW, 0x33); 1230 1231 /* read back socket 0 */ 1232 value = pcic_getb(pcic, i, 1233 PCIC_SYSMEM_0_STARTLOW); 1234 1235 /* read back chip 1 socket 0 */ 1236 j = pcic_getb(pcic, i + 2, 1237 PCIC_SYSMEM_0_STARTLOW); 1238 if (j == value) { 1239 pcic->pc_numsockets -= 2; 1240 } 1241 } 1242 } 1243 1244 smi = 0xff; /* no more override */ 1245 1246 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1247 DDI_PROP_DONTPASS, "need-mult-irq", 1248 0xffff) != 0xffff) 1249 pcic->pc_flags |= PCF_MULT_IRQ; 1250 1251 } /* !PCF_PCIBUS */ 1252 1253 /* 1254 * some platforms/busses need to have resources setup 1255 * this is temporary until a real resource allocator is 1256 * implemented. 1257 */ 1258 1259 pcic_init_assigned(dip); 1260 1261 typename = pcic->pc_chipname; 1262 1263 #ifdef PCIC_DEBUG 1264 if (pcic_debug) { 1265 int nregs, nintrs; 1266 1267 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1268 nregs = 0; 1269 1270 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1271 nintrs = 0; 1272 1273 cmn_err(CE_CONT, 1274 "pcic%d: %d register sets, %d interrupts\n", 1275 ddi_get_instance(dip), nregs, nintrs); 1276 1277 nintrs = 0; 1278 while (nregs--) { 1279 off_t size; 1280 1281 if (ddi_dev_regsize(dip, nintrs, &size) == 1282 DDI_SUCCESS) { 1283 cmn_err(CE_CONT, 1284 "\tregnum %d size %ld (0x%lx)" 1285 "bytes", 1286 nintrs, size, size); 1287 if (nintrs == 1288 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1289 PCIC_ISA_CONTROL_REG_NUM : 1290 PCIC_PCI_CONTROL_REG_NUM)) 1291 cmn_err(CE_CONT, 1292 " mapped at: 0x%p\n", 1293 (void *)pcic->ioaddr); 1294 else 1295 cmn_err(CE_CONT, "\n"); 1296 } else { 1297 cmn_err(CE_CONT, 1298 "\tddi_dev_regsize(rnumber" 1299 "= %d) returns DDI_FAILURE\n", 1300 nintrs); 1301 } 1302 nintrs++; 1303 } /* while */ 1304 } /* if (pcic_debug) */ 1305 #endif 1306 1307 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1308 1309 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1310 "disable-audio", 0)) 1311 pcic->pc_flags |= PCF_AUDIO; 1312 1313 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1314 "disable-cardbus", 0)) 1315 pcic->pc_flags &= ~PCF_CARDBUS; 1316 1317 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1318 typename); 1319 1320 /* 1321 * Init all socket SMI levels to 0 (no SMI) 1322 */ 1323 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1324 pcic->pc_sockets[i].pcs_smi = 0; 1325 pcic->pc_sockets[i].pcs_debounce_id = 0; 1326 pcic->pc_sockets[i].pcs_pcic = pcic; 1327 } 1328 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1329 1330 /* 1331 * Setup the IRQ handler(s) 1332 */ 1333 switch (pcic->pc_intr_mode) { 1334 int xx; 1335 case PCIC_INTR_MODE_ISA: 1336 /* 1337 * On a non-PCI bus, we just use whatever SMI IRQ level was 1338 * specified above, and the IO IRQ levels are allocated 1339 * dynamically. 1340 */ 1341 for (xx = 15, smi = 0; xx >= 0; xx--) { 1342 if (PCIC_IRQ(xx) & 1343 PCIC_AVAIL_IRQS) { 1344 smi = pcmcia_get_intr(dip, xx); 1345 if (smi >= 0) 1346 break; 1347 } 1348 } 1349 #if defined(PCIC_DEBUG) 1350 if (pcic_debug) 1351 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1352 #endif 1353 /* init to same so share is easy */ 1354 for (i = 0; i < pcic->pc_numsockets; i++) 1355 pcic->pc_sockets[i].pcs_smi = smi; 1356 /* any special handling of IRQ levels */ 1357 if (pcic->pc_flags & PCF_MULT_IRQ) { 1358 for (i = 2; i < pcic->pc_numsockets; i++) { 1359 if ((i & 1) == 0) { 1360 int xx; 1361 for (xx = 15, smi = 0; xx >= 0; xx--) { 1362 if (PCIC_IRQ(xx) & 1363 PCIC_AVAIL_IRQS) { 1364 smi = 1365 pcmcia_get_intr(dip, 1366 xx); 1367 if (smi >= 0) 1368 break; 1369 } 1370 } 1371 } 1372 if (smi >= 0) 1373 pcic->pc_sockets[i].pcs_smi = smi; 1374 } 1375 } 1376 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1377 sizeof (ddi_intr_handle_t), KM_SLEEP); 1378 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1379 struct intrspec *ispecp; 1380 struct ddi_parent_private_data *pdp; 1381 1382 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1383 continue; 1384 else { 1385 irqlevel = pcic->pc_sockets[i].pcs_smi; 1386 } 1387 /* 1388 * now convert the allocated IRQ into an intrspec 1389 * and ask our parent to add it. Don't use 1390 * the ddi_add_intr since we don't have a 1391 * default intrspec in all cases. 1392 * 1393 * note: this sort of violates DDI but we don't 1394 * get hardware intrspecs for many of the devices. 1395 * at the same time, we know how to allocate them 1396 * so we do the right thing. 1397 */ 1398 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1399 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1400 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1401 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1402 ddi_get_name(dip)); 1403 goto isa_exit1; 1404 } 1405 1406 /* 1407 * See earlier note: 1408 * Since some devices don't have 'intrspec' 1409 * we make one up in rootnex. 1410 * 1411 * However, it is not properly initialized as 1412 * the data it needs is present in this driver 1413 * and there is no interface to pass that up. 1414 * Specially 'irqlevel' is very important and 1415 * it is part of pcic struct. 1416 * 1417 * Set 'intrspec' up here; otherwise adding the 1418 * interrupt will fail. 1419 */ 1420 pdp = ddi_get_parent_data(dip); 1421 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1422 ispecp->intrspec_vec = irqlevel; 1423 ispecp->intrspec_pri = pcic->pc_irq; 1424 1425 /* Stay compatible w/ PCMCIA */ 1426 pcic->pc_pri = (ddi_iblock_cookie_t) 1427 (uintptr_t)pcic->pc_irq; 1428 pcic->pc_dcookie.idev_priority = 1429 (uintptr_t)pcic->pc_pri; 1430 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1431 1432 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1433 pcic->pc_irq); 1434 1435 if (i == 0) { 1436 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1437 DDI_INTR_PRI(pcic->pc_irq)); 1438 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1439 NULL); 1440 } 1441 1442 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1443 pcic_intr, (caddr_t)pcic, NULL)) { 1444 cmn_err(CE_WARN, 1445 "%s: ddi_intr_add_handler failed", 1446 ddi_get_name(dip)); 1447 goto isa_exit2; 1448 } 1449 1450 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1451 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1452 ddi_get_name(dip)); 1453 for (j = i; j < 0; j--) 1454 (void) ddi_intr_remove_handler( 1455 pcic->pc_intr_htblp[j]); 1456 goto isa_exit2; 1457 } 1458 } 1459 break; 1460 case PCIC_INTR_MODE_PCI_1: 1461 case PCIC_INTR_MODE_PCI: 1462 /* 1463 * If we're on a PCI bus, we route all interrupts, both SMI 1464 * and IO interrupts, through a single interrupt line. 1465 * Assign the SMI IRQ level to the IO IRQ level here. 1466 */ 1467 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1468 KM_SLEEP); 1469 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1470 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1471 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1472 goto pci_exit1; 1473 1474 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1475 &pri) != DDI_SUCCESS) { 1476 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1477 goto pci_exit1; 1478 } 1479 1480 pcic->pc_pri = (void *)(uintptr_t)pri; 1481 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1482 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1483 1484 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1485 pcic_intr, (caddr_t)pcic, NULL)) 1486 goto pci_exit2; 1487 1488 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1489 (void) ddi_intr_remove_handler( 1490 pcic->pc_pci_intr_hdlp[0]); 1491 goto pci_exit2; 1492 } 1493 1494 /* Stay compatible w/ PCMCIA */ 1495 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1496 1497 /* init to same (PCI) so share is easy */ 1498 for (i = 0; i < pcic->pc_numsockets; i++) 1499 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1500 break; 1501 } 1502 1503 /* 1504 * Setup the adapter hardware to some reasonable defaults. 1505 */ 1506 mutex_enter(&pcic->pc_lock); 1507 /* mark the driver state as attached */ 1508 pcic->pc_flags |= PCF_ATTACHED; 1509 pcic_setup_adapter(pcic); 1510 1511 for (j = 0; j < pcic->pc_numsockets; j++) 1512 if (ddi_intr_add_softint(dip, 1513 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1514 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1515 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1516 goto pci_exit2; 1517 1518 #if defined(PCIC_DEBUG) 1519 if (pcic_debug) 1520 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1521 pcic->pc_numsockets); 1522 #endif 1523 1524 pcic_nexus->an_iblock = &pcic->pc_pri; 1525 pcic_nexus->an_idev = &pcic->pc_dcookie; 1526 1527 mutex_exit(&pcic->pc_lock); 1528 1529 #ifdef CARDBUS 1530 (void) cardbus_enable_cd_intr(dip); 1531 if (pcic_debug) { 1532 1533 cardbus_dump_pci_config(dip); 1534 cardbus_dump_socket(dip); 1535 } 1536 1537 /* 1538 * Give the Cardbus misc module a chance to do it's per-adapter 1539 * instance setup. Note that there is no corresponding detach() 1540 * call. 1541 */ 1542 if (pcic->pc_flags & PCF_CARDBUS) 1543 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1544 cmn_err(CE_CONT, 1545 "pcic_attach: cardbus_attach failed\n"); 1546 goto pci_exit2; 1547 } 1548 #endif 1549 1550 /* 1551 * Give the PCMCIA misc module a chance to do it's per-adapter 1552 * instance setup. 1553 */ 1554 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1555 goto pci_exit2; 1556 1557 if (pcic_maxinst == -1) { 1558 /* This assumes that all instances run at the same IPL. */ 1559 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1560 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1561 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1562 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1563 v.v_maxsyspri - 2); 1564 } 1565 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1566 /* 1567 * Setup a debounce timeout to do an initial card detect 1568 * and enable interrupts. 1569 */ 1570 for (j = 0; j < pcic->pc_numsockets; j++) { 1571 pcic->pc_sockets[j].pcs_debounce_id = 1572 pcic_add_debqueue(&pcic->pc_sockets[j], 1573 drv_usectohz(pcic_debounce_time)); 1574 } 1575 1576 return (i); 1577 1578 isa_exit2: 1579 mutex_destroy(&pcic->intr_lock); 1580 mutex_destroy(&pcic->pc_lock); 1581 for (j = i; j < 0; j--) 1582 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1583 isa_exit1: 1584 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1585 ddi_regs_map_free(&pcic->handle); 1586 if (pcic->pc_flags & PCF_PCIBUS) 1587 ddi_regs_map_free(&pcic->cfg_handle); 1588 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1589 sizeof (ddi_intr_handle_t)); 1590 kmem_free(pcic, sizeof (pcicdev_t)); 1591 return (DDI_FAILURE); 1592 1593 pci_exit2: 1594 mutex_destroy(&pcic->intr_lock); 1595 mutex_destroy(&pcic->pc_lock); 1596 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1597 pci_exit1: 1598 ddi_regs_map_free(&pcic->handle); 1599 if (pcic->pc_flags & PCF_PCIBUS) 1600 ddi_regs_map_free(&pcic->cfg_handle); 1601 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1602 kmem_free(pcic, sizeof (pcicdev_t)); 1603 return (DDI_FAILURE); 1604 } 1605 1606 /* 1607 * pcic_detach() 1608 * request to detach from the system 1609 */ 1610 static int 1611 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1612 { 1613 anp_t *anp = ddi_get_driver_private(dip); 1614 pcicdev_t *pcic = anp->an_private; 1615 int i; 1616 1617 switch (cmd) { 1618 case DDI_DETACH: 1619 /* don't detach if the nexus still talks to us */ 1620 if (pcic->pc_callback != NULL) 1621 return (DDI_FAILURE); 1622 1623 /* kill off the pm simulation */ 1624 if (pcic->pc_pmtimer) 1625 (void) untimeout(pcic->pc_pmtimer); 1626 1627 /* turn everything off for all sockets and chips */ 1628 for (i = 0; i < pcic->pc_numsockets; i++) { 1629 if (pcic->pc_sockets[i].pcs_debounce_id) 1630 pcic_rm_debqueue( 1631 pcic->pc_sockets[i].pcs_debounce_id); 1632 pcic->pc_sockets[i].pcs_debounce_id = 0; 1633 1634 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1635 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1636 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1637 /* disable interrupts and put card into RESET */ 1638 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1639 } 1640 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1641 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1642 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1643 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1644 pcic->pc_flags = 0; 1645 mutex_destroy(&pcic->pc_lock); 1646 mutex_destroy(&pcic->intr_lock); 1647 cv_destroy(&pcic->pm_cv); 1648 if (pcic->pc_flags & PCF_PCIBUS) 1649 ddi_regs_map_free(&pcic->cfg_handle); 1650 if (pcic->handle) 1651 ddi_regs_map_free(&pcic->handle); 1652 kmem_free(pcic, sizeof (pcicdev_t)); 1653 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1654 return (DDI_SUCCESS); 1655 1656 case DDI_SUSPEND: 1657 case DDI_PM_SUSPEND: 1658 /* 1659 * we got a suspend event (either real or imagined) 1660 * so notify the nexus proper that all existing cards 1661 * should go away. 1662 */ 1663 mutex_enter(&pcic->pc_lock); 1664 #ifdef CARDBUS 1665 if (pcic->pc_flags & PCF_CARDBUS) { 1666 for (i = 0; i < pcic->pc_numsockets; i++) { 1667 if ((pcic->pc_sockets[i].pcs_flags & 1668 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1669 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) { 1670 1671 pcmcia_cb_suspended( 1672 pcic->pc_sockets[i].pcs_socket); 1673 } 1674 } 1675 1676 cardbus_save_children(ddi_get_child(dip)); 1677 } 1678 #endif 1679 /* turn everything off for all sockets and chips */ 1680 for (i = 0; i < pcic->pc_numsockets; i++) { 1681 if (pcic->pc_sockets[i].pcs_debounce_id) 1682 pcic_rm_debqueue( 1683 pcic->pc_sockets[i].pcs_debounce_id); 1684 pcic->pc_sockets[i].pcs_debounce_id = 0; 1685 1686 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1687 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1688 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1689 /* disable interrupts and put card into RESET */ 1690 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1691 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1692 if (pcic->pc_flags & PCF_CBPWRCTL) 1693 pcic_putcb(pcic, CB_CONTROL, 0); 1694 1695 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1696 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1697 /* 1698 * Because we are half way through a save 1699 * all this does is schedule a removal event 1700 * to cs for when the system comes back. 1701 * This doesn't actually matter. 1702 */ 1703 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1704 pcic->pc_callback) { 1705 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1706 PCE_CARD_REMOVAL, 1707 pcic->pc_sockets[i].pcs_socket); 1708 } 1709 } 1710 } 1711 1712 pcic->pc_flags |= PCF_SUSPENDED; 1713 mutex_exit(&pcic->pc_lock); 1714 1715 /* 1716 * when true power management exists, save the adapter 1717 * state here to enable a recovery. For the emulation 1718 * condition, the state is gone 1719 */ 1720 return (DDI_SUCCESS); 1721 1722 default: 1723 return (EINVAL); 1724 } 1725 } 1726 1727 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1728 static uint32_t pcic_tisysctl_offbits = 0; 1729 static uint32_t pcic_default_latency = 0x40; 1730 1731 static void 1732 pcic_setup_adapter(pcicdev_t *pcic) 1733 { 1734 int i; 1735 int value, flags; 1736 1737 #if defined(__i386) || defined(__amd64) 1738 pci_regspec_t *reg; 1739 uchar_t bus, dev, func; 1740 uint_t classcode; 1741 int length; 1742 #endif 1743 1744 if (pcic->pc_flags & PCF_PCIBUS) { 1745 /* 1746 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1747 */ 1748 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1749 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1750 } 1751 /* enable each socket */ 1752 for (i = 0; i < pcic->pc_numsockets; i++) { 1753 pcic->pc_sockets[i].pcs_flags = 0; 1754 /* find out the socket capabilities (I/O vs memory) */ 1755 value = pcic_getb(pcic, i, 1756 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1757 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1758 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1759 1760 /* disable all windows just in case */ 1761 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1762 1763 switch (pcic->pc_type) { 1764 uint32_t cfg32; 1765 uint16_t cfg16; 1766 uint8_t cfg; 1767 1768 /* enable extended registers for Vadem */ 1769 case PCIC_VADEM_VG469: 1770 case PCIC_VADEM: 1771 1772 /* enable card status change interrupt for socket */ 1773 break; 1774 1775 case PCIC_I82365SL: 1776 break; 1777 1778 case PCIC_CL_PD6710: 1779 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1780 break; 1781 1782 /* 1783 * On the CL_6730, we need to set up the interrupt 1784 * signalling mode (PCI mode) and set the SMI and 1785 * IRQ interrupt lines to PCI/level-mode. 1786 */ 1787 case PCIC_CL_PD6730: 1788 switch (pcic->pc_intr_mode) { 1789 case PCIC_INTR_MODE_PCI_1: 1790 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1791 ((clext_reg_read(pcic, i, 1792 PCIC_CLEXT_MISC_CTL_3) & 1793 ~PCIC_CLEXT_INT_PCI) | 1794 PCIC_CLEXT_INT_PCI)); 1795 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1796 (PCIC_CLEXT_IRQ_LVL_MODE | 1797 PCIC_CLEXT_SMI_LVL_MODE)); 1798 cfg = PCIC_CL_LP_DYN_MODE; 1799 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1800 break; 1801 case PCIC_INTR_MODE_ISA: 1802 break; 1803 } 1804 break; 1805 /* 1806 * On the CL_6729, we set the SMI and IRQ interrupt 1807 * lines to PCI/level-mode. as well as program the 1808 * correct clock speed divider bit. 1809 */ 1810 case PCIC_CL_PD6729: 1811 switch (pcic->pc_intr_mode) { 1812 case PCIC_INTR_MODE_PCI_1: 1813 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1814 (PCIC_CLEXT_IRQ_LVL_MODE | 1815 PCIC_CLEXT_SMI_LVL_MODE)); 1816 1817 break; 1818 case PCIC_INTR_MODE_ISA: 1819 break; 1820 } 1821 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1822 cfg = 0; 1823 cfg |= PCIC_CL_TIMER_CLK_DIV; 1824 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1825 } 1826 break; 1827 case PCIC_INTEL_i82092: 1828 cfg = PCIC_82092_EN_TIMING; 1829 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1830 cfg |= PCIC_82092_PCICLK_25MHZ; 1831 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1832 PCIC_82092_PCICON, cfg); 1833 break; 1834 case PCIC_TI_PCI1130: 1835 case PCIC_TI_PCI1131: 1836 case PCIC_TI_PCI1250: 1837 case PCIC_TI_PCI1031: 1838 cfg = ddi_get8(pcic->cfg_handle, 1839 pcic->cfgaddr + PCIC_DEVCTL_REG); 1840 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1841 switch (pcic->pc_intr_mode) { 1842 case PCIC_INTR_MODE_ISA: 1843 cfg |= PCIC_DEVCTL_INTR_ISA; 1844 break; 1845 } 1846 #ifdef PCIC_DEBUG 1847 if (pcic_debug) { 1848 cmn_err(CE_CONT, "pcic_setup_adapter: " 1849 "write reg 0x%x=%x \n", 1850 PCIC_DEVCTL_REG, cfg); 1851 } 1852 #endif 1853 ddi_put8(pcic->cfg_handle, 1854 pcic->cfgaddr + PCIC_DEVCTL_REG, 1855 cfg); 1856 1857 cfg = ddi_get8(pcic->cfg_handle, 1858 pcic->cfgaddr + PCIC_CRDCTL_REG); 1859 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1860 PCIC_CRDCTL_PCIFUNC); 1861 switch (pcic->pc_intr_mode) { 1862 case PCIC_INTR_MODE_PCI_1: 1863 cfg |= PCIC_CRDCTL_PCIINTR | 1864 PCIC_CRDCTL_PCICSC | 1865 PCIC_CRDCTL_PCIFUNC; 1866 pcic->pc_flags |= PCF_USE_SMI; 1867 break; 1868 } 1869 #ifdef PCIC_DEBUG 1870 if (pcic_debug) { 1871 cmn_err(CE_CONT, "pcic_setup_adapter: " 1872 " write reg 0x%x=%x \n", 1873 PCIC_CRDCTL_REG, cfg); 1874 } 1875 #endif 1876 ddi_put8(pcic->cfg_handle, 1877 pcic->cfgaddr + PCIC_CRDCTL_REG, 1878 cfg); 1879 break; 1880 case PCIC_TI_PCI1221: 1881 case PCIC_TI_PCI1225: 1882 cfg = ddi_get8(pcic->cfg_handle, 1883 pcic->cfgaddr + PCIC_DEVCTL_REG); 1884 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1885 #ifdef PCIC_DEBUG 1886 if (pcic_debug) { 1887 cmn_err(CE_CONT, "pcic_setup_adapter: " 1888 " write reg 0x%x=%x \n", 1889 PCIC_DEVCTL_REG, cfg); 1890 } 1891 #endif 1892 ddi_put8(pcic->cfg_handle, 1893 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1894 1895 cfg = ddi_get8(pcic->cfg_handle, 1896 pcic->cfgaddr + PCIC_DIAG_REG); 1897 if (pcic->pc_type == PCIC_TI_PCI1225) { 1898 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1899 } else { 1900 cfg |= PCIC_DIAG_ASYNC; 1901 } 1902 pcic->pc_flags |= PCF_USE_SMI; 1903 #ifdef PCIC_DEBUG 1904 if (pcic_debug) { 1905 cmn_err(CE_CONT, "pcic_setup_adapter: " 1906 " write reg 0x%x=%x \n", 1907 PCIC_DIAG_REG, cfg); 1908 } 1909 #endif 1910 ddi_put8(pcic->cfg_handle, 1911 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1912 break; 1913 case PCIC_TI_PCI1520: 1914 case PCIC_TI_PCI1510: 1915 case PCIC_TI_VENDOR: 1916 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1917 /* functional intr routed by ExCA register */ 1918 cfg = ddi_get8(pcic->cfg_handle, 1919 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1920 cfg |= PCIC_FUN_INT_MOD_ISA; 1921 ddi_put8(pcic->cfg_handle, 1922 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1923 cfg); 1924 1925 /* IRQ serialized interrupts */ 1926 cfg = ddi_get8(pcic->cfg_handle, 1927 pcic->cfgaddr + PCIC_DEVCTL_REG); 1928 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1929 cfg |= PCIC_DEVCTL_INTR_ISA; 1930 ddi_put8(pcic->cfg_handle, 1931 pcic->cfgaddr + PCIC_DEVCTL_REG, 1932 cfg); 1933 break; 1934 } 1935 1936 /* CSC interrupt routed to PCI */ 1937 cfg = ddi_get8(pcic->cfg_handle, 1938 pcic->cfgaddr + PCIC_DIAG_REG); 1939 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1940 ddi_put8(pcic->cfg_handle, 1941 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1942 1943 #if defined(__i386) || defined(__amd64) 1944 /* 1945 * Some TI chips have 2 cardbus slots(function0 and 1946 * function1), and others may have just 1 cardbus slot. 1947 * The interrupt routing register is shared between the 1948 * 2 functions and can only be accessed through 1949 * function0. Here we check the presence of the second 1950 * cardbus slot and do the right thing. 1951 */ 1952 1953 if (ddi_getlongprop(DDI_DEV_T_ANY, pcic->dip, 1954 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1955 &length) != DDI_PROP_SUCCESS) { 1956 cmn_err(CE_WARN, 1957 "pcic_setup_adapter(), failed to" 1958 " read reg property\n"); 1959 break; 1960 } 1961 1962 bus = PCI_REG_BUS_G(reg->pci_phys_hi); 1963 dev = PCI_REG_DEV_G(reg->pci_phys_hi); 1964 func = PCI_REG_FUNC_G(reg->pci_phys_hi); 1965 kmem_free((caddr_t)reg, length); 1966 1967 if (func != 0) { 1968 break; 1969 } 1970 1971 classcode = (*pci_getl_func)(bus, dev, 1, 1972 PCI_CONF_REVID); 1973 classcode >>= 8; 1974 if (classcode != 0x060700 && 1975 classcode != 0x060500) { 1976 break; 1977 } 1978 1979 /* Parallel PCI interrupts only */ 1980 cfg = ddi_get8(pcic->cfg_handle, 1981 pcic->cfgaddr + PCIC_DEVCTL_REG); 1982 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1983 ddi_put8(pcic->cfg_handle, 1984 pcic->cfgaddr + PCIC_DEVCTL_REG, 1985 cfg); 1986 1987 /* tie INTA and INTB together */ 1988 cfg = ddi_get8(pcic->cfg_handle, 1989 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 1990 cfg |= PCIC_SYSCTL_INTRTIE; 1991 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1992 PCIC_SYSCTL_REG + 3), cfg); 1993 #endif 1994 1995 break; 1996 case PCIC_TI_PCI1410: 1997 cfg = ddi_get8(pcic->cfg_handle, 1998 pcic->cfgaddr + PCIC_DIAG_REG); 1999 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2000 ddi_put8(pcic->cfg_handle, 2001 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2002 break; 2003 case PCIC_TOSHIBA_TOPIC100: 2004 case PCIC_TOSHIBA_TOPIC95: 2005 case PCIC_TOSHIBA_VENDOR: 2006 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2007 PCIC_TOSHIBA_SLOT_CTL_REG); 2008 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 2009 PCIC_TOSHIBA_SCR_SLOTEN); 2010 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 2011 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 2012 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 2013 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 2014 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2015 PCIC_TOSHIBA_INTR_CTL_REG); 2016 switch (pcic->pc_intr_mode) { 2017 case PCIC_INTR_MODE_ISA: 2018 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 2019 ddi_put8(pcic->cfg_handle, 2020 pcic->cfgaddr + 2021 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2022 2023 cfg = ddi_get8(pcic->cfg_handle, 2024 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2025 cfg |= PCIC_FUN_INT_MOD_ISA; 2026 ddi_put8(pcic->cfg_handle, 2027 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2028 cfg); 2029 break; 2030 case PCIC_INTR_MODE_PCI_1: 2031 cfg |= PCIC_TOSHIBA_ICR_SRC; 2032 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 2033 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 2034 ddi_put8(pcic->cfg_handle, 2035 pcic->cfgaddr + 2036 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2037 break; 2038 } 2039 break; 2040 case PCIC_O2MICRO_VENDOR: 2041 cfg32 = ddi_get32(pcic->cfg_handle, 2042 (uint32_t *)(pcic->cfgaddr + 2043 PCIC_O2MICRO_MISC_CTL)); 2044 switch (pcic->pc_intr_mode) { 2045 case PCIC_INTR_MODE_ISA: 2046 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2047 PCIC_O2MICRO_INT_MOD_PCI); 2048 ddi_put32(pcic->cfg_handle, 2049 (uint32_t *)(pcic->cfgaddr + 2050 PCIC_O2MICRO_MISC_CTL), 2051 cfg32); 2052 cfg = ddi_get8(pcic->cfg_handle, 2053 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2054 cfg |= PCIC_FUN_INT_MOD_ISA; 2055 ddi_put8(pcic->cfg_handle, 2056 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2057 cfg); 2058 break; 2059 case PCIC_INTR_MODE_PCI_1: 2060 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2061 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2062 ddi_put32(pcic->cfg_handle, 2063 (uint32_t *)(pcic->cfgaddr + 2064 PCIC_O2MICRO_MISC_CTL), 2065 cfg32); 2066 break; 2067 } 2068 break; 2069 case PCIC_RICOH_VENDOR: 2070 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2071 cfg16 = ddi_get16(pcic->cfg_handle, 2072 (uint16_t *)(pcic->cfgaddr + 2073 PCIC_RICOH_MISC_CTL_2)); 2074 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2075 PCIC_RICOH_FUN_INT_MOD); 2076 ddi_put16(pcic->cfg_handle, 2077 (uint16_t *)(pcic->cfgaddr + 2078 PCIC_RICOH_MISC_CTL_2), 2079 cfg16); 2080 2081 cfg16 = ddi_get16(pcic->cfg_handle, 2082 (uint16_t *)(pcic->cfgaddr + 2083 PCIC_RICOH_MISC_CTL)); 2084 cfg16 |= PCIC_RICOH_SIRQ_EN; 2085 ddi_put16(pcic->cfg_handle, 2086 (uint16_t *)(pcic->cfgaddr + 2087 PCIC_RICOH_MISC_CTL), 2088 cfg16); 2089 2090 cfg = ddi_get8(pcic->cfg_handle, 2091 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2092 cfg |= PCIC_FUN_INT_MOD_ISA; 2093 ddi_put8(pcic->cfg_handle, 2094 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2095 cfg); 2096 } 2097 break; 2098 default: 2099 break; 2100 } /* switch */ 2101 2102 /* 2103 * The default value in the EEPROM (loaded on reset) for 2104 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that 2105 * MFUNC0 is connected to INTA, and MFUNC1 is connected to 2106 * INTB. This applies to all TI CardBus controllers. 2107 */ 2108 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID && 2109 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) { 2110 value = ddi_get32(pcic->cfg_handle, 2111 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG)); 2112 value &= ~0xff; 2113 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr + 2114 PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL); 2115 } 2116 2117 /* setup general card status change interrupt */ 2118 switch (pcic->pc_type) { 2119 case PCIC_TI_PCI1225: 2120 case PCIC_TI_PCI1221: 2121 case PCIC_TI_PCI1031: 2122 case PCIC_TI_PCI1520: 2123 case PCIC_TI_PCI1410: 2124 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2125 PCIC_CHANGE_DEFAULT); 2126 break; 2127 default: 2128 if (pcic->pc_intr_mode == 2129 PCIC_INTR_MODE_PCI_1) { 2130 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2131 PCIC_CHANGE_DEFAULT); 2132 break; 2133 } else { 2134 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2135 PCIC_CHANGE_DEFAULT | 2136 (pcic->pc_sockets[i].pcs_smi << 4)); 2137 break; 2138 } 2139 } 2140 2141 pcic->pc_flags |= PCF_INTRENAB; 2142 2143 /* take card out of RESET */ 2144 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2145 /* turn power off and let CS do this */ 2146 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2147 2148 /* final chip specific initialization */ 2149 switch (pcic->pc_type) { 2150 case PCIC_VADEM: 2151 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2152 PCIC_VC_DELAYENABLE); 2153 pcic->pc_flags |= PCF_DEBOUNCE; 2154 /* FALLTHROUGH */ 2155 case PCIC_I82365SL: 2156 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2157 PCIC_GC_CSC_WRITE); 2158 /* clear any pending interrupts */ 2159 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2160 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2161 break; 2162 /* The 82092 uses PCI config space to enable interrupts */ 2163 case PCIC_INTEL_i82092: 2164 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2165 PCIC_82092_INT_ENABLE); 2166 break; 2167 case PCIC_CL_PD6729: 2168 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2169 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2170 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2171 value | PCIC_CL_TIMER_CLK_DIV); 2172 } 2173 break; 2174 } /* switch */ 2175 2176 #if defined(PCIC_DEBUG) 2177 if (pcic_debug) 2178 cmn_err(CE_CONT, 2179 "socket %d value=%x, flags = %x (%s)\n", 2180 i, value, pcic->pc_sockets[i].pcs_flags, 2181 (pcic->pc_sockets[i].pcs_flags & 2182 PCS_CARD_PRESENT) ? 2183 "card present" : "no card"); 2184 #endif 2185 } 2186 } 2187 2188 /* 2189 * pcic_intr(caddr_t, caddr_t) 2190 * interrupt handler for the PCIC style adapter 2191 * handles all basic interrupts and also checks 2192 * for status changes and notifies the nexus if 2193 * necessary 2194 * 2195 * On PCI bus adapters, also handles all card 2196 * IO interrupts. 2197 */ 2198 /*ARGSUSED*/ 2199 uint32_t 2200 pcic_intr(caddr_t arg1, caddr_t arg2) 2201 { 2202 pcicdev_t *pcic = (pcicdev_t *)arg1; 2203 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2204 uint8_t status; 2205 uint_t io_ints; 2206 2207 #if defined(PCIC_DEBUG) 2208 pcic_err(pcic->dip, 0xf, 2209 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2210 " pc_numsockets=%d \n", 2211 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2212 #endif 2213 2214 if (!(pcic->pc_flags & PCF_ATTACHED)) 2215 return (DDI_INTR_UNCLAIMED); 2216 2217 mutex_enter(&pcic->intr_lock); 2218 2219 if (pcic->pc_flags & PCF_SUSPENDED) { 2220 mutex_exit(&pcic->intr_lock); 2221 return (ret); 2222 } 2223 2224 /* 2225 * need to change to only ACK and touch the slot that 2226 * actually caused the interrupt. Currently everything 2227 * is acked 2228 * 2229 * we need to look at all known sockets to determine 2230 * what might have happened, so step through the list 2231 * of them 2232 */ 2233 2234 /* 2235 * Set the bitmask for IO interrupts to initially include all sockets 2236 */ 2237 io_ints = (1 << pcic->pc_numsockets) - 1; 2238 2239 for (i = 0; i < pcic->pc_numsockets; i++) { 2240 int card_type; 2241 pcic_socket_t *sockp; 2242 int value_cb = 0; 2243 2244 sockp = &pcic->pc_sockets[i]; 2245 /* get the socket's I/O addresses */ 2246 2247 if (sockp->pcs_flags & PCS_WAITING) { 2248 io_ints &= ~(1 << i); 2249 continue; 2250 } 2251 2252 if (sockp->pcs_flags & PCS_CARD_IO) 2253 card_type = IF_IO; 2254 else 2255 card_type = IF_MEMORY; 2256 2257 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2258 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2259 2260 value = pcic_change(pcic, i); 2261 2262 if ((value != 0) || (value_cb != 0)) { 2263 int x = pcic->pc_cb_arg; 2264 2265 ret = DDI_INTR_CLAIMED; 2266 2267 #if defined(PCIC_DEBUG) 2268 pcic_err(pcic->dip, 0x9, 2269 "card_type = %d, value_cb = 0x%x\n", 2270 card_type, 2271 value_cb ? value_cb : 2272 pcic_getcb(pcic, CB_STATUS_EVENT)); 2273 if (pcic_debug) 2274 cmn_err(CE_CONT, 2275 "\tchange on socket %d (%x)\n", i, 2276 value); 2277 #endif 2278 /* find out what happened */ 2279 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2280 2281 /* acknowledge the interrupt */ 2282 if (value_cb) 2283 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2284 2285 if (value) 2286 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2287 value); 2288 2289 if (pcic->pc_callback == NULL) { 2290 /* if not callback handler, nothing to do */ 2291 continue; 2292 } 2293 2294 /* Card Detect */ 2295 if (value & PCIC_CD_DETECT || 2296 value_cb & CB_PS_CCDMASK) { 2297 uint8_t irq; 2298 #if defined(PCIC_DEBUG) 2299 if (pcic_debug) 2300 cmn_err(CE_CONT, 2301 "\tcd_detect: status=%x," 2302 " flags=%x\n", 2303 status, sockp->pcs_flags); 2304 #else 2305 #ifdef lint 2306 if (status == 0) 2307 status++; 2308 #endif 2309 #endif 2310 /* 2311 * Turn off all interrupts for this socket here. 2312 */ 2313 irq = pcic_getb(pcic, sockp->pcs_socket, 2314 PCIC_MANAGEMENT_INT); 2315 irq &= ~PCIC_CHANGE_MASK; 2316 pcic_putb(pcic, sockp->pcs_socket, 2317 PCIC_MANAGEMENT_INT, irq); 2318 2319 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2320 2321 /* 2322 * Put the socket in debouncing state so that 2323 * the leaf driver won't receive interrupts. 2324 * Crucial for handling surprise-removal. 2325 */ 2326 sockp->pcs_flags |= PCS_DEBOUNCING; 2327 2328 if (!sockp->pcs_cd_softint_flg) { 2329 sockp->pcs_cd_softint_flg = 1; 2330 (void) ddi_intr_trigger_softint( 2331 sockp->pcs_cd_softint_hdl, NULL); 2332 } 2333 2334 io_ints &= ~(1 << i); 2335 } /* PCIC_CD_DETECT */ 2336 2337 /* Ready/Change Detect */ 2338 sockp->pcs_state ^= SBM_RDYBSY; 2339 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2340 sockp->pcs_flags |= PCS_READY; 2341 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2342 } 2343 2344 /* Battery Warn Detect */ 2345 if (card_type == IF_MEMORY && 2346 value & PCIC_BW_DETECT && 2347 !(sockp->pcs_state & SBM_BVD2)) { 2348 sockp->pcs_state |= SBM_BVD2; 2349 PC_CALLBACK(pcic->dip, x, 2350 PCE_CARD_BATTERY_WARN, i); 2351 } 2352 2353 /* Battery Dead Detect */ 2354 if (value & PCIC_BD_DETECT) { 2355 /* 2356 * need to work out event if RI not enabled 2357 * and card_type == IF_IO 2358 */ 2359 if (card_type == IF_MEMORY && 2360 !(sockp->pcs_state & SBM_BVD1)) { 2361 sockp->pcs_state |= SBM_BVD1; 2362 PC_CALLBACK(pcic->dip, x, 2363 PCE_CARD_BATTERY_DEAD, 2364 i); 2365 } else { 2366 /* 2367 * information in pin replacement 2368 * register if one is available 2369 */ 2370 PC_CALLBACK(pcic->dip, x, 2371 PCE_CARD_STATUS_CHANGE, 2372 i); 2373 } /* IF_MEMORY */ 2374 } /* PCIC_BD_DETECT */ 2375 } /* if pcic_change */ 2376 /* 2377 * for any controllers that we can detect whether a socket 2378 * had an interrupt for the PC Card, we should sort that out 2379 * here. 2380 */ 2381 } /* for pc_numsockets */ 2382 2383 /* 2384 * If we're on a PCI bus, we may need to cycle through each IO 2385 * interrupt handler that is registered since they all 2386 * share the same interrupt line. 2387 */ 2388 2389 2390 #if defined(PCIC_DEBUG) 2391 pcic_err(pcic->dip, 0xf, 2392 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2393 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2394 #endif 2395 2396 if (io_ints) { 2397 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED) 2398 ret = DDI_INTR_CLAIMED; 2399 } 2400 2401 mutex_exit(&pcic->intr_lock); 2402 2403 #if defined(PCIC_DEBUG) 2404 pcic_err(pcic->dip, 0xf, 2405 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2406 ret, value, DDI_INTR_CLAIMED); 2407 #endif 2408 2409 return (ret); 2410 } 2411 2412 /* 2413 * pcic_change() 2414 * check to see if this socket had a change in state 2415 * by checking the status change register 2416 */ 2417 static int 2418 pcic_change(pcicdev_t *pcic, int socket) 2419 { 2420 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2421 } 2422 2423 /* 2424 * pcic_do_io_intr - calls client interrupt handlers 2425 */ 2426 static int 2427 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2428 { 2429 inthandler_t *tmp; 2430 int ret = DDI_INTR_UNCLAIMED; 2431 2432 #if defined(PCIC_DEBUG) 2433 pcic_err(pcic->dip, 0xf, 2434 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2435 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2436 #endif 2437 2438 if (pcic->irq_top != NULL) { 2439 tmp = pcic->irq_current; 2440 2441 do { 2442 int cur = pcic->irq_current->socket; 2443 pcic_socket_t *sockp = 2444 &pcic->pc_sockets[cur]; 2445 2446 #if defined(PCIC_DEBUG) 2447 pcic_err(pcic->dip, 0xf, 2448 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2449 sockp->pcs_flags, PCS_CARD_PRESENT); 2450 pcic_err(pcic->dip, 0xf, 2451 "\t sockets=%d cur=%d intr=%p arg1=%p " 2452 "arg2=%p\n", 2453 sockets, cur, (void *)pcic->irq_current->intr, 2454 pcic->irq_current->arg1, 2455 pcic->irq_current->arg2); 2456 #endif 2457 if ((sockp->pcs_flags & PCS_CARD_PRESENT) && 2458 !(sockp->pcs_flags & PCS_DEBOUNCING) && 2459 (sockets & (1 << cur))) { 2460 2461 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2462 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2463 ret = DDI_INTR_CLAIMED; 2464 2465 #if defined(PCIC_DEBUG) 2466 pcic_err(pcic->dip, 0xf, 2467 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2468 ret, DDI_INTR_CLAIMED); 2469 #endif 2470 } 2471 2472 2473 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2474 pcic->irq_current = pcic->irq_top; 2475 2476 } while (pcic->irq_current != tmp); 2477 2478 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2479 pcic->irq_current = pcic->irq_top; 2480 2481 } else { 2482 ret = DDI_INTR_UNCLAIMED; 2483 } 2484 2485 #if defined(PCIC_DEBUG) 2486 pcic_err(pcic->dip, 0xf, 2487 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2488 ret, DDI_INTR_CLAIMED); 2489 #endif 2490 2491 return (ret); 2492 2493 } 2494 2495 /* 2496 * pcic_inquire_adapter() 2497 * SocketServices InquireAdapter function 2498 * get characteristics of the physical adapter 2499 */ 2500 /*ARGSUSED*/ 2501 static int 2502 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2503 { 2504 anp_t *anp = ddi_get_driver_private(dip); 2505 pcicdev_t *pcic = anp->an_private; 2506 2507 config->NumSockets = pcic->pc_numsockets; 2508 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2509 config->NumEDCs = 0; 2510 config->AdpCaps = 0; 2511 config->ActiveHigh = 0; 2512 config->ActiveLow = PCIC_AVAIL_IRQS; 2513 config->NumPower = pcic->pc_numpower; 2514 config->power_entry = pcic->pc_power; /* until we resolve this */ 2515 #if defined(PCIC_DEBUG) 2516 if (pcic_debug) { 2517 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2518 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2519 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2520 } 2521 #endif 2522 config->ResourceFlags = 0; 2523 switch (pcic->pc_intr_mode) { 2524 case PCIC_INTR_MODE_PCI_1: 2525 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2526 RES_IRQ_SHAREABLE; 2527 break; 2528 } 2529 return (SUCCESS); 2530 } 2531 2532 /* 2533 * pcic_callback() 2534 * The PCMCIA nexus calls us via this function 2535 * in order to set the callback function we are 2536 * to call the nexus with 2537 */ 2538 /*ARGSUSED*/ 2539 static int 2540 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2541 { 2542 anp_t *anp = ddi_get_driver_private(dip); 2543 pcicdev_t *pcic = anp->an_private; 2544 2545 if (handler != NULL) { 2546 pcic->pc_callback = handler; 2547 pcic->pc_cb_arg = arg; 2548 pcic->pc_flags |= PCF_CALLBACK; 2549 } else { 2550 pcic->pc_callback = NULL; 2551 pcic->pc_cb_arg = 0; 2552 pcic->pc_flags &= ~PCF_CALLBACK; 2553 } 2554 /* 2555 * we're now registered with the nexus 2556 * it is acceptable to do callbacks at this point. 2557 * don't call back from here though since it could block 2558 */ 2559 return (PC_SUCCESS); 2560 } 2561 2562 /* 2563 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2564 * calculate the speed bits from the specified memory speed 2565 * there may be more to do here 2566 */ 2567 2568 static int 2569 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2570 { 2571 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2572 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2573 2574 switch (pcic->pc_type) { 2575 case PCIC_I82365SL: 2576 case PCIC_VADEM: 2577 case PCIC_VADEM_VG469: 2578 default: 2579 /* Intel chip wants it in waitstates */ 2580 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2581 if (speed <= wspeed) 2582 wspeed = 0; 2583 else if (speed <= (wspeed += mhztons(bspeed))) 2584 wspeed = 1; 2585 else if (speed <= (wspeed += mhztons(bspeed))) 2586 wspeed = 2; 2587 else 2588 wspeed = 3; 2589 wspeed <<= 6; /* put in right bit positions */ 2590 break; 2591 2592 case PCIC_INTEL_i82092: 2593 wspeed = SYSMEM_82092_80NS; 2594 if (speed > 80) 2595 wspeed = SYSMEM_82092_100NS; 2596 if (speed > 100) 2597 wspeed = SYSMEM_82092_150NS; 2598 if (speed > 150) 2599 wspeed = SYSMEM_82092_200NS; 2600 if (speed > 200) 2601 wspeed = SYSMEM_82092_250NS; 2602 if (speed > 250) 2603 wspeed = SYSMEM_82092_600NS; 2604 wspeed <<= 5; /* put in right bit positions */ 2605 break; 2606 2607 } /* switch */ 2608 2609 return (wspeed); 2610 } 2611 2612 /* 2613 * These values are taken from the PC Card Standard Electrical Specification. 2614 * Generally the larger value is taken if 2 are possible. 2615 */ 2616 static struct pcic_card_times { 2617 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2618 uint16_t setup; /* Corresponding address setup time. */ 2619 uint16_t width; /* Corresponding width, OE or WE. */ 2620 uint16_t hold; /* Corresponding data or address hold time. */ 2621 } pcic_card_times[] = { 2622 2623 /* 2624 * Note: The rounded up times for 250, 200 & 150 have been increased 2625 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2626 * See BugID 00663. 2627 */ 2628 2629 /* 2630 * Rounded up times Original times from 2631 * that add up to the the PCMCIA Spec. 2632 * cycle time. 2633 */ 2634 {600, 180, 370, 140}, /* 100, 300, 70 */ 2635 {400, 120, 300, 90}, /* Made this one up */ 2636 {250, 100, 190, 70}, /* 30, 150, 30 */ 2637 {200, 80, 170, 70}, /* 20, 120, 30 */ 2638 {150, 50, 110, 40}, /* 20, 80, 20 */ 2639 {100, 40, 80, 40}, /* 10, 60, 15 */ 2640 {0, 10, 60, 15} /* 10, 60, 15 */ 2641 }; 2642 2643 /* 2644 * pcic_set_cdtimers 2645 * This is specific to several Cirrus Logic chips 2646 */ 2647 static void 2648 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2649 { 2650 int cmd, set, rec, offset, clk_pulse; 2651 struct pcic_card_times *ctp; 2652 2653 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2654 offset = 3; 2655 else 2656 offset = 0; 2657 2658 clk_pulse = mhztons(pcic->bus_speed); 2659 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++) 2660 ; 2661 2662 /* 2663 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2664 */ 2665 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2666 if (set < 0) 2667 set = 0; 2668 2669 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2670 if (cmd < 0) 2671 cmd = 0; 2672 2673 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2674 if (rec < 0) 2675 rec = 0; 2676 2677 #if defined(PCIC_DEBUG) 2678 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2679 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2680 (unsigned)speed, offset == 3 ? 1 : 0, 2681 ctp->cycle, clk_pulse, cmd, set, rec); 2682 #endif 2683 2684 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2685 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2686 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2687 } 2688 2689 /* 2690 * pcic_set_window 2691 * essentially the same as the Socket Services specification 2692 * We use socket and not adapter since they are identifiable 2693 * but the rest is the same 2694 * 2695 * dip pcic driver's device information 2696 * window parameters for the request 2697 */ 2698 static int 2699 pcic_set_window(dev_info_t *dip, set_window_t *window) 2700 { 2701 anp_t *anp = ddi_get_driver_private(dip); 2702 pcicdev_t *pcic = anp->an_private; 2703 int select; 2704 int socket, pages, which, ret; 2705 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2706 ra_return_t res; 2707 ndi_ra_request_t req; 2708 uint32_t base = window->base; 2709 2710 #if defined(PCIC_DEBUG) 2711 if (pcic_debug) { 2712 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2713 cmn_err(CE_CONT, 2714 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2715 window->window, window->socket, window->WindowSize, 2716 window->speed); 2717 cmn_err(CE_CONT, 2718 "\tbase=%x, state=%x\n", (unsigned)window->base, 2719 (unsigned)window->state); 2720 } 2721 #endif 2722 2723 /* 2724 * do some basic sanity checking on what we support 2725 * we don't do paged mode 2726 */ 2727 if (window->state & WS_PAGED) { 2728 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2729 return (BAD_ATTRIBUTE); 2730 } 2731 2732 /* 2733 * we don't care about previous mappings. 2734 * Card Services will deal with that so don't 2735 * even check 2736 */ 2737 2738 socket = window->socket; 2739 2740 if (!(window->state & WS_IO)) { 2741 int win, tmp; 2742 pcs_memwin_t *memp; 2743 #if defined(PCIC_DEBUG) 2744 if (pcic_debug) 2745 cmn_err(CE_CONT, "\twindow type is memory\n"); 2746 #endif 2747 /* this is memory window mapping */ 2748 win = window->window % PCIC_NUMWINSOCK; 2749 tmp = window->window / PCIC_NUMWINSOCK; 2750 2751 /* only windows 2-6 can do memory mapping */ 2752 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2753 cmn_err(CE_CONT, 2754 "\tattempt to map to non-mem window\n"); 2755 return (BAD_WINDOW); 2756 } 2757 2758 if (window->WindowSize == 0) 2759 window->WindowSize = MEM_MIN; 2760 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2761 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2762 return (BAD_SIZE); 2763 } 2764 2765 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2766 2767 memp = &sockp->pcs_windows[win].mem; 2768 memp->pcw_speed = window->speed; 2769 2770 win -= PCIC_IOWINDOWS; /* put in right range */ 2771 2772 if (window->WindowSize != memp->pcw_len) 2773 which = memp->pcw_len; 2774 else 2775 which = 0; 2776 2777 if (window->state & WS_ENABLED) { 2778 uint32_t wspeed; 2779 #if defined(PCIC_DEBUG) 2780 if (pcic_debug) { 2781 cmn_err(CE_CONT, 2782 "\tbase=%x, win=%d\n", (unsigned)base, 2783 win); 2784 if (which) 2785 cmn_err(CE_CONT, 2786 "\tneed to remap window\n"); 2787 } 2788 #endif 2789 2790 if (which && (memp->pcw_status & PCW_MAPPED)) { 2791 ddi_regs_map_free(&memp->pcw_handle); 2792 res.ra_addr_lo = memp->pcw_base; 2793 res.ra_len = memp->pcw_len; 2794 (void) pcmcia_free_mem(memp->res_dip, &res); 2795 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2796 memp->pcw_hostmem = NULL; 2797 memp->pcw_base = NULL; 2798 memp->pcw_len = 0; 2799 } 2800 2801 which = window->WindowSize >> PAGE_SHIFT; 2802 2803 if (!(memp->pcw_status & PCW_MAPPED)) { 2804 ret = 0; 2805 2806 memp->pcw_base = base; 2807 bzero(&req, sizeof (req)); 2808 req.ra_len = which << PAGE_SHIFT; 2809 req.ra_addr = (uint64_t)memp->pcw_base; 2810 req.ra_boundbase = pcic->pc_base; 2811 req.ra_boundlen = pcic->pc_bound; 2812 req.ra_flags = (memp->pcw_base ? 2813 NDI_RA_ALLOC_SPECIFIED : 0) | 2814 NDI_RA_ALLOC_BOUNDED; 2815 req.ra_align_mask = 2816 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2817 #if defined(PCIC_DEBUG) 2818 pcic_err(dip, 8, 2819 "\tlen 0x%"PRIx64 2820 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2821 " blen 0x%"PRIx64" flags 0x%x" 2822 " algn 0x%"PRIx64"\n", 2823 req.ra_len, req.ra_addr, 2824 req.ra_boundbase, 2825 req.ra_boundlen, req.ra_flags, 2826 req.ra_align_mask); 2827 #endif 2828 2829 ret = pcmcia_alloc_mem(dip, &req, &res, 2830 &memp->res_dip); 2831 if (ret == DDI_FAILURE) { 2832 mutex_exit(&pcic->pc_lock); 2833 cmn_err(CE_WARN, 2834 "\tpcmcia_alloc_mem() failed\n"); 2835 return (BAD_SIZE); 2836 } 2837 memp->pcw_base = res.ra_addr_lo; 2838 base = memp->pcw_base; 2839 2840 #if defined(PCIC_DEBUG) 2841 if (pcic_debug) 2842 cmn_err(CE_CONT, 2843 "\tsetwindow: new base=%x\n", 2844 (unsigned)memp->pcw_base); 2845 #endif 2846 memp->pcw_len = window->WindowSize; 2847 2848 which = pcmcia_map_reg(pcic->dip, 2849 window->child, 2850 &res, 2851 (uint32_t)(window->state & 2852 0xffff) | 2853 (window->socket << 16), 2854 (caddr_t *)&memp->pcw_hostmem, 2855 &memp->pcw_handle, 2856 &window->attr, NULL); 2857 2858 if (which != DDI_SUCCESS) { 2859 2860 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2861 "failed\n"); 2862 2863 res.ra_addr_lo = memp->pcw_base; 2864 res.ra_len = memp->pcw_len; 2865 (void) pcmcia_free_mem(memp->res_dip, 2866 &res); 2867 2868 mutex_exit(&pcic->pc_lock); 2869 2870 return (BAD_WINDOW); 2871 } 2872 memp->pcw_status |= PCW_MAPPED; 2873 #if defined(PCIC_DEBUG) 2874 if (pcic_debug) 2875 cmn_err(CE_CONT, 2876 "\tmap=%x, hostmem=%p\n", 2877 which, 2878 (void *)memp->pcw_hostmem); 2879 #endif 2880 } else { 2881 base = memp->pcw_base; 2882 } 2883 2884 /* report the handle back to caller */ 2885 window->handle = memp->pcw_handle; 2886 2887 #if defined(PCIC_DEBUG) 2888 if (pcic_debug) { 2889 cmn_err(CE_CONT, 2890 "\twindow mapped to %x@%x len=%d\n", 2891 (unsigned)window->base, 2892 (unsigned)memp->pcw_base, 2893 memp->pcw_len); 2894 } 2895 #endif 2896 2897 /* find the register set offset */ 2898 select = win * PCIC_MEM_1_OFFSET; 2899 #if defined(PCIC_DEBUG) 2900 if (pcic_debug) 2901 cmn_err(CE_CONT, "\tselect=%x\n", select); 2902 #endif 2903 2904 /* 2905 * at this point, the register window indicator has 2906 * been converted to be an offset from the first 2907 * set of registers that are used for programming 2908 * the window mapping and the offset used to select 2909 * the correct set of registers to access the 2910 * specified socket. This allows basing everything 2911 * off the _0 window 2912 */ 2913 2914 /* map the physical page base address */ 2915 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2916 which |= (window->speed <= MEM_SPEED_MIN) ? 2917 SYSMEM_ZERO_WAIT : 0; 2918 2919 /* need to select register set */ 2920 select = PCIC_MEM_1_OFFSET * win; 2921 2922 pcic_putb(pcic, socket, 2923 PCIC_SYSMEM_0_STARTLOW + select, 2924 SYSMEM_LOW(base)); 2925 pcic_putb(pcic, socket, 2926 PCIC_SYSMEM_0_STARTHI + select, 2927 SYSMEM_HIGH(base) | which); 2928 2929 /* 2930 * Some adapters can decode window addresses greater 2931 * than 16-bits worth, so handle them here. 2932 */ 2933 switch (pcic->pc_type) { 2934 case PCIC_INTEL_i82092: 2935 pcic_putb(pcic, socket, 2936 PCIC_82092_CPAGE, 2937 SYSMEM_EXT(base)); 2938 break; 2939 case PCIC_CL_PD6729: 2940 case PCIC_CL_PD6730: 2941 clext_reg_write(pcic, socket, 2942 PCIC_CLEXT_MMAP0_UA + win, 2943 SYSMEM_EXT(base)); 2944 break; 2945 case PCIC_TI_PCI1130: 2946 /* 2947 * Note that the TI chip has one upper byte 2948 * per socket so all windows get bound to a 2949 * 16MB segment. This must be detected and 2950 * handled appropriately. We can detect that 2951 * it is done by seeing if the pc_base has 2952 * changed and changing when the register 2953 * is first set. This will force the bounds 2954 * to be correct. 2955 */ 2956 if (pcic->pc_bound == 0xffffffff) { 2957 pcic_putb(pcic, socket, 2958 PCIC_TI_WINDOW_PAGE_PCI, 2959 SYSMEM_EXT(base)); 2960 pcic->pc_base = SYSMEM_EXT(base) << 24; 2961 pcic->pc_bound = 0x1000000; 2962 } 2963 break; 2964 case PCIC_TI_PCI1031: 2965 case PCIC_TI_PCI1131: 2966 case PCIC_TI_PCI1250: 2967 case PCIC_TI_PCI1225: 2968 case PCIC_TI_PCI1221: 2969 case PCIC_SMC_34C90: 2970 case PCIC_CL_PD6832: 2971 case PCIC_RICOH_RL5C466: 2972 case PCIC_TI_PCI1410: 2973 case PCIC_ENE_1410: 2974 case PCIC_TI_PCI1510: 2975 case PCIC_TI_PCI1520: 2976 case PCIC_O2_OZ6912: 2977 case PCIC_TI_PCI1420: 2978 case PCIC_ENE_1420: 2979 case PCIC_TI_VENDOR: 2980 case PCIC_TOSHIBA_TOPIC100: 2981 case PCIC_TOSHIBA_TOPIC95: 2982 case PCIC_TOSHIBA_VENDOR: 2983 case PCIC_RICOH_VENDOR: 2984 case PCIC_O2MICRO_VENDOR: 2985 pcic_putb(pcic, socket, 2986 PCIC_YENTA_MEM_PAGE + win, 2987 SYSMEM_EXT(base)); 2988 break; 2989 default: 2990 cmn_err(CE_NOTE, "pcic_set_window: unknown " 2991 "cardbus vendor:0x%X\n", 2992 pcic->pc_type); 2993 pcic_putb(pcic, socket, 2994 PCIC_YENTA_MEM_PAGE + win, 2995 SYSMEM_EXT(base)); 2996 2997 break; 2998 } /* switch */ 2999 3000 /* 3001 * specify the length of the mapped range 3002 * we convert to pages (rounding up) so that 3003 * the hardware gets the right thing 3004 */ 3005 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 3006 3007 /* 3008 * Setup this window's timing. 3009 */ 3010 switch (pcic->pc_type) { 3011 case PCIC_CL_PD6729: 3012 case PCIC_CL_PD6730: 3013 case PCIC_CL_PD6710: 3014 case PCIC_CL_PD6722: 3015 wspeed = SYSMEM_CLTIMER_SET_0; 3016 pcic_set_cdtimers(pcic, socket, 3017 window->speed, 3018 wspeed); 3019 break; 3020 3021 case PCIC_INTEL_i82092: 3022 default: 3023 wspeed = pcic_calc_speed(pcic, window->speed); 3024 break; 3025 } /* switch */ 3026 3027 #if defined(PCIC_DEBUG) 3028 if (pcic_debug) 3029 cmn_err(CE_CONT, 3030 "\twindow %d speed bits = %x for " 3031 "%dns\n", 3032 win, (unsigned)wspeed, window->speed); 3033 #endif 3034 3035 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 3036 SYSMEM_LOW(base + 3037 (pages * PCIC_PAGE)-1)); 3038 3039 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 3040 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 3041 wspeed); 3042 3043 /* 3044 * now map the card's memory pages - we start with page 3045 * 0 3046 * we also default to AM -- set page might change it 3047 */ 3048 base = memp->pcw_base; 3049 pcic_putb(pcic, socket, 3050 PCIC_CARDMEM_0_LOW + select, 3051 CARDMEM_LOW(0 - (uint32_t)base)); 3052 3053 pcic_putb(pcic, socket, 3054 PCIC_CARDMEM_0_HI + select, 3055 CARDMEM_HIGH(0 - (uint32_t)base) | 3056 CARDMEM_REG_ACTIVE); 3057 3058 /* 3059 * enable the window even though redundant 3060 * and SetPage may do it again. 3061 */ 3062 select = pcic_getb(pcic, socket, 3063 PCIC_MAPPING_ENABLE); 3064 select |= SYSMEM_WINDOW(win); 3065 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3066 memp->pcw_offset = 0; 3067 memp->pcw_status |= PCW_ENABLED; 3068 } else { 3069 /* 3070 * not only do we unmap the memory, the 3071 * window has been turned off. 3072 */ 3073 if (which && memp->pcw_status & PCW_MAPPED) { 3074 ddi_regs_map_free(&memp->pcw_handle); 3075 res.ra_addr_lo = memp->pcw_base; 3076 res.ra_len = memp->pcw_len; 3077 (void) pcmcia_free_mem(memp->res_dip, &res); 3078 memp->pcw_hostmem = NULL; 3079 memp->pcw_status &= ~PCW_MAPPED; 3080 } 3081 3082 /* disable current mapping */ 3083 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3084 select &= ~SYSMEM_WINDOW(win); 3085 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3086 memp->pcw_status &= ~PCW_ENABLED; 3087 } 3088 memp->pcw_len = window->WindowSize; 3089 window->handle = memp->pcw_handle; 3090 #if defined(PCIC_DEBUG) 3091 if (pcic_debug) 3092 xxdmp_all_regs(pcic, window->socket, -1); 3093 #endif 3094 } else { 3095 /* 3096 * This is a request for an IO window 3097 */ 3098 int win, tmp; 3099 pcs_iowin_t *winp; 3100 /* I/O windows */ 3101 #if defined(PCIC_DEBUG) 3102 if (pcic_debug) 3103 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3104 #endif 3105 3106 /* only windows 0 and 1 can do I/O */ 3107 win = window->window % PCIC_NUMWINSOCK; 3108 tmp = window->window / PCIC_NUMWINSOCK; 3109 3110 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3111 cmn_err(CE_WARN, 3112 "\twindow is out of range (%d)\n", 3113 window->window); 3114 return (BAD_WINDOW); 3115 } 3116 3117 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3118 3119 winp = &sockp->pcs_windows[win].io; 3120 winp->pcw_speed = window->speed; 3121 if (window->WindowSize != 1 && window->WindowSize & 1) { 3122 /* we don't want an odd-size window */ 3123 window->WindowSize++; 3124 } 3125 winp->pcw_len = window->WindowSize; 3126 3127 if (window->state & WS_ENABLED) { 3128 if (winp->pcw_status & PCW_MAPPED) { 3129 ddi_regs_map_free(&winp->pcw_handle); 3130 res.ra_addr_lo = winp->pcw_base; 3131 res.ra_len = winp->pcw_len; 3132 (void) pcmcia_free_io(winp->res_dip, &res); 3133 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3134 } 3135 3136 /* 3137 * if the I/O address wasn't allocated, allocate 3138 * it now. If it was allocated, it better 3139 * be free to use. 3140 * The winp->pcw_offset value is set and used 3141 * later on if the particular adapter 3142 * that we're running on has the ability 3143 * to translate IO accesses to the card 3144 * (such as some adapters in the Cirrus 3145 * Logic family). 3146 */ 3147 winp->pcw_offset = 0; 3148 3149 /* 3150 * Setup the request parameters for the 3151 * requested base and length. If 3152 * we're on an adapter that has 3153 * IO window offset registers, then 3154 * we don't need a specific base 3155 * address, just a length, and then 3156 * we'll cause the correct IO address 3157 * to be generated on the socket by 3158 * setting up the IO window offset 3159 * registers. 3160 * For adapters that support this capability, we 3161 * always use the IO window offset registers, 3162 * even if the passed base/length would be in 3163 * range. 3164 */ 3165 base = window->base; 3166 bzero(&req, sizeof (req)); 3167 req.ra_len = window->WindowSize; 3168 3169 req.ra_addr = (uint64_t) 3170 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3171 req.ra_flags = (req.ra_addr) ? 3172 NDI_RA_ALLOC_SPECIFIED : 0; 3173 3174 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3175 /* need to rethink this */ 3176 req.ra_boundbase = pcic->pc_iobase; 3177 req.ra_boundlen = pcic->pc_iobound; 3178 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3179 3180 #if defined(PCIC_DEBUG) 3181 pcic_err(dip, 8, 3182 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3183 "bbase 0x%"PRIx64 3184 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3185 PRIx64"\n", 3186 req.ra_len, (uint64_t)req.ra_addr, 3187 req.ra_boundbase, 3188 req.ra_boundlen, req.ra_flags, 3189 req.ra_align_mask); 3190 #endif 3191 3192 /* 3193 * Try to allocate the space. If we fail this, 3194 * return the appropriate error depending 3195 * on whether the caller specified a 3196 * specific base address or not. 3197 */ 3198 if (pcmcia_alloc_io(dip, &req, &res, 3199 &winp->res_dip) == DDI_FAILURE) { 3200 winp->pcw_status &= ~PCW_ENABLED; 3201 mutex_exit(&pcic->pc_lock); 3202 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3203 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3204 "bbase 0x%" PRIx64 3205 "blen 0x%" PRIx64 "flags 0x%x" 3206 "algn 0x%" PRIx64 "\n", 3207 req.ra_len, req.ra_addr, 3208 req.ra_boundbase, 3209 req.ra_boundlen, req.ra_flags, 3210 req.ra_align_mask); 3211 3212 return (base?BAD_BASE:BAD_SIZE); 3213 } /* pcmcia_alloc_io */ 3214 3215 /* 3216 * Don't change the original base. Either we use 3217 * the offset registers below (PCF_IO_REMAP is set) 3218 * or it was allocated correctly anyway. 3219 */ 3220 winp->pcw_base = res.ra_addr_lo; 3221 3222 #if defined(PCIC_DEBUG) 3223 pcic_err(dip, 8, 3224 "\tsetwindow: new base=%x orig base 0x%x\n", 3225 (unsigned)winp->pcw_base, base); 3226 #endif 3227 3228 if ((which = pcmcia_map_reg(pcic->dip, 3229 window->child, 3230 &res, 3231 (uint32_t)(window->state & 3232 0xffff) | 3233 (window->socket << 16), 3234 (caddr_t *)&winp->pcw_hostmem, 3235 &winp->pcw_handle, 3236 &window->attr, 3237 base)) != DDI_SUCCESS) { 3238 3239 cmn_err(CE_WARN, "pcmcia_map_reg()" 3240 "failed\n"); 3241 3242 res.ra_addr_lo = winp->pcw_base; 3243 res.ra_len = winp->pcw_len; 3244 (void) pcmcia_free_io(winp->res_dip, 3245 &res); 3246 3247 mutex_exit(&pcic->pc_lock); 3248 return (BAD_WINDOW); 3249 } 3250 3251 window->handle = winp->pcw_handle; 3252 winp->pcw_status |= PCW_MAPPED; 3253 3254 /* find the register set offset */ 3255 select = win * PCIC_IO_OFFSET; 3256 3257 #if defined(PCIC_DEBUG) 3258 if (pcic_debug) { 3259 cmn_err(CE_CONT, 3260 "\tenable: window=%d, select=%x, " 3261 "base=%x, handle=%p\n", 3262 win, select, 3263 (unsigned)window->base, 3264 (void *)window->handle); 3265 } 3266 #endif 3267 /* 3268 * at this point, the register window indicator has 3269 * been converted to be an offset from the first 3270 * set of registers that are used for programming 3271 * the window mapping and the offset used to select 3272 * the correct set of registers to access the 3273 * specified socket. This allows basing everything 3274 * off the _0 window 3275 */ 3276 3277 /* map the I/O base in */ 3278 pcic_putb(pcic, socket, 3279 PCIC_IO_ADDR_0_STARTLOW + select, 3280 LOW_BYTE((uint32_t)winp->pcw_base)); 3281 pcic_putb(pcic, socket, 3282 PCIC_IO_ADDR_0_STARTHI + select, 3283 HIGH_BYTE((uint32_t)winp->pcw_base)); 3284 3285 pcic_putb(pcic, socket, 3286 PCIC_IO_ADDR_0_STOPLOW + select, 3287 LOW_BYTE((uint32_t)winp->pcw_base + 3288 window->WindowSize - 1)); 3289 pcic_putb(pcic, socket, 3290 PCIC_IO_ADDR_0_STOPHI + select, 3291 HIGH_BYTE((uint32_t)winp->pcw_base + 3292 window->WindowSize - 1)); 3293 3294 /* 3295 * We've got the requested IO space, now see if we 3296 * need to adjust the IO window offset registers 3297 * so that the correct IO address is generated 3298 * at the socket. If this window doesn't have 3299 * this capability, then we're all done setting 3300 * up the IO resources. 3301 */ 3302 if (pcic->pc_flags & PCF_IO_REMAP) { 3303 3304 3305 /* 3306 * Note that only 16 bits are used to program 3307 * the registers but leave 32 bits on pcw_offset 3308 * so that we can generate the original base 3309 * in get_window() 3310 */ 3311 winp->pcw_offset = (base - winp->pcw_base); 3312 3313 pcic_putb(pcic, socket, 3314 PCIC_IO_OFFSET_LOW + 3315 (win * PCIC_IO_OFFSET_OFFSET), 3316 winp->pcw_offset & 0x0ff); 3317 pcic_putb(pcic, socket, 3318 PCIC_IO_OFFSET_HI + 3319 (win * PCIC_IO_OFFSET_OFFSET), 3320 (winp->pcw_offset >> 8) & 0x0ff); 3321 3322 } /* PCF_IO_REMAP */ 3323 3324 /* now get the other details (size, etc) right */ 3325 3326 /* 3327 * Set the data size control bits here. Most of the 3328 * adapters will ignore IOMEM_16BIT when 3329 * IOMEM_IOCS16 is set, except for the Intel 3330 * 82092, which only pays attention to the 3331 * IOMEM_16BIT bit. Sigh... Intel can't even 3332 * make a proper clone of their own chip. 3333 * The 82092 also apparently can't set the timing 3334 * of I/O windows. 3335 */ 3336 which = (window->state & WS_16BIT) ? 3337 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3338 3339 switch (pcic->pc_type) { 3340 case PCIC_CL_PD6729: 3341 case PCIC_CL_PD6730: 3342 case PCIC_CL_PD6710: 3343 case PCIC_CL_PD6722: 3344 case PCIC_CL_PD6832: 3345 /* 3346 * Select Timer Set 1 - this will take 3347 * effect when the PCIC_IO_CONTROL 3348 * register is written to later on; 3349 * the call to pcic_set_cdtimers 3350 * just sets up the timer itself. 3351 */ 3352 which |= IOMEM_CLTIMER_SET_1; 3353 pcic_set_cdtimers(pcic, socket, 3354 window->speed, 3355 IOMEM_CLTIMER_SET_1); 3356 which |= IOMEM_IOCS16; 3357 break; 3358 case PCIC_TI_PCI1031: 3359 3360 if (window->state & WS_16BIT) 3361 which |= IOMEM_WAIT16; 3362 3363 break; 3364 case PCIC_TI_PCI1130: 3365 3366 if (window->state & WS_16BIT) 3367 which |= IOMEM_WAIT16; 3368 3369 break; 3370 case PCIC_INTEL_i82092: 3371 break; 3372 default: 3373 if (window->speed > 3374 mhztons(pcic->bus_speed) * 3) 3375 which |= IOMEM_WAIT16; 3376 #ifdef notdef 3377 if (window->speed < 3378 mhztons(pcic->bus_speed) * 6) 3379 which |= IOMEM_ZERO_WAIT; 3380 #endif 3381 break; 3382 } /* switch (pc_type) */ 3383 3384 /* 3385 * Setup the data width and timing 3386 */ 3387 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3388 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3389 select |= IOMEM_SETWIN(win, which); 3390 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3391 3392 /* 3393 * Enable the IO window 3394 */ 3395 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3396 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3397 select | IOMEM_WINDOW(win)); 3398 3399 winp->pcw_status |= PCW_ENABLED; 3400 3401 #if defined(PCIC_DEBUG) 3402 if (pcic_debug) { 3403 cmn_err(CE_CONT, 3404 "\twhich = %x, select = %x (%x)\n", 3405 which, select, 3406 IOMEM_SETWIN(win, which)); 3407 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3408 } 3409 #endif 3410 } else { 3411 /* 3412 * not only do we unmap the IO space, the 3413 * window has been turned off. 3414 */ 3415 if (winp->pcw_status & PCW_MAPPED) { 3416 ddi_regs_map_free(&winp->pcw_handle); 3417 res.ra_addr_lo = winp->pcw_base; 3418 res.ra_len = winp->pcw_len; 3419 (void) pcmcia_free_io(winp->res_dip, &res); 3420 winp->pcw_status &= ~PCW_MAPPED; 3421 } 3422 3423 /* disable current mapping */ 3424 select = pcic_getb(pcic, socket, 3425 PCIC_MAPPING_ENABLE); 3426 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3427 select &= ~IOMEM_WINDOW(win)); 3428 winp->pcw_status &= ~PCW_ENABLED; 3429 3430 winp->pcw_base = 0; 3431 winp->pcw_len = 0; 3432 winp->pcw_offset = 0; 3433 window->base = 0; 3434 /* now make sure we don't accidentally re-enable */ 3435 /* find the register set offset */ 3436 select = win * PCIC_IO_OFFSET; 3437 pcic_putb(pcic, socket, 3438 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3439 pcic_putb(pcic, socket, 3440 PCIC_IO_ADDR_0_STARTHI + select, 0); 3441 pcic_putb(pcic, socket, 3442 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3443 pcic_putb(pcic, socket, 3444 PCIC_IO_ADDR_0_STOPHI + select, 0); 3445 } 3446 } 3447 mutex_exit(&pcic->pc_lock); 3448 3449 return (SUCCESS); 3450 } 3451 3452 /* 3453 * pcic_card_state() 3454 * compute the instantaneous Card State information 3455 */ 3456 static int 3457 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3458 { 3459 int value, result; 3460 #if defined(PCIC_DEBUG) 3461 int orig_value; 3462 #endif 3463 3464 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3465 3466 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3467 3468 #if defined(PCIC_DEBUG) 3469 orig_value = value; 3470 if (pcic_debug >= 8) 3471 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3472 (void *)sockp, 3473 value, 3474 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3475 sockp->pcs_socket); 3476 #endif 3477 /* 3478 * Lie to socket services if we are not ready. 3479 * This is when we are starting up or during debounce timeouts 3480 * or if the card is a cardbus card. 3481 */ 3482 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3483 !sockp->pcs_debounce_id && 3484 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3485 result = SBM_CD; 3486 3487 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3488 result |= SBM_WP; 3489 if (value & PCIC_POWER_ON) { 3490 if (value & PCIC_READY) 3491 result |= SBM_RDYBSY; 3492 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3493 if (value & PCIC_BVD1) 3494 result |= SBM_BVD1; 3495 if (value & PCIC_BVD2) 3496 result |= SBM_BVD2; 3497 } 3498 } else 3499 result = 0; 3500 3501 mutex_exit(&pcic->pc_lock); 3502 3503 #if defined(PCIC_DEBUG) 3504 pcic_err(pcic->dip, 8, 3505 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3506 (void *) sockp, orig_value, 3507 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3508 sockp->pcs_socket, result); 3509 #endif 3510 3511 return (result); 3512 } 3513 3514 /* 3515 * pcic_set_page() 3516 * SocketServices SetPage function 3517 * set the page of PC Card memory that should be in the mapped 3518 * window 3519 */ 3520 /*ARGSUSED*/ 3521 static int 3522 pcic_set_page(dev_info_t *dip, set_page_t *page) 3523 { 3524 anp_t *anp = ddi_get_driver_private(dip); 3525 pcicdev_t *pcic = anp->an_private; 3526 int select; 3527 int which, socket, window; 3528 uint32_t base; 3529 pcs_memwin_t *memp; 3530 3531 /* get real socket/window numbers */ 3532 window = page->window % PCIC_NUMWINSOCK; 3533 socket = page->window / PCIC_NUMWINSOCK; 3534 3535 #if defined(PCIC_DEBUG) 3536 if (pcic_debug) { 3537 cmn_err(CE_CONT, 3538 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3539 window, socket, page->page); 3540 } 3541 #endif 3542 /* only windows 2-6 work on memory */ 3543 if (window < PCIC_IOWINDOWS) 3544 return (BAD_WINDOW); 3545 3546 /* only one page supported (but any size) */ 3547 if (page->page != 0) 3548 return (BAD_PAGE); 3549 3550 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3551 3552 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3553 window -= PCIC_IOWINDOWS; 3554 3555 #if defined(PCIC_DEBUG) 3556 if (pcic_debug) 3557 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3558 (uint32_t)memp->pcw_base, 3559 (void *)memp->pcw_hostmem, memp->pcw_len); 3560 #endif 3561 3562 /* window must be enabled */ 3563 if (!(memp->pcw_status & PCW_ENABLED)) 3564 return (BAD_ATTRIBUTE); 3565 3566 /* find the register set offset */ 3567 select = window * PCIC_MEM_1_OFFSET; 3568 #if defined(PCIC_DEBUG) 3569 if (pcic_debug) 3570 cmn_err(CE_CONT, "\tselect=%x\n", select); 3571 #endif 3572 3573 /* 3574 * now map the card's memory pages - we start with page 0 3575 */ 3576 3577 which = 0; /* assume simple case */ 3578 if (page->state & PS_ATTRIBUTE) { 3579 which |= CARDMEM_REG_ACTIVE; 3580 memp->pcw_status |= PCW_ATTRIBUTE; 3581 } else { 3582 memp->pcw_status &= ~PCW_ATTRIBUTE; 3583 } 3584 3585 /* 3586 * if caller says Write Protect, enforce it. 3587 */ 3588 if (page->state & PS_WP) { 3589 which |= CARDMEM_WRITE_PROTECT; 3590 memp->pcw_status |= PCW_WP; 3591 } else { 3592 memp->pcw_status &= ~PCW_WP; 3593 } 3594 #if defined(PCIC_DEBUG) 3595 if (pcic_debug) { 3596 cmn_err(CE_CONT, "\tmemory type = %s\n", 3597 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3598 if (which & CARDMEM_WRITE_PROTECT) 3599 cmn_err(CE_CONT, "\twrite protect\n"); 3600 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3601 (unsigned)page->offset, 3602 (unsigned)memp->pcw_base, 3603 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3604 } 3605 #endif 3606 /* address computation based on 64MB range and not larger */ 3607 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3608 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3609 CARDMEM_LOW((int)page->offset - (int)base)); 3610 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3611 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3612 CARDMEM_HIGH((int)page->offset - base) | which); 3613 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3614 3615 /* 3616 * while not really necessary, this just makes sure 3617 * nothing turned the window off behind our backs 3618 */ 3619 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3620 which |= SYSMEM_WINDOW(window); 3621 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3622 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3623 3624 memp->pcw_offset = (off_t)page->offset; 3625 3626 #if defined(PCIC_DEBUG) 3627 if (pcic_debug) { 3628 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3629 (void *)memp->pcw_hostmem, 3630 (uint32_t)*memp->pcw_hostmem); 3631 3632 xxdmp_all_regs(pcic, socket, -1); 3633 3634 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3635 (void *)memp->pcw_hostmem, 3636 (uint32_t)*memp->pcw_hostmem); 3637 } 3638 #endif 3639 3640 if (which & PCW_ATTRIBUTE) 3641 pcic_mswait(pcic, socket, 2); 3642 3643 mutex_exit(&pcic->pc_lock); 3644 3645 return (SUCCESS); 3646 } 3647 3648 /* 3649 * pcic_set_vcc_level() 3650 * 3651 * set voltage based on adapter information 3652 * 3653 * this routine implements a limited solution for support of 3.3v cards. 3654 * the general solution, which would fully support the pcmcia spec 3655 * as far as allowing client drivers to request which voltage levels 3656 * to be set, requires more framework support and driver changes - ess 3657 */ 3658 static int 3659 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3660 { 3661 uint32_t socket_present_state; 3662 3663 #if defined(PCIC_DEBUG) 3664 if (pcic_debug) { 3665 cmn_err(CE_CONT, 3666 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3667 (void *)pcic, socket->VccLevel); 3668 } 3669 #endif 3670 3671 /* 3672 * check VccLevel 3673 * if this is zero, power is being turned off 3674 * if it is non-zero, power is being turned on. 3675 */ 3676 if (socket->VccLevel == 0) { 3677 return (0); 3678 } 3679 3680 /* 3681 * range checking for sanity's sake 3682 */ 3683 if (socket->VccLevel >= pcic->pc_numpower) { 3684 return (BAD_VCC); 3685 } 3686 3687 switch (pcic->pc_io_type) { 3688 /* 3689 * Yenta-compliant adapters have vcc info in the extended registers 3690 * Other adapters can be added as needed, but the 'default' case 3691 * has been left as it was previously so as not to break existing 3692 * adapters. 3693 */ 3694 case PCIC_IO_TYPE_YENTA: 3695 /* 3696 * Here we ignore the VccLevel passed in and read the 3697 * card type from the adapter socket present state register 3698 */ 3699 socket_present_state = 3700 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3701 PCIC_PRESENT_STATE_REG)); 3702 #if defined(PCIC_DEBUG) 3703 if (pcic_debug) { 3704 cmn_err(CE_CONT, 3705 "socket present state = 0x%x\n", 3706 socket_present_state); 3707 } 3708 #endif 3709 switch (socket_present_state & PCIC_VCC_MASK) { 3710 case PCIC_VCC_3VCARD: 3711 /* fall through */ 3712 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3713 socket->VccLevel = PCIC_VCC_3VLEVEL; 3714 return 3715 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3716 case PCIC_VCC_5VCARD: 3717 socket->VccLevel = PCIC_VCC_5VLEVEL; 3718 return 3719 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3720 default: 3721 /* 3722 * if no card is present, this can be the 3723 * case of a client making a SetSocket call 3724 * after card removal. In this case we return 3725 * the current power level 3726 */ 3727 return ((unsigned)ddi_get8(pcic->handle, 3728 pcic->ioaddr + CB_R2_OFFSET + 3729 PCIC_POWER_CONTROL)); 3730 } 3731 3732 default: 3733 3734 switch (socket->VccLevel) { 3735 case PCIC_VCC_3VLEVEL: 3736 return (BAD_VCC); 3737 case PCIC_VCC_5VLEVEL: 3738 /* enable Vcc */ 3739 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3740 default: 3741 return (BAD_VCC); 3742 } 3743 } 3744 } 3745 3746 3747 /* 3748 * pcic_set_socket() 3749 * Socket Services SetSocket call 3750 * sets basic socket configuration 3751 */ 3752 static int 3753 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3754 { 3755 anp_t *anp = ddi_get_driver_private(dip); 3756 pcicdev_t *pcic = anp->an_private; 3757 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3758 int irq, interrupt, mirq; 3759 int powerlevel = 0; 3760 int ind, value, orig_pwrctl; 3761 3762 #if defined(PCIC_DEBUG) 3763 if (pcic_debug) { 3764 cmn_err(CE_CONT, 3765 "pcic_set_socket(dip=%p, socket=%d)" 3766 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3767 socket->socket, socket->VccLevel, socket->Vpp1Level, 3768 socket->Vpp2Level); 3769 } 3770 #endif 3771 /* 3772 * check VccLevel, etc. before setting mutex 3773 * if this is zero, power is being turned off 3774 * if it is non-zero, power is being turned on. 3775 * the default case is to assume Vcc only. 3776 */ 3777 3778 /* this appears to be very implementation specific */ 3779 3780 if (socket->Vpp1Level != socket->Vpp2Level) 3781 return (BAD_VPP); 3782 3783 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3784 powerlevel = 0; 3785 sockp->pcs_vcc = 0; 3786 sockp->pcs_vpp1 = 0; 3787 sockp->pcs_vpp2 = 0; 3788 } else { 3789 #if defined(PCIC_DEBUG) 3790 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3791 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3792 #endif 3793 /* valid Vcc power level? */ 3794 if (socket->VccLevel >= pcic->pc_numpower) 3795 return (BAD_VCC); 3796 3797 switch (pcic_power[socket->VccLevel].PowerLevel) { 3798 case 33: /* 3.3V */ 3799 case 60: /* for bad CIS in Option GPRS card */ 3800 if (!(pcic->pc_flags & PCF_33VCAP)) { 3801 cmn_err(CE_WARN, 3802 "%s%d: Bad Request for 3.3V " 3803 "(Controller incapable)\n", 3804 ddi_get_name(pcic->dip), 3805 ddi_get_instance(pcic->dip)); 3806 return (BAD_VCC); 3807 } 3808 /* FALLTHROUGH */ 3809 case 50: /* 5V */ 3810 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3811 pcic_getcb(pcic, CB_PRESENT_STATE) & 3812 CB_PS_33VCARD) { 3813 /* 3814 * This is actually a 3.3V card. 3815 * Solaris Card Services 3816 * doesn't understand 3.3V 3817 * so we cheat and change 3818 * the setting to the one appropriate to 3.3V. 3819 * Note that this is the entry number 3820 * in the pcic_power[] array. 3821 */ 3822 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3823 } else 3824 sockp->pcs_vcc = socket->VccLevel; 3825 break; 3826 default: 3827 return (BAD_VCC); 3828 } 3829 3830 /* enable Vcc */ 3831 powerlevel = POWER_CARD_ENABLE; 3832 3833 #if defined(PCIC_DEBUG) 3834 if (pcic_debug) { 3835 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3836 socket->VccLevel, powerlevel); 3837 } 3838 #endif 3839 ind = 0; /* default index to 0 power */ 3840 if ((int)socket->Vpp1Level >= 0 && 3841 socket->Vpp1Level < pcic->pc_numpower) { 3842 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3843 & VPP1)) { 3844 return (BAD_VPP); 3845 } 3846 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3847 powerlevel |= pcic_vpp_levels[ind]; 3848 sockp->pcs_vpp1 = socket->Vpp1Level; 3849 } 3850 if ((int)socket->Vpp2Level >= 0 && 3851 socket->Vpp2Level < pcic->pc_numpower) { 3852 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3853 & VPP2)) { 3854 return (BAD_VPP); 3855 } 3856 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3857 powerlevel |= (pcic_vpp_levels[ind] << 2); 3858 sockp->pcs_vpp2 = socket->Vpp2Level; 3859 } 3860 3861 if (pcic->pc_flags & PCF_VPPX) { 3862 /* 3863 * this adapter doesn't allow separate Vpp1/Vpp2 3864 * if one is turned on, both are turned on and only 3865 * the Vpp1 bits should be set 3866 */ 3867 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3868 /* must be the same if one not zero */ 3869 if (sockp->pcs_vpp1 != 0 && 3870 sockp->pcs_vpp2 != 0) { 3871 cmn_err(CE_WARN, 3872 "%s%d: Bad Power Request " 3873 "(Vpp1/2 not the same)\n", 3874 ddi_get_name(pcic->dip), 3875 ddi_get_instance(pcic->dip)); 3876 return (BAD_VPP); 3877 } 3878 } 3879 powerlevel &= ~(3<<2); 3880 } 3881 3882 #if defined(PCIC_DEBUG) 3883 if (pcic_debug) { 3884 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3885 powerlevel, ind); 3886 } 3887 #endif 3888 } 3889 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3890 3891 /* turn socket->IREQRouting off while programming */ 3892 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3893 interrupt &= ~PCIC_INTR_MASK; 3894 if (pcic->pc_flags & PCF_USE_SMI) 3895 interrupt |= PCIC_INTR_ENABLE; 3896 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3897 3898 switch (pcic->pc_type) { 3899 case PCIC_INTEL_i82092: 3900 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3901 PCIC_82092_INT_DISABLE); 3902 break; 3903 default: 3904 break; 3905 } /* switch */ 3906 3907 /* the SCIntMask specifies events to detect */ 3908 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3909 3910 #if defined(PCIC_DEBUG) 3911 if (pcic_debug) 3912 cmn_err(CE_CONT, 3913 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3914 socket->SCIntMask, interrupt, mirq); 3915 #endif 3916 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3917 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3918 mirq & ~PCIC_CHANGE_MASK); 3919 3920 /* save the mask we want to use */ 3921 sockp->pcs_intmask = socket->SCIntMask; 3922 3923 /* 3924 * Until there is a card present it's not worth enabling 3925 * any interrupts except "Card detect". This is done 3926 * elsewhere in the driver so don't change things if 3927 * there is no card! 3928 */ 3929 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3930 3931 /* now update the hardware to reflect events desired */ 3932 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3933 mirq |= PCIC_BD_DETECT; 3934 3935 if (sockp->pcs_intmask & SBM_BVD2) 3936 mirq |= PCIC_BW_DETECT; 3937 3938 if (sockp->pcs_intmask & SBM_RDYBSY) 3939 mirq |= PCIC_RD_DETECT; 3940 3941 if (sockp->pcs_intmask & SBM_CD) 3942 mirq |= PCIC_CD_DETECT; 3943 } 3944 3945 if (sockp->pcs_flags & PCS_READY) { 3946 /* 3947 * card just came ready. 3948 * make sure enough time elapses 3949 * before touching it. 3950 */ 3951 sockp->pcs_flags &= ~PCS_READY; 3952 pcic_mswait(pcic, socket->socket, 10); 3953 } 3954 3955 #if defined(PCIC_DEBUG) 3956 if (pcic_debug) { 3957 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3958 } 3959 #endif 3960 3961 switch (pcic->pc_type) { 3962 case PCIC_I82365SL: 3963 case PCIC_VADEM: 3964 case PCIC_VADEM_VG469: 3965 /* 3966 * The Intel version has different options. This is a 3967 * special case of GPI which might be used for eject 3968 */ 3969 3970 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 3971 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 3972 pcic->pc_flags & PCF_GPI_EJECT) { 3973 irq |= PCIC_GPI_ENABLE; 3974 } else { 3975 irq &= ~PCIC_GPI_ENABLE; 3976 } 3977 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 3978 break; 3979 case PCIC_CL_PD6710: 3980 case PCIC_CL_PD6722: 3981 if (socket->IFType == IF_IO) { 3982 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 3983 value = pcic_getb(pcic, socket->socket, 3984 PCIC_MISC_CTL_1); 3985 if (pcic->pc_flags & PCF_AUDIO) 3986 value |= PCIC_MC_SPEAKER_ENB; 3987 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3988 value); 3989 } else { 3990 value = pcic_getb(pcic, socket->socket, 3991 PCIC_MISC_CTL_1); 3992 value &= ~PCIC_MC_SPEAKER_ENB; 3993 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3994 value); 3995 } 3996 break; 3997 case PCIC_CL_PD6729: 3998 case PCIC_CL_PD6730: 3999 case PCIC_CL_PD6832: 4000 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 4001 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4002 value |= PCIC_MC_SPEAKER_ENB; 4003 } else { 4004 value &= ~PCIC_MC_SPEAKER_ENB; 4005 } 4006 4007 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4008 value |= PCIC_MC_3VCC; 4009 else 4010 value &= ~PCIC_MC_3VCC; 4011 4012 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 4013 break; 4014 4015 case PCIC_O2_OZ6912: 4016 value = pcic_getcb(pcic, CB_MISCCTRL); 4017 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 4018 value |= (1<<25); 4019 else 4020 value &= ~(1<<25); 4021 pcic_putcb(pcic, CB_MISCCTRL, value); 4022 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4023 powerlevel |= 0x08; 4024 break; 4025 4026 case PCIC_TI_PCI1250: 4027 case PCIC_TI_PCI1221: 4028 case PCIC_TI_PCI1225: 4029 case PCIC_TI_PCI1410: 4030 case PCIC_ENE_1410: 4031 case PCIC_TI_PCI1510: 4032 case PCIC_TI_PCI1520: 4033 case PCIC_TI_PCI1420: 4034 case PCIC_ENE_1420: 4035 value = ddi_get8(pcic->cfg_handle, 4036 pcic->cfgaddr + PCIC_CRDCTL_REG); 4037 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4038 value |= PCIC_CRDCTL_SPKR_ENBL; 4039 } else { 4040 value &= ~PCIC_CRDCTL_SPKR_ENBL; 4041 } 4042 ddi_put8(pcic->cfg_handle, 4043 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4044 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4045 powerlevel |= 0x08; 4046 break; 4047 } 4048 4049 /* 4050 * ctlind processing -- we can ignore this 4051 * there aren't any outputs on the chip for this and 4052 * the GUI will display what it thinks is correct 4053 */ 4054 4055 /* 4056 * If outputs are enabled and the power is going off 4057 * turn off outputs first. 4058 */ 4059 4060 /* power setup -- if necessary */ 4061 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4062 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4063 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4064 pcic_putb(pcic, socket->socket, 4065 PCIC_POWER_CONTROL, orig_pwrctl); 4066 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4067 } 4068 4069 if (pcic->pc_flags & PCF_CBPWRCTL) { 4070 value = pcic_cbus_powerctl(pcic, socket->socket); 4071 powerlevel = 0; 4072 } else 4073 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4074 4075 if (value != SUCCESS) { 4076 mutex_exit(&pcic->pc_lock); 4077 return (value); 4078 } 4079 4080 /* 4081 * If outputs were disabled and the power is going on 4082 * turn on outputs afterwards. 4083 */ 4084 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4085 orig_pwrctl = pcic_getb(pcic, socket->socket, 4086 PCIC_POWER_CONTROL); 4087 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4088 pcic_putb(pcic, socket->socket, 4089 PCIC_POWER_CONTROL, orig_pwrctl); 4090 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4091 } 4092 4093 /* 4094 * Once we have done the power stuff can re-enable management 4095 * interrupts. 4096 */ 4097 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4098 4099 #if defined(PCIC_DEBUG) 4100 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4101 "cbctl 0x%x\n", 4102 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4103 pcic_getcb(pcic, CB_CONTROL)); 4104 #endif 4105 4106 /* irq processing */ 4107 if (socket->IFType == IF_IO) { 4108 /* IRQ only for I/O */ 4109 irq = socket->IREQRouting & PCIC_INTR_MASK; 4110 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4111 value &= ~PCIC_INTR_MASK; 4112 4113 /* to enable I/O operation */ 4114 value |= PCIC_IO_CARD | PCIC_RESET; 4115 sockp->pcs_flags |= PCS_CARD_IO; 4116 if (irq != sockp->pcs_irq) { 4117 if (sockp->pcs_irq != 0) 4118 cmn_err(CE_CONT, 4119 "SetSocket: IRQ mismatch %x != %x!\n", 4120 irq, sockp->pcs_irq); 4121 else 4122 sockp->pcs_irq = irq; 4123 } 4124 irq = sockp->pcs_irq; 4125 4126 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4127 if (socket->IREQRouting & IRQ_ENABLE) { 4128 pcic_enable_io_intr(pcic, socket->socket, irq); 4129 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4130 } else { 4131 pcic_disable_io_intr(pcic, socket->socket); 4132 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4133 } 4134 #if defined(PCIC_DEBUG) 4135 if (pcic_debug) { 4136 cmn_err(CE_CONT, 4137 "\tsocket type is I/O and irq %x is %s\n", irq, 4138 (socket->IREQRouting & IRQ_ENABLE) ? 4139 "enabled" : "not enabled"); 4140 xxdmp_all_regs(pcic, socket->socket, 20); 4141 } 4142 #endif 4143 } else { 4144 /* make sure I/O mode is off */ 4145 4146 sockp->pcs_irq = 0; 4147 4148 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4149 value &= ~PCIC_IO_CARD; 4150 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4151 pcic_disable_io_intr(pcic, socket->socket); 4152 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4153 } 4154 4155 sockp->pcs_state &= ~socket->State; 4156 4157 mutex_exit(&pcic->pc_lock); 4158 return (SUCCESS); 4159 } 4160 4161 /* 4162 * pcic_inquire_socket() 4163 * SocketServices InquireSocket function 4164 * returns basic characteristics of the socket 4165 */ 4166 /*ARGSUSED*/ 4167 static int 4168 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4169 { 4170 anp_t *anp = ddi_get_driver_private(dip); 4171 pcicdev_t *pcic = anp->an_private; 4172 int value; 4173 4174 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4175 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4176 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4177 value = pcic->pc_sockets[socket->socket].pcs_flags; 4178 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4179 socket->ActiveHigh = 0; 4180 /* these are the usable IRQs */ 4181 socket->ActiveLow = 0xfff0; 4182 return (SUCCESS); 4183 } 4184 4185 /* 4186 * pcic_inquire_window() 4187 * SocketServices InquireWindow function 4188 * returns detailed characteristics of the window 4189 * this is where windows get tied to sockets 4190 */ 4191 /*ARGSUSED*/ 4192 static int 4193 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4194 { 4195 int type, socket; 4196 4197 type = window->window % PCIC_NUMWINSOCK; 4198 socket = window->window / PCIC_NUMWINSOCK; 4199 4200 #if defined(PCIC_DEBUG) 4201 if (pcic_debug >= 8) 4202 cmn_err(CE_CONT, 4203 "pcic_inquire_window: window = %d/%d socket=%d\n", 4204 window->window, type, socket); 4205 #endif 4206 if (type < PCIC_IOWINDOWS) { 4207 window->WndCaps = WC_IO|WC_WAIT; 4208 type = IF_IO; 4209 } else { 4210 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4211 type = IF_MEMORY; 4212 } 4213 4214 /* initialize the socket map - one socket per window */ 4215 PR_ZERO(window->Sockets); 4216 PR_SET(window->Sockets, socket); 4217 4218 if (type == IF_IO) { 4219 iowin_char_t *io; 4220 io = &window->iowin_char; 4221 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4222 WC_16BIT; 4223 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4224 io->LastByte = (baseaddr_t)IOMEM_LAST; 4225 io->MinSize = IOMEM_MIN; 4226 io->MaxSize = IOMEM_MAX; 4227 io->ReqGran = IOMEM_GRAN; 4228 io->AddrLines = IOMEM_DECODE; 4229 io->EISASlot = 0; 4230 } else { 4231 mem_win_char_t *mem; 4232 mem = &window->mem_win_char; 4233 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4234 WC_16BIT|WC_WP; 4235 4236 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4237 mem->LastByte = (baseaddr_t)MEM_LAST; 4238 4239 mem->MinSize = MEM_MIN; 4240 mem->MaxSize = MEM_MAX; 4241 mem->ReqGran = PCIC_PAGE; 4242 mem->ReqBase = 0; 4243 mem->ReqOffset = PCIC_PAGE; 4244 mem->Slowest = MEM_SPEED_MAX; 4245 mem->Fastest = MEM_SPEED_MIN; 4246 } 4247 return (SUCCESS); 4248 } 4249 4250 /* 4251 * pcic_get_adapter() 4252 * SocketServices GetAdapter function 4253 * this is nearly a no-op. 4254 */ 4255 /*ARGSUSED*/ 4256 static int 4257 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4258 { 4259 anp_t *anp = ddi_get_driver_private(dip); 4260 pcicdev_t *pcic = anp->an_private; 4261 4262 if (pcic->pc_flags & PCF_INTRENAB) 4263 adapt->SCRouting = IRQ_ENABLE; 4264 adapt->state = 0; 4265 return (SUCCESS); 4266 } 4267 4268 /* 4269 * pcic_get_page() 4270 * SocketServices GetPage function 4271 * returns info about the window 4272 */ 4273 /*ARGSUSED*/ 4274 static int 4275 pcic_get_page(dev_info_t *dip, get_page_t *page) 4276 { 4277 anp_t *anp = ddi_get_driver_private(dip); 4278 pcicdev_t *pcic = anp->an_private; 4279 int socket, window; 4280 pcs_memwin_t *winp; 4281 4282 socket = page->window / PCIC_NUMWINSOCK; 4283 window = page->window % PCIC_NUMWINSOCK; 4284 4285 /* I/O windows are the first two */ 4286 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4287 return (BAD_WINDOW); 4288 } 4289 4290 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4291 4292 if (page->page != 0) 4293 return (BAD_PAGE); 4294 4295 page->state = 0; 4296 if (winp->pcw_status & PCW_ENABLED) 4297 page->state |= PS_ENABLED; 4298 if (winp->pcw_status & PCW_ATTRIBUTE) 4299 page->state |= PS_ATTRIBUTE; 4300 if (winp->pcw_status & PCW_WP) 4301 page->state |= PS_WP; 4302 4303 page->offset = (off_t)winp->pcw_offset; 4304 4305 return (SUCCESS); 4306 } 4307 4308 /* 4309 * pcic_get_socket() 4310 * SocketServices GetSocket 4311 * returns information about the current socket setting 4312 */ 4313 /*ARGSUSED*/ 4314 static int 4315 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4316 { 4317 anp_t *anp = ddi_get_driver_private(dip); 4318 pcicdev_t *pcic = anp->an_private; 4319 int socknum, irq_enabled; 4320 pcic_socket_t *sockp; 4321 4322 socknum = socket->socket; 4323 sockp = &pcic->pc_sockets[socknum]; 4324 4325 socket->SCIntMask = sockp->pcs_intmask; 4326 sockp->pcs_state = pcic_card_state(pcic, sockp); 4327 4328 socket->state = sockp->pcs_state; 4329 if (socket->state & SBM_CD) { 4330 socket->VccLevel = sockp->pcs_vcc; 4331 socket->Vpp1Level = sockp->pcs_vpp1; 4332 socket->Vpp2Level = sockp->pcs_vpp2; 4333 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4334 IRQ_ENABLE : 0; 4335 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4336 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4337 IF_IO : IF_MEMORY; 4338 } else { 4339 socket->VccLevel = 0; 4340 socket->Vpp1Level = 0; 4341 socket->Vpp2Level = 0; 4342 socket->IRQRouting = 0; 4343 socket->IFType = IF_MEMORY; 4344 } 4345 socket->CtlInd = 0; /* no indicators */ 4346 4347 return (SUCCESS); 4348 } 4349 4350 /* 4351 * pcic_get_status() 4352 * SocketServices GetStatus 4353 * returns status information about the PC Card in 4354 * the selected socket 4355 */ 4356 /*ARGSUSED*/ 4357 static int 4358 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4359 { 4360 anp_t *anp = ddi_get_driver_private(dip); 4361 pcicdev_t *pcic = anp->an_private; 4362 int socknum, irq_enabled; 4363 pcic_socket_t *sockp; 4364 4365 socknum = status->socket; 4366 sockp = &pcic->pc_sockets[socknum]; 4367 4368 status->CardState = pcic_card_state(pcic, sockp); 4369 status->SocketState = sockp->pcs_state; 4370 status->CtlInd = 0; /* no indicators */ 4371 4372 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4373 status->SocketState |= SBM_CD; 4374 if (status->CardState & SBM_CD) { 4375 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4376 IRQ_ENABLE : 0; 4377 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4378 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4379 IF_IO : IF_MEMORY; 4380 } else { 4381 status->IRQRouting = 0; 4382 status->IFType = IF_MEMORY; 4383 } 4384 4385 #if defined(PCIC_DEBUG) 4386 if (pcic_debug >= 8) 4387 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4388 "SocketState=%x\n", 4389 socknum, status->CardState, status->SocketState); 4390 #endif 4391 switch (pcic->pc_type) { 4392 uint32_t present_state; 4393 case PCIC_TI_PCI1410: 4394 case PCIC_TI_PCI1520: 4395 case PCIC_TI_PCI1420: 4396 case PCIC_ENE_1420: 4397 case PCIC_TOSHIBA_TOPIC100: 4398 case PCIC_TOSHIBA_TOPIC95: 4399 case PCIC_TOSHIBA_VENDOR: 4400 case PCIC_O2MICRO_VENDOR: 4401 case PCIC_TI_VENDOR: 4402 case PCIC_RICOH_VENDOR: 4403 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4404 if (present_state & PCIC_CB_CARD) 4405 status->IFType = IF_CARDBUS; 4406 #if defined(PCIC_DEBUG) 4407 if (pcic_debug >= 8) 4408 cmn_err(CE_CONT, 4409 "pcic_get_status: present_state=0x%x\n", 4410 present_state); 4411 #endif 4412 break; 4413 default: 4414 break; 4415 } 4416 4417 return (SUCCESS); 4418 } 4419 4420 /* 4421 * pcic_get_window() 4422 * SocketServices GetWindow function 4423 * returns state information about the specified window 4424 */ 4425 /*ARGSUSED*/ 4426 static int 4427 pcic_get_window(dev_info_t *dip, get_window_t *window) 4428 { 4429 anp_t *anp = ddi_get_driver_private(dip); 4430 pcicdev_t *pcic = anp->an_private; 4431 int socket, win; 4432 pcic_socket_t *sockp; 4433 pcs_memwin_t *winp; 4434 4435 socket = window->window / PCIC_NUMWINSOCK; 4436 win = window->window % PCIC_NUMWINSOCK; 4437 #if defined(PCIC_DEBUG) 4438 if (pcic_debug) { 4439 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4440 socket, win); 4441 } 4442 #endif 4443 4444 if (socket > pcic->pc_numsockets) 4445 return (BAD_WINDOW); 4446 4447 sockp = &pcic->pc_sockets[socket]; 4448 winp = &sockp->pcs_windows[win].mem; 4449 4450 window->socket = socket; 4451 window->size = winp->pcw_len; 4452 window->speed = winp->pcw_speed; 4453 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4454 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4455 4456 if (win >= PCIC_IOWINDOWS) { 4457 window->state = 0; 4458 } else { 4459 window->state = WS_IO; 4460 } 4461 if (winp->pcw_status & PCW_ENABLED) 4462 window->state |= WS_ENABLED; 4463 4464 if (winp->pcw_status & PCS_CARD_16BIT) 4465 window->state |= WS_16BIT; 4466 #if defined(PCIC_DEBUG) 4467 if (pcic_debug) 4468 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4469 window->size, (unsigned)window->speed, 4470 (void *)window->handle, window->state); 4471 #endif 4472 4473 return (SUCCESS); 4474 } 4475 4476 /* 4477 * pcic_ll_reset 4478 * low level reset 4479 * separated out so it can be called when already locked 4480 * 4481 * There are two variables that control the RESET timing: 4482 * pcic_prereset_time - time in mS before asserting RESET 4483 * pcic_reset_time - time in mS to assert RESET 4484 * 4485 */ 4486 int pcic_prereset_time = 1; 4487 int pcic_reset_time = 10; 4488 int pcic_postreset_time = 20; 4489 int pcic_vpp_is_vcc_during_reset = 0; 4490 4491 static int 4492 pcic_ll_reset(pcicdev_t *pcic, int socket) 4493 { 4494 int windowbits, iobits; 4495 uint32_t pwr; 4496 4497 /* save windows that were on */ 4498 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4499 if (pcic_reset_time == 0) 4500 return (windowbits); 4501 /* turn all windows off */ 4502 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4503 4504 #if defined(PCIC_DEBUG) 4505 pcic_err(pcic->dip, 6, 4506 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4507 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4508 pcic_getcb(pcic, CB_CONTROL), 4509 pcic_getcb(pcic, CB_PRESENT_STATE)); 4510 #endif 4511 4512 if (pcic_vpp_is_vcc_during_reset) { 4513 4514 /* 4515 * Set VPP to VCC for the duration of the reset - for aironet 4516 * card. 4517 */ 4518 if (pcic->pc_flags & PCF_CBPWRCTL) { 4519 pwr = pcic_getcb(pcic, CB_CONTROL); 4520 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4521 (void) pcic_getcb(pcic, CB_CONTROL); 4522 } else { 4523 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4524 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4525 pwr | 1); 4526 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4527 } 4528 } 4529 4530 if (pcic_prereset_time > 0) { 4531 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4532 pcic_prereset_time); 4533 pcic_mswait(pcic, socket, pcic_prereset_time); 4534 } 4535 4536 /* turn interrupts off and start a reset */ 4537 pcic_err(pcic->dip, 8, 4538 "pcic_ll_reset turn interrupts off and start a reset\n"); 4539 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4540 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4541 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4542 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4543 4544 switch (pcic->pc_type) { 4545 case PCIC_INTEL_i82092: 4546 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4547 PCIC_82092_INT_DISABLE); 4548 break; 4549 default: 4550 break; 4551 } /* switch */ 4552 4553 pcic->pc_sockets[socket].pcs_state = 0; 4554 4555 if (pcic_reset_time > 0) { 4556 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4557 pcic_reset_time); 4558 pcic_mswait(pcic, socket, pcic_reset_time); 4559 } 4560 4561 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4562 4563 /* take it out of RESET now */ 4564 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4565 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4566 4567 /* 4568 * can't access the card for 20ms, but we really don't 4569 * want to sit around that long. The pcic is still usable. 4570 * memory accesses must wait for RDY to come up. 4571 */ 4572 if (pcic_postreset_time > 0) { 4573 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4574 pcic_postreset_time); 4575 pcic_mswait(pcic, socket, pcic_postreset_time); 4576 } 4577 4578 if (pcic_vpp_is_vcc_during_reset > 1) { 4579 4580 /* 4581 * Return VPP power to whatever it was before. 4582 */ 4583 if (pcic->pc_flags & PCF_CBPWRCTL) { 4584 pcic_putcb(pcic, CB_CONTROL, pwr); 4585 (void) pcic_getcb(pcic, CB_CONTROL); 4586 } else { 4587 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4588 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4589 } 4590 } 4591 4592 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4593 4594 return (windowbits); 4595 } 4596 4597 /* 4598 * pcic_reset_socket() 4599 * SocketServices ResetSocket function 4600 * puts the PC Card in the socket into the RESET state 4601 * and then takes it out after the the cycle time 4602 * The socket is back to initial state when done 4603 */ 4604 static int 4605 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4606 { 4607 anp_t *anp = ddi_get_driver_private(dip); 4608 pcicdev_t *pcic = anp->an_private; 4609 int value; 4610 int i, mint; 4611 pcic_socket_t *sockp; 4612 4613 #if defined(PCIC_DEBUG) 4614 if (pcic_debug >= 8) 4615 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4616 (void *)dip, socket, mode, 4617 mode == RESET_MODE_FULL ? "full" : "partial"); 4618 #endif 4619 4620 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4621 4622 /* Turn off management interupts. */ 4623 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4624 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4625 4626 sockp = &pcic->pc_sockets[socket]; 4627 4628 value = pcic_ll_reset(pcic, socket); 4629 if (mode == RESET_MODE_FULL) { 4630 /* disable and unmap all mapped windows */ 4631 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4632 if (i < PCIC_IOWINDOWS) { 4633 if (sockp->pcs_windows[i].io.pcw_status & 4634 PCW_MAPPED) { 4635 pcs_iowin_t *io; 4636 io = &sockp->pcs_windows[i].io; 4637 io->pcw_status &= ~PCW_ENABLED; 4638 } 4639 } else { 4640 if (sockp->pcs_windows[i].mem.pcw_status & 4641 PCW_MAPPED) { 4642 pcs_memwin_t *mem; 4643 mem = &sockp->pcs_windows[i].mem; 4644 mem->pcw_status &= ~PCW_ENABLED; 4645 } 4646 } 4647 } 4648 } else { 4649 /* turn windows back on */ 4650 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4651 /* wait the rest of the time here */ 4652 pcic_mswait(pcic, socket, 10); 4653 } 4654 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4655 mutex_exit(&pcic->pc_lock); 4656 return (SUCCESS); 4657 } 4658 4659 /* 4660 * pcic_set_interrupt() 4661 * SocketServices SetInterrupt function 4662 */ 4663 static int 4664 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4665 { 4666 anp_t *anp = ddi_get_driver_private(dip); 4667 pcicdev_t *pcic = anp->an_private; 4668 int value = DDI_SUCCESS; 4669 inthandler_t *intr; 4670 4671 #if defined(PCIC_DEBUG) 4672 if (pcic_debug) { 4673 cmn_err(CE_CONT, 4674 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4675 pcic->pc_intr_mode); 4676 cmn_err(CE_CONT, 4677 "\t irq_top=%p handler=%p handler_id=%x\n", 4678 (void *)pcic->irq_top, (void *)handler->handler, 4679 handler->handler_id); 4680 } 4681 #endif 4682 4683 /* 4684 * If we're on a PCI bus, we route all IO IRQs through a single 4685 * PCI interrupt (typically INT A#) so we don't have to do 4686 * much other than add the caller to general interrupt handler 4687 * and set some state. 4688 */ 4689 4690 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4691 if (intr == NULL) 4692 return (NO_RESOURCE); 4693 4694 switch (pcic->pc_intr_mode) { 4695 case PCIC_INTR_MODE_PCI_1: 4696 /* 4697 * We only allow above-lock-level IO IRQ handlers 4698 * in the PCI bus case. 4699 */ 4700 4701 mutex_enter(&pcic->intr_lock); 4702 4703 if (pcic->irq_top == NULL) { 4704 pcic->irq_top = intr; 4705 pcic->irq_current = pcic->irq_top; 4706 } else { 4707 while (pcic->irq_current->next != NULL) 4708 pcic->irq_current = pcic->irq_current->next; 4709 pcic->irq_current->next = intr; 4710 pcic->irq_current = pcic->irq_current->next; 4711 } 4712 4713 pcic->irq_current->intr = 4714 (ddi_intr_handler_t *)handler->handler; 4715 pcic->irq_current->handler_id = handler->handler_id; 4716 pcic->irq_current->arg1 = handler->arg1; 4717 pcic->irq_current->arg2 = handler->arg2; 4718 pcic->irq_current->socket = handler->socket; 4719 4720 mutex_exit(&pcic->intr_lock); 4721 4722 handler->iblk_cookie = &pcic->pc_pri; 4723 handler->idev_cookie = &pcic->pc_dcookie; 4724 break; 4725 4726 default: 4727 intr->intr = (ddi_intr_handler_t *)handler->handler; 4728 intr->handler_id = handler->handler_id; 4729 intr->arg1 = handler->arg1; 4730 intr->arg2 = handler->arg2; 4731 intr->socket = handler->socket; 4732 intr->irq = handler->irq; 4733 4734 /* 4735 * need to revisit this to see if interrupts can be 4736 * shared someday. Note that IRQ is set in the common 4737 * code. 4738 */ 4739 mutex_enter(&pcic->pc_lock); 4740 if (pcic->pc_handlers == NULL) { 4741 pcic->pc_handlers = intr; 4742 intr->next = intr->prev = intr; 4743 } else { 4744 insque(intr, pcic->pc_handlers); 4745 } 4746 mutex_exit(&pcic->pc_lock); 4747 4748 break; 4749 } 4750 4751 /* 4752 * need to fill in cookies in event of multiple high priority 4753 * interrupt handlers on same IRQ 4754 */ 4755 4756 #if defined(PCIC_DEBUG) 4757 if (pcic_debug) { 4758 cmn_err(CE_CONT, 4759 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4760 (void *)pcic->irq_top, value); 4761 } 4762 #endif 4763 4764 if (value == DDI_SUCCESS) { 4765 return (SUCCESS); 4766 } else { 4767 return (BAD_IRQ); 4768 } 4769 } 4770 4771 /* 4772 * pcic_clear_interrupt() 4773 * SocketServices ClearInterrupt function 4774 * 4775 * Interrupts for PCIC are complicated by the fact that we must 4776 * follow several different models for interrupts. 4777 * ISA: there is an interrupt per adapter and per socket and 4778 * they can't be shared. 4779 * PCI: some adapters have one PCI interrupt available while others 4780 * have up to 4. Solaris may or may not allow us to use more 4781 * than 1 so we essentially share them all at this point. 4782 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4783 * This is like ISA but we have to fudge and create an intrspec 4784 * that PCI's parent understands and bypass the PCI nexus. 4785 * multifunction: this requires sharing the interrupts on a per-socket 4786 * basis. 4787 */ 4788 static int 4789 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4790 { 4791 anp_t *anp = ddi_get_driver_private(dip); 4792 pcicdev_t *pcic = anp->an_private; 4793 inthandler_t *intr, *prev, *current; 4794 int i; 4795 4796 /* 4797 * If we're on a PCI bus, we route all IO IRQs through a single 4798 * PCI interrupt (typically INT A#) so we don't have to do 4799 * much other than remove the caller from the general 4800 * interrupt handler callout list. 4801 */ 4802 4803 #if defined(PCIC_DEBUG) 4804 if (pcic_debug) { 4805 cmn_err(CE_CONT, 4806 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4807 pcic->pc_intr_mode); 4808 cmn_err(CE_CONT, 4809 "\t irq_top=%p handler=%p handler_id=%x\n", 4810 (void *)pcic->irq_top, (void *)handler->handler, 4811 handler->handler_id); 4812 } 4813 #endif 4814 4815 switch (pcic->pc_intr_mode) { 4816 case PCIC_INTR_MODE_PCI_1: 4817 4818 mutex_enter(&pcic->intr_lock); 4819 if (pcic->irq_top == NULL) { 4820 mutex_exit(&pcic->intr_lock); 4821 return (BAD_IRQ); 4822 } 4823 4824 intr = NULL; 4825 pcic->irq_current = pcic->irq_top; 4826 4827 while ((pcic->irq_current != NULL) && 4828 (pcic->irq_current->handler_id != 4829 handler->handler_id)) { 4830 intr = pcic->irq_current; 4831 pcic->irq_current = pcic->irq_current->next; 4832 } 4833 4834 if (pcic->irq_current == NULL) { 4835 mutex_exit(&pcic->intr_lock); 4836 return (BAD_IRQ); 4837 } 4838 4839 if (intr != NULL) { 4840 intr->next = pcic->irq_current->next; 4841 } else { 4842 pcic->irq_top = pcic->irq_current->next; 4843 } 4844 4845 current = pcic->irq_current; 4846 pcic->irq_current = pcic->irq_top; 4847 mutex_exit(&pcic->intr_lock); 4848 kmem_free(current, sizeof (inthandler_t)); 4849 4850 break; 4851 4852 default: 4853 4854 mutex_enter(&pcic->pc_lock); 4855 intr = pcic_handlers; 4856 prev = (inthandler_t *)&pcic_handlers; 4857 4858 while (intr != NULL) { 4859 if (intr->handler_id == handler->handler_id) { 4860 i = intr->irq & PCIC_INTR_MASK; 4861 if (--pcic_irq_map[i].count == 0) { 4862 /* multi-handler form */ 4863 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4864 (void) ddi_intr_remove_handler( 4865 pcic->pc_intr_htblp[i]); 4866 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4867 (void) pcmcia_return_intr(pcic->dip, i); 4868 #if defined(PCIC_DEBUG) 4869 if (pcic_debug) { 4870 cmn_err(CE_CONT, 4871 "removing interrupt %d at %s " 4872 "priority\n", i, "high"); 4873 cmn_err(CE_CONT, 4874 "ddi_remove_intr(%p, %x, %p)\n", 4875 (void *)dip, 4876 0, 4877 (void *)intr->iblk_cookie); 4878 } 4879 #endif 4880 } 4881 prev->next = intr->next; 4882 kmem_free(intr, sizeof (inthandler_t)); 4883 intr = prev->next; 4884 } else { 4885 prev = intr; 4886 intr = intr->next; 4887 } /* if (handler_id) */ 4888 } /* while */ 4889 4890 mutex_exit(&pcic->pc_lock); 4891 } 4892 4893 #if defined(PCIC_DEBUG) 4894 if (pcic_debug) { 4895 cmn_err(CE_CONT, 4896 "pcic_clear_interrupt: exit irq_top=%p\n", 4897 (void *)pcic->irq_top); 4898 } 4899 #endif 4900 4901 4902 return (SUCCESS); 4903 } 4904 4905 struct intel_regs { 4906 char *name; 4907 int off; 4908 char *fmt; 4909 } iregs[] = { 4910 {"ident ", 0}, 4911 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4912 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4913 "\7DRD\10OE"}, 4914 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4915 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4916 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4917 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4918 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4919 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4920 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4921 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4922 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4923 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4924 {"io0-slow ", 8}, 4925 {"io0-shi ", 9}, 4926 {"io0-elow ", 0xa}, 4927 {"io0-ehi ", 0xb}, 4928 {"io1-slow ", 0xc}, 4929 {"io1-shi ", 0xd}, 4930 {"io1-elow ", 0xe}, 4931 {"io1-ehi ", 0xf}, 4932 {"mem0-slow ", 0x10}, 4933 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4934 {"mem0-elow ", 0x12}, 4935 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4936 {"card0-low ", 0x14}, 4937 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4938 {"mem1-slow ", 0x18}, 4939 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4940 {"mem1-elow ", 0x1a}, 4941 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4942 {"card1-low ", 0x1c}, 4943 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4944 {"mem2-slow ", 0x20}, 4945 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4946 {"mem2-elow ", 0x22}, 4947 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4948 {"card2-low ", 0x24}, 4949 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4950 {"mem3-slow ", 0x28}, 4951 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4952 {"mem3-elow ", 0x2a}, 4953 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4954 {"card3-low ", 0x2c}, 4955 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4956 4957 {"mem4-slow ", 0x30}, 4958 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4959 {"mem4-elow ", 0x32}, 4960 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4961 {"card4-low ", 0x34}, 4962 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4963 {"mpage0 ", 0x40}, 4964 {"mpage1 ", 0x41}, 4965 {"mpage2 ", 0x42}, 4966 {"mpage3 ", 0x43}, 4967 {"mpage4 ", 0x44}, 4968 {NULL}, 4969 }; 4970 4971 static struct intel_regs cregs[] = { 4972 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 4973 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 4974 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 4975 {"chip-info ", 0x1f, "\20\6DUAL"}, 4976 {"IO-offlow0", 0x36}, 4977 {"IO-offhi0 ", 0x37}, 4978 {"IO-offlow1", 0x38}, 4979 {"IO-offhi1 ", 0x39}, 4980 NULL, 4981 }; 4982 4983 static struct intel_regs cxregs[] = { 4984 {"ext-ctl-1 ", 0x03, 4985 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 4986 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 4987 {"mem0-up ", 0x05}, 4988 {"mem1-up ", 0x06}, 4989 {"mem2-up ", 0x07}, 4990 {"mem3-up ", 0x08}, 4991 {"mem4-up ", 0x09}, 4992 {NULL} 4993 }; 4994 4995 void 4996 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 4997 { 4998 int i, value, j; 4999 char buff[256]; 5000 char *fmt; 5001 5002 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 5003 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 5004 int sval; 5005 if (cregs[i].off == PCIC_MISC_CTL_2) 5006 sval = 0; 5007 else 5008 sval = socket; 5009 value = pcic_getb(pcic, sval, cregs[i].off); 5010 if (i & 1) { 5011 if (cregs[i].fmt) 5012 fmt = "%s\t%s\t%b\n"; 5013 else 5014 fmt = "%s\t%s\t%x\n"; 5015 cmn_err(CE_CONT, fmt, buff, 5016 cregs[i].name, value, cregs[i].fmt); 5017 buff[0] = '\0'; 5018 } else { 5019 if (cregs[i].fmt) 5020 fmt = "\t%s\t%b"; 5021 else 5022 fmt = "\t%s\t%x"; 5023 (void) sprintf(buff, fmt, 5024 cregs[i].name, value, cregs[i].fmt); 5025 for (j = strlen(buff); j < 40; j++) 5026 buff[j] = ' '; 5027 buff[40] = '\0'; 5028 } 5029 } 5030 cmn_err(CE_CONT, "%s\n", buff); 5031 5032 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 5033 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 5034 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 5035 5036 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 5037 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 5038 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 5039 5040 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 5041 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 5042 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 5043 5044 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5045 5046 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5047 value = clext_reg_read(pcic, socket, cxregs[i].off); 5048 if (i & 1) { 5049 if (cxregs[i].fmt) 5050 fmt = "%s\t%s\t%b\n"; 5051 else 5052 fmt = "%s\t%s\t%x\n"; 5053 cmn_err(CE_CONT, fmt, buff, 5054 cxregs[i].name, value, cxregs[i].fmt); 5055 buff[0] = '\0'; 5056 } else { 5057 if (cxregs[i].fmt) 5058 fmt = "\t%s\t%b"; 5059 else 5060 fmt = "\t%s\t%x"; 5061 (void) sprintf(buff, fmt, 5062 cxregs[i].name, value, cxregs[i].fmt); 5063 for (j = strlen(buff); j < 40; j++) 5064 buff[j] = ' '; 5065 buff[40] = '\0'; 5066 } 5067 } 5068 } 5069 5070 #if defined(PCIC_DEBUG) 5071 static void 5072 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5073 { 5074 int i, value, j; 5075 char buff[256]; 5076 char *fmt; 5077 5078 #if defined(PCIC_DEBUG) 5079 if (pcic_debug < 2) 5080 return; 5081 #endif 5082 cmn_err(CE_CONT, 5083 "----------- PCIC Registers for socket %d---------\n", 5084 socket); 5085 cmn_err(CE_CONT, 5086 "\tname value name value\n"); 5087 5088 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5089 value = pcic_getb(pcic, socket, iregs[i].off); 5090 if (i & 1) { 5091 if (iregs[i].fmt) 5092 fmt = "%s\t%s\t%b\n"; 5093 else 5094 fmt = "%s\t%s\t%x\n"; 5095 cmn_err(CE_CONT, fmt, buff, 5096 iregs[i].name, value, iregs[i].fmt); 5097 buff[0] = '\0'; 5098 } else { 5099 if (iregs[i].fmt) 5100 fmt = "\t%s\t%b"; 5101 else 5102 fmt = "\t%s\t%x"; 5103 (void) sprintf(buff, fmt, 5104 iregs[i].name, value, iregs[i].fmt); 5105 for (j = strlen(buff); j < 40; j++) 5106 buff[j] = ' '; 5107 buff[40] = '\0'; 5108 } 5109 } 5110 switch (pcic->pc_type) { 5111 case PCIC_CL_PD6710: 5112 case PCIC_CL_PD6722: 5113 case PCIC_CL_PD6729: 5114 case PCIC_CL_PD6832: 5115 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5116 break; 5117 } 5118 cmn_err(CE_CONT, "%s\n", buff); 5119 } 5120 #endif 5121 5122 /* 5123 * pcic_mswait(ms) 5124 * sleep ms milliseconds 5125 * call drv_usecwait once for each ms 5126 */ 5127 static void 5128 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5129 { 5130 if (ms) { 5131 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5132 pcic_mutex_exit(&pcic->pc_lock); 5133 delay(drv_usectohz(ms*1000)); 5134 pcic_mutex_enter(&pcic->pc_lock); 5135 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5136 } 5137 } 5138 5139 /* 5140 * pcic_check_ready(pcic, index, off) 5141 * Wait for card to come ready 5142 * We only wait if the card is NOT in RESET 5143 * and power is on. 5144 */ 5145 static boolean_t 5146 pcic_check_ready(pcicdev_t *pcic, int socket) 5147 { 5148 int ifstate, intstate; 5149 5150 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5151 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5152 5153 if ((intstate & PCIC_RESET) && 5154 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5155 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5156 return (B_TRUE); 5157 5158 #ifdef PCIC_DEBUG 5159 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5160 "ifstate = 0x%x\n", intstate, ifstate); 5161 if (pcic_debug) { 5162 pcic_debug += 4; 5163 xxdmp_all_regs(pcic, socket, -1); 5164 pcic_debug -= 4; 5165 } 5166 #endif 5167 return (B_FALSE); 5168 } 5169 5170 /* 5171 * Cirrus Logic extended register read/write routines 5172 */ 5173 static int 5174 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5175 { 5176 int val; 5177 5178 switch (pcic->pc_io_type) { 5179 case PCIC_IO_TYPE_YENTA: 5180 val = ddi_get8(pcic->handle, 5181 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5182 break; 5183 default: 5184 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5185 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5186 break; 5187 } 5188 5189 return (val); 5190 } 5191 5192 static void 5193 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5194 { 5195 switch (pcic->pc_io_type) { 5196 case PCIC_IO_TYPE_YENTA: 5197 ddi_put8(pcic->handle, 5198 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5199 break; 5200 default: 5201 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5202 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5203 break; 5204 } 5205 } 5206 5207 /* 5208 * Misc PCI functions 5209 */ 5210 static void 5211 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5212 { 5213 unsigned cmd; 5214 5215 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5216 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5217 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5218 (PCI_COMM_IO|PCI_COMM_MAE)) 5219 return; 5220 5221 if (flags & PCIC_ENABLE_IO) 5222 cmd |= PCI_COMM_IO; 5223 5224 if (flags & PCIC_ENABLE_MEM) 5225 cmd |= PCI_COMM_MAE; 5226 5227 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5228 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5229 } 5230 5231 /* 5232 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5233 */ 5234 static int 5235 pcic_find_pci_type(pcicdev_t *pcic) 5236 { 5237 uint32_t vend, device; 5238 5239 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5240 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5241 "vendor-id", -1); 5242 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5243 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5244 "device-id", -1); 5245 5246 device = PCI_ID(vend, device); 5247 pcic->pc_type = device; 5248 pcic->pc_chipname = "PCI:unknown"; 5249 5250 switch (device) { 5251 case PCIC_INTEL_i82092: 5252 pcic->pc_chipname = PCIC_TYPE_i82092; 5253 break; 5254 case PCIC_CL_PD6729: 5255 pcic->pc_chipname = PCIC_TYPE_PD6729; 5256 /* 5257 * Some 6730's incorrectly identify themselves 5258 * as a 6729, so we need to do some more tests 5259 * here to see if the device that's claiming 5260 * to be a 6729 is really a 6730. 5261 */ 5262 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5263 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5264 0) { 5265 pcic->pc_chipname = PCIC_TYPE_PD6730; 5266 pcic->pc_type = PCIC_CL_PD6730; 5267 } 5268 break; 5269 case PCIC_CL_PD6730: 5270 pcic->pc_chipname = PCIC_TYPE_PD6730; 5271 break; 5272 case PCIC_CL_PD6832: 5273 pcic->pc_chipname = PCIC_TYPE_PD6832; 5274 break; 5275 case PCIC_SMC_34C90: 5276 pcic->pc_chipname = PCIC_TYPE_34C90; 5277 break; 5278 case PCIC_TOSHIBA_TOPIC95: 5279 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5280 break; 5281 case PCIC_TOSHIBA_TOPIC100: 5282 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5283 break; 5284 case PCIC_TI_PCI1031: 5285 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5286 break; 5287 case PCIC_TI_PCI1130: 5288 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5289 break; 5290 case PCIC_TI_PCI1131: 5291 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5292 break; 5293 case PCIC_TI_PCI1250: 5294 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5295 break; 5296 case PCIC_TI_PCI1225: 5297 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5298 break; 5299 case PCIC_TI_PCI1410: 5300 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5301 break; 5302 case PCIC_TI_PCI1510: 5303 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5304 break; 5305 case PCIC_TI_PCI1520: 5306 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5307 break; 5308 case PCIC_TI_PCI1221: 5309 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5310 break; 5311 case PCIC_TI_PCI1050: 5312 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5313 break; 5314 case PCIC_ENE_1410: 5315 pcic->pc_chipname = PCIC_TYPE_1410; 5316 break; 5317 case PCIC_O2_OZ6912: 5318 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5319 break; 5320 case PCIC_RICOH_RL5C466: 5321 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5322 break; 5323 case PCIC_TI_PCI1420: 5324 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5325 break; 5326 case PCIC_ENE_1420: 5327 pcic->pc_chipname = PCIC_TYPE_1420; 5328 break; 5329 default: 5330 switch (PCI_ID(vend, (uint32_t)0)) { 5331 case PCIC_TOSHIBA_VENDOR: 5332 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5333 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5334 break; 5335 case PCIC_TI_VENDOR: 5336 pcic->pc_chipname = PCIC_TYPE_TI; 5337 pcic->pc_type = PCIC_TI_VENDOR; 5338 break; 5339 case PCIC_O2MICRO_VENDOR: 5340 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5341 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5342 break; 5343 case PCIC_RICOH_VENDOR: 5344 pcic->pc_chipname = PCIC_TYPE_RICOH; 5345 pcic->pc_type = PCIC_RICOH_VENDOR; 5346 break; 5347 default: 5348 if (!(pcic->pc_flags & PCF_CARDBUS)) 5349 return (DDI_FAILURE); 5350 pcic->pc_chipname = PCIC_TYPE_YENTA; 5351 break; 5352 } 5353 } 5354 return (DDI_SUCCESS); 5355 } 5356 5357 static void 5358 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5359 { 5360 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5361 pcic->cfgaddr + PCIC_82092_PPIRR); 5362 uchar_t val; 5363 5364 if (intr == PCIC_82092_CTL_SMI) { 5365 val = PCIC_82092_SMI_CTL(socket, 5366 PCIC_82092_INT_DISABLE); 5367 ppirr &= ~val; 5368 val = PCIC_82092_SMI_CTL(socket, state); 5369 ppirr |= val; 5370 } else { 5371 val = PCIC_82092_IRQ_CTL(socket, 5372 PCIC_82092_INT_DISABLE); 5373 ppirr &= ~val; 5374 val = PCIC_82092_IRQ_CTL(socket, state); 5375 ppirr |= val; 5376 } 5377 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5378 ppirr); 5379 } 5380 5381 static uint_t 5382 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5383 { 5384 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5385 uint_t rc = DDI_INTR_UNCLAIMED; 5386 5387 _NOTE(ARGUNUSED(arg2)) 5388 5389 mutex_enter(&sockp->pcs_pcic->pc_lock); 5390 if (sockp->pcs_cd_softint_flg) { 5391 uint8_t status; 5392 sockp->pcs_cd_softint_flg = 0; 5393 rc = DDI_INTR_CLAIMED; 5394 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5395 PCIC_INTERFACE_STATUS); 5396 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5397 } 5398 mutex_exit(&sockp->pcs_pcic->pc_lock); 5399 return (rc); 5400 } 5401 5402 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5403 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5404 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5405 5406 #ifdef CARDBUS 5407 static uint32_t pcic_cbps_on = 0; 5408 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5409 CB_PS_XVCARD | CB_PS_YVCARD; 5410 #else 5411 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5412 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5413 CB_PS_CBCARD | 5414 CB_PS_XVCARD | CB_PS_YVCARD; 5415 #endif 5416 static void 5417 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5418 { 5419 boolean_t do_debounce = B_FALSE; 5420 int debounce_time = drv_usectohz(pcic_debounce_time); 5421 uint8_t irq; 5422 timeout_id_t debounce; 5423 5424 /* 5425 * Always reset debounce but may need to check original state later. 5426 */ 5427 debounce = sockp->pcs_debounce_id; 5428 sockp->pcs_debounce_id = 0; 5429 5430 /* 5431 * Check to see whether a card is present or not. There are 5432 * only two states that we are concerned with - the state 5433 * where both CD pins are asserted, which means that the 5434 * card is fully seated, and the state where neither CD 5435 * pin is asserted, which means that the card is not 5436 * present. 5437 * The CD signals are generally very noisy and cause a lot of 5438 * contact bounce as the card is being inserted and 5439 * removed, so we need to do some software debouncing. 5440 */ 5441 5442 #ifdef PCIC_DEBUG 5443 pcic_err(pcic->dip, 6, 5444 "pcic%d handle_cd_change: socket %d card status 0x%x" 5445 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5446 sockp->pcs_socket, status, debounce); 5447 #endif 5448 switch (status & PCIC_ISTAT_CD_MASK) { 5449 case PCIC_CD_PRESENT_OK: 5450 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5451 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5452 uint32_t cbps; 5453 #ifdef PCIC_DEBUG 5454 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5455 #endif 5456 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5457 #ifdef PCIC_DEBUG 5458 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5459 #endif 5460 /* 5461 * Check the CB bits are sane. 5462 */ 5463 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5464 cbps & pcic_cbps_off) { 5465 cmn_err(CE_WARN, 5466 "%s%d: Odd Cardbus Present State 0x%x\n", 5467 ddi_get_name(pcic->dip), 5468 ddi_get_instance(pcic->dip), 5469 cbps); 5470 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5471 debounce = 0; 5472 debounce_time = drv_usectohz(1000000); 5473 } 5474 if (debounce) { 5475 sockp->pcs_flags |= PCS_CARD_PRESENT; 5476 if (pcic_do_insertion) { 5477 5478 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5479 5480 if (cbps & CB_PS_16BITCARD) { 5481 pcic_err(pcic->dip, 5482 8, "16 bit card inserted\n"); 5483 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5484 /* calls pcm_adapter_callback() */ 5485 if (pcic->pc_callback) { 5486 5487 (void) ddi_prop_update_string( 5488 DDI_DEV_T_NONE, 5489 pcic->dip, PCM_DEVICETYPE, 5490 "pccard"); 5491 PC_CALLBACK(pcic->dip, 5492 pcic->pc_cb_arg, 5493 PCE_CARD_INSERT, 5494 sockp->pcs_socket); 5495 } 5496 } else if (cbps & CB_PS_CBCARD) { 5497 pcic_err(pcic->dip, 5498 8, "32 bit card inserted\n"); 5499 5500 if (pcic->pc_flags & PCF_CARDBUS) { 5501 sockp->pcs_flags |= 5502 PCS_CARD_ISCARDBUS; 5503 #ifdef CARDBUS 5504 if (!pcic_load_cardbus(pcic, 5505 sockp)) { 5506 pcic_unload_cardbus( 5507 pcic, sockp); 5508 } 5509 5510 #else 5511 cmn_err(CE_NOTE, 5512 "32 bit Cardbus not" 5513 " supported in" 5514 " this device driver\n"); 5515 #endif 5516 } else { 5517 /* 5518 * Ignore the card 5519 */ 5520 cmn_err(CE_NOTE, 5521 "32 bit Cardbus not" 5522 " supported on this" 5523 " device\n"); 5524 } 5525 } else { 5526 cmn_err(CE_NOTE, 5527 "Unsupported PCMCIA card" 5528 " inserted\n"); 5529 } 5530 } 5531 } else { 5532 do_debounce = B_TRUE; 5533 } 5534 } else { 5535 /* 5536 * It is possible to come through here if the system 5537 * starts up with cards already inserted. Do nothing 5538 * and don't worry about it. 5539 */ 5540 #ifdef PCIC_DEBUG 5541 pcic_err(pcic->dip, 5, 5542 "pcic%d: Odd card insertion indication on socket %d\n", 5543 ddi_get_instance(pcic->dip), 5544 sockp->pcs_socket); 5545 #endif 5546 } 5547 break; 5548 5549 default: 5550 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5551 /* 5552 * Someone has started to insert a card so delay a while. 5553 */ 5554 do_debounce = B_TRUE; 5555 break; 5556 } 5557 /* 5558 * Otherwise this is basically the same as not present 5559 * so fall through. 5560 */ 5561 5562 /* FALLTHRU */ 5563 case 0: 5564 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5565 if (pcic->pc_flags & PCF_CBPWRCTL) { 5566 pcic_putcb(pcic, CB_CONTROL, 0); 5567 } else { 5568 pcic_putb(pcic, sockp->pcs_socket, 5569 PCIC_POWER_CONTROL, 0); 5570 (void) pcic_getb(pcic, sockp->pcs_socket, 5571 PCIC_POWER_CONTROL); 5572 } 5573 #ifdef PCIC_DEBUG 5574 pcic_err(pcic->dip, 8, "Card removed\n"); 5575 #endif 5576 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5577 5578 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5579 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5580 if (pcic_do_removal && pcic->pc_callback) { 5581 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5582 PCE_CARD_REMOVAL, sockp->pcs_socket); 5583 } 5584 } 5585 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5586 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5587 sockp->pcs_flags |= PCS_CARD_CBREM; 5588 } 5589 sockp->pcs_flags |= PCS_CARD_REMOVED; 5590 5591 do_debounce = B_TRUE; 5592 } 5593 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5594 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5595 /* 5596 * Ensure that we do the unloading in the 5597 * debounce handler, that way we're not doing 5598 * nasty things in an interrupt handler. e.g. 5599 * a USB device will wait for data which will 5600 * obviously never come because we've 5601 * unplugged the device, but the wait will 5602 * wait forever because no interrupts can 5603 * come in... 5604 */ 5605 #ifdef CARDBUS 5606 pcic_unload_cardbus(pcic, sockp); 5607 /* pcic_dump_all(pcic); */ 5608 #endif 5609 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5610 } 5611 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5612 } 5613 break; 5614 } /* switch */ 5615 5616 if (do_debounce) { 5617 /* 5618 * Delay doing 5619 * anything for a while so that things can settle 5620 * down a little. Interrupts are already disabled. 5621 * Reset the state and we'll reevaluate the 5622 * whole kit 'n kaboodle when the timeout fires 5623 */ 5624 #ifdef PCIC_DEBUG 5625 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5626 "socket %d.%d\n", 5627 ddi_get_instance(pcic->dip), 5628 sockp->pcs_socket); 5629 #endif 5630 sockp->pcs_debounce_id = 5631 pcic_add_debqueue(sockp, debounce_time); 5632 5633 /* 5634 * We bug out here without re-enabling interrupts. They will 5635 * be re-enabled when the debounce timeout swings through 5636 * here. 5637 */ 5638 return; 5639 } 5640 5641 /* 5642 * Turn on Card detect interrupts. Other interrupts will be 5643 * enabled during set_socket calls. 5644 * 5645 * Note that set_socket only changes interrupt settings when there 5646 * is a card present. 5647 */ 5648 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5649 irq |= PCIC_CD_DETECT; 5650 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5651 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5652 5653 /* Out from debouncing state */ 5654 sockp->pcs_flags &= ~PCS_DEBOUNCING; 5655 5656 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5657 } 5658 5659 /* 5660 * pcic_getb() 5661 * get an I/O byte based on the yardware decode method 5662 */ 5663 static uint8_t 5664 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5665 { 5666 int work; 5667 5668 #if defined(PCIC_DEBUG) 5669 if (pcic_debug == 0x7fff) { 5670 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5671 (void *)pcic, socket, reg); 5672 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5673 pcic->pc_io_type, (void *)pcic->handle, 5674 (void *)pcic->ioaddr); 5675 } 5676 #endif 5677 5678 switch (pcic->pc_io_type) { 5679 case PCIC_IO_TYPE_YENTA: 5680 return (ddi_get8(pcic->handle, 5681 pcic->ioaddr + CB_R2_OFFSET + reg)); 5682 default: 5683 work = (socket * PCIC_SOCKET_1) | reg; 5684 ddi_put8(pcic->handle, pcic->ioaddr, work); 5685 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5686 } 5687 } 5688 5689 static void 5690 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5691 { 5692 int work; 5693 5694 #if defined(PCIC_DEBUG) 5695 if (pcic_debug == 0x7fff) { 5696 cmn_err(CE_CONT, 5697 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5698 (void *)pcic, socket, reg, value); 5699 cmn_err(CE_CONT, 5700 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5701 pcic->pc_io_type, (void *)pcic->handle, 5702 (void *)pcic->ioaddr); 5703 } 5704 #endif 5705 5706 5707 switch (pcic->pc_io_type) { 5708 case PCIC_IO_TYPE_YENTA: 5709 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5710 value); 5711 break; 5712 default: 5713 work = (socket * PCIC_SOCKET_1) | reg; 5714 ddi_put8(pcic->handle, pcic->ioaddr, work); 5715 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5716 break; 5717 } 5718 } 5719 5720 /* 5721 * chip identification functions 5722 */ 5723 5724 /* 5725 * chip identification: Cirrus Logic PD6710/6720/6722 5726 */ 5727 static int 5728 pcic_ci_cirrus(pcicdev_t *pcic) 5729 { 5730 int value1, value2; 5731 5732 /* Init the CL id mode */ 5733 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5734 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5735 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5736 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5737 5738 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5739 (value2 & PCIC_CI_ID) == 0) { 5740 /* chip is a Cirrus Logic and not Intel */ 5741 pcic->pc_type = PCIC_CL_PD6710; 5742 if (value1 & PCIC_CI_SLOTS) 5743 pcic->pc_chipname = PCIC_TYPE_PD6720; 5744 else 5745 pcic->pc_chipname = PCIC_TYPE_PD6710; 5746 /* now fine tune things just in case a 6722 */ 5747 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5748 if (value1 == 0) { 5749 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5750 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5751 if (value1 == 0x55) { 5752 pcic->pc_chipname = PCIC_TYPE_PD6722; 5753 pcic->pc_type = PCIC_CL_PD6722; 5754 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5755 } 5756 } 5757 return (1); 5758 } 5759 return (0); 5760 } 5761 5762 /* 5763 * chip identification: Vadem (VG365/465/468/469) 5764 */ 5765 5766 static void 5767 pcic_vadem_enable(pcicdev_t *pcic) 5768 { 5769 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5770 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5771 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5772 } 5773 5774 static int 5775 pcic_ci_vadem(pcicdev_t *pcic) 5776 { 5777 int value; 5778 5779 pcic_vadem_enable(pcic); 5780 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5781 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5782 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5783 (value | PCIC_VADEM_D3) || 5784 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5785 PCIC_VADEM_469) { 5786 int vadem, new; 5787 pcic_vadem_enable(pcic); 5788 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5789 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5790 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5791 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5792 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5793 5794 /* want to lock but leave mouse or other on */ 5795 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5796 switch (value & PCIC_REV_MASK) { 5797 case PCIC_VADEM_365: 5798 pcic->pc_chipname = PCIC_VG_365; 5799 pcic->pc_type = PCIC_VADEM; 5800 break; 5801 case PCIC_VADEM_465: 5802 pcic->pc_chipname = PCIC_VG_465; 5803 pcic->pc_type = PCIC_VADEM; 5804 pcic->pc_flags |= PCF_1SOCKET; 5805 break; 5806 case PCIC_VADEM_468: 5807 pcic->pc_chipname = PCIC_VG_468; 5808 pcic->pc_type = PCIC_VADEM; 5809 break; 5810 case PCIC_VADEM_469: 5811 pcic->pc_chipname = PCIC_VG_469; 5812 pcic->pc_type = PCIC_VADEM_VG469; 5813 break; 5814 } 5815 return (1); 5816 } 5817 return (0); 5818 } 5819 5820 /* 5821 * chip identification: Ricoh 5822 */ 5823 static int 5824 pcic_ci_ricoh(pcicdev_t *pcic) 5825 { 5826 int value; 5827 5828 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5829 switch (value) { 5830 case PCIC_RF_296: 5831 pcic->pc_type = PCIC_RICOH; 5832 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5833 return (1); 5834 case PCIC_RF_396: 5835 pcic->pc_type = PCIC_RICOH; 5836 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5837 return (1); 5838 } 5839 return (0); 5840 } 5841 5842 5843 /* 5844 * set up available address spaces in busra 5845 */ 5846 static void 5847 pcic_init_assigned(dev_info_t *dip) 5848 { 5849 pcm_regs_t *pcic_avail_p; 5850 pci_regspec_t *pci_avail_p, *regs; 5851 int len, entries, rlen; 5852 dev_info_t *pdip; 5853 5854 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5855 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5856 /* 5857 * found "available" property at the cardbus/pcmcia node 5858 * need to translate address space entries from pcmcia 5859 * format to pci format 5860 */ 5861 entries = len / sizeof (pcm_regs_t); 5862 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5863 KM_SLEEP); 5864 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5865 entries) == DDI_SUCCESS) 5866 (void) pci_resource_setup_avail(dip, pci_avail_p, 5867 entries); 5868 kmem_free(pcic_avail_p, len); 5869 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5870 return; 5871 } 5872 5873 /* 5874 * "legacy" platforms will have "available" property in pci node 5875 */ 5876 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5877 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5878 "available", (caddr_t)&pci_avail_p, &len) == 5879 DDI_PROP_SUCCESS) { 5880 /* (void) pci_resource_setup(pdip); */ 5881 kmem_free(pci_avail_p, len); 5882 break; 5883 } 5884 } 5885 5886 if (pdip == NULL) { 5887 int len; 5888 char bus_type[16] = "(unknown)"; 5889 dev_info_t *par; 5890 5891 cmn_err(CE_CONT, 5892 "?pcic_init_assigned: no available property for pcmcia\n"); 5893 5894 /* 5895 * This code is taken from pci_resource_setup() but does 5896 * not attempt to use the "available" property to populate 5897 * the ndi maps that are created. 5898 * The fact that we will actually 5899 * free some resource below (that was allocated by OBP) 5900 * should be enough to be going on with. 5901 */ 5902 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5903 len = sizeof (bus_type); 5904 5905 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5906 PROP_LEN_AND_VAL_BUF, 5907 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5908 "device_type", 5909 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5910 (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 5911 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0)) 5912 break; 5913 } 5914 if (par != NULL && 5915 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5916 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5917 par = NULL; 5918 } else { 5919 #ifdef CARDBUS 5920 cardbus_bus_range_t *bus_range; 5921 int k; 5922 5923 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5924 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5925 if (bus_range->lo != bus_range->hi) 5926 pcic_err(pdip, 9, "allowable bus range is " 5927 "%u->%u\n", bus_range->lo, bus_range->hi); 5928 else { 5929 pcic_err(pdip, 0, 5930 "!No spare PCI bus numbers, range is " 5931 "%u->%u, cardbus isn't usable\n", 5932 bus_range->lo, bus_range->hi); 5933 } 5934 kmem_free(bus_range, k); 5935 } else 5936 pcic_err(pdip, 0, "!No bus-range property seems to " 5937 "have been set up\n"); 5938 #endif 5939 /* 5940 * Have a valid parent with the "available" property 5941 */ 5942 (void) pci_resource_setup(pdip); 5943 } 5944 5945 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5946 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5947 "assigned-addresses", 5948 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5949 ra_return_t ra; 5950 5951 /* 5952 * On the UltraBook IIi the ranges are assigned under 5953 * openboot. If we don't free them here the first I/O 5954 * space that can be used is up above 0x10000 which 5955 * doesn't work for this driver due to restrictions 5956 * on the PCI I/O addresses the controllers can cope with. 5957 * They are never going to be used by anything else 5958 * so free them up to the general pool. AG. 5959 */ 5960 pcic_err(dip, 1, "Free assigned addresses\n"); 5961 5962 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5963 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5964 regs[0].pci_size_low == 0x1000000) { 5965 ra.ra_addr_lo = regs[0].pci_phys_low; 5966 ra.ra_len = regs[0].pci_size_low; 5967 (void) pcmcia_free_mem(dip, &ra); 5968 } 5969 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5970 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5971 (regs[1].pci_size_low == 0x8000 || 5972 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5973 { 5974 ra.ra_addr_lo = regs[1].pci_phys_low; 5975 ra.ra_len = regs[1].pci_size_low; 5976 (void) pcmcia_free_io(dip, &ra); 5977 } 5978 kmem_free((caddr_t)regs, rlen); 5979 } 5980 } 5981 5982 /* 5983 * translate "available" from pcmcia format to pci format 5984 */ 5985 static int 5986 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 5987 pci_regspec_t *pci_p, int entries) 5988 { 5989 int i, range_len, range_entries; 5990 pcic_ranges_t *pcic_range_p; 5991 5992 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 5993 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 5994 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 5995 "no ranges property for pcmcia\n"); 5996 return (DDI_FAILURE); 5997 } 5998 5999 range_entries = range_len / sizeof (pcic_ranges_t); 6000 6001 /* for each "available" entry to be translated */ 6002 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 6003 int j; 6004 pcic_ranges_t *range_p = pcic_range_p; 6005 pci_p->pci_phys_hi = -1u; /* default invalid value */ 6006 6007 /* for each "ranges" entry to be searched */ 6008 for (j = 0; j < range_entries; j++, range_p++) { 6009 uint64_t range_end = range_p->pcic_range_caddrlo + 6010 range_p->pcic_range_size; 6011 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 6012 6013 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 6014 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 6015 (range_end < avail_end)) 6016 continue; 6017 6018 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 6019 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 6020 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 6021 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 6022 pci_p->pci_size_hi = 0; 6023 pci_p->pci_size_low = pcic_p->phys_len; 6024 } 6025 } 6026 kmem_free(pcic_range_p, range_len); 6027 return (DDI_SUCCESS); 6028 } 6029 6030 static int 6031 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 6032 { 6033 #ifdef CARDBUS 6034 if (cardbus_is_cb_minor(*dev)) 6035 return (cardbus_open(dev, flag, otyp, cred)); 6036 #endif 6037 return (EINVAL); 6038 } 6039 6040 static int 6041 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 6042 { 6043 #ifdef CARDBUS 6044 if (cardbus_is_cb_minor(dev)) 6045 return (cardbus_close(dev, flag, otyp, cred)); 6046 #endif 6047 return (EINVAL); 6048 } 6049 6050 static int 6051 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 6052 int *rval) 6053 { 6054 #ifdef CARDBUS 6055 if (cardbus_is_cb_minor(dev)) 6056 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6057 #endif 6058 return (EINVAL); 6059 } 6060 6061 6062 static boolean_t 6063 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6064 { 6065 uint32_t present_state; 6066 dev_info_t *dip = pcic->dip; 6067 set_socket_t s; 6068 get_socket_t g; 6069 boolean_t retval; 6070 unsigned vccLevel; 6071 6072 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6073 6074 pcic_mutex_exit(&pcic->pc_lock); 6075 6076 bzero(&s, sizeof (set_socket_t)); 6077 s.socket = sockp->pcs_socket; 6078 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6079 s.IFType = IF_CARDBUS; 6080 s.State = (unsigned)~0; 6081 6082 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6083 if (present_state & PCIC_VCC_3VCARD) 6084 s.VccLevel = PCIC_VCC_3VLEVEL; 6085 else if (present_state & PCIC_VCC_5VCARD) 6086 s.VccLevel = PCIC_VCC_5VLEVEL; 6087 else { 6088 cmn_err(CE_CONT, 6089 "pcic_load_cardbus: unsupported card voltage\n"); 6090 goto failure; 6091 } 6092 vccLevel = s.VccLevel; 6093 s.Vpp1Level = s.Vpp2Level = 0; 6094 6095 if (pcic_set_socket(dip, &s) != SUCCESS) 6096 goto failure; 6097 6098 if (pcic_reset_socket(dip, sockp->pcs_socket, 6099 RESET_MODE_CARD_ONLY) != SUCCESS) 6100 goto failure; 6101 6102 bzero(&g, sizeof (get_socket_t)); 6103 g.socket = sockp->pcs_socket; 6104 if (pcic_get_socket(dip, &g) != SUCCESS) 6105 goto failure; 6106 6107 bzero(&s, sizeof (set_socket_t)); 6108 s.socket = sockp->pcs_socket; 6109 s.SCIntMask = SBM_CD; 6110 s.IREQRouting = g.IRQRouting; 6111 s.IFType = g.IFType; 6112 s.CtlInd = g.CtlInd; 6113 s.State = (unsigned)~0; 6114 s.VccLevel = vccLevel; 6115 s.Vpp1Level = s.Vpp2Level = 0; 6116 6117 retval = pcic_set_socket(dip, &s); 6118 pcmcia_cb_resumed(s.socket); 6119 if (retval != SUCCESS) 6120 goto failure; 6121 6122 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6123 goto exit; 6124 6125 failure: 6126 retval = B_FALSE; 6127 6128 exit: 6129 pcic_mutex_enter(&pcic->pc_lock); 6130 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6131 retval ? "success" : "failure"); 6132 return (retval); 6133 } 6134 6135 static void 6136 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6137 { 6138 dev_info_t *dip = pcic->dip; 6139 set_socket_t s; 6140 6141 pcic_mutex_exit(&pcic->pc_lock); 6142 6143 cardbus_unload_cardbus(dip); 6144 6145 bzero(&s, sizeof (set_socket_t)); 6146 s.socket = sockp->pcs_socket; 6147 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6148 s.IREQRouting = 0; 6149 s.IFType = IF_MEMORY; 6150 s.CtlInd = 0; 6151 s.State = 0; 6152 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6153 6154 (void) pcic_set_socket(dip, &s); 6155 6156 pcic_mutex_enter(&pcic->pc_lock); 6157 } 6158 6159 static uint32_t 6160 pcic_getcb(pcicdev_t *pcic, int reg) 6161 { 6162 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6163 6164 return (ddi_get32(pcic->handle, 6165 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6166 } 6167 6168 static void 6169 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6170 { 6171 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6172 6173 ddi_put32(pcic->handle, 6174 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6175 } 6176 6177 static void 6178 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6179 { 6180 uint8_t value; 6181 uint16_t brdgctl; 6182 6183 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6184 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6185 6186 switch (pcic->pc_type) { 6187 case PCIC_INTEL_i82092: 6188 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6189 PCIC_82092_INT_ENABLE); 6190 break; 6191 case PCIC_O2_OZ6912: 6192 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6193 value |= 0x8; 6194 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6195 break; 6196 case PCIC_CL_PD6832: 6197 case PCIC_TI_PCI1250: 6198 case PCIC_TI_PCI1221: 6199 case PCIC_TI_PCI1225: 6200 case PCIC_TI_PCI1410: 6201 case PCIC_ENE_1410: 6202 case PCIC_TI_PCI1510: 6203 case PCIC_TI_PCI1520: 6204 case PCIC_TI_PCI1420: 6205 case PCIC_ENE_1420: 6206 /* route card functional interrupts to PCI interrupts */ 6207 brdgctl = ddi_get16(pcic->cfg_handle, 6208 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6209 pcic_err(NULL, 1, 6210 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6211 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6212 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6213 ddi_put16(pcic->cfg_handle, 6214 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6215 brdgctl); 6216 /* Flush the write */ 6217 (void) ddi_get16(pcic->cfg_handle, 6218 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6219 break; 6220 default: 6221 break; 6222 } 6223 } 6224 6225 static void 6226 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6227 { 6228 uint8_t value; 6229 uint16_t brdgctl; 6230 6231 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6232 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6233 6234 switch (pcic->pc_type) { 6235 case PCIC_INTEL_i82092: 6236 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6237 PCIC_82092_INT_DISABLE); 6238 break; 6239 case PCIC_O2_OZ6912: 6240 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6241 value &= ~0x8; 6242 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6243 /* Flush the write */ 6244 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6245 break; 6246 case PCIC_CL_PD6832: 6247 case PCIC_TI_PCI1250: 6248 case PCIC_TI_PCI1221: 6249 case PCIC_TI_PCI1225: 6250 case PCIC_TI_PCI1410: 6251 case PCIC_ENE_1410: 6252 case PCIC_TI_PCI1510: 6253 case PCIC_TI_PCI1520: 6254 case PCIC_TI_PCI1420: 6255 case PCIC_ENE_1420: 6256 /* 6257 * This maps I/O interrupts to ExCA which 6258 * have been turned off by the write to 6259 * PCIC_INTERRUPT above. It would appear to 6260 * be the only way to actually turn I/O Ints off 6261 * while retaining CS Ints. 6262 */ 6263 brdgctl = ddi_get16(pcic->cfg_handle, 6264 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6265 pcic_err(NULL, 1, 6266 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6267 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6268 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6269 ddi_put16(pcic->cfg_handle, 6270 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6271 brdgctl); 6272 /* Flush the write */ 6273 (void) ddi_get16(pcic->cfg_handle, 6274 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6275 break; 6276 default: 6277 break; 6278 } 6279 } 6280 6281 static void 6282 pcic_cb_enable_intr(dev_info_t *dip) 6283 { 6284 anp_t *anp = ddi_get_driver_private(dip); 6285 pcicdev_t *pcic = anp->an_private; 6286 6287 mutex_enter(&pcic->pc_lock); 6288 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6289 mutex_exit(&pcic->pc_lock); 6290 } 6291 6292 static void 6293 pcic_cb_disable_intr(dev_info_t *dip) 6294 { 6295 anp_t *anp = ddi_get_driver_private(dip); 6296 pcicdev_t *pcic = anp->an_private; 6297 6298 mutex_enter(&pcic->pc_lock); 6299 pcic_disable_io_intr(pcic, 0); 6300 mutex_exit(&pcic->pc_lock); 6301 } 6302 6303 static int 6304 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6305 { 6306 int nerr = 0; 6307 if (e & PCI_STAT_PERROR) { 6308 nerr++; 6309 cmn_err(CE_CONT, "detected parity error.\n"); 6310 } 6311 if (e & PCI_STAT_S_SYSERR) { 6312 nerr++; 6313 if (bridge_secondary) 6314 cmn_err(CE_CONT, "received system error.\n"); 6315 else 6316 cmn_err(CE_CONT, "signalled system error.\n"); 6317 } 6318 if (e & PCI_STAT_R_MAST_AB) { 6319 nerr++; 6320 cmn_err(CE_CONT, "received master abort.\n"); 6321 } 6322 if (e & PCI_STAT_R_TARG_AB) 6323 cmn_err(CE_CONT, "received target abort.\n"); 6324 if (e & PCI_STAT_S_TARG_AB) 6325 cmn_err(CE_CONT, "signalled target abort\n"); 6326 if (e & PCI_STAT_S_PERROR) { 6327 nerr++; 6328 cmn_err(CE_CONT, "signalled parity error\n"); 6329 } 6330 return (nerr); 6331 } 6332 6333 #if defined(__sparc) 6334 static int 6335 pcic_fault(enum pci_fault_ops op, void *arg) 6336 { 6337 pcicdev_t *pcic = (pcicdev_t *)arg; 6338 ushort_t pci_cfg_stat = 6339 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6340 ushort_t pci_cfg_sec_stat = 6341 pci_config_get16(pcic->cfg_handle, 0x16); 6342 char nm[24]; 6343 int nerr = 0; 6344 6345 cardbus_dump_pci_config(pcic->dip); 6346 6347 switch (op) { 6348 case FAULT_LOG: 6349 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6350 ddi_get_instance(pcic->dip)); 6351 6352 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6353 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6354 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6355 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6356 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6357 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6358 return (nerr); 6359 case FAULT_POKEFINI: 6360 case FAULT_RESET: 6361 pci_config_put16(pcic->cfg_handle, 6362 PCI_CONF_STAT, pci_cfg_stat); 6363 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6364 break; 6365 case FAULT_POKEFLT: 6366 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6367 return (1); 6368 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6369 return (1); 6370 break; 6371 default: 6372 break; 6373 } 6374 return (DDI_SUCCESS); 6375 } 6376 #endif 6377 6378 static void 6379 pcic_do_resume(pcicdev_t *pcic) 6380 { 6381 int i, interrupt; 6382 uint8_t cfg; 6383 6384 6385 #if defined(PCIC_DEBUG) 6386 pcic_err(NULL, 6, "pcic_do_resume(): entered\n"); 6387 #endif 6388 6389 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6390 for (i = 0; i < pcic->pc_numsockets; i++) { 6391 /* Enable interrupts on PCI if needs be */ 6392 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6393 if (pcic->pc_flags & PCF_USE_SMI) 6394 interrupt |= PCIC_INTR_ENABLE; 6395 pcic_putb(pcic, i, PCIC_INTERRUPT, 6396 PCIC_RESET | interrupt); 6397 pcic->pc_sockets[i].pcs_debounce_id = 6398 pcic_add_debqueue(&pcic->pc_sockets[i], 6399 drv_usectohz(pcic_debounce_time)); 6400 } 6401 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6402 if (pcic_do_pcmcia_sr) 6403 (void) pcmcia_wait_insert(pcic->dip); 6404 /* 6405 * The CardBus controller may be in RESET state after the 6406 * system is resumed from sleeping. The RESET bit is in 6407 * the Bridge Control register. This is true for all(TI, 6408 * Toshiba ToPIC95/97, RICOH, and O2Micro) CardBus 6409 * controllers. Need to clear the RESET bit explicitly. 6410 */ 6411 cfg = ddi_get8(pcic->cfg_handle, 6412 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 6413 if (cfg & (1<<6)) { 6414 cfg &= ~(1<<6); 6415 ddi_put8(pcic->cfg_handle, 6416 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 6417 cfg); 6418 cfg = ddi_get8(pcic->cfg_handle, 6419 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 6420 if (cfg & (1<<6)) { 6421 pcic_err(pcic->dip, 1, 6422 "Failed to take pcic out of reset"); 6423 } 6424 } 6425 6426 } 6427 6428 static void 6429 pcic_debounce(pcic_socket_t *pcs) 6430 { 6431 uint8_t status, stschng; 6432 6433 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6434 pcs->pcs_flags &= ~PCS_STARTING; 6435 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6436 PCIC_CARD_STATUS_CHANGE); 6437 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6438 PCIC_INTERFACE_STATUS); 6439 #ifdef PCIC_DEBUG 6440 pcic_err(pcs->pcs_pcic->dip, 8, 6441 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6442 "chg 0x%x flg 0x%x\n", 6443 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6444 status, stschng, pcs->pcs_flags); 6445 #endif 6446 6447 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6448 PCIC_CD_DETECT); 6449 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6450 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6451 } 6452 6453 static void 6454 pcic_deb_thread() 6455 { 6456 callb_cpr_t cprinfo; 6457 struct debounce *debp; 6458 clock_t lastt; 6459 6460 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6461 callb_generic_cpr, "pcic debounce thread"); 6462 mutex_enter(&pcic_deb_mtx); 6463 while (pcic_deb_threadid) { 6464 while (pcic_deb_queue) { 6465 #ifdef PCIC_DEBUG 6466 pcic_dump_debqueue("Thread"); 6467 #endif 6468 debp = pcic_deb_queue; 6469 (void) drv_getparm(LBOLT, &lastt); 6470 if (lastt >= debp->expire) { 6471 pcic_deb_queue = debp->next; 6472 mutex_exit(&pcic_deb_mtx); 6473 pcic_debounce(debp->pcs); 6474 mutex_enter(&pcic_deb_mtx); 6475 kmem_free(debp, sizeof (*debp)); 6476 } else { 6477 (void) cv_timedwait(&pcic_deb_cv, 6478 &pcic_deb_mtx, debp->expire); 6479 } 6480 } 6481 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6482 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6483 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6484 } 6485 pcic_deb_threadid = (kthread_t *)1; 6486 cv_signal(&pcic_deb_cv); 6487 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6488 thread_exit(); 6489 } 6490 6491 static void * 6492 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6493 { 6494 clock_t lbolt; 6495 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6496 6497 (void) drv_getparm(LBOLT, &lbolt); 6498 dbp = kmem_alloc(sizeof (struct debounce), KM_SLEEP); 6499 6500 dbp->expire = lbolt + clocks; 6501 dbp->pcs = pcs; 6502 mutex_enter(&pcic_deb_mtx); 6503 while (*dbpp) { 6504 if (dbp->expire > (*dbpp)->expire) 6505 dbpp = &((*dbpp)->next); 6506 else 6507 break; 6508 } 6509 dbp->next = *dbpp; 6510 *dbpp = dbp; 6511 #ifdef PCIC_DEBUG 6512 pcic_dump_debqueue("Add"); 6513 #endif 6514 cv_signal(&pcic_deb_cv); 6515 mutex_exit(&pcic_deb_mtx); 6516 return (dbp); 6517 } 6518 6519 static void 6520 pcic_rm_debqueue(void *id) 6521 { 6522 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6523 6524 dbp = (struct debounce *)id; 6525 mutex_enter(&pcic_deb_mtx); 6526 while (*dbpp) { 6527 if (*dbpp == dbp) { 6528 *dbpp = dbp->next; 6529 kmem_free(dbp, sizeof (*dbp)); 6530 #ifdef PCIC_DEBUG 6531 pcic_dump_debqueue("Remove"); 6532 #endif 6533 cv_signal(&pcic_deb_cv); 6534 mutex_exit(&pcic_deb_mtx); 6535 return; 6536 } 6537 dbpp = &((*dbpp)->next); 6538 } 6539 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6540 mutex_exit(&pcic_deb_mtx); 6541 } 6542 6543 6544 static int pcic_powerdelay = 0; 6545 6546 static int 6547 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6548 { 6549 int ind, value, orig_pwrctl; 6550 6551 /* power setup -- if necessary */ 6552 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6553 6554 #if defined(PCIC_DEBUG) 6555 pcic_err(pcic->dip, 6, 6556 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6557 socket, powerlevel, orig_pwrctl); 6558 #endif 6559 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6560 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6561 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6562 if (powerlevel != orig_pwrctl) { 6563 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6564 int ifs; 6565 /* 6566 * set power to socket 6567 * note that the powerlevel was calculated earlier 6568 */ 6569 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6570 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6571 6572 /* 6573 * this second write to the power control register 6574 * is needed to resolve a problem on 6575 * the IBM ThinkPad 750 6576 * where the first write doesn't latch. 6577 * The second write appears to always work and 6578 * doesn't hurt the operation of other chips 6579 * so we can just use it -- this is good since we can't 6580 * determine what chip the 750 actually uses 6581 * (I suspect an early Ricoh). 6582 */ 6583 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6584 6585 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6586 pcic_mswait(pcic, socket, pcic_powerdelay); 6587 #if defined(PCIC_DEBUG) 6588 pcic_err(pcic->dip, 8, 6589 "\tpowerlevel reg = %x (ifs %x)\n", 6590 value, pcic_getb(pcic, socket, 6591 PCIC_INTERFACE_STATUS)); 6592 pcic_err(pcic->dip, 8, 6593 "CBus regs: PS 0x%x, Control 0x%x\n", 6594 pcic_getcb(pcic, CB_PRESENT_STATE), 6595 pcic_getcb(pcic, CB_CONTROL)); 6596 #endif 6597 /* 6598 * since power was touched, make sure it says it 6599 * is on. This lets it become stable. 6600 */ 6601 for (ind = 0; ind < 20; ind++) { 6602 ifs = pcic_getb(pcic, socket, 6603 PCIC_INTERFACE_STATUS); 6604 if (ifs & PCIC_POWER_ON) 6605 break; 6606 else { 6607 pcic_putb(pcic, socket, 6608 PCIC_POWER_CONTROL, 0); 6609 (void) pcic_getb(pcic, socket, 6610 PCIC_POWER_CONTROL); 6611 pcic_mswait(pcic, socket, 40); 6612 if (ind == 10) { 6613 pcic_putcb(pcic, CB_EVENT_FORCE, 6614 CB_EF_CVTEST); 6615 pcic_mswait(pcic, socket, 100); 6616 } 6617 pcic_putb(pcic, socket, 6618 PCIC_POWER_CONTROL, 6619 powerlevel & ~POWER_OUTPUT_ENABLE); 6620 (void) pcic_getb(pcic, socket, 6621 PCIC_POWER_CONTROL); 6622 pcic_mswait(pcic, socket, 6623 pcic_powerdelay); 6624 pcic_putb(pcic, socket, 6625 PCIC_POWER_CONTROL, powerlevel); 6626 (void) pcic_getb(pcic, socket, 6627 PCIC_POWER_CONTROL); 6628 pcic_mswait(pcic, socket, 6629 pcic_powerdelay); 6630 } 6631 } 6632 6633 if (!(ifs & PCIC_POWER_ON)) { 6634 cmn_err(CE_WARN, 6635 "pcic socket %d: Power didn't get turned" 6636 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6637 "misc1 0x%x igc 0x%x ind %d\n", 6638 socket, ifs, 6639 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6640 orig_pwrctl, 6641 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6642 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6643 ind); 6644 return (BAD_VCC); 6645 } 6646 #if defined(PCIC_DEBUG) 6647 pcic_err(pcic->dip, 8, 6648 "\tind = %d, if status %x pwrc 0x%x " 6649 "misc1 0x%x igc 0x%x\n", 6650 ind, ifs, 6651 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6652 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6653 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6654 #endif 6655 } else { 6656 /* explicitly turned off the power */ 6657 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6658 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6659 } 6660 } 6661 return (SUCCESS); 6662 } 6663 6664 static int pcic_cbdoreset_during_poweron = 1; 6665 static int 6666 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6667 { 6668 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6669 int ind, iobits; 6670 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6671 6672 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6673 6674 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6675 cbctl |= pcic_cbv_levels[ind]; 6676 6677 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6678 cbctl |= (pcic_cbv_levels[ind]<<4); 6679 6680 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6681 6682 #if defined(PCIC_DEBUG) 6683 pcic_err(pcic->dip, 6, 6684 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6685 "cbctl 0x%x->0x%x\n", 6686 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6687 #endif 6688 if (cbctl != orig_cbctl) { 6689 if (pcic_cbdoreset_during_poweron && 6690 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6691 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6692 pcic_putb(pcic, socket, PCIC_INTERRUPT, 6693 iobits & ~PCIC_RESET); 6694 } 6695 pcic_putcb(pcic, CB_CONTROL, cbctl); 6696 6697 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6698 pcic_mswait(pcic, socket, pcic_powerdelay); 6699 return (SUCCESS); 6700 } 6701 for (ind = 0; ind < 20; ind++) { 6702 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6703 6704 if (cbstev & CB_SE_POWER_CYCLE) { 6705 6706 /* 6707 * delay 400 ms: though the standard defines that the Vcc 6708 * set-up time is 20 ms, some PC-Card bridge requires longer 6709 * duration. 6710 * Note: We should check the status AFTER the delay to give time 6711 * for things to stabilize. 6712 */ 6713 pcic_mswait(pcic, socket, 400); 6714 6715 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6716 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6717 /* break; */ 6718 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6719 } 6720 if (cbctl & CB_PS_BADVCC) { 6721 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6722 break; 6723 } 6724 6725 #if defined(PCIC_DEBUG) 6726 pcic_err(pcic->dip, 8, 6727 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6728 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6729 cbctl, orig_cbctl); 6730 #endif 6731 if (pcic_cbdoreset_during_poweron && 6732 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6733 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6734 } 6735 return (SUCCESS); 6736 } 6737 pcic_mswait(pcic, socket, 40); 6738 } 6739 if (pcic_cbdoreset_during_poweron && 6740 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6741 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6742 } 6743 cmn_err(CE_WARN, 6744 "pcic socket %d: Power didn't get turned on/off!\n" 6745 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6746 "vcc %d vpp1 %d", socket, cbstev, 6747 pcic_getcb(pcic, CB_PRESENT_STATE), 6748 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6749 return (BAD_VCC); 6750 } 6751 return (SUCCESS); 6752 } 6753 6754 static int pcic_do_pprintf = 0; 6755 6756 static void 6757 pcic_dump_debqueue(char *msg) 6758 { 6759 struct debounce *debp = pcic_deb_queue; 6760 clock_t lbolt; 6761 6762 (void) drv_getparm(LBOLT, &lbolt); 6763 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6764 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6765 while (debp) { 6766 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6767 (void *) debp, (int)debp->expire, (void *) debp->next, 6768 debp->pcs->pcs_debounce_id); 6769 debp = debp->next; 6770 } 6771 } 6772 6773 6774 /* PRINTFLIKE3 */ 6775 static void 6776 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6777 { 6778 if (pcic_debug && (level <= pcic_debug)) { 6779 va_list adx; 6780 int instance; 6781 char buf[256]; 6782 const char *name; 6783 #if !defined(PCIC_DEBUG) 6784 int ce; 6785 char qmark = 0; 6786 6787 if (level <= 3) 6788 ce = CE_WARN; 6789 else 6790 ce = CE_CONT; 6791 if (level == 4) 6792 qmark = 1; 6793 #endif 6794 6795 if (dip) { 6796 instance = ddi_get_instance(dip); 6797 /* name = ddi_binding_name(dip); */ 6798 name = ddi_driver_name(dip); 6799 } else { 6800 instance = 0; 6801 name = ""; 6802 } 6803 6804 va_start(adx, fmt); 6805 (void) vsprintf(buf, fmt, adx); 6806 va_end(adx); 6807 6808 #if defined(PCIC_DEBUG) 6809 if (pcic_do_pprintf) { 6810 if (dip) { 6811 if (instance >= 0) 6812 prom_printf("%s(%d),0x%p: %s", name, 6813 instance, (void *)dip, buf); 6814 else 6815 prom_printf("%s,0x%p: %s", 6816 name, (void *)dip, buf); 6817 } else 6818 prom_printf(buf); 6819 } else { 6820 if (dip) { 6821 if (instance >= 0) 6822 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6823 name, instance, (void *) dip, buf); 6824 else 6825 cmn_err(CE_CONT, "%s,0x%p: %s", 6826 name, (void *) dip, buf); 6827 } else 6828 cmn_err(CE_CONT, buf); 6829 } 6830 #else 6831 if (dip) 6832 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6833 instance, buf); 6834 else 6835 cmn_err(ce, qmark ? "?%s" : buf, buf); 6836 #endif 6837 } 6838 } 6839