1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCIC device/interrupt handler 31 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 32 * and Toshiba (and possibly other clones) PCMCIA adapter chip 33 * sets. It implements a subset of Socket Services as defined 34 * in the Solaris PCMCIA design documents 35 */ 36 37 /* 38 * currently defined "properties" 39 * 40 * clock-frequency bus clock frequency 41 * smi system management interrupt override 42 * need-mult-irq need status IRQ for each pair of sockets 43 * disable-audio don't route audio signal to speaker 44 */ 45 46 47 #include <sys/types.h> 48 #include <sys/inttypes.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/user.h> 52 #include <sys/buf.h> 53 #include <sys/file.h> 54 #include <sys/uio.h> 55 #include <sys/conf.h> 56 #include <sys/stat.h> 57 #include <sys/autoconf.h> 58 #include <sys/vtoc.h> 59 #include <sys/dkio.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/sunndi.h> 63 #include <sys/var.h> 64 #include <sys/callb.h> 65 #include <sys/open.h> 66 #include <sys/ddidmareq.h> 67 #include <sys/dma_engine.h> 68 #include <sys/kstat.h> 69 #include <sys/kmem.h> 70 #include <sys/modctl.h> 71 #include <sys/pci.h> 72 #include <sys/pci_impl.h> 73 74 #include <sys/pctypes.h> 75 #include <sys/pcmcia.h> 76 #include <sys/sservice.h> 77 78 #include <sys/note.h> 79 80 #include <sys/pcic_reg.h> 81 #include <sys/pcic_var.h> 82 83 #if defined(__sparc) 84 #include <sys/pci/pci_nexus.h> 85 #endif 86 87 #include <sys/hotplug/hpcsvc.h> 88 #include "cardbus/cardbus.h" 89 90 #define SOFTC_SIZE (sizeof (anp_t)) 91 92 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 93 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 94 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 95 static uint_t pcic_intr(caddr_t, caddr_t); 96 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 97 static int pcic_probe(dev_info_t *); 98 99 static int pcic_open(dev_t *, int, int, cred_t *); 100 static int pcic_close(dev_t, int, int, cred_t *); 101 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 102 103 typedef struct pcm_regs pcm_regs_t; 104 105 static void pcic_init_assigned(dev_info_t *); 106 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 107 pci_regspec_t *, int); 108 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 109 110 /* 111 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 112 * are xlated into DMA ctlops. To make this nexus work on x86, we 113 * need to have the default ddi_dma_mctl ctlops in the bus_ops 114 * structure, just to pass the request to the parent. The correct 115 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 116 */ 117 static 118 struct bus_ops pcmciabus_ops = { 119 BUSO_REV, 120 pcmcia_bus_map, 121 NULL, 122 NULL, 123 NULL, 124 i_ddi_map_fault, 125 ddi_no_dma_map, 126 ddi_no_dma_allochdl, 127 ddi_no_dma_freehdl, 128 ddi_no_dma_bindhdl, 129 ddi_no_dma_unbindhdl, 130 ddi_no_dma_flush, 131 ddi_no_dma_win, 132 ddi_dma_mctl, 133 pcmcia_ctlops, 134 pcmcia_prop_op, 135 NULL, /* (*bus_get_eventcookie)(); */ 136 NULL, /* (*bus_add_eventcall)(); */ 137 NULL, /* (*bus_remove_eventcall)(); */ 138 NULL, /* (*bus_post_event)(); */ 139 NULL, /* (*bus_intr_ctl)(); */ 140 NULL, /* (*bus_config)(); */ 141 NULL, /* (*bus_unconfig)(); */ 142 NULL, /* (*bus_fm_init)(); */ 143 NULL, /* (*bus_fm_fini)(); */ 144 NULL, /* (*bus_enter)() */ 145 NULL, /* (*bus_exit)() */ 146 NULL, /* (*bus_power)() */ 147 pcmcia_intr_ops /* (*bus_intr_op)(); */ 148 }; 149 150 static struct cb_ops pcic_cbops = { 151 pcic_open, 152 pcic_close, 153 nodev, 154 nodev, 155 nodev, 156 nodev, 157 nodev, 158 pcic_ioctl, 159 nodev, 160 nodev, 161 nodev, 162 nochpoll, 163 ddi_prop_op, 164 NULL, 165 #ifdef CARDBUS 166 D_NEW | D_MP | D_HOTPLUG 167 #else 168 D_NEW | D_MP 169 #endif 170 }; 171 172 static struct dev_ops pcic_devops = { 173 DEVO_REV, 174 0, 175 pcic_getinfo, 176 nulldev, 177 pcic_probe, 178 pcic_attach, 179 pcic_detach, 180 nulldev, 181 &pcic_cbops, 182 &pcmciabus_ops, 183 NULL 184 }; 185 186 void *pcic_soft_state_p = NULL; 187 static int pcic_maxinst = -1; 188 189 int pcic_do_insertion = 1; 190 int pcic_do_removal = 1; 191 192 struct irqmap { 193 int irq; 194 int count; 195 } pcic_irq_map[16]; 196 197 198 int pcic_debug = 0x0; 199 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 200 extern void cardbus_dump_pci_config(dev_info_t *dip); 201 extern void cardbus_dump_socket(dev_info_t *dip); 202 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 203 static void pcic_dump_debqueue(char *msg); 204 205 #if defined(PCIC_DEBUG) 206 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 207 208 #define pcic_mutex_enter(a) \ 209 { \ 210 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 211 mutex_enter(a); \ 212 }; 213 214 #define pcic_mutex_exit(a) \ 215 { \ 216 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 217 mutex_exit(a); \ 218 }; 219 220 #else 221 #define pcic_mutex_enter(a) mutex_enter(a) 222 #define pcic_mutex_exit(a) mutex_exit(a) 223 #endif 224 225 #define PCIC_VCC_3VLEVEL 1 226 #define PCIC_VCC_5VLEVEL 2 227 #define PCIC_VCC_12LEVEL 3 228 229 /* bit patterns to select voltage levels */ 230 int pcic_vpp_levels[13] = { 231 0, 0, 0, 232 1, /* 3.3V */ 233 0, 234 1, /* 5V */ 235 0, 0, 0, 0, 0, 0, 236 2 /* 12V */ 237 }; 238 239 uint8_t pcic_cbv_levels[13] = { 240 0, 0, 0, 241 3, /* 3.3V */ 242 0, 243 2, /* 5V */ 244 0, 0, 0, 0, 0, 0, 245 1 /* 12V */ 246 }; 247 248 struct power_entry pcic_power[4] = { 249 { 250 0, VCC|VPP1|VPP2 251 }, 252 { 253 33, /* 3.3Volt */ 254 VCC|VPP1|VPP2 255 }, 256 { 257 5*10, /* 5Volt */ 258 VCC|VPP1|VPP2 /* currently only know about this */ 259 }, 260 { 261 12*10, /* 12Volt */ 262 VPP1|VPP2 263 } 264 }; 265 266 /* 267 * Base used to allocate ranges of PCI memory on x86 systems 268 * Each instance gets a chunk above the base that is used to map 269 * in the memory and I/O windows for that device. 270 * Pages below the base are also allocated for the EXCA registers, 271 * one per instance. 272 */ 273 #define PCIC_PCI_MEMCHUNK 0x1000000 274 275 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 276 static int pcic_debounce_time = 200000; /* In micro-seconds */ 277 278 struct debounce { 279 pcic_socket_t *pcs; 280 clock_t expire; 281 struct debounce *next; 282 }; 283 284 static struct debounce *pcic_deb_queue = NULL; 285 static kmutex_t pcic_deb_mtx; 286 static kcondvar_t pcic_deb_cv; 287 static kthread_t *pcic_deb_threadid; 288 289 static inthandler_t *pcic_handlers; 290 291 static void pcic_setup_adapter(pcicdev_t *); 292 static int pcic_change(pcicdev_t *, int); 293 static int pcic_ll_reset(pcicdev_t *, int); 294 static void pcic_mswait(pcicdev_t *, int, int); 295 static boolean_t pcic_check_ready(pcicdev_t *, int); 296 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 297 static void pcic_ready_wait(pcicdev_t *, int); 298 extern int pcmcia_get_intr(dev_info_t *, int); 299 extern int pcmcia_return_intr(dev_info_t *, int); 300 extern void pcmcia_cb_suspended(int); 301 extern void pcmcia_cb_resumed(int); 302 303 static int pcic_callback(dev_info_t *, int (*)(), int); 304 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 305 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 306 static int pcic_get_page(dev_info_t *, get_page_t *); 307 static int pcic_get_socket(dev_info_t *, get_socket_t *); 308 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 309 static int pcic_get_window(dev_info_t *, get_window_t *); 310 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 311 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 312 static int pcic_reset_socket(dev_info_t *, int, int); 313 static int pcic_set_page(dev_info_t *, set_page_t *); 314 static int pcic_set_window(dev_info_t *, set_window_t *); 315 static int pcic_set_socket(dev_info_t *, set_socket_t *); 316 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 317 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 318 static void pcic_pm_detection(void *); 319 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 320 static int clext_reg_read(pcicdev_t *, int, uchar_t); 321 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 322 static int pcic_calc_speed(pcicdev_t *, uint32_t); 323 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 324 static int pcic_find_pci_type(pcicdev_t *); 325 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 326 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 327 static uint_t pcic_cd_softint(caddr_t, caddr_t); 328 static uint8_t pcic_getb(pcicdev_t *, int, int); 329 static void pcic_putb(pcicdev_t *, int, int, int8_t); 330 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 331 static uint_t pcic_softintr(caddr_t, caddr_t); 332 333 static void pcic_debounce(pcic_socket_t *); 334 static void pcic_do_resume(pcicdev_t *); 335 static void *pcic_add_debqueue(pcic_socket_t *, int); 336 static void pcic_rm_debqueue(void *); 337 static void pcic_deb_thread(); 338 339 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 340 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 341 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 342 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 343 static void pcic_cb_enable_intr(dev_info_t *); 344 static void pcic_cb_disable_intr(dev_info_t *); 345 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 346 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 347 348 static cb_nexus_cb_t pcic_cbnexus_ops = { 349 pcic_cb_enable_intr, 350 pcic_cb_disable_intr 351 }; 352 353 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 354 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 355 356 #if defined(__sparc) 357 static int pcic_fault(enum pci_fault_ops op, void *arg); 358 #endif 359 360 361 /* 362 * pcmcia interface operations structure 363 * this is the private interface that is exported to the nexus 364 */ 365 pcmcia_if_t pcic_if_ops = { 366 PCIF_MAGIC, 367 PCIF_VERSION, 368 pcic_callback, 369 pcic_get_adapter, 370 pcic_get_page, 371 pcic_get_socket, 372 pcic_get_status, 373 pcic_get_window, 374 pcic_inquire_adapter, 375 pcic_inquire_socket, 376 pcic_inquire_window, 377 pcic_reset_socket, 378 pcic_set_page, 379 pcic_set_window, 380 pcic_set_socket, 381 pcic_set_interrupt, 382 pcic_clear_interrupt, 383 NULL, 384 }; 385 386 /* 387 * chip type identification routines 388 * this list of functions is searched until one of them succeeds 389 * or all fail. i82365SL is assumed if failed. 390 */ 391 static int pcic_ci_cirrus(pcicdev_t *); 392 static int pcic_ci_vadem(pcicdev_t *); 393 static int pcic_ci_ricoh(pcicdev_t *); 394 395 int (*pcic_ci_funcs[])(pcicdev_t *) = { 396 pcic_ci_cirrus, 397 pcic_ci_vadem, 398 pcic_ci_ricoh, 399 NULL 400 }; 401 402 static struct modldrv modldrv = { 403 &mod_driverops, /* Type of module. This one is a driver */ 404 "PCIC PCMCIA adapter driver %I%", /* Name of the module. */ 405 &pcic_devops, /* driver ops */ 406 }; 407 408 static struct modlinkage modlinkage = { 409 MODREV_1, (void *)&modldrv, NULL 410 }; 411 412 int 413 _init() 414 { 415 int stat; 416 417 /* Allocate soft state */ 418 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 419 SOFTC_SIZE, 2)) != DDI_SUCCESS) 420 return (stat); 421 422 if ((stat = mod_install(&modlinkage)) != 0) 423 ddi_soft_state_fini(&pcic_soft_state_p); 424 425 return (stat); 426 } 427 428 int 429 _fini() 430 { 431 int stat = 0; 432 433 if ((stat = mod_remove(&modlinkage)) != 0) 434 return (stat); 435 436 if (pcic_deb_threadid) { 437 mutex_enter(&pcic_deb_mtx); 438 pcic_deb_threadid = 0; 439 while (!pcic_deb_threadid) 440 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 441 pcic_deb_threadid = 0; 442 mutex_exit(&pcic_deb_mtx); 443 444 mutex_destroy(&pcic_deb_mtx); 445 cv_destroy(&pcic_deb_cv); 446 } 447 448 ddi_soft_state_fini(&pcic_soft_state_p); 449 450 return (stat); 451 } 452 453 int 454 _info(struct modinfo *modinfop) 455 { 456 return (mod_info(&modlinkage, modinfop)); 457 } 458 459 /* 460 * pcic_getinfo() 461 * provide instance/device information about driver 462 */ 463 /*ARGSUSED*/ 464 static int 465 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 466 { 467 anp_t *anp; 468 int error = DDI_SUCCESS; 469 minor_t minor; 470 471 switch (cmd) { 472 case DDI_INFO_DEVT2DEVINFO: 473 minor = getminor((dev_t)arg); 474 minor &= 0x7f; 475 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 476 *result = NULL; 477 else 478 *result = anp->an_dip; 479 break; 480 case DDI_INFO_DEVT2INSTANCE: 481 minor = getminor((dev_t)arg); 482 minor &= 0x7f; 483 *result = (void *)((long)minor); 484 break; 485 default: 486 error = DDI_FAILURE; 487 break; 488 } 489 return (error); 490 } 491 492 static int 493 pcic_probe(dev_info_t *dip) 494 { 495 int value; 496 ddi_device_acc_attr_t attr; 497 ddi_acc_handle_t handle; 498 uchar_t *index, *data; 499 500 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 501 return (DDI_PROBE_DONTCARE); 502 503 /* 504 * find a PCIC device (any vendor) 505 * while there can be up to 4 such devices in 506 * a system, we currently only look for 1 507 * per probe. There will be up to 2 chips per 508 * instance since they share I/O space 509 */ 510 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 511 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 512 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 513 514 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 515 (caddr_t *)&index, 516 PCIC_ISA_CONTROL_REG_OFFSET, 517 PCIC_ISA_CONTROL_REG_LENGTH, 518 &attr, &handle) != DDI_SUCCESS) 519 return (DDI_PROBE_FAILURE); 520 521 data = index + 1; 522 523 #if defined(PCIC_DEBUG) 524 if (pcic_debug) 525 cmn_err(CE_CONT, "pcic_probe: entered\n"); 526 if (pcic_debug) 527 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 528 #endif 529 ddi_put8(handle, index, PCIC_CHIP_REVISION); 530 ddi_put8(handle, data, 0); 531 value = ddi_get8(handle, data); 532 #if defined(PCIC_DEBUG) 533 if (pcic_debug) 534 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 535 #endif 536 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 537 (value & 0x30) == 0) { 538 /* 539 * we probably have a PCIC chip in the system 540 * do a little more checking. If we find one, 541 * reset everything in case of softboot 542 */ 543 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 544 ddi_put8(handle, data, 0); 545 value = ddi_get8(handle, data); 546 #if defined(PCIC_DEBUG) 547 if (pcic_debug) 548 cmn_err(CE_CONT, "\tzero test = %x\n", value); 549 #endif 550 /* should read back as zero */ 551 if (value == 0) { 552 /* 553 * we do have one and it is off the bus 554 */ 555 #if defined(PCIC_DEBUG) 556 if (pcic_debug) 557 cmn_err(CE_CONT, "pcic_probe: success\n"); 558 #endif 559 ddi_regs_map_free(&handle); 560 return (DDI_PROBE_SUCCESS); 561 } 562 } 563 #if defined(PCIC_DEBUG) 564 if (pcic_debug) 565 cmn_err(CE_CONT, "pcic_probe: failed\n"); 566 #endif 567 ddi_regs_map_free(&handle); 568 return (DDI_PROBE_FAILURE); 569 } 570 571 /* 572 * These are just defaults they can also be changed via a property in the 573 * conf file. 574 */ 575 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 576 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 577 static int pcic_do_pcmcia_sr = 1; 578 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 579 580 /* 581 * enable insertion/removal interrupt for 32bit cards 582 */ 583 static int 584 cardbus_enable_cd_intr(dev_info_t *dip) 585 { 586 ddi_acc_handle_t iohandle; 587 caddr_t ioaddr; 588 ddi_device_acc_attr_t attr; 589 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 590 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 591 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 592 (void) ddi_regs_map_setup(dip, 1, 593 (caddr_t *)&ioaddr, 594 0, 595 4096, 596 &attr, &iohandle); 597 598 /* CSC Interrupt: Card detect interrupt on */ 599 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 600 ddi_get32(iohandle, 601 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 602 603 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 604 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 605 606 ddi_regs_map_free(&iohandle); 607 return (1); 608 } 609 610 /* 611 * pcic_attach() 612 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 613 * to the system. This is a child of "sysbus" since that is where 614 * the hardware lives, but it provides services to the "pcmcia" 615 * nexus driver. It gives a pointer back via its private data 616 * structure which contains both the dip and socket services entry 617 * points 618 */ 619 static int 620 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 621 { 622 anp_t *pcic_nexus; 623 pcicdev_t *pcic; 624 int irqlevel, value; 625 int pci_cfrn, pci_ctrn; 626 int i, j, smi, actual; 627 char *typename; 628 char bus_type[16] = "(unknown)"; 629 int len = sizeof (bus_type); 630 ddi_device_acc_attr_t attr; 631 anp_t *anp = ddi_get_driver_private(dip); 632 uint_t pri; 633 634 #if defined(PCIC_DEBUG) 635 if (pcic_debug) { 636 cmn_err(CE_CONT, "pcic_attach: entered\n"); 637 } 638 #endif 639 switch (cmd) { 640 case DDI_ATTACH: 641 break; 642 case DDI_RESUME: 643 pcic = anp->an_private; 644 /* 645 * for now, this is a simulated resume. 646 * a real one may need different things. 647 */ 648 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 649 mutex_enter(&pcic->pc_lock); 650 /* should probe for new sockets showing up */ 651 pcic_setup_adapter(pcic); 652 pcic->pc_flags &= ~PCF_SUSPENDED; 653 mutex_exit(&pcic->pc_lock); 654 (void) pcmcia_begin_resume(dip); 655 656 pcic_do_resume(pcic); 657 #ifdef CARDBUS 658 cardbus_restore_children(ddi_get_child(dip)); 659 #endif 660 661 /* 662 * for complete implementation need END_RESUME (later) 663 */ 664 return (DDI_SUCCESS); 665 666 } 667 return (DDI_SUCCESS); 668 default: 669 return (DDI_FAILURE); 670 } 671 672 /* 673 * Allocate soft state associated with this instance. 674 */ 675 if (ddi_soft_state_zalloc(pcic_soft_state_p, 676 ddi_get_instance(dip)) != DDI_SUCCESS) { 677 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 678 ddi_get_instance(dip)); 679 return (DDI_FAILURE); 680 } 681 682 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 683 ddi_get_instance(dip)); 684 685 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 686 687 pcic->dip = dip; 688 pcic_nexus->an_dip = dip; 689 pcic_nexus->an_if = &pcic_if_ops; 690 pcic_nexus->an_private = pcic; 691 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 692 pcic->pc_power = pcic_power; 693 694 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 695 "pci-control-reg-number", pci_control_reg_num); 696 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 697 "pci-config-reg-number", pci_config_reg_num); 698 699 ddi_set_driver_private(dip, pcic_nexus); 700 701 /* 702 * pcic->pc_irq is really the IPL level we want to run at 703 * set the default values here and override from intr spec 704 */ 705 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 706 "interrupt-priorities", -1); 707 708 if (pcic->pc_irq == -1) { 709 int actual; 710 uint_t pri; 711 ddi_intr_handle_t hdl; 712 713 /* see if intrspec tells us different */ 714 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 715 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 716 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 717 pcic->pc_irq = pri; 718 else 719 pcic->pc_irq = LOCK_LEVEL + 1; 720 (void) ddi_intr_free(hdl); 721 } 722 } 723 pcic_nexus->an_ipl = pcic->pc_irq; 724 725 /* 726 * Check our parent bus type. We do different things based on which 727 * bus we're on. 728 */ 729 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 730 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 731 "device_type", (caddr_t)&bus_type[0], &len) != 732 DDI_PROP_SUCCESS) { 733 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 734 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 735 "bus-type", (caddr_t)&bus_type[0], &len) != 736 DDI_PROP_SUCCESS) { 737 738 cmn_err(CE_CONT, 739 "pcic%d: can't find parent bus type\n", 740 ddi_get_instance(dip)); 741 742 kmem_free(pcic, sizeof (pcicdev_t)); 743 ddi_soft_state_free(pcic_soft_state_p, 744 ddi_get_instance(dip)); 745 return (DDI_FAILURE); 746 } 747 } /* ddi_prop_op("device_type") */ 748 749 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 750 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) { 751 pcic->pc_flags = PCF_PCIBUS; 752 } else { 753 cmn_err(CE_WARN, "!pcic%d: non-pci mode (%s) not supported, " 754 "set BIOS to yenta mode if applicable\n", 755 ddi_get_instance(dip), bus_type); 756 kmem_free(pcic, sizeof (pcicdev_t)); 757 ddi_soft_state_free(pcic_soft_state_p, 758 ddi_get_instance(dip)); 759 return (DDI_FAILURE); 760 } 761 762 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 763 DDI_PROP_CANSLEEP, 764 "clock-frequency", 0)) == 0) { 765 if (pcic->pc_flags & PCF_PCIBUS) 766 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 767 else 768 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 769 } else { 770 /* 771 * OBP can declare the speed in Hz... 772 */ 773 if (pcic->bus_speed > 1000000) 774 pcic->bus_speed /= 1000000; 775 } /* ddi_prop_op("clock-frequency") */ 776 777 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 778 779 #ifdef PCIC_DEBUG 780 if (pcic_debug) { 781 cmn_err(CE_CONT, 782 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 783 ddi_get_instance(dip), 784 bus_type, pcic->bus_speed); 785 } 786 #endif 787 788 /* 789 * The reg properties on a PCI node are different than those 790 * on a non-PCI node. Handle that difference here. 791 * If it turns out to be a CardBus chip, we have even more 792 * differences. 793 */ 794 if (pcic->pc_flags & PCF_PCIBUS) { 795 int class_code; 796 #if defined(__i386) || defined(__amd64) 797 pcic->pc_base = 0x1000000; 798 pcic->pc_bound = (uint32_t)~0; 799 pcic->pc_iobase = 0x1000; 800 pcic->pc_iobound = 0xefff; 801 #elif defined(__sparc) 802 pcic->pc_base = 0x0; 803 pcic->pc_bound = (uint32_t)~0; 804 pcic->pc_iobase = 0x00000; 805 pcic->pc_iobound = 0xffff; 806 #endif 807 808 /* usually need to get at config space so map first */ 809 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 810 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 811 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 812 813 if (ddi_regs_map_setup(dip, pci_cfrn, 814 (caddr_t *)&pcic->cfgaddr, 815 PCIC_PCI_CONFIG_REG_OFFSET, 816 PCIC_PCI_CONFIG_REG_LENGTH, 817 &attr, 818 &pcic->cfg_handle) != 819 DDI_SUCCESS) { 820 cmn_err(CE_CONT, 821 "pcic%d: unable to map config space" 822 "regs\n", 823 ddi_get_instance(dip)); 824 825 kmem_free(pcic, sizeof (pcicdev_t)); 826 return (DDI_FAILURE); 827 } /* ddi_regs_map_setup */ 828 829 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 830 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 831 "class-code", -1); 832 #ifdef PCIC_DEBUG 833 if (pcic_debug) { 834 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 835 class_code); 836 } 837 #endif 838 839 switch (class_code) { 840 case PCIC_PCI_CARDBUS: 841 pcic->pc_flags |= PCF_CARDBUS; 842 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 843 /* 844 * Get access to the adapter registers on the 845 * PCI bus. A 4K memory page 846 */ 847 #if defined(PCIC_DEBUG) 848 pcic_err(dip, 8, "Is Cardbus device\n"); 849 if (pcic_debug) { 850 int nr; 851 long rs; 852 (void) ddi_dev_nregs(dip, &nr); 853 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 854 "cfghndl 0x%p nregs %d", 855 (void *)pcic->cfgaddr, 856 (void *)pcic->cfg_handle, nr); 857 858 (void) ddi_dev_regsize(dip, 859 PCIC_PCI_CONTROL_REG_NUM, &rs); 860 861 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 862 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 863 } 864 #endif 865 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 866 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 867 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 868 869 if (ddi_regs_map_setup(dip, pci_ctrn, 870 (caddr_t *)&pcic->ioaddr, 871 PCIC_PCI_CONTROL_REG_OFFSET, 872 PCIC_CB_CONTROL_REG_LENGTH, 873 &attr, &pcic->handle) != 874 DDI_SUCCESS) { 875 cmn_err(CE_CONT, 876 "pcic%d: unable to map PCI regs\n", 877 ddi_get_instance(dip)); 878 ddi_regs_map_free(&pcic->cfg_handle); 879 kmem_free(pcic, sizeof (pcicdev_t)); 880 return (DDI_FAILURE); 881 } /* ddi_regs_map_setup */ 882 883 /* 884 * Find out the chip type - If we're on a PCI bus, 885 * the adapter has that information in the PCI 886 * config space. 887 * Note that we call pcic_find_pci_type here since 888 * it needs a valid mapped pcic->handle to 889 * access some of the adapter registers in 890 * some cases. 891 */ 892 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 893 ddi_regs_map_free(&pcic->handle); 894 ddi_regs_map_free(&pcic->cfg_handle); 895 kmem_free(pcic, sizeof (pcicdev_t)); 896 cmn_err(CE_WARN, "pcic: %s: unsupported " 897 "bridge\n", 898 ddi_get_name_addr(dip)); 899 return (DDI_FAILURE); 900 } 901 break; 902 903 default: 904 case PCIC_PCI_PCMCIA: 905 /* 906 * Get access to the adapter IO registers on the 907 * PCI bus config space. 908 */ 909 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 910 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 911 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 912 913 /* 914 * We need a default mapping to the adapter's IO 915 * control register space. For most adapters 916 * that are of class PCIC_PCI_PCMCIA (or of 917 * a default class) the control registers 918 * will be using the 82365-type control/data 919 * format. 920 */ 921 if (ddi_regs_map_setup(dip, pci_ctrn, 922 (caddr_t *)&pcic->ioaddr, 923 PCIC_PCI_CONTROL_REG_OFFSET, 924 PCIC_PCI_CONTROL_REG_LENGTH, 925 &attr, 926 &pcic->handle) != DDI_SUCCESS) { 927 cmn_err(CE_CONT, 928 "pcic%d: unable to map PCI regs\n", 929 ddi_get_instance(dip)); 930 ddi_regs_map_free(&pcic->cfg_handle); 931 kmem_free(pcic, sizeof (pcicdev_t)); 932 return (DDI_FAILURE); 933 } /* ddi_regs_map_setup */ 934 935 /* 936 * Find out the chip type - If we're on a PCI bus, 937 * the adapter has that information in the PCI 938 * config space. 939 * Note that we call pcic_find_pci_type here since 940 * it needs a valid mapped pcic->handle to 941 * access some of the adapter registers in 942 * some cases. 943 */ 944 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 945 ddi_regs_map_free(&pcic->handle); 946 ddi_regs_map_free(&pcic->cfg_handle); 947 kmem_free(pcic, sizeof (pcicdev_t)); 948 cmn_err(CE_WARN, "pcic: %s: unsupported " 949 "bridge\n", 950 ddi_get_name_addr(dip)); 951 return (DDI_FAILURE); 952 } 953 954 /* 955 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 956 * for extended registers even though they are 957 * not CardBus adapters. For those adapters, 958 * re-map pcic->handle to be large enough to 959 * encompass the Yenta registers. 960 */ 961 switch (pcic->pc_type) { 962 case PCIC_TI_PCI1031: 963 ddi_regs_map_free(&pcic->handle); 964 965 if (ddi_regs_map_setup(dip, 966 PCIC_PCI_CONTROL_REG_NUM, 967 (caddr_t *)&pcic->ioaddr, 968 PCIC_PCI_CONTROL_REG_OFFSET, 969 PCIC_CB_CONTROL_REG_LENGTH, 970 &attr, 971 &pcic->handle) != DDI_SUCCESS) { 972 cmn_err(CE_CONT, 973 "pcic%d: unable to map " 974 "PCI regs\n", 975 ddi_get_instance(dip)); 976 ddi_regs_map_free(&pcic->cfg_handle); 977 kmem_free(pcic, sizeof (pcicdev_t)); 978 return (DDI_FAILURE); 979 } /* ddi_regs_map_setup */ 980 break; 981 default: 982 break; 983 } /* switch (pcic->pc_type) */ 984 break; 985 } /* switch (class_code) */ 986 } else { 987 /* 988 * We're not on a PCI bus, so assume an ISA bus type 989 * register property. Get access to the adapter IO 990 * registers on a non-PCI bus. 991 */ 992 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 993 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 994 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 995 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 996 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 997 998 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 999 (caddr_t *)&pcic->ioaddr, 1000 PCIC_ISA_CONTROL_REG_OFFSET, 1001 PCIC_ISA_CONTROL_REG_LENGTH, 1002 &attr, 1003 &pcic->handle) != DDI_SUCCESS) { 1004 cmn_err(CE_CONT, 1005 "pcic%d: unable to map ISA registers\n", 1006 ddi_get_instance(dip)); 1007 1008 kmem_free(pcic, sizeof (pcicdev_t)); 1009 return (DDI_FAILURE); 1010 } /* ddi_regs_map_setup */ 1011 1012 /* ISA bus is limited to 24-bits, but not first 640K */ 1013 pcic->pc_base = 0xd0000; 1014 pcic->pc_bound = (uint32_t)~0; 1015 pcic->pc_iobase = 0x1000; 1016 pcic->pc_iobound = 0xefff; 1017 } /* !PCF_PCIBUS */ 1018 1019 #ifdef PCIC_DEBUG 1020 if (pcic_debug) { 1021 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1022 pcic->pc_flags, pcic->pc_type); 1023 } 1024 #endif 1025 1026 /* 1027 * Setup various adapter registers for the PCI case. For the 1028 * non-PCI case, find out the chip type. 1029 */ 1030 if (pcic->pc_flags & PCF_PCIBUS) { 1031 int iline; 1032 #if defined(__sparc) 1033 iline = 0; 1034 #else 1035 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1036 #endif 1037 1038 /* set flags and socket counts based on chip type */ 1039 switch (pcic->pc_type) { 1040 uint32_t cfg; 1041 case PCIC_INTEL_i82092: 1042 cfg = ddi_get8(pcic->cfg_handle, 1043 pcic->cfgaddr + PCIC_82092_PCICON); 1044 /* we can only support 4 Socket version */ 1045 if (cfg & PCIC_82092_4_SOCKETS) { 1046 pcic->pc_numsockets = 4; 1047 pcic->pc_type = PCIC_INTEL_i82092; 1048 if (iline != 0xFF) 1049 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1050 else 1051 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1052 } else { 1053 cmn_err(CE_CONT, 1054 "pcic%d: Intel 82092 adapter " 1055 "in unsupported configuration: 0x%x", 1056 ddi_get_instance(pcic->dip), cfg); 1057 pcic->pc_numsockets = 0; 1058 } /* PCIC_82092_4_SOCKETS */ 1059 break; 1060 case PCIC_CL_PD6730: 1061 case PCIC_CL_PD6729: 1062 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1063 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1064 DDI_PROP_CANSLEEP, 1065 "interrupts", 0); 1066 /* if not interrupt pin then must use ISA style IRQs */ 1067 if (cfg == 0 || iline == 0xFF) 1068 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1069 else { 1070 /* 1071 * we have the option to use PCI interrupts. 1072 * this might not be optimal but in some cases 1073 * is the only thing possible (sparc case). 1074 * we now deterine what is possible. 1075 */ 1076 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1077 } 1078 pcic->pc_numsockets = 2; 1079 pcic->pc_flags |= PCF_IO_REMAP; 1080 break; 1081 case PCIC_TI_PCI1031: 1082 /* this chip doesn't do CardBus but looks like one */ 1083 pcic->pc_flags &= ~PCF_CARDBUS; 1084 /* FALLTHROUGH */ 1085 default: 1086 pcic->pc_flags |= PCF_IO_REMAP; 1087 /* FALLTHROUGH */ 1088 /* indicate feature even if not supported */ 1089 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1090 /* Not sure if these apply to all these chips */ 1091 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1092 pcic->pc_flags |= pcic_use_cbpwrctl; 1093 1094 pcic->pc_numsockets = 1; /* one per function */ 1095 if (iline != 0xFF) { 1096 uint8_t cfg; 1097 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1098 1099 cfg = ddi_get8(pcic->cfg_handle, 1100 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1101 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1102 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1103 PCIC_BRIDGE_CTL_REG), cfg); 1104 } 1105 else 1106 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1107 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1108 break; 1109 } 1110 } else { 1111 /* 1112 * We're not on a PCI bus so do some more 1113 * checking for adapter type here. 1114 * For the non-PCI bus case: 1115 * It could be any one of a number of different chips 1116 * If we can't determine anything else, it is assumed 1117 * to be an Intel 82365SL. The Cirrus Logic PD6710 1118 * has an extension register that provides unique 1119 * identification. Toshiba chip isn't detailed as yet. 1120 */ 1121 1122 /* Init the CL id mode */ 1123 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1124 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1125 1126 /* default to Intel i82365SL and then refine */ 1127 pcic->pc_type = PCIC_I82365SL; 1128 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1129 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1130 /* go until one succeeds or none left */ 1131 if (pcic_ci_funcs[value](pcic)) 1132 break; 1133 } 1134 1135 /* any chip specific flags get set here */ 1136 switch (pcic->pc_type) { 1137 case PCIC_CL_PD6722: 1138 pcic->pc_flags |= PCF_DMA; 1139 } 1140 1141 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1142 /* 1143 * look for total number of sockets. 1144 * basically check each possible socket for 1145 * presence like in probe 1146 */ 1147 1148 /* turn all windows off */ 1149 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1150 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1151 1152 /* 1153 * if a zero is read back, then this socket 1154 * might be present. It would be except for 1155 * some systems that map the secondary PCIC 1156 * chip space back to the first. 1157 */ 1158 if (value != 0) { 1159 /* definitely not so skip */ 1160 /* note: this is for Compaq support */ 1161 continue; 1162 } 1163 1164 /* further tests */ 1165 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1166 PCIC_REV_MASK; 1167 if (!(value >= PCIC_REV_LEVEL_LOW && 1168 value <= PCIC_REV_LEVEL_HI)) 1169 break; 1170 1171 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1172 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1173 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1174 1175 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1176 if (value != 0xaa || j != 0x55) 1177 break; 1178 1179 /* 1180 * at this point we know if we have hardware 1181 * of some type and not just the bus holding 1182 * a pattern for us. We still have to determine 1183 * the case where more than 2 sockets are 1184 * really the same due to peculiar mappings of 1185 * hardware. 1186 */ 1187 j = pcic->pc_numsockets++; 1188 pcic->pc_sockets[j].pcs_flags = 0; 1189 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1190 pcic->pc_sockets[j].pcs_socket = i; 1191 1192 /* put PC Card into RESET, just in case */ 1193 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1194 pcic_putb(pcic, i, PCIC_INTERRUPT, 1195 value & ~PCIC_RESET); 1196 } 1197 1198 #if defined(PCIC_DEBUG) 1199 if (pcic_debug) 1200 cmn_err(CE_CONT, "num sockets = %d\n", 1201 pcic->pc_numsockets); 1202 #endif 1203 if (pcic->pc_numsockets == 0) { 1204 ddi_regs_map_free(&pcic->handle); 1205 kmem_free(pcic, sizeof (pcicdev_t)); 1206 return (DDI_FAILURE); 1207 } 1208 1209 /* 1210 * need to think this through again in light of 1211 * Compaq not following the model that all the 1212 * chip vendors recommend. IBM 755 seems to be 1213 * afflicted as well. Basically, if the vendor 1214 * wired things wrong, socket 0 responds for socket 2 1215 * accesses, etc. 1216 */ 1217 if (pcic->pc_numsockets > 2) { 1218 int count = pcic->pc_numsockets / 4; 1219 for (i = 0; i < count; i++) { 1220 /* put pattern into socket 0 */ 1221 pcic_putb(pcic, i, 1222 PCIC_SYSMEM_0_STARTLOW, 0x11); 1223 1224 /* put pattern into socket 2 */ 1225 pcic_putb(pcic, i + 2, 1226 PCIC_SYSMEM_0_STARTLOW, 0x33); 1227 1228 /* read back socket 0 */ 1229 value = pcic_getb(pcic, i, 1230 PCIC_SYSMEM_0_STARTLOW); 1231 1232 /* read back chip 1 socket 0 */ 1233 j = pcic_getb(pcic, i + 2, 1234 PCIC_SYSMEM_0_STARTLOW); 1235 if (j == value) { 1236 pcic->pc_numsockets -= 2; 1237 } 1238 } 1239 } 1240 1241 smi = 0xff; /* no more override */ 1242 1243 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1244 DDI_PROP_DONTPASS, "need-mult-irq", 1245 0xffff) != 0xffff) 1246 pcic->pc_flags |= PCF_MULT_IRQ; 1247 1248 } /* !PCF_PCIBUS */ 1249 1250 /* 1251 * some platforms/busses need to have resources setup 1252 * this is temporary until a real resource allocator is 1253 * implemented. 1254 */ 1255 1256 pcic_init_assigned(dip); 1257 1258 typename = pcic->pc_chipname; 1259 1260 #ifdef PCIC_DEBUG 1261 if (pcic_debug) { 1262 int nregs, nintrs; 1263 1264 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1265 nregs = 0; 1266 1267 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1268 nintrs = 0; 1269 1270 cmn_err(CE_CONT, 1271 "pcic%d: %d register sets, %d interrupts\n", 1272 ddi_get_instance(dip), nregs, nintrs); 1273 1274 nintrs = 0; 1275 while (nregs--) { 1276 off_t size; 1277 1278 if (ddi_dev_regsize(dip, nintrs, &size) == 1279 DDI_SUCCESS) { 1280 cmn_err(CE_CONT, 1281 "\tregnum %d size %ld (0x%lx)" 1282 "bytes", 1283 nintrs, size, size); 1284 if (nintrs == 1285 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1286 PCIC_ISA_CONTROL_REG_NUM : 1287 PCIC_PCI_CONTROL_REG_NUM)) 1288 cmn_err(CE_CONT, 1289 " mapped at: 0x%p\n", 1290 (void *)pcic->ioaddr); 1291 else 1292 cmn_err(CE_CONT, "\n"); 1293 } else { 1294 cmn_err(CE_CONT, 1295 "\tddi_dev_regsize(rnumber" 1296 "= %d) returns DDI_FAILURE\n", 1297 nintrs); 1298 } 1299 nintrs++; 1300 } /* while */ 1301 } /* if (pcic_debug) */ 1302 #endif 1303 1304 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1305 1306 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1307 "disable-audio", 0)) 1308 pcic->pc_flags |= PCF_AUDIO; 1309 1310 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1311 "disable-cardbus", 0)) 1312 pcic->pc_flags &= ~PCF_CARDBUS; 1313 1314 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1315 typename); 1316 1317 /* 1318 * Init all socket SMI levels to 0 (no SMI) 1319 */ 1320 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1321 pcic->pc_sockets[i].pcs_smi = 0; 1322 pcic->pc_sockets[i].pcs_debounce_id = 0; 1323 pcic->pc_sockets[i].pcs_pcic = pcic; 1324 } 1325 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1326 1327 /* 1328 * Setup the IRQ handler(s) 1329 */ 1330 switch (pcic->pc_intr_mode) { 1331 int xx; 1332 case PCIC_INTR_MODE_ISA: 1333 /* 1334 * On a non-PCI bus, we just use whatever SMI IRQ level was 1335 * specified above, and the IO IRQ levels are allocated 1336 * dynamically. 1337 */ 1338 for (xx = 15, smi = 0; xx >= 0; xx--) { 1339 if (PCIC_IRQ(xx) & 1340 PCIC_AVAIL_IRQS) { 1341 smi = pcmcia_get_intr(dip, xx); 1342 if (smi >= 0) 1343 break; 1344 } 1345 } 1346 #if defined(PCIC_DEBUG) 1347 if (pcic_debug) 1348 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1349 #endif 1350 /* init to same so share is easy */ 1351 for (i = 0; i < pcic->pc_numsockets; i++) 1352 pcic->pc_sockets[i].pcs_smi = smi; 1353 /* any special handling of IRQ levels */ 1354 if (pcic->pc_flags & PCF_MULT_IRQ) { 1355 for (i = 2; i < pcic->pc_numsockets; i++) { 1356 if ((i & 1) == 0) { 1357 int xx; 1358 for (xx = 15, smi = 0; xx >= 0; xx--) { 1359 if (PCIC_IRQ(xx) & 1360 PCIC_AVAIL_IRQS) { 1361 smi = 1362 pcmcia_get_intr(dip, 1363 xx); 1364 if (smi >= 0) 1365 break; 1366 } 1367 } 1368 } 1369 if (smi >= 0) 1370 pcic->pc_sockets[i].pcs_smi = smi; 1371 } 1372 } 1373 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1374 sizeof (ddi_intr_handle_t), KM_SLEEP); 1375 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1376 struct intrspec *ispecp; 1377 struct ddi_parent_private_data *pdp; 1378 1379 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1380 continue; 1381 else { 1382 irqlevel = pcic->pc_sockets[i].pcs_smi; 1383 } 1384 /* 1385 * now convert the allocated IRQ into an intrspec 1386 * and ask our parent to add it. Don't use 1387 * the ddi_add_intr since we don't have a 1388 * default intrspec in all cases. 1389 * 1390 * note: this sort of violates DDI but we don't 1391 * get hardware intrspecs for many of the devices. 1392 * at the same time, we know how to allocate them 1393 * so we do the right thing. 1394 */ 1395 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1396 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1397 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1398 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1399 ddi_get_name(dip)); 1400 goto isa_exit1; 1401 } 1402 1403 /* 1404 * See earlier note: 1405 * Since some devices don't have 'intrspec' 1406 * we make one up in rootnex. 1407 * 1408 * However, it is not properly initialized as 1409 * the data it needs is present in this driver 1410 * and there is no interface to pass that up. 1411 * Specially 'irqlevel' is very important and 1412 * it is part of pcic struct. 1413 * 1414 * Set 'intrspec' up here; otherwise adding the 1415 * interrupt will fail. 1416 */ 1417 pdp = ddi_get_parent_data(dip); 1418 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1419 ispecp->intrspec_vec = irqlevel; 1420 ispecp->intrspec_pri = pcic->pc_irq; 1421 1422 /* Stay compatible w/ PCMCIA */ 1423 pcic->pc_pri = (ddi_iblock_cookie_t) 1424 (uintptr_t)pcic->pc_irq; 1425 pcic->pc_dcookie.idev_priority = 1426 (uintptr_t)pcic->pc_pri; 1427 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1428 1429 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1430 pcic->pc_irq); 1431 1432 if (i == 0) { 1433 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1434 DDI_INTR_PRI(pcic->pc_irq)); 1435 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1436 NULL); 1437 } 1438 1439 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1440 pcic_intr, (caddr_t)pcic, NULL)) { 1441 cmn_err(CE_WARN, 1442 "%s: ddi_intr_add_handler failed", 1443 ddi_get_name(dip)); 1444 goto isa_exit2; 1445 } 1446 1447 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1448 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1449 ddi_get_name(dip)); 1450 for (j = i; j < 0; j--) 1451 (void) ddi_intr_remove_handler( 1452 pcic->pc_intr_htblp[j]); 1453 goto isa_exit2; 1454 } 1455 } 1456 break; 1457 case PCIC_INTR_MODE_PCI_1: 1458 case PCIC_INTR_MODE_PCI: 1459 /* 1460 * If we're on a PCI bus, we route all interrupts, both SMI 1461 * and IO interrupts, through a single interrupt line. 1462 * Assign the SMI IRQ level to the IO IRQ level here. 1463 */ 1464 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1465 KM_SLEEP); 1466 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1467 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1468 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1469 goto pci_exit1; 1470 1471 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1472 &pri) != DDI_SUCCESS) { 1473 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1474 goto pci_exit1; 1475 } 1476 1477 pcic->pc_pri = (void *)(uintptr_t)pri; 1478 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1479 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1480 1481 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1482 pcic_intr, (caddr_t)pcic, NULL)) 1483 goto pci_exit2; 1484 1485 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1486 (void) ddi_intr_remove_handler( 1487 pcic->pc_pci_intr_hdlp[0]); 1488 goto pci_exit2; 1489 } 1490 1491 /* Stay compatible w/ PCMCIA */ 1492 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1493 1494 /* init to same (PCI) so share is easy */ 1495 for (i = 0; i < pcic->pc_numsockets; i++) 1496 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1497 break; 1498 } 1499 1500 /* 1501 * Setup the adapter hardware to some reasonable defaults. 1502 */ 1503 mutex_enter(&pcic->pc_lock); 1504 /* mark the driver state as attached */ 1505 pcic->pc_flags |= PCF_ATTACHED; 1506 pcic_setup_adapter(pcic); 1507 1508 for (j = 0; j < pcic->pc_numsockets; j++) 1509 if (ddi_intr_add_softint(dip, 1510 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1511 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1512 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1513 goto pci_exit2; 1514 1515 #if defined(PCIC_DEBUG) 1516 if (pcic_debug) 1517 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1518 pcic->pc_numsockets); 1519 #endif 1520 1521 pcic_nexus->an_iblock = &pcic->pc_pri; 1522 pcic_nexus->an_idev = &pcic->pc_dcookie; 1523 1524 mutex_exit(&pcic->pc_lock); 1525 1526 #ifdef CARDBUS 1527 (void) cardbus_enable_cd_intr(dip); 1528 if (pcic_debug) { 1529 1530 cardbus_dump_pci_config(dip); 1531 cardbus_dump_socket(dip); 1532 } 1533 1534 /* 1535 * Give the Cardbus misc module a chance to do it's per-adapter 1536 * instance setup. Note that there is no corresponding detach() 1537 * call. 1538 */ 1539 if (pcic->pc_flags & PCF_CARDBUS) 1540 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1541 cmn_err(CE_CONT, 1542 "pcic_attach: cardbus_attach failed\n"); 1543 goto pci_exit2; 1544 } 1545 #endif 1546 1547 /* 1548 * Give the PCMCIA misc module a chance to do it's per-adapter 1549 * instance setup. 1550 */ 1551 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1552 goto pci_exit2; 1553 1554 if (pcic_maxinst == -1) { 1555 /* This assumes that all instances run at the same IPL. */ 1556 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1557 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1558 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1559 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1560 v.v_maxsyspri - 2); 1561 } 1562 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1563 /* 1564 * Setup a debounce timeout to do an initial card detect 1565 * and enable interrupts. 1566 */ 1567 for (j = 0; j < pcic->pc_numsockets; j++) { 1568 pcic->pc_sockets[j].pcs_debounce_id = 1569 pcic_add_debqueue(&pcic->pc_sockets[j], 1570 drv_usectohz(pcic_debounce_time)); 1571 } 1572 1573 return (i); 1574 1575 isa_exit2: 1576 mutex_destroy(&pcic->intr_lock); 1577 mutex_destroy(&pcic->pc_lock); 1578 for (j = i; j < 0; j--) 1579 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1580 isa_exit1: 1581 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1582 ddi_regs_map_free(&pcic->handle); 1583 if (pcic->pc_flags & PCF_PCIBUS) 1584 ddi_regs_map_free(&pcic->cfg_handle); 1585 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1586 sizeof (ddi_intr_handle_t)); 1587 kmem_free(pcic, sizeof (pcicdev_t)); 1588 return (DDI_FAILURE); 1589 1590 pci_exit2: 1591 mutex_destroy(&pcic->intr_lock); 1592 mutex_destroy(&pcic->pc_lock); 1593 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1594 pci_exit1: 1595 ddi_regs_map_free(&pcic->handle); 1596 if (pcic->pc_flags & PCF_PCIBUS) 1597 ddi_regs_map_free(&pcic->cfg_handle); 1598 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1599 kmem_free(pcic, sizeof (pcicdev_t)); 1600 return (DDI_FAILURE); 1601 } 1602 1603 /* 1604 * pcic_detach() 1605 * request to detach from the system 1606 */ 1607 static int 1608 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1609 { 1610 anp_t *anp = ddi_get_driver_private(dip); 1611 pcicdev_t *pcic = anp->an_private; 1612 int i; 1613 1614 switch (cmd) { 1615 case DDI_DETACH: 1616 /* don't detach if the nexus still talks to us */ 1617 if (pcic->pc_callback != NULL) 1618 return (DDI_FAILURE); 1619 1620 /* kill off the pm simulation */ 1621 if (pcic->pc_pmtimer) 1622 (void) untimeout(pcic->pc_pmtimer); 1623 1624 /* turn everything off for all sockets and chips */ 1625 for (i = 0; i < pcic->pc_numsockets; i++) { 1626 if (pcic->pc_sockets[i].pcs_debounce_id) 1627 pcic_rm_debqueue( 1628 pcic->pc_sockets[i].pcs_debounce_id); 1629 pcic->pc_sockets[i].pcs_debounce_id = 0; 1630 1631 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1632 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1633 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1634 /* disable interrupts and put card into RESET */ 1635 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1636 } 1637 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1638 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1639 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1640 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1641 pcic->pc_flags = 0; 1642 mutex_destroy(&pcic->pc_lock); 1643 mutex_destroy(&pcic->intr_lock); 1644 cv_destroy(&pcic->pm_cv); 1645 if (pcic->pc_flags & PCF_PCIBUS) 1646 ddi_regs_map_free(&pcic->cfg_handle); 1647 if (pcic->handle) 1648 ddi_regs_map_free(&pcic->handle); 1649 kmem_free(pcic, sizeof (pcicdev_t)); 1650 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1651 return (DDI_SUCCESS); 1652 1653 case DDI_SUSPEND: 1654 case DDI_PM_SUSPEND: 1655 /* 1656 * we got a suspend event (either real or imagined) 1657 * so notify the nexus proper that all existing cards 1658 * should go away. 1659 */ 1660 mutex_enter(&pcic->pc_lock); 1661 #ifdef CARDBUS 1662 if (pcic->pc_flags & PCF_CARDBUS) { 1663 for (i = 0; i < pcic->pc_numsockets; i++) { 1664 if ((pcic->pc_sockets[i].pcs_flags & 1665 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1666 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) { 1667 1668 pcmcia_cb_suspended( 1669 pcic->pc_sockets[i].pcs_socket); 1670 } 1671 } 1672 1673 cardbus_save_children(ddi_get_child(dip)); 1674 } 1675 #endif 1676 /* turn everything off for all sockets and chips */ 1677 for (i = 0; i < pcic->pc_numsockets; i++) { 1678 if (pcic->pc_sockets[i].pcs_debounce_id) 1679 pcic_rm_debqueue( 1680 pcic->pc_sockets[i].pcs_debounce_id); 1681 pcic->pc_sockets[i].pcs_debounce_id = 0; 1682 1683 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1684 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1685 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1686 /* disable interrupts and put card into RESET */ 1687 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1688 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1689 if (pcic->pc_flags & PCF_CBPWRCTL) 1690 pcic_putcb(pcic, CB_CONTROL, 0); 1691 1692 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1693 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1694 /* 1695 * Because we are half way through a save 1696 * all this does is schedule a removal event 1697 * to cs for when the system comes back. 1698 * This doesn't actually matter. 1699 */ 1700 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1701 pcic->pc_callback) { 1702 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1703 PCE_CARD_REMOVAL, 1704 pcic->pc_sockets[i].pcs_socket); 1705 } 1706 } 1707 } 1708 1709 pcic->pc_flags |= PCF_SUSPENDED; 1710 mutex_exit(&pcic->pc_lock); 1711 1712 /* 1713 * when true power management exists, save the adapter 1714 * state here to enable a recovery. For the emulation 1715 * condition, the state is gone 1716 */ 1717 return (DDI_SUCCESS); 1718 1719 default: 1720 return (EINVAL); 1721 } 1722 } 1723 1724 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1725 static uint32_t pcic_tisysctl_offbits = 0; 1726 static uint32_t pcic_default_latency = 0x40; 1727 1728 static void 1729 pcic_setup_adapter(pcicdev_t *pcic) 1730 { 1731 int i; 1732 int value, flags; 1733 1734 if (pcic->pc_flags & PCF_PCIBUS) { 1735 /* 1736 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1737 */ 1738 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1739 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1740 } 1741 /* enable each socket */ 1742 for (i = 0; i < pcic->pc_numsockets; i++) { 1743 pcic->pc_sockets[i].pcs_flags = 0; 1744 /* find out the socket capabilities (I/O vs memory) */ 1745 value = pcic_getb(pcic, i, 1746 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1747 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1748 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1749 1750 /* disable all windows just in case */ 1751 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1752 1753 switch (pcic->pc_type) { 1754 uint32_t cfg32; 1755 uint16_t cfg16; 1756 uint8_t cfg; 1757 1758 /* enable extended registers for Vadem */ 1759 case PCIC_VADEM_VG469: 1760 case PCIC_VADEM: 1761 1762 /* enable card status change interrupt for socket */ 1763 break; 1764 1765 case PCIC_I82365SL: 1766 break; 1767 1768 case PCIC_CL_PD6710: 1769 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1770 break; 1771 1772 /* 1773 * On the CL_6730, we need to set up the interrupt 1774 * signalling mode (PCI mode) and set the SMI and 1775 * IRQ interrupt lines to PCI/level-mode. 1776 */ 1777 case PCIC_CL_PD6730: 1778 switch (pcic->pc_intr_mode) { 1779 case PCIC_INTR_MODE_PCI_1: 1780 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1781 ((clext_reg_read(pcic, i, 1782 PCIC_CLEXT_MISC_CTL_3) & 1783 ~PCIC_CLEXT_INT_PCI) | 1784 PCIC_CLEXT_INT_PCI)); 1785 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1786 (PCIC_CLEXT_IRQ_LVL_MODE | 1787 PCIC_CLEXT_SMI_LVL_MODE)); 1788 cfg = PCIC_CL_LP_DYN_MODE; 1789 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1790 break; 1791 case PCIC_INTR_MODE_ISA: 1792 break; 1793 } 1794 break; 1795 /* 1796 * On the CL_6729, we set the SMI and IRQ interrupt 1797 * lines to PCI/level-mode. as well as program the 1798 * correct clock speed divider bit. 1799 */ 1800 case PCIC_CL_PD6729: 1801 switch (pcic->pc_intr_mode) { 1802 case PCIC_INTR_MODE_PCI_1: 1803 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1804 (PCIC_CLEXT_IRQ_LVL_MODE | 1805 PCIC_CLEXT_SMI_LVL_MODE)); 1806 1807 break; 1808 case PCIC_INTR_MODE_ISA: 1809 break; 1810 } 1811 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1812 cfg = 0; 1813 cfg |= PCIC_CL_TIMER_CLK_DIV; 1814 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1815 } 1816 break; 1817 case PCIC_INTEL_i82092: 1818 cfg = PCIC_82092_EN_TIMING; 1819 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1820 cfg |= PCIC_82092_PCICLK_25MHZ; 1821 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1822 PCIC_82092_PCICON, cfg); 1823 break; 1824 case PCIC_TI_PCI1130: 1825 case PCIC_TI_PCI1131: 1826 case PCIC_TI_PCI1250: 1827 case PCIC_TI_PCI1031: 1828 cfg = ddi_get8(pcic->cfg_handle, 1829 pcic->cfgaddr + PCIC_DEVCTL_REG); 1830 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1831 switch (pcic->pc_intr_mode) { 1832 case PCIC_INTR_MODE_ISA: 1833 cfg |= PCIC_DEVCTL_INTR_ISA; 1834 break; 1835 } 1836 #ifdef PCIC_DEBUG 1837 if (pcic_debug) { 1838 cmn_err(CE_CONT, "pcic_setup_adapter: " 1839 "write reg 0x%x=%x \n", 1840 PCIC_DEVCTL_REG, cfg); 1841 } 1842 #endif 1843 ddi_put8(pcic->cfg_handle, 1844 pcic->cfgaddr + PCIC_DEVCTL_REG, 1845 cfg); 1846 1847 cfg = ddi_get8(pcic->cfg_handle, 1848 pcic->cfgaddr + PCIC_CRDCTL_REG); 1849 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1850 PCIC_CRDCTL_PCIFUNC); 1851 switch (pcic->pc_intr_mode) { 1852 case PCIC_INTR_MODE_PCI_1: 1853 cfg |= PCIC_CRDCTL_PCIINTR | 1854 PCIC_CRDCTL_PCICSC | 1855 PCIC_CRDCTL_PCIFUNC; 1856 pcic->pc_flags |= PCF_USE_SMI; 1857 break; 1858 } 1859 #ifdef PCIC_DEBUG 1860 if (pcic_debug) { 1861 cmn_err(CE_CONT, "pcic_setup_adapter: " 1862 " write reg 0x%x=%x \n", 1863 PCIC_CRDCTL_REG, cfg); 1864 } 1865 #endif 1866 ddi_put8(pcic->cfg_handle, 1867 pcic->cfgaddr + PCIC_CRDCTL_REG, 1868 cfg); 1869 break; 1870 case PCIC_TI_PCI1221: 1871 case PCIC_TI_PCI1225: 1872 cfg = ddi_get8(pcic->cfg_handle, 1873 pcic->cfgaddr + PCIC_DEVCTL_REG); 1874 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1875 #ifdef PCIC_DEBUG 1876 if (pcic_debug) { 1877 cmn_err(CE_CONT, "pcic_setup_adapter: " 1878 " write reg 0x%x=%x \n", 1879 PCIC_DEVCTL_REG, cfg); 1880 } 1881 #endif 1882 ddi_put8(pcic->cfg_handle, 1883 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1884 1885 cfg = ddi_get8(pcic->cfg_handle, 1886 pcic->cfgaddr + PCIC_DIAG_REG); 1887 if (pcic->pc_type == PCIC_TI_PCI1225) { 1888 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1889 } else { 1890 cfg |= PCIC_DIAG_ASYNC; 1891 } 1892 pcic->pc_flags |= PCF_USE_SMI; 1893 #ifdef PCIC_DEBUG 1894 if (pcic_debug) { 1895 cmn_err(CE_CONT, "pcic_setup_adapter: " 1896 " write reg 0x%x=%x \n", 1897 PCIC_DIAG_REG, cfg); 1898 } 1899 #endif 1900 ddi_put8(pcic->cfg_handle, 1901 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1902 break; 1903 case PCIC_TI_PCI1520: 1904 case PCIC_TI_PCI1510: 1905 case PCIC_TI_VENDOR: 1906 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1907 cfg = ddi_get8(pcic->cfg_handle, 1908 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1909 cfg |= PCIC_FUN_INT_MOD_ISA; 1910 ddi_put8(pcic->cfg_handle, 1911 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1912 cfg); 1913 } 1914 cfg = ddi_get8(pcic->cfg_handle, 1915 pcic->cfgaddr + PCIC_DEVCTL_REG); 1916 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1917 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) 1918 cfg |= PCIC_DEVCTL_INTR_ISA; 1919 ddi_put8(pcic->cfg_handle, 1920 pcic->cfgaddr + PCIC_DEVCTL_REG, 1921 cfg); 1922 1923 /* tie INTA and INTB together */ 1924 cfg = ddi_get8(pcic->cfg_handle, 1925 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 1926 cfg |= PCIC_SYSCTL_INTRTIE; 1927 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1928 PCIC_SYSCTL_REG + 3), cfg); 1929 cfg = ddi_get8(pcic->cfg_handle, 1930 pcic->cfgaddr + PCIC_DIAG_REG); 1931 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1932 ddi_put8(pcic->cfg_handle, 1933 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1934 break; 1935 case PCIC_TI_PCI1410: 1936 cfg = ddi_get8(pcic->cfg_handle, 1937 pcic->cfgaddr + PCIC_DIAG_REG); 1938 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1939 ddi_put8(pcic->cfg_handle, 1940 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1941 break; 1942 case PCIC_TOSHIBA_TOPIC100: 1943 case PCIC_TOSHIBA_TOPIC95: 1944 case PCIC_TOSHIBA_VENDOR: 1945 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 1946 PCIC_TOSHIBA_SLOT_CTL_REG); 1947 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 1948 PCIC_TOSHIBA_SCR_SLOTEN); 1949 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 1950 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 1951 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1952 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 1953 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 1954 PCIC_TOSHIBA_INTR_CTL_REG); 1955 switch (pcic->pc_intr_mode) { 1956 case PCIC_INTR_MODE_ISA: 1957 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 1958 ddi_put8(pcic->cfg_handle, 1959 pcic->cfgaddr + 1960 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 1961 1962 cfg = ddi_get8(pcic->cfg_handle, 1963 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1964 cfg |= PCIC_FUN_INT_MOD_ISA; 1965 ddi_put8(pcic->cfg_handle, 1966 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1967 cfg); 1968 break; 1969 case PCIC_INTR_MODE_PCI_1: 1970 cfg |= PCIC_TOSHIBA_ICR_SRC; 1971 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 1972 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 1973 ddi_put8(pcic->cfg_handle, 1974 pcic->cfgaddr + 1975 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 1976 break; 1977 } 1978 break; 1979 case PCIC_O2MICRO_VENDOR: 1980 cfg32 = ddi_get32(pcic->cfg_handle, 1981 (uint32_t *)(pcic->cfgaddr + 1982 PCIC_O2MICRO_MISC_CTL)); 1983 switch (pcic->pc_intr_mode) { 1984 case PCIC_INTR_MODE_ISA: 1985 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 1986 PCIC_O2MICRO_INT_MOD_PCI); 1987 ddi_put32(pcic->cfg_handle, 1988 (uint32_t *)(pcic->cfgaddr + 1989 PCIC_O2MICRO_MISC_CTL), 1990 cfg32); 1991 cfg = ddi_get8(pcic->cfg_handle, 1992 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1993 cfg |= PCIC_FUN_INT_MOD_ISA; 1994 ddi_put8(pcic->cfg_handle, 1995 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1996 cfg); 1997 break; 1998 case PCIC_INTR_MODE_PCI_1: 1999 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2000 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2001 ddi_put32(pcic->cfg_handle, 2002 (uint32_t *)(pcic->cfgaddr + 2003 PCIC_O2MICRO_MISC_CTL), 2004 cfg32); 2005 break; 2006 } 2007 break; 2008 case PCIC_RICOH_VENDOR: 2009 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2010 cfg16 = ddi_get16(pcic->cfg_handle, 2011 (uint16_t *)(pcic->cfgaddr + 2012 PCIC_RICOH_MISC_CTL_2)); 2013 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2014 PCIC_RICOH_FUN_INT_MOD); 2015 ddi_put16(pcic->cfg_handle, 2016 (uint16_t *)(pcic->cfgaddr + 2017 PCIC_RICOH_MISC_CTL_2), 2018 cfg16); 2019 2020 cfg16 = ddi_get16(pcic->cfg_handle, 2021 (uint16_t *)(pcic->cfgaddr + 2022 PCIC_RICOH_MISC_CTL)); 2023 cfg16 |= PCIC_RICOH_SIRQ_EN; 2024 ddi_put16(pcic->cfg_handle, 2025 (uint16_t *)(pcic->cfgaddr + 2026 PCIC_RICOH_MISC_CTL), 2027 cfg16); 2028 2029 cfg = ddi_get8(pcic->cfg_handle, 2030 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2031 cfg |= PCIC_FUN_INT_MOD_ISA; 2032 ddi_put8(pcic->cfg_handle, 2033 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2034 cfg); 2035 } 2036 break; 2037 default: 2038 break; 2039 } /* switch */ 2040 2041 /* 2042 * The default value in the EEPROM (loaded on reset) for 2043 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that 2044 * MFUNC0 is connected to INTA, and MFUNC1 is connected to 2045 * INTB. This applies to all TI CardBus controllers. 2046 */ 2047 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID && 2048 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) { 2049 value = ddi_get32(pcic->cfg_handle, 2050 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG)); 2051 value &= ~0xff; 2052 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr + 2053 PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL); 2054 } 2055 2056 /* setup general card status change interrupt */ 2057 switch (pcic->pc_type) { 2058 case PCIC_TI_PCI1225: 2059 case PCIC_TI_PCI1221: 2060 case PCIC_TI_PCI1031: 2061 case PCIC_TI_PCI1520: 2062 case PCIC_TI_PCI1410: 2063 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2064 PCIC_CHANGE_DEFAULT); 2065 break; 2066 default: 2067 if (pcic->pc_intr_mode == 2068 PCIC_INTR_MODE_PCI_1) { 2069 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2070 PCIC_CHANGE_DEFAULT); 2071 break; 2072 } else { 2073 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2074 PCIC_CHANGE_DEFAULT | 2075 (pcic->pc_sockets[i].pcs_smi << 4)); 2076 break; 2077 } 2078 } 2079 2080 pcic->pc_flags |= PCF_INTRENAB; 2081 2082 /* take card out of RESET */ 2083 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2084 /* turn power off and let CS do this */ 2085 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2086 2087 /* final chip specific initialization */ 2088 switch (pcic->pc_type) { 2089 case PCIC_VADEM: 2090 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2091 PCIC_VC_DELAYENABLE); 2092 pcic->pc_flags |= PCF_DEBOUNCE; 2093 /* FALLTHROUGH */ 2094 case PCIC_I82365SL: 2095 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2096 PCIC_GC_CSC_WRITE); 2097 /* clear any pending interrupts */ 2098 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2099 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2100 break; 2101 /* The 82092 uses PCI config space to enable interrupts */ 2102 case PCIC_INTEL_i82092: 2103 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2104 PCIC_82092_INT_ENABLE); 2105 break; 2106 case PCIC_CL_PD6729: 2107 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2108 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2109 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2110 value | PCIC_CL_TIMER_CLK_DIV); 2111 } 2112 break; 2113 } /* switch */ 2114 2115 #if defined(PCIC_DEBUG) 2116 if (pcic_debug) 2117 cmn_err(CE_CONT, 2118 "socket %d value=%x, flags = %x (%s)\n", 2119 i, value, pcic->pc_sockets[i].pcs_flags, 2120 (pcic->pc_sockets[i].pcs_flags & 2121 PCS_CARD_PRESENT) ? 2122 "card present" : "no card"); 2123 #endif 2124 } 2125 } 2126 2127 /* 2128 * pcic_intr(caddr_t, caddr_t) 2129 * interrupt handler for the PCIC style adapter 2130 * handles all basic interrupts and also checks 2131 * for status changes and notifies the nexus if 2132 * necessary 2133 * 2134 * On PCI bus adapters, also handles all card 2135 * IO interrupts. 2136 */ 2137 /*ARGSUSED*/ 2138 uint32_t 2139 pcic_intr(caddr_t arg1, caddr_t arg2) 2140 { 2141 pcicdev_t *pcic = (pcicdev_t *)arg1; 2142 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2143 uint8_t status; 2144 uint_t io_ints; 2145 2146 #if defined(PCIC_DEBUG) 2147 pcic_err(pcic->dip, 0xf, 2148 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2149 " pc_numsockets=%d \n", 2150 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2151 #endif 2152 2153 if (!(pcic->pc_flags & PCF_ATTACHED)) 2154 return (DDI_INTR_UNCLAIMED); 2155 2156 mutex_enter(&pcic->intr_lock); 2157 2158 if (pcic->pc_flags & PCF_SUSPENDED) { 2159 mutex_exit(&pcic->intr_lock); 2160 return (ret); 2161 } 2162 2163 /* 2164 * need to change to only ACK and touch the slot that 2165 * actually caused the interrupt. Currently everything 2166 * is acked 2167 * 2168 * we need to look at all known sockets to determine 2169 * what might have happened, so step through the list 2170 * of them 2171 */ 2172 2173 /* 2174 * Set the bitmask for IO interrupts to initially include all sockets 2175 */ 2176 io_ints = (1 << pcic->pc_numsockets) - 1; 2177 2178 for (i = 0; i < pcic->pc_numsockets; i++) { 2179 int card_type; 2180 pcic_socket_t *sockp; 2181 int value_cb = 0; 2182 2183 sockp = &pcic->pc_sockets[i]; 2184 /* get the socket's I/O addresses */ 2185 2186 if (sockp->pcs_flags & PCS_WAITING) { 2187 io_ints &= ~(1 << i); 2188 continue; 2189 } 2190 2191 if (sockp->pcs_flags & PCS_CARD_IO) 2192 card_type = IF_IO; 2193 else 2194 card_type = IF_MEMORY; 2195 2196 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2197 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2198 2199 value = pcic_change(pcic, i); 2200 2201 if ((value != 0) || (value_cb != 0)) { 2202 int x = pcic->pc_cb_arg; 2203 2204 ret = DDI_INTR_CLAIMED; 2205 2206 #if defined(PCIC_DEBUG) 2207 pcic_err(pcic->dip, 0x9, 2208 "card_type = %d, value_cb = 0x%x\n", 2209 card_type, 2210 value_cb ? value_cb : 2211 pcic_getcb(pcic, CB_STATUS_EVENT)); 2212 if (pcic_debug) 2213 cmn_err(CE_CONT, 2214 "\tchange on socket %d (%x)\n", i, 2215 value); 2216 #endif 2217 /* find out what happened */ 2218 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2219 2220 /* acknowledge the interrupt */ 2221 if (value_cb) 2222 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2223 2224 if (value) 2225 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2226 value); 2227 2228 if (pcic->pc_callback == NULL) { 2229 /* if not callback handler, nothing to do */ 2230 continue; 2231 } 2232 2233 /* Card Detect */ 2234 if (value & PCIC_CD_DETECT || 2235 value_cb & CB_PS_CCDMASK) { 2236 uint8_t irq; 2237 #if defined(PCIC_DEBUG) 2238 if (pcic_debug) 2239 cmn_err(CE_CONT, 2240 "\tcd_detect: status=%x," 2241 " flags=%x\n", 2242 status, sockp->pcs_flags); 2243 #else 2244 #ifdef lint 2245 if (status == 0) 2246 status++; 2247 #endif 2248 #endif 2249 /* 2250 * Turn off all interrupts for this socket here. 2251 */ 2252 irq = pcic_getb(pcic, sockp->pcs_socket, 2253 PCIC_MANAGEMENT_INT); 2254 irq &= ~PCIC_CHANGE_MASK; 2255 pcic_putb(pcic, sockp->pcs_socket, 2256 PCIC_MANAGEMENT_INT, irq); 2257 2258 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2259 2260 /* 2261 * Put the socket in debouncing state so that 2262 * the leaf driver won't receive interrupts. 2263 * Crucial for handling surprise-removal. 2264 */ 2265 sockp->pcs_flags |= PCS_DEBOUNCING; 2266 2267 if (!sockp->pcs_cd_softint_flg) { 2268 sockp->pcs_cd_softint_flg = 1; 2269 (void) ddi_intr_trigger_softint( 2270 sockp->pcs_cd_softint_hdl, NULL); 2271 } 2272 2273 io_ints &= ~(1 << i); 2274 } /* PCIC_CD_DETECT */ 2275 2276 /* Ready/Change Detect */ 2277 sockp->pcs_state ^= SBM_RDYBSY; 2278 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2279 sockp->pcs_flags |= PCS_READY; 2280 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2281 } 2282 2283 /* Battery Warn Detect */ 2284 if (card_type == IF_MEMORY && 2285 value & PCIC_BW_DETECT && 2286 !(sockp->pcs_state & SBM_BVD2)) { 2287 sockp->pcs_state |= SBM_BVD2; 2288 PC_CALLBACK(pcic->dip, x, 2289 PCE_CARD_BATTERY_WARN, i); 2290 } 2291 2292 /* Battery Dead Detect */ 2293 if (value & PCIC_BD_DETECT) { 2294 /* 2295 * need to work out event if RI not enabled 2296 * and card_type == IF_IO 2297 */ 2298 if (card_type == IF_MEMORY && 2299 !(sockp->pcs_state & SBM_BVD1)) { 2300 sockp->pcs_state |= SBM_BVD1; 2301 PC_CALLBACK(pcic->dip, x, 2302 PCE_CARD_BATTERY_DEAD, 2303 i); 2304 } else { 2305 /* 2306 * information in pin replacement 2307 * register if one is available 2308 */ 2309 PC_CALLBACK(pcic->dip, x, 2310 PCE_CARD_STATUS_CHANGE, 2311 i); 2312 } /* IF_MEMORY */ 2313 } /* PCIC_BD_DETECT */ 2314 } /* if pcic_change */ 2315 /* 2316 * for any controllers that we can detect whether a socket 2317 * had an interrupt for the PC Card, we should sort that out 2318 * here. 2319 */ 2320 } /* for pc_numsockets */ 2321 2322 /* 2323 * If we're on a PCI bus, we may need to cycle through each IO 2324 * interrupt handler that is registered since they all 2325 * share the same interrupt line. 2326 */ 2327 2328 2329 #if defined(PCIC_DEBUG) 2330 pcic_err(pcic->dip, 0xf, 2331 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2332 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2333 #endif 2334 2335 if (io_ints) { 2336 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED) 2337 ret = DDI_INTR_CLAIMED; 2338 } 2339 2340 mutex_exit(&pcic->intr_lock); 2341 2342 #if defined(PCIC_DEBUG) 2343 pcic_err(pcic->dip, 0xf, 2344 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2345 ret, value, DDI_INTR_CLAIMED); 2346 #endif 2347 2348 return (ret); 2349 } 2350 2351 /* 2352 * pcic_change() 2353 * check to see if this socket had a change in state 2354 * by checking the status change register 2355 */ 2356 static int 2357 pcic_change(pcicdev_t *pcic, int socket) 2358 { 2359 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2360 } 2361 2362 /* 2363 * pcic_do_io_intr - calls client interrupt handlers 2364 */ 2365 static int 2366 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2367 { 2368 inthandler_t *tmp; 2369 int ret = DDI_INTR_UNCLAIMED; 2370 2371 #if defined(PCIC_DEBUG) 2372 pcic_err(pcic->dip, 0xf, 2373 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2374 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2375 #endif 2376 2377 if (pcic->irq_top != NULL) { 2378 tmp = pcic->irq_current; 2379 2380 do { 2381 int cur = pcic->irq_current->socket; 2382 pcic_socket_t *sockp = 2383 &pcic->pc_sockets[cur]; 2384 2385 #if defined(PCIC_DEBUG) 2386 pcic_err(pcic->dip, 0xf, 2387 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2388 sockp->pcs_flags, PCS_CARD_PRESENT); 2389 pcic_err(pcic->dip, 0xf, 2390 "\t sockets=%d cur=%d intr=%p arg1=%p " 2391 "arg2=%p\n", 2392 sockets, cur, (void *)pcic->irq_current->intr, 2393 pcic->irq_current->arg1, 2394 pcic->irq_current->arg2); 2395 #endif 2396 if ((sockp->pcs_flags & PCS_CARD_PRESENT) && 2397 !(sockp->pcs_flags & PCS_DEBOUNCING) && 2398 (sockets & (1 << cur))) { 2399 2400 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2401 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2402 ret = DDI_INTR_CLAIMED; 2403 2404 #if defined(PCIC_DEBUG) 2405 pcic_err(pcic->dip, 0xf, 2406 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2407 ret, DDI_INTR_CLAIMED); 2408 #endif 2409 } 2410 2411 2412 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2413 pcic->irq_current = pcic->irq_top; 2414 2415 } while (pcic->irq_current != tmp); 2416 2417 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2418 pcic->irq_current = pcic->irq_top; 2419 2420 } else { 2421 ret = DDI_INTR_UNCLAIMED; 2422 } 2423 2424 #if defined(PCIC_DEBUG) 2425 pcic_err(pcic->dip, 0xf, 2426 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2427 ret, DDI_INTR_CLAIMED); 2428 #endif 2429 2430 return (ret); 2431 2432 } 2433 2434 /* 2435 * pcic_inquire_adapter() 2436 * SocketServices InquireAdapter function 2437 * get characteristics of the physical adapter 2438 */ 2439 /*ARGSUSED*/ 2440 static int 2441 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2442 { 2443 anp_t *anp = ddi_get_driver_private(dip); 2444 pcicdev_t *pcic = anp->an_private; 2445 2446 config->NumSockets = pcic->pc_numsockets; 2447 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2448 config->NumEDCs = 0; 2449 config->AdpCaps = 0; 2450 config->ActiveHigh = 0; 2451 config->ActiveLow = PCIC_AVAIL_IRQS; 2452 config->NumPower = pcic->pc_numpower; 2453 config->power_entry = pcic->pc_power; /* until we resolve this */ 2454 #if defined(PCIC_DEBUG) 2455 if (pcic_debug) { 2456 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2457 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2458 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2459 } 2460 #endif 2461 config->ResourceFlags = 0; 2462 switch (pcic->pc_intr_mode) { 2463 case PCIC_INTR_MODE_PCI_1: 2464 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2465 RES_IRQ_SHAREABLE; 2466 break; 2467 } 2468 return (SUCCESS); 2469 } 2470 2471 /* 2472 * pcic_callback() 2473 * The PCMCIA nexus calls us via this function 2474 * in order to set the callback function we are 2475 * to call the nexus with 2476 */ 2477 /*ARGSUSED*/ 2478 static int 2479 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2480 { 2481 anp_t *anp = ddi_get_driver_private(dip); 2482 pcicdev_t *pcic = anp->an_private; 2483 2484 if (handler != NULL) { 2485 pcic->pc_callback = handler; 2486 pcic->pc_cb_arg = arg; 2487 pcic->pc_flags |= PCF_CALLBACK; 2488 } else { 2489 pcic->pc_callback = NULL; 2490 pcic->pc_cb_arg = 0; 2491 pcic->pc_flags &= ~PCF_CALLBACK; 2492 } 2493 /* 2494 * we're now registered with the nexus 2495 * it is acceptable to do callbacks at this point. 2496 * don't call back from here though since it could block 2497 */ 2498 return (PC_SUCCESS); 2499 } 2500 2501 /* 2502 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2503 * calculate the speed bits from the specified memory speed 2504 * there may be more to do here 2505 */ 2506 2507 static int 2508 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2509 { 2510 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2511 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2512 2513 switch (pcic->pc_type) { 2514 case PCIC_I82365SL: 2515 case PCIC_VADEM: 2516 case PCIC_VADEM_VG469: 2517 default: 2518 /* Intel chip wants it in waitstates */ 2519 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2520 if (speed <= wspeed) 2521 wspeed = 0; 2522 else if (speed <= (wspeed += mhztons(bspeed))) 2523 wspeed = 1; 2524 else if (speed <= (wspeed += mhztons(bspeed))) 2525 wspeed = 2; 2526 else 2527 wspeed = 3; 2528 wspeed <<= 6; /* put in right bit positions */ 2529 break; 2530 2531 case PCIC_INTEL_i82092: 2532 wspeed = SYSMEM_82092_80NS; 2533 if (speed > 80) 2534 wspeed = SYSMEM_82092_100NS; 2535 if (speed > 100) 2536 wspeed = SYSMEM_82092_150NS; 2537 if (speed > 150) 2538 wspeed = SYSMEM_82092_200NS; 2539 if (speed > 200) 2540 wspeed = SYSMEM_82092_250NS; 2541 if (speed > 250) 2542 wspeed = SYSMEM_82092_600NS; 2543 wspeed <<= 5; /* put in right bit positions */ 2544 break; 2545 2546 } /* switch */ 2547 2548 return (wspeed); 2549 } 2550 2551 /* 2552 * These values are taken from the PC Card Standard Electrical Specification. 2553 * Generally the larger value is taken if 2 are possible. 2554 */ 2555 static struct pcic_card_times { 2556 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2557 uint16_t setup; /* Corresponding address setup time. */ 2558 uint16_t width; /* Corresponding width, OE or WE. */ 2559 uint16_t hold; /* Corresponding data or address hold time. */ 2560 } pcic_card_times[] = { 2561 2562 /* 2563 * Note: The rounded up times for 250, 200 & 150 have been increased 2564 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2565 * See BugID 00663. 2566 */ 2567 2568 /* 2569 * Rounded up times Original times from 2570 * that add up to the the PCMCIA Spec. 2571 * cycle time. 2572 */ 2573 {600, 180, 370, 140}, /* 100, 300, 70 */ 2574 {400, 120, 300, 90}, /* Made this one up */ 2575 {250, 100, 190, 70}, /* 30, 150, 30 */ 2576 {200, 80, 170, 70}, /* 20, 120, 30 */ 2577 {150, 50, 110, 40}, /* 20, 80, 20 */ 2578 {100, 40, 80, 40}, /* 10, 60, 15 */ 2579 {0, 10, 60, 15} /* 10, 60, 15 */ 2580 }; 2581 2582 /* 2583 * pcic_set_cdtimers 2584 * This is specific to several Cirrus Logic chips 2585 */ 2586 static void 2587 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2588 { 2589 int cmd, set, rec, offset, clk_pulse; 2590 struct pcic_card_times *ctp; 2591 2592 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2593 offset = 3; 2594 else 2595 offset = 0; 2596 2597 clk_pulse = mhztons(pcic->bus_speed); 2598 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++); 2599 2600 /* 2601 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2602 */ 2603 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2604 if (set < 0) 2605 set = 0; 2606 2607 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2608 if (cmd < 0) 2609 cmd = 0; 2610 2611 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2612 if (rec < 0) 2613 rec = 0; 2614 2615 #if defined(PCIC_DEBUG) 2616 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2617 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2618 (unsigned)speed, offset == 3 ? 1 : 0, 2619 ctp->cycle, clk_pulse, cmd, set, rec); 2620 #endif 2621 2622 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2623 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2624 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2625 } 2626 2627 /* 2628 * pcic_set_window 2629 * essentially the same as the Socket Services specification 2630 * We use socket and not adapter since they are identifiable 2631 * but the rest is the same 2632 * 2633 * dip pcic driver's device information 2634 * window parameters for the request 2635 */ 2636 static int 2637 pcic_set_window(dev_info_t *dip, set_window_t *window) 2638 { 2639 anp_t *anp = ddi_get_driver_private(dip); 2640 pcicdev_t *pcic = anp->an_private; 2641 int select; 2642 int socket, pages, which, ret; 2643 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2644 ra_return_t res; 2645 ndi_ra_request_t req; 2646 uint32_t base = window->base; 2647 2648 #if defined(PCIC_DEBUG) 2649 if (pcic_debug) { 2650 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2651 cmn_err(CE_CONT, 2652 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2653 window->window, window->socket, window->WindowSize, 2654 window->speed); 2655 cmn_err(CE_CONT, 2656 "\tbase=%x, state=%x\n", (unsigned)window->base, 2657 (unsigned)window->state); 2658 } 2659 #endif 2660 2661 /* 2662 * do some basic sanity checking on what we support 2663 * we don't do paged mode 2664 */ 2665 if (window->state & WS_PAGED) { 2666 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2667 return (BAD_ATTRIBUTE); 2668 } 2669 2670 /* 2671 * we don't care about previous mappings. 2672 * Card Services will deal with that so don't 2673 * even check 2674 */ 2675 2676 socket = window->socket; 2677 2678 if (!(window->state & WS_IO)) { 2679 int win, tmp; 2680 pcs_memwin_t *memp; 2681 #if defined(PCIC_DEBUG) 2682 if (pcic_debug) 2683 cmn_err(CE_CONT, "\twindow type is memory\n"); 2684 #endif 2685 /* this is memory window mapping */ 2686 win = window->window % PCIC_NUMWINSOCK; 2687 tmp = window->window / PCIC_NUMWINSOCK; 2688 2689 /* only windows 2-6 can do memory mapping */ 2690 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2691 cmn_err(CE_CONT, 2692 "\tattempt to map to non-mem window\n"); 2693 return (BAD_WINDOW); 2694 } 2695 2696 if (window->WindowSize == 0) 2697 window->WindowSize = MEM_MIN; 2698 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2699 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2700 return (BAD_SIZE); 2701 } 2702 2703 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2704 2705 memp = &sockp->pcs_windows[win].mem; 2706 memp->pcw_speed = window->speed; 2707 2708 win -= PCIC_IOWINDOWS; /* put in right range */ 2709 2710 if (window->WindowSize != memp->pcw_len) 2711 which = memp->pcw_len; 2712 else 2713 which = 0; 2714 2715 if (window->state & WS_ENABLED) { 2716 uint32_t wspeed; 2717 #if defined(PCIC_DEBUG) 2718 if (pcic_debug) { 2719 cmn_err(CE_CONT, 2720 "\tbase=%x, win=%d\n", (unsigned)base, 2721 win); 2722 if (which) 2723 cmn_err(CE_CONT, 2724 "\tneed to remap window\n"); 2725 } 2726 #endif 2727 2728 if (which && (memp->pcw_status & PCW_MAPPED)) { 2729 ddi_regs_map_free(&memp->pcw_handle); 2730 res.ra_addr_lo = memp->pcw_base; 2731 res.ra_len = memp->pcw_len; 2732 (void) pcmcia_free_mem(memp->res_dip, &res); 2733 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2734 memp->pcw_hostmem = NULL; 2735 memp->pcw_base = NULL; 2736 memp->pcw_len = 0; 2737 } 2738 2739 which = window->WindowSize >> PAGE_SHIFT; 2740 2741 if (!(memp->pcw_status & PCW_MAPPED)) { 2742 ret = 0; 2743 2744 memp->pcw_base = base; 2745 bzero(&req, sizeof (req)); 2746 req.ra_len = which << PAGE_SHIFT; 2747 req.ra_addr = (uint64_t)memp->pcw_base; 2748 req.ra_boundbase = pcic->pc_base; 2749 req.ra_boundlen = pcic->pc_bound; 2750 req.ra_flags = (memp->pcw_base ? 2751 NDI_RA_ALLOC_SPECIFIED : 0) | 2752 NDI_RA_ALLOC_BOUNDED; 2753 req.ra_align_mask = 2754 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2755 #if defined(PCIC_DEBUG) 2756 pcic_err(dip, 8, 2757 "\tlen 0x%"PRIx64 2758 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2759 " blen 0x%"PRIx64" flags 0x%x" 2760 " algn 0x%"PRIx64"\n", 2761 req.ra_len, req.ra_addr, 2762 req.ra_boundbase, 2763 req.ra_boundlen, req.ra_flags, 2764 req.ra_align_mask); 2765 #endif 2766 2767 ret = pcmcia_alloc_mem(dip, &req, &res, 2768 &memp->res_dip); 2769 if (ret == DDI_FAILURE) { 2770 mutex_exit(&pcic->pc_lock); 2771 cmn_err(CE_WARN, 2772 "\tpcmcia_alloc_mem() failed\n"); 2773 return (BAD_SIZE); 2774 } 2775 memp->pcw_base = res.ra_addr_lo; 2776 base = memp->pcw_base; 2777 2778 #if defined(PCIC_DEBUG) 2779 if (pcic_debug) 2780 cmn_err(CE_CONT, 2781 "\tsetwindow: new base=%x\n", 2782 (unsigned)memp->pcw_base); 2783 #endif 2784 memp->pcw_len = window->WindowSize; 2785 2786 which = pcmcia_map_reg(pcic->dip, 2787 window->child, 2788 &res, 2789 (uint32_t)(window->state & 2790 0xffff) | 2791 (window->socket << 16), 2792 (caddr_t *)&memp->pcw_hostmem, 2793 &memp->pcw_handle, 2794 &window->attr, NULL); 2795 2796 if (which != DDI_SUCCESS) { 2797 2798 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2799 "failed\n"); 2800 2801 res.ra_addr_lo = memp->pcw_base; 2802 res.ra_len = memp->pcw_len; 2803 (void) pcmcia_free_mem(memp->res_dip, &res); 2804 2805 mutex_exit(&pcic->pc_lock); 2806 2807 return (BAD_WINDOW); 2808 } 2809 memp->pcw_status |= PCW_MAPPED; 2810 #if defined(PCIC_DEBUG) 2811 if (pcic_debug) 2812 cmn_err(CE_CONT, 2813 "\tmap=%x, hostmem=%p\n", 2814 which, 2815 (void *)memp->pcw_hostmem); 2816 #endif 2817 } else { 2818 base = memp->pcw_base; 2819 } 2820 2821 /* report the handle back to caller */ 2822 window->handle = memp->pcw_handle; 2823 2824 #if defined(PCIC_DEBUG) 2825 if (pcic_debug) { 2826 cmn_err(CE_CONT, 2827 "\twindow mapped to %x@%x len=%d\n", 2828 (unsigned)window->base, 2829 (unsigned)memp->pcw_base, 2830 memp->pcw_len); 2831 } 2832 #endif 2833 2834 /* find the register set offset */ 2835 select = win * PCIC_MEM_1_OFFSET; 2836 #if defined(PCIC_DEBUG) 2837 if (pcic_debug) 2838 cmn_err(CE_CONT, "\tselect=%x\n", select); 2839 #endif 2840 2841 /* 2842 * at this point, the register window indicator has 2843 * been converted to be an offset from the first 2844 * set of registers that are used for programming 2845 * the window mapping and the offset used to select 2846 * the correct set of registers to access the 2847 * specified socket. This allows basing everything 2848 * off the _0 window 2849 */ 2850 2851 /* map the physical page base address */ 2852 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2853 which |= (window->speed <= MEM_SPEED_MIN) ? 2854 SYSMEM_ZERO_WAIT : 0; 2855 2856 /* need to select register set */ 2857 select = PCIC_MEM_1_OFFSET * win; 2858 2859 pcic_putb(pcic, socket, 2860 PCIC_SYSMEM_0_STARTLOW + select, 2861 SYSMEM_LOW(base)); 2862 pcic_putb(pcic, socket, 2863 PCIC_SYSMEM_0_STARTHI + select, 2864 SYSMEM_HIGH(base) | which); 2865 2866 /* 2867 * Some adapters can decode window addresses greater 2868 * than 16-bits worth, so handle them here. 2869 */ 2870 switch (pcic->pc_type) { 2871 case PCIC_INTEL_i82092: 2872 pcic_putb(pcic, socket, 2873 PCIC_82092_CPAGE, 2874 SYSMEM_EXT(base)); 2875 break; 2876 case PCIC_CL_PD6729: 2877 case PCIC_CL_PD6730: 2878 clext_reg_write(pcic, socket, 2879 PCIC_CLEXT_MMAP0_UA + win, 2880 SYSMEM_EXT(base)); 2881 break; 2882 case PCIC_TI_PCI1130: 2883 /* 2884 * Note that the TI chip has one upper byte 2885 * per socket so all windows get bound to a 2886 * 16MB segment. This must be detected and 2887 * handled appropriately. We can detect that 2888 * it is done by seeing if the pc_base has 2889 * changed and changing when the register 2890 * is first set. This will force the bounds 2891 * to be correct. 2892 */ 2893 if (pcic->pc_bound == 0xffffffff) { 2894 pcic_putb(pcic, socket, 2895 PCIC_TI_WINDOW_PAGE_PCI, 2896 SYSMEM_EXT(base)); 2897 pcic->pc_base = SYSMEM_EXT(base) << 24; 2898 pcic->pc_bound = 0x1000000; 2899 } 2900 break; 2901 case PCIC_TI_PCI1031: 2902 case PCIC_TI_PCI1131: 2903 case PCIC_TI_PCI1250: 2904 case PCIC_TI_PCI1225: 2905 case PCIC_TI_PCI1221: 2906 case PCIC_SMC_34C90: 2907 case PCIC_CL_PD6832: 2908 case PCIC_RICOH_RL5C466: 2909 case PCIC_TI_PCI1410: 2910 case PCIC_ENE_1410: 2911 case PCIC_TI_PCI1510: 2912 case PCIC_TI_PCI1520: 2913 case PCIC_O2_OZ6912: 2914 case PCIC_TI_PCI1420: 2915 case PCIC_ENE_1420: 2916 case PCIC_TI_VENDOR: 2917 case PCIC_TOSHIBA_TOPIC100: 2918 case PCIC_TOSHIBA_TOPIC95: 2919 case PCIC_TOSHIBA_VENDOR: 2920 case PCIC_RICOH_VENDOR: 2921 case PCIC_O2MICRO_VENDOR: 2922 pcic_putb(pcic, socket, 2923 PCIC_YENTA_MEM_PAGE + win, 2924 SYSMEM_EXT(base)); 2925 break; 2926 default: 2927 cmn_err(CE_NOTE, "pcic_set_window: unknown " 2928 "cardbus vendor:0x%X\n", 2929 pcic->pc_type); 2930 pcic_putb(pcic, socket, 2931 PCIC_YENTA_MEM_PAGE + win, 2932 SYSMEM_EXT(base)); 2933 2934 break; 2935 } /* switch */ 2936 2937 /* 2938 * specify the length of the mapped range 2939 * we convert to pages (rounding up) so that 2940 * the hardware gets the right thing 2941 */ 2942 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 2943 2944 /* 2945 * Setup this window's timing. 2946 */ 2947 switch (pcic->pc_type) { 2948 case PCIC_CL_PD6729: 2949 case PCIC_CL_PD6730: 2950 case PCIC_CL_PD6710: 2951 case PCIC_CL_PD6722: 2952 wspeed = SYSMEM_CLTIMER_SET_0; 2953 pcic_set_cdtimers(pcic, socket, 2954 window->speed, 2955 wspeed); 2956 break; 2957 2958 case PCIC_INTEL_i82092: 2959 default: 2960 wspeed = pcic_calc_speed(pcic, window->speed); 2961 break; 2962 } /* switch */ 2963 2964 #if defined(PCIC_DEBUG) 2965 if (pcic_debug) 2966 cmn_err(CE_CONT, 2967 "\twindow %d speed bits = %x for " 2968 "%dns\n", 2969 win, (unsigned)wspeed, window->speed); 2970 #endif 2971 2972 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 2973 SYSMEM_LOW(base + 2974 (pages * PCIC_PAGE)-1)); 2975 2976 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 2977 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 2978 wspeed); 2979 2980 /* 2981 * now map the card's memory pages - we start with page 2982 * 0 2983 * we also default to AM -- set page might change it 2984 */ 2985 base = memp->pcw_base; 2986 pcic_putb(pcic, socket, 2987 PCIC_CARDMEM_0_LOW + select, 2988 CARDMEM_LOW(0 - (uint32_t)base)); 2989 2990 pcic_putb(pcic, socket, 2991 PCIC_CARDMEM_0_HI + select, 2992 CARDMEM_HIGH(0 - (uint32_t)base) | 2993 CARDMEM_REG_ACTIVE); 2994 2995 /* 2996 * enable the window even though redundant 2997 * and SetPage may do it again. 2998 */ 2999 select = pcic_getb(pcic, socket, 3000 PCIC_MAPPING_ENABLE); 3001 select |= SYSMEM_WINDOW(win); 3002 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3003 memp->pcw_offset = 0; 3004 memp->pcw_status |= PCW_ENABLED; 3005 } else { 3006 /* 3007 * not only do we unmap the memory, the 3008 * window has been turned off. 3009 */ 3010 if (which && memp->pcw_status & PCW_MAPPED) { 3011 ddi_regs_map_free(&memp->pcw_handle); 3012 res.ra_addr_lo = memp->pcw_base; 3013 res.ra_len = memp->pcw_len; 3014 (void) pcmcia_free_mem(memp->res_dip, &res); 3015 memp->pcw_hostmem = NULL; 3016 memp->pcw_status &= ~PCW_MAPPED; 3017 } 3018 3019 /* disable current mapping */ 3020 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3021 select &= ~SYSMEM_WINDOW(win); 3022 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3023 memp->pcw_status &= ~PCW_ENABLED; 3024 } 3025 memp->pcw_len = window->WindowSize; 3026 window->handle = memp->pcw_handle; 3027 #if defined(PCIC_DEBUG) 3028 if (pcic_debug) 3029 xxdmp_all_regs(pcic, window->socket, -1); 3030 #endif 3031 } else { 3032 /* 3033 * This is a request for an IO window 3034 */ 3035 int win, tmp; 3036 pcs_iowin_t *winp; 3037 /* I/O windows */ 3038 #if defined(PCIC_DEBUG) 3039 if (pcic_debug) 3040 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3041 #endif 3042 3043 /* only windows 0 and 1 can do I/O */ 3044 win = window->window % PCIC_NUMWINSOCK; 3045 tmp = window->window / PCIC_NUMWINSOCK; 3046 3047 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3048 cmn_err(CE_WARN, 3049 "\twindow is out of range (%d)\n", 3050 window->window); 3051 return (BAD_WINDOW); 3052 } 3053 3054 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3055 3056 winp = &sockp->pcs_windows[win].io; 3057 winp->pcw_speed = window->speed; 3058 if (window->WindowSize != 1 && window->WindowSize & 1) { 3059 /* we don't want an odd-size window */ 3060 window->WindowSize++; 3061 } 3062 winp->pcw_len = window->WindowSize; 3063 3064 if (window->state & WS_ENABLED) { 3065 if (winp->pcw_status & PCW_MAPPED) { 3066 ddi_regs_map_free(&winp->pcw_handle); 3067 res.ra_addr_lo = winp->pcw_base; 3068 res.ra_len = winp->pcw_len; 3069 (void) pcmcia_free_io(winp->res_dip, &res); 3070 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3071 } 3072 3073 /* 3074 * if the I/O address wasn't allocated, allocate 3075 * it now. If it was allocated, it better 3076 * be free to use. 3077 * The winp->pcw_offset value is set and used 3078 * later on if the particular adapter 3079 * that we're running on has the ability 3080 * to translate IO accesses to the card 3081 * (such as some adapters in the Cirrus 3082 * Logic family). 3083 */ 3084 winp->pcw_offset = 0; 3085 3086 /* 3087 * Setup the request parameters for the 3088 * requested base and length. If 3089 * we're on an adapter that has 3090 * IO window offset registers, then 3091 * we don't need a specific base 3092 * address, just a length, and then 3093 * we'll cause the correct IO address 3094 * to be generated on the socket by 3095 * setting up the IO window offset 3096 * registers. 3097 * For adapters that support this capability, we 3098 * always use the IO window offset registers, 3099 * even if the passed base/length would be in 3100 * range. 3101 */ 3102 base = window->base; 3103 bzero(&req, sizeof (req)); 3104 req.ra_len = window->WindowSize; 3105 3106 req.ra_addr = (uint64_t) 3107 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3108 req.ra_flags = (req.ra_addr) ? 3109 NDI_RA_ALLOC_SPECIFIED : 0; 3110 3111 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3112 /* need to rethink this */ 3113 req.ra_boundbase = pcic->pc_iobase; 3114 req.ra_boundlen = pcic->pc_iobound; 3115 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3116 3117 #if defined(PCIC_DEBUG) 3118 pcic_err(dip, 8, 3119 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3120 "bbase 0x%"PRIx64 3121 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3122 PRIx64"\n", 3123 req.ra_len, (uint64_t)req.ra_addr, 3124 req.ra_boundbase, 3125 req.ra_boundlen, req.ra_flags, 3126 req.ra_align_mask); 3127 #endif 3128 3129 /* 3130 * Try to allocate the space. If we fail this, 3131 * return the appropriate error depending 3132 * on whether the caller specified a 3133 * specific base address or not. 3134 */ 3135 if (pcmcia_alloc_io(dip, &req, &res, 3136 &winp->res_dip) == DDI_FAILURE) { 3137 winp->pcw_status &= ~PCW_ENABLED; 3138 mutex_exit(&pcic->pc_lock); 3139 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3140 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3141 "bbase 0x%" PRIx64 3142 "blen 0x%" PRIx64 "flags 0x%x" 3143 "algn 0x%" PRIx64 "\n", 3144 req.ra_len, req.ra_addr, 3145 req.ra_boundbase, 3146 req.ra_boundlen, req.ra_flags, 3147 req.ra_align_mask); 3148 3149 return (base?BAD_BASE:BAD_SIZE); 3150 } /* pcmcia_alloc_io */ 3151 3152 /* 3153 * Don't change the original base. Either we use 3154 * the offset registers below (PCF_IO_REMAP is set) 3155 * or it was allocated correctly anyway. 3156 */ 3157 winp->pcw_base = res.ra_addr_lo; 3158 3159 #if defined(PCIC_DEBUG) 3160 pcic_err(dip, 8, 3161 "\tsetwindow: new base=%x orig base 0x%x\n", 3162 (unsigned)winp->pcw_base, base); 3163 #endif 3164 3165 if ((which = pcmcia_map_reg(pcic->dip, 3166 window->child, 3167 &res, 3168 (uint32_t)(window->state & 3169 0xffff) | 3170 (window->socket << 16), 3171 (caddr_t *)&winp->pcw_hostmem, 3172 &winp->pcw_handle, 3173 &window->attr, 3174 base)) != DDI_SUCCESS) { 3175 3176 cmn_err(CE_WARN, "pcmcia_map_reg()" 3177 "failed\n"); 3178 3179 res.ra_addr_lo = winp->pcw_base; 3180 res.ra_len = winp->pcw_len; 3181 (void) pcmcia_free_io(winp->res_dip, &res); 3182 3183 mutex_exit(&pcic->pc_lock); 3184 return (BAD_WINDOW); 3185 } 3186 3187 window->handle = winp->pcw_handle; 3188 winp->pcw_status |= PCW_MAPPED; 3189 3190 /* find the register set offset */ 3191 select = win * PCIC_IO_OFFSET; 3192 3193 #if defined(PCIC_DEBUG) 3194 if (pcic_debug) { 3195 cmn_err(CE_CONT, 3196 "\tenable: window=%d, select=%x, " 3197 "base=%x, handle=%p\n", 3198 win, select, 3199 (unsigned)window->base, 3200 (void *)window->handle); 3201 } 3202 #endif 3203 /* 3204 * at this point, the register window indicator has 3205 * been converted to be an offset from the first 3206 * set of registers that are used for programming 3207 * the window mapping and the offset used to select 3208 * the correct set of registers to access the 3209 * specified socket. This allows basing everything 3210 * off the _0 window 3211 */ 3212 3213 /* map the I/O base in */ 3214 pcic_putb(pcic, socket, 3215 PCIC_IO_ADDR_0_STARTLOW + select, 3216 LOW_BYTE((uint32_t)winp->pcw_base)); 3217 pcic_putb(pcic, socket, 3218 PCIC_IO_ADDR_0_STARTHI + select, 3219 HIGH_BYTE((uint32_t)winp->pcw_base)); 3220 3221 pcic_putb(pcic, socket, 3222 PCIC_IO_ADDR_0_STOPLOW + select, 3223 LOW_BYTE((uint32_t)winp->pcw_base + 3224 window->WindowSize - 1)); 3225 pcic_putb(pcic, socket, 3226 PCIC_IO_ADDR_0_STOPHI + select, 3227 HIGH_BYTE((uint32_t)winp->pcw_base + 3228 window->WindowSize - 1)); 3229 3230 /* 3231 * We've got the requested IO space, now see if we 3232 * need to adjust the IO window offset registers 3233 * so that the correct IO address is generated 3234 * at the socket. If this window doesn't have 3235 * this capability, then we're all done setting 3236 * up the IO resources. 3237 */ 3238 if (pcic->pc_flags & PCF_IO_REMAP) { 3239 3240 3241 /* 3242 * Note that only 16 bits are used to program 3243 * the registers but leave 32 bits on pcw_offset 3244 * so that we can generate the original base 3245 * in get_window() 3246 */ 3247 winp->pcw_offset = (base - winp->pcw_base); 3248 3249 pcic_putb(pcic, socket, 3250 PCIC_IO_OFFSET_LOW + 3251 (win * PCIC_IO_OFFSET_OFFSET), 3252 winp->pcw_offset & 0x0ff); 3253 pcic_putb(pcic, socket, 3254 PCIC_IO_OFFSET_HI + 3255 (win * PCIC_IO_OFFSET_OFFSET), 3256 (winp->pcw_offset >> 8) & 0x0ff); 3257 3258 } /* PCF_IO_REMAP */ 3259 3260 /* now get the other details (size, etc) right */ 3261 3262 /* 3263 * Set the data size control bits here. Most of the 3264 * adapters will ignore IOMEM_16BIT when 3265 * IOMEM_IOCS16 is set, except for the Intel 3266 * 82092, which only pays attention to the 3267 * IOMEM_16BIT bit. Sigh... Intel can't even 3268 * make a proper clone of their own chip. 3269 * The 82092 also apparently can't set the timing 3270 * of I/O windows. 3271 */ 3272 which = (window->state & WS_16BIT) ? 3273 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3274 3275 switch (pcic->pc_type) { 3276 case PCIC_CL_PD6729: 3277 case PCIC_CL_PD6730: 3278 case PCIC_CL_PD6710: 3279 case PCIC_CL_PD6722: 3280 case PCIC_CL_PD6832: 3281 /* 3282 * Select Timer Set 1 - this will take 3283 * effect when the PCIC_IO_CONTROL 3284 * register is written to later on; 3285 * the call to pcic_set_cdtimers 3286 * just sets up the timer itself. 3287 */ 3288 which |= IOMEM_CLTIMER_SET_1; 3289 pcic_set_cdtimers(pcic, socket, 3290 window->speed, 3291 IOMEM_CLTIMER_SET_1); 3292 which |= IOMEM_IOCS16; 3293 break; 3294 case PCIC_TI_PCI1031: 3295 3296 if (window->state & WS_16BIT) 3297 which |= IOMEM_WAIT16; 3298 3299 break; 3300 case PCIC_TI_PCI1130: 3301 3302 if (window->state & WS_16BIT) 3303 which |= IOMEM_WAIT16; 3304 3305 break; 3306 case PCIC_INTEL_i82092: 3307 break; 3308 default: 3309 if (window->speed > 3310 mhztons(pcic->bus_speed) * 3) 3311 which |= IOMEM_WAIT16; 3312 #ifdef notdef 3313 if (window->speed < 3314 mhztons(pcic->bus_speed) * 6) 3315 which |= IOMEM_ZERO_WAIT; 3316 #endif 3317 break; 3318 } /* switch (pc_type) */ 3319 3320 /* 3321 * Setup the data width and timing 3322 */ 3323 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3324 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3325 select |= IOMEM_SETWIN(win, which); 3326 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3327 3328 /* 3329 * Enable the IO window 3330 */ 3331 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3332 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3333 select | IOMEM_WINDOW(win)); 3334 3335 winp->pcw_status |= PCW_ENABLED; 3336 3337 #if defined(PCIC_DEBUG) 3338 if (pcic_debug) { 3339 cmn_err(CE_CONT, 3340 "\twhich = %x, select = %x (%x)\n", 3341 which, select, 3342 IOMEM_SETWIN(win, which)); 3343 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3344 } 3345 #endif 3346 } else { 3347 /* 3348 * not only do we unmap the IO space, the 3349 * window has been turned off. 3350 */ 3351 if (winp->pcw_status & PCW_MAPPED) { 3352 ddi_regs_map_free(&winp->pcw_handle); 3353 res.ra_addr_lo = winp->pcw_base; 3354 res.ra_len = winp->pcw_len; 3355 (void) pcmcia_free_io(winp->res_dip, &res); 3356 winp->pcw_status &= ~PCW_MAPPED; 3357 } 3358 3359 /* disable current mapping */ 3360 select = pcic_getb(pcic, socket, 3361 PCIC_MAPPING_ENABLE); 3362 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3363 select &= ~IOMEM_WINDOW(win)); 3364 winp->pcw_status &= ~PCW_ENABLED; 3365 3366 winp->pcw_base = 0; 3367 winp->pcw_len = 0; 3368 winp->pcw_offset = 0; 3369 window->base = 0; 3370 /* now make sure we don't accidentally re-enable */ 3371 /* find the register set offset */ 3372 select = win * PCIC_IO_OFFSET; 3373 pcic_putb(pcic, socket, 3374 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3375 pcic_putb(pcic, socket, 3376 PCIC_IO_ADDR_0_STARTHI + select, 0); 3377 pcic_putb(pcic, socket, 3378 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3379 pcic_putb(pcic, socket, 3380 PCIC_IO_ADDR_0_STOPHI + select, 0); 3381 } 3382 } 3383 mutex_exit(&pcic->pc_lock); 3384 3385 return (SUCCESS); 3386 } 3387 3388 /* 3389 * pcic_card_state() 3390 * compute the instantaneous Card State information 3391 */ 3392 static int 3393 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3394 { 3395 int value, result; 3396 #if defined(PCIC_DEBUG) 3397 int orig_value; 3398 #endif 3399 3400 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3401 3402 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3403 3404 #if defined(PCIC_DEBUG) 3405 orig_value = value; 3406 if (pcic_debug >= 8) 3407 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3408 (void *)sockp, 3409 value, 3410 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3411 sockp->pcs_socket); 3412 #endif 3413 /* 3414 * Lie to socket services if we are not ready. 3415 * This is when we are starting up or during debounce timeouts 3416 * or if the card is a cardbus card. 3417 */ 3418 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3419 !sockp->pcs_debounce_id && 3420 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3421 result = SBM_CD; 3422 3423 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3424 result |= SBM_WP; 3425 if (value & PCIC_POWER_ON) { 3426 if (value & PCIC_READY) 3427 result |= SBM_RDYBSY; 3428 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3429 if (value & PCIC_BVD1) 3430 result |= SBM_BVD1; 3431 if (value & PCIC_BVD2) 3432 result |= SBM_BVD2; 3433 } 3434 } else 3435 result = 0; 3436 3437 mutex_exit(&pcic->pc_lock); 3438 3439 #if defined(PCIC_DEBUG) 3440 pcic_err(pcic->dip, 8, 3441 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3442 (void *) sockp, orig_value, 3443 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3444 sockp->pcs_socket, result); 3445 #endif 3446 3447 return (result); 3448 } 3449 3450 /* 3451 * pcic_set_page() 3452 * SocketServices SetPage function 3453 * set the page of PC Card memory that should be in the mapped 3454 * window 3455 */ 3456 /*ARGSUSED*/ 3457 static int 3458 pcic_set_page(dev_info_t *dip, set_page_t *page) 3459 { 3460 anp_t *anp = ddi_get_driver_private(dip); 3461 pcicdev_t *pcic = anp->an_private; 3462 int select; 3463 int which, socket, window; 3464 uint32_t base; 3465 pcs_memwin_t *memp; 3466 3467 /* get real socket/window numbers */ 3468 window = page->window % PCIC_NUMWINSOCK; 3469 socket = page->window / PCIC_NUMWINSOCK; 3470 3471 #if defined(PCIC_DEBUG) 3472 if (pcic_debug) { 3473 cmn_err(CE_CONT, 3474 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3475 window, socket, page->page); 3476 } 3477 #endif 3478 /* only windows 2-6 work on memory */ 3479 if (window < PCIC_IOWINDOWS) 3480 return (BAD_WINDOW); 3481 3482 /* only one page supported (but any size) */ 3483 if (page->page != 0) 3484 return (BAD_PAGE); 3485 3486 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3487 3488 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3489 window -= PCIC_IOWINDOWS; 3490 3491 #if defined(PCIC_DEBUG) 3492 if (pcic_debug) 3493 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3494 (uint32_t)memp->pcw_base, 3495 (void *)memp->pcw_hostmem, memp->pcw_len); 3496 #endif 3497 3498 /* window must be enabled */ 3499 if (!(memp->pcw_status & PCW_ENABLED)) 3500 return (BAD_ATTRIBUTE); 3501 3502 /* find the register set offset */ 3503 select = window * PCIC_MEM_1_OFFSET; 3504 #if defined(PCIC_DEBUG) 3505 if (pcic_debug) 3506 cmn_err(CE_CONT, "\tselect=%x\n", select); 3507 #endif 3508 3509 /* 3510 * now map the card's memory pages - we start with page 0 3511 */ 3512 3513 which = 0; /* assume simple case */ 3514 if (page->state & PS_ATTRIBUTE) { 3515 which |= CARDMEM_REG_ACTIVE; 3516 memp->pcw_status |= PCW_ATTRIBUTE; 3517 } else { 3518 memp->pcw_status &= ~PCW_ATTRIBUTE; 3519 } 3520 3521 /* 3522 * if caller says Write Protect, enforce it. 3523 */ 3524 if (page->state & PS_WP) { 3525 which |= CARDMEM_WRITE_PROTECT; 3526 memp->pcw_status |= PCW_WP; 3527 } else { 3528 memp->pcw_status &= ~PCW_WP; 3529 } 3530 #if defined(PCIC_DEBUG) 3531 if (pcic_debug) { 3532 cmn_err(CE_CONT, "\tmemory type = %s\n", 3533 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3534 if (which & CARDMEM_WRITE_PROTECT) 3535 cmn_err(CE_CONT, "\twrite protect\n"); 3536 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3537 (unsigned)page->offset, 3538 (unsigned)memp->pcw_base, 3539 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3540 } 3541 #endif 3542 /* address computation based on 64MB range and not larger */ 3543 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3544 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3545 CARDMEM_LOW((int)page->offset - (int)base)); 3546 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3547 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3548 CARDMEM_HIGH((int)page->offset - base) | which); 3549 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3550 3551 /* 3552 * while not really necessary, this just makes sure 3553 * nothing turned the window off behind our backs 3554 */ 3555 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3556 which |= SYSMEM_WINDOW(window); 3557 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3558 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3559 3560 memp->pcw_offset = (off_t)page->offset; 3561 3562 #if defined(PCIC_DEBUG) 3563 if (pcic_debug) { 3564 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3565 (void *)memp->pcw_hostmem, 3566 (uint32_t)*memp->pcw_hostmem); 3567 3568 xxdmp_all_regs(pcic, socket, -1); 3569 3570 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3571 (void *)memp->pcw_hostmem, 3572 (uint32_t)*memp->pcw_hostmem); 3573 } 3574 #endif 3575 3576 if (which & PCW_ATTRIBUTE) 3577 pcic_mswait(pcic, socket, 2); 3578 3579 mutex_exit(&pcic->pc_lock); 3580 3581 return (SUCCESS); 3582 } 3583 3584 /* 3585 * pcic_set_vcc_level() 3586 * 3587 * set voltage based on adapter information 3588 * 3589 * this routine implements a limited solution for support of 3.3v cards. 3590 * the general solution, which would fully support the pcmcia spec 3591 * as far as allowing client drivers to request which voltage levels 3592 * to be set, requires more framework support and driver changes - ess 3593 */ 3594 static int 3595 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3596 { 3597 uint32_t socket_present_state; 3598 3599 #if defined(PCIC_DEBUG) 3600 if (pcic_debug) { 3601 cmn_err(CE_CONT, 3602 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3603 (void *)pcic, socket->VccLevel); 3604 } 3605 #endif 3606 3607 /* 3608 * check VccLevel 3609 * if this is zero, power is being turned off 3610 * if it is non-zero, power is being turned on. 3611 */ 3612 if (socket->VccLevel == 0) { 3613 return (0); 3614 } 3615 3616 /* 3617 * range checking for sanity's sake 3618 */ 3619 if (socket->VccLevel >= pcic->pc_numpower) { 3620 return (BAD_VCC); 3621 } 3622 3623 switch (pcic->pc_io_type) { 3624 /* 3625 * Yenta-compliant adapters have vcc info in the extended registers 3626 * Other adapters can be added as needed, but the 'default' case 3627 * has been left as it was previously so as not to break existing 3628 * adapters. 3629 */ 3630 case PCIC_IO_TYPE_YENTA: 3631 /* 3632 * Here we ignore the VccLevel passed in and read the 3633 * card type from the adapter socket present state register 3634 */ 3635 socket_present_state = 3636 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3637 PCIC_PRESENT_STATE_REG)); 3638 #if defined(PCIC_DEBUG) 3639 if (pcic_debug) { 3640 cmn_err(CE_CONT, 3641 "socket present state = 0x%x\n", 3642 socket_present_state); 3643 } 3644 #endif 3645 switch (socket_present_state & PCIC_VCC_MASK) { 3646 case PCIC_VCC_3VCARD: 3647 /* fall through */ 3648 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3649 socket->VccLevel = PCIC_VCC_3VLEVEL; 3650 return 3651 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3652 case PCIC_VCC_5VCARD: 3653 socket->VccLevel = PCIC_VCC_5VLEVEL; 3654 return 3655 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3656 default: 3657 /* 3658 * if no card is present, this can be the 3659 * case of a client making a SetSocket call 3660 * after card removal. In this case we return 3661 * the current power level 3662 */ 3663 return ((unsigned)ddi_get8(pcic->handle, 3664 pcic->ioaddr + CB_R2_OFFSET + 3665 PCIC_POWER_CONTROL)); 3666 } 3667 3668 default: 3669 3670 switch (socket->VccLevel) { 3671 case PCIC_VCC_3VLEVEL: 3672 return (BAD_VCC); 3673 case PCIC_VCC_5VLEVEL: 3674 /* enable Vcc */ 3675 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3676 default: 3677 return (BAD_VCC); 3678 } 3679 } 3680 } 3681 3682 3683 /* 3684 * pcic_set_socket() 3685 * Socket Services SetSocket call 3686 * sets basic socket configuration 3687 */ 3688 static int 3689 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3690 { 3691 anp_t *anp = ddi_get_driver_private(dip); 3692 pcicdev_t *pcic = anp->an_private; 3693 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3694 int irq, interrupt, mirq; 3695 int powerlevel = 0; 3696 int ind, value, orig_pwrctl; 3697 3698 #if defined(PCIC_DEBUG) 3699 if (pcic_debug) { 3700 cmn_err(CE_CONT, 3701 "pcic_set_socket(dip=%p, socket=%d)" 3702 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3703 socket->socket, socket->VccLevel, socket->Vpp1Level, 3704 socket->Vpp2Level); 3705 } 3706 #endif 3707 /* 3708 * check VccLevel, etc. before setting mutex 3709 * if this is zero, power is being turned off 3710 * if it is non-zero, power is being turned on. 3711 * the default case is to assume Vcc only. 3712 */ 3713 3714 /* this appears to be very implementation specific */ 3715 3716 if (socket->Vpp1Level != socket->Vpp2Level) 3717 return (BAD_VPP); 3718 3719 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3720 powerlevel = 0; 3721 sockp->pcs_vcc = 0; 3722 sockp->pcs_vpp1 = 0; 3723 sockp->pcs_vpp2 = 0; 3724 } else { 3725 #if defined(PCIC_DEBUG) 3726 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3727 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3728 #endif 3729 /* valid Vcc power level? */ 3730 if (socket->VccLevel >= pcic->pc_numpower) 3731 return (BAD_VCC); 3732 3733 switch (pcic_power[socket->VccLevel].PowerLevel) { 3734 case 33: /* 3.3V */ 3735 case 60: /* for bad CIS in Option GPRS card */ 3736 if (!(pcic->pc_flags & PCF_33VCAP)) { 3737 cmn_err(CE_WARN, 3738 "%s%d: Bad Request for 3.3V " 3739 "(Controller incapable)\n", 3740 ddi_get_name(pcic->dip), 3741 ddi_get_instance(pcic->dip)); 3742 return (BAD_VCC); 3743 } 3744 /* FALLTHROUGH */ 3745 case 50: /* 5V */ 3746 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3747 pcic_getcb(pcic, CB_PRESENT_STATE) & 3748 CB_PS_33VCARD) { 3749 /* 3750 * This is actually a 3.3V card. 3751 * Solaris Card Services 3752 * doesn't understand 3.3V 3753 * so we cheat and change 3754 * the setting to the one appropriate to 3.3V. 3755 * Note that this is the entry number 3756 * in the pcic_power[] array. 3757 */ 3758 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3759 } else 3760 sockp->pcs_vcc = socket->VccLevel; 3761 break; 3762 default: 3763 return (BAD_VCC); 3764 } 3765 3766 /* enable Vcc */ 3767 powerlevel = POWER_CARD_ENABLE; 3768 3769 #if defined(PCIC_DEBUG) 3770 if (pcic_debug) { 3771 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3772 socket->VccLevel, powerlevel); 3773 } 3774 #endif 3775 ind = 0; /* default index to 0 power */ 3776 if ((int)socket->Vpp1Level >= 0 && 3777 socket->Vpp1Level < pcic->pc_numpower) { 3778 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3779 & VPP1)) { 3780 return (BAD_VPP); 3781 } 3782 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3783 powerlevel |= pcic_vpp_levels[ind]; 3784 sockp->pcs_vpp1 = socket->Vpp1Level; 3785 } 3786 if ((int)socket->Vpp2Level >= 0 && 3787 socket->Vpp2Level < pcic->pc_numpower) { 3788 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3789 & VPP2)) { 3790 return (BAD_VPP); 3791 } 3792 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3793 powerlevel |= (pcic_vpp_levels[ind] << 2); 3794 sockp->pcs_vpp2 = socket->Vpp2Level; 3795 } 3796 3797 if (pcic->pc_flags & PCF_VPPX) { 3798 /* 3799 * this adapter doesn't allow separate Vpp1/Vpp2 3800 * if one is turned on, both are turned on and only 3801 * the Vpp1 bits should be set 3802 */ 3803 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3804 /* must be the same if one not zero */ 3805 if (sockp->pcs_vpp1 != 0 && 3806 sockp->pcs_vpp2 != 0) { 3807 cmn_err(CE_WARN, 3808 "%s%d: Bad Power Request " 3809 "(Vpp1/2 not the same)\n", 3810 ddi_get_name(pcic->dip), 3811 ddi_get_instance(pcic->dip)); 3812 return (BAD_VPP); 3813 } 3814 } 3815 powerlevel &= ~(3<<2); 3816 } 3817 3818 #if defined(PCIC_DEBUG) 3819 if (pcic_debug) { 3820 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3821 powerlevel, ind); 3822 } 3823 #endif 3824 } 3825 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3826 3827 /* turn socket->IREQRouting off while programming */ 3828 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3829 interrupt &= ~PCIC_INTR_MASK; 3830 if (pcic->pc_flags & PCF_USE_SMI) 3831 interrupt |= PCIC_INTR_ENABLE; 3832 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3833 3834 switch (pcic->pc_type) { 3835 case PCIC_INTEL_i82092: 3836 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3837 PCIC_82092_INT_DISABLE); 3838 break; 3839 default: 3840 break; 3841 } /* switch */ 3842 3843 /* the SCIntMask specifies events to detect */ 3844 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3845 3846 #if defined(PCIC_DEBUG) 3847 if (pcic_debug) 3848 cmn_err(CE_CONT, 3849 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3850 socket->SCIntMask, interrupt, mirq); 3851 #endif 3852 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3853 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3854 mirq & ~PCIC_CHANGE_MASK); 3855 3856 /* save the mask we want to use */ 3857 sockp->pcs_intmask = socket->SCIntMask; 3858 3859 /* 3860 * Until there is a card present it's not worth enabling 3861 * any interrupts except "Card detect". This is done 3862 * elsewhere in the driver so don't change things if 3863 * there is no card! 3864 */ 3865 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3866 3867 /* now update the hardware to reflect events desired */ 3868 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3869 mirq |= PCIC_BD_DETECT; 3870 3871 if (sockp->pcs_intmask & SBM_BVD2) 3872 mirq |= PCIC_BW_DETECT; 3873 3874 if (sockp->pcs_intmask & SBM_RDYBSY) 3875 mirq |= PCIC_RD_DETECT; 3876 3877 if (sockp->pcs_intmask & SBM_CD) 3878 mirq |= PCIC_CD_DETECT; 3879 } 3880 3881 if (sockp->pcs_flags & PCS_READY) { 3882 /* 3883 * card just came ready. 3884 * make sure enough time elapses 3885 * before touching it. 3886 */ 3887 sockp->pcs_flags &= ~PCS_READY; 3888 pcic_mswait(pcic, socket->socket, 10); 3889 } 3890 3891 #if defined(PCIC_DEBUG) 3892 if (pcic_debug) { 3893 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3894 } 3895 #endif 3896 3897 switch (pcic->pc_type) { 3898 case PCIC_I82365SL: 3899 case PCIC_VADEM: 3900 case PCIC_VADEM_VG469: 3901 /* 3902 * The Intel version has different options. This is a 3903 * special case of GPI which might be used for eject 3904 */ 3905 3906 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 3907 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 3908 pcic->pc_flags & PCF_GPI_EJECT) { 3909 irq |= PCIC_GPI_ENABLE; 3910 } else { 3911 irq &= ~PCIC_GPI_ENABLE; 3912 } 3913 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 3914 break; 3915 case PCIC_CL_PD6710: 3916 case PCIC_CL_PD6722: 3917 if (socket->IFType == IF_IO) { 3918 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 3919 value = pcic_getb(pcic, socket->socket, 3920 PCIC_MISC_CTL_1); 3921 if (pcic->pc_flags & PCF_AUDIO) 3922 value |= PCIC_MC_SPEAKER_ENB; 3923 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3924 value); 3925 } else { 3926 value = pcic_getb(pcic, socket->socket, 3927 PCIC_MISC_CTL_1); 3928 value &= ~PCIC_MC_SPEAKER_ENB; 3929 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3930 value); 3931 } 3932 break; 3933 case PCIC_CL_PD6729: 3934 case PCIC_CL_PD6730: 3935 case PCIC_CL_PD6832: 3936 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 3937 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 3938 value |= PCIC_MC_SPEAKER_ENB; 3939 } else { 3940 value &= ~PCIC_MC_SPEAKER_ENB; 3941 } 3942 3943 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 3944 value |= PCIC_MC_3VCC; 3945 else 3946 value &= ~PCIC_MC_3VCC; 3947 3948 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 3949 break; 3950 3951 case PCIC_O2_OZ6912: 3952 value = pcic_getcb(pcic, CB_MISCCTRL); 3953 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 3954 value |= (1<<25); 3955 else 3956 value &= ~(1<<25); 3957 pcic_putcb(pcic, CB_MISCCTRL, value); 3958 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 3959 powerlevel |= 0x08; 3960 break; 3961 3962 case PCIC_TI_PCI1250: 3963 case PCIC_TI_PCI1221: 3964 case PCIC_TI_PCI1225: 3965 case PCIC_TI_PCI1410: 3966 case PCIC_ENE_1410: 3967 case PCIC_TI_PCI1510: 3968 case PCIC_TI_PCI1520: 3969 case PCIC_TI_PCI1420: 3970 case PCIC_ENE_1420: 3971 value = ddi_get8(pcic->cfg_handle, 3972 pcic->cfgaddr + PCIC_CRDCTL_REG); 3973 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 3974 value |= PCIC_CRDCTL_SPKR_ENBL; 3975 } else { 3976 value &= ~PCIC_CRDCTL_SPKR_ENBL; 3977 } 3978 ddi_put8(pcic->cfg_handle, 3979 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 3980 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 3981 powerlevel |= 0x08; 3982 break; 3983 } 3984 3985 /* 3986 * ctlind processing -- we can ignore this 3987 * there aren't any outputs on the chip for this and 3988 * the GUI will display what it thinks is correct 3989 */ 3990 3991 /* 3992 * If outputs are enabled and the power is going off 3993 * turn off outputs first. 3994 */ 3995 3996 /* power setup -- if necessary */ 3997 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 3998 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 3999 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4000 pcic_putb(pcic, socket->socket, 4001 PCIC_POWER_CONTROL, orig_pwrctl); 4002 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4003 } 4004 4005 if (pcic->pc_flags & PCF_CBPWRCTL) { 4006 value = pcic_cbus_powerctl(pcic, socket->socket); 4007 powerlevel = 0; 4008 } else 4009 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4010 4011 if (value != SUCCESS) { 4012 mutex_exit(&pcic->pc_lock); 4013 return (value); 4014 } 4015 4016 /* 4017 * If outputs were disabled and the power is going on 4018 * turn on outputs afterwards. 4019 */ 4020 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4021 orig_pwrctl = pcic_getb(pcic, socket->socket, 4022 PCIC_POWER_CONTROL); 4023 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4024 pcic_putb(pcic, socket->socket, 4025 PCIC_POWER_CONTROL, orig_pwrctl); 4026 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4027 } 4028 4029 /* 4030 * Once we have done the power stuff can re-enable management 4031 * interrupts. 4032 */ 4033 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4034 4035 #if defined(PCIC_DEBUG) 4036 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4037 "cbctl 0x%x\n", 4038 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4039 pcic_getcb(pcic, CB_CONTROL)); 4040 #endif 4041 4042 /* irq processing */ 4043 if (socket->IFType == IF_IO) { 4044 /* IRQ only for I/O */ 4045 irq = socket->IREQRouting & PCIC_INTR_MASK; 4046 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4047 value &= ~PCIC_INTR_MASK; 4048 4049 /* to enable I/O operation */ 4050 value |= PCIC_IO_CARD | PCIC_RESET; 4051 sockp->pcs_flags |= PCS_CARD_IO; 4052 if (irq != sockp->pcs_irq) { 4053 if (sockp->pcs_irq != 0) 4054 cmn_err(CE_CONT, 4055 "SetSocket: IRQ mismatch %x != %x!\n", 4056 irq, sockp->pcs_irq); 4057 else 4058 sockp->pcs_irq = irq; 4059 } 4060 irq = sockp->pcs_irq; 4061 4062 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4063 if (socket->IREQRouting & IRQ_ENABLE) { 4064 pcic_enable_io_intr(pcic, socket->socket, irq); 4065 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4066 } else { 4067 pcic_disable_io_intr(pcic, socket->socket); 4068 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4069 } 4070 #if defined(PCIC_DEBUG) 4071 if (pcic_debug) { 4072 cmn_err(CE_CONT, 4073 "\tsocket type is I/O and irq %x is %s\n", irq, 4074 (socket->IREQRouting & IRQ_ENABLE) ? 4075 "enabled" : "not enabled"); 4076 xxdmp_all_regs(pcic, socket->socket, 20); 4077 } 4078 #endif 4079 } else { 4080 /* make sure I/O mode is off */ 4081 4082 sockp->pcs_irq = 0; 4083 4084 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4085 value &= ~PCIC_IO_CARD; 4086 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4087 pcic_disable_io_intr(pcic, socket->socket); 4088 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4089 } 4090 4091 sockp->pcs_state &= ~socket->State; 4092 4093 mutex_exit(&pcic->pc_lock); 4094 return (SUCCESS); 4095 } 4096 4097 /* 4098 * pcic_inquire_socket() 4099 * SocketServices InquireSocket function 4100 * returns basic characteristics of the socket 4101 */ 4102 /*ARGSUSED*/ 4103 static int 4104 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4105 { 4106 anp_t *anp = ddi_get_driver_private(dip); 4107 pcicdev_t *pcic = anp->an_private; 4108 int value; 4109 4110 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4111 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4112 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4113 value = pcic->pc_sockets[socket->socket].pcs_flags; 4114 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4115 socket->ActiveHigh = 0; 4116 /* these are the usable IRQs */ 4117 socket->ActiveLow = 0xfff0; 4118 return (SUCCESS); 4119 } 4120 4121 /* 4122 * pcic_inquire_window() 4123 * SocketServices InquireWindow function 4124 * returns detailed characteristics of the window 4125 * this is where windows get tied to sockets 4126 */ 4127 /*ARGSUSED*/ 4128 static int 4129 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4130 { 4131 int type, socket; 4132 4133 type = window->window % PCIC_NUMWINSOCK; 4134 socket = window->window / PCIC_NUMWINSOCK; 4135 4136 #if defined(PCIC_DEBUG) 4137 if (pcic_debug >= 8) 4138 cmn_err(CE_CONT, 4139 "pcic_inquire_window: window = %d/%d socket=%d\n", 4140 window->window, type, socket); 4141 #endif 4142 if (type < PCIC_IOWINDOWS) { 4143 window->WndCaps = WC_IO|WC_WAIT; 4144 type = IF_IO; 4145 } else { 4146 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4147 type = IF_MEMORY; 4148 } 4149 4150 /* initialize the socket map - one socket per window */ 4151 PR_ZERO(window->Sockets); 4152 PR_SET(window->Sockets, socket); 4153 4154 if (type == IF_IO) { 4155 iowin_char_t *io; 4156 io = &window->iowin_char; 4157 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4158 WC_16BIT; 4159 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4160 io->LastByte = (baseaddr_t)IOMEM_LAST; 4161 io->MinSize = IOMEM_MIN; 4162 io->MaxSize = IOMEM_MAX; 4163 io->ReqGran = IOMEM_GRAN; 4164 io->AddrLines = IOMEM_DECODE; 4165 io->EISASlot = 0; 4166 } else { 4167 mem_win_char_t *mem; 4168 mem = &window->mem_win_char; 4169 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4170 WC_16BIT|WC_WP; 4171 4172 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4173 mem->LastByte = (baseaddr_t)MEM_LAST; 4174 4175 mem->MinSize = MEM_MIN; 4176 mem->MaxSize = MEM_MAX; 4177 mem->ReqGran = PCIC_PAGE; 4178 mem->ReqBase = 0; 4179 mem->ReqOffset = PCIC_PAGE; 4180 mem->Slowest = MEM_SPEED_MAX; 4181 mem->Fastest = MEM_SPEED_MIN; 4182 } 4183 return (SUCCESS); 4184 } 4185 4186 /* 4187 * pcic_get_adapter() 4188 * SocketServices GetAdapter function 4189 * this is nearly a no-op. 4190 */ 4191 /*ARGSUSED*/ 4192 static int 4193 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4194 { 4195 anp_t *anp = ddi_get_driver_private(dip); 4196 pcicdev_t *pcic = anp->an_private; 4197 4198 if (pcic->pc_flags & PCF_INTRENAB) 4199 adapt->SCRouting = IRQ_ENABLE; 4200 adapt->state = 0; 4201 return (SUCCESS); 4202 } 4203 4204 /* 4205 * pcic_get_page() 4206 * SocketServices GetPage function 4207 * returns info about the window 4208 */ 4209 /*ARGSUSED*/ 4210 static int 4211 pcic_get_page(dev_info_t *dip, get_page_t *page) 4212 { 4213 anp_t *anp = ddi_get_driver_private(dip); 4214 pcicdev_t *pcic = anp->an_private; 4215 int socket, window; 4216 pcs_memwin_t *winp; 4217 4218 socket = page->window / PCIC_NUMWINSOCK; 4219 window = page->window % PCIC_NUMWINSOCK; 4220 4221 /* I/O windows are the first two */ 4222 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4223 return (BAD_WINDOW); 4224 } 4225 4226 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4227 4228 if (page->page != 0) 4229 return (BAD_PAGE); 4230 4231 page->state = 0; 4232 if (winp->pcw_status & PCW_ENABLED) 4233 page->state |= PS_ENABLED; 4234 if (winp->pcw_status & PCW_ATTRIBUTE) 4235 page->state |= PS_ATTRIBUTE; 4236 if (winp->pcw_status & PCW_WP) 4237 page->state |= PS_WP; 4238 4239 page->offset = (off_t)winp->pcw_offset; 4240 4241 return (SUCCESS); 4242 } 4243 4244 /* 4245 * pcic_get_socket() 4246 * SocketServices GetSocket 4247 * returns information about the current socket setting 4248 */ 4249 /*ARGSUSED*/ 4250 static int 4251 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4252 { 4253 anp_t *anp = ddi_get_driver_private(dip); 4254 pcicdev_t *pcic = anp->an_private; 4255 int socknum, irq_enabled; 4256 pcic_socket_t *sockp; 4257 4258 socknum = socket->socket; 4259 sockp = &pcic->pc_sockets[socknum]; 4260 4261 socket->SCIntMask = sockp->pcs_intmask; 4262 sockp->pcs_state = pcic_card_state(pcic, sockp); 4263 4264 socket->state = sockp->pcs_state; 4265 if (socket->state & SBM_CD) { 4266 socket->VccLevel = sockp->pcs_vcc; 4267 socket->Vpp1Level = sockp->pcs_vpp1; 4268 socket->Vpp2Level = sockp->pcs_vpp2; 4269 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4270 IRQ_ENABLE : 0; 4271 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4272 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4273 IF_IO : IF_MEMORY; 4274 } else { 4275 socket->VccLevel = 0; 4276 socket->Vpp1Level = 0; 4277 socket->Vpp2Level = 0; 4278 socket->IRQRouting = 0; 4279 socket->IFType = IF_MEMORY; 4280 } 4281 socket->CtlInd = 0; /* no indicators */ 4282 4283 return (SUCCESS); 4284 } 4285 4286 /* 4287 * pcic_get_status() 4288 * SocketServices GetStatus 4289 * returns status information about the PC Card in 4290 * the selected socket 4291 */ 4292 /*ARGSUSED*/ 4293 static int 4294 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4295 { 4296 anp_t *anp = ddi_get_driver_private(dip); 4297 pcicdev_t *pcic = anp->an_private; 4298 int socknum, irq_enabled; 4299 pcic_socket_t *sockp; 4300 4301 socknum = status->socket; 4302 sockp = &pcic->pc_sockets[socknum]; 4303 4304 status->CardState = pcic_card_state(pcic, sockp); 4305 status->SocketState = sockp->pcs_state; 4306 status->CtlInd = 0; /* no indicators */ 4307 4308 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4309 status->SocketState |= SBM_CD; 4310 if (status->CardState & SBM_CD) { 4311 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4312 IRQ_ENABLE : 0; 4313 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4314 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4315 IF_IO : IF_MEMORY; 4316 } else { 4317 status->IRQRouting = 0; 4318 status->IFType = IF_MEMORY; 4319 } 4320 4321 #if defined(PCIC_DEBUG) 4322 if (pcic_debug >= 8) 4323 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4324 "SocketState=%x\n", 4325 socknum, status->CardState, status->SocketState); 4326 #endif 4327 switch (pcic->pc_type) { 4328 uint32_t present_state; 4329 case PCIC_TI_PCI1410: 4330 case PCIC_TI_PCI1520: 4331 case PCIC_TI_PCI1420: 4332 case PCIC_ENE_1420: 4333 case PCIC_TOSHIBA_TOPIC100: 4334 case PCIC_TOSHIBA_TOPIC95: 4335 case PCIC_TOSHIBA_VENDOR: 4336 case PCIC_O2MICRO_VENDOR: 4337 case PCIC_TI_VENDOR: 4338 case PCIC_RICOH_VENDOR: 4339 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4340 if (present_state & PCIC_CB_CARD) 4341 status->IFType = IF_CARDBUS; 4342 #if defined(PCIC_DEBUG) 4343 if (pcic_debug >= 8) 4344 cmn_err(CE_CONT, "pcic_get_status: present_state=0x%x\n", 4345 present_state); 4346 #endif 4347 break; 4348 default: 4349 break; 4350 } 4351 4352 return (SUCCESS); 4353 } 4354 4355 /* 4356 * pcic_get_window() 4357 * SocketServices GetWindow function 4358 * returns state information about the specified window 4359 */ 4360 /*ARGSUSED*/ 4361 static int 4362 pcic_get_window(dev_info_t *dip, get_window_t *window) 4363 { 4364 anp_t *anp = ddi_get_driver_private(dip); 4365 pcicdev_t *pcic = anp->an_private; 4366 int socket, win; 4367 pcic_socket_t *sockp; 4368 pcs_memwin_t *winp; 4369 4370 socket = window->window / PCIC_NUMWINSOCK; 4371 win = window->window % PCIC_NUMWINSOCK; 4372 #if defined(PCIC_DEBUG) 4373 if (pcic_debug) { 4374 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4375 socket, win); 4376 } 4377 #endif 4378 4379 if (socket > pcic->pc_numsockets) 4380 return (BAD_WINDOW); 4381 4382 sockp = &pcic->pc_sockets[socket]; 4383 winp = &sockp->pcs_windows[win].mem; 4384 4385 window->socket = socket; 4386 window->size = winp->pcw_len; 4387 window->speed = winp->pcw_speed; 4388 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4389 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4390 4391 if (win >= PCIC_IOWINDOWS) { 4392 window->state = 0; 4393 } else { 4394 window->state = WS_IO; 4395 } 4396 if (winp->pcw_status & PCW_ENABLED) 4397 window->state |= WS_ENABLED; 4398 4399 if (winp->pcw_status & PCS_CARD_16BIT) 4400 window->state |= WS_16BIT; 4401 #if defined(PCIC_DEBUG) 4402 if (pcic_debug) 4403 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4404 window->size, (unsigned)window->speed, 4405 (void *)window->handle, window->state); 4406 #endif 4407 4408 return (SUCCESS); 4409 } 4410 4411 /* 4412 * pcic_ll_reset 4413 * low level reset 4414 * separated out so it can be called when already locked 4415 * 4416 * There are two variables that control the RESET timing: 4417 * pcic_prereset_time - time in mS before asserting RESET 4418 * pcic_reset_time - time in mS to assert RESET 4419 * 4420 */ 4421 int pcic_prereset_time = 1; 4422 int pcic_reset_time = 10; 4423 int pcic_postreset_time = 20; 4424 int pcic_vpp_is_vcc_during_reset = 0; 4425 4426 static int 4427 pcic_ll_reset(pcicdev_t *pcic, int socket) 4428 { 4429 int windowbits, iobits; 4430 uint32_t pwr; 4431 4432 /* save windows that were on */ 4433 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4434 if (pcic_reset_time == 0) 4435 return (windowbits); 4436 /* turn all windows off */ 4437 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4438 4439 #if defined(PCIC_DEBUG) 4440 pcic_err(pcic->dip, 6, 4441 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4442 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4443 pcic_getcb(pcic, CB_CONTROL), 4444 pcic_getcb(pcic, CB_PRESENT_STATE)); 4445 #endif 4446 4447 if (pcic_vpp_is_vcc_during_reset) { 4448 4449 /* 4450 * Set VPP to VCC for the duration of the reset - for aironet 4451 * card. 4452 */ 4453 if (pcic->pc_flags & PCF_CBPWRCTL) { 4454 pwr = pcic_getcb(pcic, CB_CONTROL); 4455 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4456 (void) pcic_getcb(pcic, CB_CONTROL); 4457 } else { 4458 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4459 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4460 pwr | 1); 4461 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4462 } 4463 } 4464 4465 if (pcic_prereset_time > 0) { 4466 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4467 pcic_prereset_time); 4468 pcic_mswait(pcic, socket, pcic_prereset_time); 4469 } 4470 4471 /* turn interrupts off and start a reset */ 4472 pcic_err(pcic->dip, 8, 4473 "pcic_ll_reset turn interrupts off and start a reset\n"); 4474 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4475 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4476 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4477 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4478 4479 switch (pcic->pc_type) { 4480 case PCIC_INTEL_i82092: 4481 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4482 PCIC_82092_INT_DISABLE); 4483 break; 4484 default: 4485 break; 4486 } /* switch */ 4487 4488 pcic->pc_sockets[socket].pcs_state = 0; 4489 4490 if (pcic_reset_time > 0) { 4491 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4492 pcic_reset_time); 4493 pcic_mswait(pcic, socket, pcic_reset_time); 4494 } 4495 4496 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4497 4498 /* take it out of RESET now */ 4499 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4500 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4501 4502 /* 4503 * can't access the card for 20ms, but we really don't 4504 * want to sit around that long. The pcic is still usable. 4505 * memory accesses must wait for RDY to come up. 4506 */ 4507 if (pcic_postreset_time > 0) { 4508 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4509 pcic_postreset_time); 4510 pcic_mswait(pcic, socket, pcic_postreset_time); 4511 } 4512 4513 if (pcic_vpp_is_vcc_during_reset > 1) { 4514 4515 /* 4516 * Return VPP power to whatever it was before. 4517 */ 4518 if (pcic->pc_flags & PCF_CBPWRCTL) { 4519 pcic_putcb(pcic, CB_CONTROL, pwr); 4520 (void) pcic_getcb(pcic, CB_CONTROL); 4521 } else { 4522 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4523 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4524 } 4525 } 4526 4527 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4528 4529 return (windowbits); 4530 } 4531 4532 /* 4533 * pcic_reset_socket() 4534 * SocketServices ResetSocket function 4535 * puts the PC Card in the socket into the RESET state 4536 * and then takes it out after the the cycle time 4537 * The socket is back to initial state when done 4538 */ 4539 static int 4540 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4541 { 4542 anp_t *anp = ddi_get_driver_private(dip); 4543 pcicdev_t *pcic = anp->an_private; 4544 int value; 4545 int i, mint; 4546 pcic_socket_t *sockp; 4547 4548 #if defined(PCIC_DEBUG) 4549 if (pcic_debug >= 8) 4550 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4551 (void *)dip, socket, mode, 4552 mode == RESET_MODE_FULL ? "full" : "partial"); 4553 #endif 4554 4555 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4556 4557 /* Turn off management interupts. */ 4558 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4559 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4560 4561 sockp = &pcic->pc_sockets[socket]; 4562 4563 value = pcic_ll_reset(pcic, socket); 4564 if (mode == RESET_MODE_FULL) { 4565 /* disable and unmap all mapped windows */ 4566 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4567 if (i < PCIC_IOWINDOWS) { 4568 if (sockp->pcs_windows[i].io.pcw_status & 4569 PCW_MAPPED) { 4570 pcs_iowin_t *io; 4571 io = &sockp->pcs_windows[i].io; 4572 io->pcw_status &= ~PCW_ENABLED; 4573 } 4574 } else { 4575 if (sockp->pcs_windows[i].mem.pcw_status & 4576 PCW_MAPPED) { 4577 pcs_memwin_t *mem; 4578 mem = &sockp->pcs_windows[i].mem; 4579 mem->pcw_status &= ~PCW_ENABLED; 4580 } 4581 } 4582 } 4583 } else { 4584 /* turn windows back on */ 4585 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4586 /* wait the rest of the time here */ 4587 pcic_mswait(pcic, socket, 10); 4588 } 4589 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4590 mutex_exit(&pcic->pc_lock); 4591 return (SUCCESS); 4592 } 4593 4594 /* 4595 * pcic_set_interrupt() 4596 * SocketServices SetInterrupt function 4597 */ 4598 static int 4599 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4600 { 4601 anp_t *anp = ddi_get_driver_private(dip); 4602 pcicdev_t *pcic = anp->an_private; 4603 int value = DDI_SUCCESS; 4604 inthandler_t *intr; 4605 4606 #if defined(PCIC_DEBUG) 4607 if (pcic_debug) { 4608 cmn_err(CE_CONT, 4609 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4610 pcic->pc_intr_mode); 4611 cmn_err(CE_CONT, 4612 "\t irq_top=%p handler=%p handler_id=%x\n", 4613 (void *)pcic->irq_top, (void *)handler->handler, 4614 handler->handler_id); 4615 } 4616 #endif 4617 4618 /* 4619 * If we're on a PCI bus, we route all IO IRQs through a single 4620 * PCI interrupt (typically INT A#) so we don't have to do 4621 * much other than add the caller to general interrupt handler 4622 * and set some state. 4623 */ 4624 4625 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4626 if (intr == NULL) 4627 return (NO_RESOURCE); 4628 4629 switch (pcic->pc_intr_mode) { 4630 case PCIC_INTR_MODE_PCI_1: 4631 /* 4632 * We only allow above-lock-level IO IRQ handlers 4633 * in the PCI bus case. 4634 */ 4635 4636 mutex_enter(&pcic->intr_lock); 4637 4638 if (pcic->irq_top == NULL) { 4639 pcic->irq_top = intr; 4640 pcic->irq_current = pcic->irq_top; 4641 } else { 4642 while (pcic->irq_current->next != NULL) 4643 pcic->irq_current = pcic->irq_current->next; 4644 pcic->irq_current->next = intr; 4645 pcic->irq_current = pcic->irq_current->next; 4646 } 4647 4648 pcic->irq_current->intr = 4649 (ddi_intr_handler_t *)handler->handler; 4650 pcic->irq_current->handler_id = handler->handler_id; 4651 pcic->irq_current->arg1 = handler->arg1; 4652 pcic->irq_current->arg2 = handler->arg2; 4653 pcic->irq_current->socket = handler->socket; 4654 4655 mutex_exit(&pcic->intr_lock); 4656 4657 handler->iblk_cookie = &pcic->pc_pri; 4658 handler->idev_cookie = &pcic->pc_dcookie; 4659 break; 4660 4661 default: 4662 intr->intr = (ddi_intr_handler_t *)handler->handler; 4663 intr->handler_id = handler->handler_id; 4664 intr->arg1 = handler->arg1; 4665 intr->arg2 = handler->arg2; 4666 intr->socket = handler->socket; 4667 intr->irq = handler->irq; 4668 4669 /* 4670 * need to revisit this to see if interrupts can be 4671 * shared someday. Note that IRQ is set in the common 4672 * code. 4673 */ 4674 mutex_enter(&pcic->pc_lock); 4675 if (pcic->pc_handlers == NULL) { 4676 pcic->pc_handlers = intr; 4677 intr->next = intr->prev = intr; 4678 } else { 4679 insque(intr, pcic->pc_handlers); 4680 } 4681 mutex_exit(&pcic->pc_lock); 4682 4683 break; 4684 } 4685 4686 /* 4687 * need to fill in cookies in event of multiple high priority 4688 * interrupt handlers on same IRQ 4689 */ 4690 4691 #if defined(PCIC_DEBUG) 4692 if (pcic_debug) { 4693 cmn_err(CE_CONT, 4694 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4695 (void *)pcic->irq_top, value); 4696 } 4697 #endif 4698 4699 if (value == DDI_SUCCESS) { 4700 return (SUCCESS); 4701 } else { 4702 return (BAD_IRQ); 4703 } 4704 } 4705 4706 /* 4707 * pcic_clear_interrupt() 4708 * SocketServices ClearInterrupt function 4709 * 4710 * Interrupts for PCIC are complicated by the fact that we must 4711 * follow several different models for interrupts. 4712 * ISA: there is an interrupt per adapter and per socket and 4713 * they can't be shared. 4714 * PCI: some adapters have one PCI interrupt available while others 4715 * have up to 4. Solaris may or may not allow us to use more 4716 * than 1 so we essentially share them all at this point. 4717 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4718 * This is like ISA but we have to fudge and create an intrspec 4719 * that PCI's parent understands and bypass the PCI nexus. 4720 * multifunction: this requires sharing the interrupts on a per-socket 4721 * basis. 4722 */ 4723 static int 4724 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4725 { 4726 anp_t *anp = ddi_get_driver_private(dip); 4727 pcicdev_t *pcic = anp->an_private; 4728 inthandler_t *intr, *prev, *current; 4729 int i; 4730 4731 /* 4732 * If we're on a PCI bus, we route all IO IRQs through a single 4733 * PCI interrupt (typically INT A#) so we don't have to do 4734 * much other than remove the caller from the general 4735 * interrupt handler callout list. 4736 */ 4737 4738 #if defined(PCIC_DEBUG) 4739 if (pcic_debug) { 4740 cmn_err(CE_CONT, 4741 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4742 pcic->pc_intr_mode); 4743 cmn_err(CE_CONT, 4744 "\t irq_top=%p handler=%p handler_id=%x\n", 4745 (void *)pcic->irq_top, (void *)handler->handler, 4746 handler->handler_id); 4747 } 4748 #endif 4749 4750 switch (pcic->pc_intr_mode) { 4751 case PCIC_INTR_MODE_PCI_1: 4752 4753 mutex_enter(&pcic->intr_lock); 4754 if (pcic->irq_top == NULL) { 4755 mutex_exit(&pcic->intr_lock); 4756 return (BAD_IRQ); 4757 } 4758 4759 intr = NULL; 4760 pcic->irq_current = pcic->irq_top; 4761 4762 while ((pcic->irq_current != NULL) && 4763 (pcic->irq_current->handler_id != 4764 handler->handler_id)) { 4765 intr = pcic->irq_current; 4766 pcic->irq_current = pcic->irq_current->next; 4767 } 4768 4769 if (pcic->irq_current == NULL) { 4770 mutex_exit(&pcic->intr_lock); 4771 return (BAD_IRQ); 4772 } 4773 4774 if (intr != NULL) { 4775 intr->next = pcic->irq_current->next; 4776 } else { 4777 pcic->irq_top = pcic->irq_current->next; 4778 } 4779 4780 current = pcic->irq_current; 4781 pcic->irq_current = pcic->irq_top; 4782 mutex_exit(&pcic->intr_lock); 4783 kmem_free(current, sizeof (inthandler_t)); 4784 4785 break; 4786 4787 default: 4788 4789 mutex_enter(&pcic->pc_lock); 4790 intr = pcic_handlers; 4791 prev = (inthandler_t *)&pcic_handlers; 4792 4793 while (intr != NULL) { 4794 if (intr->handler_id == handler->handler_id) { 4795 i = intr->irq & PCIC_INTR_MASK; 4796 if (--pcic_irq_map[i].count == 0) { 4797 /* multi-handler form */ 4798 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4799 (void) ddi_intr_remove_handler( 4800 pcic->pc_intr_htblp[i]); 4801 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4802 (void) pcmcia_return_intr(pcic->dip, i); 4803 #if defined(PCIC_DEBUG) 4804 if (pcic_debug) { 4805 cmn_err(CE_CONT, 4806 "removing interrupt %d at %s " 4807 "priority\n", i, "high"); 4808 cmn_err(CE_CONT, 4809 "ddi_remove_intr(%p, %x, %p)\n", 4810 (void *)dip, 4811 0, 4812 (void *)intr->iblk_cookie); 4813 } 4814 #endif 4815 } 4816 prev->next = intr->next; 4817 kmem_free(intr, sizeof (inthandler_t)); 4818 intr = prev->next; 4819 } else { 4820 prev = intr; 4821 intr = intr->next; 4822 } /* if (handler_id) */ 4823 } /* while */ 4824 4825 mutex_exit(&pcic->pc_lock); 4826 } 4827 4828 #if defined(PCIC_DEBUG) 4829 if (pcic_debug) { 4830 cmn_err(CE_CONT, 4831 "pcic_clear_interrupt: exit irq_top=%p\n", 4832 (void *)pcic->irq_top); 4833 } 4834 #endif 4835 4836 4837 return (SUCCESS); 4838 } 4839 4840 struct intel_regs { 4841 char *name; 4842 int off; 4843 char *fmt; 4844 } iregs[] = { 4845 {"ident ", 0}, 4846 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4847 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4848 "\7DRD\10OE"}, 4849 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4850 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4851 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4852 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4853 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4854 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4855 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4856 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4857 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4858 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4859 {"io0-slow ", 8}, 4860 {"io0-shi ", 9}, 4861 {"io0-elow ", 0xa}, 4862 {"io0-ehi ", 0xb}, 4863 {"io1-slow ", 0xc}, 4864 {"io1-shi ", 0xd}, 4865 {"io1-elow ", 0xe}, 4866 {"io1-ehi ", 0xf}, 4867 {"mem0-slow ", 0x10}, 4868 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4869 {"mem0-elow ", 0x12}, 4870 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4871 {"card0-low ", 0x14}, 4872 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4873 {"mem1-slow ", 0x18}, 4874 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4875 {"mem1-elow ", 0x1a}, 4876 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4877 {"card1-low ", 0x1c}, 4878 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4879 {"mem2-slow ", 0x20}, 4880 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4881 {"mem2-elow ", 0x22}, 4882 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4883 {"card2-low ", 0x24}, 4884 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4885 {"mem3-slow ", 0x28}, 4886 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4887 {"mem3-elow ", 0x2a}, 4888 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4889 {"card3-low ", 0x2c}, 4890 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4891 4892 {"mem4-slow ", 0x30}, 4893 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4894 {"mem4-elow ", 0x32}, 4895 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4896 {"card4-low ", 0x34}, 4897 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4898 {"mpage0 ", 0x40}, 4899 {"mpage1 ", 0x41}, 4900 {"mpage2 ", 0x42}, 4901 {"mpage3 ", 0x43}, 4902 {"mpage4 ", 0x44}, 4903 {NULL}, 4904 }; 4905 4906 static struct intel_regs cregs[] = { 4907 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 4908 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 4909 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 4910 {"chip-info ", 0x1f, "\20\6DUAL"}, 4911 {"IO-offlow0", 0x36}, 4912 {"IO-offhi0 ", 0x37}, 4913 {"IO-offlow1", 0x38}, 4914 {"IO-offhi1 ", 0x39}, 4915 NULL, 4916 }; 4917 4918 static struct intel_regs cxregs[] = { 4919 {"ext-ctl-1 ", 0x03, 4920 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 4921 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 4922 {"mem0-up ", 0x05}, 4923 {"mem1-up ", 0x06}, 4924 {"mem2-up ", 0x07}, 4925 {"mem3-up ", 0x08}, 4926 {"mem4-up ", 0x09}, 4927 {NULL} 4928 }; 4929 4930 void 4931 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 4932 { 4933 int i, value, j; 4934 char buff[256]; 4935 char *fmt; 4936 4937 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 4938 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 4939 int sval; 4940 if (cregs[i].off == PCIC_MISC_CTL_2) 4941 sval = 0; 4942 else 4943 sval = socket; 4944 value = pcic_getb(pcic, sval, cregs[i].off); 4945 if (i & 1) { 4946 if (cregs[i].fmt) 4947 fmt = "%s\t%s\t%b\n"; 4948 else 4949 fmt = "%s\t%s\t%x\n"; 4950 cmn_err(CE_CONT, fmt, buff, 4951 cregs[i].name, value, cregs[i].fmt); 4952 buff[0] = '\0'; 4953 } else { 4954 if (cregs[i].fmt) 4955 fmt = "\t%s\t%b"; 4956 else 4957 fmt = "\t%s\t%x"; 4958 (void) sprintf(buff, fmt, 4959 cregs[i].name, value, cregs[i].fmt); 4960 for (j = strlen(buff); j < 40; j++) 4961 buff[j] = ' '; 4962 buff[40] = '\0'; 4963 } 4964 } 4965 cmn_err(CE_CONT, "%s\n", buff); 4966 4967 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 4968 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 4969 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 4970 4971 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 4972 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 4973 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 4974 4975 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 4976 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 4977 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 4978 4979 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 4980 4981 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 4982 value = clext_reg_read(pcic, socket, cxregs[i].off); 4983 if (i & 1) { 4984 if (cxregs[i].fmt) 4985 fmt = "%s\t%s\t%b\n"; 4986 else 4987 fmt = "%s\t%s\t%x\n"; 4988 cmn_err(CE_CONT, fmt, buff, 4989 cxregs[i].name, value, cxregs[i].fmt); 4990 buff[0] = '\0'; 4991 } else { 4992 if (cxregs[i].fmt) 4993 fmt = "\t%s\t%b"; 4994 else 4995 fmt = "\t%s\t%x"; 4996 (void) sprintf(buff, fmt, 4997 cxregs[i].name, value, cxregs[i].fmt); 4998 for (j = strlen(buff); j < 40; j++) 4999 buff[j] = ' '; 5000 buff[40] = '\0'; 5001 } 5002 } 5003 } 5004 5005 #if defined(PCIC_DEBUG) 5006 static void 5007 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5008 { 5009 int i, value, j; 5010 char buff[256]; 5011 char *fmt; 5012 5013 #if defined(PCIC_DEBUG) 5014 if (pcic_debug < 2) 5015 return; 5016 #endif 5017 cmn_err(CE_CONT, 5018 "----------- PCIC Registers for socket %d---------\n", 5019 socket); 5020 cmn_err(CE_CONT, 5021 "\tname value name value\n"); 5022 5023 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5024 value = pcic_getb(pcic, socket, iregs[i].off); 5025 if (i & 1) { 5026 if (iregs[i].fmt) 5027 fmt = "%s\t%s\t%b\n"; 5028 else 5029 fmt = "%s\t%s\t%x\n"; 5030 cmn_err(CE_CONT, fmt, buff, 5031 iregs[i].name, value, iregs[i].fmt); 5032 buff[0] = '\0'; 5033 } else { 5034 if (iregs[i].fmt) 5035 fmt = "\t%s\t%b"; 5036 else 5037 fmt = "\t%s\t%x"; 5038 (void) sprintf(buff, fmt, 5039 iregs[i].name, value, iregs[i].fmt); 5040 for (j = strlen(buff); j < 40; j++) 5041 buff[j] = ' '; 5042 buff[40] = '\0'; 5043 } 5044 } 5045 switch (pcic->pc_type) { 5046 case PCIC_CL_PD6710: 5047 case PCIC_CL_PD6722: 5048 case PCIC_CL_PD6729: 5049 case PCIC_CL_PD6832: 5050 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5051 break; 5052 } 5053 cmn_err(CE_CONT, "%s\n", buff); 5054 } 5055 #endif 5056 5057 /* 5058 * pcic_mswait(ms) 5059 * sleep ms milliseconds 5060 * call drv_usecwait once for each ms 5061 */ 5062 static void 5063 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5064 { 5065 if (ms) { 5066 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5067 pcic_mutex_exit(&pcic->pc_lock); 5068 delay(drv_usectohz(ms*1000)); 5069 pcic_mutex_enter(&pcic->pc_lock); 5070 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5071 } 5072 } 5073 5074 /* 5075 * pcic_check_ready(pcic, index, off) 5076 * Wait for card to come ready 5077 * We only wait if the card is NOT in RESET 5078 * and power is on. 5079 */ 5080 static boolean_t 5081 pcic_check_ready(pcicdev_t *pcic, int socket) 5082 { 5083 int ifstate, intstate; 5084 5085 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5086 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5087 5088 if ((intstate & PCIC_RESET) && 5089 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5090 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5091 return (B_TRUE); 5092 5093 #ifdef PCIC_DEBUG 5094 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5095 "ifstate = 0x%x\n", intstate, ifstate); 5096 if (pcic_debug) { 5097 pcic_debug += 4; 5098 xxdmp_all_regs(pcic, socket, -1); 5099 pcic_debug -= 4; 5100 } 5101 #endif 5102 return (B_FALSE); 5103 } 5104 5105 /* 5106 * Cirrus Logic extended register read/write routines 5107 */ 5108 static int 5109 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5110 { 5111 int val; 5112 5113 switch (pcic->pc_io_type) { 5114 case PCIC_IO_TYPE_YENTA: 5115 val = ddi_get8(pcic->handle, 5116 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5117 break; 5118 default: 5119 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5120 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5121 break; 5122 } 5123 5124 return (val); 5125 } 5126 5127 static void 5128 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5129 { 5130 switch (pcic->pc_io_type) { 5131 case PCIC_IO_TYPE_YENTA: 5132 ddi_put8(pcic->handle, 5133 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5134 break; 5135 default: 5136 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5137 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5138 break; 5139 } 5140 } 5141 5142 /* 5143 * Misc PCI functions 5144 */ 5145 static void 5146 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5147 { 5148 unsigned cmd; 5149 5150 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5151 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5152 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5153 (PCI_COMM_IO|PCI_COMM_MAE)) 5154 return; 5155 5156 if (flags & PCIC_ENABLE_IO) 5157 cmd |= PCI_COMM_IO; 5158 5159 if (flags & PCIC_ENABLE_MEM) 5160 cmd |= PCI_COMM_MAE; 5161 5162 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5163 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5164 } 5165 5166 /* 5167 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5168 */ 5169 static int 5170 pcic_find_pci_type(pcicdev_t *pcic) 5171 { 5172 uint32_t vend, device; 5173 5174 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5175 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5176 "vendor-id", -1); 5177 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5178 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5179 "device-id", -1); 5180 5181 device = PCI_ID(vend, device); 5182 pcic->pc_type = device; 5183 pcic->pc_chipname = "PCI:unknown"; 5184 5185 switch (device) { 5186 case PCIC_INTEL_i82092: 5187 pcic->pc_chipname = PCIC_TYPE_i82092; 5188 break; 5189 case PCIC_CL_PD6729: 5190 pcic->pc_chipname = PCIC_TYPE_PD6729; 5191 /* 5192 * Some 6730's incorrectly identify themselves 5193 * as a 6729, so we need to do some more tests 5194 * here to see if the device that's claiming 5195 * to be a 6729 is really a 6730. 5196 */ 5197 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5198 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5199 0) { 5200 pcic->pc_chipname = PCIC_TYPE_PD6730; 5201 pcic->pc_type = PCIC_CL_PD6730; 5202 } 5203 break; 5204 case PCIC_CL_PD6730: 5205 pcic->pc_chipname = PCIC_TYPE_PD6730; 5206 break; 5207 case PCIC_CL_PD6832: 5208 pcic->pc_chipname = PCIC_TYPE_PD6832; 5209 break; 5210 case PCIC_SMC_34C90: 5211 pcic->pc_chipname = PCIC_TYPE_34C90; 5212 break; 5213 case PCIC_TOSHIBA_TOPIC95: 5214 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5215 break; 5216 case PCIC_TOSHIBA_TOPIC100: 5217 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5218 break; 5219 case PCIC_TI_PCI1031: 5220 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5221 break; 5222 case PCIC_TI_PCI1130: 5223 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5224 break; 5225 case PCIC_TI_PCI1131: 5226 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5227 break; 5228 case PCIC_TI_PCI1250: 5229 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5230 break; 5231 case PCIC_TI_PCI1225: 5232 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5233 break; 5234 case PCIC_TI_PCI1410: 5235 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5236 break; 5237 case PCIC_TI_PCI1510: 5238 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5239 break; 5240 case PCIC_TI_PCI1520: 5241 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5242 break; 5243 case PCIC_TI_PCI1221: 5244 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5245 break; 5246 case PCIC_TI_PCI1050: 5247 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5248 break; 5249 case PCIC_ENE_1410: 5250 pcic->pc_chipname = PCIC_TYPE_1410; 5251 break; 5252 case PCIC_O2_OZ6912: 5253 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5254 break; 5255 case PCIC_RICOH_RL5C466: 5256 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5257 break; 5258 case PCIC_TI_PCI1420: 5259 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5260 break; 5261 case PCIC_ENE_1420: 5262 pcic->pc_chipname = PCIC_TYPE_1420; 5263 break; 5264 default: 5265 switch (PCI_ID(vend, (uint32_t)0)) { 5266 case PCIC_TOSHIBA_VENDOR: 5267 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5268 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5269 break; 5270 case PCIC_TI_VENDOR: 5271 pcic->pc_chipname = PCIC_TYPE_TI; 5272 pcic->pc_type = PCIC_TI_VENDOR; 5273 break; 5274 case PCIC_O2MICRO_VENDOR: 5275 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5276 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5277 break; 5278 case PCIC_RICOH_VENDOR: 5279 pcic->pc_chipname = PCIC_TYPE_RICOH; 5280 pcic->pc_type = PCIC_RICOH_VENDOR; 5281 break; 5282 default: 5283 if (!(pcic->pc_flags & PCF_CARDBUS)) 5284 return (DDI_FAILURE); 5285 pcic->pc_chipname = PCIC_TYPE_YENTA; 5286 break; 5287 } 5288 } 5289 return (DDI_SUCCESS); 5290 } 5291 5292 static void 5293 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5294 { 5295 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5296 pcic->cfgaddr + PCIC_82092_PPIRR); 5297 uchar_t val; 5298 5299 if (intr == PCIC_82092_CTL_SMI) { 5300 val = PCIC_82092_SMI_CTL(socket, 5301 PCIC_82092_INT_DISABLE); 5302 ppirr &= ~val; 5303 val = PCIC_82092_SMI_CTL(socket, state); 5304 ppirr |= val; 5305 } else { 5306 val = PCIC_82092_IRQ_CTL(socket, 5307 PCIC_82092_INT_DISABLE); 5308 ppirr &= ~val; 5309 val = PCIC_82092_IRQ_CTL(socket, state); 5310 ppirr |= val; 5311 } 5312 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5313 ppirr); 5314 } 5315 5316 static uint_t 5317 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5318 { 5319 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5320 uint_t rc = DDI_INTR_UNCLAIMED; 5321 5322 _NOTE(ARGUNUSED(arg2)) 5323 5324 mutex_enter(&sockp->pcs_pcic->pc_lock); 5325 if (sockp->pcs_cd_softint_flg) { 5326 uint8_t status; 5327 sockp->pcs_cd_softint_flg = 0; 5328 rc = DDI_INTR_CLAIMED; 5329 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5330 PCIC_INTERFACE_STATUS); 5331 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5332 } 5333 mutex_exit(&sockp->pcs_pcic->pc_lock); 5334 return (rc); 5335 } 5336 5337 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5338 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5339 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5340 5341 #ifdef CARDBUS 5342 static uint32_t pcic_cbps_on = 0; 5343 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5344 CB_PS_XVCARD | CB_PS_YVCARD; 5345 #else 5346 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5347 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5348 CB_PS_CBCARD | 5349 CB_PS_XVCARD | CB_PS_YVCARD; 5350 #endif 5351 static void 5352 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5353 { 5354 boolean_t do_debounce = B_FALSE; 5355 int debounce_time = drv_usectohz(pcic_debounce_time); 5356 uint8_t irq; 5357 timeout_id_t debounce; 5358 5359 /* 5360 * Always reset debounce but may need to check original state later. 5361 */ 5362 debounce = sockp->pcs_debounce_id; 5363 sockp->pcs_debounce_id = 0; 5364 5365 /* 5366 * Check to see whether a card is present or not. There are 5367 * only two states that we are concerned with - the state 5368 * where both CD pins are asserted, which means that the 5369 * card is fully seated, and the state where neither CD 5370 * pin is asserted, which means that the card is not 5371 * present. 5372 * The CD signals are generally very noisy and cause a lot of 5373 * contact bounce as the card is being inserted and 5374 * removed, so we need to do some software debouncing. 5375 */ 5376 5377 #ifdef PCIC_DEBUG 5378 pcic_err(pcic->dip, 6, 5379 "pcic%d handle_cd_change: socket %d card status 0x%x" 5380 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5381 sockp->pcs_socket, status, debounce); 5382 #endif 5383 switch (status & PCIC_ISTAT_CD_MASK) { 5384 case PCIC_CD_PRESENT_OK: 5385 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5386 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5387 uint32_t cbps; 5388 #ifdef PCIC_DEBUG 5389 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5390 #endif 5391 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5392 #ifdef PCIC_DEBUG 5393 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5394 #endif 5395 /* 5396 * Check the CB bits are sane. 5397 */ 5398 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5399 cbps & pcic_cbps_off) { 5400 cmn_err(CE_WARN, 5401 "%s%d: Odd Cardbus Present State 0x%x\n", 5402 ddi_get_name(pcic->dip), 5403 ddi_get_instance(pcic->dip), 5404 cbps); 5405 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5406 debounce = 0; 5407 debounce_time = drv_usectohz(1000000); 5408 } 5409 if (debounce) { 5410 sockp->pcs_flags |= PCS_CARD_PRESENT; 5411 if (pcic_do_insertion) { 5412 5413 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5414 5415 if (cbps & CB_PS_16BITCARD) { 5416 pcic_err(pcic->dip, 8, "16 bit card inserted\n"); 5417 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5418 /* calls pcm_adapter_callback() */ 5419 if (pcic->pc_callback) { 5420 5421 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 5422 pcic->dip, PCM_DEVICETYPE, 5423 "pccard"); 5424 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5425 PCE_CARD_INSERT, 5426 sockp->pcs_socket); 5427 } 5428 } else if (cbps & CB_PS_CBCARD) { 5429 pcic_err(pcic->dip, 8, "32 bit card inserted\n"); 5430 5431 if (pcic->pc_flags & PCF_CARDBUS) { 5432 sockp->pcs_flags |= PCS_CARD_ISCARDBUS; 5433 #ifdef CARDBUS 5434 if (!pcic_load_cardbus(pcic, sockp)) { 5435 pcic_unload_cardbus(pcic, sockp); 5436 } 5437 5438 #else 5439 cmn_err(CE_NOTE, 5440 "32 bit Cardbus not supported in" 5441 " this device driver\n"); 5442 #endif 5443 } else { 5444 /* 5445 * Ignore the card 5446 */ 5447 cmn_err(CE_NOTE, 5448 "32 bit Cardbus not supported on this" 5449 " device\n"); 5450 } 5451 } else { 5452 cmn_err(CE_NOTE, 5453 "Unsupported PCMCIA card inserted\n"); 5454 } 5455 } 5456 } else { 5457 do_debounce = B_TRUE; 5458 } 5459 } else { 5460 /* 5461 * It is possible to come through here if the system 5462 * starts up with cards already inserted. Do nothing 5463 * and don't worry about it. 5464 */ 5465 #ifdef PCIC_DEBUG 5466 pcic_err(pcic->dip, 5, 5467 "pcic%d: Odd card insertion indication on socket %d\n", 5468 ddi_get_instance(pcic->dip), 5469 sockp->pcs_socket); 5470 #endif 5471 } 5472 break; 5473 5474 default: 5475 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5476 /* 5477 * Someone has started to insert a card so delay a while. 5478 */ 5479 do_debounce = B_TRUE; 5480 break; 5481 } 5482 /* 5483 * Otherwise this is basically the same as not present 5484 * so fall through. 5485 */ 5486 5487 /* FALLTHRU */ 5488 case 0: 5489 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5490 if (pcic->pc_flags & PCF_CBPWRCTL) { 5491 pcic_putcb(pcic, CB_CONTROL, 0); 5492 } else { 5493 pcic_putb(pcic, sockp->pcs_socket, PCIC_POWER_CONTROL, 0); 5494 (void) pcic_getb(pcic, sockp->pcs_socket, 5495 PCIC_POWER_CONTROL); 5496 } 5497 #ifdef PCIC_DEBUG 5498 pcic_err(pcic->dip, 8, "Card removed\n"); 5499 #endif 5500 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5501 5502 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5503 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5504 if (pcic_do_removal && pcic->pc_callback) { 5505 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5506 PCE_CARD_REMOVAL, sockp->pcs_socket); 5507 } 5508 } 5509 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5510 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5511 sockp->pcs_flags |= PCS_CARD_CBREM; 5512 } 5513 sockp->pcs_flags |= PCS_CARD_REMOVED; 5514 5515 do_debounce = B_TRUE; 5516 } 5517 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5518 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5519 /* 5520 * Ensure that we do the unloading in the 5521 * debounce handler, that way we're not doing 5522 * nasty things in an interrupt handler. e.g. 5523 * a USB device will wait for data which will 5524 * obviously never come because we've 5525 * unplugged the device, but the wait will 5526 * wait forever because no interrupts can 5527 * come in... 5528 */ 5529 #ifdef CARDBUS 5530 pcic_unload_cardbus(pcic, sockp); 5531 /* pcic_dump_all(pcic); */ 5532 #endif 5533 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5534 } 5535 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5536 } 5537 break; 5538 } /* switch */ 5539 5540 if (do_debounce) { 5541 /* 5542 * Delay doing 5543 * anything for a while so that things can settle 5544 * down a little. Interrupts are already disabled. 5545 * Reset the state and we'll reevaluate the 5546 * whole kit 'n kaboodle when the timeout fires 5547 */ 5548 #ifdef PCIC_DEBUG 5549 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5550 "socket %d.%d\n", 5551 ddi_get_instance(pcic->dip), 5552 sockp->pcs_socket); 5553 #endif 5554 sockp->pcs_debounce_id = pcic_add_debqueue(sockp, debounce_time); 5555 5556 /* 5557 * We bug out here without re-enabling interrupts. They will 5558 * be re-enabled when the debounce timeout swings through 5559 * here. 5560 */ 5561 return; 5562 } 5563 5564 /* 5565 * Turn on Card detect interrupts. Other interrupts will be 5566 * enabled during set_socket calls. 5567 * 5568 * Note that set_socket only changes interrupt settings when there 5569 * is a card present. 5570 */ 5571 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5572 irq |= PCIC_CD_DETECT; 5573 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5574 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5575 5576 /* Out from debouncing state */ 5577 sockp->pcs_flags &= ~PCS_DEBOUNCING; 5578 5579 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5580 } 5581 5582 /* 5583 * pcic_getb() 5584 * get an I/O byte based on the yardware decode method 5585 */ 5586 static uint8_t 5587 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5588 { 5589 int work; 5590 5591 #if defined(PCIC_DEBUG) 5592 if (pcic_debug == 0x7fff) { 5593 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5594 (void *)pcic, socket, reg); 5595 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5596 pcic->pc_io_type, (void *)pcic->handle, 5597 (void *)pcic->ioaddr); 5598 } 5599 #endif 5600 5601 switch (pcic->pc_io_type) { 5602 case PCIC_IO_TYPE_YENTA: 5603 return (ddi_get8(pcic->handle, 5604 pcic->ioaddr + CB_R2_OFFSET + reg)); 5605 default: 5606 work = (socket * PCIC_SOCKET_1) | reg; 5607 ddi_put8(pcic->handle, pcic->ioaddr, work); 5608 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5609 } 5610 } 5611 5612 static void 5613 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5614 { 5615 int work; 5616 5617 #if defined(PCIC_DEBUG) 5618 if (pcic_debug == 0x7fff) { 5619 cmn_err(CE_CONT, 5620 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5621 (void *)pcic, socket, reg, value); 5622 cmn_err(CE_CONT, 5623 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5624 pcic->pc_io_type, (void *)pcic->handle, 5625 (void *)pcic->ioaddr); 5626 } 5627 #endif 5628 5629 5630 switch (pcic->pc_io_type) { 5631 case PCIC_IO_TYPE_YENTA: 5632 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5633 value); 5634 break; 5635 default: 5636 work = (socket * PCIC_SOCKET_1) | reg; 5637 ddi_put8(pcic->handle, pcic->ioaddr, work); 5638 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5639 break; 5640 } 5641 } 5642 5643 /* 5644 * chip identification functions 5645 */ 5646 5647 /* 5648 * chip identification: Cirrus Logic PD6710/6720/6722 5649 */ 5650 static int 5651 pcic_ci_cirrus(pcicdev_t *pcic) 5652 { 5653 int value1, value2; 5654 5655 /* Init the CL id mode */ 5656 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5657 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5658 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5659 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5660 5661 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5662 (value2 & PCIC_CI_ID) == 0) { 5663 /* chip is a Cirrus Logic and not Intel */ 5664 pcic->pc_type = PCIC_CL_PD6710; 5665 if (value1 & PCIC_CI_SLOTS) 5666 pcic->pc_chipname = PCIC_TYPE_PD6720; 5667 else 5668 pcic->pc_chipname = PCIC_TYPE_PD6710; 5669 /* now fine tune things just in case a 6722 */ 5670 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5671 if (value1 == 0) { 5672 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5673 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5674 if (value1 == 0x55) { 5675 pcic->pc_chipname = PCIC_TYPE_PD6722; 5676 pcic->pc_type = PCIC_CL_PD6722; 5677 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5678 } 5679 } 5680 return (1); 5681 } 5682 return (0); 5683 } 5684 5685 /* 5686 * chip identification: Vadem (VG365/465/468/469) 5687 */ 5688 5689 static void 5690 pcic_vadem_enable(pcicdev_t *pcic) 5691 { 5692 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5693 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5694 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5695 } 5696 5697 static int 5698 pcic_ci_vadem(pcicdev_t *pcic) 5699 { 5700 int value; 5701 5702 pcic_vadem_enable(pcic); 5703 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5704 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5705 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5706 (value | PCIC_VADEM_D3) || 5707 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5708 PCIC_VADEM_469) { 5709 int vadem, new; 5710 pcic_vadem_enable(pcic); 5711 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5712 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5713 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5714 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5715 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5716 5717 /* want to lock but leave mouse or other on */ 5718 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5719 switch (value & PCIC_REV_MASK) { 5720 case PCIC_VADEM_365: 5721 pcic->pc_chipname = PCIC_VG_365; 5722 pcic->pc_type = PCIC_VADEM; 5723 break; 5724 case PCIC_VADEM_465: 5725 pcic->pc_chipname = PCIC_VG_465; 5726 pcic->pc_type = PCIC_VADEM; 5727 pcic->pc_flags |= PCF_1SOCKET; 5728 break; 5729 case PCIC_VADEM_468: 5730 pcic->pc_chipname = PCIC_VG_468; 5731 pcic->pc_type = PCIC_VADEM; 5732 break; 5733 case PCIC_VADEM_469: 5734 pcic->pc_chipname = PCIC_VG_469; 5735 pcic->pc_type = PCIC_VADEM_VG469; 5736 break; 5737 } 5738 return (1); 5739 } 5740 return (0); 5741 } 5742 5743 /* 5744 * chip identification: Ricoh 5745 */ 5746 static int 5747 pcic_ci_ricoh(pcicdev_t *pcic) 5748 { 5749 int value; 5750 5751 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5752 switch (value) { 5753 case PCIC_RF_296: 5754 pcic->pc_type = PCIC_RICOH; 5755 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5756 return (1); 5757 case PCIC_RF_396: 5758 pcic->pc_type = PCIC_RICOH; 5759 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5760 return (1); 5761 } 5762 return (0); 5763 } 5764 5765 5766 /* 5767 * set up available address spaces in busra 5768 */ 5769 static void 5770 pcic_init_assigned(dev_info_t *dip) 5771 { 5772 pcm_regs_t *pcic_avail_p; 5773 pci_regspec_t *pci_avail_p, *regs; 5774 int len, entries, rlen; 5775 dev_info_t *pdip; 5776 5777 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5778 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5779 /* 5780 * found "available" property at the cardbus/pcmcia node 5781 * need to translate address space entries from pcmcia 5782 * format to pci format 5783 */ 5784 entries = len / sizeof (pcm_regs_t); 5785 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5786 KM_SLEEP); 5787 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5788 entries) == DDI_SUCCESS) 5789 (void) pci_resource_setup_avail(dip, pci_avail_p, 5790 entries); 5791 kmem_free(pcic_avail_p, len); 5792 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5793 return; 5794 } 5795 5796 /* 5797 * "legacy" platforms will have "available" property in pci node 5798 */ 5799 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5800 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5801 "available", (caddr_t)&pci_avail_p, &len) == 5802 DDI_PROP_SUCCESS) { 5803 /* (void) pci_resource_setup(pdip); */ 5804 kmem_free(pci_avail_p, len); 5805 break; 5806 } 5807 } 5808 5809 if (pdip == NULL) { 5810 int len; 5811 char bus_type[16] = "(unknown)"; 5812 dev_info_t *par; 5813 5814 cmn_err(CE_CONT, 5815 "?pcic_init_assigned: no available property for pcmcia\n"); 5816 5817 /* 5818 * This code is taken from pci_resource_setup() but does 5819 * not attempt to use the "available" property to populate 5820 * the ndi maps that are created. 5821 * The fact that we will actually 5822 * free some resource below (that was allocated by OBP) 5823 * should be enough to be going on with. 5824 */ 5825 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5826 len = sizeof (bus_type); 5827 5828 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5829 PROP_LEN_AND_VAL_BUF, 5830 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5831 "device_type", 5832 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5833 (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 5834 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0)) 5835 break; 5836 } 5837 if (par != NULL && 5838 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5839 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5840 par = NULL; 5841 } else { 5842 #ifdef CARDBUS 5843 cardbus_bus_range_t *bus_range; 5844 int k; 5845 5846 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5847 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5848 if (bus_range->lo != bus_range->hi) 5849 pcic_err(pdip, 9, "allowable bus range is " 5850 "%u->%u\n", bus_range->lo, bus_range->hi); 5851 else { 5852 pcic_err(pdip, 0, 5853 "!No spare PCI bus numbers, range is " 5854 "%u->%u, cardbus isn't usable\n", 5855 bus_range->lo, bus_range->hi); 5856 } 5857 kmem_free(bus_range, k); 5858 } else 5859 pcic_err(pdip, 0, "!No bus-range property seems to " 5860 "have been set up\n"); 5861 #endif 5862 /* 5863 * Have a valid parent with the "available" property 5864 */ 5865 (void) pci_resource_setup(pdip); 5866 } 5867 5868 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5869 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5870 "assigned-addresses", 5871 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5872 ra_return_t ra; 5873 5874 /* 5875 * On the UltraBook IIi the ranges are assigned under 5876 * openboot. If we don't free them here the first I/O 5877 * space that can be used is up above 0x10000 which 5878 * doesn't work for this driver due to restrictions 5879 * on the PCI I/O addresses the controllers can cope with. 5880 * They are never going to be used by anything else 5881 * so free them up to the general pool. AG. 5882 */ 5883 pcic_err(dip, 1, "Free assigned addresses\n"); 5884 5885 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5886 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5887 regs[0].pci_size_low == 0x1000000) { 5888 ra.ra_addr_lo = regs[0].pci_phys_low; 5889 ra.ra_len = regs[0].pci_size_low; 5890 (void) pcmcia_free_mem(dip, &ra); 5891 } 5892 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5893 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5894 (regs[1].pci_size_low == 0x8000 || 5895 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5896 { 5897 ra.ra_addr_lo = regs[1].pci_phys_low; 5898 ra.ra_len = regs[1].pci_size_low; 5899 (void) pcmcia_free_io(dip, &ra); 5900 } 5901 kmem_free((caddr_t)regs, rlen); 5902 } 5903 } 5904 5905 /* 5906 * translate "available" from pcmcia format to pci format 5907 */ 5908 static int 5909 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 5910 pci_regspec_t *pci_p, int entries) 5911 { 5912 int i, range_len, range_entries; 5913 pcic_ranges_t *pcic_range_p; 5914 5915 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 5916 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 5917 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 5918 "no ranges property for pcmcia\n"); 5919 return (DDI_FAILURE); 5920 } 5921 5922 range_entries = range_len / sizeof (pcic_ranges_t); 5923 5924 /* for each "available" entry to be translated */ 5925 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 5926 int j; 5927 pcic_ranges_t *range_p = pcic_range_p; 5928 pci_p->pci_phys_hi = -1u; /* default invalid value */ 5929 5930 /* for each "ranges" entry to be searched */ 5931 for (j = 0; j < range_entries; j++, range_p++) { 5932 uint64_t range_end = range_p->pcic_range_caddrlo + 5933 range_p->pcic_range_size; 5934 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 5935 5936 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 5937 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 5938 (range_end < avail_end)) 5939 continue; 5940 5941 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 5942 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 5943 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 5944 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 5945 pci_p->pci_size_hi = 0; 5946 pci_p->pci_size_low = pcic_p->phys_len; 5947 } 5948 } 5949 kmem_free(pcic_range_p, range_len); 5950 return (DDI_SUCCESS); 5951 } 5952 5953 static int 5954 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 5955 { 5956 #ifdef CARDBUS 5957 if (cardbus_is_cb_minor(*dev)) 5958 return (cardbus_open(dev, flag, otyp, cred)); 5959 #endif 5960 return (EINVAL); 5961 } 5962 5963 static int 5964 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 5965 { 5966 #ifdef CARDBUS 5967 if (cardbus_is_cb_minor(dev)) 5968 return (cardbus_close(dev, flag, otyp, cred)); 5969 #endif 5970 return (EINVAL); 5971 } 5972 5973 static int 5974 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 5975 int *rval) 5976 { 5977 #ifdef CARDBUS 5978 if (cardbus_is_cb_minor(dev)) 5979 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 5980 #endif 5981 return (EINVAL); 5982 } 5983 5984 5985 static boolean_t 5986 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 5987 { 5988 uint32_t present_state; 5989 dev_info_t *dip = pcic->dip; 5990 set_socket_t s; 5991 get_socket_t g; 5992 boolean_t retval; 5993 unsigned vccLevel; 5994 5995 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 5996 5997 pcic_mutex_exit(&pcic->pc_lock); 5998 5999 bzero(&s, sizeof (set_socket_t)); 6000 s.socket = sockp->pcs_socket; 6001 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6002 s.IFType = IF_CARDBUS; 6003 s.State = (unsigned)~0; 6004 6005 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6006 if (present_state & PCIC_VCC_3VCARD) 6007 s.VccLevel = PCIC_VCC_3VLEVEL; 6008 else if (present_state & PCIC_VCC_5VCARD) 6009 s.VccLevel = PCIC_VCC_5VLEVEL; 6010 else { 6011 cmn_err(CE_CONT, 6012 "pcic_load_cardbus: unsupported card voltage\n"); 6013 goto failure; 6014 } 6015 vccLevel = s.VccLevel; 6016 s.Vpp1Level = s.Vpp2Level = 0; 6017 6018 if (pcic_set_socket(dip, &s) != SUCCESS) 6019 goto failure; 6020 6021 if (pcic_reset_socket(dip, sockp->pcs_socket, 6022 RESET_MODE_CARD_ONLY) != SUCCESS) 6023 goto failure; 6024 6025 bzero(&g, sizeof (get_socket_t)); 6026 g.socket = sockp->pcs_socket; 6027 if (pcic_get_socket(dip, &g) != SUCCESS) 6028 goto failure; 6029 6030 bzero(&s, sizeof (set_socket_t)); 6031 s.socket = sockp->pcs_socket; 6032 s.SCIntMask = SBM_CD; 6033 s.IREQRouting = g.IRQRouting; 6034 s.IFType = g.IFType; 6035 s.CtlInd = g.CtlInd; 6036 s.State = (unsigned)~0; 6037 s.VccLevel = vccLevel; 6038 s.Vpp1Level = s.Vpp2Level = 0; 6039 6040 retval = pcic_set_socket(dip, &s); 6041 pcmcia_cb_resumed(s.socket); 6042 if (retval != SUCCESS) 6043 goto failure; 6044 6045 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6046 goto exit; 6047 6048 failure: 6049 retval = B_FALSE; 6050 6051 exit: 6052 pcic_mutex_enter(&pcic->pc_lock); 6053 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6054 retval ? "success" : "failure"); 6055 return (retval); 6056 } 6057 6058 static void 6059 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6060 { 6061 dev_info_t *dip = pcic->dip; 6062 set_socket_t s; 6063 6064 pcic_mutex_exit(&pcic->pc_lock); 6065 6066 cardbus_unload_cardbus(dip); 6067 6068 bzero(&s, sizeof (set_socket_t)); 6069 s.socket = sockp->pcs_socket; 6070 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6071 s.IREQRouting = 0; 6072 s.IFType = IF_MEMORY; 6073 s.CtlInd = 0; 6074 s.State = 0; 6075 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6076 6077 (void) pcic_set_socket(dip, &s); 6078 6079 pcic_mutex_enter(&pcic->pc_lock); 6080 } 6081 6082 static uint32_t 6083 pcic_getcb(pcicdev_t *pcic, int reg) 6084 { 6085 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6086 6087 return (ddi_get32(pcic->handle, 6088 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6089 } 6090 6091 static void 6092 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6093 { 6094 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6095 6096 ddi_put32(pcic->handle, 6097 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6098 } 6099 6100 static void 6101 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6102 { 6103 uint8_t value; 6104 uint16_t brdgctl; 6105 6106 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6107 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6108 6109 switch (pcic->pc_type) { 6110 case PCIC_INTEL_i82092: 6111 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6112 PCIC_82092_INT_ENABLE); 6113 break; 6114 case PCIC_O2_OZ6912: 6115 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6116 value |= 0x8; 6117 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6118 break; 6119 case PCIC_CL_PD6832: 6120 case PCIC_TI_PCI1250: 6121 case PCIC_TI_PCI1221: 6122 case PCIC_TI_PCI1225: 6123 case PCIC_TI_PCI1410: 6124 case PCIC_ENE_1410: 6125 case PCIC_TI_PCI1510: 6126 case PCIC_TI_PCI1520: 6127 case PCIC_TI_PCI1420: 6128 case PCIC_ENE_1420: 6129 /* route card functional interrupts to PCI interrupts */ 6130 brdgctl = ddi_get16(pcic->cfg_handle, 6131 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6132 pcic_err(NULL, 1, 6133 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6134 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6135 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6136 ddi_put16(pcic->cfg_handle, 6137 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6138 brdgctl); 6139 /* Flush the write */ 6140 (void) ddi_get16(pcic->cfg_handle, 6141 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6142 break; 6143 default: 6144 break; 6145 } 6146 } 6147 6148 static void 6149 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6150 { 6151 uint8_t value; 6152 uint16_t brdgctl; 6153 6154 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6155 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6156 6157 switch (pcic->pc_type) { 6158 case PCIC_INTEL_i82092: 6159 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6160 PCIC_82092_INT_DISABLE); 6161 break; 6162 case PCIC_O2_OZ6912: 6163 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6164 value &= ~0x8; 6165 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6166 /* Flush the write */ 6167 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6168 break; 6169 case PCIC_CL_PD6832: 6170 case PCIC_TI_PCI1250: 6171 case PCIC_TI_PCI1221: 6172 case PCIC_TI_PCI1225: 6173 case PCIC_TI_PCI1410: 6174 case PCIC_ENE_1410: 6175 case PCIC_TI_PCI1510: 6176 case PCIC_TI_PCI1520: 6177 case PCIC_TI_PCI1420: 6178 case PCIC_ENE_1420: 6179 /* 6180 * This maps I/O interrupts to ExCA which 6181 * have been turned off by the write to 6182 * PCIC_INTERRUPT above. It would appear to 6183 * be the only way to actually turn I/O Ints off 6184 * while retaining CS Ints. 6185 */ 6186 brdgctl = ddi_get16(pcic->cfg_handle, 6187 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6188 pcic_err(NULL, 1, 6189 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6190 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6191 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6192 ddi_put16(pcic->cfg_handle, 6193 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6194 brdgctl); 6195 /* Flush the write */ 6196 (void) ddi_get16(pcic->cfg_handle, 6197 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6198 break; 6199 default: 6200 break; 6201 } 6202 } 6203 6204 static void 6205 pcic_cb_enable_intr(dev_info_t *dip) 6206 { 6207 anp_t *anp = ddi_get_driver_private(dip); 6208 pcicdev_t *pcic = anp->an_private; 6209 6210 mutex_enter(&pcic->pc_lock); 6211 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6212 mutex_exit(&pcic->pc_lock); 6213 } 6214 6215 static void 6216 pcic_cb_disable_intr(dev_info_t *dip) 6217 { 6218 anp_t *anp = ddi_get_driver_private(dip); 6219 pcicdev_t *pcic = anp->an_private; 6220 6221 mutex_enter(&pcic->pc_lock); 6222 pcic_disable_io_intr(pcic, 0); 6223 mutex_exit(&pcic->pc_lock); 6224 } 6225 6226 static int 6227 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6228 { 6229 int nerr = 0; 6230 if (e & PCI_STAT_PERROR) { 6231 nerr++; 6232 cmn_err(CE_CONT, "detected parity error.\n"); 6233 } 6234 if (e & PCI_STAT_S_SYSERR) { 6235 nerr++; 6236 if (bridge_secondary) 6237 cmn_err(CE_CONT, "received system error.\n"); 6238 else 6239 cmn_err(CE_CONT, "signalled system error.\n"); 6240 } 6241 if (e & PCI_STAT_R_MAST_AB) { 6242 nerr++; 6243 cmn_err(CE_CONT, "received master abort.\n"); 6244 } 6245 if (e & PCI_STAT_R_TARG_AB) 6246 cmn_err(CE_CONT, "received target abort.\n"); 6247 if (e & PCI_STAT_S_TARG_AB) 6248 cmn_err(CE_CONT, "signalled target abort\n"); 6249 if (e & PCI_STAT_S_PERROR) { 6250 nerr++; 6251 cmn_err(CE_CONT, "signalled parity error\n"); 6252 } 6253 return (nerr); 6254 } 6255 6256 #if defined(__sparc) 6257 static int 6258 pcic_fault(enum pci_fault_ops op, void *arg) 6259 { 6260 pcicdev_t *pcic = (pcicdev_t *)arg; 6261 ushort_t pci_cfg_stat = 6262 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6263 ushort_t pci_cfg_sec_stat = 6264 pci_config_get16(pcic->cfg_handle, 0x16); 6265 char nm[24]; 6266 int nerr = 0; 6267 6268 cardbus_dump_pci_config(pcic->dip); 6269 6270 switch (op) { 6271 case FAULT_LOG: 6272 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6273 ddi_get_instance(pcic->dip)); 6274 6275 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6276 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6277 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6278 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6279 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6280 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6281 return (nerr); 6282 case FAULT_POKEFINI: 6283 case FAULT_RESET: 6284 pci_config_put16(pcic->cfg_handle, 6285 PCI_CONF_STAT, pci_cfg_stat); 6286 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6287 break; 6288 case FAULT_POKEFLT: 6289 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6290 return (1); 6291 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6292 return (1); 6293 break; 6294 default: 6295 break; 6296 } 6297 return (DDI_SUCCESS); 6298 } 6299 #endif 6300 6301 static void 6302 pcic_do_resume(pcicdev_t *pcic) 6303 { 6304 int i, interrupt; 6305 uint8_t cfg; 6306 6307 6308 #if defined(PCIC_DEBUG) 6309 pcic_err(NULL, 6, "pcic_do_resume(): entered\n"); 6310 #endif 6311 6312 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6313 for (i = 0; i < pcic->pc_numsockets; i++) { 6314 /* Enable interrupts on PCI if needs be */ 6315 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6316 if (pcic->pc_flags & PCF_USE_SMI) 6317 interrupt |= PCIC_INTR_ENABLE; 6318 pcic_putb(pcic, i, PCIC_INTERRUPT, 6319 PCIC_RESET | interrupt); 6320 pcic->pc_sockets[i].pcs_debounce_id = 6321 pcic_add_debqueue(&pcic->pc_sockets[i], 6322 drv_usectohz(pcic_debounce_time)); 6323 } 6324 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6325 if (pcic_do_pcmcia_sr) 6326 (void) pcmcia_wait_insert(pcic->dip); 6327 /* 6328 * The CardBus controller may be in RESET state after the 6329 * system is resumed from sleeping. The RESET bit is in 6330 * the Bridge Control register. This is true for all(TI, 6331 * Toshiba ToPIC95/97, RICOH, and O2Micro) CardBus 6332 * controllers. Need to clear the RESET bit explicitly. 6333 */ 6334 cfg = ddi_get8(pcic->cfg_handle, 6335 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 6336 if (cfg & (1<<6)) { 6337 cfg &= ~(1<<6); 6338 ddi_put8(pcic->cfg_handle, 6339 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 6340 cfg); 6341 cfg = ddi_get8(pcic->cfg_handle, 6342 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 6343 if (cfg & (1<<6)) { 6344 pcic_err(pcic->dip, 1, "Failed to take pcic out of reset"); 6345 } 6346 } 6347 6348 } 6349 6350 static void 6351 pcic_debounce(pcic_socket_t *pcs) 6352 { 6353 uint8_t status, stschng; 6354 6355 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6356 pcs->pcs_flags &= ~PCS_STARTING; 6357 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6358 PCIC_CARD_STATUS_CHANGE); 6359 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6360 PCIC_INTERFACE_STATUS); 6361 #ifdef PCIC_DEBUG 6362 pcic_err(pcs->pcs_pcic->dip, 8, 6363 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6364 "chg 0x%x flg 0x%x\n", 6365 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6366 status, stschng, pcs->pcs_flags); 6367 #endif 6368 6369 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6370 PCIC_CD_DETECT); 6371 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6372 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6373 } 6374 6375 static void 6376 pcic_deb_thread() 6377 { 6378 callb_cpr_t cprinfo; 6379 struct debounce *debp; 6380 clock_t lastt; 6381 6382 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6383 callb_generic_cpr, "pcic debounce thread"); 6384 mutex_enter(&pcic_deb_mtx); 6385 while (pcic_deb_threadid) { 6386 while (pcic_deb_queue) { 6387 #ifdef PCIC_DEBUG 6388 pcic_dump_debqueue("Thread"); 6389 #endif 6390 debp = pcic_deb_queue; 6391 (void) drv_getparm(LBOLT, &lastt); 6392 if (lastt >= debp->expire) { 6393 pcic_deb_queue = debp->next; 6394 mutex_exit(&pcic_deb_mtx); 6395 pcic_debounce(debp->pcs); 6396 mutex_enter(&pcic_deb_mtx); 6397 kmem_free(debp, sizeof (*debp)); 6398 } else { 6399 (void) cv_timedwait(&pcic_deb_cv, 6400 &pcic_deb_mtx, debp->expire); 6401 } 6402 } 6403 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6404 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6405 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6406 } 6407 pcic_deb_threadid = (kthread_t *)1; 6408 cv_signal(&pcic_deb_cv); 6409 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6410 thread_exit(); 6411 } 6412 6413 static void * 6414 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6415 { 6416 clock_t lbolt; 6417 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6418 6419 (void) drv_getparm(LBOLT, &lbolt); 6420 dbp = kmem_alloc(sizeof (struct debounce), KM_SLEEP); 6421 6422 dbp->expire = lbolt + clocks; 6423 dbp->pcs = pcs; 6424 mutex_enter(&pcic_deb_mtx); 6425 while (*dbpp) { 6426 if (dbp->expire > (*dbpp)->expire) 6427 dbpp = &((*dbpp)->next); 6428 else 6429 break; 6430 } 6431 dbp->next = *dbpp; 6432 *dbpp = dbp; 6433 #ifdef PCIC_DEBUG 6434 pcic_dump_debqueue("Add"); 6435 #endif 6436 cv_signal(&pcic_deb_cv); 6437 mutex_exit(&pcic_deb_mtx); 6438 return (dbp); 6439 } 6440 6441 static void 6442 pcic_rm_debqueue(void *id) 6443 { 6444 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6445 6446 dbp = (struct debounce *)id; 6447 mutex_enter(&pcic_deb_mtx); 6448 while (*dbpp) { 6449 if (*dbpp == dbp) { 6450 *dbpp = dbp->next; 6451 kmem_free(dbp, sizeof (*dbp)); 6452 #ifdef PCIC_DEBUG 6453 pcic_dump_debqueue("Remove"); 6454 #endif 6455 cv_signal(&pcic_deb_cv); 6456 mutex_exit(&pcic_deb_mtx); 6457 return; 6458 } 6459 dbpp = &((*dbpp)->next); 6460 } 6461 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6462 mutex_exit(&pcic_deb_mtx); 6463 } 6464 6465 6466 static int pcic_powerdelay = 0; 6467 6468 static int 6469 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6470 { 6471 int ind, value, orig_pwrctl; 6472 6473 /* power setup -- if necessary */ 6474 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6475 6476 #if defined(PCIC_DEBUG) 6477 pcic_err(pcic->dip, 6, 6478 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6479 socket, powerlevel, orig_pwrctl); 6480 #endif 6481 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6482 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6483 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6484 if (powerlevel != orig_pwrctl) { 6485 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6486 int ifs; 6487 /* 6488 * set power to socket 6489 * note that the powerlevel was calculated earlier 6490 */ 6491 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6492 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6493 6494 /* 6495 * this second write to the power control register 6496 * is needed to resolve a problem on 6497 * the IBM ThinkPad 750 6498 * where the first write doesn't latch. 6499 * The second write appears to always work and 6500 * doesn't hurt the operation of other chips 6501 * so we can just use it -- this is good since we can't 6502 * determine what chip the 750 actually uses 6503 * (I suspect an early Ricoh). 6504 */ 6505 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6506 6507 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6508 pcic_mswait(pcic, socket, pcic_powerdelay); 6509 #if defined(PCIC_DEBUG) 6510 pcic_err(pcic->dip, 8, 6511 "\tpowerlevel reg = %x (ifs %x)\n", 6512 value, pcic_getb(pcic, socket, 6513 PCIC_INTERFACE_STATUS)); 6514 pcic_err(pcic->dip, 8, 6515 "CBus regs: PS 0x%x, Control 0x%x\n", 6516 pcic_getcb(pcic, CB_PRESENT_STATE), 6517 pcic_getcb(pcic, CB_CONTROL)); 6518 #endif 6519 /* 6520 * since power was touched, make sure it says it 6521 * is on. This lets it become stable. 6522 */ 6523 for (ind = 0; ind < 20; ind++) { 6524 ifs = pcic_getb(pcic, socket, 6525 PCIC_INTERFACE_STATUS); 6526 if (ifs & PCIC_POWER_ON) 6527 break; 6528 else { 6529 pcic_putb(pcic, socket, 6530 PCIC_POWER_CONTROL, 0); 6531 (void) pcic_getb(pcic, socket, 6532 PCIC_POWER_CONTROL); 6533 pcic_mswait(pcic, socket, 40); 6534 if (ind == 10) { 6535 pcic_putcb(pcic, CB_EVENT_FORCE, 6536 CB_EF_CVTEST); 6537 pcic_mswait(pcic, socket, 100); 6538 } 6539 pcic_putb(pcic, socket, 6540 PCIC_POWER_CONTROL, 6541 powerlevel & ~POWER_OUTPUT_ENABLE); 6542 (void) pcic_getb(pcic, socket, 6543 PCIC_POWER_CONTROL); 6544 pcic_mswait(pcic, socket, 6545 pcic_powerdelay); 6546 pcic_putb(pcic, socket, 6547 PCIC_POWER_CONTROL, powerlevel); 6548 (void) pcic_getb(pcic, socket, 6549 PCIC_POWER_CONTROL); 6550 pcic_mswait(pcic, socket, 6551 pcic_powerdelay); 6552 } 6553 } 6554 6555 if (!(ifs & PCIC_POWER_ON)) { 6556 cmn_err(CE_WARN, 6557 "pcic socket %d: Power didn't get turned" 6558 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6559 "misc1 0x%x igc 0x%x ind %d\n", 6560 socket, ifs, 6561 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6562 orig_pwrctl, 6563 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6564 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6565 ind); 6566 return (BAD_VCC); 6567 } 6568 #if defined(PCIC_DEBUG) 6569 pcic_err(pcic->dip, 8, 6570 "\tind = %d, if status %x pwrc 0x%x " 6571 "misc1 0x%x igc 0x%x\n", 6572 ind, ifs, 6573 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6574 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6575 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6576 #endif 6577 } else { 6578 /* explicitly turned off the power */ 6579 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6580 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6581 } 6582 } 6583 return (SUCCESS); 6584 } 6585 6586 static int pcic_cbdoreset_during_poweron = 1; 6587 static int 6588 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6589 { 6590 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6591 int ind, iobits; 6592 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6593 6594 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6595 6596 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6597 cbctl |= pcic_cbv_levels[ind]; 6598 6599 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6600 cbctl |= (pcic_cbv_levels[ind]<<4); 6601 6602 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6603 6604 #if defined(PCIC_DEBUG) 6605 pcic_err(pcic->dip, 6, 6606 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6607 "cbctl 0x%x->0x%x\n", 6608 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6609 #endif 6610 if (cbctl != orig_cbctl) { 6611 if (pcic_cbdoreset_during_poweron && 6612 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6613 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6614 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits & ~PCIC_RESET); 6615 } 6616 pcic_putcb(pcic, CB_CONTROL, cbctl); 6617 6618 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6619 pcic_mswait(pcic, socket, pcic_powerdelay); 6620 return (SUCCESS); 6621 } 6622 for (ind = 0; ind < 20; ind++) { 6623 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6624 6625 if (cbstev & CB_SE_POWER_CYCLE) { 6626 6627 /* 6628 * delay 400 ms: though the standard defines that the Vcc 6629 * set-up time is 20 ms, some PC-Card bridge requires longer 6630 * duration. 6631 * Note: We should check the status AFTER the delay to give time 6632 * for things to stabilize. 6633 */ 6634 pcic_mswait(pcic, socket, 400); 6635 6636 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6637 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6638 /* break; */ 6639 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6640 } 6641 if (cbctl & CB_PS_BADVCC) { 6642 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6643 break; 6644 } 6645 6646 #if defined(PCIC_DEBUG) 6647 pcic_err(pcic->dip, 8, 6648 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6649 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6650 cbctl, orig_cbctl); 6651 #endif 6652 if (pcic_cbdoreset_during_poweron && 6653 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6654 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6655 } 6656 return (SUCCESS); 6657 } 6658 pcic_mswait(pcic, socket, 40); 6659 } 6660 if (pcic_cbdoreset_during_poweron && 6661 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6662 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6663 } 6664 cmn_err(CE_WARN, 6665 "pcic socket %d: Power didn't get turned on/off!\n" 6666 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6667 "vcc %d vpp1 %d", socket, cbstev, 6668 pcic_getcb(pcic, CB_PRESENT_STATE), 6669 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6670 return (BAD_VCC); 6671 } 6672 return (SUCCESS); 6673 } 6674 6675 static int pcic_do_pprintf = 0; 6676 6677 static void 6678 pcic_dump_debqueue(char *msg) 6679 { 6680 struct debounce *debp = pcic_deb_queue; 6681 clock_t lbolt; 6682 6683 (void) drv_getparm(LBOLT, &lbolt); 6684 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6685 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6686 while (debp) { 6687 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6688 (void *) debp, (int)debp->expire, (void *) debp->next, 6689 debp->pcs->pcs_debounce_id); 6690 debp = debp->next; 6691 } 6692 } 6693 6694 6695 /* PRINTFLIKE3 */ 6696 static void 6697 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6698 { 6699 if (pcic_debug && (level <= pcic_debug)) { 6700 va_list adx; 6701 int instance; 6702 char buf[256]; 6703 const char *name; 6704 #if !defined(PCIC_DEBUG) 6705 int ce; 6706 char qmark = 0; 6707 6708 if (level <= 3) 6709 ce = CE_WARN; 6710 else 6711 ce = CE_CONT; 6712 if (level == 4) 6713 qmark = 1; 6714 #endif 6715 6716 if (dip) { 6717 instance = ddi_get_instance(dip); 6718 /* name = ddi_binding_name(dip); */ 6719 name = ddi_driver_name(dip); 6720 } else { 6721 instance = 0; 6722 name = ""; 6723 } 6724 6725 va_start(adx, fmt); 6726 (void) vsprintf(buf, fmt, adx); 6727 va_end(adx); 6728 6729 #if defined(PCIC_DEBUG) 6730 if (pcic_do_pprintf) { 6731 if (dip) { 6732 if (instance >= 0) 6733 prom_printf("%s(%d),0x%p: %s", name, 6734 instance, dip, buf); 6735 else 6736 prom_printf("%s,0x%p: %s", 6737 name, dip, buf); 6738 } else 6739 prom_printf(buf); 6740 } else { 6741 if (dip) { 6742 if (instance >= 0) 6743 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6744 name, instance, (void *) dip, buf); 6745 else 6746 cmn_err(CE_CONT, "%s,0x%p: %s", 6747 name, (void *) dip, buf); 6748 } else 6749 cmn_err(CE_CONT, buf); 6750 } 6751 #else 6752 if (dip) 6753 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6754 instance, buf); 6755 else 6756 cmn_err(ce, qmark ? "?%s" : buf, buf); 6757 #endif 6758 } 6759 } 6760