1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_mac.h> 30 31 static void nxge_get_niu_property(dev_info_t *, niu_type_t *); 32 static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t); 33 static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t); 34 static void nxge_use_cfg_neptune_properties(p_nxge_t); 35 static void nxge_use_cfg_dma_config(p_nxge_t); 36 static void nxge_use_cfg_vlan_class_config(p_nxge_t); 37 static void nxge_use_cfg_mac_class_config(p_nxge_t); 38 static void nxge_use_cfg_class_config(p_nxge_t); 39 static void nxge_use_cfg_link_cfg(p_nxge_t); 40 static void nxge_set_hw_dma_config(p_nxge_t); 41 static void nxge_set_hw_vlan_class_config(p_nxge_t); 42 static void nxge_set_hw_mac_class_config(p_nxge_t); 43 static void nxge_set_hw_class_config(p_nxge_t); 44 static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t); 45 static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t, 46 uint8_t, int *); 47 static void nxge_init_mmac(p_nxge_t, boolean_t); 48 49 uint32_t nxge_use_hw_property = 1; 50 uint32_t nxge_groups_per_port = 2; 51 52 extern uint32_t nxge_use_partition; 53 extern uint32_t nxge_dma_obp_props_only; 54 55 extern uint16_t nxge_rcr_timeout; 56 extern uint16_t nxge_rcr_threshold; 57 58 extern uint_t nxge_rx_intr(void *, void *); 59 extern uint_t nxge_tx_intr(void *, void *); 60 extern uint_t nxge_mif_intr(void *, void *); 61 extern uint_t nxge_mac_intr(void *, void *); 62 extern uint_t nxge_syserr_intr(void *, void *); 63 extern void *nxge_list; 64 65 #define NXGE_SHARED_REG_SW_SIM 66 67 #ifdef NXGE_SHARED_REG_SW_SIM 68 uint64_t global_dev_ctrl = 0; 69 #endif 70 71 #define MAX_SIBLINGS NXGE_MAX_PORTS 72 73 extern uint32_t nxge_rbr_size; 74 extern uint32_t nxge_rcr_size; 75 extern uint32_t nxge_tx_ring_size; 76 extern uint32_t nxge_rbr_spare_size; 77 78 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 79 80 static uint8_t p2_tx_fair[2] = {12, 12}; 81 static uint8_t p2_tx_equal[2] = {12, 12}; 82 static uint8_t p4_tx_fair[4] = {6, 6, 6, 6}; 83 static uint8_t p4_tx_equal[4] = {6, 6, 6, 6}; 84 static uint8_t p2_rx_fair[2] = {8, 8}; 85 static uint8_t p2_rx_equal[2] = {8, 8}; 86 static uint8_t p4_rx_fair[4] = {4, 4, 4, 4}; 87 static uint8_t p4_rx_equal[4] = {4, 4, 4, 4}; 88 89 static uint8_t p2_rdcgrp_fair[2] = {4, 4}; 90 static uint8_t p2_rdcgrp_equal[2] = {4, 4}; 91 static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1}; 92 static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2}; 93 static uint8_t p2_rdcgrp_cls[2] = {1, 1}; 94 static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1}; 95 96 static uint8_t rx_4_1G[4] = {4, 4, 4, 4}; 97 static uint8_t rx_2_10G[2] = {8, 8}; 98 static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2}; 99 static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2}; 100 static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2}; 101 102 static uint8_t tx_4_1G[4] = {6, 6, 6, 6}; 103 static uint8_t tx_2_10G[2] = {12, 12}; 104 static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2}; 105 static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4}; 106 static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4}; 107 108 typedef enum { 109 DEFAULT = 0, 110 EQUAL, 111 FAIR, 112 CUSTOM, 113 CLASSIFY, 114 L2_CLASSIFY, 115 L3_DISTRIBUTE, 116 L3_CLASSIFY, 117 L3_TCAM, 118 CONFIG_TOKEN_NONE 119 } config_token_t; 120 121 static char *token_names[] = { 122 "default", 123 "equal", 124 "fair", 125 "custom", 126 "classify", 127 "l2_classify", 128 "l3_distribute", 129 "l3_classify", 130 "l3_tcam", 131 "none", 132 }; 133 134 void nxge_virint_regs_dump(p_nxge_t nxgep); 135 136 void 137 nxge_virint_regs_dump(p_nxge_t nxgep) 138 { 139 npi_handle_t handle; 140 141 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump")); 142 handle = NXGE_DEV_NPI_HANDLE(nxgep); 143 (void) npi_vir_dump_pio_fzc_regs_one(handle); 144 (void) npi_vir_dump_ldgnum(handle); 145 (void) npi_vir_dump_ldsv(handle); 146 (void) npi_vir_dump_imask0(handle); 147 (void) npi_vir_dump_sid(handle); 148 (void) npi_mac_dump_regs(handle, nxgep->function_num); 149 (void) npi_ipp_dump_regs(handle, nxgep->function_num); 150 (void) npi_fflp_dump_regs(handle); 151 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump")); 152 } 153 154 /* 155 * For now: we hard coded the DMA configurations. 156 * and assume for one partition only. 157 * 158 * OBP. Then OBP will pass this partition's 159 * Neptune configurations to fcode to create 160 * properties for them. 161 * 162 * Since Neptune(PCI-E) and NIU (Niagara-2) has 163 * different bus interfaces, the driver needs 164 * to know which bus it is connected to. 165 * Ravinder suggested: create a device property. 166 * In partitioning environment, we cannot 167 * use .conf file (need to check). If conf changes, 168 * need to reboot the system. 169 * The following function assumes that we will 170 * retrieve its properties from a virtualized nexus driver. 171 */ 172 173 nxge_status_t 174 nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result) 175 { 176 nxge_status_t status = NXGE_OK; 177 int instance; 178 p_nxge_t nxgep; 179 180 #ifndef NXGE_SHARED_REG_SW_SIM 181 npi_handle_t handle; 182 uint16_t sr16, cr16; 183 #endif 184 instance = ddi_get_instance(dip); 185 NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance)); 186 187 if (nxge_list == NULL) { 188 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 189 "nxge_cntlops: nxge_list null")); 190 return (NXGE_ERROR); 191 } 192 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 193 if (nxgep == NULL) { 194 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 195 "nxge_cntlops: nxgep null")); 196 return (NXGE_ERROR); 197 } 198 #ifndef NXGE_SHARED_REG_SW_SIM 199 handle = nxgep->npi_reg_handle; 200 #endif 201 switch (ctlop) { 202 case NXGE_CTLOPS_NIUTYPE: 203 nxge_get_niu_property(dip, (niu_type_t *)result); 204 return (status); 205 206 case NXGE_CTLOPS_GET_SHARED_REG: 207 #ifdef NXGE_SHARED_REG_SW_SIM 208 *(uint64_t *)result = global_dev_ctrl; 209 return (0); 210 #else 211 status = npi_dev_func_sr_sr_get(handle, &sr16); 212 *(uint16_t *)result = sr16; 213 NXGE_DEBUG_MSG((NULL, VIR_CTL, 214 "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG")); 215 return (0); 216 #endif 217 218 case NXGE_CTLOPS_SET_SHARED_REG_LOCK: 219 #ifdef NXGE_SHARED_REG_SW_SIM 220 global_dev_ctrl = *(uint64_t *)arg; 221 return (0); 222 #else 223 status = NPI_FAILURE; 224 while (status != NPI_SUCCESS) 225 status = npi_dev_func_sr_lock_enter(handle); 226 227 sr16 = *(uint16_t *)arg; 228 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 229 status = npi_dev_func_sr_lock_free(handle); 230 NXGE_DEBUG_MSG((NULL, VIR_CTL, 231 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 232 return (0); 233 #endif 234 235 case NXGE_CTLOPS_UPDATE_SHARED_REG: 236 #ifdef NXGE_SHARED_REG_SW_SIM 237 global_dev_ctrl |= *(uint64_t *)arg; 238 return (0); 239 #else 240 status = NPI_FAILURE; 241 while (status != NPI_SUCCESS) 242 status = npi_dev_func_sr_lock_enter(handle); 243 status = npi_dev_func_sr_sr_get(handle, &sr16); 244 sr16 |= *(uint16_t *)arg; 245 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 246 status = npi_dev_func_sr_lock_free(handle); 247 NXGE_DEBUG_MSG((NULL, VIR_CTL, 248 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 249 return (0); 250 #endif 251 252 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL: 253 #ifdef NXGE_SHARED_REG_SW_SIM 254 global_dev_ctrl |= *(uint64_t *)arg; 255 return (0); 256 #else 257 status = npi_dev_func_sr_sr_get(handle, &sr16); 258 cr16 = *(uint16_t *)arg; 259 sr16 &= ~cr16; 260 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 261 NXGE_DEBUG_MSG((NULL, VIR_CTL, 262 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 263 return (0); 264 #endif 265 266 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG: 267 #ifdef NXGE_SHARED_REG_SW_SIM 268 global_dev_ctrl |= *(uint64_t *)arg; 269 return (0); 270 #else 271 status = NPI_FAILURE; 272 while (status != NPI_SUCCESS) 273 status = npi_dev_func_sr_lock_enter(handle); 274 status = npi_dev_func_sr_sr_get(handle, &sr16); 275 cr16 = *(uint16_t *)arg; 276 sr16 &= ~cr16; 277 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 278 status = npi_dev_func_sr_lock_free(handle); 279 NXGE_DEBUG_MSG((NULL, VIR_CTL, 280 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 281 return (0); 282 #endif 283 284 case NXGE_CTLOPS_GET_LOCK_BLOCK: 285 #ifdef NXGE_SHARED_REG_SW_SIM 286 global_dev_ctrl |= *(uint64_t *)arg; 287 return (0); 288 #else 289 status = NPI_FAILURE; 290 while (status != NPI_SUCCESS) 291 status = npi_dev_func_sr_lock_enter(handle); 292 NXGE_DEBUG_MSG((NULL, VIR_CTL, 293 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK")); 294 return (0); 295 #endif 296 case NXGE_CTLOPS_GET_LOCK_TRY: 297 #ifdef NXGE_SHARED_REG_SW_SIM 298 global_dev_ctrl |= *(uint64_t *)arg; 299 return (0); 300 #else 301 status = npi_dev_func_sr_lock_enter(handle); 302 NXGE_DEBUG_MSG((NULL, VIR_CTL, 303 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY")); 304 if (status == NPI_SUCCESS) 305 return (NXGE_OK); 306 else 307 return (NXGE_ERROR); 308 #endif 309 case NXGE_CTLOPS_FREE_LOCK: 310 #ifdef NXGE_SHARED_REG_SW_SIM 311 global_dev_ctrl |= *(uint64_t *)arg; 312 return (0); 313 #else 314 status = npi_dev_func_sr_lock_free(handle); 315 NXGE_DEBUG_MSG((NULL, VIR_CTL, 316 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE")); 317 if (status == NPI_SUCCESS) 318 return (NXGE_OK); 319 else 320 return (NXGE_ERROR); 321 #endif 322 323 default: 324 status = NXGE_ERROR; 325 } 326 327 return (status); 328 } 329 330 void 331 nxge_common_lock_get(p_nxge_t nxgep) 332 { 333 uint32_t status = NPI_FAILURE; 334 npi_handle_t handle; 335 336 #if defined(NXGE_SHARE_REG_SW_SIM) 337 return; 338 #endif 339 handle = nxgep->npi_reg_handle; 340 while (status != NPI_SUCCESS) 341 status = npi_dev_func_sr_lock_enter(handle); 342 } 343 344 void 345 nxge_common_lock_free(p_nxge_t nxgep) 346 { 347 npi_handle_t handle; 348 349 #if defined(NXGE_SHARE_REG_SW_SIM) 350 return; 351 #endif 352 handle = nxgep->npi_reg_handle; 353 (void) npi_dev_func_sr_lock_free(handle); 354 } 355 356 357 static void 358 nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type) 359 { 360 uchar_t *prop_val; 361 uint_t prop_len; 362 363 *niu_type = NIU_TYPE_NONE; 364 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, 365 "niu-type", (uchar_t **)&prop_val, 366 &prop_len) == DDI_PROP_SUCCESS) { 367 if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) { 368 *niu_type = N2_NIU; 369 } 370 ddi_prop_free(prop_val); 371 } 372 } 373 374 static config_token_t 375 nxge_get_config_token(char *prop) 376 { 377 config_token_t token = DEFAULT; 378 379 while (token < CONFIG_TOKEN_NONE) { 380 if (strncmp(prop, token_names[token], 4) == 0) 381 break; 382 token++; 383 } 384 return (token); 385 } 386 387 /* per port */ 388 389 static nxge_status_t 390 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token, 391 dev_info_t *s_dip[]) 392 { 393 nxge_status_t status = NXGE_OK; 394 int ddi_status; 395 int num_ports = nxgep->nports; 396 int port, bits, j; 397 uint8_t start_grp = 0, num_grps = 0; 398 p_nxge_param_t param_arr; 399 uint32_t grp_bitmap[MAX_SIBLINGS]; 400 int custom_start_grp[MAX_SIBLINGS]; 401 int custom_num_grp[MAX_SIBLINGS]; 402 uint8_t bad_config = B_FALSE; 403 char *start_prop, *num_prop, *cfg_prop; 404 405 start_grp = 0; 406 param_arr = nxgep->param_arr; 407 start_prop = param_arr[param_rdc_grps_start].fcode_name; 408 num_prop = param_arr[param_rx_rdc_grps].fcode_name; 409 410 switch (token) { 411 case FAIR: 412 cfg_prop = "fair"; 413 for (port = 0; port < num_ports; port++) { 414 custom_num_grp[port] = 415 (num_ports == 4) ? 416 p4_rdcgrp_fair[port] : 417 p2_rdcgrp_fair[port]; 418 custom_start_grp[port] = start_grp; 419 start_grp += custom_num_grp[port]; 420 } 421 break; 422 423 case EQUAL: 424 cfg_prop = "equal"; 425 for (port = 0; port < num_ports; port++) { 426 custom_num_grp[port] = 427 (num_ports == 4) ? 428 p4_rdcgrp_equal[port] : 429 p2_rdcgrp_equal[port]; 430 custom_start_grp[port] = start_grp; 431 start_grp += custom_num_grp[port]; 432 } 433 break; 434 435 436 case CLASSIFY: 437 cfg_prop = "classify"; 438 for (port = 0; port < num_ports; port++) { 439 custom_num_grp[port] = (num_ports == 4) ? 440 p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port]; 441 custom_start_grp[port] = start_grp; 442 start_grp += custom_num_grp[port]; 443 } 444 break; 445 446 case CUSTOM: 447 cfg_prop = "custom"; 448 /* See if it is good config */ 449 num_grps = 0; 450 for (port = 0; port < num_ports; port++) { 451 custom_start_grp[port] = 452 ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port], 453 DDI_PROP_DONTPASS, start_prop, -1); 454 if ((custom_start_grp[port] == -1) || 455 (custom_start_grp[port] >= 456 NXGE_MAX_RDC_GRPS)) { 457 bad_config = B_TRUE; 458 break; 459 } 460 custom_num_grp[port] = ddi_prop_get_int( 461 DDI_DEV_T_NONE, 462 s_dip[port], 463 DDI_PROP_DONTPASS, 464 num_prop, -1); 465 466 if ((custom_num_grp[port] == -1) || 467 (custom_num_grp[port] > 468 NXGE_MAX_RDC_GRPS) || 469 ((custom_num_grp[port] + 470 custom_start_grp[port]) >= 471 NXGE_MAX_RDC_GRPS)) { 472 bad_config = B_TRUE; 473 break; 474 } 475 num_grps += custom_num_grp[port]; 476 if (num_grps > NXGE_MAX_RDC_GRPS) { 477 bad_config = B_TRUE; 478 break; 479 } 480 grp_bitmap[port] = 0; 481 for (bits = 0; 482 bits < custom_num_grp[port]; 483 bits++) { 484 grp_bitmap[port] |= 485 (1 << (bits + custom_start_grp[port])); 486 } 487 488 } 489 490 if (bad_config == B_FALSE) { 491 /* check for overlap */ 492 for (port = 0; port < num_ports - 1; port++) { 493 for (j = port + 1; j < num_ports; j++) { 494 if (grp_bitmap[port] & 495 grp_bitmap[j]) { 496 bad_config = B_TRUE; 497 break; 498 } 499 } 500 if (bad_config == B_TRUE) 501 break; 502 } 503 } 504 if (bad_config == B_TRUE) { 505 /* use default config */ 506 for (port = 0; port < num_ports; port++) { 507 custom_num_grp[port] = 508 (num_ports == 4) ? 509 p4_rx_fair[port] : p2_rx_fair[port]; 510 custom_start_grp[port] = start_grp; 511 start_grp += custom_num_grp[port]; 512 } 513 } 514 break; 515 516 default: 517 /* use default config */ 518 cfg_prop = "fair"; 519 for (port = 0; port < num_ports; port++) { 520 custom_num_grp[port] = (num_ports == 4) ? 521 p4_rx_fair[port] : p2_rx_fair[port]; 522 custom_start_grp[port] = start_grp; 523 start_grp += custom_num_grp[port]; 524 } 525 break; 526 } 527 528 /* Now Update the rx properties */ 529 for (port = 0; port < num_ports; port++) { 530 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 531 "rxdma-grp-cfg", cfg_prop); 532 if (ddi_status != DDI_PROP_SUCCESS) { 533 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 534 " property %s not updating", 535 cfg_prop)); 536 status |= NXGE_DDI_FAILED; 537 } 538 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 539 num_prop, custom_num_grp[port]); 540 541 if (ddi_status != DDI_PROP_SUCCESS) { 542 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 543 " property %s not updating", 544 num_prop)); 545 status |= NXGE_DDI_FAILED; 546 } 547 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 548 start_prop, custom_start_grp[port]); 549 550 if (ddi_status != DDI_PROP_SUCCESS) { 551 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 552 " property %s not updating", 553 start_prop)); 554 status |= NXGE_DDI_FAILED; 555 } 556 } 557 if (status & NXGE_DDI_FAILED) 558 status |= NXGE_ERROR; 559 560 return (status); 561 } 562 563 static nxge_status_t 564 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token, 565 dev_info_t *s_dip[]) 566 { 567 nxge_status_t status = NXGE_OK; 568 int ddi_status; 569 int num_ports = nxgep->nports; 570 int port, bits, j; 571 uint8_t start_rdc = 0, num_rdc = 0; 572 p_nxge_param_t param_arr; 573 uint32_t rdc_bitmap[MAX_SIBLINGS]; 574 int custom_start_rdc[MAX_SIBLINGS]; 575 int custom_num_rdc[MAX_SIBLINGS]; 576 uint8_t bad_config = B_FALSE; 577 int *prop_val; 578 uint_t prop_len; 579 char *start_rdc_prop, *num_rdc_prop, *cfg_prop; 580 581 start_rdc = 0; 582 param_arr = nxgep->param_arr; 583 start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name; 584 num_rdc_prop = param_arr[param_rxdma_channels].fcode_name; 585 586 switch (token) { 587 case FAIR: 588 cfg_prop = "fair"; 589 for (port = 0; port < num_ports; port++) { 590 custom_num_rdc[port] = (num_ports == 4) ? 591 p4_rx_fair[port] : p2_rx_fair[port]; 592 custom_start_rdc[port] = start_rdc; 593 start_rdc += custom_num_rdc[port]; 594 } 595 break; 596 597 case EQUAL: 598 cfg_prop = "equal"; 599 for (port = 0; port < num_ports; port++) { 600 custom_num_rdc[port] = (num_ports == 4) ? 601 p4_rx_equal[port] : 602 p2_rx_equal[port]; 603 custom_start_rdc[port] = start_rdc; 604 start_rdc += custom_num_rdc[port]; 605 } 606 break; 607 608 case CUSTOM: 609 cfg_prop = "custom"; 610 /* See if it is good config */ 611 num_rdc = 0; 612 for (port = 0; port < num_ports; port++) { 613 ddi_status = ddi_prop_lookup_int_array( 614 DDI_DEV_T_ANY, 615 s_dip[port], 0, 616 start_rdc_prop, 617 &prop_val, 618 &prop_len); 619 if (ddi_status == DDI_SUCCESS) 620 custom_start_rdc[port] = *prop_val; 621 else { 622 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 623 " %s custom start port %d" 624 " read failed ", 625 " rxdma-cfg", port)); 626 bad_config = B_TRUE; 627 status |= NXGE_DDI_FAILED; 628 } 629 if ((custom_start_rdc[port] == -1) || 630 (custom_start_rdc[port] >= 631 NXGE_MAX_RDCS)) { 632 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 633 " %s custom start %d" 634 " out of range %x ", 635 " rxdma-cfg", 636 port, 637 custom_start_rdc[port])); 638 bad_config = B_TRUE; 639 break; 640 } 641 ddi_status = ddi_prop_lookup_int_array( 642 DDI_DEV_T_ANY, 643 s_dip[port], 644 0, 645 num_rdc_prop, 646 &prop_val, 647 &prop_len); 648 649 if (ddi_status == DDI_SUCCESS) 650 custom_num_rdc[port] = *prop_val; 651 else { 652 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 653 " %s custom num port %d" 654 " read failed ", 655 "rxdma-cfg", port)); 656 bad_config = B_TRUE; 657 status |= NXGE_DDI_FAILED; 658 } 659 660 if ((custom_num_rdc[port] == -1) || 661 (custom_num_rdc[port] > 662 NXGE_MAX_RDCS) || 663 ((custom_num_rdc[port] + 664 custom_start_rdc[port]) > 665 NXGE_MAX_RDCS)) { 666 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 667 " %s custom num %d" 668 " out of range %x ", 669 " rxdma-cfg", 670 port, custom_num_rdc[port])); 671 bad_config = B_TRUE; 672 break; 673 } 674 num_rdc += custom_num_rdc[port]; 675 if (num_rdc > NXGE_MAX_RDCS) { 676 bad_config = B_TRUE; 677 break; 678 } 679 rdc_bitmap[port] = 0; 680 for (bits = 0; 681 bits < custom_num_rdc[port]; bits++) { 682 rdc_bitmap[port] |= 683 (1 << (bits + custom_start_rdc[port])); 684 } 685 } 686 687 if (bad_config == B_FALSE) { 688 /* check for overlap */ 689 for (port = 0; port < num_ports - 1; port++) { 690 for (j = port + 1; j < num_ports; j++) { 691 if (rdc_bitmap[port] & 692 rdc_bitmap[j]) { 693 NXGE_DEBUG_MSG((nxgep, 694 CFG_CTL, 695 " rxdma-cfg" 696 " property custom" 697 " bit overlap" 698 " %d %d ", 699 port, j)); 700 bad_config = B_TRUE; 701 break; 702 } 703 } 704 if (bad_config == B_TRUE) 705 break; 706 } 707 } 708 if (bad_config == B_TRUE) { 709 /* use default config */ 710 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 711 " rxdma-cfg property:" 712 " bad custom config:" 713 " use default")); 714 for (port = 0; port < num_ports; port++) { 715 custom_num_rdc[port] = 716 (num_ports == 4) ? 717 p4_rx_fair[port] : 718 p2_rx_fair[port]; 719 custom_start_rdc[port] = start_rdc; 720 start_rdc += custom_num_rdc[port]; 721 } 722 } 723 break; 724 725 default: 726 /* use default config */ 727 cfg_prop = "fair"; 728 for (port = 0; port < num_ports; port++) { 729 custom_num_rdc[port] = (num_ports == 4) ? 730 p4_rx_fair[port] : p2_rx_fair[port]; 731 custom_start_rdc[port] = start_rdc; 732 start_rdc += custom_num_rdc[port]; 733 } 734 break; 735 } 736 737 /* Now Update the rx properties */ 738 for (port = 0; port < num_ports; port++) { 739 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 740 " update property rxdma-cfg with %s ", cfg_prop)); 741 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 742 "rxdma-cfg", cfg_prop); 743 if (ddi_status != DDI_PROP_SUCCESS) { 744 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 745 " property rxdma-cfg is not updating to %s", 746 cfg_prop)); 747 status |= NXGE_DDI_FAILED; 748 } 749 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 750 num_rdc_prop, custom_num_rdc[port])); 751 752 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 753 num_rdc_prop, custom_num_rdc[port]); 754 755 if (ddi_status != DDI_PROP_SUCCESS) { 756 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 757 " property %s not updating with %d", 758 num_rdc_prop, custom_num_rdc[port])); 759 status |= NXGE_DDI_FAILED; 760 } 761 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 762 start_rdc_prop, custom_start_rdc[port])); 763 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 764 start_rdc_prop, custom_start_rdc[port]); 765 766 if (ddi_status != DDI_PROP_SUCCESS) { 767 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 768 " property %s not updating with %d ", 769 start_rdc_prop, custom_start_rdc[port])); 770 status |= NXGE_DDI_FAILED; 771 } 772 } 773 if (status & NXGE_DDI_FAILED) 774 status |= NXGE_ERROR; 775 return (status); 776 } 777 778 static nxge_status_t 779 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token, 780 dev_info_t *s_dip[]) 781 { 782 nxge_status_t status = NXGE_OK; 783 int ddi_status = DDI_SUCCESS; 784 int num_ports = nxgep->nports; 785 int port, bits, j; 786 uint8_t start_tdc = 0, num_tdc = 0; 787 p_nxge_param_t param_arr; 788 uint32_t tdc_bitmap[MAX_SIBLINGS]; 789 int custom_start_tdc[MAX_SIBLINGS]; 790 int custom_num_tdc[MAX_SIBLINGS]; 791 uint8_t bad_config = B_FALSE; 792 int *prop_val; 793 uint_t prop_len; 794 char *start_tdc_prop, *num_tdc_prop, *cfg_prop; 795 796 start_tdc = 0; 797 param_arr = nxgep->param_arr; 798 start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name; 799 num_tdc_prop = param_arr[param_txdma_channels].fcode_name; 800 801 switch (token) { 802 case FAIR: 803 cfg_prop = "fair"; 804 for (port = 0; port < num_ports; port++) { 805 custom_num_tdc[port] = (num_ports == 4) ? 806 p4_tx_fair[port] : p2_tx_fair[port]; 807 custom_start_tdc[port] = start_tdc; 808 start_tdc += custom_num_tdc[port]; 809 } 810 break; 811 812 case EQUAL: 813 cfg_prop = "equal"; 814 for (port = 0; port < num_ports; port++) { 815 custom_num_tdc[port] = (num_ports == 4) ? 816 p4_tx_equal[port] : p2_tx_equal[port]; 817 custom_start_tdc[port] = start_tdc; 818 start_tdc += custom_num_tdc[port]; 819 } 820 break; 821 822 case CUSTOM: 823 cfg_prop = "custom"; 824 /* See if it is good config */ 825 num_tdc = 0; 826 for (port = 0; port < num_ports; port++) { 827 ddi_status = ddi_prop_lookup_int_array( 828 DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop, 829 &prop_val, &prop_len); 830 if (ddi_status == DDI_SUCCESS) 831 custom_start_tdc[port] = *prop_val; 832 else { 833 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 834 " %s custom start port %d" 835 " read failed ", " txdma-cfg", port)); 836 bad_config = B_TRUE; 837 status |= NXGE_DDI_FAILED; 838 } 839 840 if ((custom_start_tdc[port] == -1) || 841 (custom_start_tdc[port] >= 842 NXGE_MAX_RDCS)) { 843 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 844 " %s custom start %d" 845 " out of range %x ", " txdma-cfg", 846 port, custom_start_tdc[port])); 847 bad_config = B_TRUE; 848 break; 849 } 850 851 ddi_status = ddi_prop_lookup_int_array( 852 DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop, 853 &prop_val, &prop_len); 854 if (ddi_status == DDI_SUCCESS) 855 custom_num_tdc[port] = *prop_val; 856 else { 857 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 858 " %s custom num port %d" 859 " read failed ", " txdma-cfg", port)); 860 bad_config = B_TRUE; 861 status |= NXGE_DDI_FAILED; 862 } 863 864 if ((custom_num_tdc[port] == -1) || 865 (custom_num_tdc[port] > 866 NXGE_MAX_TDCS) || 867 ((custom_num_tdc[port] + 868 custom_start_tdc[port]) > 869 NXGE_MAX_TDCS)) { 870 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 871 " %s custom num %d" 872 " out of range %x ", " rxdma-cfg", 873 port, custom_num_tdc[port])); 874 bad_config = B_TRUE; 875 break; 876 } 877 num_tdc += custom_num_tdc[port]; 878 if (num_tdc > NXGE_MAX_TDCS) { 879 bad_config = B_TRUE; 880 break; 881 } 882 tdc_bitmap[port] = 0; 883 for (bits = 0; 884 bits < custom_num_tdc[port]; bits++) { 885 tdc_bitmap[port] |= 886 (1 << 887 (bits + custom_start_tdc[port])); 888 } 889 890 } 891 892 if (bad_config == B_FALSE) { 893 /* check for overlap */ 894 for (port = 0; port < num_ports - 1; port++) { 895 for (j = port + 1; j < num_ports; j++) { 896 if (tdc_bitmap[port] & 897 tdc_bitmap[j]) { 898 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 899 " rxdma-cfg" 900 " property custom" 901 " bit overlap" 902 " %d %d ", 903 port, j)); 904 bad_config = B_TRUE; 905 break; 906 } 907 } 908 if (bad_config == B_TRUE) 909 break; 910 } 911 } 912 if (bad_config == B_TRUE) { 913 /* use default config */ 914 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 915 " txdma-cfg property:" 916 " bad custom config:" " use default")); 917 918 for (port = 0; port < num_ports; port++) { 919 custom_num_tdc[port] = (num_ports == 4) ? 920 p4_tx_fair[port] : p2_tx_fair[port]; 921 custom_start_tdc[port] = start_tdc; 922 start_tdc += custom_num_tdc[port]; 923 } 924 } 925 break; 926 927 default: 928 /* use default config */ 929 cfg_prop = "fair"; 930 for (port = 0; port < num_ports; port++) { 931 custom_num_tdc[port] = (num_ports == 4) ? 932 p4_tx_fair[port] : p2_tx_fair[port]; 933 custom_start_tdc[port] = start_tdc; 934 start_tdc += custom_num_tdc[port]; 935 } 936 break; 937 } 938 939 /* Now Update the tx properties */ 940 for (port = 0; port < num_ports; port++) { 941 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 942 " update property txdma-cfg with %s ", cfg_prop)); 943 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 944 "txdma-cfg", cfg_prop); 945 if (ddi_status != DDI_PROP_SUCCESS) { 946 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 947 " property txdma-cfg is not updating to %s", 948 cfg_prop)); 949 status |= NXGE_DDI_FAILED; 950 } 951 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 952 num_tdc_prop, custom_num_tdc[port])); 953 954 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 955 num_tdc_prop, custom_num_tdc[port]); 956 957 if (ddi_status != DDI_PROP_SUCCESS) { 958 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 959 " property %s not updating with %d", 960 num_tdc_prop, 961 custom_num_tdc[port])); 962 status |= NXGE_DDI_FAILED; 963 } 964 965 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 966 start_tdc_prop, custom_start_tdc[port])); 967 968 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 969 start_tdc_prop, custom_start_tdc[port]); 970 if (ddi_status != DDI_PROP_SUCCESS) { 971 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 972 " property %s not updating with %d ", 973 start_tdc_prop, custom_start_tdc[port])); 974 status |= NXGE_DDI_FAILED; 975 } 976 } 977 if (status & NXGE_DDI_FAILED) 978 status |= NXGE_ERROR; 979 return (status); 980 } 981 982 static nxge_status_t 983 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags, 984 config_token_t token, dev_info_t *s_dip[]) 985 { 986 nxge_status_t status = NXGE_OK; 987 988 switch (flags) { 989 case COMMON_TXDMA_CFG: 990 if (nxge_dma_obp_props_only == 0) 991 status = nxge_update_txdma_properties(nxgep, 992 token, s_dip); 993 break; 994 case COMMON_RXDMA_CFG: 995 if (nxge_dma_obp_props_only == 0) 996 status = nxge_update_rxdma_properties(nxgep, 997 token, s_dip); 998 999 break; 1000 case COMMON_RXDMA_GRP_CFG: 1001 status = nxge_update_rxdma_grp_properties(nxgep, 1002 token, s_dip); 1003 break; 1004 default: 1005 return (NXGE_ERROR); 1006 } 1007 return (status); 1008 } 1009 1010 /* 1011 * verify consistence. 1012 * (May require publishing the properties on all the ports. 1013 * 1014 * What if properties are published on function 0 device only? 1015 * 1016 * 1017 * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required ) 1018 * What about class configs? 1019 * 1020 * If consistent, update the property on all the siblings. 1021 * set a flag on hardware shared register 1022 * The rest of the siblings will check the flag 1023 * if the flag is set, they will use the updated property 1024 * without doing any validation. 1025 */ 1026 1027 nxge_status_t 1028 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop, 1029 uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[]) 1030 { 1031 nxge_status_t status = NXGE_OK; 1032 int ddi_status = DDI_SUCCESS; 1033 int i = 0, found = 0, update_prop = B_TRUE; 1034 int *cfg_val; 1035 uint_t new_value, cfg_value[MAX_SIBLINGS]; 1036 uint_t prop_len; 1037 uint_t known_cfg_value; 1038 1039 known_cfg_value = (uint_t)known_cfg; 1040 1041 if (override == B_TRUE) { 1042 new_value = known_cfg_value; 1043 for (i = 0; i < nxgep->nports; i++) { 1044 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1045 c_dip[i], prop, new_value); 1046 #ifdef NXGE_DEBUG_ERROR 1047 if (ddi_status != DDI_PROP_SUCCESS) 1048 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1049 " property %s failed update ", prop)); 1050 #endif 1051 } 1052 if (ddi_status != DDI_PROP_SUCCESS) 1053 return (NXGE_ERROR | NXGE_DDI_FAILED); 1054 } 1055 for (i = 0; i < nxgep->nports; i++) { 1056 cfg_value[i] = known_cfg_value; 1057 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0, 1058 prop, &cfg_val, 1059 &prop_len) == DDI_PROP_SUCCESS) { 1060 cfg_value[i] = *cfg_val; 1061 ddi_prop_free(cfg_val); 1062 found++; 1063 } 1064 } 1065 1066 if (found != i) { 1067 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1068 " property %s not specified on all ports", prop)); 1069 if (found == 0) { 1070 /* not specified: Use default */ 1071 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1072 " property %s not specified on any port:" 1073 " Using default", prop)); 1074 new_value = known_cfg_value; 1075 } else { 1076 /* specified on some */ 1077 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1078 " property %s not specified" 1079 " on some ports: Using default", prop)); 1080 /* ? use p0 value instead ? */ 1081 new_value = known_cfg_value; 1082 } 1083 } else { 1084 /* check type and consistence */ 1085 /* found on all devices */ 1086 for (i = 1; i < found; i++) { 1087 if (cfg_value[i] != cfg_value[i - 1]) { 1088 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1089 " property %s inconsistent:" 1090 " Using default", prop)); 1091 new_value = known_cfg_value; 1092 break; 1093 } 1094 /* 1095 * Found on all the ports and consistent. Nothing to 1096 * do. 1097 */ 1098 update_prop = B_FALSE; 1099 } 1100 } 1101 1102 if (update_prop == B_TRUE) { 1103 for (i = 0; i < nxgep->nports; i++) { 1104 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1105 c_dip[i], prop, new_value); 1106 #ifdef NXGE_DEBUG_ERROR 1107 if (ddi_status != DDI_SUCCESS) 1108 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1109 " property %s not updating with %d" 1110 " Using default", 1111 prop, new_value)); 1112 #endif 1113 if (ddi_status != DDI_PROP_SUCCESS) 1114 status |= NXGE_DDI_FAILED; 1115 } 1116 } 1117 if (status & NXGE_DDI_FAILED) 1118 status |= NXGE_ERROR; 1119 1120 return (status); 1121 } 1122 1123 static uint64_t 1124 nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg) 1125 { 1126 int start_prop; 1127 uint64_t cfg_value; 1128 p_nxge_param_t param_arr; 1129 1130 param_arr = nxgep->param_arr; 1131 cfg_value = param_arr[class_prop].value; 1132 start_prop = param_h1_init_value; 1133 1134 /* update the properties per quick config */ 1135 switch (rx_quick_cfg) { 1136 case CFG_L3_WEB: 1137 case CFG_L3_DISTRIBUTE: 1138 cfg_value = nxge_classify_get_cfg_value(nxgep, 1139 rx_quick_cfg, class_prop - start_prop); 1140 break; 1141 default: 1142 cfg_value = param_arr[class_prop].value; 1143 break; 1144 } 1145 return (cfg_value); 1146 } 1147 1148 static nxge_status_t 1149 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[]) 1150 { 1151 nxge_status_t status = NXGE_OK; 1152 int rx_quick_cfg, class_prop, start_prop, end_prop; 1153 char *prop_name; 1154 int override = B_TRUE; 1155 uint64_t cfg_value; 1156 p_nxge_param_t param_arr; 1157 1158 param_arr = nxgep->param_arr; 1159 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 1160 start_prop = param_h1_init_value; 1161 end_prop = param_class_opt_ipv6_sctp; 1162 1163 /* update the properties per quick config */ 1164 if (rx_quick_cfg == CFG_NOT_SPECIFIED) 1165 override = B_FALSE; 1166 1167 /* 1168 * these parameter affect the classification outcome. 1169 * these parameters are used to configure the Flow key and 1170 * the TCAM key for each of the IP classes. 1171 * Included here are also the H1 and H2 initial values 1172 * which affect the distribution as well as final hash value 1173 * (hence the offset into RDC table and FCRAM bucket location) 1174 * 1175 */ 1176 for (class_prop = start_prop; class_prop <= end_prop; class_prop++) { 1177 prop_name = param_arr[class_prop].fcode_name; 1178 cfg_value = nxge_class_get_known_cfg(nxgep, 1179 class_prop, rx_quick_cfg); 1180 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1181 cfg_value, override, c_dip); 1182 } 1183 1184 /* 1185 * these properties do not affect the actual classification outcome. 1186 * used to enable/disable or tune the fflp hardware 1187 * 1188 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable 1189 * 1190 */ 1191 override = B_FALSE; 1192 for (class_prop = param_fcram_access_ratio; 1193 class_prop <= param_llc_snap_enable; class_prop++) { 1194 prop_name = param_arr[class_prop].fcode_name; 1195 cfg_value = param_arr[class_prop].value; 1196 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1197 cfg_value, override, c_dip); 1198 } 1199 1200 return (status); 1201 } 1202 1203 nxge_status_t 1204 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag) 1205 { 1206 nxge_status_t status = NXGE_OK; 1207 int i = 0, found = 0; 1208 int num_siblings; 1209 dev_info_t *c_dip[MAX_SIBLINGS + 1]; 1210 char *prop_val[MAX_SIBLINGS]; 1211 config_token_t c_token[MAX_SIBLINGS]; 1212 char *prop; 1213 1214 if (nxge_dma_obp_props_only) 1215 return (NXGE_OK); 1216 1217 num_siblings = 0; 1218 c_dip[num_siblings] = ddi_get_child(nxgep->p_dip); 1219 while (c_dip[num_siblings]) { 1220 c_dip[num_siblings + 1] = 1221 ddi_get_next_sibling(c_dip[num_siblings]); 1222 num_siblings++; 1223 } 1224 1225 switch (flag) { 1226 case COMMON_TXDMA_CFG: 1227 prop = "txdma-cfg"; 1228 break; 1229 case COMMON_RXDMA_CFG: 1230 prop = "rxdma-cfg"; 1231 break; 1232 case COMMON_RXDMA_GRP_CFG: 1233 prop = "rxdma-grp-cfg"; 1234 break; 1235 case COMMON_CLASS_CFG: 1236 status = nxge_cfg_verify_set_classify(nxgep, c_dip); 1237 return (status); 1238 default: 1239 return (NXGE_ERROR); 1240 } 1241 1242 i = 0; 1243 while (i < num_siblings) { 1244 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop, 1245 (char **)&prop_val[i]) == DDI_PROP_SUCCESS) { 1246 c_token[i] = nxge_get_config_token(prop_val[i]); 1247 ddi_prop_free(prop_val[i]); 1248 found++; 1249 } else 1250 c_token[i] = CONFIG_TOKEN_NONE; 1251 i++; 1252 } 1253 1254 if (found != i) { 1255 if (found == 0) { 1256 /* not specified: Use default */ 1257 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1258 " property %s not specified on any port:" 1259 " Using default", prop)); 1260 1261 status = nxge_update_cfg_properties(nxgep, 1262 flag, FAIR, c_dip); 1263 return (status); 1264 } else { 1265 /* 1266 * if the convention is to use function 0 device then 1267 * populate the other devices with this configuration. 1268 * 1269 * The other alternative is to use the default config. 1270 */ 1271 /* not specified: Use default */ 1272 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1273 " property %s not specified on some ports:" 1274 " Using default", prop)); 1275 status = nxge_update_cfg_properties(nxgep, 1276 flag, FAIR, c_dip); 1277 return (status); 1278 } 1279 } 1280 1281 /* check type and consistence */ 1282 /* found on all devices */ 1283 for (i = 1; i < found; i++) { 1284 if (c_token[i] != c_token[i - 1]) { 1285 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1286 " property %s inconsistent:" 1287 " Using default", prop)); 1288 status = nxge_update_cfg_properties(nxgep, 1289 flag, FAIR, c_dip); 1290 return (status); 1291 } 1292 } 1293 1294 /* 1295 * Found on all the ports check if it is custom configuration. if 1296 * custom, then verify consistence 1297 * 1298 * finally create soft properties 1299 */ 1300 status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip); 1301 return (status); 1302 } 1303 1304 nxge_status_t 1305 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep) 1306 { 1307 nxge_status_t status = NXGE_OK; 1308 int ddi_status = DDI_SUCCESS; 1309 char *prop_val; 1310 char *rx_prop; 1311 char *prop; 1312 uint32_t cfg_value = CFG_NOT_SPECIFIED; 1313 p_nxge_param_t param_arr; 1314 1315 param_arr = nxgep->param_arr; 1316 rx_prop = param_arr[param_rx_quick_cfg].fcode_name; 1317 1318 prop = "rx-quick-cfg"; 1319 1320 /* 1321 * good value are 1322 * 1323 * "web-server" "generic-server" "l3-classify" "flow-classify" 1324 */ 1325 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0, 1326 prop, (char **)&prop_val) != DDI_PROP_SUCCESS) { 1327 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1328 " property %s not specified: using default ", prop)); 1329 cfg_value = CFG_NOT_SPECIFIED; 1330 } else { 1331 cfg_value = CFG_L3_DISTRIBUTE; 1332 if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) { 1333 cfg_value = CFG_L3_WEB; 1334 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1335 " %s: web server ", prop)); 1336 } 1337 if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) { 1338 cfg_value = CFG_L3_DISTRIBUTE; 1339 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1340 " %s: distribute ", prop)); 1341 } 1342 /* more */ 1343 ddi_prop_free(prop_val); 1344 } 1345 1346 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1347 rx_prop, cfg_value); 1348 if (ddi_status != DDI_PROP_SUCCESS) 1349 status |= NXGE_DDI_FAILED; 1350 1351 /* now handle specified cases: */ 1352 if (status & NXGE_DDI_FAILED) 1353 status |= NXGE_ERROR; 1354 return (status); 1355 } 1356 1357 static void 1358 nxge_use_cfg_link_cfg(p_nxge_t nxgep) 1359 { 1360 int *prop_val; 1361 uint_t prop_len; 1362 dev_info_t *dip; 1363 int speed; 1364 int duplex; 1365 int adv_autoneg_cap; 1366 int adv_10gfdx_cap; 1367 int adv_10ghdx_cap; 1368 int adv_1000fdx_cap; 1369 int adv_1000hdx_cap; 1370 int adv_100fdx_cap; 1371 int adv_100hdx_cap; 1372 int adv_10fdx_cap; 1373 int adv_10hdx_cap; 1374 int status = DDI_SUCCESS; 1375 1376 dip = nxgep->dip; 1377 1378 /* 1379 * first find out the card type and the supported link speeds and 1380 * features 1381 */ 1382 /* add code for card type */ 1383 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap", 1384 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1385 ddi_prop_free(prop_val); 1386 return; 1387 } 1388 1389 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap", 1390 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1391 ddi_prop_free(prop_val); 1392 return; 1393 } 1394 1395 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap", 1396 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1397 ddi_prop_free(prop_val); 1398 return; 1399 } 1400 1401 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap", 1402 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1403 ddi_prop_free(prop_val); 1404 return; 1405 } 1406 1407 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap", 1408 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1409 ddi_prop_free(prop_val); 1410 return; 1411 } 1412 1413 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap", 1414 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1415 ddi_prop_free(prop_val); 1416 return; 1417 } 1418 1419 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap", 1420 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1421 ddi_prop_free(prop_val); 1422 return; 1423 } 1424 1425 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap", 1426 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1427 ddi_prop_free(prop_val); 1428 return; 1429 } 1430 1431 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed", 1432 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1433 if (strncmp("10000", (caddr_t)prop_val, 1434 (size_t)prop_len) == 0) { 1435 speed = 10000; 1436 } else if (strncmp("1000", (caddr_t)prop_val, 1437 (size_t)prop_len) == 0) { 1438 speed = 1000; 1439 } else if (strncmp("100", (caddr_t)prop_val, 1440 (size_t)prop_len) == 0) { 1441 speed = 100; 1442 } else if (strncmp("10", (caddr_t)prop_val, 1443 (size_t)prop_len) == 0) { 1444 speed = 10; 1445 } else if (strncmp("auto", (caddr_t)prop_val, 1446 (size_t)prop_len) == 0) { 1447 speed = 0; 1448 } else { 1449 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1450 "speed property is invalid reverting to auto")); 1451 speed = 0; 1452 } 1453 ddi_prop_free(prop_val); 1454 } else 1455 speed = 0; 1456 1457 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex", 1458 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1459 if (strncmp("full", (caddr_t)prop_val, 1460 (size_t)prop_len) == 0) { 1461 duplex = 2; 1462 } else if (strncmp("half", (caddr_t)prop_val, 1463 (size_t)prop_len) == 0) { 1464 duplex = 1; 1465 } else if (strncmp("auto", (caddr_t)prop_val, 1466 (size_t)prop_len) == 0) { 1467 duplex = 0; 1468 } else { 1469 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1470 "duplex property is invalid" 1471 " reverting to auto")); 1472 duplex = 0; 1473 } 1474 ddi_prop_free(prop_val); 1475 } else 1476 duplex = 0; 1477 1478 adv_autoneg_cap = (speed == 0) || (duplex == 0); 1479 if (adv_autoneg_cap == 0) { 1480 adv_10gfdx_cap = ((speed == 10000) && (duplex == 2)); 1481 adv_10ghdx_cap = adv_10gfdx_cap; 1482 adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1)); 1483 adv_1000fdx_cap = adv_10ghdx_cap; 1484 adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2)); 1485 adv_1000hdx_cap = adv_1000fdx_cap; 1486 adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1)); 1487 adv_100fdx_cap = adv_1000hdx_cap; 1488 adv_100fdx_cap |= ((speed == 100) && (duplex == 2)); 1489 adv_100hdx_cap = adv_100fdx_cap; 1490 adv_100hdx_cap |= ((speed == 100) && (duplex == 1)); 1491 adv_10fdx_cap = adv_100hdx_cap; 1492 adv_10fdx_cap |= ((speed == 10) && (duplex == 2)); 1493 adv_10hdx_cap = adv_10fdx_cap; 1494 adv_10hdx_cap |= ((speed == 10) && (duplex == 1)); 1495 } else if (speed == 0) { 1496 adv_10gfdx_cap = (duplex == 2); 1497 adv_10ghdx_cap = (duplex == 1); 1498 adv_1000fdx_cap = (duplex == 2); 1499 adv_1000hdx_cap = (duplex == 1); 1500 adv_100fdx_cap = (duplex == 2); 1501 adv_100hdx_cap = (duplex == 1); 1502 adv_10fdx_cap = (duplex == 2); 1503 adv_10hdx_cap = (duplex == 1); 1504 } 1505 if (duplex == 0) { 1506 adv_10gfdx_cap = (speed == 0); 1507 adv_10gfdx_cap |= (speed == 10000); 1508 adv_10ghdx_cap = adv_10gfdx_cap; 1509 adv_10ghdx_cap |= (speed == 10000); 1510 adv_1000fdx_cap = adv_10ghdx_cap; 1511 adv_1000fdx_cap |= (speed == 1000); 1512 adv_1000hdx_cap = adv_1000fdx_cap; 1513 adv_1000hdx_cap |= (speed == 1000); 1514 adv_100fdx_cap = adv_1000hdx_cap; 1515 adv_100fdx_cap |= (speed == 100); 1516 adv_100hdx_cap = adv_100fdx_cap; 1517 adv_100hdx_cap |= (speed == 100); 1518 adv_10fdx_cap = adv_100hdx_cap; 1519 adv_10fdx_cap |= (speed == 10); 1520 adv_10hdx_cap = adv_10fdx_cap; 1521 adv_10hdx_cap |= (speed == 10); 1522 } 1523 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1524 "adv-autoneg-cap", &adv_autoneg_cap, 1); 1525 if (status) 1526 return; 1527 1528 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1529 "adv-10gfdx-cap", &adv_10gfdx_cap, 1); 1530 if (status) 1531 goto nxge_map_myargs_to_gmii_fail1; 1532 1533 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1534 "adv-10ghdx-cap", &adv_10ghdx_cap, 1); 1535 if (status) 1536 goto nxge_map_myargs_to_gmii_fail2; 1537 1538 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1539 "adv-1000fdx-cap", &adv_1000fdx_cap, 1); 1540 if (status) 1541 goto nxge_map_myargs_to_gmii_fail3; 1542 1543 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1544 "adv-1000hdx-cap", &adv_1000hdx_cap, 1); 1545 if (status) 1546 goto nxge_map_myargs_to_gmii_fail4; 1547 1548 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1549 "adv-100fdx-cap", &adv_100fdx_cap, 1); 1550 if (status) 1551 goto nxge_map_myargs_to_gmii_fail5; 1552 1553 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1554 "adv-100hdx-cap", &adv_100hdx_cap, 1); 1555 if (status) 1556 goto nxge_map_myargs_to_gmii_fail6; 1557 1558 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1559 "adv-10fdx-cap", &adv_10fdx_cap, 1); 1560 if (status) 1561 goto nxge_map_myargs_to_gmii_fail7; 1562 1563 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1564 "adv-10hdx-cap", &adv_10hdx_cap, 1); 1565 if (status) 1566 goto nxge_map_myargs_to_gmii_fail8; 1567 1568 return; 1569 1570 nxge_map_myargs_to_gmii_fail9: 1571 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap"); 1572 1573 nxge_map_myargs_to_gmii_fail8: 1574 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap"); 1575 1576 nxge_map_myargs_to_gmii_fail7: 1577 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap"); 1578 1579 nxge_map_myargs_to_gmii_fail6: 1580 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap"); 1581 1582 nxge_map_myargs_to_gmii_fail5: 1583 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap"); 1584 1585 nxge_map_myargs_to_gmii_fail4: 1586 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap"); 1587 1588 nxge_map_myargs_to_gmii_fail3: 1589 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap"); 1590 1591 nxge_map_myargs_to_gmii_fail2: 1592 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap"); 1593 1594 nxge_map_myargs_to_gmii_fail1: 1595 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap"); 1596 } 1597 1598 nxge_status_t 1599 nxge_get_config_properties(p_nxge_t nxgep) 1600 { 1601 nxge_status_t status = NXGE_OK; 1602 p_nxge_hw_list_t hw_p; 1603 1604 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties")); 1605 1606 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 1607 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1608 " nxge_get_config_properties:" 1609 " common hardware not set", nxgep->niu_type)); 1610 return (NXGE_ERROR); 1611 } 1612 1613 /* 1614 * Get info on how many ports Neptune card has. 1615 */ 1616 nxgep->nports = nxge_get_nports(nxgep); 1617 if (nxgep->nports <= 0) { 1618 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1619 "<==nxge_get_config_properties: Invalid Neptune type 0x%x", 1620 nxgep->niu_type)); 1621 return (NXGE_ERROR); 1622 } 1623 nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY; 1624 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1625 nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY; 1626 } 1627 if (nxgep->function_num >= nxgep->nports) { 1628 return (NXGE_ERROR); 1629 } 1630 1631 status = nxge_get_mac_addr_properties(nxgep); 1632 if (status != NXGE_OK) 1633 return (NXGE_ERROR); 1634 1635 /* 1636 * read the configuration type. If none is specified, used default. 1637 * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM 1638 * are shared equally across all the ports. 1639 * 1640 * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional 1641 * to the port speed. 1642 * 1643 * 1644 * custom: DMA channels, RDC groups, TCAM, FCRAM partition is 1645 * specified in nxge.conf. Need to read each parameter and set 1646 * up the parameters in nxge structures. 1647 * 1648 */ 1649 switch (nxgep->niu_type) { 1650 case N2_NIU: 1651 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1652 " ==> nxge_get_config_properties: N2")); 1653 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1654 if ((hw_p->flags & COMMON_CFG_VALID) != 1655 COMMON_CFG_VALID) { 1656 status = nxge_cfg_verify_set(nxgep, 1657 COMMON_RXDMA_GRP_CFG); 1658 status = nxge_cfg_verify_set(nxgep, 1659 COMMON_CLASS_CFG); 1660 hw_p->flags |= COMMON_CFG_VALID; 1661 } 1662 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1663 status = nxge_use_cfg_n2niu_properties(nxgep); 1664 break; 1665 default: 1666 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1667 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1668 " nxge_get_config_properties:" 1669 " unknown NIU type 0x%x", nxgep->niu_type)); 1670 return (NXGE_ERROR); 1671 } 1672 1673 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1674 " ==> nxge_get_config_properties: Neptune")); 1675 status = nxge_cfg_verify_set_quick_config(nxgep); 1676 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1677 if ((hw_p->flags & COMMON_CFG_VALID) != 1678 COMMON_CFG_VALID) { 1679 status = nxge_cfg_verify_set(nxgep, 1680 COMMON_TXDMA_CFG); 1681 status = nxge_cfg_verify_set(nxgep, 1682 COMMON_RXDMA_CFG); 1683 status = nxge_cfg_verify_set(nxgep, 1684 COMMON_RXDMA_GRP_CFG); 1685 status = nxge_cfg_verify_set(nxgep, 1686 COMMON_CLASS_CFG); 1687 hw_p->flags |= COMMON_CFG_VALID; 1688 } 1689 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1690 nxge_use_cfg_neptune_properties(nxgep); 1691 status = NXGE_OK; 1692 break; 1693 } 1694 1695 /* 1696 * Get the software LSO enable flag property from the 1697 * driver configuration file (nxge.conf). 1698 * This flag will be set to disable (0) if this property 1699 * does not exist. 1700 */ 1701 nxgep->soft_lso_enable = ddi_prop_get_int(DDI_DEV_T_ANY, nxgep->dip, 1702 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, "soft-lso-enable", 0); 1703 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1704 "nxge_get_config_properties: software lso %d\n", 1705 nxgep->soft_lso_enable)); 1706 1707 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties")); 1708 return (status); 1709 } 1710 1711 static nxge_status_t 1712 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep) 1713 { 1714 nxge_status_t status = NXGE_OK; 1715 1716 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties")); 1717 1718 status = nxge_use_default_dma_config_n2(nxgep); 1719 if (status != NXGE_OK) { 1720 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1721 " ==> nxge_use_cfg_n2niu_properties (err 0x%x)", 1722 status)); 1723 return (status | NXGE_ERROR); 1724 } 1725 1726 (void) nxge_use_cfg_vlan_class_config(nxgep); 1727 (void) nxge_use_cfg_mac_class_config(nxgep); 1728 (void) nxge_use_cfg_class_config(nxgep); 1729 (void) nxge_use_cfg_link_cfg(nxgep); 1730 1731 /* 1732 * Read in the hardware (fcode) properties. Use the ndd array to read 1733 * each property. 1734 */ 1735 (void) nxge_get_param_soft_properties(nxgep); 1736 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties")); 1737 1738 return (status); 1739 } 1740 1741 static void 1742 nxge_use_cfg_neptune_properties(p_nxge_t nxgep) 1743 { 1744 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties")); 1745 1746 (void) nxge_use_cfg_dma_config(nxgep); 1747 (void) nxge_use_cfg_vlan_class_config(nxgep); 1748 (void) nxge_use_cfg_mac_class_config(nxgep); 1749 (void) nxge_use_cfg_class_config(nxgep); 1750 (void) nxge_use_cfg_link_cfg(nxgep); 1751 1752 /* 1753 * Read in the hardware (fcode) properties. Use the ndd array to read 1754 * each property. 1755 */ 1756 (void) nxge_get_param_soft_properties(nxgep); 1757 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties")); 1758 } 1759 1760 /* 1761 * FWARC 2006/556 1762 */ 1763 1764 static nxge_status_t 1765 nxge_use_default_dma_config_n2(p_nxge_t nxgep) 1766 { 1767 int ndmas; 1768 int nrxgp; 1769 uint8_t func; 1770 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1771 p_nxge_hw_pt_cfg_t p_cfgp; 1772 int *prop_val; 1773 uint_t prop_len; 1774 int i; 1775 nxge_status_t status = NXGE_OK; 1776 1777 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2")); 1778 1779 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1780 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1781 1782 func = nxgep->function_num; 1783 p_cfgp->function_number = func; 1784 ndmas = NXGE_TDMA_PER_NIU_PORT; 1785 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1786 "tx-dma-channels", (int **)&prop_val, 1787 &prop_len) == DDI_PROP_SUCCESS) { 1788 p_cfgp->start_tdc = prop_val[0]; 1789 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1790 "==> nxge_use_default_dma_config_n2: tdc starts %d " 1791 "(#%d)", p_cfgp->start_tdc, prop_len)); 1792 1793 ndmas = prop_val[1]; 1794 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1795 "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)", 1796 ndmas, prop_len)); 1797 ddi_prop_free(prop_val); 1798 } else { 1799 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1800 "==> nxge_use_default_dma_config_n2: " 1801 "get tx-dma-channels failed")); 1802 return (NXGE_DDI_FAILED); 1803 } 1804 1805 p_cfgp->max_tdcs = nxgep->max_tdcs = ndmas; 1806 nxgep->tdc_mask = (ndmas - 1); 1807 1808 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1809 "p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d start %d", 1810 p_cfgp, p_cfgp->max_tdcs, nxgep->max_tdcs, p_cfgp->start_tdc)); 1811 1812 /* Receive DMA */ 1813 ndmas = NXGE_RDMA_PER_NIU_PORT; 1814 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1815 "rx-dma-channels", (int **)&prop_val, 1816 &prop_len) == DDI_PROP_SUCCESS) { 1817 p_cfgp->start_rdc = prop_val[0]; 1818 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1819 "==> nxge_use_default_dma_config_n2(obp): rdc start %d" 1820 " (#%d)", p_cfgp->start_rdc, prop_len)); 1821 ndmas = prop_val[1]; 1822 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1823 "==> nxge_use_default_dma_config_n2(obp):#rdc %d (#%d)", 1824 ndmas, prop_len)); 1825 ddi_prop_free(prop_val); 1826 } else { 1827 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1828 "==> nxge_use_default_dma_config_n2: " 1829 "get rx-dma-channel failed")); 1830 return (NXGE_DDI_FAILED); 1831 } 1832 1833 p_cfgp->max_rdcs = nxgep->max_rdcs = ndmas; 1834 nxgep->rdc_mask = (ndmas - 1); 1835 1836 /* Hypervisor: rdc # and group # use the same # !! */ 1837 p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->max_tdcs; 1838 p_cfgp->start_grpid = 0; 1839 p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0; 1840 1841 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1842 "interrupts", (int **)&prop_val, 1843 &prop_len) == DDI_PROP_SUCCESS) { 1844 /* 1845 * For each device assigned, the content of each interrupts 1846 * property is its logical device group. 1847 * 1848 * Assignment of interrupts property is in the the following 1849 * order: 1850 * 1851 * MAC MIF (if configured) SYSTEM ERROR (if configured) first 1852 * receive channel next channel...... last receive channel 1853 * first transmit channel next channel...... last transmit 1854 * channel 1855 * 1856 * prop_len should be at least for one mac and total # of rx and 1857 * tx channels. Function 0 owns MIF and ERROR 1858 */ 1859 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1860 "==> nxge_use_default_dma_config_n2(obp): " 1861 "# interrupts %d", prop_len)); 1862 1863 switch (func) { 1864 case 0: 1865 p_cfgp->ldg_chn_start = 3; 1866 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0; 1867 p_cfgp->mif_ldvid = NXGE_MIF_LD; 1868 p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD; 1869 1870 break; 1871 case 1: 1872 p_cfgp->ldg_chn_start = 1; 1873 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1; 1874 1875 break; 1876 default: 1877 status = NXGE_DDI_FAILED; 1878 break; 1879 } 1880 1881 if (status != NXGE_OK) 1882 return (status); 1883 1884 for (i = 0; i < prop_len; i++) { 1885 p_cfgp->ldg[i] = prop_val[i]; 1886 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1887 "==> nxge_use_default_dma_config_n2(obp): " 1888 "interrupt #%d, ldg %d", 1889 i, p_cfgp->ldg[i])); 1890 } 1891 1892 p_cfgp->max_grpids = prop_len; 1893 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1894 "==> nxge_use_default_dma_config_n2(obp): %d " 1895 "(#%d) maxgrpids %d channel starts %d", 1896 p_cfgp->mac_ldvid, i, p_cfgp->max_grpids, 1897 p_cfgp->ldg_chn_start)); 1898 ddi_prop_free(prop_val); 1899 } else { 1900 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1901 "==> nxge_use_default_dma_config_n2: " 1902 "get interrupts failed")); 1903 return (NXGE_DDI_FAILED); 1904 } 1905 1906 p_cfgp->max_ldgs = p_cfgp->max_grpids; 1907 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1908 "==> nxge_use_default_dma_config_n2: " 1909 "p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d" 1910 "start_grpid %d macid %d mifid %d serrid %d", 1911 p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids, 1912 p_cfgp->start_grpid, 1913 p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid)); 1914 1915 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1916 "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d", 1917 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs)); 1918 1919 /* 1920 * RDC groups and the beginning RDC group assigned to this function. 1921 */ 1922 nrxgp = 2; 1923 p_cfgp->max_rdc_grpids = nrxgp; 1924 p_cfgp->start_rdc_grpid = (nxgep->function_num * nrxgp); 1925 1926 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1927 "rx-rdc-grps", nrxgp); 1928 if (status) { 1929 return (NXGE_DDI_FAILED); 1930 } 1931 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1932 "rx-rdc-grps-begin", p_cfgp->start_rdc_grpid); 1933 if (status) { 1934 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 1935 "rx-rdc-grps"); 1936 return (NXGE_DDI_FAILED); 1937 } 1938 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1939 "p_cfgp $%p # rdc groups %d start rdc group id %d", 1940 p_cfgp, p_cfgp->max_rdc_grpids, 1941 p_cfgp->start_rdc_grpid)); 1942 1943 nxge_set_hw_dma_config(nxgep); 1944 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2")); 1945 return (status); 1946 } 1947 1948 static void 1949 nxge_use_cfg_dma_config(p_nxge_t nxgep) 1950 { 1951 int tx_ndmas, rx_ndmas, nrxgp, st_txdma, st_rxdma; 1952 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1953 p_nxge_hw_pt_cfg_t p_cfgp; 1954 dev_info_t *dip; 1955 p_nxge_param_t param_arr; 1956 char *prop; 1957 int *prop_val; 1958 uint_t prop_len; 1959 int i; 1960 uint8_t *ch_arr_p; 1961 1962 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config")); 1963 param_arr = nxgep->param_arr; 1964 1965 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1966 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1967 dip = nxgep->dip; 1968 p_cfgp->function_number = nxgep->function_num; 1969 prop = param_arr[param_txdma_channels_begin].fcode_name; 1970 1971 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 1972 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1973 p_cfgp->start_tdc = *prop_val; 1974 ddi_prop_free(prop_val); 1975 } else { 1976 switch (nxgep->niu_type) { 1977 case NEPTUNE_4_1GC: 1978 ch_arr_p = &tx_4_1G[0]; 1979 break; 1980 case NEPTUNE_2_10GF: 1981 ch_arr_p = &tx_2_10G[0]; 1982 break; 1983 case NEPTUNE_2_10GF_2_1GC: 1984 case NEPTUNE_2_10GF_2_1GRF: 1985 ch_arr_p = &tx_2_10G_2_1G[0]; 1986 break; 1987 case NEPTUNE_1_10GF_3_1GC: 1988 ch_arr_p = &tx_1_10G_3_1G[0]; 1989 break; 1990 case NEPTUNE_1_1GC_1_10GF_2_1GC: 1991 ch_arr_p = &tx_1_1G_1_10G_2_1G[0]; 1992 break; 1993 default: 1994 switch (nxgep->platform_type) { 1995 case P_NEPTUNE_ALONSO: 1996 ch_arr_p = &tx_2_10G_2_1G[0]; 1997 break; 1998 default: 1999 ch_arr_p = &p4_tx_equal[0]; 2000 break; 2001 } 2002 break; 2003 } 2004 st_txdma = 0; 2005 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++) 2006 st_txdma += *ch_arr_p; 2007 2008 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2009 prop, st_txdma); 2010 p_cfgp->start_tdc = st_txdma; 2011 } 2012 2013 prop = param_arr[param_txdma_channels].fcode_name; 2014 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2015 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2016 tx_ndmas = *prop_val; 2017 ddi_prop_free(prop_val); 2018 } else { 2019 switch (nxgep->niu_type) { 2020 case NEPTUNE_4_1GC: 2021 tx_ndmas = tx_4_1G[nxgep->function_num]; 2022 break; 2023 case NEPTUNE_2_10GF: 2024 tx_ndmas = tx_2_10G[nxgep->function_num]; 2025 break; 2026 case NEPTUNE_2_10GF_2_1GC: 2027 case NEPTUNE_2_10GF_2_1GRF: 2028 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num]; 2029 break; 2030 case NEPTUNE_1_10GF_3_1GC: 2031 tx_ndmas = tx_1_10G_3_1G[nxgep->function_num]; 2032 break; 2033 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2034 tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num]; 2035 break; 2036 default: 2037 switch (nxgep->platform_type) { 2038 case P_NEPTUNE_ALONSO: 2039 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num]; 2040 break; 2041 default: 2042 tx_ndmas = p4_tx_equal[nxgep->function_num]; 2043 break; 2044 } 2045 break; 2046 } 2047 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2048 prop, tx_ndmas); 2049 } 2050 2051 p_cfgp->max_tdcs = nxgep->max_tdcs = tx_ndmas; 2052 nxgep->tdc_mask = (tx_ndmas - 1); 2053 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2054 "p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d", 2055 p_cfgp, p_cfgp->max_tdcs, nxgep->max_tdcs)); 2056 2057 prop = param_arr[param_rxdma_channels_begin].fcode_name; 2058 2059 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2060 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2061 p_cfgp->start_rdc = *prop_val; 2062 ddi_prop_free(prop_val); 2063 } else { 2064 switch (nxgep->niu_type) { 2065 case NEPTUNE_4_1GC: 2066 ch_arr_p = &rx_4_1G[0]; 2067 break; 2068 case NEPTUNE_2_10GF: 2069 ch_arr_p = &rx_2_10G[0]; 2070 break; 2071 case NEPTUNE_2_10GF_2_1GC: 2072 case NEPTUNE_2_10GF_2_1GRF: 2073 ch_arr_p = &rx_2_10G_2_1G[0]; 2074 break; 2075 case NEPTUNE_1_10GF_3_1GC: 2076 ch_arr_p = &rx_1_10G_3_1G[0]; 2077 break; 2078 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2079 ch_arr_p = &rx_1_1G_1_10G_2_1G[0]; 2080 break; 2081 default: 2082 switch (nxgep->platform_type) { 2083 case P_NEPTUNE_ALONSO: 2084 ch_arr_p = &rx_2_10G_2_1G[0]; 2085 break; 2086 default: 2087 ch_arr_p = &p4_rx_equal[0]; 2088 break; 2089 } 2090 break; 2091 } 2092 st_rxdma = 0; 2093 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++) 2094 st_rxdma += *ch_arr_p; 2095 2096 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2097 prop, st_rxdma); 2098 p_cfgp->start_rdc = st_rxdma; 2099 } 2100 2101 prop = param_arr[param_rxdma_channels].fcode_name; 2102 2103 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2104 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2105 rx_ndmas = *prop_val; 2106 ddi_prop_free(prop_val); 2107 } else { 2108 switch (nxgep->niu_type) { 2109 case NEPTUNE_4_1GC: 2110 rx_ndmas = rx_4_1G[nxgep->function_num]; 2111 break; 2112 case NEPTUNE_2_10GF: 2113 rx_ndmas = rx_2_10G[nxgep->function_num]; 2114 break; 2115 case NEPTUNE_2_10GF_2_1GC: 2116 case NEPTUNE_2_10GF_2_1GRF: 2117 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num]; 2118 break; 2119 case NEPTUNE_1_10GF_3_1GC: 2120 rx_ndmas = rx_1_10G_3_1G[nxgep->function_num]; 2121 break; 2122 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2123 rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num]; 2124 break; 2125 default: 2126 switch (nxgep->platform_type) { 2127 case P_NEPTUNE_ALONSO: 2128 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num]; 2129 break; 2130 default: 2131 rx_ndmas = p4_rx_equal[nxgep->function_num]; 2132 break; 2133 } 2134 break; 2135 } 2136 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2137 prop, rx_ndmas); 2138 } 2139 2140 p_cfgp->max_rdcs = nxgep->max_rdcs = rx_ndmas; 2141 2142 prop = param_arr[param_rdc_grps_start].fcode_name; 2143 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2144 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2145 p_cfgp->start_rdc_grpid = *prop_val; 2146 ddi_prop_free(prop_val); 2147 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2148 "==> nxge_use_default_dma_config: " 2149 "use property " "start_grpid %d ", 2150 p_cfgp->start_grpid)); 2151 } else { 2152 p_cfgp->start_rdc_grpid = nxgep->function_num; 2153 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2154 prop, p_cfgp->start_rdc_grpid); 2155 2156 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2157 "==> nxge_use_default_dma_config: " 2158 "use default " 2159 "start_grpid %d (same as function #)", 2160 p_cfgp->start_grpid)); 2161 } 2162 2163 prop = param_arr[param_rx_rdc_grps].fcode_name; 2164 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2165 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2166 nrxgp = *prop_val; 2167 ddi_prop_free(prop_val); 2168 } else { 2169 nrxgp = 1; 2170 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2171 prop, nrxgp); 2172 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2173 "==> nxge_use_default_dma_config: " 2174 "num_rdc_grpid not found: use def:# of " 2175 "rdc groups %d\n", nrxgp)); 2176 } 2177 2178 p_cfgp->max_rdc_grpids = nrxgp; 2179 2180 /* 2181 * 2/4 ports have the same hard-wired logical groups assigned. 2182 */ 2183 p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS; 2184 p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS; 2185 2186 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: " 2187 "p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d" 2188 "start_grpid %d", 2189 p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids, 2190 p_cfgp->start_grpid)); 2191 2192 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2193 "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d " 2194 "start_rdc_grpid %d", 2195 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs, 2196 p_cfgp->start_rdc_grpid)); 2197 2198 prop = param_arr[param_rxdma_intr_time].fcode_name; 2199 2200 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2201 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2202 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2203 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2204 nxgep->dip, prop, prop_val, prop_len); 2205 } 2206 ddi_prop_free(prop_val); 2207 } 2208 prop = param_arr[param_rxdma_intr_pkts].fcode_name; 2209 2210 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2211 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2212 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2213 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2214 nxgep->dip, prop, prop_val, prop_len); 2215 } 2216 ddi_prop_free(prop_val); 2217 } 2218 nxge_set_hw_dma_config(nxgep); 2219 2220 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: " 2221 "sTDC[%d] nTDC[%d] sRDC[%d] nRDC[%d]", 2222 p_cfgp->start_tdc, p_cfgp->max_tdcs, 2223 p_cfgp->start_rdc, p_cfgp->max_rdcs)); 2224 2225 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config")); 2226 } 2227 2228 static void 2229 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep) 2230 { 2231 uint_t vlan_cnt; 2232 int *vlan_cfg_val; 2233 int status; 2234 p_nxge_param_t param_arr; 2235 char *prop; 2236 2237 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config")); 2238 param_arr = nxgep->param_arr; 2239 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2240 2241 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2242 &vlan_cfg_val, &vlan_cnt); 2243 if (status == DDI_PROP_SUCCESS) { 2244 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2245 nxgep->dip, prop, vlan_cfg_val, vlan_cnt); 2246 ddi_prop_free(vlan_cfg_val); 2247 } 2248 nxge_set_hw_vlan_class_config(nxgep); 2249 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config")); 2250 } 2251 2252 static void 2253 nxge_use_cfg_mac_class_config(p_nxge_t nxgep) 2254 { 2255 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2256 p_nxge_hw_pt_cfg_t p_cfgp; 2257 uint_t mac_cnt; 2258 int *mac_cfg_val; 2259 int status; 2260 p_nxge_param_t param_arr; 2261 char *prop; 2262 2263 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config")); 2264 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2265 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2266 p_cfgp->start_mac_entry = 0; 2267 param_arr = nxgep->param_arr; 2268 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2269 2270 switch (nxgep->function_num) { 2271 case 0: 2272 case 1: 2273 /* 10G ports */ 2274 p_cfgp->max_macs = NXGE_MAX_MACS_XMACS; 2275 break; 2276 case 2: 2277 case 3: 2278 /* 1G ports */ 2279 default: 2280 p_cfgp->max_macs = NXGE_MAX_MACS_BMACS; 2281 break; 2282 } 2283 2284 p_cfgp->mac_pref = 1; 2285 p_cfgp->def_mac_rxdma_grpid = p_cfgp->start_rdc_grpid; 2286 2287 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2288 "== nxge_use_cfg_mac_class_config: " 2289 " mac_pref bit set def_mac_rxdma_grpid %d", 2290 p_cfgp->def_mac_rxdma_grpid)); 2291 2292 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2293 &mac_cfg_val, &mac_cnt); 2294 if (status == DDI_PROP_SUCCESS) { 2295 if (mac_cnt <= p_cfgp->max_macs) 2296 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2297 nxgep->dip, prop, mac_cfg_val, mac_cnt); 2298 ddi_prop_free(mac_cfg_val); 2299 } 2300 nxge_set_hw_mac_class_config(nxgep); 2301 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config")); 2302 } 2303 2304 static void 2305 nxge_use_cfg_class_config(p_nxge_t nxgep) 2306 { 2307 nxge_set_hw_class_config(nxgep); 2308 } 2309 2310 static void 2311 nxge_set_rdc_intr_property(p_nxge_t nxgep) 2312 { 2313 int i; 2314 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2315 2316 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property")); 2317 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2318 2319 for (i = 0; i < NXGE_MAX_RDCS; i++) { 2320 p_dma_cfgp->rcr_timeout[i] = nxge_rcr_timeout; 2321 p_dma_cfgp->rcr_threshold[i] = nxge_rcr_threshold; 2322 } 2323 2324 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property")); 2325 } 2326 2327 static void 2328 nxge_set_hw_dma_config(p_nxge_t nxgep) 2329 { 2330 int i, j, rdc, ndmas, ngrps, bitmap, end, st_rdc; 2331 int32_t status; 2332 uint8_t rdcs_per_grp; 2333 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2334 p_nxge_hw_pt_cfg_t p_cfgp; 2335 p_nxge_rdc_grp_t rdc_grp_p; 2336 int rdcgrp_cfg = CFG_NOT_SPECIFIED, rx_quick_cfg; 2337 char *prop, *prop_val; 2338 p_nxge_param_t param_arr; 2339 config_token_t token; 2340 2341 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config")); 2342 2343 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2344 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2345 rdc_grp_p = p_dma_cfgp->rdc_grps; 2346 2347 /* Transmit DMA Channels */ 2348 bitmap = 0; 2349 end = p_cfgp->start_tdc + p_cfgp->max_tdcs; 2350 nxgep->ntdc = p_cfgp->max_tdcs; 2351 p_dma_cfgp->tx_dma_map = 0; 2352 for (i = p_cfgp->start_tdc; i < end; i++) { 2353 bitmap |= (1 << i); 2354 nxgep->tdc[i - p_cfgp->start_tdc] = (uint8_t)i; 2355 } 2356 2357 p_dma_cfgp->tx_dma_map = bitmap; 2358 param_arr = nxgep->param_arr; 2359 2360 /* Assume RDCs are evenly distributed */ 2361 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 2362 switch (rx_quick_cfg) { 2363 case CFG_NOT_SPECIFIED: 2364 prop = "rxdma-grp-cfg"; 2365 status = ddi_prop_lookup_string(DDI_DEV_T_NONE, 2366 nxgep->dip, 0, prop, (char **)&prop_val); 2367 if (status != DDI_PROP_SUCCESS) { 2368 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2369 " property %s not found", prop)); 2370 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2371 } else { 2372 token = nxge_get_config_token(prop_val); 2373 switch (token) { 2374 case L2_CLASSIFY: 2375 break; 2376 case CLASSIFY: 2377 case L3_CLASSIFY: 2378 case L3_DISTRIBUTE: 2379 case L3_TCAM: 2380 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2381 break; 2382 default: 2383 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2384 break; 2385 } 2386 ddi_prop_free(prop_val); 2387 } 2388 break; 2389 case CFG_L3_WEB: 2390 case CFG_L3_DISTRIBUTE: 2391 case CFG_L2_CLASSIFY: 2392 case CFG_L3_TCAM: 2393 rdcgrp_cfg = rx_quick_cfg; 2394 break; 2395 default: 2396 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2397 break; 2398 } 2399 2400 /* Receive DMA Channels */ 2401 st_rdc = p_cfgp->start_rdc; 2402 nxgep->nrdc = p_cfgp->max_rdcs; 2403 2404 for (i = 0; i < p_cfgp->max_rdcs; i++) { 2405 nxgep->rdc[i] = i + p_cfgp->start_rdc; 2406 } 2407 2408 switch (rdcgrp_cfg) { 2409 case CFG_L3_DISTRIBUTE: 2410 case CFG_L3_WEB: 2411 case CFG_L3_TCAM: 2412 ndmas = p_cfgp->max_rdcs; 2413 ngrps = 1; 2414 rdcs_per_grp = ndmas / ngrps; 2415 break; 2416 case CFG_L2_CLASSIFY: 2417 ndmas = p_cfgp->max_rdcs / 2; 2418 if (p_cfgp->max_rdcs < 2) 2419 ndmas = 1; 2420 ngrps = 1; 2421 rdcs_per_grp = ndmas / ngrps; 2422 break; 2423 default: 2424 ngrps = p_cfgp->max_rdc_grpids; 2425 ndmas = p_cfgp->max_rdcs; 2426 rdcs_per_grp = ndmas / ngrps; 2427 break; 2428 } 2429 2430 for (i = 0; i < ngrps; i++) { 2431 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 2432 rdc_grp_p->start_rdc = st_rdc + i * rdcs_per_grp; 2433 rdc_grp_p->max_rdcs = rdcs_per_grp; 2434 2435 /* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */ 2436 rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ; 2437 rdc = rdc_grp_p->start_rdc; 2438 for (j = 0; j < NXGE_MAX_RDCS; j++) { 2439 rdc_grp_p->rdc[j] = rdc++; 2440 if (rdc == (rdc_grp_p->start_rdc + rdcs_per_grp)) { 2441 rdc = rdc_grp_p->start_rdc; 2442 } 2443 } 2444 rdc_grp_p->def_rdc = rdc_grp_p->rdc[0]; 2445 rdc_grp_p->flag = 1; /* configured */ 2446 } 2447 2448 /* default RDC */ 2449 p_cfgp->def_rdc = p_cfgp->start_rdc; 2450 nxgep->def_rdc = p_cfgp->start_rdc; 2451 2452 /* full 18 byte header ? */ 2453 p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER; 2454 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G; 2455 if (nxgep->function_num > 1) 2456 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G; 2457 p_dma_cfgp->rbr_size = nxge_rbr_size; 2458 p_dma_cfgp->rcr_size = nxge_rcr_size; 2459 2460 nxge_set_rdc_intr_property(nxgep); 2461 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config")); 2462 } 2463 2464 boolean_t 2465 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc) 2466 { 2467 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2468 p_nxge_hw_pt_cfg_t p_cfgp; 2469 int status = B_TRUE; 2470 2471 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member")); 2472 2473 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2474 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2475 2476 /* Receive DMA Channels */ 2477 if (rdc < p_cfgp->max_rdcs) 2478 status = B_TRUE; 2479 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member")); 2480 return (status); 2481 } 2482 2483 boolean_t 2484 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc) 2485 { 2486 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2487 p_nxge_hw_pt_cfg_t p_cfgp; 2488 int status = B_FALSE; 2489 2490 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member")); 2491 2492 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2493 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2494 2495 /* Receive DMA Channels */ 2496 if (tdc < p_cfgp->max_tdcs) 2497 status = B_TRUE; 2498 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member")); 2499 return (status); 2500 } 2501 2502 boolean_t 2503 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc) 2504 { 2505 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2506 int status = B_TRUE; 2507 p_nxge_rdc_grp_t rdc_grp_p; 2508 2509 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2510 " ==> nxge_check_rxdma_rdcgrp_member")); 2511 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " nxge_check_rxdma_rdcgrp_member" 2512 " rdc %d group %d", rdc, rdc_grp)); 2513 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2514 2515 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 2516 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " max %d ", rdc_grp_p->max_rdcs)); 2517 if (rdc >= rdc_grp_p->max_rdcs) { 2518 status = B_FALSE; 2519 } 2520 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2521 " <== nxge_check_rxdma_rdcgrp_member")); 2522 return (status); 2523 } 2524 2525 boolean_t 2526 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp) 2527 { 2528 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2529 p_nxge_hw_pt_cfg_t p_cfgp; 2530 int status = B_TRUE; 2531 2532 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member")); 2533 2534 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2535 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2536 2537 if (rdc_grp >= p_cfgp->max_rdc_grpids) 2538 status = B_FALSE; 2539 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member")); 2540 return (status); 2541 } 2542 2543 static void 2544 nxge_set_hw_vlan_class_config(p_nxge_t nxgep) 2545 { 2546 int i; 2547 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2548 p_nxge_hw_pt_cfg_t p_cfgp; 2549 p_nxge_param_t param_arr; 2550 uint_t vlan_cnt; 2551 int *vlan_cfg_val; 2552 nxge_param_map_t *vmap; 2553 char *prop; 2554 p_nxge_class_pt_cfg_t p_class_cfgp; 2555 uint32_t good_cfg[32]; 2556 int good_count = 0; 2557 nxge_mv_cfg_t *vlan_tbl; 2558 2559 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config")); 2560 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2561 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2562 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2563 2564 param_arr = nxgep->param_arr; 2565 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2566 2567 /* 2568 * By default, VLAN to RDC group mapping is disabled Need to read HW or 2569 * .conf properties to find out if mapping is required 2570 * 2571 * Format 2572 * 2573 * uint32_t array, each array entry specifying the VLAN id and the 2574 * mapping 2575 * 2576 * bit[30] = add bit[29] = remove bit[28] = preference bits[23-16] = 2577 * rdcgrp bits[15-0] = VLAN ID ( ) 2578 */ 2579 2580 for (i = 0; i < NXGE_MAX_VLANS; i++) { 2581 p_class_cfgp->vlan_tbl[i].flag = 0; 2582 } 2583 2584 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 2585 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2586 &vlan_cfg_val, &vlan_cnt) == DDI_PROP_SUCCESS) { 2587 for (i = 0; i < vlan_cnt; i++) { 2588 vmap = (nxge_param_map_t *)&vlan_cfg_val[i]; 2589 if ((vmap->param_id) && 2590 (vmap->param_id < NXGE_MAX_VLANS) && 2591 (vmap->map_to < 2592 p_cfgp->max_rdc_grpids) && 2593 (vmap->map_to >= (uint8_t)0)) { 2594 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2595 " nxge_vlan_config mapping" 2596 " id %d grp %d", 2597 vmap->param_id, vmap->map_to)); 2598 good_cfg[good_count] = vlan_cfg_val[i]; 2599 if (vlan_tbl[vmap->param_id].flag == 0) 2600 good_count++; 2601 vlan_tbl[vmap->param_id].flag = 1; 2602 vlan_tbl[vmap->param_id].rdctbl = 2603 vmap->map_to + p_cfgp->start_rdc_grpid; 2604 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 2605 } 2606 } 2607 ddi_prop_free(vlan_cfg_val); 2608 if (good_count != vlan_cnt) { 2609 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2610 nxgep->dip, prop, (int *)good_cfg, good_count); 2611 } 2612 } 2613 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config")); 2614 } 2615 2616 static void 2617 nxge_set_hw_mac_class_config(p_nxge_t nxgep) 2618 { 2619 int i; 2620 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2621 p_nxge_hw_pt_cfg_t p_cfgp; 2622 p_nxge_param_t param_arr; 2623 uint_t mac_cnt; 2624 int *mac_cfg_val; 2625 nxge_param_map_t *mac_map; 2626 char *prop; 2627 p_nxge_class_pt_cfg_t p_class_cfgp; 2628 int good_count = 0; 2629 int good_cfg[NXGE_MAX_MACS]; 2630 nxge_mv_cfg_t *mac_host_info; 2631 2632 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config")); 2633 2634 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2635 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2636 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2637 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 2638 2639 param_arr = nxgep->param_arr; 2640 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2641 2642 for (i = 0; i < NXGE_MAX_MACS; i++) { 2643 p_class_cfgp->mac_host_info[i].flag = 0; 2644 p_class_cfgp->mac_host_info[i].rdctbl = 2645 p_cfgp->def_mac_rxdma_grpid; 2646 } 2647 2648 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2649 &mac_cfg_val, &mac_cnt) == DDI_PROP_SUCCESS) { 2650 for (i = 0; i < mac_cnt; i++) { 2651 mac_map = (nxge_param_map_t *)&mac_cfg_val[i]; 2652 if ((mac_map->param_id < p_cfgp->max_macs) && 2653 (mac_map->map_to < 2654 p_cfgp->max_rdc_grpids) && 2655 (mac_map->map_to >= (uint8_t)0)) { 2656 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2657 " nxge_mac_config mapping" 2658 " id %d grp %d", 2659 mac_map->param_id, mac_map->map_to)); 2660 mac_host_info[mac_map->param_id].mpr_npr = 2661 mac_map->pref; 2662 mac_host_info[mac_map->param_id].rdctbl = 2663 mac_map->map_to + 2664 p_cfgp->start_rdc_grpid; 2665 good_cfg[good_count] = mac_cfg_val[i]; 2666 if (mac_host_info[mac_map->param_id].flag == 0) 2667 good_count++; 2668 mac_host_info[mac_map->param_id].flag = 1; 2669 } 2670 } 2671 ddi_prop_free(mac_cfg_val); 2672 if (good_count != mac_cnt) { 2673 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2674 nxgep->dip, prop, good_cfg, good_count); 2675 } 2676 } 2677 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config")); 2678 } 2679 2680 static void 2681 nxge_set_hw_class_config(p_nxge_t nxgep) 2682 { 2683 int i; 2684 p_nxge_param_t param_arr; 2685 int *int_prop_val; 2686 uint32_t cfg_value; 2687 char *prop; 2688 p_nxge_class_pt_cfg_t p_class_cfgp; 2689 int start_prop, end_prop; 2690 uint_t prop_cnt; 2691 2692 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config")); 2693 2694 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2695 param_arr = nxgep->param_arr; 2696 start_prop = param_class_opt_ip_usr4; 2697 end_prop = param_class_opt_ipv6_sctp; 2698 2699 for (i = start_prop; i <= end_prop; i++) { 2700 prop = param_arr[i].fcode_name; 2701 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 2702 0, prop, &int_prop_val, 2703 &prop_cnt) == DDI_PROP_SUCCESS) { 2704 cfg_value = (uint32_t)*int_prop_val; 2705 ddi_prop_free(int_prop_val); 2706 } else { 2707 cfg_value = (uint32_t)param_arr[i].value; 2708 } 2709 p_class_cfgp->class_cfg[i - start_prop] = cfg_value; 2710 } 2711 2712 prop = param_arr[param_h1_init_value].fcode_name; 2713 2714 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2715 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) { 2716 cfg_value = (uint32_t)*int_prop_val; 2717 ddi_prop_free(int_prop_val); 2718 } else { 2719 cfg_value = (uint32_t)param_arr[param_h1_init_value].value; 2720 } 2721 2722 p_class_cfgp->init_h1 = (uint32_t)cfg_value; 2723 prop = param_arr[param_h2_init_value].fcode_name; 2724 2725 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2726 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) { 2727 cfg_value = (uint32_t)*int_prop_val; 2728 ddi_prop_free(int_prop_val); 2729 } else { 2730 cfg_value = (uint32_t)param_arr[param_h2_init_value].value; 2731 } 2732 2733 p_class_cfgp->init_h2 = (uint16_t)cfg_value; 2734 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config")); 2735 } 2736 2737 nxge_status_t 2738 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 2739 { 2740 int i, maxldvs, maxldgs, start, end, nldvs; 2741 int ldv, endldg; 2742 uint8_t func; 2743 uint8_t channel; 2744 uint8_t chn_start; 2745 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 2746 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2747 p_nxge_hw_pt_cfg_t p_cfgp; 2748 p_nxge_ldgv_t ldgvp; 2749 p_nxge_ldg_t ldgp, ptr; 2750 p_nxge_ldv_t ldvp; 2751 nxge_status_t status = NXGE_OK; 2752 2753 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2")); 2754 if (!*navail_p) { 2755 *nrequired_p = 0; 2756 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2757 "<== nxge_ldgv_init:no avail")); 2758 return (NXGE_ERROR); 2759 } 2760 /* 2761 * N2/NIU: one logical device owns one logical group. and each 2762 * device/group will be assigned one vector by Hypervisor. 2763 */ 2764 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2765 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2766 maxldgs = p_cfgp->max_ldgs; 2767 if (!maxldgs) { 2768 /* No devices configured. */ 2769 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: " 2770 "no logical groups configured.")); 2771 return (NXGE_ERROR); 2772 } else { 2773 maxldvs = maxldgs + 1; 2774 } 2775 2776 /* 2777 * If function zero instance, it needs to handle the system and MIF 2778 * error interrupts. MIF interrupt may not be needed for N2/NIU. 2779 */ 2780 func = nxgep->function_num; 2781 if (func == 0) { 2782 own_sys_err = B_TRUE; 2783 if (!p_cfgp->ser_ldvid) { 2784 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2785 "nxge_ldgv_init_n2: func 0, ERR ID not set!")); 2786 } 2787 /* MIF interrupt */ 2788 if (!p_cfgp->mif_ldvid) { 2789 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2790 "nxge_ldgv_init_n2: func 0, MIF ID not set!")); 2791 } 2792 } 2793 2794 /* 2795 * Assume single partition, each function owns mac. 2796 */ 2797 if (!nxge_use_partition) 2798 own_fzc = B_TRUE; 2799 2800 ldgvp = nxgep->ldgvp; 2801 if (ldgvp == NULL) { 2802 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 2803 nxgep->ldgvp = ldgvp; 2804 ldgvp->maxldgs = (uint8_t)maxldgs; 2805 ldgvp->maxldvs = (uint8_t)maxldvs; 2806 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs, 2807 KM_SLEEP); 2808 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs, 2809 KM_SLEEP); 2810 } else { 2811 ldgp = ldgvp->ldgp; 2812 ldvp = ldgvp->ldvp; 2813 } 2814 2815 ldgvp->ndma_ldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 2816 ldgvp->tmres = NXGE_TIMER_RESO; 2817 2818 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2819 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d", 2820 maxldvs, maxldgs)); 2821 2822 /* logical start_ldg is ldv */ 2823 ptr = ldgp; 2824 for (i = 0; i < maxldgs; i++) { 2825 ptr->func = func; 2826 ptr->arm = B_TRUE; 2827 ptr->vldg_index = (uint8_t)i; 2828 ptr->ldg_timer = NXGE_TIMER_LDG; 2829 ptr->ldg = p_cfgp->ldg[i]; 2830 ptr->sys_intr_handler = nxge_intr; 2831 ptr->nldvs = 0; 2832 ptr->ldvp = NULL; 2833 ptr->nxgep = nxgep; 2834 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2835 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d " 2836 "ldg %d ldgptr $%p", 2837 maxldvs, maxldgs, ptr->ldg, ptr)); 2838 ptr++; 2839 } 2840 2841 endldg = NXGE_INT_MAX_LDG; 2842 nldvs = 0; 2843 ldgvp->nldvs = 0; 2844 ldgp->ldvp = NULL; 2845 *nrequired_p = 0; 2846 2847 /* 2848 * logical device group table is organized in the following order (same 2849 * as what interrupt property has). function 0: owns MAC, MIF, error, 2850 * rx, tx. function 1: owns MAC, rx, tx. 2851 */ 2852 2853 if (own_fzc && p_cfgp->mac_ldvid) { 2854 /* Each function should own MAC interrupt */ 2855 ldv = p_cfgp->mac_ldvid; 2856 ldvp->ldv = (uint8_t)ldv; 2857 ldvp->is_mac = B_TRUE; 2858 ldvp->ldv_intr_handler = nxge_mac_intr; 2859 ldvp->ldv_ldf_masks = 0; 2860 ldvp->nxgep = nxgep; 2861 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2862 "==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d " 2863 "ldg %d ldgptr $%p ldvptr $%p", 2864 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2865 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2866 nldvs++; 2867 } 2868 2869 if (own_fzc && p_cfgp->mif_ldvid) { 2870 ldv = p_cfgp->mif_ldvid; 2871 ldvp->ldv = (uint8_t)ldv; 2872 ldvp->is_mif = B_TRUE; 2873 ldvp->ldv_intr_handler = nxge_mif_intr; 2874 ldvp->ldv_ldf_masks = 0; 2875 ldvp->nxgep = nxgep; 2876 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2877 "==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d " 2878 "ldg %d ldgptr $%p ldvptr $%p", 2879 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2880 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2881 nldvs++; 2882 } 2883 2884 ldv = NXGE_SYS_ERROR_LD; 2885 ldvp->use_timer = B_TRUE; 2886 if (own_sys_err && p_cfgp->ser_ldvid) { 2887 ldv = p_cfgp->ser_ldvid; 2888 /* 2889 * Unmask the system interrupt states. 2890 */ 2891 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 2892 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 2893 SYS_ERR_ZCP_MASK); 2894 } 2895 ldvp->ldv = (uint8_t)ldv; 2896 ldvp->is_syserr = B_TRUE; 2897 ldvp->ldv_intr_handler = nxge_syserr_intr; 2898 ldvp->ldv_ldf_masks = 0; 2899 ldvp->nxgep = nxgep; 2900 ldgvp->ldvp_syserr = ldvp; 2901 2902 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2903 "==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d " 2904 "ldg %d ldgptr $%p ldvptr p%p", 2905 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2906 2907 if (own_sys_err && p_cfgp->ser_ldvid) { 2908 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2909 } else { 2910 ldvp++; 2911 } 2912 2913 nldvs++; 2914 2915 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 2916 "(before rx) func %d nldvs %d navail %d nrequired %d", 2917 func, nldvs, *navail_p, *nrequired_p)); 2918 2919 /* 2920 * Receive DMA channels. 2921 */ 2922 channel = p_cfgp->start_rdc; 2923 start = p_cfgp->start_rdc + NXGE_RDMA_LD_START; 2924 end = start + p_cfgp->max_rdcs; 2925 chn_start = p_cfgp->ldg_chn_start; 2926 /* 2927 * Start with RDC to configure logical devices for each group. 2928 */ 2929 for (i = 0, ldv = start; ldv < end; i++, ldv++, chn_start++) { 2930 ldvp->is_rxdma = B_TRUE; 2931 ldvp->ldv = (uint8_t)ldv; 2932 ldvp->channel = channel++; 2933 ldvp->vdma_index = (uint8_t)i; 2934 ldvp->ldv_intr_handler = nxge_rx_intr; 2935 ldvp->ldv_ldf_masks = 0; 2936 ldvp->nxgep = nxgep; 2937 ldgp->ldg = p_cfgp->ldg[chn_start]; 2938 2939 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2940 "==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d " 2941 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx", 2942 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2943 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2944 nldvs++; 2945 } 2946 2947 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 2948 "func %d nldvs %d navail %d nrequired %d", 2949 func, nldvs, *navail_p, *nrequired_p)); 2950 2951 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 2952 "func %d nldvs %d navail %d nrequired %d ldgp 0x%llx " 2953 "ldvp 0x%llx", 2954 func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp)); 2955 /* 2956 * Transmit DMA channels. 2957 */ 2958 channel = p_cfgp->start_tdc; 2959 start = p_cfgp->start_tdc + NXGE_TDMA_LD_START; 2960 end = start + p_cfgp->max_tdcs; 2961 for (i = 0, ldv = start; ldv < end; i++, ldv++, chn_start++) { 2962 ldvp->is_txdma = B_TRUE; 2963 ldvp->ldv = (uint8_t)ldv; 2964 ldvp->channel = channel++; 2965 ldvp->vdma_index = (uint8_t)i; 2966 ldvp->ldv_intr_handler = nxge_tx_intr; 2967 ldvp->ldv_ldf_masks = 0; 2968 ldgp->ldg = p_cfgp->ldg[chn_start]; 2969 ldvp->nxgep = nxgep; 2970 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2971 "==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d " 2972 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx", 2973 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2974 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2975 nldvs++; 2976 } 2977 2978 ldgvp->ldg_intrs = *nrequired_p; 2979 ldgvp->nldvs = (uint8_t)nldvs; 2980 2981 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 2982 "func %d nldvs %d maxgrps %d navail %d nrequired %d", 2983 func, nldvs, maxldgs, *navail_p, *nrequired_p)); 2984 2985 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2")); 2986 return (status); 2987 } 2988 2989 /* 2990 * Interrupts related interface functions. 2991 */ 2992 2993 nxge_status_t 2994 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 2995 { 2996 int i, maxldvs, maxldgs, start, end, nldvs; 2997 int ldv, ldg, endldg, ngrps; 2998 uint8_t func; 2999 uint8_t channel; 3000 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 3001 p_nxge_dma_pt_cfg_t p_dma_cfgp; 3002 p_nxge_hw_pt_cfg_t p_cfgp; 3003 p_nxge_ldgv_t ldgvp; 3004 p_nxge_ldg_t ldgp, ptr; 3005 p_nxge_ldv_t ldvp; 3006 nxge_status_t status = NXGE_OK; 3007 3008 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init")); 3009 if (!*navail_p) { 3010 *nrequired_p = 0; 3011 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3012 "<== nxge_ldgv_init:no avail")); 3013 return (NXGE_ERROR); 3014 } 3015 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 3016 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 3017 3018 nldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 3019 3020 /* 3021 * If function zero instance, it needs to handle the system error 3022 * interrupts. 3023 */ 3024 func = nxgep->function_num; 3025 if (func == 0) { 3026 nldvs++; 3027 own_sys_err = B_TRUE; 3028 } else { 3029 /* use timer */ 3030 nldvs++; 3031 } 3032 3033 /* 3034 * Assume single partition, each function owns mac. 3035 */ 3036 if (!nxge_use_partition) { 3037 /* mac */ 3038 nldvs++; 3039 /* MIF */ 3040 nldvs++; 3041 own_fzc = B_TRUE; 3042 } 3043 maxldvs = nldvs; 3044 maxldgs = p_cfgp->max_ldgs; 3045 if (!maxldvs || !maxldgs) { 3046 /* No devices configured. */ 3047 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: " 3048 "no logical devices or groups configured.")); 3049 return (NXGE_ERROR); 3050 } 3051 ldgvp = nxgep->ldgvp; 3052 if (ldgvp == NULL) { 3053 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 3054 nxgep->ldgvp = ldgvp; 3055 ldgvp->maxldgs = (uint8_t)maxldgs; 3056 ldgvp->maxldvs = (uint8_t)maxldvs; 3057 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs, 3058 KM_SLEEP); 3059 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs, 3060 KM_SLEEP); 3061 } 3062 ldgvp->ndma_ldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 3063 ldgvp->tmres = NXGE_TIMER_RESO; 3064 3065 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3066 "==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d", 3067 maxldvs, maxldgs, nldvs)); 3068 ldg = p_cfgp->start_ldg; 3069 ptr = ldgp; 3070 for (i = 0; i < maxldgs; i++) { 3071 ptr->func = func; 3072 ptr->arm = B_TRUE; 3073 ptr->vldg_index = (uint8_t)i; 3074 ptr->ldg_timer = NXGE_TIMER_LDG; 3075 ptr->ldg = ldg++; 3076 ptr->sys_intr_handler = nxge_intr; 3077 ptr->nldvs = 0; 3078 ptr->nxgep = nxgep; 3079 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3080 "==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d", 3081 maxldvs, maxldgs, ptr->ldg)); 3082 ptr++; 3083 } 3084 3085 ldg = p_cfgp->start_ldg; 3086 if (maxldgs > *navail_p) { 3087 ngrps = *navail_p; 3088 } else { 3089 ngrps = maxldgs; 3090 } 3091 endldg = ldg + ngrps; 3092 3093 /* 3094 * Receive DMA channels. 3095 */ 3096 channel = p_cfgp->start_rdc; 3097 start = p_cfgp->start_rdc + NXGE_RDMA_LD_START; 3098 end = start + p_cfgp->max_rdcs; 3099 nldvs = 0; 3100 ldgvp->nldvs = 0; 3101 ldgp->ldvp = NULL; 3102 *nrequired_p = 0; 3103 3104 /* 3105 * Start with RDC to configure logical devices for each group. 3106 */ 3107 for (i = 0, ldv = start; ldv < end; i++, ldv++) { 3108 ldvp->is_rxdma = B_TRUE; 3109 ldvp->ldv = (uint8_t)ldv; 3110 /* If non-seq needs to change the following code */ 3111 ldvp->channel = channel++; 3112 ldvp->vdma_index = (uint8_t)i; 3113 ldvp->ldv_intr_handler = nxge_rx_intr; 3114 ldvp->ldv_ldf_masks = 0; 3115 ldvp->use_timer = B_FALSE; 3116 ldvp->nxgep = nxgep; 3117 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3118 nldvs++; 3119 } 3120 3121 /* 3122 * Transmit DMA channels. 3123 */ 3124 channel = p_cfgp->start_tdc; 3125 start = p_cfgp->start_tdc + NXGE_TDMA_LD_START; 3126 end = start + p_cfgp->max_tdcs; 3127 for (i = 0, ldv = start; ldv < end; i++, ldv++) { 3128 ldvp->is_txdma = B_TRUE; 3129 ldvp->ldv = (uint8_t)ldv; 3130 ldvp->channel = channel++; 3131 ldvp->vdma_index = (uint8_t)i; 3132 ldvp->ldv_intr_handler = nxge_tx_intr; 3133 ldvp->ldv_ldf_masks = 0; 3134 ldvp->use_timer = B_FALSE; 3135 ldvp->nxgep = nxgep; 3136 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3137 nldvs++; 3138 } 3139 3140 if (own_fzc) { 3141 ldv = NXGE_MIF_LD; 3142 ldvp->ldv = (uint8_t)ldv; 3143 ldvp->is_mif = B_TRUE; 3144 ldvp->ldv_intr_handler = nxge_mif_intr; 3145 ldvp->ldv_ldf_masks = 0; 3146 ldvp->use_timer = B_FALSE; 3147 ldvp->nxgep = nxgep; 3148 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3149 nldvs++; 3150 } 3151 /* 3152 * MAC port (function zero control) 3153 */ 3154 if (own_fzc) { 3155 ldvp->is_mac = B_TRUE; 3156 ldvp->ldv_intr_handler = nxge_mac_intr; 3157 ldvp->ldv_ldf_masks = 0; 3158 ldv = func + NXGE_MAC_LD_START; 3159 ldvp->ldv = (uint8_t)ldv; 3160 ldvp->use_timer = B_FALSE; 3161 ldvp->nxgep = nxgep; 3162 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3163 nldvs++; 3164 } 3165 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3166 "func %d nldvs %d navail %d nrequired %d", 3167 func, nldvs, *navail_p, *nrequired_p)); 3168 /* 3169 * Function 0 owns system error interrupts. 3170 */ 3171 ldvp->use_timer = B_TRUE; 3172 if (own_sys_err) { 3173 ldv = NXGE_SYS_ERROR_LD; 3174 ldvp->ldv = (uint8_t)ldv; 3175 ldvp->is_syserr = B_TRUE; 3176 ldvp->ldv_intr_handler = nxge_syserr_intr; 3177 ldvp->ldv_ldf_masks = 0; 3178 ldvp->nxgep = nxgep; 3179 ldgvp->ldvp_syserr = ldvp; 3180 /* 3181 * Unmask the system interrupt states. 3182 */ 3183 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 3184 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 3185 SYS_ERR_ZCP_MASK); 3186 3187 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3188 nldvs++; 3189 } else { 3190 ldv = NXGE_SYS_ERROR_LD; 3191 ldvp->ldv = (uint8_t)ldv; 3192 ldvp->is_syserr = B_TRUE; 3193 ldvp->ldv_intr_handler = nxge_syserr_intr; 3194 ldvp->nxgep = nxgep; 3195 ldvp->ldv_ldf_masks = 0; 3196 ldgvp->ldvp_syserr = ldvp; 3197 } 3198 3199 ldgvp->ldg_intrs = *nrequired_p; 3200 3201 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3202 "func %d nldvs %d navail %d nrequired %d", 3203 func, nldvs, *navail_p, *nrequired_p)); 3204 3205 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init")); 3206 return (status); 3207 } 3208 3209 nxge_status_t 3210 nxge_ldgv_uninit(p_nxge_t nxgep) 3211 { 3212 p_nxge_ldgv_t ldgvp; 3213 3214 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit")); 3215 ldgvp = nxgep->ldgvp; 3216 if (ldgvp == NULL) { 3217 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: " 3218 "no logical group configured.")); 3219 return (NXGE_OK); 3220 } 3221 if (ldgvp->ldgp) { 3222 KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs); 3223 } 3224 if (ldgvp->ldvp) { 3225 KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs); 3226 } 3227 KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t)); 3228 nxgep->ldgvp = NULL; 3229 3230 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit")); 3231 return (NXGE_OK); 3232 } 3233 3234 nxge_status_t 3235 nxge_intr_ldgv_init(p_nxge_t nxgep) 3236 { 3237 nxge_status_t status = NXGE_OK; 3238 3239 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init")); 3240 /* 3241 * Configure the logical device group numbers, state vectors and 3242 * interrupt masks for each logical device. 3243 */ 3244 status = nxge_fzc_intr_init(nxgep); 3245 3246 /* 3247 * Configure logical device masks and timers. 3248 */ 3249 status = nxge_intr_mask_mgmt(nxgep); 3250 3251 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init")); 3252 return (status); 3253 } 3254 3255 nxge_status_t 3256 nxge_intr_mask_mgmt(p_nxge_t nxgep) 3257 { 3258 p_nxge_ldgv_t ldgvp; 3259 p_nxge_ldg_t ldgp; 3260 p_nxge_ldv_t ldvp; 3261 npi_handle_t handle; 3262 int i, j; 3263 npi_status_t rs = NPI_SUCCESS; 3264 3265 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt")); 3266 3267 if ((ldgvp = nxgep->ldgvp) == NULL) { 3268 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3269 "<== nxge_intr_mask_mgmt: Null ldgvp")); 3270 return (NXGE_ERROR); 3271 } 3272 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3273 ldgp = ldgvp->ldgp; 3274 ldvp = ldgvp->ldvp; 3275 if (ldgp == NULL || ldvp == NULL) { 3276 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3277 "<== nxge_intr_mask_mgmt: Null ldgp or ldvp")); 3278 return (NXGE_ERROR); 3279 } 3280 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3281 "==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs)); 3282 /* Initialize masks. */ 3283 if (nxgep->niu_type != N2_NIU) { 3284 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3285 "==> nxge_intr_mask_mgmt(Neptune): # intrs %d ", 3286 ldgvp->ldg_intrs)); 3287 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3288 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3289 "==> nxge_intr_mask_mgmt(Neptune): # ldv %d " 3290 "in group %d", ldgp->nldvs, ldgp->ldg)); 3291 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3292 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3293 "==> nxge_intr_mask_mgmt: set ldv # %d " 3294 "for ldg %d", ldvp->ldv, ldgp->ldg)); 3295 rs = npi_intr_mask_set(handle, ldvp->ldv, 3296 ldvp->ldv_ldf_masks); 3297 if (rs != NPI_SUCCESS) { 3298 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3299 "<== nxge_intr_mask_mgmt: " 3300 "set mask failed " 3301 " rs 0x%x ldv %d mask 0x%x", 3302 rs, ldvp->ldv, 3303 ldvp->ldv_ldf_masks)); 3304 return (NXGE_ERROR | rs); 3305 } 3306 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3307 "==> nxge_intr_mask_mgmt: " 3308 "set mask OK " 3309 " rs 0x%x ldv %d mask 0x%x", 3310 rs, ldvp->ldv, 3311 ldvp->ldv_ldf_masks)); 3312 } 3313 } 3314 } 3315 ldgp = ldgvp->ldgp; 3316 /* Configure timer and arm bit */ 3317 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3318 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3319 ldgp->arm, ldgp->ldg_timer); 3320 if (rs != NPI_SUCCESS) { 3321 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3322 "<== nxge_intr_mask_mgmt: " 3323 "set timer failed " 3324 " rs 0x%x dg %d timer 0x%x", 3325 rs, ldgp->ldg, ldgp->ldg_timer)); 3326 return (NXGE_ERROR | rs); 3327 } 3328 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3329 "==> nxge_intr_mask_mgmt: " 3330 "set timer OK " 3331 " rs 0x%x ldg %d timer 0x%x", 3332 rs, ldgp->ldg, ldgp->ldg_timer)); 3333 } 3334 3335 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt")); 3336 return (NXGE_OK); 3337 } 3338 3339 nxge_status_t 3340 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on) 3341 { 3342 p_nxge_ldgv_t ldgvp; 3343 p_nxge_ldg_t ldgp; 3344 p_nxge_ldv_t ldvp; 3345 npi_handle_t handle; 3346 int i, j; 3347 npi_status_t rs = NPI_SUCCESS; 3348 3349 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3350 "==> nxge_intr_mask_mgmt_set (%d)", on)); 3351 3352 if (nxgep->niu_type == N2_NIU) { 3353 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3354 "<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)", 3355 on)); 3356 return (NXGE_ERROR); 3357 } 3358 3359 if ((ldgvp = nxgep->ldgvp) == NULL) { 3360 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3361 "==> nxge_intr_mask_mgmt_set: Null ldgvp")); 3362 return (NXGE_ERROR); 3363 } 3364 3365 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3366 ldgp = ldgvp->ldgp; 3367 ldvp = ldgvp->ldvp; 3368 if (ldgp == NULL || ldvp == NULL) { 3369 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3370 "<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp")); 3371 return (NXGE_ERROR); 3372 } 3373 /* set masks. */ 3374 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3375 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3376 "==> nxge_intr_mask_mgmt_set: flag %d ldg %d" 3377 "set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs)); 3378 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3379 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3380 "==> nxge_intr_mask_mgmt_set: " 3381 "for %d %d flag %d", i, j, on)); 3382 if (on) { 3383 ldvp->ldv_ldf_masks = 0; 3384 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3385 "==> nxge_intr_mask_mgmt_set: " 3386 "ON mask off")); 3387 } else if (!on) { 3388 ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK; 3389 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3390 "==> nxge_intr_mask_mgmt_set:mask on")); 3391 } 3392 rs = npi_intr_mask_set(handle, ldvp->ldv, 3393 ldvp->ldv_ldf_masks); 3394 if (rs != NPI_SUCCESS) { 3395 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3396 "==> nxge_intr_mask_mgmt_set: " 3397 "set mask failed " 3398 " rs 0x%x ldv %d mask 0x%x", 3399 rs, ldvp->ldv, ldvp->ldv_ldf_masks)); 3400 return (NXGE_ERROR | rs); 3401 } 3402 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3403 "==> nxge_intr_mask_mgmt_set: flag %d" 3404 "set mask OK " 3405 " ldv %d mask 0x%x", 3406 on, ldvp->ldv, ldvp->ldv_ldf_masks)); 3407 } 3408 } 3409 3410 ldgp = ldgvp->ldgp; 3411 /* set the arm bit */ 3412 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3413 if (on && !ldgp->arm) { 3414 ldgp->arm = B_TRUE; 3415 } else if (!on && ldgp->arm) { 3416 ldgp->arm = B_FALSE; 3417 } 3418 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3419 ldgp->arm, ldgp->ldg_timer); 3420 if (rs != NPI_SUCCESS) { 3421 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3422 "<== nxge_intr_mask_mgmt_set: " 3423 "set timer failed " 3424 " rs 0x%x ldg %d timer 0x%x", 3425 rs, ldgp->ldg, ldgp->ldg_timer)); 3426 return (NXGE_ERROR | rs); 3427 } 3428 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3429 "==> nxge_intr_mask_mgmt_set: OK (flag %d) " 3430 "set timer " 3431 " ldg %d timer 0x%x", 3432 on, ldgp->ldg, ldgp->ldg_timer)); 3433 } 3434 3435 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set")); 3436 return (NXGE_OK); 3437 } 3438 3439 static nxge_status_t 3440 nxge_get_mac_addr_properties(p_nxge_t nxgep) 3441 { 3442 #if defined(_BIG_ENDIAN) 3443 uchar_t *prop_val; 3444 uint_t prop_len; 3445 uint_t j; 3446 #endif 3447 uint_t i; 3448 uint8_t func_num; 3449 boolean_t compute_macs = B_TRUE; 3450 3451 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties ")); 3452 3453 #if defined(_BIG_ENDIAN) 3454 /* 3455 * Get the ethernet address. 3456 */ 3457 (void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr); 3458 3459 /* 3460 * Check if it is an adapter with its own local mac address If it is 3461 * present, override the system mac address. 3462 */ 3463 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3464 "local-mac-address", &prop_val, 3465 &prop_len) == DDI_PROP_SUCCESS) { 3466 if (prop_len == ETHERADDRL) { 3467 nxgep->factaddr = *(p_ether_addr_t)prop_val; 3468 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = " 3469 "%02x:%02x:%02x:%02x:%02x:%02x", 3470 prop_val[0], prop_val[1], prop_val[2], 3471 prop_val[3], prop_val[4], prop_val[5])); 3472 } 3473 ddi_prop_free(prop_val); 3474 } 3475 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3476 "local-mac-address?", &prop_val, 3477 &prop_len) == DDI_PROP_SUCCESS) { 3478 if (strncmp("true", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3479 nxgep->ouraddr = nxgep->factaddr; 3480 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3481 "Using local MAC address")); 3482 } 3483 ddi_prop_free(prop_val); 3484 } else { 3485 nxgep->ouraddr = nxgep->factaddr; 3486 } 3487 3488 if ((!nxgep->vpd_info.present) || 3489 (nxge_is_valid_local_mac(nxgep->factaddr))) 3490 goto got_mac_addr; 3491 3492 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: " 3493 "MAC address from properties is not valid...reading from PROM")); 3494 3495 #endif 3496 if (!nxgep->vpd_info.ver_valid) { 3497 (void) nxge_espc_mac_addrs_get(nxgep); 3498 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3499 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get " 3500 "MAC address")); 3501 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 3502 "[%s] invalid...please update", 3503 nxgep->vpd_info.ver)); 3504 return (NXGE_ERROR); 3505 } 3506 nxgep->ouraddr = nxgep->factaddr; 3507 goto got_mac_addr; 3508 } 3509 /* 3510 * First get the MAC address from the info in the VPD data read 3511 * from the EEPROM. 3512 */ 3513 nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr, 3514 nxgep->function_num, &nxgep->factaddr); 3515 3516 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3517 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3518 "nxge_get_mac_addr_properties: " 3519 "MAC address in EEPROM VPD data not valid" 3520 "...reading from NCR registers")); 3521 (void) nxge_espc_mac_addrs_get(nxgep); 3522 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3523 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get " 3524 "MAC address")); 3525 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 3526 "[%s] invalid...please update", 3527 nxgep->vpd_info.ver)); 3528 return (NXGE_ERROR); 3529 } 3530 } 3531 3532 nxgep->ouraddr = nxgep->factaddr; 3533 3534 got_mac_addr: 3535 func_num = nxgep->function_num; 3536 3537 /* 3538 * Note: mac-addresses property is the list of mac addresses for a 3539 * port. NXGE_MAX_MMAC_ADDRS is the total number of MAC addresses 3540 * allocated for a board. 3541 */ 3542 nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS; 3543 3544 #if defined(_BIG_ENDIAN) 3545 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3546 "mac-addresses", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3547 /* 3548 * XAUI may have up to 18 MACs, more than the XMAC can 3549 * use (1 unique MAC plus 16 alternate MACs) 3550 */ 3551 nxgep->nxge_mmac_info.num_factory_mmac = 3552 prop_len / ETHERADDRL - 1; 3553 if (nxgep->nxge_mmac_info.num_factory_mmac > 3554 XMAC_MAX_ALT_ADDR_ENTRY) { 3555 nxgep->nxge_mmac_info.num_factory_mmac = 3556 XMAC_MAX_ALT_ADDR_ENTRY; 3557 } 3558 3559 for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) { 3560 for (j = 0; j < ETHERADDRL; j++) { 3561 nxgep->nxge_mmac_info.factory_mac_pool[i][j] = 3562 *(prop_val + (i * ETHERADDRL) + j); 3563 } 3564 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3565 "nxge_get_mac_addr_properties: Alt mac[%d] from " 3566 "mac-addresses property[%2x:%2x:%2x:%2x:%2x:%2x]", 3567 i, nxgep->nxge_mmac_info.factory_mac_pool[i][0], 3568 nxgep->nxge_mmac_info.factory_mac_pool[i][1], 3569 nxgep->nxge_mmac_info.factory_mac_pool[i][2], 3570 nxgep->nxge_mmac_info.factory_mac_pool[i][3], 3571 nxgep->nxge_mmac_info.factory_mac_pool[i][4], 3572 nxgep->nxge_mmac_info.factory_mac_pool[i][5])); 3573 } 3574 3575 compute_macs = B_FALSE; 3576 ddi_prop_free(prop_val); 3577 goto got_mmac_info; 3578 } 3579 #endif 3580 /* 3581 * total_factory_macs = 32 3582 * num_factory_mmac = (32 >> (nports/2)) - 1 3583 * So if nports = 4, then num_factory_mmac = 7 3584 * if nports = 2, then num_factory_mmac = 15 3585 */ 3586 nxgep->nxge_mmac_info.num_factory_mmac = 3587 ((nxgep->nxge_mmac_info.total_factory_macs >> 3588 (nxgep->nports >> 1))) - 1; 3589 3590 got_mmac_info: 3591 3592 if ((nxgep->function_num < 2) && 3593 (nxgep->nxge_mmac_info.num_factory_mmac > 3594 XMAC_MAX_ALT_ADDR_ENTRY)) { 3595 nxgep->nxge_mmac_info.num_factory_mmac = 3596 XMAC_MAX_ALT_ADDR_ENTRY; 3597 } else if ((nxgep->function_num > 1) && 3598 (nxgep->nxge_mmac_info.num_factory_mmac > 3599 BMAC_MAX_ALT_ADDR_ENTRY)) { 3600 nxgep->nxge_mmac_info.num_factory_mmac = 3601 BMAC_MAX_ALT_ADDR_ENTRY; 3602 } 3603 3604 for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) { 3605 (void) npi_mac_altaddr_disable(nxgep->npi_handle, 3606 NXGE_GET_PORT_NUM(func_num), i); 3607 } 3608 3609 (void) nxge_init_mmac(nxgep, compute_macs); 3610 return (NXGE_OK); 3611 } 3612 3613 void 3614 nxge_get_xcvr_properties(p_nxge_t nxgep) 3615 { 3616 uchar_t *prop_val; 3617 uint_t prop_len; 3618 3619 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties")); 3620 3621 /* 3622 * Read the type of physical layer interface being used. 3623 */ 3624 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3625 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3626 "phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3627 if (strncmp("pcs", (caddr_t)prop_val, 3628 (size_t)prop_len) == 0) { 3629 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3630 } else { 3631 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3632 } 3633 ddi_prop_free(prop_val); 3634 } else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3635 "phy-interface", &prop_val, 3636 &prop_len) == DDI_PROP_SUCCESS) { 3637 if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3638 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3639 } else { 3640 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3641 } 3642 ddi_prop_free(prop_val); 3643 } 3644 } 3645 3646 /* 3647 * Static functions start here. 3648 */ 3649 3650 static void 3651 nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv, 3652 uint8_t endldg, int *ngrps) 3653 { 3654 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup")); 3655 /* Assign the group number for each device. */ 3656 (*ldvp)->ldg_assigned = (*ldgp)->ldg; 3657 (*ldvp)->ldgp = *ldgp; 3658 (*ldvp)->ldv = ldv; 3659 3660 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3661 "ldv %d endldg %d ldg %d, ldvp $%p", 3662 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3663 3664 (*ldgp)->nldvs++; 3665 if ((*ldgp)->ldg == (endldg - 1)) { 3666 if ((*ldgp)->ldvp == NULL) { 3667 (*ldgp)->ldvp = *ldvp; 3668 *ngrps += 1; 3669 NXGE_DEBUG_MSG((NULL, INT_CTL, 3670 "==> nxge_ldgv_setup: ngrps %d", *ngrps)); 3671 } 3672 NXGE_DEBUG_MSG((NULL, INT_CTL, 3673 "==> nxge_ldgv_setup: ldvp $%p ngrps %d", 3674 *ldvp, *ngrps)); 3675 ++*ldvp; 3676 } else { 3677 (*ldgp)->ldvp = *ldvp; 3678 *ngrps += 1; 3679 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): " 3680 "ldv %d endldg %d ldg %d, ldvp $%p", 3681 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3682 (*ldvp) = ++*ldvp; 3683 (*ldgp) = ++*ldgp; 3684 NXGE_DEBUG_MSG((NULL, INT_CTL, 3685 "==> nxge_ldgv_setup: new ngrps %d", *ngrps)); 3686 } 3687 3688 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3689 "ldv %d ldvp $%p endldg %d ngrps %d", 3690 ldv, ldvp, endldg, *ngrps)); 3691 3692 NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup")); 3693 } 3694 3695 /* 3696 * Note: This function assumes the following distribution of mac 3697 * addresses among 4 ports in neptune: 3698 * 3699 * ------------- 3700 * 0| |0 - local-mac-address for fn 0 3701 * ------------- 3702 * 1| |1 - local-mac-address for fn 1 3703 * ------------- 3704 * 2| |2 - local-mac-address for fn 2 3705 * ------------- 3706 * 3| |3 - local-mac-address for fn 3 3707 * ------------- 3708 * | |4 - Start of alt. mac addr. for fn 0 3709 * | | 3710 * | | 3711 * | |10 3712 * -------------- 3713 * | |11 - Start of alt. mac addr. for fn 1 3714 * | | 3715 * | | 3716 * | |17 3717 * -------------- 3718 * | |18 - Start of alt. mac addr. for fn 2 3719 * | | 3720 * | | 3721 * | |24 3722 * -------------- 3723 * | |25 - Start of alt. mac addr. for fn 3 3724 * | | 3725 * | | 3726 * | |31 3727 * -------------- 3728 * 3729 * For N2/NIU the mac addresses is from XAUI card. 3730 * 3731 * When 'compute_addrs' is true, the alternate mac addresses are computed 3732 * using the unique mac address as base. Otherwise the alternate addresses 3733 * are assigned from the list read off the 'mac-addresses' property. 3734 */ 3735 3736 static void 3737 nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs) 3738 { 3739 int slot; 3740 uint8_t func_num; 3741 uint16_t *base_mmac_addr; 3742 uint32_t alt_mac_ls4b; 3743 uint16_t *mmac_addr; 3744 uint32_t base_mac_ls4b; /* least significant 4 bytes */ 3745 nxge_mmac_t *mmac_info; 3746 npi_mac_addr_t mac_addr; 3747 3748 func_num = nxgep->function_num; 3749 base_mmac_addr = (uint16_t *)&nxgep->factaddr; 3750 mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info; 3751 3752 if (compute_addrs) { 3753 base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 | 3754 base_mmac_addr[2]; 3755 3756 if (nxgep->niu_type == N2_NIU) { 3757 /* ls4b of 1st altmac */ 3758 alt_mac_ls4b = base_mac_ls4b + 1; 3759 } else { /* Neptune */ 3760 alt_mac_ls4b = base_mac_ls4b + 3761 (nxgep->nports - func_num) + 3762 (func_num * (mmac_info->num_factory_mmac)); 3763 } 3764 } 3765 3766 /* Set flags for unique MAC */ 3767 mmac_info->mac_pool[0].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 3768 3769 /* Clear flags of all alternate MAC slots */ 3770 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 3771 if (slot <= mmac_info->num_factory_mmac) 3772 mmac_info->mac_pool[slot].flags = MMAC_VENDOR_ADDR; 3773 else 3774 mmac_info->mac_pool[slot].flags = 0; 3775 } 3776 3777 /* Generate and store factory alternate MACs */ 3778 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 3779 mmac_addr = (uint16_t *)&mmac_info->factory_mac_pool[slot]; 3780 if (compute_addrs) { 3781 mmac_addr[0] = base_mmac_addr[0]; 3782 mac_addr.w2 = mmac_addr[0]; 3783 3784 mmac_addr[1] = (alt_mac_ls4b >> 16) & 0x0FFFF; 3785 mac_addr.w1 = mmac_addr[1]; 3786 3787 mmac_addr[2] = alt_mac_ls4b & 0x0FFFF; 3788 mac_addr.w0 = mmac_addr[2]; 3789 3790 alt_mac_ls4b++; 3791 } else { 3792 mac_addr.w2 = mmac_addr[0]; 3793 mac_addr.w1 = mmac_addr[1]; 3794 mac_addr.w0 = mmac_addr[2]; 3795 } 3796 3797 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3798 "mac_pool_addr[%2x:%2x:%2x:%2x:%2x:%2x] npi_addr[%x%x%x]", 3799 mmac_info->factory_mac_pool[slot][0], 3800 mmac_info->factory_mac_pool[slot][1], 3801 mmac_info->factory_mac_pool[slot][2], 3802 mmac_info->factory_mac_pool[slot][3], 3803 mmac_info->factory_mac_pool[slot][4], 3804 mmac_info->factory_mac_pool[slot][5], 3805 mac_addr.w0, mac_addr.w1, mac_addr.w2)); 3806 /* 3807 * slot minus 1 because npi_mac_altaddr_entry expects 0 3808 * for the first alternate mac address. 3809 */ 3810 (void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 3811 NXGE_GET_PORT_NUM(func_num), slot - 1, &mac_addr); 3812 } 3813 /* Initialize the first two parameters for mmac kstat */ 3814 nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac; 3815 nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac; 3816 } 3817