1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_hio.h> 30 31 #include <inet/common.h> 32 #include <inet/mi.h> 33 #include <inet/nd.h> 34 35 extern uint64_t npi_debug_level; 36 37 #define NXGE_PARAM_MAC_RW \ 38 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 39 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 40 41 #define NXGE_PARAM_MAC_DONT_SHOW \ 42 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 43 44 #define NXGE_PARAM_RXDMA_RW \ 45 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 46 NXGE_PARAM_READ_PROP 47 48 #define NXGE_PARAM_RXDMA_RWC \ 49 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 50 NXGE_PARAM_READ_PROP 51 52 #define NXGE_PARAM_L2CLASS_CFG \ 53 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 54 NXGE_PARAM_NDD_WR_OK 55 56 #define NXGE_PARAM_CLASS_RWS \ 57 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 58 59 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 60 61 #define SET_RX_INTR_TIME_DISABLE 0 62 #define SET_RX_INTR_TIME_ENABLE 1 63 #define SET_RX_INTR_PKTS 2 64 65 #define BASE_ANY 0 66 #define BASE_BINARY 2 67 #define BASE_HEX 16 68 #define BASE_DECIMAL 10 69 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 70 #define ALL_FF_32 0xFFFFFFFFUL 71 72 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 73 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 74 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 75 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 76 77 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 78 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 79 80 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 81 ((mblk_t *)pmp)->b_wptr += plen; \ 82 rlen -= plen; \ 83 } 84 85 int nxge_param_set_mac(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_ether_usr(p_nxge_t, 92 queue_t *, mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ip_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_fflp_hash_init(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 102 mblk_t *, char *, caddr_t); 103 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 104 mblk_t *, char *, caddr_t); 105 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 108 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 109 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 110 p_mblk_t, caddr_t); 111 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 112 p_mblk_t, caddr_t); 113 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 118 p_mblk_t, caddr_t); 119 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 120 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 121 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 122 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 123 char *, caddr_t); 124 static int nxge_param_set_npi_debug_flag(p_nxge_t, 125 queue_t *, mblk_t *, char *, caddr_t); 126 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 127 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 128 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 129 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 130 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 131 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static void nxge_param_sync(p_nxge_t); 135 136 /* 137 * Global array of Neptune changable parameters. 138 * This array is initialized to correspond to the default 139 * Neptune 4 port configuration. This array would be copied 140 * into each port's parameter structure and modifed per 141 * fcode and nxge.conf configuration. Later, the parameters are 142 * exported to ndd to display and run-time configuration (at least 143 * some of them). 144 * 145 * Parameters with DONT_SHOW are not shown by ndd. 146 * 147 */ 148 149 static nxge_param_t nxge_param_arr[] = { 150 /* 151 * min max value old hw-name conf-name 152 */ 153 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 154 0, 999, 1000, 0, "instance", "instance"}, 155 156 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 157 0, 999, 1000, 0, "main-instance", "main_instance"}, 158 159 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 160 0, 3, 0, 0, "function-number", "function_number"}, 161 162 /* Partition Id */ 163 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 164 0, 8, 0, 0, "partition-id", "partition_id"}, 165 166 /* Read Write Permission Mode */ 167 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 168 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 169 170 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 171 0, 32, 0, 0, "version", "fw_version"}, 172 173 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 174 0, 32, 0, 0, "port-mode", "port_mode"}, 175 176 /* hw cfg types */ 177 /* control the DMA config of Neptune/NIU */ 178 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 179 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 180 "niu-cfg-type", "niu_cfg_type"}, 181 182 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 183 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 184 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 185 "tx-qcfg-type", "tx_qcfg_type"}, 186 187 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 188 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 189 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 190 "rx-qcfg-type", "rx_qcfg_type"}, 191 192 { nxge_param_get_mac, nxge_param_set_mac, 193 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 194 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 195 196 { nxge_param_get_mac, nxge_param_set_mac, 197 NXGE_PARAM_DONT_SHOW, 198 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 199 200 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 201 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 202 203 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 204 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 205 206 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 207 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 208 209 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 210 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 211 212 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 213 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 214 215 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 216 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 217 218 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 219 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 220 221 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 222 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 223 224 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 225 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 226 227 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 228 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 229 230 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 231 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 232 233 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 234 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 235 236 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 237 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 238 239 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 240 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 241 242 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 243 0, 255, 8, 8, "ipg0", "ipg0"}, 244 245 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 246 0, 255, 8, 8, "ipg1", "ipg1"}, 247 248 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 249 0, 255, 4, 4, "ipg2", "ipg2"}, 250 251 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 252 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 253 254 /* Transmit DMA channels */ 255 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 256 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 257 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 258 259 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 260 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 261 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 262 263 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 264 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 265 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 266 { nxge_param_get_txdma_info, NULL, 267 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 268 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 269 270 /* Receive DMA channels */ 271 { nxge_param_get_generic, NULL, 272 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 273 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 274 275 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 276 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 277 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 278 279 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 280 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 281 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 282 "rx-drr-weight", "rx_drr_weight"}, 283 284 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 285 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 286 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 287 288 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 289 NXGE_PARAM_DONT_SHOW, 290 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 291 292 { nxge_param_get_rxdma_info, NULL, 293 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 294 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 295 "rx-rbr-size", "rx_rbr_size"}, 296 297 { nxge_param_get_rxdma_info, NULL, 298 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 299 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 300 "rx-rcr-size", "rx_rcr_size"}, 301 302 { nxge_param_get_generic, nxge_param_set_port_rdc, 303 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 304 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 305 306 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 307 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 308 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 309 310 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 311 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 312 RXDMA_RCR_PTHRES_DEFAULT, 0, 313 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 314 315 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 316 NXGE_PARAM_DONT_SHOW, 317 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 318 319 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 320 NXGE_PARAM_DONT_SHOW, 321 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 322 323 { nxge_param_get_generic, nxge_param_set_grp_rdc, 324 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 325 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 326 327 { nxge_param_get_generic, nxge_param_set_grp_rdc, 328 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 329 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 330 331 { nxge_param_get_generic, nxge_param_set_grp_rdc, 332 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 333 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 334 335 { nxge_param_get_generic, nxge_param_set_grp_rdc, 336 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 337 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 338 339 { nxge_param_get_generic, nxge_param_set_grp_rdc, 340 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 341 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 342 343 { nxge_param_get_generic, nxge_param_set_grp_rdc, 344 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 345 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 346 347 { nxge_param_get_generic, nxge_param_set_grp_rdc, 348 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 349 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 350 351 { nxge_param_get_generic, nxge_param_set_grp_rdc, 352 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 353 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 354 355 { nxge_param_get_rxdma_rdcgrp_info, NULL, 356 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 357 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 358 359 /* Logical device groups */ 360 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 361 0, 63, 0, 0, "start-ldg", "start_ldg"}, 362 363 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 364 0, 64, 0, 0, "max-ldg", "max_ldg" }, 365 366 /* MAC table information */ 367 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 368 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 369 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 370 371 /* VLAN table information */ 372 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 373 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 374 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 375 376 { nxge_param_get_generic, NULL, 377 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 378 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 379 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 380 381 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 382 NXGE_PARAM_DONT_SHOW, 383 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 384 385 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 386 NXGE_PARAM_DONT_SHOW, 387 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 388 389 { nxge_param_get_generic, nxge_param_tcam_enable, 390 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 391 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 392 393 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 394 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 395 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 396 397 { nxge_param_get_generic, nxge_param_llc_snap_enable, 398 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 399 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 400 401 { nxge_param_get_generic, nxge_param_fflp_hash_init, 402 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 403 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 404 405 { nxge_param_get_generic, nxge_param_fflp_hash_init, 406 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 407 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 408 409 { nxge_param_get_generic, nxge_param_set_ether_usr, 410 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 411 0, ALL_FF_32, 0x0, 0, 412 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 413 414 { nxge_param_get_generic, nxge_param_set_ether_usr, 415 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 416 0, ALL_FF_32, 0x0, 0, 417 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 418 419 { nxge_param_get_generic, nxge_param_set_ip_usr, 420 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 421 0, ALL_FF_32, 0x0, 0, 422 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 423 424 { nxge_param_get_generic, nxge_param_set_ip_usr, 425 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 426 0, ALL_FF_32, 0x0, 0, 427 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 428 429 { nxge_param_get_generic, nxge_param_set_ip_usr, 430 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 431 0, ALL_FF_32, 0x0, 0, 432 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 433 434 { nxge_param_get_generic, nxge_param_set_ip_usr, 435 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 436 0, ALL_FF_32, 0x0, 0, 437 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 438 439 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 440 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 441 0, ALL_FF_32, 0x0, 0, 442 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 443 444 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 445 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 446 0, ALL_FF_32, 0x0, 0, 447 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 448 449 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 450 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 451 0, ALL_FF_32, 0x0, 0, 452 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 453 454 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 455 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 456 0, ALL_FF_32, 0x0, 0, 457 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 458 459 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 460 NXGE_PARAM_CLASS_RWS, 461 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 462 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 463 464 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 465 NXGE_PARAM_CLASS_RWS, 466 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 467 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 468 469 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 470 NXGE_PARAM_CLASS_RWS, 471 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 472 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 473 474 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 475 NXGE_PARAM_CLASS_RWS, 476 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 477 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 478 479 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 480 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 481 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 482 483 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 484 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 485 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 486 487 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 488 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 489 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 490 491 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 492 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 493 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 494 495 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 496 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 497 0ULL, ALL_FF_64, 0ULL, 0ULL, 498 "nxge-debug-flag", "nxge_debug_flag"}, 499 500 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 501 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 502 0ULL, ALL_FF_64, 0ULL, 0ULL, 503 "npi-debug-flag", "npi_debug_flag"}, 504 505 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 506 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 507 508 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 509 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 510 511 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 512 NXGE_PARAM_DONT_SHOW, 513 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 514 515 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 516 NXGE_PARAM_DONT_SHOW, 517 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 518 519 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 520 NXGE_PARAM_DONT_SHOW, 521 0, 0x0fffffff, 0x0fffffff, 0, 522 "dump-fflp-regs", "dump_fflp_regs"}, 523 524 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 525 NXGE_PARAM_DONT_SHOW, 526 0, 0x0fffffff, 0x0fffffff, 0, 527 "dump-vlan-table", "dump_vlan_table"}, 528 529 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 530 NXGE_PARAM_DONT_SHOW, 531 0, 0x0fffffff, 0x0fffffff, 0, 532 "dump-rdc-table", "dump_rdc_table"}, 533 534 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 535 NXGE_PARAM_DONT_SHOW, 536 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 537 538 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 539 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 540 }; 541 542 extern void *nxge_list; 543 544 void 545 nxge_get_param_soft_properties(p_nxge_t nxgep) 546 { 547 548 p_nxge_param_t param_arr; 549 uint_t prop_len; 550 int i, j; 551 uint32_t param_count; 552 uint32_t *int_prop_val; 553 554 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 555 556 param_arr = nxgep->param_arr; 557 param_count = nxgep->param_count; 558 for (i = 0; i < param_count; i++) { 559 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 560 continue; 561 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 562 continue; 563 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 564 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 565 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 566 nxgep->dip, 0, param_arr[i].fcode_name, 567 (int **)&int_prop_val, 568 (uint_t *)&prop_len) 569 == DDI_PROP_SUCCESS) { 570 uint32_t *cfg_value; 571 uint64_t prop_count; 572 573 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 574 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 575 #if defined(__i386) 576 cfg_value = 577 (uint32_t *)(int32_t)param_arr[i].value; 578 #else 579 cfg_value = (uint32_t *)param_arr[i].value; 580 #endif 581 for (j = 0; j < prop_len; j++) { 582 cfg_value[j] = int_prop_val[j]; 583 } 584 prop_count = prop_len; 585 param_arr[i].type |= 586 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 587 ddi_prop_free(int_prop_val); 588 } 589 continue; 590 } 591 592 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 593 param_arr[i].fcode_name, 594 (int **)&int_prop_val, 595 &prop_len) == DDI_PROP_SUCCESS) { 596 if ((*int_prop_val >= param_arr[i].minimum) && 597 (*int_prop_val <= param_arr[i].maximum)) 598 param_arr[i].value = *int_prop_val; 599 #ifdef NXGE_DEBUG_ERROR 600 else { 601 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 602 "nxge%d: 'prom' file parameter error\n", 603 nxgep->instance)); 604 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 605 "Parameter keyword '%s'" 606 " is outside valid range\n", 607 param_arr[i].name)); 608 } 609 #endif 610 ddi_prop_free(int_prop_val); 611 } 612 613 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 614 param_arr[i].name, 615 (int **)&int_prop_val, 616 &prop_len) == DDI_PROP_SUCCESS) { 617 if ((*int_prop_val >= param_arr[i].minimum) && 618 (*int_prop_val <= param_arr[i].maximum)) 619 param_arr[i].value = *int_prop_val; 620 #ifdef NXGE_DEBUG_ERROR 621 else { 622 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 623 "nxge%d: 'conf' file parameter error\n", 624 nxgep->instance)); 625 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 626 "Parameter keyword '%s'" 627 "is outside valid range\n", 628 param_arr[i].name)); 629 } 630 #endif 631 ddi_prop_free(int_prop_val); 632 } 633 } 634 } 635 636 static int 637 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 638 { 639 int status = B_TRUE; 640 int channel; 641 uint8_t grp; 642 char *prop_name; 643 char *end; 644 uint32_t name_chars; 645 646 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 647 "nxge_private_param_register %s", param_arr->name)); 648 649 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 650 return (B_TRUE); 651 652 prop_name = param_arr->name; 653 if (param_arr->type & NXGE_PARAM_RXDMA) { 654 if (strncmp("rxdma_intr", prop_name, 10) == 0) 655 return (B_TRUE); 656 name_chars = strlen("default_grp"); 657 if (strncmp("default_grp", prop_name, name_chars) == 0) { 658 prop_name += name_chars; 659 grp = mi_strtol(prop_name, &end, 10); 660 /* now check if this rdcgrp is in config */ 661 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 662 } 663 name_chars = strlen(prop_name); 664 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 665 return (B_TRUE); 666 } 667 return (B_FALSE); 668 } 669 670 if (param_arr->type & NXGE_PARAM_TXDMA) { 671 name_chars = strlen("txdma"); 672 if (strncmp("txdma", prop_name, name_chars) == 0) { 673 prop_name += name_chars; 674 channel = mi_strtol(prop_name, &end, 10); 675 /* now check if this rdc is in config */ 676 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 677 " nxge_private_param_register: %d", 678 channel)); 679 return (nxge_check_txdma_port_member(nxgep, channel)); 680 } 681 return (B_FALSE); 682 } 683 684 status = B_FALSE; 685 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 686 687 return (status); 688 } 689 690 void 691 nxge_setup_param(p_nxge_t nxgep) 692 { 693 p_nxge_param_t param_arr; 694 int i; 695 pfi_t set_pfi; 696 697 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 698 699 /* 700 * Make sure the param_instance is set to a valid device instance. 701 */ 702 if (nxge_param_arr[param_instance].value == 1000) 703 nxge_param_arr[param_instance].value = nxgep->instance; 704 705 param_arr = nxgep->param_arr; 706 param_arr[param_instance].value = nxgep->instance; 707 param_arr[param_function_number].value = nxgep->function_num; 708 709 for (i = 0; i < nxgep->param_count; i++) { 710 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 711 (nxge_private_param_register(nxgep, 712 ¶m_arr[i]) == B_FALSE)) { 713 param_arr[i].setf = NULL; 714 param_arr[i].getf = NULL; 715 } 716 717 if (param_arr[i].type & NXGE_PARAM_CMPLX) 718 param_arr[i].setf = NULL; 719 720 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 721 param_arr[i].setf = NULL; 722 param_arr[i].getf = NULL; 723 } 724 725 set_pfi = (pfi_t)param_arr[i].setf; 726 727 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 728 set_pfi = NULL; 729 } 730 731 } 732 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 733 } 734 735 void 736 nxge_init_param(p_nxge_t nxgep) 737 { 738 p_nxge_param_t param_arr; 739 int i, alloc_size; 740 uint64_t alloc_count; 741 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 742 /* 743 * Make sure the param_instance is set to a valid device instance. 744 */ 745 if (nxge_param_arr[param_instance].value == 1000) 746 nxge_param_arr[param_instance].value = nxgep->instance; 747 748 param_arr = nxgep->param_arr; 749 if (param_arr == NULL) { 750 param_arr = (p_nxge_param_t) 751 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 752 } 753 754 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 755 param_arr[i] = nxge_param_arr[i]; 756 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 757 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 758 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 759 alloc_size = alloc_count * sizeof (uint64_t); 760 param_arr[i].value = 761 #if defined(__i386) 762 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 763 KM_SLEEP); 764 #else 765 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 766 #endif 767 param_arr[i].old_value = 768 #if defined(__i386) 769 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 770 KM_SLEEP); 771 #else 772 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 773 #endif 774 param_arr[i].type |= 775 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 776 } 777 } 778 779 nxgep->param_arr = param_arr; 780 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 781 782 nxge_param_sync(nxgep); 783 784 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 785 nxgep->param_count)); 786 } 787 788 void 789 nxge_destroy_param(p_nxge_t nxgep) 790 { 791 int i; 792 uint64_t free_size, free_count; 793 794 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 795 796 if (nxgep->param_arr == NULL) 797 return; 798 /* 799 * Make sure the param_instance is set to a valid device instance. 800 */ 801 if (nxge_param_arr[param_instance].value == nxgep->instance) { 802 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 803 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 804 (i != nxgep->instance)) 805 break; 806 } 807 nxge_param_arr[param_instance].value = i; 808 } 809 810 for (i = 0; i < nxgep->param_count; i++) 811 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 812 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 813 free_count = ((nxgep->param_arr[i].type & 814 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 815 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 816 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 817 free_size = sizeof (uint64_t) * free_count; 818 #if defined(__i386) 819 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 820 free_size); 821 #else 822 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 823 #endif 824 #if defined(__i386) 825 KMEM_FREE((void *)(uint32_t) 826 nxgep->param_arr[i].old_value, free_size); 827 #else 828 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 829 free_size); 830 #endif 831 } 832 833 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 834 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 835 } 836 837 /* 838 * Extracts the value from the 'nxge' parameter array and prints the 839 * parameter value. cp points to the required parameter. 840 */ 841 842 /* ARGSUSED */ 843 int 844 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 845 { 846 p_nxge_param_t pa = (p_nxge_param_t)cp; 847 848 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 849 "==> nxge_param_get_generic name %s ", pa->name)); 850 851 if (pa->value > 0xffffffff) 852 (void) mi_mpprintf(mp, "%x%x", 853 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 854 else 855 (void) mi_mpprintf(mp, "%x", (int)pa->value); 856 857 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 858 return (0); 859 } 860 861 /* ARGSUSED */ 862 static int 863 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 864 { 865 p_nxge_param_t pa = (p_nxge_param_t)cp; 866 867 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 868 869 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 870 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 871 return (0); 872 } 873 874 /* ARGSUSED */ 875 static int 876 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 877 { 878 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 879 880 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 881 nxgep->instance, nxgep->vpd_info.ver); 882 883 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 884 return (0); 885 } 886 887 /* ARGSUSED */ 888 static int 889 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 890 { 891 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 892 893 switch (nxgep->mac.portmode) { 894 case PORT_1G_COPPER: 895 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 896 nxgep->instance, 897 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 898 break; 899 case PORT_1G_FIBER: 900 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 901 nxgep->instance, 902 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 903 break; 904 case PORT_10G_COPPER: 905 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 906 "%s\n", nxgep->instance, 907 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 908 break; 909 case PORT_10G_FIBER: 910 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 911 nxgep->instance, 912 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 913 break; 914 case PORT_10G_SERDES: 915 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 916 "%s\n", nxgep->instance, 917 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 918 break; 919 case PORT_1G_SERDES: 920 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 921 nxgep->instance, 922 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 923 break; 924 case PORT_1G_RGMII_FIBER: 925 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 926 "Fiber %s\n", nxgep->instance, 927 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 928 break; 929 case PORT_HSP_MODE: 930 (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 931 "PHY, Currently NOT present\n", nxgep->instance); 932 break; 933 case PORT_10G_TN1010: 934 (void) mi_mpprintf(mp, "Port mode for nxge%d:" 935 " 10G Copper with TN1010 %s\n", nxgep->instance, 936 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 937 break; 938 case PORT_1G_TN1010: 939 (void) mi_mpprintf(mp, "Port mode for nxge%d:" 940 " 1G Copper with TN1010 %s\n", nxgep->instance, 941 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 942 break; 943 default: 944 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 945 nxgep->instance, 946 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 947 break; 948 } 949 950 (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 951 nxgep->instance, 952 nxgep->soft_lso_enable ? "enable" : "disable"); 953 954 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 955 return (0); 956 } 957 958 /* ARGSUSED */ 959 int 960 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 961 { 962 963 uint_t print_len, buf_len; 964 p_mblk_t np; 965 966 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 967 int tdc; 968 969 nxge_grp_set_t *set; 970 971 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 972 973 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 974 nxgep->function_num); 975 976 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 977 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 978 return (0); 979 } 980 981 buf_len = buff_alloc_size; 982 mp->b_cont = np; 983 print_len = 0; 984 985 ((mblk_t *)np)->b_wptr += print_len; 986 buf_len -= print_len; 987 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 988 "TDC\t HW TDC\t\n"); 989 ((mblk_t *)np)->b_wptr += print_len; 990 buf_len -= print_len; 991 992 set = &nxgep->tx_set; 993 for (tdc = 0; tdc < NXGE_MAX_RDCS; tdc++) { 994 if ((1 << tdc) & set->owned.map) { 995 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 996 buf_len, "%d\n", tdc); 997 ((mblk_t *)np)->b_wptr += print_len; 998 buf_len -= print_len; 999 } 1000 } 1001 1002 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 1003 return (0); 1004 } 1005 1006 /* ARGSUSED */ 1007 int 1008 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1009 { 1010 uint_t print_len, buf_len; 1011 p_mblk_t np; 1012 int rdc; 1013 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1014 p_nxge_hw_pt_cfg_t p_cfgp; 1015 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1016 p_rx_rcr_rings_t rx_rcr_rings; 1017 p_rx_rcr_ring_t *rcr_rings; 1018 p_rx_rbr_rings_t rx_rbr_rings; 1019 p_rx_rbr_ring_t *rbr_rings; 1020 nxge_grp_set_t *set; 1021 1022 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1023 1024 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1025 nxgep->function_num); 1026 1027 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1028 /* The following may work even if we cannot get a large buf. */ 1029 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1030 return (0); 1031 } 1032 1033 buf_len = buff_alloc_size; 1034 mp->b_cont = np; 1035 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1036 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1037 1038 rx_rcr_rings = nxgep->rx_rcr_rings; 1039 rcr_rings = rx_rcr_rings->rcr_rings; 1040 rx_rbr_rings = nxgep->rx_rbr_rings; 1041 rbr_rings = rx_rbr_rings->rbr_rings; 1042 1043 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1044 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 1045 1046 ((mblk_t *)np)->b_wptr += print_len; 1047 buf_len -= print_len; 1048 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1049 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1050 "chunks\t RCR ptr\n"); 1051 1052 ((mblk_t *)np)->b_wptr += print_len; 1053 buf_len -= print_len; 1054 1055 set = &nxgep->rx_set; 1056 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1057 if ((1 << rdc) & set->owned.map) { 1058 print_len = snprintf((char *) 1059 ((mblk_t *)np)->b_wptr, buf_len, 1060 " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1061 rdc, 1062 p_dma_cfgp->rcr_timeout[rdc], 1063 p_dma_cfgp->rcr_threshold[rdc], 1064 rbr_rings[rdc], 1065 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1066 ((mblk_t *)np)->b_wptr += print_len; 1067 buf_len -= print_len; 1068 } 1069 } 1070 1071 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1072 return (0); 1073 } 1074 1075 /* ARGSUSED */ 1076 int 1077 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1078 p_mblk_t mp, caddr_t cp) 1079 { 1080 uint_t print_len, buf_len; 1081 p_mblk_t np; 1082 int offset, rdc, i, rdc_grp; 1083 p_nxge_rdc_grp_t rdc_grp_p; 1084 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1085 p_nxge_hw_pt_cfg_t p_cfgp; 1086 1087 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1088 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1089 "==> nxge_param_get_rxdma_rdcgrp_info")); 1090 1091 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1092 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1093 1094 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1095 nxgep->function_num); 1096 1097 rdc_grp = p_cfgp->def_mac_rxdma_grpid; 1098 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1099 /* The following may work even if we cannot get a large buf. */ 1100 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1101 return (0); 1102 } 1103 1104 buf_len = buff_alloc_size; 1105 mp->b_cont = np; 1106 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1107 "Total RDC Groups\t %d \n" 1108 "default RDC group\t %d\n", 1109 p_cfgp->max_rdc_grpids, 1110 p_cfgp->def_mac_rxdma_grpid); 1111 1112 ((mblk_t *)np)->b_wptr += print_len; 1113 buf_len -= print_len; 1114 1115 for (i = 0; i < NXGE_MAX_RDCS; i++) { 1116 if (p_cfgp->grpids[i]) { 1117 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1118 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1119 buf_len, 1120 "\nRDC Group Info for Group [%d] %d\n" 1121 "RDC Count %d\tstart RDC %d\n" 1122 "RDC Group Population Information" 1123 " (offsets 0 - 15)\n", 1124 i, rdc_grp, rdc_grp_p->max_rdcs, 1125 rdc_grp_p->start_rdc); 1126 1127 ((mblk_t *)np)->b_wptr += print_len; 1128 buf_len -= print_len; 1129 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1130 buf_len, "\n"); 1131 ((mblk_t *)np)->b_wptr += print_len; 1132 buf_len -= print_len; 1133 1134 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1135 print_len = snprintf( 1136 (char *)((mblk_t *)np)->b_wptr, 1137 buf_len, "[%d]=%d ", rdc, 1138 rdc_grp_p->start_rdc + rdc); 1139 ((mblk_t *)np)->b_wptr += print_len; 1140 buf_len -= print_len; 1141 } 1142 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1143 buf_len, "\n"); 1144 ((mblk_t *)np)->b_wptr += print_len; 1145 buf_len -= print_len; 1146 1147 for (offset = 0; offset < 16; offset++) { 1148 print_len = snprintf( 1149 (char *)((mblk_t *)np)->b_wptr, 1150 buf_len, " %c", 1151 rdc_grp_p->map & (1 << offset) ? 1152 '1' : '0'); 1153 ((mblk_t *)np)->b_wptr += print_len; 1154 buf_len -= print_len; 1155 } 1156 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1157 buf_len, "\n"); 1158 ((mblk_t *)np)->b_wptr += print_len; 1159 buf_len -= print_len; 1160 } 1161 } 1162 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1163 "<== nxge_param_get_rxdma_rdcgrp_info")); 1164 return (0); 1165 } 1166 1167 int 1168 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1169 { 1170 p_mblk_t tmp; 1171 1172 tmp = mp; 1173 while (tmp->b_cont) 1174 tmp = tmp->b_cont; 1175 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1176 tmp->b_cont = allocb(1024, BPRI_HI); 1177 tmp = tmp->b_cont; 1178 if (!tmp) 1179 return (ENOMEM); 1180 } 1181 1182 *nmp = tmp; 1183 return (0); 1184 } 1185 1186 1187 /* ARGSUSED */ 1188 int 1189 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1190 char *value, caddr_t cp) 1191 { 1192 char *end; 1193 uint32_t new_value; 1194 p_nxge_param_t pa = (p_nxge_param_t)cp; 1195 1196 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1197 new_value = (uint32_t)mi_strtol(value, &end, 10); 1198 if (end == value || new_value < pa->minimum || 1199 new_value > pa->maximum) { 1200 return (EINVAL); 1201 } 1202 pa->value = new_value; 1203 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1204 return (0); 1205 } 1206 1207 1208 /* ARGSUSED */ 1209 int 1210 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1211 char *value, caddr_t cp) 1212 { 1213 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1214 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1215 return (0); 1216 } 1217 1218 1219 /* ARGSUSED */ 1220 int 1221 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1222 char *value, caddr_t cp) 1223 { 1224 char *end; 1225 uint32_t new_value; 1226 int status = 0; 1227 p_nxge_param_t pa = (p_nxge_param_t)cp; 1228 1229 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1230 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1231 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1232 return (EINVAL); 1233 } 1234 1235 if (pa->value != new_value) { 1236 pa->old_value = pa->value; 1237 pa->value = new_value; 1238 } 1239 1240 if (!nxge_param_link_update(nxgep)) { 1241 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1242 " false ret from nxge_param_link_update")); 1243 status = EINVAL; 1244 } 1245 1246 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1247 return (status); 1248 } 1249 1250 /* ARGSUSED */ 1251 int 1252 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1253 char *value, caddr_t cp) 1254 { 1255 char *end; 1256 uint32_t cfg_value; 1257 p_nxge_param_t pa = (p_nxge_param_t)cp; 1258 1259 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1260 1261 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1262 1263 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1264 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1265 return (EINVAL); 1266 } 1267 1268 if ((pa->value != cfg_value)) { 1269 pa->old_value = pa->value; 1270 pa->value = cfg_value; 1271 nxgep->intr_threshold = pa->value; 1272 } 1273 1274 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1275 return (0); 1276 } 1277 1278 /* ARGSUSED */ 1279 int 1280 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1281 char *value, caddr_t cp) 1282 { 1283 char *end; 1284 uint32_t cfg_value; 1285 p_nxge_param_t pa = (p_nxge_param_t)cp; 1286 1287 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1288 1289 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1290 1291 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1292 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1293 return (EINVAL); 1294 } 1295 1296 if ((pa->value != cfg_value)) { 1297 pa->old_value = pa->value; 1298 pa->value = cfg_value; 1299 nxgep->intr_timeout = pa->value; 1300 } 1301 1302 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1303 return (0); 1304 } 1305 1306 /* ARGSUSED */ 1307 static int 1308 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1309 mblk_t *mp, char *value, caddr_t cp) 1310 { 1311 char *end; 1312 uint32_t status = 0, cfg_value; 1313 p_nxge_param_t pa = (p_nxge_param_t)cp; 1314 uint32_t cfg_it = B_FALSE; 1315 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1316 p_nxge_hw_pt_cfg_t p_cfgp; 1317 uint32_t *val_ptr, *old_val_ptr; 1318 nxge_param_map_t *mac_map; 1319 p_nxge_class_pt_cfg_t p_class_cfgp; 1320 nxge_mv_cfg_t *mac_host_info; 1321 1322 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1323 1324 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1325 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1326 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1327 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1328 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1329 1330 /* 1331 * now do decoding 1332 */ 1333 mac_map = (nxge_param_map_t *)&cfg_value; 1334 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1335 cfg_value, mac_map->param_id, mac_map->map_to)); 1336 1337 if ((mac_map->param_id < p_cfgp->max_macs) && 1338 p_cfgp->grpids[mac_map->map_to]) { 1339 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1340 " nxge_param_set_mac_rdcgrp mapping" 1341 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1342 #if defined(__i386) 1343 val_ptr = (uint32_t *)(uint32_t)pa->value; 1344 #else 1345 val_ptr = (uint32_t *)pa->value; 1346 #endif 1347 #if defined(__i386) 1348 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1349 #else 1350 old_val_ptr = (uint32_t *)pa->old_value; 1351 #endif 1352 if (val_ptr[mac_map->param_id] != cfg_value) { 1353 old_val_ptr[mac_map->param_id] = 1354 val_ptr[mac_map->param_id]; 1355 val_ptr[mac_map->param_id] = cfg_value; 1356 mac_host_info[mac_map->param_id].mpr_npr = 1357 mac_map->pref; 1358 mac_host_info[mac_map->param_id].flag = 1; 1359 mac_host_info[mac_map->param_id].rdctbl = 1360 mac_map->map_to; 1361 cfg_it = B_TRUE; 1362 } 1363 } else { 1364 return (EINVAL); 1365 } 1366 1367 if (cfg_it == B_TRUE) { 1368 status = nxge_logical_mac_assign_rdc_table(nxgep, 1369 (uint8_t)mac_map->param_id); 1370 if (status != NXGE_OK) 1371 return (EINVAL); 1372 } 1373 1374 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1375 return (0); 1376 } 1377 1378 /* ARGSUSED */ 1379 static int 1380 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1381 mblk_t *mp, char *value, caddr_t cp) 1382 { 1383 char *end; 1384 uint32_t status = 0, cfg_value; 1385 p_nxge_param_t pa = (p_nxge_param_t)cp; 1386 uint32_t cfg_it = B_FALSE; 1387 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1388 p_nxge_hw_pt_cfg_t p_cfgp; 1389 uint32_t *val_ptr, *old_val_ptr; 1390 nxge_param_map_t *vmap, *old_map; 1391 p_nxge_class_pt_cfg_t p_class_cfgp; 1392 uint64_t cfgd_vlans; 1393 int i, inc = 0, cfg_position; 1394 nxge_mv_cfg_t *vlan_tbl; 1395 1396 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1397 1398 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1399 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1400 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1401 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1402 1403 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1404 1405 /* now do decoding */ 1406 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1407 NXGE_PARAM_ARRAY_CNT_SHIFT); 1408 1409 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1410 /* 1411 * for now, we process only upto max 1412 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1413 * In the future, we may want to expand 1414 * the storage array and continue 1415 */ 1416 return (EINVAL); 1417 } 1418 1419 vmap = (nxge_param_map_t *)&cfg_value; 1420 if ((vmap->param_id) && 1421 (vmap->param_id < NXGE_MAX_VLANS) && 1422 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1423 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1424 "nxge_param_set_vlan_rdcgrp mapping" 1425 " id %d grp %d", 1426 vmap->param_id, vmap->map_to)); 1427 #if defined(__i386) 1428 val_ptr = (uint32_t *)(uint32_t)pa->value; 1429 #else 1430 val_ptr = (uint32_t *)pa->value; 1431 #endif 1432 #if defined(__i386) 1433 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1434 #else 1435 old_val_ptr = (uint32_t *)pa->old_value; 1436 #endif 1437 1438 /* search to see if this vlan id is already configured */ 1439 for (i = 0; i < cfgd_vlans; i++) { 1440 old_map = (nxge_param_map_t *)&val_ptr[i]; 1441 if ((old_map->param_id == 0) || 1442 (vmap->param_id == old_map->param_id) || 1443 (vlan_tbl[vmap->param_id].flag)) { 1444 cfg_position = i; 1445 break; 1446 } 1447 } 1448 1449 if (cfgd_vlans == 0) { 1450 cfg_position = 0; 1451 inc++; 1452 } 1453 1454 if (i == cfgd_vlans) { 1455 cfg_position = i; 1456 inc++; 1457 } 1458 1459 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1460 "set_vlan_rdcgrp mapping" 1461 " i %d cfgd_vlans %llx position %d ", 1462 i, cfgd_vlans, cfg_position)); 1463 if (val_ptr[cfg_position] != cfg_value) { 1464 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1465 val_ptr[cfg_position] = cfg_value; 1466 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1467 vlan_tbl[vmap->param_id].flag = 1; 1468 vlan_tbl[vmap->param_id].rdctbl = 1469 vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 1470 cfg_it = B_TRUE; 1471 if (inc) { 1472 cfgd_vlans++; 1473 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1474 pa->type |= (cfgd_vlans << 1475 NXGE_PARAM_ARRAY_CNT_SHIFT); 1476 1477 } 1478 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1479 "after: param_set_vlan_rdcgrp " 1480 " cfg_vlans %llx position %d \n", 1481 cfgd_vlans, cfg_position)); 1482 } 1483 } else { 1484 return (EINVAL); 1485 } 1486 1487 if (cfg_it == B_TRUE) { 1488 status = nxge_fflp_config_vlan_table(nxgep, 1489 (uint16_t)vmap->param_id); 1490 if (status != NXGE_OK) 1491 return (EINVAL); 1492 } 1493 1494 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1495 return (0); 1496 } 1497 1498 /* ARGSUSED */ 1499 static int 1500 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1501 mblk_t *mp, caddr_t cp) 1502 { 1503 1504 uint_t print_len, buf_len; 1505 p_mblk_t np; 1506 int i; 1507 uint32_t *val_ptr; 1508 nxge_param_map_t *vmap; 1509 p_nxge_param_t pa = (p_nxge_param_t)cp; 1510 p_nxge_class_pt_cfg_t p_class_cfgp; 1511 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1512 p_nxge_hw_pt_cfg_t p_cfgp; 1513 uint64_t cfgd_vlans = 0; 1514 nxge_mv_cfg_t *vlan_tbl; 1515 int buff_alloc_size = 1516 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1517 1518 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1519 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1520 nxgep->function_num); 1521 1522 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1523 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1524 return (0); 1525 } 1526 1527 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1528 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1529 1530 buf_len = buff_alloc_size; 1531 mp->b_cont = np; 1532 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1533 NXGE_PARAM_ARRAY_CNT_SHIFT; 1534 1535 i = (int)cfgd_vlans; 1536 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1537 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1538 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1539 "Configured VLANs %d\n" 1540 "VLAN ID\t RDC GRP (Actual/Port)\t" 1541 " Prefernce\n", i); 1542 ((mblk_t *)np)->b_wptr += print_len; 1543 buf_len -= print_len; 1544 #if defined(__i386) 1545 val_ptr = (uint32_t *)(uint32_t)pa->value; 1546 #else 1547 val_ptr = (uint32_t *)pa->value; 1548 #endif 1549 1550 for (i = 0; i < cfgd_vlans; i++) { 1551 vmap = (nxge_param_map_t *)&val_ptr[i]; 1552 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1553 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1554 buf_len, 1555 " %d\t\t %d/%d\t\t %d\n", 1556 vmap->param_id, 1557 vlan_tbl[vmap->param_id].rdctbl, 1558 vlan_tbl[vmap->param_id].rdctbl - 1559 p_cfgp->def_mac_rxdma_grpid, 1560 vlan_tbl[vmap->param_id].mpr_npr); 1561 ((mblk_t *)np)->b_wptr += print_len; 1562 buf_len -= print_len; 1563 } 1564 } 1565 1566 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1567 return (0); 1568 } 1569 1570 /* ARGSUSED */ 1571 static int 1572 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1573 mblk_t *mp, caddr_t cp) 1574 { 1575 uint_t print_len, buf_len; 1576 p_mblk_t np; 1577 int i; 1578 p_nxge_class_pt_cfg_t p_class_cfgp; 1579 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1580 p_nxge_hw_pt_cfg_t p_cfgp; 1581 nxge_mv_cfg_t *mac_host_info; 1582 1583 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1584 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1585 (void) mi_mpprintf(mp, 1586 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1587 nxgep->function_num); 1588 1589 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1590 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1591 return (0); 1592 } 1593 1594 buf_len = buff_alloc_size; 1595 mp->b_cont = np; 1596 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1597 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1598 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1599 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1600 print_len = snprintf((char *)np->b_wptr, buf_len, 1601 "MAC ID\t RDC GRP (Actual/Port)\t" 1602 " Prefernce\n"); 1603 ((mblk_t *)np)->b_wptr += print_len; 1604 buf_len -= print_len; 1605 for (i = 0; i < p_cfgp->max_macs; i++) { 1606 if (mac_host_info[i].flag) { 1607 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1608 buf_len, 1609 " %d\t %d/%d\t\t %d\n", 1610 i, mac_host_info[i].rdctbl, 1611 mac_host_info[i].rdctbl - 1612 p_cfgp->def_mac_rxdma_grpid, 1613 mac_host_info[i].mpr_npr); 1614 ((mblk_t *)np)->b_wptr += print_len; 1615 buf_len -= print_len; 1616 } 1617 } 1618 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1619 "Done Info Dumping \n"); 1620 ((mblk_t *)np)->b_wptr += print_len; 1621 buf_len -= print_len; 1622 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1623 return (0); 1624 } 1625 1626 /* ARGSUSED */ 1627 static int 1628 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1629 mblk_t *mp, char *value, caddr_t cp) 1630 { 1631 uint32_t status = 0, cfg_value; 1632 p_nxge_param_t pa = (p_nxge_param_t)cp; 1633 uint32_t cfg_it = B_FALSE; 1634 char *end; 1635 1636 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1637 1638 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1639 if (pa->value != cfg_value) { 1640 pa->old_value = pa->value; 1641 pa->value = cfg_value; 1642 cfg_it = B_TRUE; 1643 } 1644 1645 if (cfg_it == B_TRUE) { 1646 if (pa->value) 1647 status = nxge_fflp_config_tcam_enable(nxgep); 1648 else 1649 status = nxge_fflp_config_tcam_disable(nxgep); 1650 if (status != NXGE_OK) 1651 return (EINVAL); 1652 } 1653 1654 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1655 return (0); 1656 } 1657 1658 /* ARGSUSED */ 1659 static int 1660 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1661 mblk_t *mp, char *value, caddr_t cp) 1662 { 1663 uint32_t status = 0, cfg_value; 1664 p_nxge_param_t pa = (p_nxge_param_t)cp; 1665 uint32_t cfg_it = B_FALSE; 1666 char *end; 1667 1668 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1669 1670 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1671 if (pa->value != cfg_value) { 1672 pa->old_value = pa->value; 1673 pa->value = cfg_value; 1674 cfg_it = B_TRUE; 1675 } 1676 1677 if (cfg_it == B_TRUE) { 1678 if (pa->value) 1679 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1680 else 1681 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1682 if (status != NXGE_OK) 1683 return (EINVAL); 1684 } 1685 1686 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1687 return (0); 1688 } 1689 1690 /* ARGSUSED */ 1691 static int 1692 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1693 mblk_t *mp, char *value, caddr_t cp) 1694 { 1695 char *end; 1696 uint32_t status = 0, cfg_value; 1697 p_nxge_param_t pa = (p_nxge_param_t)cp; 1698 uint32_t cfg_it = B_FALSE; 1699 1700 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1701 1702 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1703 if (pa->value != cfg_value) { 1704 pa->old_value = pa->value; 1705 pa->value = cfg_value; 1706 cfg_it = B_TRUE; 1707 } 1708 1709 if (cfg_it == B_TRUE) { 1710 if (pa->value) 1711 status = nxge_fflp_config_tcam_enable(nxgep); 1712 else 1713 status = nxge_fflp_config_tcam_disable(nxgep); 1714 if (status != NXGE_OK) 1715 return (EINVAL); 1716 } 1717 1718 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1719 return (0); 1720 } 1721 1722 /* ARGSUSED */ 1723 static int 1724 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1725 mblk_t *mp, char *value, caddr_t cp) 1726 { 1727 char *end; 1728 uint8_t ether_class; 1729 uint32_t status = 0, cfg_value; 1730 p_nxge_param_t pa = (p_nxge_param_t)cp; 1731 uint8_t cfg_it = B_FALSE; 1732 1733 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1734 1735 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1736 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1737 return (EINVAL); 1738 } 1739 1740 if (pa->value != cfg_value) { 1741 pa->old_value = pa->value; 1742 pa->value = cfg_value; 1743 cfg_it = B_TRUE; 1744 } 1745 1746 /* do the actual hw setup */ 1747 if (cfg_it == B_TRUE) { 1748 ether_class = mi_strtol(pa->name, &end, 10); 1749 #ifdef lint 1750 ether_class = ether_class; 1751 #endif 1752 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1753 } 1754 1755 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1756 return (status); 1757 } 1758 1759 /* ARGSUSED */ 1760 static int 1761 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1762 mblk_t *mp, char *value, caddr_t cp) 1763 { 1764 char *end; 1765 tcam_class_t class; 1766 uint32_t status, cfg_value; 1767 p_nxge_param_t pa = (p_nxge_param_t)cp; 1768 uint32_t cfg_it = B_FALSE; 1769 1770 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1771 1772 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1773 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1774 return (EINVAL); 1775 } 1776 1777 if (pa->value != cfg_value) { 1778 pa->old_value = pa->value; 1779 pa->value = cfg_value; 1780 cfg_it = B_TRUE; 1781 } 1782 1783 /* do the actual hw setup with cfg_value. */ 1784 if (cfg_it == B_TRUE) { 1785 class = mi_strtol(pa->name, &end, 10); 1786 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1787 } 1788 1789 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1790 return (status); 1791 } 1792 1793 /* ARGSUSED */ 1794 static int 1795 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1796 { 1797 int i; 1798 int class_instance = param_class_opt_ip_usr4; 1799 p_nxge_param_t param_arr; 1800 1801 param_arr = nxgep->param_arr; 1802 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1803 if (strcmp(param_arr[class_instance].name, name) == 0) 1804 return (i); 1805 class_instance++; 1806 } 1807 return (-1); 1808 } 1809 1810 /* ARGSUSED */ 1811 int 1812 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1813 mblk_t *mp, char *value, caddr_t cp) 1814 { 1815 char *end; 1816 uint32_t status, cfg_value; 1817 p_nxge_param_t pa = (p_nxge_param_t)cp; 1818 tcam_class_t class; 1819 uint32_t cfg_it = B_FALSE; 1820 1821 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1822 1823 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1824 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1825 return (EINVAL); 1826 } 1827 1828 if (pa->value != cfg_value) { 1829 pa->old_value = pa->value; 1830 pa->value = cfg_value; 1831 cfg_it = B_TRUE; 1832 } 1833 1834 if (cfg_it == B_TRUE) { 1835 /* do the actual hw setup */ 1836 class = nxge_class_name_2value(nxgep, pa->name); 1837 if (class == -1) 1838 return (EINVAL); 1839 1840 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1841 if (status != NXGE_OK) 1842 return (EINVAL); 1843 } 1844 1845 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1846 return (0); 1847 } 1848 1849 /* ARGSUSED */ 1850 static int 1851 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1852 mblk_t *mp, caddr_t cp) 1853 { 1854 uint32_t status, cfg_value; 1855 p_nxge_param_t pa = (p_nxge_param_t)cp; 1856 tcam_class_t class; 1857 1858 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1859 1860 /* do the actual hw setup */ 1861 class = nxge_class_name_2value(nxgep, pa->name); 1862 if (class == -1) 1863 return (EINVAL); 1864 1865 cfg_value = 0; 1866 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1867 if (status != NXGE_OK) 1868 return (EINVAL); 1869 1870 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1871 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1872 1873 pa->value = cfg_value; 1874 (void) mi_mpprintf(mp, "%x", cfg_value); 1875 1876 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1877 return (0); 1878 } 1879 1880 /* ARGSUSED */ 1881 static int 1882 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1883 mblk_t *mp, char *value, caddr_t cp) 1884 { 1885 char *end; 1886 uint32_t status, cfg_value; 1887 p_nxge_param_t pa = (p_nxge_param_t)cp; 1888 tcam_class_t class; 1889 uint32_t cfg_it = B_FALSE; 1890 1891 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1892 1893 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1894 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1895 return (EINVAL); 1896 } 1897 1898 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1899 "nxge_param_fflp_hash_init value %x", cfg_value)); 1900 1901 if (pa->value != cfg_value) { 1902 pa->old_value = pa->value; 1903 pa->value = cfg_value; 1904 cfg_it = B_TRUE; 1905 } 1906 1907 if (cfg_it == B_TRUE) { 1908 char *h_name; 1909 1910 /* do the actual hw setup */ 1911 h_name = pa->name; 1912 h_name++; 1913 class = mi_strtol(h_name, &end, 10); 1914 switch (class) { 1915 case 1: 1916 status = nxge_fflp_set_hash1(nxgep, 1917 (uint32_t)pa->value); 1918 break; 1919 case 2: 1920 status = nxge_fflp_set_hash2(nxgep, 1921 (uint16_t)pa->value); 1922 break; 1923 1924 default: 1925 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1926 " nxge_param_fflp_hash_init" 1927 " %s Wrong hash var %d", 1928 pa->name, class)); 1929 return (EINVAL); 1930 } 1931 if (status != NXGE_OK) 1932 return (EINVAL); 1933 } 1934 1935 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1936 return (0); 1937 } 1938 1939 /* ARGSUSED */ 1940 static int 1941 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1942 mblk_t *mp, char *value, caddr_t cp) 1943 { 1944 char *end; 1945 uint32_t status = 0, cfg_value; 1946 p_nxge_param_t pa = (p_nxge_param_t)cp; 1947 uint32_t cfg_it = B_FALSE; 1948 int rdc_grp; 1949 uint8_t real_rdc; 1950 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1951 p_nxge_hw_pt_cfg_t p_cfgp; 1952 p_nxge_rdc_grp_t rdc_grp_p; 1953 1954 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1955 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1956 1957 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1958 1959 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1960 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1961 return (EINVAL); 1962 } 1963 1964 if (cfg_value >= p_cfgp->max_rdcs) { 1965 return (EINVAL); 1966 } 1967 1968 if (pa->value != cfg_value) { 1969 pa->old_value = pa->value; 1970 pa->value = cfg_value; 1971 cfg_it = B_TRUE; 1972 } 1973 1974 if (cfg_it == B_TRUE) { 1975 char *grp_name; 1976 grp_name = pa->name; 1977 grp_name += strlen("default-grp"); 1978 rdc_grp = mi_strtol(grp_name, &end, 10); 1979 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1980 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1981 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1982 cfg_value) == B_FALSE) { 1983 pa->value = pa->old_value; 1984 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1985 " nxge_param_set_grp_rdc" 1986 " %d read %d actual %d outof range", 1987 rdc_grp, cfg_value, real_rdc)); 1988 return (EINVAL); 1989 } 1990 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1991 real_rdc); 1992 if (status != NXGE_OK) 1993 return (EINVAL); 1994 } 1995 1996 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1997 return (0); 1998 } 1999 2000 /* ARGSUSED */ 2001 static int 2002 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 2003 mblk_t *mp, char *value, caddr_t cp) 2004 { 2005 char *end; 2006 uint32_t status = B_TRUE, cfg_value; 2007 p_nxge_param_t pa = (p_nxge_param_t)cp; 2008 uint32_t cfg_it = B_FALSE; 2009 2010 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2011 p_nxge_hw_pt_cfg_t p_cfgp; 2012 2013 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 2014 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2015 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2016 2017 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2018 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2019 return (EINVAL); 2020 } 2021 2022 if (pa->value != cfg_value) { 2023 if (cfg_value >= p_cfgp->max_rdcs) 2024 return (EINVAL); 2025 pa->old_value = pa->value; 2026 pa->value = cfg_value; 2027 cfg_it = B_TRUE; 2028 } 2029 2030 if (cfg_it == B_TRUE) { 2031 int rdc; 2032 if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2033 return (EINVAL); 2034 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2035 nxgep->function_num, rdc); 2036 if (status != NXGE_OK) 2037 return (EINVAL); 2038 } 2039 2040 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2041 return (0); 2042 } 2043 2044 /* ARGSUSED */ 2045 static int 2046 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2047 mblk_t *mp, char *value, caddr_t cp) 2048 { 2049 char *end; 2050 uint32_t status = 0; 2051 uint64_t cfg_value = 0; 2052 p_nxge_param_t pa = (p_nxge_param_t)cp; 2053 uint32_t cfg_it = B_FALSE; 2054 2055 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2056 cfg_value = mi_strtol(value, &end, BASE_HEX); 2057 2058 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2059 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2060 " nxge_param_set_nxge_debug_flag" 2061 " outof range %llx", cfg_value)); 2062 return (EINVAL); 2063 } 2064 if (pa->value != cfg_value) { 2065 pa->old_value = pa->value; 2066 pa->value = cfg_value; 2067 cfg_it = B_TRUE; 2068 } 2069 2070 if (cfg_it == B_TRUE) { 2071 nxgep->nxge_debug_level = pa->value; 2072 } 2073 2074 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2075 return (status); 2076 } 2077 2078 /* ARGSUSED */ 2079 static int 2080 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2081 { 2082 int status = 0; 2083 p_nxge_param_t pa = (p_nxge_param_t)cp; 2084 2085 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2086 2087 if (pa->value > 0xffffffff) 2088 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2089 (int)(pa->value & 0xffffffff)); 2090 else 2091 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2092 2093 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2094 return (status); 2095 } 2096 2097 /* ARGSUSED */ 2098 static int 2099 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2100 mblk_t *mp, char *value, caddr_t cp) 2101 { 2102 char *end; 2103 uint32_t status = 0; 2104 uint64_t cfg_value = 0; 2105 p_nxge_param_t pa; 2106 uint32_t cfg_it = B_FALSE; 2107 2108 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2109 cfg_value = mi_strtol(value, &end, BASE_HEX); 2110 pa = (p_nxge_param_t)cp; 2111 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2112 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2113 " outof range %llx", cfg_value)); 2114 return (EINVAL); 2115 } 2116 if (pa->value != cfg_value) { 2117 pa->old_value = pa->value; 2118 pa->value = cfg_value; 2119 cfg_it = B_TRUE; 2120 } 2121 2122 if (cfg_it == B_TRUE) { 2123 npi_debug_level = pa->value; 2124 } 2125 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2126 return (status); 2127 } 2128 2129 /* ARGSUSED */ 2130 static int 2131 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2132 { 2133 nxge_grp_set_t *set = &nxgep->rx_set; 2134 int rdc; 2135 2136 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2137 2138 if (!isLDOMguest(nxgep)) 2139 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2140 2141 for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2142 if ((1 << rdc) & set->owned.map) { 2143 (void) nxge_dump_rxdma_channel(nxgep, rdc); 2144 } 2145 } 2146 2147 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2148 return (0); 2149 } 2150 2151 /* ARGSUSED */ 2152 static int 2153 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2154 { 2155 nxge_grp_set_t *set = &nxgep->tx_set; 2156 int tdc; 2157 2158 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2159 2160 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2161 if ((1 << tdc) & set->owned.map) { 2162 (void) nxge_txdma_regs_dump(nxgep, tdc); 2163 } 2164 } 2165 2166 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2167 return (0); 2168 } 2169 2170 /* ARGSUSED */ 2171 static int 2172 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2173 { 2174 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2175 2176 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2177 2178 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2179 return (0); 2180 } 2181 2182 /* ARGSUSED */ 2183 static int 2184 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2185 { 2186 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2187 2188 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2189 nxgep->function_num); 2190 2191 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2192 return (0); 2193 } 2194 2195 /* ARGSUSED */ 2196 static int 2197 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2198 { 2199 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2200 2201 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2202 nxgep->function_num); 2203 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2204 return (0); 2205 } 2206 2207 /* ARGSUSED */ 2208 static int 2209 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2210 { 2211 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2212 2213 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2214 2215 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2216 return (0); 2217 } 2218 2219 /* ARGSUSED */ 2220 static int 2221 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2222 { 2223 uint8_t table; 2224 2225 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2226 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2227 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2228 table); 2229 } 2230 2231 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2232 return (0); 2233 } 2234 2235 typedef struct block_info { 2236 char *name; 2237 uint32_t offset; 2238 } block_info_t; 2239 2240 block_info_t reg_block[] = { 2241 {"PIO", PIO}, 2242 {"FZC_PIO", FZC_PIO}, 2243 {"FZC_XMAC", FZC_MAC}, 2244 {"FZC_IPP", FZC_IPP}, 2245 {"FFLP", FFLP}, 2246 {"FZC_FFLP", FZC_FFLP}, 2247 {"PIO_VADDR", PIO_VADDR}, 2248 {"ZCP", ZCP}, 2249 {"FZC_ZCP", FZC_ZCP}, 2250 {"DMC", DMC}, 2251 {"FZC_DMC", FZC_DMC}, 2252 {"TXC", TXC}, 2253 {"FZC_TXC", FZC_TXC}, 2254 {"PIO_LDSV", PIO_LDSV}, 2255 {"PIO_LDGIM", PIO_LDGIM}, 2256 {"PIO_IMASK0", PIO_IMASK0}, 2257 {"PIO_IMASK1", PIO_IMASK1}, 2258 {"FZC_PROM", FZC_PROM}, 2259 {"END", ALL_FF_32}, 2260 }; 2261 2262 /* ARGSUSED */ 2263 static int 2264 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2265 { 2266 uint_t print_len, buf_len; 2267 p_mblk_t np; 2268 int rdc, tdc, block; 2269 uint64_t base; 2270 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2271 p_nxge_hw_pt_cfg_t p_cfgp; 2272 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2273 p_tx_ring_t *tx_rings; 2274 p_rx_rcr_rings_t rx_rcr_rings; 2275 p_rx_rcr_ring_t *rcr_rings; 2276 p_rx_rbr_rings_t rx_rbr_rings; 2277 p_rx_rbr_ring_t *rbr_rings; 2278 2279 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2280 "==> nxge_param_dump_ptrs")); 2281 2282 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2283 nxgep->function_num); 2284 2285 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2286 /* The following may work even if we cannot get a large buf. */ 2287 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2288 return (0); 2289 } 2290 2291 buf_len = buff_alloc_size; 2292 mp->b_cont = np; 2293 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2294 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2295 2296 rx_rcr_rings = nxgep->rx_rcr_rings; 2297 rcr_rings = rx_rcr_rings->rcr_rings; 2298 rx_rbr_rings = nxgep->rx_rbr_rings; 2299 rbr_rings = rx_rbr_rings->rbr_rings; 2300 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2301 "nxgep (nxge_t) $%p\n" 2302 "dev_regs (dev_regs_t) $%p\n", 2303 nxgep, nxgep->dev_regs); 2304 2305 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2306 2307 /* do register pointers */ 2308 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2309 "reg base (npi_reg_ptr_t) $%p\t " 2310 "pci reg (npi_reg_ptr_t) $%p\n", 2311 nxgep->dev_regs->nxge_regp, 2312 nxgep->dev_regs->nxge_pciregp); 2313 2314 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2315 2316 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2317 "\nBlock \t Offset \n"); 2318 2319 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2320 block = 0; 2321 #if defined(__i386) 2322 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2323 #else 2324 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2325 #endif 2326 while (reg_block[block].offset != ALL_FF_32) { 2327 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2328 "%9s\t 0x%llx\n", 2329 reg_block[block].name, 2330 (unsigned long long)(reg_block[block].offset + base)); 2331 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2332 block++; 2333 } 2334 2335 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2336 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2337 "rbrp (rx_rbr_ring_t)\n"); 2338 2339 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2340 2341 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2342 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2343 " %d\t $%p\t\t $%p\n", 2344 rdc, rcr_rings[rdc], 2345 rbr_rings[rdc]); 2346 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2347 } 2348 2349 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2350 "\nTDC\t tdcp (tx_ring_t)\n"); 2351 2352 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2353 tx_rings = nxgep->tx_rings->rings; 2354 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 2355 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2356 " %d\t $%p\n", tdc, tx_rings[tdc]); 2357 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2358 } 2359 2360 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2361 2362 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2363 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2364 return (0); 2365 } 2366 2367 2368 /* ARGSUSED */ 2369 int 2370 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2371 { 2372 ND *nd; 2373 NDE *nde; 2374 char *rwtag; 2375 boolean_t get_ok, set_ok; 2376 size_t param_len; 2377 int status = 0; 2378 2379 nd = (ND *)param; 2380 if (!nd) 2381 return (ENOENT); 2382 2383 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2384 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2385 (nde->nde_get_pfi != NULL); 2386 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2387 (nde->nde_set_pfi != NULL); 2388 if (get_ok) { 2389 if (set_ok) 2390 rwtag = "read and write"; 2391 else 2392 rwtag = "read only"; 2393 } else if (set_ok) 2394 rwtag = "write only"; 2395 else { 2396 continue; 2397 } 2398 param_len = strlen(rwtag); 2399 param_len += strlen(nde->nde_name); 2400 param_len += 4; 2401 2402 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2403 } 2404 return (status); 2405 } 2406 2407 /* ARGSUSED */ 2408 int 2409 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2410 { 2411 return (EACCES); 2412 } 2413 2414 /* ARGSUSED */ 2415 int 2416 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2417 caddr_t data) 2418 { 2419 return (EACCES); 2420 } 2421 2422 boolean_t 2423 nxge_param_link_update(p_nxge_t nxgep) 2424 { 2425 p_nxge_param_t param_arr; 2426 nxge_param_index_t i; 2427 boolean_t update_xcvr; 2428 boolean_t update_dev; 2429 int instance; 2430 boolean_t status = B_TRUE; 2431 2432 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 2433 2434 param_arr = nxgep->param_arr; 2435 instance = nxgep->instance; 2436 update_xcvr = B_FALSE; 2437 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2438 update_xcvr |= param_arr[i].value; 2439 } 2440 2441 if (update_xcvr) { 2442 update_xcvr = B_FALSE; 2443 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2444 update_xcvr |= 2445 (param_arr[i].value != param_arr[i].old_value); 2446 param_arr[i].old_value = param_arr[i].value; 2447 } 2448 if (update_xcvr) { 2449 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2450 "==> nxge_param_link_update: update xcvr")); 2451 RW_ENTER_WRITER(&nxgep->filter_lock); 2452 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2453 (void) nxge_link_init(nxgep); 2454 (void) nxge_mac_init(nxgep); 2455 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2456 RW_EXIT(&nxgep->filter_lock); 2457 } 2458 } else { 2459 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2460 " no link capabilities.", instance); 2461 cmn_err(CE_WARN, " Restoring previous setting."); 2462 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2463 param_arr[i].value = param_arr[i].old_value; 2464 } 2465 2466 update_dev = B_FALSE; 2467 2468 if (update_dev) { 2469 RW_ENTER_WRITER(&nxgep->filter_lock); 2470 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2471 "==> nxge_param_link_update: update dev")); 2472 (void) nxge_rx_mac_disable(nxgep); 2473 (void) nxge_tx_mac_disable(nxgep); 2474 (void) nxge_tx_mac_enable(nxgep); 2475 (void) nxge_rx_mac_enable(nxgep); 2476 RW_EXIT(&nxgep->filter_lock); 2477 } 2478 2479 nxge_param_hw_update_exit: 2480 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2481 "<== nxge_param_link_update status = 0x%08x", status)); 2482 return (status); 2483 } 2484 2485 /* 2486 * synchronize the adv* and en* parameters. 2487 * 2488 * See comments in <sys/dld.h> for details of the *_en_* 2489 * parameters. The usage of ndd for setting adv parameters will 2490 * synchronize all the en parameters with the nxge parameters, 2491 * implicitly disabling any settings made via dladm. 2492 */ 2493 static void 2494 nxge_param_sync(p_nxge_t nxgep) 2495 { 2496 p_nxge_param_t param_arr; 2497 param_arr = nxgep->param_arr; 2498 2499 nxgep->param_en_pause = param_arr[param_anar_pause].value; 2500 nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 2501 nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 2502 nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 2503 } 2504 2505 /* ARGSUSED */ 2506 int 2507 nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 2508 { 2509 uint32_t status, cfg_value; 2510 p_nxge_param_t pa = (p_nxge_param_t)cp; 2511 tcam_class_t class; 2512 2513 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 2514 2515 /* do the actual hw setup */ 2516 class = nxge_class_name_2value(nxgep, pa->name); 2517 if (class == -1) 2518 return (EINVAL); 2519 2520 cfg_value = 0; 2521 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 2522 if (status != NXGE_OK) 2523 return (EINVAL); 2524 2525 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2526 "nxge_param_get_ip_opt_get %x ", cfg_value)); 2527 2528 pa->value = cfg_value; 2529 2530 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 2531 return (0); 2532 } 2533