1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 28 */ 29 #include <sys/nxge/nxge_impl.h> 30 #include <sys/nxge/nxge_hio.h> 31 #include <sys/nxge/nxge_rxdma.h> 32 #include <sys/pcie.h> 33 34 uint32_t nxge_use_partition = 0; /* debug partition flag */ 35 uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 36 uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 37 /* 38 * PSARC/2007/453 MSI-X interrupt limit override 39 * (This PSARC case is limited to MSI-X vectors 40 * and SPARC platforms only). 41 */ 42 #if defined(_BIG_ENDIAN) 43 uint32_t nxge_msi_enable = 2; 44 #else 45 uint32_t nxge_msi_enable = 1; 46 #endif 47 48 /* 49 * Software workaround for a Neptune (PCI-E) 50 * hardware interrupt bug which the hardware 51 * may generate spurious interrupts after the 52 * device interrupt handler was removed. If this flag 53 * is enabled, the driver will reset the 54 * hardware when devices are being detached. 55 */ 56 uint32_t nxge_peu_reset_enable = 0; 57 58 /* 59 * Software workaround for the hardware 60 * checksum bugs that affect packet transmission 61 * and receive: 62 * 63 * Usage of nxge_cksum_offload: 64 * 65 * (1) nxge_cksum_offload = 0 (default): 66 * - transmits packets: 67 * TCP: uses the hardware checksum feature. 68 * UDP: driver will compute the software checksum 69 * based on the partial checksum computed 70 * by the IP layer. 71 * - receives packets 72 * TCP: marks packets checksum flags based on hardware result. 73 * UDP: will not mark checksum flags. 74 * 75 * (2) nxge_cksum_offload = 1: 76 * - transmit packets: 77 * TCP/UDP: uses the hardware checksum feature. 78 * - receives packets 79 * TCP/UDP: marks packet checksum flags based on hardware result. 80 * 81 * (3) nxge_cksum_offload = 2: 82 * - The driver will not register its checksum capability. 83 * Checksum for both TCP and UDP will be computed 84 * by the stack. 85 * - The software LSO is not allowed in this case. 86 * 87 * (4) nxge_cksum_offload > 2: 88 * - Will be treated as it is set to 2 89 * (stack will compute the checksum). 90 * 91 * (5) If the hardware bug is fixed, this workaround 92 * needs to be updated accordingly to reflect 93 * the new hardware revision. 94 */ 95 uint32_t nxge_cksum_offload = 0; 96 97 /* 98 * Globals: tunable parameters (/etc/system or adb) 99 * 100 */ 101 uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 102 uint32_t nxge_rbr_spare_size = 0; 103 uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 104 uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 105 boolean_t nxge_no_msg = B_TRUE; /* control message display */ 106 uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 107 uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 108 uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 109 uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 110 uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 111 boolean_t nxge_jumbo_enable = B_FALSE; 112 uint16_t nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT; 113 uint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD; 114 nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 115 116 /* MAX LSO size */ 117 #define NXGE_LSO_MAXLEN 65535 118 uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 119 120 /* 121 * Debugging flags: 122 * nxge_no_tx_lb : transmit load balancing 123 * nxge_tx_lb_policy: 0 - TCP port (default) 124 * 3 - DEST MAC 125 */ 126 uint32_t nxge_no_tx_lb = 0; 127 uint32_t nxge_tx_lb_policy = NXGE_TX_LB_TCPUDP; 128 129 /* 130 * Add tunable to reduce the amount of time spent in the 131 * ISR doing Rx Processing. 132 */ 133 uint32_t nxge_max_rx_pkts = 1024; 134 135 /* 136 * Tunables to manage the receive buffer blocks. 137 * 138 * nxge_rx_threshold_hi: copy all buffers. 139 * nxge_rx_bcopy_size_type: receive buffer block size type. 140 * nxge_rx_threshold_lo: copy only up to tunable block size type. 141 */ 142 nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 143 nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 144 nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 145 146 /* Use kmem_alloc() to allocate data buffers. */ 147 #if defined(_BIG_ENDIAN) 148 uint32_t nxge_use_kmem_alloc = 1; 149 #else 150 uint32_t nxge_use_kmem_alloc = 0; 151 #endif 152 153 rtrace_t npi_rtracebuf; 154 155 /* 156 * The hardware sometimes fails to allow enough time for the link partner 157 * to send an acknowledgement for packets that the hardware sent to it. The 158 * hardware resends the packets earlier than it should be in those instances. 159 * This behavior caused some switches to acknowledge the wrong packets 160 * and it triggered the fatal error. 161 * This software workaround is to set the replay timer to a value 162 * suggested by the hardware team. 163 * 164 * PCI config space replay timer register: 165 * The following replay timeout value is 0xc 166 * for bit 14:18. 167 */ 168 #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 169 #define PCI_REPLAY_TIMEOUT_SHIFT 14 170 171 uint32_t nxge_set_replay_timer = 1; 172 uint32_t nxge_replay_timeout = 0xc; 173 174 /* 175 * The transmit serialization sometimes causes 176 * longer sleep before calling the driver transmit 177 * function as it sleeps longer than it should. 178 * The performace group suggests that a time wait tunable 179 * can be used to set the maximum wait time when needed 180 * and the default is set to 1 tick. 181 */ 182 uint32_t nxge_tx_serial_maxsleep = 1; 183 184 #if defined(sun4v) 185 /* 186 * Hypervisor N2/NIU services information. 187 */ 188 static hsvc_info_t niu_hsvc = { 189 HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 190 NIU_MINOR_VER, "nxge" 191 }; 192 193 static int nxge_hsvc_register(p_nxge_t); 194 #endif 195 196 /* 197 * Function Prototypes 198 */ 199 static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 200 static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 201 static void nxge_unattach(p_nxge_t); 202 static int nxge_quiesce(dev_info_t *); 203 204 #if NXGE_PROPERTY 205 static void nxge_remove_hard_properties(p_nxge_t); 206 #endif 207 208 /* 209 * These two functions are required by nxge_hio.c 210 */ 211 extern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr); 212 extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 213 extern void nxge_grp_cleanup(p_nxge_t nxge); 214 215 static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 216 217 static nxge_status_t nxge_setup_mutexes(p_nxge_t); 218 static void nxge_destroy_mutexes(p_nxge_t); 219 220 static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 221 static void nxge_unmap_regs(p_nxge_t nxgep); 222 #ifdef NXGE_DEBUG 223 static void nxge_test_map_regs(p_nxge_t nxgep); 224 #endif 225 226 static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 227 static nxge_status_t nxge_add_soft_intrs(p_nxge_t nxgep); 228 static void nxge_remove_intrs(p_nxge_t nxgep); 229 static void nxge_remove_soft_intrs(p_nxge_t nxgep); 230 231 static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 232 static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 233 static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 234 static void nxge_intrs_enable(p_nxge_t nxgep); 235 static void nxge_intrs_disable(p_nxge_t nxgep); 236 237 static void nxge_suspend(p_nxge_t); 238 static nxge_status_t nxge_resume(p_nxge_t); 239 240 static nxge_status_t nxge_setup_dev(p_nxge_t); 241 static void nxge_destroy_dev(p_nxge_t); 242 243 static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 244 static void nxge_free_mem_pool(p_nxge_t); 245 246 nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 247 static void nxge_free_rx_mem_pool(p_nxge_t); 248 249 nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 250 static void nxge_free_tx_mem_pool(p_nxge_t); 251 252 static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 253 struct ddi_dma_attr *, 254 size_t, ddi_device_acc_attr_t *, uint_t, 255 p_nxge_dma_common_t); 256 257 static void nxge_dma_mem_free(p_nxge_dma_common_t); 258 static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 259 260 static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 261 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 262 static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 263 264 static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 265 p_nxge_dma_common_t *, size_t); 266 static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 267 268 extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 269 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 270 static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 271 272 extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 273 p_nxge_dma_common_t *, 274 size_t); 275 static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 276 277 static int nxge_init_common_dev(p_nxge_t); 278 static void nxge_uninit_common_dev(p_nxge_t); 279 extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 280 char *, caddr_t); 281 282 /* 283 * The next declarations are for the GLDv3 interface. 284 */ 285 static int nxge_m_start(void *); 286 static void nxge_m_stop(void *); 287 static int nxge_m_unicst(void *, const uint8_t *); 288 static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 289 static int nxge_m_promisc(void *, boolean_t); 290 static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 291 static void nxge_m_resources(void *); 292 mblk_t *nxge_m_tx(void *arg, mblk_t *); 293 static nxge_status_t nxge_mac_register(p_nxge_t); 294 static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 295 mac_addr_slot_t slot); 296 void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, 297 boolean_t factory); 298 static int nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr); 299 static int nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr); 300 static int nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr); 301 static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 302 static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 303 uint_t, const void *); 304 static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 305 uint_t, uint_t, void *); 306 static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 307 const void *); 308 static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 309 void *); 310 static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 311 312 static void nxge_niu_peu_reset(p_nxge_t nxgep); 313 static void nxge_set_pci_replay_timeout(nxge_t *); 314 315 mac_priv_prop_t nxge_priv_props[] = { 316 {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 317 {"_adv_pause_cap", MAC_PROP_PERM_RW}, 318 {"_function_number", MAC_PROP_PERM_READ}, 319 {"_fw_version", MAC_PROP_PERM_READ}, 320 {"_port_mode", MAC_PROP_PERM_READ}, 321 {"_hot_swap_phy", MAC_PROP_PERM_READ}, 322 {"_accept_jumbo", MAC_PROP_PERM_RW}, 323 {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 324 {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 325 {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 326 {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 327 {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 328 {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 329 {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 330 {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 331 {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 332 {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 333 {"_soft_lso_enable", MAC_PROP_PERM_RW} 334 }; 335 336 #define NXGE_MAX_PRIV_PROPS \ 337 (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 338 339 #define NXGE_M_CALLBACK_FLAGS\ 340 (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 341 342 343 #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 344 #define MAX_DUMP_SZ 256 345 346 #define NXGE_M_CALLBACK_FLAGS \ 347 (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 348 349 mac_callbacks_t nxge_m_callbacks = { 350 NXGE_M_CALLBACK_FLAGS, 351 nxge_m_stat, 352 nxge_m_start, 353 nxge_m_stop, 354 nxge_m_promisc, 355 nxge_m_multicst, 356 nxge_m_unicst, 357 nxge_m_tx, 358 nxge_m_resources, 359 nxge_m_ioctl, 360 nxge_m_getcapab, 361 NULL, 362 NULL, 363 nxge_m_setprop, 364 nxge_m_getprop 365 }; 366 367 void 368 nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 369 370 /* PSARC/2007/453 MSI-X interrupt limit override. */ 371 #define NXGE_MSIX_REQUEST_10G 8 372 #define NXGE_MSIX_REQUEST_1G 2 373 static int nxge_create_msi_property(p_nxge_t); 374 375 /* 376 * These global variables control the message 377 * output. 378 */ 379 out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 380 uint64_t nxge_debug_level; 381 382 /* 383 * This list contains the instance structures for the Neptune 384 * devices present in the system. The lock exists to guarantee 385 * mutually exclusive access to the list. 386 */ 387 void *nxge_list = NULL; 388 389 void *nxge_hw_list = NULL; 390 nxge_os_mutex_t nxge_common_lock; 391 392 extern uint64_t npi_debug_level; 393 394 extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 395 extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 396 extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 397 extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 398 extern void nxge_fm_init(p_nxge_t, 399 ddi_device_acc_attr_t *, 400 ddi_device_acc_attr_t *, 401 ddi_dma_attr_t *); 402 extern void nxge_fm_fini(p_nxge_t); 403 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 404 405 /* 406 * Count used to maintain the number of buffers being used 407 * by Neptune instances and loaned up to the upper layers. 408 */ 409 uint32_t nxge_mblks_pending = 0; 410 411 /* 412 * Device register access attributes for PIO. 413 */ 414 static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 415 DDI_DEVICE_ATTR_V0, 416 DDI_STRUCTURE_LE_ACC, 417 DDI_STRICTORDER_ACC, 418 }; 419 420 /* 421 * Device descriptor access attributes for DMA. 422 */ 423 static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 424 DDI_DEVICE_ATTR_V0, 425 DDI_STRUCTURE_LE_ACC, 426 DDI_STRICTORDER_ACC 427 }; 428 429 /* 430 * Device buffer access attributes for DMA. 431 */ 432 static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 433 DDI_DEVICE_ATTR_V0, 434 DDI_STRUCTURE_BE_ACC, 435 DDI_STRICTORDER_ACC 436 }; 437 438 ddi_dma_attr_t nxge_desc_dma_attr = { 439 DMA_ATTR_V0, /* version number. */ 440 0, /* low address */ 441 0xffffffffffffffff, /* high address */ 442 0xffffffffffffffff, /* address counter max */ 443 #ifndef NIU_PA_WORKAROUND 444 0x100000, /* alignment */ 445 #else 446 0x2000, 447 #endif 448 0xfc00fc, /* dlim_burstsizes */ 449 0x1, /* minimum transfer size */ 450 0xffffffffffffffff, /* maximum transfer size */ 451 0xffffffffffffffff, /* maximum segment size */ 452 1, /* scatter/gather list length */ 453 (unsigned int) 1, /* granularity */ 454 0 /* attribute flags */ 455 }; 456 457 ddi_dma_attr_t nxge_tx_dma_attr = { 458 DMA_ATTR_V0, /* version number. */ 459 0, /* low address */ 460 0xffffffffffffffff, /* high address */ 461 0xffffffffffffffff, /* address counter max */ 462 #if defined(_BIG_ENDIAN) 463 0x2000, /* alignment */ 464 #else 465 0x1000, /* alignment */ 466 #endif 467 0xfc00fc, /* dlim_burstsizes */ 468 0x1, /* minimum transfer size */ 469 0xffffffffffffffff, /* maximum transfer size */ 470 0xffffffffffffffff, /* maximum segment size */ 471 5, /* scatter/gather list length */ 472 (unsigned int) 1, /* granularity */ 473 0 /* attribute flags */ 474 }; 475 476 ddi_dma_attr_t nxge_rx_dma_attr = { 477 DMA_ATTR_V0, /* version number. */ 478 0, /* low address */ 479 0xffffffffffffffff, /* high address */ 480 0xffffffffffffffff, /* address counter max */ 481 0x2000, /* alignment */ 482 0xfc00fc, /* dlim_burstsizes */ 483 0x1, /* minimum transfer size */ 484 0xffffffffffffffff, /* maximum transfer size */ 485 0xffffffffffffffff, /* maximum segment size */ 486 1, /* scatter/gather list length */ 487 (unsigned int) 1, /* granularity */ 488 DDI_DMA_RELAXED_ORDERING /* attribute flags */ 489 }; 490 491 ddi_dma_lim_t nxge_dma_limits = { 492 (uint_t)0, /* dlim_addr_lo */ 493 (uint_t)0xffffffff, /* dlim_addr_hi */ 494 (uint_t)0xffffffff, /* dlim_cntr_max */ 495 (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 496 0x1, /* dlim_minxfer */ 497 1024 /* dlim_speed */ 498 }; 499 500 dma_method_t nxge_force_dma = DVMA; 501 502 /* 503 * dma chunk sizes. 504 * 505 * Try to allocate the largest possible size 506 * so that fewer number of dma chunks would be managed 507 */ 508 #ifdef NIU_PA_WORKAROUND 509 size_t alloc_sizes [] = {0x2000}; 510 #else 511 size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 512 0x10000, 0x20000, 0x40000, 0x80000, 513 0x100000, 0x200000, 0x400000, 0x800000, 514 0x1000000, 0x2000000, 0x4000000}; 515 #endif 516 517 /* 518 * Translate "dev_t" to a pointer to the associated "dev_info_t". 519 */ 520 521 extern void nxge_get_environs(nxge_t *); 522 523 static int 524 nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 525 { 526 p_nxge_t nxgep = NULL; 527 int instance; 528 int status = DDI_SUCCESS; 529 uint8_t portn; 530 nxge_mmac_t *mmac_info; 531 p_nxge_param_t param_arr; 532 533 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 534 535 /* 536 * Get the device instance since we'll need to setup 537 * or retrieve a soft state for this instance. 538 */ 539 instance = ddi_get_instance(dip); 540 541 switch (cmd) { 542 case DDI_ATTACH: 543 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 544 break; 545 546 case DDI_RESUME: 547 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 548 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 549 if (nxgep == NULL) { 550 status = DDI_FAILURE; 551 break; 552 } 553 if (nxgep->dip != dip) { 554 status = DDI_FAILURE; 555 break; 556 } 557 if (nxgep->suspended == DDI_PM_SUSPEND) { 558 status = ddi_dev_is_needed(nxgep->dip, 0, 1); 559 } else { 560 status = nxge_resume(nxgep); 561 } 562 goto nxge_attach_exit; 563 564 case DDI_PM_RESUME: 565 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 566 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 567 if (nxgep == NULL) { 568 status = DDI_FAILURE; 569 break; 570 } 571 if (nxgep->dip != dip) { 572 status = DDI_FAILURE; 573 break; 574 } 575 status = nxge_resume(nxgep); 576 goto nxge_attach_exit; 577 578 default: 579 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 580 status = DDI_FAILURE; 581 goto nxge_attach_exit; 582 } 583 584 585 if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 586 status = DDI_FAILURE; 587 goto nxge_attach_exit; 588 } 589 590 nxgep = ddi_get_soft_state(nxge_list, instance); 591 if (nxgep == NULL) { 592 status = NXGE_ERROR; 593 goto nxge_attach_fail2; 594 } 595 596 nxgep->nxge_magic = NXGE_MAGIC; 597 598 nxgep->drv_state = 0; 599 nxgep->dip = dip; 600 nxgep->instance = instance; 601 nxgep->p_dip = ddi_get_parent(dip); 602 nxgep->nxge_debug_level = nxge_debug_level; 603 npi_debug_level = nxge_debug_level; 604 605 /* Are we a guest running in a Hybrid I/O environment? */ 606 nxge_get_environs(nxgep); 607 608 status = nxge_map_regs(nxgep); 609 610 if (status != NXGE_OK) { 611 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 612 goto nxge_attach_fail3; 613 } 614 615 nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, 616 &nxge_dev_desc_dma_acc_attr, 617 &nxge_rx_dma_attr); 618 619 /* Create & initialize the per-Neptune data structure */ 620 /* (even if we're a guest). */ 621 status = nxge_init_common_dev(nxgep); 622 if (status != NXGE_OK) { 623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 624 "nxge_init_common_dev failed")); 625 goto nxge_attach_fail4; 626 } 627 628 /* 629 * Software workaround: set the replay timer. 630 */ 631 if (nxgep->niu_type != N2_NIU) { 632 nxge_set_pci_replay_timeout(nxgep); 633 } 634 635 #if defined(sun4v) 636 /* This is required by nxge_hio_init(), which follows. */ 637 if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 638 goto nxge_attach_fail4; 639 #endif 640 641 if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 642 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 643 "nxge_hio_init failed")); 644 goto nxge_attach_fail4; 645 } 646 647 if (nxgep->niu_type == NEPTUNE_2_10GF) { 648 if (nxgep->function_num > 1) { 649 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 650 " function %d. Only functions 0 and 1 are " 651 "supported for this card.", nxgep->function_num)); 652 status = NXGE_ERROR; 653 goto nxge_attach_fail4; 654 } 655 } 656 657 if (isLDOMguest(nxgep)) { 658 /* 659 * Use the function number here. 660 */ 661 nxgep->mac.portnum = nxgep->function_num; 662 nxgep->mac.porttype = PORT_TYPE_LOGICAL; 663 664 /* XXX We'll set the MAC address counts to 1 for now. */ 665 mmac_info = &nxgep->nxge_mmac_info; 666 mmac_info->num_mmac = 1; 667 mmac_info->naddrfree = 1; 668 } else { 669 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 670 nxgep->mac.portnum = portn; 671 if ((portn == 0) || (portn == 1)) 672 nxgep->mac.porttype = PORT_TYPE_XMAC; 673 else 674 nxgep->mac.porttype = PORT_TYPE_BMAC; 675 /* 676 * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 677 * internally, the rest 2 ports use BMAC (1G "Big" MAC). 678 * The two types of MACs have different characterizations. 679 */ 680 mmac_info = &nxgep->nxge_mmac_info; 681 if (nxgep->function_num < 2) { 682 mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 683 mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 684 } else { 685 mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 686 mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 687 } 688 } 689 /* 690 * Setup the Ndd parameters for the this instance. 691 */ 692 nxge_init_param(nxgep); 693 694 /* 695 * Setup Register Tracing Buffer. 696 */ 697 npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 698 699 /* init stats ptr */ 700 nxge_init_statsp(nxgep); 701 702 /* 703 * Copy the vpd info from eeprom to a local data 704 * structure, and then check its validity. 705 */ 706 if (!isLDOMguest(nxgep)) { 707 int *regp; 708 uint_t reglen; 709 int rv; 710 711 nxge_vpd_info_get(nxgep); 712 713 /* Find the NIU config handle. */ 714 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 715 ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 716 "reg", ®p, ®len); 717 718 if (rv != DDI_PROP_SUCCESS) { 719 goto nxge_attach_fail5; 720 } 721 /* 722 * The address_hi, that is the first int, in the reg 723 * property consists of config handle, but need to remove 724 * the bits 28-31 which are OBP specific info. 725 */ 726 nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 727 ddi_prop_free(regp); 728 } 729 730 if (isLDOMguest(nxgep)) { 731 uchar_t *prop_val; 732 uint_t prop_len; 733 uint32_t max_frame_size; 734 735 extern void nxge_get_logical_props(p_nxge_t); 736 737 nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 738 nxgep->mac.portmode = PORT_LOGICAL; 739 (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 740 "phy-type", "virtual transceiver"); 741 742 nxgep->nports = 1; 743 nxgep->board_ver = 0; /* XXX What? */ 744 745 /* 746 * local-mac-address property gives us info on which 747 * specific MAC address the Hybrid resource is associated 748 * with. 749 */ 750 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 751 "local-mac-address", &prop_val, 752 &prop_len) != DDI_PROP_SUCCESS) { 753 goto nxge_attach_fail5; 754 } 755 if (prop_len != ETHERADDRL) { 756 ddi_prop_free(prop_val); 757 goto nxge_attach_fail5; 758 } 759 ether_copy(prop_val, nxgep->hio_mac_addr); 760 ddi_prop_free(prop_val); 761 nxge_get_logical_props(nxgep); 762 763 /* 764 * Enable Jumbo property based on the "max-frame-size" 765 * property value. 766 */ 767 max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY, 768 nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 769 "max-frame-size", NXGE_MTU_DEFAULT_MAX); 770 if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) && 771 (max_frame_size <= TX_JUMBO_MTU)) { 772 param_arr = nxgep->param_arr; 773 774 param_arr[param_accept_jumbo].value = 1; 775 nxgep->mac.is_jumbo = B_TRUE; 776 nxgep->mac.maxframesize = (uint16_t)max_frame_size; 777 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 778 NXGE_EHEADER_VLAN_CRC; 779 } 780 } else { 781 status = nxge_xcvr_find(nxgep); 782 783 if (status != NXGE_OK) { 784 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 785 " Couldn't determine card type" 786 " .... exit ")); 787 goto nxge_attach_fail5; 788 } 789 790 status = nxge_get_config_properties(nxgep); 791 792 if (status != NXGE_OK) { 793 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 794 "get_hw create failed")); 795 goto nxge_attach_fail; 796 } 797 } 798 799 /* 800 * Setup the Kstats for the driver. 801 */ 802 nxge_setup_kstats(nxgep); 803 804 if (!isLDOMguest(nxgep)) 805 nxge_setup_param(nxgep); 806 807 status = nxge_setup_system_dma_pages(nxgep); 808 if (status != NXGE_OK) { 809 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 810 goto nxge_attach_fail; 811 } 812 813 nxge_hw_id_init(nxgep); 814 815 if (!isLDOMguest(nxgep)) 816 nxge_hw_init_niu_common(nxgep); 817 818 status = nxge_setup_mutexes(nxgep); 819 if (status != NXGE_OK) { 820 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 821 goto nxge_attach_fail; 822 } 823 824 #if defined(sun4v) 825 if (isLDOMguest(nxgep)) { 826 /* Find our VR & channel sets. */ 827 status = nxge_hio_vr_add(nxgep); 828 if (status != NXGE_OK) { 829 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 830 "nxge_hio_vr_add failed")); 831 (void) hsvc_unregister(&nxgep->niu_hsvc); 832 nxgep->niu_hsvc_available = B_FALSE; 833 } 834 goto nxge_attach_exit; 835 } 836 #endif 837 838 status = nxge_setup_dev(nxgep); 839 if (status != DDI_SUCCESS) { 840 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 841 goto nxge_attach_fail; 842 } 843 844 status = nxge_add_intrs(nxgep); 845 if (status != DDI_SUCCESS) { 846 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 847 goto nxge_attach_fail; 848 } 849 850 status = nxge_add_soft_intrs(nxgep); 851 if (status != DDI_SUCCESS) { 852 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 853 "add_soft_intr failed")); 854 goto nxge_attach_fail; 855 } 856 857 /* If a guest, register with vio_net instead. */ 858 if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 859 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 860 "unable to register to mac layer (%d)", status)); 861 goto nxge_attach_fail; 862 } 863 864 mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 865 866 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 867 "registered to mac (instance %d)", instance)); 868 869 /* nxge_link_monitor calls xcvr.check_link recursively */ 870 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 871 872 goto nxge_attach_exit; 873 874 nxge_attach_fail: 875 nxge_unattach(nxgep); 876 goto nxge_attach_fail1; 877 878 nxge_attach_fail5: 879 /* 880 * Tear down the ndd parameters setup. 881 */ 882 nxge_destroy_param(nxgep); 883 884 /* 885 * Tear down the kstat setup. 886 */ 887 nxge_destroy_kstats(nxgep); 888 889 nxge_attach_fail4: 890 if (nxgep->nxge_hw_p) { 891 nxge_uninit_common_dev(nxgep); 892 nxgep->nxge_hw_p = NULL; 893 } 894 895 nxge_attach_fail3: 896 /* 897 * Unmap the register setup. 898 */ 899 nxge_unmap_regs(nxgep); 900 901 nxge_fm_fini(nxgep); 902 903 nxge_attach_fail2: 904 ddi_soft_state_free(nxge_list, nxgep->instance); 905 906 nxge_attach_fail1: 907 if (status != NXGE_OK) 908 status = (NXGE_ERROR | NXGE_DDI_FAILED); 909 nxgep = NULL; 910 911 nxge_attach_exit: 912 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 913 status)); 914 915 return (status); 916 } 917 918 static int 919 nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 920 { 921 int status = DDI_SUCCESS; 922 int instance; 923 p_nxge_t nxgep = NULL; 924 925 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 926 instance = ddi_get_instance(dip); 927 nxgep = ddi_get_soft_state(nxge_list, instance); 928 if (nxgep == NULL) { 929 status = DDI_FAILURE; 930 goto nxge_detach_exit; 931 } 932 933 switch (cmd) { 934 case DDI_DETACH: 935 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 936 break; 937 938 case DDI_PM_SUSPEND: 939 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 940 nxgep->suspended = DDI_PM_SUSPEND; 941 nxge_suspend(nxgep); 942 break; 943 944 case DDI_SUSPEND: 945 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 946 if (nxgep->suspended != DDI_PM_SUSPEND) { 947 nxgep->suspended = DDI_SUSPEND; 948 nxge_suspend(nxgep); 949 } 950 break; 951 952 default: 953 status = DDI_FAILURE; 954 } 955 956 if (cmd != DDI_DETACH) 957 goto nxge_detach_exit; 958 959 /* 960 * Stop the xcvr polling. 961 */ 962 nxgep->suspended = cmd; 963 964 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 965 966 if (isLDOMguest(nxgep)) { 967 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 968 nxge_m_stop((void *)nxgep); 969 nxge_hio_unregister(nxgep); 970 } else if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 971 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 972 "<== nxge_detach status = 0x%08X", status)); 973 return (DDI_FAILURE); 974 } 975 976 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 977 "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 978 979 nxge_unattach(nxgep); 980 nxgep = NULL; 981 982 nxge_detach_exit: 983 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 984 status)); 985 986 return (status); 987 } 988 989 static void 990 nxge_unattach(p_nxge_t nxgep) 991 { 992 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 993 994 if (nxgep == NULL || nxgep->dev_regs == NULL) { 995 return; 996 } 997 998 nxgep->nxge_magic = 0; 999 1000 if (nxgep->nxge_timerid) { 1001 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 1002 nxgep->nxge_timerid = 0; 1003 } 1004 1005 /* 1006 * If this flag is set, it will affect the Neptune 1007 * only. 1008 */ 1009 if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 1010 nxge_niu_peu_reset(nxgep); 1011 } 1012 1013 #if defined(sun4v) 1014 if (isLDOMguest(nxgep)) { 1015 (void) nxge_hio_vr_release(nxgep); 1016 } 1017 #endif 1018 1019 if (nxgep->nxge_hw_p) { 1020 nxge_uninit_common_dev(nxgep); 1021 nxgep->nxge_hw_p = NULL; 1022 } 1023 1024 #if defined(sun4v) 1025 if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 1026 (void) hsvc_unregister(&nxgep->niu_hsvc); 1027 nxgep->niu_hsvc_available = B_FALSE; 1028 } 1029 #endif 1030 /* 1031 * Stop any further interrupts. 1032 */ 1033 nxge_remove_intrs(nxgep); 1034 1035 /* remove soft interrups */ 1036 nxge_remove_soft_intrs(nxgep); 1037 1038 /* 1039 * Stop the device and free resources. 1040 */ 1041 if (!isLDOMguest(nxgep)) { 1042 nxge_destroy_dev(nxgep); 1043 } 1044 1045 /* 1046 * Tear down the ndd parameters setup. 1047 */ 1048 nxge_destroy_param(nxgep); 1049 1050 /* 1051 * Tear down the kstat setup. 1052 */ 1053 nxge_destroy_kstats(nxgep); 1054 1055 /* 1056 * Destroy all mutexes. 1057 */ 1058 nxge_destroy_mutexes(nxgep); 1059 1060 /* 1061 * Remove the list of ndd parameters which 1062 * were setup during attach. 1063 */ 1064 if (nxgep->dip) { 1065 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1066 " nxge_unattach: remove all properties")); 1067 1068 (void) ddi_prop_remove_all(nxgep->dip); 1069 } 1070 1071 #if NXGE_PROPERTY 1072 nxge_remove_hard_properties(nxgep); 1073 #endif 1074 1075 /* 1076 * Unmap the register setup. 1077 */ 1078 nxge_unmap_regs(nxgep); 1079 1080 nxge_fm_fini(nxgep); 1081 1082 ddi_soft_state_free(nxge_list, nxgep->instance); 1083 1084 NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 1085 } 1086 1087 #if defined(sun4v) 1088 int 1089 nxge_hsvc_register(nxge_t *nxgep) 1090 { 1091 nxge_status_t status; 1092 1093 if (nxgep->niu_type == N2_NIU) { 1094 nxgep->niu_hsvc_available = B_FALSE; 1095 bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t)); 1096 if ((status = hsvc_register(&nxgep->niu_hsvc, 1097 &nxgep->niu_min_ver)) != 0) { 1098 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1099 "nxge_attach: %s: cannot negotiate " 1100 "hypervisor services revision %d group: 0x%lx " 1101 "major: 0x%lx minor: 0x%lx errno: %d", 1102 niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1103 niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1104 niu_hsvc.hsvc_minor, status)); 1105 return (DDI_FAILURE); 1106 } 1107 nxgep->niu_hsvc_available = B_TRUE; 1108 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1109 "NIU Hypervisor service enabled")); 1110 } 1111 1112 return (DDI_SUCCESS); 1113 } 1114 #endif 1115 1116 static char n2_siu_name[] = "niu"; 1117 1118 static nxge_status_t 1119 nxge_map_regs(p_nxge_t nxgep) 1120 { 1121 int ddi_status = DDI_SUCCESS; 1122 p_dev_regs_t dev_regs; 1123 char buf[MAXPATHLEN + 1]; 1124 char *devname; 1125 #ifdef NXGE_DEBUG 1126 char *sysname; 1127 #endif 1128 off_t regsize; 1129 nxge_status_t status = NXGE_OK; 1130 #if !defined(_BIG_ENDIAN) 1131 off_t pci_offset; 1132 uint16_t pcie_devctl; 1133 #endif 1134 1135 if (isLDOMguest(nxgep)) { 1136 return (nxge_guest_regs_map(nxgep)); 1137 } 1138 1139 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 1140 nxgep->dev_regs = NULL; 1141 dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 1142 dev_regs->nxge_regh = NULL; 1143 dev_regs->nxge_pciregh = NULL; 1144 dev_regs->nxge_msix_regh = NULL; 1145 dev_regs->nxge_vir_regh = NULL; 1146 dev_regs->nxge_vir2_regh = NULL; 1147 nxgep->niu_type = NIU_TYPE_NONE; 1148 1149 devname = ddi_pathname(nxgep->dip, buf); 1150 ASSERT(strlen(devname) > 0); 1151 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1152 "nxge_map_regs: pathname devname %s", devname)); 1153 1154 /* 1155 * The driver is running on a N2-NIU system if devname is something 1156 * like "/niu@80/network@0" 1157 */ 1158 if (strstr(devname, n2_siu_name)) { 1159 /* N2/NIU */ 1160 nxgep->niu_type = N2_NIU; 1161 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1162 "nxge_map_regs: N2/NIU devname %s", devname)); 1163 /* get function number */ 1164 nxgep->function_num = 1165 (devname[strlen(devname) -1] == '1' ? 1 : 0); 1166 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1167 "nxge_map_regs: N2/NIU function number %d", 1168 nxgep->function_num)); 1169 } else { 1170 int *prop_val; 1171 uint_t prop_len; 1172 uint8_t func_num; 1173 1174 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 1175 0, "reg", 1176 &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 1177 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1178 "Reg property not found")); 1179 ddi_status = DDI_FAILURE; 1180 goto nxge_map_regs_fail0; 1181 1182 } else { 1183 func_num = (prop_val[0] >> 8) & 0x7; 1184 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1185 "Reg property found: fun # %d", 1186 func_num)); 1187 nxgep->function_num = func_num; 1188 if (isLDOMguest(nxgep)) { 1189 nxgep->function_num /= 2; 1190 return (NXGE_OK); 1191 } 1192 ddi_prop_free(prop_val); 1193 } 1194 } 1195 1196 switch (nxgep->niu_type) { 1197 default: 1198 (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 1199 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1200 "nxge_map_regs: pci config size 0x%x", regsize)); 1201 1202 ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 1203 (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 1204 &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 1205 if (ddi_status != DDI_SUCCESS) { 1206 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1207 "ddi_map_regs, nxge bus config regs failed")); 1208 goto nxge_map_regs_fail0; 1209 } 1210 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1211 "nxge_map_reg: PCI config addr 0x%0llx " 1212 " handle 0x%0llx", dev_regs->nxge_pciregp, 1213 dev_regs->nxge_pciregh)); 1214 /* 1215 * IMP IMP 1216 * workaround for bit swapping bug in HW 1217 * which ends up in no-snoop = yes 1218 * resulting, in DMA not synched properly 1219 */ 1220 #if !defined(_BIG_ENDIAN) 1221 /* workarounds for x86 systems */ 1222 pci_offset = 0x80 + PCIE_DEVCTL; 1223 pcie_devctl = 0x0; 1224 pcie_devctl &= PCIE_DEVCTL_ENABLE_NO_SNOOP; 1225 pcie_devctl |= PCIE_DEVCTL_RO_EN; 1226 pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 1227 pcie_devctl); 1228 #endif 1229 1230 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1231 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1232 "nxge_map_regs: pio size 0x%x", regsize)); 1233 /* set up the device mapped register */ 1234 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1235 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1236 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1237 if (ddi_status != DDI_SUCCESS) { 1238 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1239 "ddi_map_regs for Neptune global reg failed")); 1240 goto nxge_map_regs_fail1; 1241 } 1242 1243 /* set up the msi/msi-x mapped register */ 1244 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1245 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1246 "nxge_map_regs: msix size 0x%x", regsize)); 1247 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1248 (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 1249 &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 1250 if (ddi_status != DDI_SUCCESS) { 1251 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1252 "ddi_map_regs for msi reg failed")); 1253 goto nxge_map_regs_fail2; 1254 } 1255 1256 /* set up the vio region mapped register */ 1257 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1258 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1259 "nxge_map_regs: vio size 0x%x", regsize)); 1260 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1261 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1262 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1263 1264 if (ddi_status != DDI_SUCCESS) { 1265 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1266 "ddi_map_regs for nxge vio reg failed")); 1267 goto nxge_map_regs_fail3; 1268 } 1269 nxgep->dev_regs = dev_regs; 1270 1271 NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 1272 NPI_PCI_ADD_HANDLE_SET(nxgep, 1273 (npi_reg_ptr_t)dev_regs->nxge_pciregp); 1274 NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 1275 NPI_MSI_ADD_HANDLE_SET(nxgep, 1276 (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 1277 1278 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1279 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1280 1281 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1282 NPI_REG_ADD_HANDLE_SET(nxgep, 1283 (npi_reg_ptr_t)dev_regs->nxge_regp); 1284 1285 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1286 NPI_VREG_ADD_HANDLE_SET(nxgep, 1287 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1288 1289 break; 1290 1291 case N2_NIU: 1292 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 1293 /* 1294 * Set up the device mapped register (FWARC 2006/556) 1295 * (changed back to 1: reg starts at 1!) 1296 */ 1297 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1298 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1299 "nxge_map_regs: dev size 0x%x", regsize)); 1300 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1301 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1302 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1303 1304 if (ddi_status != DDI_SUCCESS) { 1305 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1306 "ddi_map_regs for N2/NIU, global reg failed ")); 1307 goto nxge_map_regs_fail1; 1308 } 1309 1310 /* set up the first vio region mapped register */ 1311 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1312 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1313 "nxge_map_regs: vio (1) size 0x%x", regsize)); 1314 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1315 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1316 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1317 1318 if (ddi_status != DDI_SUCCESS) { 1319 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1320 "ddi_map_regs for nxge vio reg failed")); 1321 goto nxge_map_regs_fail2; 1322 } 1323 /* set up the second vio region mapped register */ 1324 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1325 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1326 "nxge_map_regs: vio (3) size 0x%x", regsize)); 1327 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1328 (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 1329 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 1330 1331 if (ddi_status != DDI_SUCCESS) { 1332 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1333 "ddi_map_regs for nxge vio2 reg failed")); 1334 goto nxge_map_regs_fail3; 1335 } 1336 nxgep->dev_regs = dev_regs; 1337 1338 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1339 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1340 1341 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1342 NPI_REG_ADD_HANDLE_SET(nxgep, 1343 (npi_reg_ptr_t)dev_regs->nxge_regp); 1344 1345 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1346 NPI_VREG_ADD_HANDLE_SET(nxgep, 1347 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1348 1349 NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 1350 NPI_V2REG_ADD_HANDLE_SET(nxgep, 1351 (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 1352 1353 break; 1354 } 1355 1356 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 1357 " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 1358 1359 goto nxge_map_regs_exit; 1360 nxge_map_regs_fail3: 1361 if (dev_regs->nxge_msix_regh) { 1362 ddi_regs_map_free(&dev_regs->nxge_msix_regh); 1363 } 1364 if (dev_regs->nxge_vir_regh) { 1365 ddi_regs_map_free(&dev_regs->nxge_regh); 1366 } 1367 nxge_map_regs_fail2: 1368 if (dev_regs->nxge_regh) { 1369 ddi_regs_map_free(&dev_regs->nxge_regh); 1370 } 1371 nxge_map_regs_fail1: 1372 if (dev_regs->nxge_pciregh) { 1373 ddi_regs_map_free(&dev_regs->nxge_pciregh); 1374 } 1375 nxge_map_regs_fail0: 1376 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 1377 kmem_free(dev_regs, sizeof (dev_regs_t)); 1378 1379 nxge_map_regs_exit: 1380 if (ddi_status != DDI_SUCCESS) 1381 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1382 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 1383 return (status); 1384 } 1385 1386 static void 1387 nxge_unmap_regs(p_nxge_t nxgep) 1388 { 1389 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1390 1391 if (isLDOMguest(nxgep)) { 1392 nxge_guest_regs_map_free(nxgep); 1393 return; 1394 } 1395 1396 if (nxgep->dev_regs) { 1397 if (nxgep->dev_regs->nxge_pciregh) { 1398 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1399 "==> nxge_unmap_regs: bus")); 1400 ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 1401 nxgep->dev_regs->nxge_pciregh = NULL; 1402 } 1403 if (nxgep->dev_regs->nxge_regh) { 1404 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1405 "==> nxge_unmap_regs: device registers")); 1406 ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 1407 nxgep->dev_regs->nxge_regh = NULL; 1408 } 1409 if (nxgep->dev_regs->nxge_msix_regh) { 1410 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1411 "==> nxge_unmap_regs: device interrupts")); 1412 ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 1413 nxgep->dev_regs->nxge_msix_regh = NULL; 1414 } 1415 if (nxgep->dev_regs->nxge_vir_regh) { 1416 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1417 "==> nxge_unmap_regs: vio region")); 1418 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 1419 nxgep->dev_regs->nxge_vir_regh = NULL; 1420 } 1421 if (nxgep->dev_regs->nxge_vir2_regh) { 1422 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1423 "==> nxge_unmap_regs: vio2 region")); 1424 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 1425 nxgep->dev_regs->nxge_vir2_regh = NULL; 1426 } 1427 1428 kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 1429 nxgep->dev_regs = NULL; 1430 } 1431 1432 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 1433 } 1434 1435 static nxge_status_t 1436 nxge_setup_mutexes(p_nxge_t nxgep) 1437 { 1438 int ddi_status = DDI_SUCCESS; 1439 nxge_status_t status = NXGE_OK; 1440 nxge_classify_t *classify_ptr; 1441 int partition; 1442 1443 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 1444 1445 /* 1446 * Get the interrupt cookie so the mutexes can be 1447 * Initialized. 1448 */ 1449 if (isLDOMguest(nxgep)) { 1450 nxgep->interrupt_cookie = 0; 1451 } else { 1452 ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1453 &nxgep->interrupt_cookie); 1454 1455 if (ddi_status != DDI_SUCCESS) { 1456 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1457 "<== nxge_setup_mutexes: failed 0x%x", 1458 ddi_status)); 1459 goto nxge_setup_mutexes_exit; 1460 } 1461 } 1462 1463 cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 1464 MUTEX_INIT(&nxgep->poll_lock, NULL, 1465 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1466 1467 /* 1468 * Initialize mutexes for this device. 1469 */ 1470 MUTEX_INIT(nxgep->genlock, NULL, 1471 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1472 MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 1473 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1474 MUTEX_INIT(&nxgep->mif_lock, NULL, 1475 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1476 MUTEX_INIT(&nxgep->group_lock, NULL, 1477 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1478 RW_INIT(&nxgep->filter_lock, NULL, 1479 RW_DRIVER, (void *)nxgep->interrupt_cookie); 1480 1481 classify_ptr = &nxgep->classifier; 1482 /* 1483 * FFLP Mutexes are never used in interrupt context 1484 * as fflp operation can take very long time to 1485 * complete and hence not suitable to invoke from interrupt 1486 * handlers. 1487 */ 1488 MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 1489 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1490 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1491 MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 1492 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1493 for (partition = 0; partition < MAX_PARTITION; partition++) { 1494 MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 1495 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1496 } 1497 } 1498 1499 nxge_setup_mutexes_exit: 1500 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1501 "<== nxge_setup_mutexes status = %x", status)); 1502 1503 if (ddi_status != DDI_SUCCESS) 1504 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1505 1506 return (status); 1507 } 1508 1509 static void 1510 nxge_destroy_mutexes(p_nxge_t nxgep) 1511 { 1512 int partition; 1513 nxge_classify_t *classify_ptr; 1514 1515 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 1516 RW_DESTROY(&nxgep->filter_lock); 1517 MUTEX_DESTROY(&nxgep->group_lock); 1518 MUTEX_DESTROY(&nxgep->mif_lock); 1519 MUTEX_DESTROY(&nxgep->ouraddr_lock); 1520 MUTEX_DESTROY(nxgep->genlock); 1521 1522 classify_ptr = &nxgep->classifier; 1523 MUTEX_DESTROY(&classify_ptr->tcam_lock); 1524 1525 /* Destroy all polling resources. */ 1526 MUTEX_DESTROY(&nxgep->poll_lock); 1527 cv_destroy(&nxgep->poll_cv); 1528 1529 /* free data structures, based on HW type */ 1530 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1531 MUTEX_DESTROY(&classify_ptr->fcram_lock); 1532 for (partition = 0; partition < MAX_PARTITION; partition++) { 1533 MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 1534 } 1535 } 1536 1537 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 1538 } 1539 1540 nxge_status_t 1541 nxge_init(p_nxge_t nxgep) 1542 { 1543 nxge_status_t status = NXGE_OK; 1544 1545 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 1546 1547 if (nxgep->drv_state & STATE_HW_INITIALIZED) { 1548 return (status); 1549 } 1550 1551 /* 1552 * Allocate system memory for the receive/transmit buffer blocks 1553 * and receive/transmit descriptor rings. 1554 */ 1555 status = nxge_alloc_mem_pool(nxgep); 1556 if (status != NXGE_OK) { 1557 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 1558 goto nxge_init_fail1; 1559 } 1560 1561 if (!isLDOMguest(nxgep)) { 1562 /* 1563 * Initialize and enable the TXC registers. 1564 * (Globally enable the Tx controller, 1565 * enable the port, configure the dma channel bitmap, 1566 * configure the max burst size). 1567 */ 1568 status = nxge_txc_init(nxgep); 1569 if (status != NXGE_OK) { 1570 NXGE_ERROR_MSG((nxgep, 1571 NXGE_ERR_CTL, "init txc failed\n")); 1572 goto nxge_init_fail2; 1573 } 1574 } 1575 1576 /* 1577 * Initialize and enable TXDMA channels. 1578 */ 1579 status = nxge_init_txdma_channels(nxgep); 1580 if (status != NXGE_OK) { 1581 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 1582 goto nxge_init_fail3; 1583 } 1584 1585 /* 1586 * Initialize and enable RXDMA channels. 1587 */ 1588 status = nxge_init_rxdma_channels(nxgep); 1589 if (status != NXGE_OK) { 1590 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 1591 goto nxge_init_fail4; 1592 } 1593 1594 /* 1595 * The guest domain is now done. 1596 */ 1597 if (isLDOMguest(nxgep)) { 1598 nxgep->drv_state |= STATE_HW_INITIALIZED; 1599 goto nxge_init_exit; 1600 } 1601 1602 /* 1603 * Initialize TCAM and FCRAM (Neptune). 1604 */ 1605 status = nxge_classify_init(nxgep); 1606 if (status != NXGE_OK) { 1607 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 1608 goto nxge_init_fail5; 1609 } 1610 1611 /* 1612 * Initialize ZCP 1613 */ 1614 status = nxge_zcp_init(nxgep); 1615 if (status != NXGE_OK) { 1616 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 1617 goto nxge_init_fail5; 1618 } 1619 1620 /* 1621 * Initialize IPP. 1622 */ 1623 status = nxge_ipp_init(nxgep); 1624 if (status != NXGE_OK) { 1625 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 1626 goto nxge_init_fail5; 1627 } 1628 1629 /* 1630 * Initialize the MAC block. 1631 */ 1632 status = nxge_mac_init(nxgep); 1633 if (status != NXGE_OK) { 1634 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 1635 goto nxge_init_fail5; 1636 } 1637 1638 nxge_intrs_enable(nxgep); /* XXX What changes do I need to make here? */ 1639 1640 /* 1641 * Enable hardware interrupts. 1642 */ 1643 nxge_intr_hw_enable(nxgep); 1644 nxgep->drv_state |= STATE_HW_INITIALIZED; 1645 1646 goto nxge_init_exit; 1647 1648 nxge_init_fail5: 1649 nxge_uninit_rxdma_channels(nxgep); 1650 nxge_init_fail4: 1651 nxge_uninit_txdma_channels(nxgep); 1652 nxge_init_fail3: 1653 if (!isLDOMguest(nxgep)) { 1654 (void) nxge_txc_uninit(nxgep); 1655 } 1656 nxge_init_fail2: 1657 nxge_free_mem_pool(nxgep); 1658 nxge_init_fail1: 1659 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1660 "<== nxge_init status (failed) = 0x%08x", status)); 1661 return (status); 1662 1663 nxge_init_exit: 1664 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 1665 status)); 1666 return (status); 1667 } 1668 1669 1670 timeout_id_t 1671 nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 1672 { 1673 if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 1674 return (timeout(func, (caddr_t)nxgep, 1675 drv_usectohz(1000 * msec))); 1676 } 1677 return (NULL); 1678 } 1679 1680 /*ARGSUSED*/ 1681 void 1682 nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 1683 { 1684 if (timerid) { 1685 (void) untimeout(timerid); 1686 } 1687 } 1688 1689 void 1690 nxge_uninit(p_nxge_t nxgep) 1691 { 1692 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 1693 1694 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1695 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1696 "==> nxge_uninit: not initialized")); 1697 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1698 "<== nxge_uninit")); 1699 return; 1700 } 1701 1702 /* stop timer */ 1703 if (nxgep->nxge_timerid) { 1704 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 1705 nxgep->nxge_timerid = 0; 1706 } 1707 1708 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1709 (void) nxge_intr_hw_disable(nxgep); 1710 1711 /* 1712 * Reset the receive MAC side. 1713 */ 1714 (void) nxge_rx_mac_disable(nxgep); 1715 1716 /* Disable and soft reset the IPP */ 1717 if (!isLDOMguest(nxgep)) 1718 (void) nxge_ipp_disable(nxgep); 1719 1720 /* Free classification resources */ 1721 (void) nxge_classify_uninit(nxgep); 1722 1723 /* 1724 * Reset the transmit/receive DMA side. 1725 */ 1726 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 1727 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1728 1729 nxge_uninit_txdma_channels(nxgep); 1730 nxge_uninit_rxdma_channels(nxgep); 1731 1732 /* 1733 * Reset the transmit MAC side. 1734 */ 1735 (void) nxge_tx_mac_disable(nxgep); 1736 1737 nxge_free_mem_pool(nxgep); 1738 1739 /* 1740 * Start the timer if the reset flag is not set. 1741 * If this reset flag is set, the link monitor 1742 * will not be started in order to stop furthur bus 1743 * activities coming from this interface. 1744 * The driver will start the monitor function 1745 * if the interface was initialized again later. 1746 */ 1747 if (!nxge_peu_reset_enable) { 1748 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1749 } 1750 1751 nxgep->drv_state &= ~STATE_HW_INITIALIZED; 1752 1753 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 1754 "nxge_mblks_pending %d", nxge_mblks_pending)); 1755 } 1756 1757 void 1758 nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 1759 { 1760 #if defined(__i386) 1761 size_t reg; 1762 #else 1763 uint64_t reg; 1764 #endif 1765 uint64_t regdata; 1766 int i, retry; 1767 1768 bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 1769 regdata = 0; 1770 retry = 1; 1771 1772 for (i = 0; i < retry; i++) { 1773 NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 1774 } 1775 bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 1776 } 1777 1778 void 1779 nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 1780 { 1781 #if defined(__i386) 1782 size_t reg; 1783 #else 1784 uint64_t reg; 1785 #endif 1786 uint64_t buf[2]; 1787 1788 bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 1789 #if defined(__i386) 1790 reg = (size_t)buf[0]; 1791 #else 1792 reg = buf[0]; 1793 #endif 1794 1795 NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 1796 } 1797 1798 1799 nxge_os_mutex_t nxgedebuglock; 1800 int nxge_debug_init = 0; 1801 1802 /*ARGSUSED*/ 1803 /*VARARGS*/ 1804 void 1805 nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 1806 { 1807 char msg_buffer[1048]; 1808 char prefix_buffer[32]; 1809 int instance; 1810 uint64_t debug_level; 1811 int cmn_level = CE_CONT; 1812 va_list ap; 1813 1814 if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1815 /* In case a developer has changed nxge_debug_level. */ 1816 if (nxgep->nxge_debug_level != nxge_debug_level) 1817 nxgep->nxge_debug_level = nxge_debug_level; 1818 } 1819 1820 debug_level = (nxgep == NULL) ? nxge_debug_level : 1821 nxgep->nxge_debug_level; 1822 1823 if ((level & debug_level) || 1824 (level == NXGE_NOTE) || 1825 (level == NXGE_ERR_CTL)) { 1826 /* do the msg processing */ 1827 if (nxge_debug_init == 0) { 1828 MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 1829 nxge_debug_init = 1; 1830 } 1831 1832 MUTEX_ENTER(&nxgedebuglock); 1833 1834 if ((level & NXGE_NOTE)) { 1835 cmn_level = CE_NOTE; 1836 } 1837 1838 if (level & NXGE_ERR_CTL) { 1839 cmn_level = CE_WARN; 1840 } 1841 1842 va_start(ap, fmt); 1843 (void) vsprintf(msg_buffer, fmt, ap); 1844 va_end(ap); 1845 if (nxgep == NULL) { 1846 instance = -1; 1847 (void) sprintf(prefix_buffer, "%s :", "nxge"); 1848 } else { 1849 instance = nxgep->instance; 1850 (void) sprintf(prefix_buffer, 1851 "%s%d :", "nxge", instance); 1852 } 1853 1854 MUTEX_EXIT(&nxgedebuglock); 1855 cmn_err(cmn_level, "!%s %s\n", 1856 prefix_buffer, msg_buffer); 1857 1858 } 1859 } 1860 1861 char * 1862 nxge_dump_packet(char *addr, int size) 1863 { 1864 uchar_t *ap = (uchar_t *)addr; 1865 int i; 1866 static char etherbuf[1024]; 1867 char *cp = etherbuf; 1868 char digits[] = "0123456789abcdef"; 1869 1870 if (!size) 1871 size = 60; 1872 1873 if (size > MAX_DUMP_SZ) { 1874 /* Dump the leading bytes */ 1875 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1876 if (*ap > 0x0f) 1877 *cp++ = digits[*ap >> 4]; 1878 *cp++ = digits[*ap++ & 0xf]; 1879 *cp++ = ':'; 1880 } 1881 for (i = 0; i < 20; i++) 1882 *cp++ = '.'; 1883 /* Dump the last MAX_DUMP_SZ/2 bytes */ 1884 ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 1885 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1886 if (*ap > 0x0f) 1887 *cp++ = digits[*ap >> 4]; 1888 *cp++ = digits[*ap++ & 0xf]; 1889 *cp++ = ':'; 1890 } 1891 } else { 1892 for (i = 0; i < size; i++) { 1893 if (*ap > 0x0f) 1894 *cp++ = digits[*ap >> 4]; 1895 *cp++ = digits[*ap++ & 0xf]; 1896 *cp++ = ':'; 1897 } 1898 } 1899 *--cp = 0; 1900 return (etherbuf); 1901 } 1902 1903 #ifdef NXGE_DEBUG 1904 static void 1905 nxge_test_map_regs(p_nxge_t nxgep) 1906 { 1907 ddi_acc_handle_t cfg_handle; 1908 p_pci_cfg_t cfg_ptr; 1909 ddi_acc_handle_t dev_handle; 1910 char *dev_ptr; 1911 ddi_acc_handle_t pci_config_handle; 1912 uint32_t regval; 1913 int i; 1914 1915 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 1916 1917 dev_handle = nxgep->dev_regs->nxge_regh; 1918 dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 1919 1920 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1921 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1922 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1923 1924 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1925 "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 1926 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1927 "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 1928 &cfg_ptr->vendorid)); 1929 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1930 "\tvendorid 0x%x devid 0x%x", 1931 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 1932 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 1933 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1934 "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 1935 "bar1c 0x%x", 1936 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 1937 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 1938 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 1939 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 1940 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1941 "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 1942 "base 28 0x%x bar2c 0x%x\n", 1943 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 1944 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 1945 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 1946 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 1947 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1948 "\nNeptune PCI BAR: base30 0x%x\n", 1949 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 1950 1951 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1952 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1953 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1954 "first 0x%llx second 0x%llx third 0x%llx " 1955 "last 0x%llx ", 1956 NXGE_PIO_READ64(dev_handle, 1957 (uint64_t *)(dev_ptr + 0), 0), 1958 NXGE_PIO_READ64(dev_handle, 1959 (uint64_t *)(dev_ptr + 8), 0), 1960 NXGE_PIO_READ64(dev_handle, 1961 (uint64_t *)(dev_ptr + 16), 0), 1962 NXGE_PIO_READ64(cfg_handle, 1963 (uint64_t *)(dev_ptr + 24), 0))); 1964 } 1965 } 1966 1967 #endif 1968 1969 static void 1970 nxge_suspend(p_nxge_t nxgep) 1971 { 1972 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 1973 1974 nxge_intrs_disable(nxgep); 1975 nxge_destroy_dev(nxgep); 1976 1977 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 1978 } 1979 1980 static nxge_status_t 1981 nxge_resume(p_nxge_t nxgep) 1982 { 1983 nxge_status_t status = NXGE_OK; 1984 1985 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 1986 1987 nxgep->suspended = DDI_RESUME; 1988 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1989 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1990 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 1991 (void) nxge_rx_mac_enable(nxgep); 1992 (void) nxge_tx_mac_enable(nxgep); 1993 nxge_intrs_enable(nxgep); 1994 nxgep->suspended = 0; 1995 1996 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1997 "<== nxge_resume status = 0x%x", status)); 1998 return (status); 1999 } 2000 2001 static nxge_status_t 2002 nxge_setup_dev(p_nxge_t nxgep) 2003 { 2004 nxge_status_t status = NXGE_OK; 2005 2006 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 2007 nxgep->mac.portnum)); 2008 2009 status = nxge_link_init(nxgep); 2010 2011 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 2012 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2013 "port%d Bad register acc handle", nxgep->mac.portnum)); 2014 status = NXGE_ERROR; 2015 } 2016 2017 if (status != NXGE_OK) { 2018 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2019 " nxge_setup_dev status " 2020 "(xcvr init 0x%08x)", status)); 2021 goto nxge_setup_dev_exit; 2022 } 2023 2024 nxge_setup_dev_exit: 2025 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2026 "<== nxge_setup_dev port %d status = 0x%08x", 2027 nxgep->mac.portnum, status)); 2028 2029 return (status); 2030 } 2031 2032 static void 2033 nxge_destroy_dev(p_nxge_t nxgep) 2034 { 2035 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 2036 2037 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2038 2039 (void) nxge_hw_stop(nxgep); 2040 2041 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 2042 } 2043 2044 static nxge_status_t 2045 nxge_setup_system_dma_pages(p_nxge_t nxgep) 2046 { 2047 int ddi_status = DDI_SUCCESS; 2048 uint_t count; 2049 ddi_dma_cookie_t cookie; 2050 uint_t iommu_pagesize; 2051 nxge_status_t status = NXGE_OK; 2052 2053 NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 2054 nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 2055 if (nxgep->niu_type != N2_NIU) { 2056 iommu_pagesize = dvma_pagesize(nxgep->dip); 2057 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2058 " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2059 " default_block_size %d iommu_pagesize %d", 2060 nxgep->sys_page_sz, 2061 ddi_ptob(nxgep->dip, (ulong_t)1), 2062 nxgep->rx_default_block_size, 2063 iommu_pagesize)); 2064 2065 if (iommu_pagesize != 0) { 2066 if (nxgep->sys_page_sz == iommu_pagesize) { 2067 if (iommu_pagesize > 0x4000) 2068 nxgep->sys_page_sz = 0x4000; 2069 } else { 2070 if (nxgep->sys_page_sz > iommu_pagesize) 2071 nxgep->sys_page_sz = iommu_pagesize; 2072 } 2073 } 2074 } 2075 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2076 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2077 "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2078 "default_block_size %d page mask %d", 2079 nxgep->sys_page_sz, 2080 ddi_ptob(nxgep->dip, (ulong_t)1), 2081 nxgep->rx_default_block_size, 2082 nxgep->sys_page_mask)); 2083 2084 2085 switch (nxgep->sys_page_sz) { 2086 default: 2087 nxgep->sys_page_sz = 0x1000; 2088 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2089 nxgep->rx_default_block_size = 0x1000; 2090 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2091 break; 2092 case 0x1000: 2093 nxgep->rx_default_block_size = 0x1000; 2094 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2095 break; 2096 case 0x2000: 2097 nxgep->rx_default_block_size = 0x2000; 2098 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2099 break; 2100 case 0x4000: 2101 nxgep->rx_default_block_size = 0x4000; 2102 nxgep->rx_bksize_code = RBR_BKSIZE_16K; 2103 break; 2104 case 0x8000: 2105 nxgep->rx_default_block_size = 0x8000; 2106 nxgep->rx_bksize_code = RBR_BKSIZE_32K; 2107 break; 2108 } 2109 2110 #ifndef USE_RX_BIG_BUF 2111 nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 2112 #else 2113 nxgep->rx_default_block_size = 0x2000; 2114 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2115 #endif 2116 /* 2117 * Get the system DMA burst size. 2118 */ 2119 ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 2120 DDI_DMA_DONTWAIT, 0, 2121 &nxgep->dmasparehandle); 2122 if (ddi_status != DDI_SUCCESS) { 2123 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2124 "ddi_dma_alloc_handle: failed " 2125 " status 0x%x", ddi_status)); 2126 goto nxge_get_soft_properties_exit; 2127 } 2128 2129 ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 2130 (caddr_t)nxgep->dmasparehandle, 2131 sizeof (nxgep->dmasparehandle), 2132 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2133 DDI_DMA_DONTWAIT, 0, 2134 &cookie, &count); 2135 if (ddi_status != DDI_DMA_MAPPED) { 2136 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2137 "Binding spare handle to find system" 2138 " burstsize failed.")); 2139 ddi_status = DDI_FAILURE; 2140 goto nxge_get_soft_properties_fail1; 2141 } 2142 2143 nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 2144 (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 2145 2146 nxge_get_soft_properties_fail1: 2147 ddi_dma_free_handle(&nxgep->dmasparehandle); 2148 2149 nxge_get_soft_properties_exit: 2150 2151 if (ddi_status != DDI_SUCCESS) 2152 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2153 2154 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2155 "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 2156 return (status); 2157 } 2158 2159 static nxge_status_t 2160 nxge_alloc_mem_pool(p_nxge_t nxgep) 2161 { 2162 nxge_status_t status = NXGE_OK; 2163 2164 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 2165 2166 status = nxge_alloc_rx_mem_pool(nxgep); 2167 if (status != NXGE_OK) { 2168 return (NXGE_ERROR); 2169 } 2170 2171 status = nxge_alloc_tx_mem_pool(nxgep); 2172 if (status != NXGE_OK) { 2173 nxge_free_rx_mem_pool(nxgep); 2174 return (NXGE_ERROR); 2175 } 2176 2177 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 2178 return (NXGE_OK); 2179 } 2180 2181 static void 2182 nxge_free_mem_pool(p_nxge_t nxgep) 2183 { 2184 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 2185 2186 nxge_free_rx_mem_pool(nxgep); 2187 nxge_free_tx_mem_pool(nxgep); 2188 2189 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 2190 } 2191 2192 nxge_status_t 2193 nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 2194 { 2195 uint32_t rdc_max; 2196 p_nxge_dma_pt_cfg_t p_all_cfgp; 2197 p_nxge_hw_pt_cfg_t p_cfgp; 2198 p_nxge_dma_pool_t dma_poolp; 2199 p_nxge_dma_common_t *dma_buf_p; 2200 p_nxge_dma_pool_t dma_cntl_poolp; 2201 p_nxge_dma_common_t *dma_cntl_p; 2202 uint32_t *num_chunks; /* per dma */ 2203 nxge_status_t status = NXGE_OK; 2204 2205 uint32_t nxge_port_rbr_size; 2206 uint32_t nxge_port_rbr_spare_size; 2207 uint32_t nxge_port_rcr_size; 2208 uint32_t rx_cntl_alloc_size; 2209 2210 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 2211 2212 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2213 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2214 rdc_max = NXGE_MAX_RDCS; 2215 2216 /* 2217 * Allocate memory for the common DMA data structures. 2218 */ 2219 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2220 KM_SLEEP); 2221 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2222 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2223 2224 dma_cntl_poolp = (p_nxge_dma_pool_t) 2225 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2226 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2227 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2228 2229 num_chunks = (uint32_t *)KMEM_ZALLOC( 2230 sizeof (uint32_t) * rdc_max, KM_SLEEP); 2231 2232 /* 2233 * Assume that each DMA channel will be configured with 2234 * the default block size. 2235 * rbr block counts are modulo the batch count (16). 2236 */ 2237 nxge_port_rbr_size = p_all_cfgp->rbr_size; 2238 nxge_port_rcr_size = p_all_cfgp->rcr_size; 2239 2240 if (!nxge_port_rbr_size) { 2241 nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 2242 } 2243 if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 2244 nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 2245 (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 2246 } 2247 2248 p_all_cfgp->rbr_size = nxge_port_rbr_size; 2249 nxge_port_rbr_spare_size = nxge_rbr_spare_size; 2250 2251 if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 2252 nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 2253 (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 2254 } 2255 if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 2256 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2257 "nxge_alloc_rx_mem_pool: RBR size too high %d, " 2258 "set to default %d", 2259 nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 2260 nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 2261 } 2262 if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 2263 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2264 "nxge_alloc_rx_mem_pool: RCR too high %d, " 2265 "set to default %d", 2266 nxge_port_rcr_size, RCR_DEFAULT_MAX)); 2267 nxge_port_rcr_size = RCR_DEFAULT_MAX; 2268 } 2269 2270 /* 2271 * N2/NIU has limitation on the descriptor sizes (contiguous 2272 * memory allocation on data buffers to 4M (contig_mem_alloc) 2273 * and little endian for control buffers (must use the ddi/dki mem alloc 2274 * function). 2275 */ 2276 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2277 if (nxgep->niu_type == N2_NIU) { 2278 nxge_port_rbr_spare_size = 0; 2279 if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 2280 (!ISP2(nxge_port_rbr_size))) { 2281 nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 2282 } 2283 if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 2284 (!ISP2(nxge_port_rcr_size))) { 2285 nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 2286 } 2287 } 2288 #endif 2289 2290 /* 2291 * Addresses of receive block ring, receive completion ring and the 2292 * mailbox must be all cache-aligned (64 bytes). 2293 */ 2294 rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 2295 rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 2296 rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 2297 rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 2298 2299 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 2300 "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 2301 "nxge_port_rcr_size = %d " 2302 "rx_cntl_alloc_size = %d", 2303 nxge_port_rbr_size, nxge_port_rbr_spare_size, 2304 nxge_port_rcr_size, 2305 rx_cntl_alloc_size)); 2306 2307 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2308 if (nxgep->niu_type == N2_NIU) { 2309 uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2310 (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2311 2312 if (!ISP2(rx_buf_alloc_size)) { 2313 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2314 "==> nxge_alloc_rx_mem_pool: " 2315 " must be power of 2")); 2316 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2317 goto nxge_alloc_rx_mem_pool_exit; 2318 } 2319 2320 if (rx_buf_alloc_size > (1 << 22)) { 2321 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2322 "==> nxge_alloc_rx_mem_pool: " 2323 " limit size to 4M")); 2324 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2325 goto nxge_alloc_rx_mem_pool_exit; 2326 } 2327 2328 if (rx_cntl_alloc_size < 0x2000) { 2329 rx_cntl_alloc_size = 0x2000; 2330 } 2331 } 2332 #endif 2333 nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 2334 nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2335 nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2336 nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 2337 2338 dma_poolp->ndmas = p_cfgp->max_rdcs; 2339 dma_poolp->num_chunks = num_chunks; 2340 dma_poolp->buf_allocated = B_TRUE; 2341 nxgep->rx_buf_pool_p = dma_poolp; 2342 dma_poolp->dma_buf_pool_p = dma_buf_p; 2343 2344 dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 2345 dma_cntl_poolp->buf_allocated = B_TRUE; 2346 nxgep->rx_cntl_pool_p = dma_cntl_poolp; 2347 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 2348 2349 /* Allocate the receive rings, too. */ 2350 nxgep->rx_rbr_rings = 2351 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2352 nxgep->rx_rbr_rings->rbr_rings = 2353 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2354 nxgep->rx_rcr_rings = 2355 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2356 nxgep->rx_rcr_rings->rcr_rings = 2357 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2358 nxgep->rx_mbox_areas_p = 2359 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2360 nxgep->rx_mbox_areas_p->rxmbox_areas = 2361 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2362 2363 nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2364 p_cfgp->max_rdcs; 2365 2366 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2367 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2368 2369 nxge_alloc_rx_mem_pool_exit: 2370 return (status); 2371 } 2372 2373 /* 2374 * nxge_alloc_rxb 2375 * 2376 * Allocate buffers for an RDC. 2377 * 2378 * Arguments: 2379 * nxgep 2380 * channel The channel to map into our kernel space. 2381 * 2382 * Notes: 2383 * 2384 * NPI function calls: 2385 * 2386 * NXGE function calls: 2387 * 2388 * Registers accessed: 2389 * 2390 * Context: 2391 * 2392 * Taking apart: 2393 * 2394 * Open questions: 2395 * 2396 */ 2397 nxge_status_t 2398 nxge_alloc_rxb( 2399 p_nxge_t nxgep, 2400 int channel) 2401 { 2402 size_t rx_buf_alloc_size; 2403 nxge_status_t status = NXGE_OK; 2404 2405 nxge_dma_common_t **data; 2406 nxge_dma_common_t **control; 2407 uint32_t *num_chunks; 2408 2409 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2410 2411 /* 2412 * Allocate memory for the receive buffers and descriptor rings. 2413 * Replace these allocation functions with the interface functions 2414 * provided by the partition manager if/when they are available. 2415 */ 2416 2417 /* 2418 * Allocate memory for the receive buffer blocks. 2419 */ 2420 rx_buf_alloc_size = (nxgep->rx_default_block_size * 2421 (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2422 2423 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2424 num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2425 2426 if ((status = nxge_alloc_rx_buf_dma( 2427 nxgep, channel, data, rx_buf_alloc_size, 2428 nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2429 return (status); 2430 } 2431 2432 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2433 "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2434 2435 /* 2436 * Allocate memory for descriptor rings and mailbox. 2437 */ 2438 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2439 2440 if ((status = nxge_alloc_rx_cntl_dma( 2441 nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2442 != NXGE_OK) { 2443 nxge_free_rx_cntl_dma(nxgep, *control); 2444 (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2445 nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2446 return (status); 2447 } 2448 2449 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2450 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2451 2452 return (status); 2453 } 2454 2455 void 2456 nxge_free_rxb( 2457 p_nxge_t nxgep, 2458 int channel) 2459 { 2460 nxge_dma_common_t *data; 2461 nxge_dma_common_t *control; 2462 uint32_t num_chunks; 2463 2464 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2465 2466 data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2467 num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2468 nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2469 2470 nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2471 nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2472 2473 control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2474 nxge_free_rx_cntl_dma(nxgep, control); 2475 2476 nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2477 2478 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2479 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2480 2481 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2482 } 2483 2484 static void 2485 nxge_free_rx_mem_pool(p_nxge_t nxgep) 2486 { 2487 int rdc_max = NXGE_MAX_RDCS; 2488 2489 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 2490 2491 if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 2492 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2493 "<== nxge_free_rx_mem_pool " 2494 "(null rx buf pool or buf not allocated")); 2495 return; 2496 } 2497 if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 2498 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2499 "<== nxge_free_rx_mem_pool " 2500 "(null rx cntl buf pool or cntl buf not allocated")); 2501 return; 2502 } 2503 2504 KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2505 sizeof (p_nxge_dma_common_t) * rdc_max); 2506 KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 2507 2508 KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2509 sizeof (uint32_t) * rdc_max); 2510 KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2511 sizeof (p_nxge_dma_common_t) * rdc_max); 2512 KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 2513 2514 nxgep->rx_buf_pool_p = 0; 2515 nxgep->rx_cntl_pool_p = 0; 2516 2517 KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2518 sizeof (p_rx_rbr_ring_t) * rdc_max); 2519 KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2520 KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2521 sizeof (p_rx_rcr_ring_t) * rdc_max); 2522 KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2523 KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2524 sizeof (p_rx_mbox_t) * rdc_max); 2525 KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2526 2527 nxgep->rx_rbr_rings = 0; 2528 nxgep->rx_rcr_rings = 0; 2529 nxgep->rx_mbox_areas_p = 0; 2530 2531 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 2532 } 2533 2534 2535 static nxge_status_t 2536 nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 2537 p_nxge_dma_common_t *dmap, 2538 size_t alloc_size, size_t block_size, uint32_t *num_chunks) 2539 { 2540 p_nxge_dma_common_t rx_dmap; 2541 nxge_status_t status = NXGE_OK; 2542 size_t total_alloc_size; 2543 size_t allocated = 0; 2544 int i, size_index, array_size; 2545 boolean_t use_kmem_alloc = B_FALSE; 2546 2547 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 2548 2549 rx_dmap = (p_nxge_dma_common_t) 2550 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 2551 KM_SLEEP); 2552 2553 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2554 " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 2555 dma_channel, alloc_size, block_size, dmap)); 2556 2557 total_alloc_size = alloc_size; 2558 2559 #if defined(RX_USE_RECLAIM_POST) 2560 total_alloc_size = alloc_size + alloc_size/4; 2561 #endif 2562 2563 i = 0; 2564 size_index = 0; 2565 array_size = sizeof (alloc_sizes)/sizeof (size_t); 2566 while ((alloc_sizes[size_index] < alloc_size) && 2567 (size_index < array_size)) 2568 size_index++; 2569 if (size_index >= array_size) { 2570 size_index = array_size - 1; 2571 } 2572 2573 /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2574 if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2575 use_kmem_alloc = B_TRUE; 2576 #if defined(__i386) || defined(__amd64) 2577 size_index = 0; 2578 #endif 2579 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2580 "==> nxge_alloc_rx_buf_dma: " 2581 "Neptune use kmem_alloc() - size_index %d", 2582 size_index)); 2583 } 2584 2585 while ((allocated < total_alloc_size) && 2586 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 2587 rx_dmap[i].dma_chunk_index = i; 2588 rx_dmap[i].block_size = block_size; 2589 rx_dmap[i].alength = alloc_sizes[size_index]; 2590 rx_dmap[i].orig_alength = rx_dmap[i].alength; 2591 rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 2592 rx_dmap[i].dma_channel = dma_channel; 2593 rx_dmap[i].contig_alloc_type = B_FALSE; 2594 rx_dmap[i].kmem_alloc_type = B_FALSE; 2595 rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 2596 2597 /* 2598 * N2/NIU: data buffers must be contiguous as the driver 2599 * needs to call Hypervisor api to set up 2600 * logical pages. 2601 */ 2602 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 2603 rx_dmap[i].contig_alloc_type = B_TRUE; 2604 rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2605 } else if (use_kmem_alloc) { 2606 /* For Neptune, use kmem_alloc */ 2607 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2608 "==> nxge_alloc_rx_buf_dma: " 2609 "Neptune use kmem_alloc()")); 2610 rx_dmap[i].kmem_alloc_type = B_TRUE; 2611 rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 2612 } 2613 2614 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2615 "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 2616 "i %d nblocks %d alength %d", 2617 dma_channel, i, &rx_dmap[i], block_size, 2618 i, rx_dmap[i].nblocks, 2619 rx_dmap[i].alength)); 2620 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2621 &nxge_rx_dma_attr, 2622 rx_dmap[i].alength, 2623 &nxge_dev_buf_dma_acc_attr, 2624 DDI_DMA_READ | DDI_DMA_STREAMING, 2625 (p_nxge_dma_common_t)(&rx_dmap[i])); 2626 if (status != NXGE_OK) { 2627 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2628 "nxge_alloc_rx_buf_dma: Alloc Failed: " 2629 "dma %d size_index %d size requested %d", 2630 dma_channel, 2631 size_index, 2632 rx_dmap[i].alength)); 2633 size_index--; 2634 } else { 2635 rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2636 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2637 " nxge_alloc_rx_buf_dma DONE alloc mem: " 2638 "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2639 "buf_alloc_state %d alloc_type %d", 2640 dma_channel, 2641 &rx_dmap[i], 2642 rx_dmap[i].kaddrp, 2643 rx_dmap[i].alength, 2644 rx_dmap[i].buf_alloc_state, 2645 rx_dmap[i].buf_alloc_type)); 2646 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2647 " alloc_rx_buf_dma allocated rdc %d " 2648 "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2649 dma_channel, i, rx_dmap[i].alength, 2650 rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2651 rx_dmap[i].kaddrp)); 2652 i++; 2653 allocated += alloc_sizes[size_index]; 2654 } 2655 } 2656 2657 if (allocated < total_alloc_size) { 2658 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2659 "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 2660 "allocated 0x%x requested 0x%x", 2661 dma_channel, 2662 allocated, total_alloc_size)); 2663 status = NXGE_ERROR; 2664 goto nxge_alloc_rx_mem_fail1; 2665 } 2666 2667 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2668 "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 2669 "allocated 0x%x requested 0x%x", 2670 dma_channel, 2671 allocated, total_alloc_size)); 2672 2673 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2674 " alloc_rx_buf_dma rdc %d allocated %d chunks", 2675 dma_channel, i)); 2676 *num_chunks = i; 2677 *dmap = rx_dmap; 2678 2679 goto nxge_alloc_rx_mem_exit; 2680 2681 nxge_alloc_rx_mem_fail1: 2682 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2683 2684 nxge_alloc_rx_mem_exit: 2685 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2686 "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 2687 2688 return (status); 2689 } 2690 2691 /*ARGSUSED*/ 2692 static void 2693 nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 2694 uint32_t num_chunks) 2695 { 2696 int i; 2697 2698 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2699 "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 2700 2701 if (dmap == 0) 2702 return; 2703 2704 for (i = 0; i < num_chunks; i++) { 2705 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2706 "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 2707 i, dmap)); 2708 nxge_dma_free_rx_data_buf(dmap++); 2709 } 2710 2711 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 2712 } 2713 2714 /*ARGSUSED*/ 2715 static nxge_status_t 2716 nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 2717 p_nxge_dma_common_t *dmap, size_t size) 2718 { 2719 p_nxge_dma_common_t rx_dmap; 2720 nxge_status_t status = NXGE_OK; 2721 2722 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 2723 2724 rx_dmap = (p_nxge_dma_common_t) 2725 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 2726 2727 rx_dmap->contig_alloc_type = B_FALSE; 2728 rx_dmap->kmem_alloc_type = B_FALSE; 2729 2730 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2731 &nxge_desc_dma_attr, 2732 size, 2733 &nxge_dev_desc_dma_acc_attr, 2734 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2735 rx_dmap); 2736 if (status != NXGE_OK) { 2737 goto nxge_alloc_rx_cntl_dma_fail1; 2738 } 2739 2740 *dmap = rx_dmap; 2741 goto nxge_alloc_rx_cntl_dma_exit; 2742 2743 nxge_alloc_rx_cntl_dma_fail1: 2744 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 2745 2746 nxge_alloc_rx_cntl_dma_exit: 2747 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2748 "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 2749 2750 return (status); 2751 } 2752 2753 /*ARGSUSED*/ 2754 static void 2755 nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2756 { 2757 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2758 2759 if (dmap == 0) 2760 return; 2761 2762 nxge_dma_mem_free(dmap); 2763 2764 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2765 } 2766 2767 typedef struct { 2768 size_t tx_size; 2769 size_t cr_size; 2770 size_t threshhold; 2771 } nxge_tdc_sizes_t; 2772 2773 static 2774 nxge_status_t 2775 nxge_tdc_sizes( 2776 nxge_t *nxgep, 2777 nxge_tdc_sizes_t *sizes) 2778 { 2779 uint32_t threshhold; /* The bcopy() threshhold */ 2780 size_t tx_size; /* Transmit buffer size */ 2781 size_t cr_size; /* Completion ring size */ 2782 2783 /* 2784 * Assume that each DMA channel will be configured with the 2785 * default transmit buffer size for copying transmit data. 2786 * (If a packet is bigger than this, it will not be copied.) 2787 */ 2788 if (nxgep->niu_type == N2_NIU) { 2789 threshhold = TX_BCOPY_SIZE; 2790 } else { 2791 threshhold = nxge_bcopy_thresh; 2792 } 2793 tx_size = nxge_tx_ring_size * threshhold; 2794 2795 cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2796 cr_size += sizeof (txdma_mailbox_t); 2797 2798 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2799 if (nxgep->niu_type == N2_NIU) { 2800 if (!ISP2(tx_size)) { 2801 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2802 "==> nxge_tdc_sizes: Tx size" 2803 " must be power of 2")); 2804 return (NXGE_ERROR); 2805 } 2806 2807 if (tx_size > (1 << 22)) { 2808 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2809 "==> nxge_tdc_sizes: Tx size" 2810 " limited to 4M")); 2811 return (NXGE_ERROR); 2812 } 2813 2814 if (cr_size < 0x2000) 2815 cr_size = 0x2000; 2816 } 2817 #endif 2818 2819 sizes->threshhold = threshhold; 2820 sizes->tx_size = tx_size; 2821 sizes->cr_size = cr_size; 2822 2823 return (NXGE_OK); 2824 } 2825 /* 2826 * nxge_alloc_txb 2827 * 2828 * Allocate buffers for an TDC. 2829 * 2830 * Arguments: 2831 * nxgep 2832 * channel The channel to map into our kernel space. 2833 * 2834 * Notes: 2835 * 2836 * NPI function calls: 2837 * 2838 * NXGE function calls: 2839 * 2840 * Registers accessed: 2841 * 2842 * Context: 2843 * 2844 * Taking apart: 2845 * 2846 * Open questions: 2847 * 2848 */ 2849 nxge_status_t 2850 nxge_alloc_txb( 2851 p_nxge_t nxgep, 2852 int channel) 2853 { 2854 nxge_dma_common_t **dma_buf_p; 2855 nxge_dma_common_t **dma_cntl_p; 2856 uint32_t *num_chunks; 2857 nxge_status_t status = NXGE_OK; 2858 2859 nxge_tdc_sizes_t sizes; 2860 2861 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2862 2863 if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2864 return (NXGE_ERROR); 2865 2866 /* 2867 * Allocate memory for transmit buffers and descriptor rings. 2868 * Replace these allocation functions with the interface functions 2869 * provided by the partition manager Real Soon Now. 2870 */ 2871 dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2872 num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2873 2874 dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2875 2876 /* 2877 * Allocate memory for transmit buffers and descriptor rings. 2878 * Replace allocation functions with interface functions provided 2879 * by the partition manager when it is available. 2880 * 2881 * Allocate memory for the transmit buffer pool. 2882 */ 2883 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2884 "sizes: tx: %ld, cr:%ld, th:%ld", 2885 sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2886 2887 *num_chunks = 0; 2888 status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2889 sizes.tx_size, sizes.threshhold, num_chunks); 2890 if (status != NXGE_OK) { 2891 cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2892 return (status); 2893 } 2894 2895 /* 2896 * Allocate memory for descriptor rings and mailbox. 2897 */ 2898 status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2899 sizes.cr_size); 2900 if (status != NXGE_OK) { 2901 nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2902 cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2903 return (status); 2904 } 2905 2906 return (NXGE_OK); 2907 } 2908 2909 void 2910 nxge_free_txb( 2911 p_nxge_t nxgep, 2912 int channel) 2913 { 2914 nxge_dma_common_t *data; 2915 nxge_dma_common_t *control; 2916 uint32_t num_chunks; 2917 2918 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2919 2920 data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2921 num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2922 nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2923 2924 nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2925 nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2926 2927 control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2928 nxge_free_tx_cntl_dma(nxgep, control); 2929 2930 nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2931 2932 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2933 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2934 2935 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 2936 } 2937 2938 /* 2939 * nxge_alloc_tx_mem_pool 2940 * 2941 * This function allocates all of the per-port TDC control data structures. 2942 * The per-channel (TDC) data structures are allocated when needed. 2943 * 2944 * Arguments: 2945 * nxgep 2946 * 2947 * Notes: 2948 * 2949 * Context: 2950 * Any domain 2951 */ 2952 nxge_status_t 2953 nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 2954 { 2955 nxge_hw_pt_cfg_t *p_cfgp; 2956 nxge_dma_pool_t *dma_poolp; 2957 nxge_dma_common_t **dma_buf_p; 2958 nxge_dma_pool_t *dma_cntl_poolp; 2959 nxge_dma_common_t **dma_cntl_p; 2960 uint32_t *num_chunks; /* per dma */ 2961 int tdc_max; 2962 2963 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 2964 2965 p_cfgp = &nxgep->pt_config.hw_config; 2966 tdc_max = NXGE_MAX_TDCS; 2967 2968 /* 2969 * Allocate memory for each transmit DMA channel. 2970 */ 2971 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2972 KM_SLEEP); 2973 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2974 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2975 2976 dma_cntl_poolp = (p_nxge_dma_pool_t) 2977 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2978 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2979 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2980 2981 if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 2982 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2983 "nxge_alloc_tx_mem_pool: TDC too high %d, " 2984 "set to default %d", 2985 nxge_tx_ring_size, TDC_DEFAULT_MAX)); 2986 nxge_tx_ring_size = TDC_DEFAULT_MAX; 2987 } 2988 2989 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2990 /* 2991 * N2/NIU has limitation on the descriptor sizes (contiguous 2992 * memory allocation on data buffers to 4M (contig_mem_alloc) 2993 * and little endian for control buffers (must use the ddi/dki mem alloc 2994 * function). The transmit ring is limited to 8K (includes the 2995 * mailbox). 2996 */ 2997 if (nxgep->niu_type == N2_NIU) { 2998 if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 2999 (!ISP2(nxge_tx_ring_size))) { 3000 nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 3001 } 3002 } 3003 #endif 3004 3005 nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 3006 3007 num_chunks = (uint32_t *)KMEM_ZALLOC( 3008 sizeof (uint32_t) * tdc_max, KM_SLEEP); 3009 3010 dma_poolp->ndmas = p_cfgp->tdc.owned; 3011 dma_poolp->num_chunks = num_chunks; 3012 dma_poolp->dma_buf_pool_p = dma_buf_p; 3013 nxgep->tx_buf_pool_p = dma_poolp; 3014 3015 dma_poolp->buf_allocated = B_TRUE; 3016 3017 dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 3018 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 3019 nxgep->tx_cntl_pool_p = dma_cntl_poolp; 3020 3021 dma_cntl_poolp->buf_allocated = B_TRUE; 3022 3023 nxgep->tx_rings = 3024 KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3025 nxgep->tx_rings->rings = 3026 KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3027 nxgep->tx_mbox_areas_p = 3028 KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3029 nxgep->tx_mbox_areas_p->txmbox_areas_p = 3030 KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 3031 3032 nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 3033 3034 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 3035 "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 3036 tdc_max, dma_poolp->ndmas)); 3037 3038 return (NXGE_OK); 3039 } 3040 3041 nxge_status_t 3042 nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 3043 p_nxge_dma_common_t *dmap, size_t alloc_size, 3044 size_t block_size, uint32_t *num_chunks) 3045 { 3046 p_nxge_dma_common_t tx_dmap; 3047 nxge_status_t status = NXGE_OK; 3048 size_t total_alloc_size; 3049 size_t allocated = 0; 3050 int i, size_index, array_size; 3051 3052 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 3053 3054 tx_dmap = (p_nxge_dma_common_t) 3055 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 3056 KM_SLEEP); 3057 3058 total_alloc_size = alloc_size; 3059 i = 0; 3060 size_index = 0; 3061 array_size = sizeof (alloc_sizes) / sizeof (size_t); 3062 while ((alloc_sizes[size_index] < alloc_size) && 3063 (size_index < array_size)) 3064 size_index++; 3065 if (size_index >= array_size) { 3066 size_index = array_size - 1; 3067 } 3068 3069 while ((allocated < total_alloc_size) && 3070 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 3071 3072 tx_dmap[i].dma_chunk_index = i; 3073 tx_dmap[i].block_size = block_size; 3074 tx_dmap[i].alength = alloc_sizes[size_index]; 3075 tx_dmap[i].orig_alength = tx_dmap[i].alength; 3076 tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 3077 tx_dmap[i].dma_channel = dma_channel; 3078 tx_dmap[i].contig_alloc_type = B_FALSE; 3079 tx_dmap[i].kmem_alloc_type = B_FALSE; 3080 3081 /* 3082 * N2/NIU: data buffers must be contiguous as the driver 3083 * needs to call Hypervisor api to set up 3084 * logical pages. 3085 */ 3086 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 3087 tx_dmap[i].contig_alloc_type = B_TRUE; 3088 } 3089 3090 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3091 &nxge_tx_dma_attr, 3092 tx_dmap[i].alength, 3093 &nxge_dev_buf_dma_acc_attr, 3094 DDI_DMA_WRITE | DDI_DMA_STREAMING, 3095 (p_nxge_dma_common_t)(&tx_dmap[i])); 3096 if (status != NXGE_OK) { 3097 size_index--; 3098 } else { 3099 i++; 3100 allocated += alloc_sizes[size_index]; 3101 } 3102 } 3103 3104 if (allocated < total_alloc_size) { 3105 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3106 "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 3107 "allocated 0x%x requested 0x%x", 3108 dma_channel, 3109 allocated, total_alloc_size)); 3110 status = NXGE_ERROR; 3111 goto nxge_alloc_tx_mem_fail1; 3112 } 3113 3114 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3115 "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 3116 "allocated 0x%x requested 0x%x", 3117 dma_channel, 3118 allocated, total_alloc_size)); 3119 3120 *num_chunks = i; 3121 *dmap = tx_dmap; 3122 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3123 "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 3124 *dmap, i)); 3125 goto nxge_alloc_tx_mem_exit; 3126 3127 nxge_alloc_tx_mem_fail1: 3128 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 3129 3130 nxge_alloc_tx_mem_exit: 3131 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3132 "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 3133 3134 return (status); 3135 } 3136 3137 /*ARGSUSED*/ 3138 static void 3139 nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 3140 uint32_t num_chunks) 3141 { 3142 int i; 3143 3144 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 3145 3146 if (dmap == 0) 3147 return; 3148 3149 for (i = 0; i < num_chunks; i++) { 3150 nxge_dma_mem_free(dmap++); 3151 } 3152 3153 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 3154 } 3155 3156 /*ARGSUSED*/ 3157 nxge_status_t 3158 nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 3159 p_nxge_dma_common_t *dmap, size_t size) 3160 { 3161 p_nxge_dma_common_t tx_dmap; 3162 nxge_status_t status = NXGE_OK; 3163 3164 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 3165 tx_dmap = (p_nxge_dma_common_t) 3166 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 3167 3168 tx_dmap->contig_alloc_type = B_FALSE; 3169 tx_dmap->kmem_alloc_type = B_FALSE; 3170 3171 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3172 &nxge_desc_dma_attr, 3173 size, 3174 &nxge_dev_desc_dma_acc_attr, 3175 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3176 tx_dmap); 3177 if (status != NXGE_OK) { 3178 goto nxge_alloc_tx_cntl_dma_fail1; 3179 } 3180 3181 *dmap = tx_dmap; 3182 goto nxge_alloc_tx_cntl_dma_exit; 3183 3184 nxge_alloc_tx_cntl_dma_fail1: 3185 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 3186 3187 nxge_alloc_tx_cntl_dma_exit: 3188 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3189 "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 3190 3191 return (status); 3192 } 3193 3194 /*ARGSUSED*/ 3195 static void 3196 nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 3197 { 3198 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 3199 3200 if (dmap == 0) 3201 return; 3202 3203 nxge_dma_mem_free(dmap); 3204 3205 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 3206 } 3207 3208 /* 3209 * nxge_free_tx_mem_pool 3210 * 3211 * This function frees all of the per-port TDC control data structures. 3212 * The per-channel (TDC) data structures are freed when the channel 3213 * is stopped. 3214 * 3215 * Arguments: 3216 * nxgep 3217 * 3218 * Notes: 3219 * 3220 * Context: 3221 * Any domain 3222 */ 3223 static void 3224 nxge_free_tx_mem_pool(p_nxge_t nxgep) 3225 { 3226 int tdc_max = NXGE_MAX_TDCS; 3227 3228 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 3229 3230 if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3231 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3232 "<== nxge_free_tx_mem_pool " 3233 "(null tx buf pool or buf not allocated")); 3234 return; 3235 } 3236 if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3237 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3238 "<== nxge_free_tx_mem_pool " 3239 "(null tx cntl buf pool or cntl buf not allocated")); 3240 return; 3241 } 3242 3243 /* 1. Free the mailboxes. */ 3244 KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3245 sizeof (p_tx_mbox_t) * tdc_max); 3246 KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 3247 3248 nxgep->tx_mbox_areas_p = 0; 3249 3250 /* 2. Free the transmit ring arrays. */ 3251 KMEM_FREE(nxgep->tx_rings->rings, 3252 sizeof (p_tx_ring_t) * tdc_max); 3253 KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 3254 3255 nxgep->tx_rings = 0; 3256 3257 /* 3. Free the completion ring data structures. */ 3258 KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3259 sizeof (p_nxge_dma_common_t) * tdc_max); 3260 KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 3261 3262 nxgep->tx_cntl_pool_p = 0; 3263 3264 /* 4. Free the data ring data structures. */ 3265 KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3266 sizeof (uint32_t) * tdc_max); 3267 KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3268 sizeof (p_nxge_dma_common_t) * tdc_max); 3269 KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 3270 3271 nxgep->tx_buf_pool_p = 0; 3272 3273 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 3274 } 3275 3276 /*ARGSUSED*/ 3277 static nxge_status_t 3278 nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 3279 struct ddi_dma_attr *dma_attrp, 3280 size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 3281 p_nxge_dma_common_t dma_p) 3282 { 3283 caddr_t kaddrp; 3284 int ddi_status = DDI_SUCCESS; 3285 boolean_t contig_alloc_type; 3286 boolean_t kmem_alloc_type; 3287 3288 contig_alloc_type = dma_p->contig_alloc_type; 3289 3290 if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 3291 /* 3292 * contig_alloc_type for contiguous memory only allowed 3293 * for N2/NIU. 3294 */ 3295 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3296 "nxge_dma_mem_alloc: alloc type not allowed (%d)", 3297 dma_p->contig_alloc_type)); 3298 return (NXGE_ERROR | NXGE_DDI_FAILED); 3299 } 3300 3301 dma_p->dma_handle = NULL; 3302 dma_p->acc_handle = NULL; 3303 dma_p->kaddrp = dma_p->last_kaddrp = NULL; 3304 dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 3305 ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 3306 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 3307 if (ddi_status != DDI_SUCCESS) { 3308 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3309 "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 3310 return (NXGE_ERROR | NXGE_DDI_FAILED); 3311 } 3312 3313 kmem_alloc_type = dma_p->kmem_alloc_type; 3314 3315 switch (contig_alloc_type) { 3316 case B_FALSE: 3317 switch (kmem_alloc_type) { 3318 case B_FALSE: 3319 ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 3320 length, 3321 acc_attr_p, 3322 xfer_flags, 3323 DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 3324 &dma_p->acc_handle); 3325 if (ddi_status != DDI_SUCCESS) { 3326 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3327 "nxge_dma_mem_alloc: " 3328 "ddi_dma_mem_alloc failed")); 3329 ddi_dma_free_handle(&dma_p->dma_handle); 3330 dma_p->dma_handle = NULL; 3331 return (NXGE_ERROR | NXGE_DDI_FAILED); 3332 } 3333 if (dma_p->alength < length) { 3334 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3335 "nxge_dma_mem_alloc:di_dma_mem_alloc " 3336 "< length.")); 3337 ddi_dma_mem_free(&dma_p->acc_handle); 3338 ddi_dma_free_handle(&dma_p->dma_handle); 3339 dma_p->acc_handle = NULL; 3340 dma_p->dma_handle = NULL; 3341 return (NXGE_ERROR); 3342 } 3343 3344 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3345 NULL, 3346 kaddrp, dma_p->alength, xfer_flags, 3347 DDI_DMA_DONTWAIT, 3348 0, &dma_p->dma_cookie, &dma_p->ncookies); 3349 if (ddi_status != DDI_DMA_MAPPED) { 3350 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3351 "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3352 "failed " 3353 "(staus 0x%x ncookies %d.)", ddi_status, 3354 dma_p->ncookies)); 3355 if (dma_p->acc_handle) { 3356 ddi_dma_mem_free(&dma_p->acc_handle); 3357 dma_p->acc_handle = NULL; 3358 } 3359 ddi_dma_free_handle(&dma_p->dma_handle); 3360 dma_p->dma_handle = NULL; 3361 return (NXGE_ERROR | NXGE_DDI_FAILED); 3362 } 3363 3364 if (dma_p->ncookies != 1) { 3365 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3366 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3367 "> 1 cookie" 3368 "(staus 0x%x ncookies %d.)", ddi_status, 3369 dma_p->ncookies)); 3370 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3371 if (dma_p->acc_handle) { 3372 ddi_dma_mem_free(&dma_p->acc_handle); 3373 dma_p->acc_handle = NULL; 3374 } 3375 ddi_dma_free_handle(&dma_p->dma_handle); 3376 dma_p->dma_handle = NULL; 3377 dma_p->acc_handle = NULL; 3378 return (NXGE_ERROR); 3379 } 3380 break; 3381 3382 case B_TRUE: 3383 kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3384 if (kaddrp == NULL) { 3385 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3386 "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3387 "kmem alloc failed")); 3388 return (NXGE_ERROR); 3389 } 3390 3391 dma_p->alength = length; 3392 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3393 NULL, kaddrp, dma_p->alength, xfer_flags, 3394 DDI_DMA_DONTWAIT, 0, 3395 &dma_p->dma_cookie, &dma_p->ncookies); 3396 if (ddi_status != DDI_DMA_MAPPED) { 3397 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3398 "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3399 "(kmem_alloc) failed kaddrp $%p length %d " 3400 "(staus 0x%x (%d) ncookies %d.)", 3401 kaddrp, length, 3402 ddi_status, ddi_status, dma_p->ncookies)); 3403 KMEM_FREE(kaddrp, length); 3404 dma_p->acc_handle = NULL; 3405 ddi_dma_free_handle(&dma_p->dma_handle); 3406 dma_p->dma_handle = NULL; 3407 dma_p->kaddrp = NULL; 3408 return (NXGE_ERROR | NXGE_DDI_FAILED); 3409 } 3410 3411 if (dma_p->ncookies != 1) { 3412 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3413 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3414 "(kmem_alloc) > 1 cookie" 3415 "(staus 0x%x ncookies %d.)", ddi_status, 3416 dma_p->ncookies)); 3417 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3418 KMEM_FREE(kaddrp, length); 3419 ddi_dma_free_handle(&dma_p->dma_handle); 3420 dma_p->dma_handle = NULL; 3421 dma_p->acc_handle = NULL; 3422 dma_p->kaddrp = NULL; 3423 return (NXGE_ERROR); 3424 } 3425 3426 dma_p->kaddrp = kaddrp; 3427 3428 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 3429 "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 3430 "kaddr $%p alength %d", 3431 dma_p, 3432 kaddrp, 3433 dma_p->alength)); 3434 break; 3435 } 3436 break; 3437 3438 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3439 case B_TRUE: 3440 kaddrp = (caddr_t)contig_mem_alloc(length); 3441 if (kaddrp == NULL) { 3442 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3443 "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 3444 ddi_dma_free_handle(&dma_p->dma_handle); 3445 return (NXGE_ERROR | NXGE_DDI_FAILED); 3446 } 3447 3448 dma_p->alength = length; 3449 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 3450 kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 3451 &dma_p->dma_cookie, &dma_p->ncookies); 3452 if (ddi_status != DDI_DMA_MAPPED) { 3453 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3454 "nxge_dma_mem_alloc:di_dma_addr_bind failed " 3455 "(status 0x%x ncookies %d.)", ddi_status, 3456 dma_p->ncookies)); 3457 3458 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3459 "==> nxge_dma_mem_alloc: (not mapped)" 3460 "length %lu (0x%x) " 3461 "free contig kaddrp $%p " 3462 "va_to_pa $%p", 3463 length, length, 3464 kaddrp, 3465 va_to_pa(kaddrp))); 3466 3467 3468 contig_mem_free((void *)kaddrp, length); 3469 ddi_dma_free_handle(&dma_p->dma_handle); 3470 3471 dma_p->dma_handle = NULL; 3472 dma_p->acc_handle = NULL; 3473 dma_p->alength = NULL; 3474 dma_p->kaddrp = NULL; 3475 3476 return (NXGE_ERROR | NXGE_DDI_FAILED); 3477 } 3478 3479 if (dma_p->ncookies != 1 || 3480 (dma_p->dma_cookie.dmac_laddress == NULL)) { 3481 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3482 "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 3483 "cookie or " 3484 "dmac_laddress is NULL $%p size %d " 3485 " (status 0x%x ncookies %d.)", 3486 ddi_status, 3487 dma_p->dma_cookie.dmac_laddress, 3488 dma_p->dma_cookie.dmac_size, 3489 dma_p->ncookies)); 3490 3491 contig_mem_free((void *)kaddrp, length); 3492 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3493 ddi_dma_free_handle(&dma_p->dma_handle); 3494 3495 dma_p->alength = 0; 3496 dma_p->dma_handle = NULL; 3497 dma_p->acc_handle = NULL; 3498 dma_p->kaddrp = NULL; 3499 3500 return (NXGE_ERROR | NXGE_DDI_FAILED); 3501 } 3502 break; 3503 3504 #else 3505 case B_TRUE: 3506 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3507 "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 3508 return (NXGE_ERROR | NXGE_DDI_FAILED); 3509 #endif 3510 } 3511 3512 dma_p->kaddrp = kaddrp; 3513 dma_p->last_kaddrp = (unsigned char *)kaddrp + 3514 dma_p->alength - RXBUF_64B_ALIGNED; 3515 #if defined(__i386) 3516 dma_p->ioaddr_pp = 3517 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3518 #else 3519 dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3520 #endif 3521 dma_p->last_ioaddr_pp = 3522 #if defined(__i386) 3523 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3524 #else 3525 (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3526 #endif 3527 dma_p->alength - RXBUF_64B_ALIGNED; 3528 3529 NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 3530 3531 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3532 dma_p->orig_ioaddr_pp = 3533 (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3534 dma_p->orig_alength = length; 3535 dma_p->orig_kaddrp = kaddrp; 3536 dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 3537 #endif 3538 3539 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 3540 "dma buffer allocated: dma_p $%p " 3541 "return dmac_ladress from cookie $%p cookie dmac_size %d " 3542 "dma_p->ioaddr_p $%p " 3543 "dma_p->orig_ioaddr_p $%p " 3544 "orig_vatopa $%p " 3545 "alength %d (0x%x) " 3546 "kaddrp $%p " 3547 "length %d (0x%x)", 3548 dma_p, 3549 dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 3550 dma_p->ioaddr_pp, 3551 dma_p->orig_ioaddr_pp, 3552 dma_p->orig_vatopa, 3553 dma_p->alength, dma_p->alength, 3554 kaddrp, 3555 length, length)); 3556 3557 return (NXGE_OK); 3558 } 3559 3560 static void 3561 nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 3562 { 3563 if (dma_p->dma_handle != NULL) { 3564 if (dma_p->ncookies) { 3565 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3566 dma_p->ncookies = 0; 3567 } 3568 ddi_dma_free_handle(&dma_p->dma_handle); 3569 dma_p->dma_handle = NULL; 3570 } 3571 3572 if (dma_p->acc_handle != NULL) { 3573 ddi_dma_mem_free(&dma_p->acc_handle); 3574 dma_p->acc_handle = NULL; 3575 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3576 } 3577 3578 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3579 if (dma_p->contig_alloc_type && 3580 dma_p->orig_kaddrp && dma_p->orig_alength) { 3581 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 3582 "kaddrp $%p (orig_kaddrp $%p)" 3583 "mem type %d ", 3584 "orig_alength %d " 3585 "alength 0x%x (%d)", 3586 dma_p->kaddrp, 3587 dma_p->orig_kaddrp, 3588 dma_p->contig_alloc_type, 3589 dma_p->orig_alength, 3590 dma_p->alength, dma_p->alength)); 3591 3592 contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 3593 dma_p->orig_alength = NULL; 3594 dma_p->orig_kaddrp = NULL; 3595 dma_p->contig_alloc_type = B_FALSE; 3596 } 3597 #endif 3598 dma_p->kaddrp = NULL; 3599 dma_p->alength = NULL; 3600 } 3601 3602 static void 3603 nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3604 { 3605 uint64_t kaddr; 3606 uint32_t buf_size; 3607 3608 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3609 3610 if (dma_p->dma_handle != NULL) { 3611 if (dma_p->ncookies) { 3612 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3613 dma_p->ncookies = 0; 3614 } 3615 ddi_dma_free_handle(&dma_p->dma_handle); 3616 dma_p->dma_handle = NULL; 3617 } 3618 3619 if (dma_p->acc_handle != NULL) { 3620 ddi_dma_mem_free(&dma_p->acc_handle); 3621 dma_p->acc_handle = NULL; 3622 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3623 } 3624 3625 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3626 "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3627 dma_p, 3628 dma_p->buf_alloc_state)); 3629 3630 if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3631 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3632 "<== nxge_dma_free_rx_data_buf: " 3633 "outstanding data buffers")); 3634 return; 3635 } 3636 3637 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3638 if (dma_p->contig_alloc_type && 3639 dma_p->orig_kaddrp && dma_p->orig_alength) { 3640 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3641 "kaddrp $%p (orig_kaddrp $%p)" 3642 "mem type %d ", 3643 "orig_alength %d " 3644 "alength 0x%x (%d)", 3645 dma_p->kaddrp, 3646 dma_p->orig_kaddrp, 3647 dma_p->contig_alloc_type, 3648 dma_p->orig_alength, 3649 dma_p->alength, dma_p->alength)); 3650 3651 kaddr = (uint64_t)dma_p->orig_kaddrp; 3652 buf_size = dma_p->orig_alength; 3653 nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3654 dma_p->orig_alength = NULL; 3655 dma_p->orig_kaddrp = NULL; 3656 dma_p->contig_alloc_type = B_FALSE; 3657 dma_p->kaddrp = NULL; 3658 dma_p->alength = NULL; 3659 return; 3660 } 3661 #endif 3662 3663 if (dma_p->kmem_alloc_type) { 3664 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3665 "nxge_dma_free_rx_data_buf: free kmem " 3666 "kaddrp $%p (orig_kaddrp $%p)" 3667 "alloc type %d " 3668 "orig_alength %d " 3669 "alength 0x%x (%d)", 3670 dma_p->kaddrp, 3671 dma_p->orig_kaddrp, 3672 dma_p->kmem_alloc_type, 3673 dma_p->orig_alength, 3674 dma_p->alength, dma_p->alength)); 3675 #if defined(__i386) 3676 kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3677 #else 3678 kaddr = (uint64_t)dma_p->kaddrp; 3679 #endif 3680 buf_size = dma_p->orig_alength; 3681 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3682 "nxge_dma_free_rx_data_buf: free dmap $%p " 3683 "kaddr $%p buf_size %d", 3684 dma_p, 3685 kaddr, buf_size)); 3686 nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3687 dma_p->alength = 0; 3688 dma_p->orig_alength = 0; 3689 dma_p->kaddrp = NULL; 3690 dma_p->kmem_alloc_type = B_FALSE; 3691 } 3692 3693 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3694 } 3695 3696 /* 3697 * nxge_m_start() -- start transmitting and receiving. 3698 * 3699 * This function is called by the MAC layer when the first 3700 * stream is open to prepare the hardware ready for sending 3701 * and transmitting packets. 3702 */ 3703 static int 3704 nxge_m_start(void *arg) 3705 { 3706 p_nxge_t nxgep = (p_nxge_t)arg; 3707 3708 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 3709 3710 if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 3711 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 3712 } 3713 3714 MUTEX_ENTER(nxgep->genlock); 3715 if (nxge_init(nxgep) != NXGE_OK) { 3716 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3717 "<== nxge_m_start: initialization failed")); 3718 MUTEX_EXIT(nxgep->genlock); 3719 return (EIO); 3720 } 3721 3722 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 3723 goto nxge_m_start_exit; 3724 /* 3725 * Start timer to check the system error and tx hangs 3726 */ 3727 if (!isLDOMguest(nxgep)) 3728 nxgep->nxge_timerid = nxge_start_timer(nxgep, 3729 nxge_check_hw_state, NXGE_CHECK_TIMER); 3730 #if defined(sun4v) 3731 else 3732 nxge_hio_start_timer(nxgep); 3733 #endif 3734 3735 nxgep->link_notify = B_TRUE; 3736 3737 nxgep->nxge_mac_state = NXGE_MAC_STARTED; 3738 3739 nxge_m_start_exit: 3740 MUTEX_EXIT(nxgep->genlock); 3741 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 3742 return (0); 3743 } 3744 3745 /* 3746 * nxge_m_stop(): stop transmitting and receiving. 3747 */ 3748 static void 3749 nxge_m_stop(void *arg) 3750 { 3751 p_nxge_t nxgep = (p_nxge_t)arg; 3752 3753 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 3754 3755 MUTEX_ENTER(nxgep->genlock); 3756 nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 3757 3758 if (nxgep->nxge_timerid) { 3759 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 3760 nxgep->nxge_timerid = 0; 3761 } 3762 3763 nxge_uninit(nxgep); 3764 3765 nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 3766 3767 MUTEX_EXIT(nxgep->genlock); 3768 3769 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 3770 } 3771 3772 static int 3773 nxge_m_unicst(void *arg, const uint8_t *macaddr) 3774 { 3775 p_nxge_t nxgep = (p_nxge_t)arg; 3776 struct ether_addr addrp; 3777 3778 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_m_unicst")); 3779 3780 bcopy(macaddr, (uint8_t *)&addrp, ETHERADDRL); 3781 if (nxge_set_mac_addr(nxgep, &addrp)) { 3782 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3783 "<== nxge_m_unicst: set unitcast failed")); 3784 return (EINVAL); 3785 } 3786 3787 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_unicst")); 3788 3789 return (0); 3790 } 3791 3792 static int 3793 nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 3794 { 3795 p_nxge_t nxgep = (p_nxge_t)arg; 3796 struct ether_addr addrp; 3797 3798 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3799 "==> nxge_m_multicst: add %d", add)); 3800 3801 bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 3802 if (add) { 3803 if (nxge_add_mcast_addr(nxgep, &addrp)) { 3804 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3805 "<== nxge_m_multicst: add multicast failed")); 3806 return (EINVAL); 3807 } 3808 } else { 3809 if (nxge_del_mcast_addr(nxgep, &addrp)) { 3810 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3811 "<== nxge_m_multicst: del multicast failed")); 3812 return (EINVAL); 3813 } 3814 } 3815 3816 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 3817 3818 return (0); 3819 } 3820 3821 static int 3822 nxge_m_promisc(void *arg, boolean_t on) 3823 { 3824 p_nxge_t nxgep = (p_nxge_t)arg; 3825 3826 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3827 "==> nxge_m_promisc: on %d", on)); 3828 3829 if (nxge_set_promisc(nxgep, on)) { 3830 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3831 "<== nxge_m_promisc: set promisc failed")); 3832 return (EINVAL); 3833 } 3834 3835 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3836 "<== nxge_m_promisc: on %d", on)); 3837 3838 return (0); 3839 } 3840 3841 static void 3842 nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 3843 { 3844 p_nxge_t nxgep = (p_nxge_t)arg; 3845 struct iocblk *iocp; 3846 boolean_t need_privilege; 3847 int err; 3848 int cmd; 3849 3850 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 3851 3852 iocp = (struct iocblk *)mp->b_rptr; 3853 iocp->ioc_error = 0; 3854 need_privilege = B_TRUE; 3855 cmd = iocp->ioc_cmd; 3856 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 3857 switch (cmd) { 3858 default: 3859 miocnak(wq, mp, 0, EINVAL); 3860 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 3861 return; 3862 3863 case LB_GET_INFO_SIZE: 3864 case LB_GET_INFO: 3865 case LB_GET_MODE: 3866 need_privilege = B_FALSE; 3867 break; 3868 case LB_SET_MODE: 3869 break; 3870 3871 3872 case NXGE_GET_MII: 3873 case NXGE_PUT_MII: 3874 case NXGE_GET64: 3875 case NXGE_PUT64: 3876 case NXGE_GET_TX_RING_SZ: 3877 case NXGE_GET_TX_DESC: 3878 case NXGE_TX_SIDE_RESET: 3879 case NXGE_RX_SIDE_RESET: 3880 case NXGE_GLOBAL_RESET: 3881 case NXGE_RESET_MAC: 3882 case NXGE_TX_REGS_DUMP: 3883 case NXGE_RX_REGS_DUMP: 3884 case NXGE_INT_REGS_DUMP: 3885 case NXGE_VIR_INT_REGS_DUMP: 3886 case NXGE_PUT_TCAM: 3887 case NXGE_GET_TCAM: 3888 case NXGE_RTRACE: 3889 case NXGE_RDUMP: 3890 3891 need_privilege = B_FALSE; 3892 break; 3893 case NXGE_INJECT_ERR: 3894 cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 3895 nxge_err_inject(nxgep, wq, mp); 3896 break; 3897 } 3898 3899 if (need_privilege) { 3900 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 3901 if (err != 0) { 3902 miocnak(wq, mp, 0, err); 3903 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3904 "<== nxge_m_ioctl: no priv")); 3905 return; 3906 } 3907 } 3908 3909 switch (cmd) { 3910 3911 case LB_GET_MODE: 3912 case LB_SET_MODE: 3913 case LB_GET_INFO_SIZE: 3914 case LB_GET_INFO: 3915 nxge_loopback_ioctl(nxgep, wq, mp, iocp); 3916 break; 3917 3918 case NXGE_GET_MII: 3919 case NXGE_PUT_MII: 3920 case NXGE_PUT_TCAM: 3921 case NXGE_GET_TCAM: 3922 case NXGE_GET64: 3923 case NXGE_PUT64: 3924 case NXGE_GET_TX_RING_SZ: 3925 case NXGE_GET_TX_DESC: 3926 case NXGE_TX_SIDE_RESET: 3927 case NXGE_RX_SIDE_RESET: 3928 case NXGE_GLOBAL_RESET: 3929 case NXGE_RESET_MAC: 3930 case NXGE_TX_REGS_DUMP: 3931 case NXGE_RX_REGS_DUMP: 3932 case NXGE_INT_REGS_DUMP: 3933 case NXGE_VIR_INT_REGS_DUMP: 3934 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 3935 "==> nxge_m_ioctl: cmd 0x%x", cmd)); 3936 nxge_hw_ioctl(nxgep, wq, mp, iocp); 3937 break; 3938 } 3939 3940 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 3941 } 3942 3943 extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 3944 3945 static void 3946 nxge_m_resources(void *arg) 3947 { 3948 p_nxge_t nxgep = arg; 3949 mac_rx_fifo_t mrf; 3950 3951 nxge_grp_set_t *set = &nxgep->rx_set; 3952 uint8_t rdc; 3953 3954 rx_rcr_ring_t *ring; 3955 3956 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_m_resources")); 3957 3958 MUTEX_ENTER(nxgep->genlock); 3959 3960 if (set->owned.map == 0) { 3961 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 3962 "nxge_m_resources: no receive resources")); 3963 goto nxge_m_resources_exit; 3964 } 3965 3966 /* 3967 * CR 6492541 Check to see if the drv_state has been initialized, 3968 * if not * call nxge_init(). 3969 */ 3970 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 3971 if (nxge_init(nxgep) != NXGE_OK) 3972 goto nxge_m_resources_exit; 3973 } 3974 3975 mrf.mrf_type = MAC_RX_FIFO; 3976 mrf.mrf_blank = nxge_rx_hw_blank; 3977 mrf.mrf_arg = (void *)nxgep; 3978 3979 mrf.mrf_normal_blank_time = 128; 3980 mrf.mrf_normal_pkt_count = 8; 3981 3982 /* 3983 * Export our receive resources to the MAC layer. 3984 */ 3985 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 3986 if ((1 << rdc) & set->owned.map) { 3987 ring = nxgep->rx_rcr_rings->rcr_rings[rdc]; 3988 if (ring == 0) { 3989 /* 3990 * This is a big deal only if we are 3991 * *not* in an LDOMs environment. 3992 */ 3993 if (nxgep->environs == SOLARIS_DOMAIN) { 3994 cmn_err(CE_NOTE, 3995 "==> nxge_m_resources: " 3996 "ring %d == 0", rdc); 3997 } 3998 continue; 3999 } 4000 ring->rcr_mac_handle = mac_resource_add 4001 (nxgep->mach, (mac_resource_t *)&mrf); 4002 4003 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4004 "==> nxge_m_resources: RDC %d RCR %p MAC handle %p", 4005 rdc, ring, ring->rcr_mac_handle)); 4006 } 4007 } 4008 4009 nxge_m_resources_exit: 4010 MUTEX_EXIT(nxgep->genlock); 4011 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_m_resources")); 4012 } 4013 4014 void 4015 nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, boolean_t factory) 4016 { 4017 p_nxge_mmac_stats_t mmac_stats; 4018 int i; 4019 nxge_mmac_t *mmac_info; 4020 4021 mmac_info = &nxgep->nxge_mmac_info; 4022 4023 mmac_stats = &nxgep->statsp->mmac_stats; 4024 mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 4025 mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 4026 4027 for (i = 0; i < ETHERADDRL; i++) { 4028 if (factory) { 4029 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4030 = mmac_info->factory_mac_pool[slot][ 4031 (ETHERADDRL-1) - i]; 4032 } else { 4033 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4034 = mmac_info->mac_pool[slot].addr[ 4035 (ETHERADDRL - 1) - i]; 4036 } 4037 } 4038 } 4039 4040 /* 4041 * nxge_altmac_set() -- Set an alternate MAC address 4042 */ 4043 static int 4044 nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, mac_addr_slot_t slot) 4045 { 4046 uint8_t addrn; 4047 uint8_t portn; 4048 npi_mac_addr_t altmac; 4049 hostinfo_t mac_rdc; 4050 p_nxge_class_pt_cfg_t clscfgp; 4051 4052 altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 4053 altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 4054 altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 4055 4056 portn = nxgep->mac.portnum; 4057 addrn = (uint8_t)slot - 1; 4058 4059 if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, portn, 4060 addrn, &altmac) != NPI_SUCCESS) 4061 return (EIO); 4062 4063 /* 4064 * Set the rdc table number for the host info entry 4065 * for this mac address slot. 4066 */ 4067 clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 4068 mac_rdc.value = 0; 4069 mac_rdc.bits.w0.rdc_tbl_num = clscfgp->mac_host_info[addrn].rdctbl; 4070 mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 4071 4072 if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 4073 nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 4074 return (EIO); 4075 } 4076 4077 /* 4078 * Enable comparison with the alternate MAC address. 4079 * While the first alternate addr is enabled by bit 1 of register 4080 * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 4081 * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 4082 * accordingly before calling npi_mac_altaddr_entry. 4083 */ 4084 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4085 addrn = (uint8_t)slot - 1; 4086 else 4087 addrn = (uint8_t)slot; 4088 4089 if (npi_mac_altaddr_enable(nxgep->npi_handle, portn, addrn) 4090 != NPI_SUCCESS) 4091 return (EIO); 4092 4093 return (0); 4094 } 4095 4096 /* 4097 * nxeg_m_mmac_add() - find an unused address slot, set the address 4098 * value to the one specified, enable the port to start filtering on 4099 * the new MAC address. Returns 0 on success. 4100 */ 4101 int 4102 nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr) 4103 { 4104 p_nxge_t nxgep = arg; 4105 mac_addr_slot_t slot; 4106 nxge_mmac_t *mmac_info; 4107 int err; 4108 nxge_status_t status; 4109 4110 mutex_enter(nxgep->genlock); 4111 4112 /* 4113 * Make sure that nxge is initialized, if _start() has 4114 * not been called. 4115 */ 4116 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4117 status = nxge_init(nxgep); 4118 if (status != NXGE_OK) { 4119 mutex_exit(nxgep->genlock); 4120 return (ENXIO); 4121 } 4122 } 4123 4124 mmac_info = &nxgep->nxge_mmac_info; 4125 if (mmac_info->naddrfree == 0) { 4126 mutex_exit(nxgep->genlock); 4127 return (ENOSPC); 4128 } 4129 if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 4130 maddr->mma_addrlen)) { 4131 mutex_exit(nxgep->genlock); 4132 return (EINVAL); 4133 } 4134 /* 4135 * Search for the first available slot. Because naddrfree 4136 * is not zero, we are guaranteed to find one. 4137 * Slot 0 is for unique (primary) MAC. The first alternate 4138 * MAC slot is slot 1. 4139 * Each of the first two ports of Neptune has 16 alternate 4140 * MAC slots but only the first 7 (of 15) slots have assigned factory 4141 * MAC addresses. We first search among the slots without bundled 4142 * factory MACs. If we fail to find one in that range, then we 4143 * search the slots with bundled factory MACs. A factory MAC 4144 * will be wasted while the slot is used with a user MAC address. 4145 * But the slot could be used by factory MAC again after calling 4146 * nxge_m_mmac_remove and nxge_m_mmac_reserve. 4147 */ 4148 if (mmac_info->num_factory_mmac < mmac_info->num_mmac) { 4149 for (slot = mmac_info->num_factory_mmac + 1; 4150 slot <= mmac_info->num_mmac; slot++) { 4151 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4152 break; 4153 } 4154 if (slot > mmac_info->num_mmac) { 4155 for (slot = 1; slot <= mmac_info->num_factory_mmac; 4156 slot++) { 4157 if (!(mmac_info->mac_pool[slot].flags 4158 & MMAC_SLOT_USED)) 4159 break; 4160 } 4161 } 4162 } else { 4163 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 4164 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4165 break; 4166 } 4167 } 4168 ASSERT(slot <= mmac_info->num_mmac); 4169 if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) != 0) { 4170 mutex_exit(nxgep->genlock); 4171 return (err); 4172 } 4173 bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 4174 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 4175 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4176 mmac_info->naddrfree--; 4177 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4178 4179 maddr->mma_slot = slot; 4180 4181 mutex_exit(nxgep->genlock); 4182 return (0); 4183 } 4184 4185 /* 4186 * This function reserves an unused slot and programs the slot and the HW 4187 * with a factory mac address. 4188 */ 4189 static int 4190 nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr) 4191 { 4192 p_nxge_t nxgep = arg; 4193 mac_addr_slot_t slot; 4194 nxge_mmac_t *mmac_info; 4195 int err; 4196 nxge_status_t status; 4197 4198 mutex_enter(nxgep->genlock); 4199 4200 /* 4201 * Make sure that nxge is initialized, if _start() has 4202 * not been called. 4203 */ 4204 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4205 status = nxge_init(nxgep); 4206 if (status != NXGE_OK) { 4207 mutex_exit(nxgep->genlock); 4208 return (ENXIO); 4209 } 4210 } 4211 4212 mmac_info = &nxgep->nxge_mmac_info; 4213 if (mmac_info->naddrfree == 0) { 4214 mutex_exit(nxgep->genlock); 4215 return (ENOSPC); 4216 } 4217 4218 slot = maddr->mma_slot; 4219 if (slot == -1) { /* -1: Take the first available slot */ 4220 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 4221 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4222 break; 4223 } 4224 if (slot > mmac_info->num_factory_mmac) { 4225 mutex_exit(nxgep->genlock); 4226 return (ENOSPC); 4227 } 4228 } 4229 if (slot < 1 || slot > mmac_info->num_factory_mmac) { 4230 /* 4231 * Do not support factory MAC at a slot greater than 4232 * num_factory_mmac even when there are available factory 4233 * MAC addresses because the alternate MACs are bundled with 4234 * slot[1] through slot[num_factory_mmac] 4235 */ 4236 mutex_exit(nxgep->genlock); 4237 return (EINVAL); 4238 } 4239 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4240 mutex_exit(nxgep->genlock); 4241 return (EBUSY); 4242 } 4243 /* Verify the address to be reserved */ 4244 if (!mac_unicst_verify(nxgep->mach, 4245 mmac_info->factory_mac_pool[slot], ETHERADDRL)) { 4246 mutex_exit(nxgep->genlock); 4247 return (EINVAL); 4248 } 4249 if (err = nxge_altmac_set(nxgep, 4250 mmac_info->factory_mac_pool[slot], slot)) { 4251 mutex_exit(nxgep->genlock); 4252 return (err); 4253 } 4254 bcopy(mmac_info->factory_mac_pool[slot], maddr->mma_addr, ETHERADDRL); 4255 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 4256 mmac_info->naddrfree--; 4257 4258 nxge_mmac_kstat_update(nxgep, slot, B_TRUE); 4259 mutex_exit(nxgep->genlock); 4260 4261 /* Pass info back to the caller */ 4262 maddr->mma_slot = slot; 4263 maddr->mma_addrlen = ETHERADDRL; 4264 maddr->mma_flags = MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 4265 4266 return (0); 4267 } 4268 4269 /* 4270 * Remove the specified mac address and update the HW not to filter 4271 * the mac address anymore. 4272 */ 4273 int 4274 nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot) 4275 { 4276 p_nxge_t nxgep = arg; 4277 nxge_mmac_t *mmac_info; 4278 uint8_t addrn; 4279 uint8_t portn; 4280 int err = 0; 4281 nxge_status_t status; 4282 4283 mutex_enter(nxgep->genlock); 4284 4285 /* 4286 * Make sure that nxge is initialized, if _start() has 4287 * not been called. 4288 */ 4289 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4290 status = nxge_init(nxgep); 4291 if (status != NXGE_OK) { 4292 mutex_exit(nxgep->genlock); 4293 return (ENXIO); 4294 } 4295 } 4296 4297 mmac_info = &nxgep->nxge_mmac_info; 4298 if (slot < 1 || slot > mmac_info->num_mmac) { 4299 mutex_exit(nxgep->genlock); 4300 return (EINVAL); 4301 } 4302 4303 portn = nxgep->mac.portnum; 4304 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4305 addrn = (uint8_t)slot - 1; 4306 else 4307 addrn = (uint8_t)slot; 4308 4309 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4310 if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 4311 == NPI_SUCCESS) { 4312 mmac_info->naddrfree++; 4313 mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 4314 /* 4315 * Regardless if the MAC we just stopped filtering 4316 * is a user addr or a facory addr, we must set 4317 * the MMAC_VENDOR_ADDR flag if this slot has an 4318 * associated factory MAC to indicate that a factory 4319 * MAC is available. 4320 */ 4321 if (slot <= mmac_info->num_factory_mmac) { 4322 mmac_info->mac_pool[slot].flags 4323 |= MMAC_VENDOR_ADDR; 4324 } 4325 /* 4326 * Clear mac_pool[slot].addr so that kstat shows 0 4327 * alternate MAC address if the slot is not used. 4328 * (But nxge_m_mmac_get returns the factory MAC even 4329 * when the slot is not used!) 4330 */ 4331 bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 4332 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4333 } else { 4334 err = EIO; 4335 } 4336 } else { 4337 err = EINVAL; 4338 } 4339 4340 mutex_exit(nxgep->genlock); 4341 return (err); 4342 } 4343 4344 /* 4345 * Modify a mac address added by nxge_m_mmac_add or nxge_m_mmac_reserve(). 4346 */ 4347 static int 4348 nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr) 4349 { 4350 p_nxge_t nxgep = arg; 4351 mac_addr_slot_t slot; 4352 nxge_mmac_t *mmac_info; 4353 int err = 0; 4354 nxge_status_t status; 4355 4356 if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 4357 maddr->mma_addrlen)) 4358 return (EINVAL); 4359 4360 slot = maddr->mma_slot; 4361 4362 mutex_enter(nxgep->genlock); 4363 4364 /* 4365 * Make sure that nxge is initialized, if _start() has 4366 * not been called. 4367 */ 4368 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4369 status = nxge_init(nxgep); 4370 if (status != NXGE_OK) { 4371 mutex_exit(nxgep->genlock); 4372 return (ENXIO); 4373 } 4374 } 4375 4376 mmac_info = &nxgep->nxge_mmac_info; 4377 if (slot < 1 || slot > mmac_info->num_mmac) { 4378 mutex_exit(nxgep->genlock); 4379 return (EINVAL); 4380 } 4381 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4382 if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) 4383 != 0) { 4384 bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, 4385 ETHERADDRL); 4386 /* 4387 * Assume that the MAC passed down from the caller 4388 * is not a factory MAC address (The user should 4389 * call mmac_remove followed by mmac_reserve if 4390 * he wants to use the factory MAC for this slot). 4391 */ 4392 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4393 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4394 } 4395 } else { 4396 err = EINVAL; 4397 } 4398 mutex_exit(nxgep->genlock); 4399 return (err); 4400 } 4401 4402 /* 4403 * nxge_m_mmac_get() - Get the MAC address and other information 4404 * related to the slot. mma_flags should be set to 0 in the call. 4405 * Note: although kstat shows MAC address as zero when a slot is 4406 * not used, Crossbow expects nxge_m_mmac_get to copy factory MAC 4407 * to the caller as long as the slot is not using a user MAC address. 4408 * The following table shows the rules, 4409 * 4410 * USED VENDOR mma_addr 4411 * ------------------------------------------------------------ 4412 * (1) Slot uses a user MAC: yes no user MAC 4413 * (2) Slot uses a factory MAC: yes yes factory MAC 4414 * (3) Slot is not used but is 4415 * factory MAC capable: no yes factory MAC 4416 * (4) Slot is not used and is 4417 * not factory MAC capable: no no 0 4418 * ------------------------------------------------------------ 4419 */ 4420 static int 4421 nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr) 4422 { 4423 nxge_t *nxgep = arg; 4424 mac_addr_slot_t slot; 4425 nxge_mmac_t *mmac_info; 4426 nxge_status_t status; 4427 4428 slot = maddr->mma_slot; 4429 4430 mutex_enter(nxgep->genlock); 4431 4432 /* 4433 * Make sure that nxge is initialized, if _start() has 4434 * not been called. 4435 */ 4436 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4437 status = nxge_init(nxgep); 4438 if (status != NXGE_OK) { 4439 mutex_exit(nxgep->genlock); 4440 return (ENXIO); 4441 } 4442 } 4443 4444 mmac_info = &nxgep->nxge_mmac_info; 4445 4446 if (slot < 1 || slot > mmac_info->num_mmac) { 4447 mutex_exit(nxgep->genlock); 4448 return (EINVAL); 4449 } 4450 maddr->mma_flags = 0; 4451 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) 4452 maddr->mma_flags |= MMAC_SLOT_USED; 4453 4454 if (mmac_info->mac_pool[slot].flags & MMAC_VENDOR_ADDR) { 4455 maddr->mma_flags |= MMAC_VENDOR_ADDR; 4456 bcopy(mmac_info->factory_mac_pool[slot], 4457 maddr->mma_addr, ETHERADDRL); 4458 maddr->mma_addrlen = ETHERADDRL; 4459 } else { 4460 if (maddr->mma_flags & MMAC_SLOT_USED) { 4461 bcopy(mmac_info->mac_pool[slot].addr, 4462 maddr->mma_addr, ETHERADDRL); 4463 maddr->mma_addrlen = ETHERADDRL; 4464 } else { 4465 bzero(maddr->mma_addr, ETHERADDRL); 4466 maddr->mma_addrlen = 0; 4467 } 4468 } 4469 mutex_exit(nxgep->genlock); 4470 return (0); 4471 } 4472 4473 static boolean_t 4474 nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 4475 { 4476 nxge_t *nxgep = arg; 4477 uint32_t *txflags = cap_data; 4478 multiaddress_capab_t *mmacp = cap_data; 4479 4480 switch (cap) { 4481 case MAC_CAPAB_HCKSUM: 4482 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4483 "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4484 if (nxge_cksum_offload <= 1) { 4485 *txflags = HCKSUM_INET_PARTIAL; 4486 } 4487 break; 4488 4489 case MAC_CAPAB_POLL: 4490 /* 4491 * There's nothing for us to fill in, simply returning 4492 * B_TRUE stating that we support polling is sufficient. 4493 */ 4494 break; 4495 4496 case MAC_CAPAB_MULTIADDRESS: 4497 mmacp = (multiaddress_capab_t *)cap_data; 4498 mutex_enter(nxgep->genlock); 4499 4500 mmacp->maddr_naddr = nxgep->nxge_mmac_info.num_mmac; 4501 mmacp->maddr_naddrfree = nxgep->nxge_mmac_info.naddrfree; 4502 mmacp->maddr_flag = 0; /* 0 is required by PSARC2006/265 */ 4503 /* 4504 * maddr_handle is driver's private data, passed back to 4505 * entry point functions as arg. 4506 */ 4507 mmacp->maddr_handle = nxgep; 4508 mmacp->maddr_add = nxge_m_mmac_add; 4509 mmacp->maddr_remove = nxge_m_mmac_remove; 4510 mmacp->maddr_modify = nxge_m_mmac_modify; 4511 mmacp->maddr_get = nxge_m_mmac_get; 4512 mmacp->maddr_reserve = nxge_m_mmac_reserve; 4513 4514 mutex_exit(nxgep->genlock); 4515 break; 4516 4517 case MAC_CAPAB_LSO: { 4518 mac_capab_lso_t *cap_lso = cap_data; 4519 4520 if (nxgep->soft_lso_enable) { 4521 if (nxge_cksum_offload <= 1) { 4522 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4523 if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4524 nxge_lso_max = NXGE_LSO_MAXLEN; 4525 } 4526 cap_lso->lso_basic_tcp_ipv4.lso_max = 4527 nxge_lso_max; 4528 } 4529 break; 4530 } else { 4531 return (B_FALSE); 4532 } 4533 } 4534 4535 #if defined(sun4v) 4536 case MAC_CAPAB_RINGS: { 4537 mac_capab_rings_t *mrings = (mac_capab_rings_t *)cap_data; 4538 4539 /* 4540 * Only the service domain driver responds to 4541 * this capability request. 4542 */ 4543 if (isLDOMservice(nxgep)) { 4544 mrings->mr_handle = (void *)nxgep; 4545 4546 /* 4547 * No dynamic allocation of groups and 4548 * rings at this time. Shares dictate the 4549 * configuration. 4550 */ 4551 mrings->mr_gadd_ring = NULL; 4552 mrings->mr_grem_ring = NULL; 4553 mrings->mr_rget = NULL; 4554 mrings->mr_gget = nxge_hio_group_get; 4555 4556 if (mrings->mr_type == MAC_RING_TYPE_RX) { 4557 mrings->mr_rnum = 8; /* XXX */ 4558 mrings->mr_gnum = 6; /* XXX */ 4559 } else { 4560 mrings->mr_rnum = 8; /* XXX */ 4561 mrings->mr_gnum = 0; /* XXX */ 4562 } 4563 } else 4564 return (B_FALSE); 4565 break; 4566 } 4567 4568 case MAC_CAPAB_SHARES: { 4569 mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4570 4571 /* 4572 * Only the service domain driver responds to 4573 * this capability request. 4574 */ 4575 if (isLDOMservice(nxgep)) { 4576 mshares->ms_snum = 3; 4577 mshares->ms_handle = (void *)nxgep; 4578 mshares->ms_salloc = nxge_hio_share_alloc; 4579 mshares->ms_sfree = nxge_hio_share_free; 4580 mshares->ms_sadd = NULL; 4581 mshares->ms_sremove = NULL; 4582 mshares->ms_squery = nxge_hio_share_query; 4583 } else 4584 return (B_FALSE); 4585 break; 4586 } 4587 #endif 4588 default: 4589 return (B_FALSE); 4590 } 4591 return (B_TRUE); 4592 } 4593 4594 static boolean_t 4595 nxge_param_locked(mac_prop_id_t pr_num) 4596 { 4597 /* 4598 * All adv_* parameters are locked (read-only) while 4599 * the device is in any sort of loopback mode ... 4600 */ 4601 switch (pr_num) { 4602 case MAC_PROP_ADV_1000FDX_CAP: 4603 case MAC_PROP_EN_1000FDX_CAP: 4604 case MAC_PROP_ADV_1000HDX_CAP: 4605 case MAC_PROP_EN_1000HDX_CAP: 4606 case MAC_PROP_ADV_100FDX_CAP: 4607 case MAC_PROP_EN_100FDX_CAP: 4608 case MAC_PROP_ADV_100HDX_CAP: 4609 case MAC_PROP_EN_100HDX_CAP: 4610 case MAC_PROP_ADV_10FDX_CAP: 4611 case MAC_PROP_EN_10FDX_CAP: 4612 case MAC_PROP_ADV_10HDX_CAP: 4613 case MAC_PROP_EN_10HDX_CAP: 4614 case MAC_PROP_AUTONEG: 4615 case MAC_PROP_FLOWCTRL: 4616 return (B_TRUE); 4617 } 4618 return (B_FALSE); 4619 } 4620 4621 /* 4622 * callback functions for set/get of properties 4623 */ 4624 static int 4625 nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4626 uint_t pr_valsize, const void *pr_val) 4627 { 4628 nxge_t *nxgep = barg; 4629 p_nxge_param_t param_arr; 4630 p_nxge_stats_t statsp; 4631 int err = 0; 4632 uint8_t val; 4633 uint32_t cur_mtu, new_mtu, old_framesize; 4634 link_flowctrl_t fl; 4635 4636 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 4637 param_arr = nxgep->param_arr; 4638 statsp = nxgep->statsp; 4639 mutex_enter(nxgep->genlock); 4640 if (statsp->port_stats.lb_mode != nxge_lb_normal && 4641 nxge_param_locked(pr_num)) { 4642 /* 4643 * All adv_* parameters are locked (read-only) 4644 * while the device is in any sort of loopback mode. 4645 */ 4646 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4647 "==> nxge_m_setprop: loopback mode: read only")); 4648 mutex_exit(nxgep->genlock); 4649 return (EBUSY); 4650 } 4651 4652 val = *(uint8_t *)pr_val; 4653 switch (pr_num) { 4654 case MAC_PROP_EN_1000FDX_CAP: 4655 nxgep->param_en_1000fdx = val; 4656 param_arr[param_anar_1000fdx].value = val; 4657 4658 goto reprogram; 4659 4660 case MAC_PROP_EN_100FDX_CAP: 4661 nxgep->param_en_100fdx = val; 4662 param_arr[param_anar_100fdx].value = val; 4663 4664 goto reprogram; 4665 4666 case MAC_PROP_EN_10FDX_CAP: 4667 nxgep->param_en_10fdx = val; 4668 param_arr[param_anar_10fdx].value = val; 4669 4670 goto reprogram; 4671 4672 case MAC_PROP_EN_1000HDX_CAP: 4673 case MAC_PROP_EN_100HDX_CAP: 4674 case MAC_PROP_EN_10HDX_CAP: 4675 case MAC_PROP_ADV_1000FDX_CAP: 4676 case MAC_PROP_ADV_1000HDX_CAP: 4677 case MAC_PROP_ADV_100FDX_CAP: 4678 case MAC_PROP_ADV_100HDX_CAP: 4679 case MAC_PROP_ADV_10FDX_CAP: 4680 case MAC_PROP_ADV_10HDX_CAP: 4681 case MAC_PROP_STATUS: 4682 case MAC_PROP_SPEED: 4683 case MAC_PROP_DUPLEX: 4684 err = EINVAL; /* cannot set read-only properties */ 4685 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4686 "==> nxge_m_setprop: read only property %d", 4687 pr_num)); 4688 break; 4689 4690 case MAC_PROP_AUTONEG: 4691 param_arr[param_autoneg].value = val; 4692 4693 goto reprogram; 4694 4695 case MAC_PROP_MTU: 4696 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 4697 err = EBUSY; 4698 break; 4699 } 4700 4701 cur_mtu = nxgep->mac.default_mtu; 4702 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 4703 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4704 "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 4705 new_mtu, nxgep->mac.is_jumbo)); 4706 4707 if (new_mtu == cur_mtu) { 4708 err = 0; 4709 break; 4710 } 4711 if (new_mtu < NXGE_DEFAULT_MTU || 4712 new_mtu > NXGE_MAXIMUM_MTU) { 4713 err = EINVAL; 4714 break; 4715 } 4716 4717 if ((new_mtu > NXGE_DEFAULT_MTU) && 4718 !nxgep->mac.is_jumbo) { 4719 err = EINVAL; 4720 break; 4721 } 4722 4723 old_framesize = (uint32_t)nxgep->mac.maxframesize; 4724 nxgep->mac.maxframesize = (uint16_t) 4725 (new_mtu + NXGE_EHEADER_VLAN_CRC); 4726 if (nxge_mac_set_framesize(nxgep)) { 4727 nxgep->mac.maxframesize = 4728 (uint16_t)old_framesize; 4729 err = EINVAL; 4730 break; 4731 } 4732 4733 err = mac_maxsdu_update(nxgep->mach, new_mtu); 4734 if (err) { 4735 nxgep->mac.maxframesize = 4736 (uint16_t)old_framesize; 4737 err = EINVAL; 4738 break; 4739 } 4740 4741 nxgep->mac.default_mtu = new_mtu; 4742 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4743 "==> nxge_m_setprop: set MTU: %d maxframe %d", 4744 new_mtu, nxgep->mac.maxframesize)); 4745 break; 4746 4747 case MAC_PROP_FLOWCTRL: 4748 bcopy(pr_val, &fl, sizeof (fl)); 4749 switch (fl) { 4750 default: 4751 err = EINVAL; 4752 break; 4753 4754 case LINK_FLOWCTRL_NONE: 4755 param_arr[param_anar_pause].value = 0; 4756 break; 4757 4758 case LINK_FLOWCTRL_RX: 4759 param_arr[param_anar_pause].value = 1; 4760 break; 4761 4762 case LINK_FLOWCTRL_TX: 4763 case LINK_FLOWCTRL_BI: 4764 err = EINVAL; 4765 break; 4766 } 4767 4768 reprogram: 4769 if (err == 0) { 4770 if (!nxge_param_link_update(nxgep)) { 4771 err = EINVAL; 4772 } 4773 } 4774 break; 4775 case MAC_PROP_PRIVATE: 4776 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4777 "==> nxge_m_setprop: private property")); 4778 err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 4779 pr_val); 4780 break; 4781 4782 default: 4783 err = ENOTSUP; 4784 break; 4785 } 4786 4787 mutex_exit(nxgep->genlock); 4788 4789 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4790 "<== nxge_m_setprop (return %d)", err)); 4791 return (err); 4792 } 4793 4794 static int 4795 nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4796 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 4797 { 4798 nxge_t *nxgep = barg; 4799 p_nxge_param_t param_arr = nxgep->param_arr; 4800 p_nxge_stats_t statsp = nxgep->statsp; 4801 int err = 0; 4802 link_flowctrl_t fl; 4803 uint64_t tmp = 0; 4804 link_state_t ls; 4805 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 4806 4807 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4808 "==> nxge_m_getprop: pr_num %d", pr_num)); 4809 4810 if (pr_valsize == 0) 4811 return (EINVAL); 4812 4813 if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 4814 err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 4815 return (err); 4816 } 4817 4818 bzero(pr_val, pr_valsize); 4819 switch (pr_num) { 4820 case MAC_PROP_DUPLEX: 4821 *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 4822 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4823 "==> nxge_m_getprop: duplex mode %d", 4824 *(uint8_t *)pr_val)); 4825 break; 4826 4827 case MAC_PROP_SPEED: 4828 if (pr_valsize < sizeof (uint64_t)) 4829 return (EINVAL); 4830 tmp = statsp->mac_stats.link_speed * 1000000ull; 4831 bcopy(&tmp, pr_val, sizeof (tmp)); 4832 break; 4833 4834 case MAC_PROP_STATUS: 4835 if (pr_valsize < sizeof (link_state_t)) 4836 return (EINVAL); 4837 if (!statsp->mac_stats.link_up) 4838 ls = LINK_STATE_DOWN; 4839 else 4840 ls = LINK_STATE_UP; 4841 bcopy(&ls, pr_val, sizeof (ls)); 4842 break; 4843 4844 case MAC_PROP_AUTONEG: 4845 *(uint8_t *)pr_val = 4846 param_arr[param_autoneg].value; 4847 break; 4848 4849 case MAC_PROP_FLOWCTRL: 4850 if (pr_valsize < sizeof (link_flowctrl_t)) 4851 return (EINVAL); 4852 4853 fl = LINK_FLOWCTRL_NONE; 4854 if (param_arr[param_anar_pause].value) { 4855 fl = LINK_FLOWCTRL_RX; 4856 } 4857 bcopy(&fl, pr_val, sizeof (fl)); 4858 break; 4859 4860 case MAC_PROP_ADV_1000FDX_CAP: 4861 *(uint8_t *)pr_val = 4862 param_arr[param_anar_1000fdx].value; 4863 break; 4864 4865 case MAC_PROP_EN_1000FDX_CAP: 4866 *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 4867 break; 4868 4869 case MAC_PROP_ADV_100FDX_CAP: 4870 *(uint8_t *)pr_val = 4871 param_arr[param_anar_100fdx].value; 4872 break; 4873 4874 case MAC_PROP_EN_100FDX_CAP: 4875 *(uint8_t *)pr_val = nxgep->param_en_100fdx; 4876 break; 4877 4878 case MAC_PROP_ADV_10FDX_CAP: 4879 *(uint8_t *)pr_val = 4880 param_arr[param_anar_10fdx].value; 4881 break; 4882 4883 case MAC_PROP_EN_10FDX_CAP: 4884 *(uint8_t *)pr_val = nxgep->param_en_10fdx; 4885 break; 4886 4887 case MAC_PROP_EN_1000HDX_CAP: 4888 case MAC_PROP_EN_100HDX_CAP: 4889 case MAC_PROP_EN_10HDX_CAP: 4890 case MAC_PROP_ADV_1000HDX_CAP: 4891 case MAC_PROP_ADV_100HDX_CAP: 4892 case MAC_PROP_ADV_10HDX_CAP: 4893 err = ENOTSUP; 4894 break; 4895 4896 case MAC_PROP_PRIVATE: 4897 err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 4898 pr_valsize, pr_val); 4899 break; 4900 default: 4901 err = EINVAL; 4902 break; 4903 } 4904 4905 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 4906 4907 return (err); 4908 } 4909 4910 /* ARGSUSED */ 4911 static int 4912 nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 4913 const void *pr_val) 4914 { 4915 p_nxge_param_t param_arr = nxgep->param_arr; 4916 int err = 0; 4917 long result; 4918 4919 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4920 "==> nxge_set_priv_prop: name %s", pr_name)); 4921 4922 if (strcmp(pr_name, "_accept_jumbo") == 0) { 4923 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4924 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4925 "<== nxge_set_priv_prop: name %s " 4926 "pr_val %s result %d " 4927 "param %d is_jumbo %d", 4928 pr_name, pr_val, result, 4929 param_arr[param_accept_jumbo].value, 4930 nxgep->mac.is_jumbo)); 4931 4932 if (result > 1 || result < 0) { 4933 err = EINVAL; 4934 } else { 4935 if (nxgep->mac.is_jumbo == 4936 (uint32_t)result) { 4937 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4938 "no change (%d %d)", 4939 nxgep->mac.is_jumbo, 4940 result)); 4941 return (0); 4942 } 4943 } 4944 4945 param_arr[param_accept_jumbo].value = result; 4946 nxgep->mac.is_jumbo = B_FALSE; 4947 if (result) { 4948 nxgep->mac.is_jumbo = B_TRUE; 4949 } 4950 4951 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4952 "<== nxge_set_priv_prop: name %s (value %d) is_jumbo %d", 4953 pr_name, result, nxgep->mac.is_jumbo)); 4954 4955 return (err); 4956 } 4957 4958 /* Blanking */ 4959 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 4960 err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 4961 (char *)pr_val, 4962 (caddr_t)¶m_arr[param_rxdma_intr_time]); 4963 if (err) { 4964 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4965 "<== nxge_set_priv_prop: " 4966 "unable to set (%s)", pr_name)); 4967 err = EINVAL; 4968 } else { 4969 err = 0; 4970 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4971 "<== nxge_set_priv_prop: " 4972 "set (%s)", pr_name)); 4973 } 4974 4975 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4976 "<== nxge_set_priv_prop: name %s (value %d)", 4977 pr_name, result)); 4978 4979 return (err); 4980 } 4981 4982 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 4983 err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 4984 (char *)pr_val, 4985 (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 4986 if (err) { 4987 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4988 "<== nxge_set_priv_prop: " 4989 "unable to set (%s)", pr_name)); 4990 err = EINVAL; 4991 } else { 4992 err = 0; 4993 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4994 "<== nxge_set_priv_prop: " 4995 "set (%s)", pr_name)); 4996 } 4997 4998 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4999 "<== nxge_set_priv_prop: name %s (value %d)", 5000 pr_name, result)); 5001 5002 return (err); 5003 } 5004 5005 /* Classification */ 5006 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 5007 if (pr_val == NULL) { 5008 err = EINVAL; 5009 return (err); 5010 } 5011 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5012 5013 err = nxge_param_set_ip_opt(nxgep, NULL, 5014 NULL, (char *)pr_val, 5015 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 5016 5017 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5018 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5019 pr_name, result)); 5020 5021 return (err); 5022 } 5023 5024 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5025 if (pr_val == NULL) { 5026 err = EINVAL; 5027 return (err); 5028 } 5029 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5030 5031 err = nxge_param_set_ip_opt(nxgep, NULL, 5032 NULL, (char *)pr_val, 5033 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5034 5035 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5036 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5037 pr_name, result)); 5038 5039 return (err); 5040 } 5041 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5042 if (pr_val == NULL) { 5043 err = EINVAL; 5044 return (err); 5045 } 5046 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5047 5048 err = nxge_param_set_ip_opt(nxgep, NULL, 5049 NULL, (char *)pr_val, 5050 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5051 5052 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5053 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5054 pr_name, result)); 5055 5056 return (err); 5057 } 5058 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5059 if (pr_val == NULL) { 5060 err = EINVAL; 5061 return (err); 5062 } 5063 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5064 5065 err = nxge_param_set_ip_opt(nxgep, NULL, 5066 NULL, (char *)pr_val, 5067 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5068 5069 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5070 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5071 pr_name, result)); 5072 5073 return (err); 5074 } 5075 5076 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5077 if (pr_val == NULL) { 5078 err = EINVAL; 5079 return (err); 5080 } 5081 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5082 5083 err = nxge_param_set_ip_opt(nxgep, NULL, 5084 NULL, (char *)pr_val, 5085 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5086 5087 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5088 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5089 pr_name, result)); 5090 5091 return (err); 5092 } 5093 5094 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5095 if (pr_val == NULL) { 5096 err = EINVAL; 5097 return (err); 5098 } 5099 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5100 5101 err = nxge_param_set_ip_opt(nxgep, NULL, 5102 NULL, (char *)pr_val, 5103 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5104 5105 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5106 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5107 pr_name, result)); 5108 5109 return (err); 5110 } 5111 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5112 if (pr_val == NULL) { 5113 err = EINVAL; 5114 return (err); 5115 } 5116 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5117 5118 err = nxge_param_set_ip_opt(nxgep, NULL, 5119 NULL, (char *)pr_val, 5120 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5121 5122 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5123 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5124 pr_name, result)); 5125 5126 return (err); 5127 } 5128 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5129 if (pr_val == NULL) { 5130 err = EINVAL; 5131 return (err); 5132 } 5133 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5134 5135 err = nxge_param_set_ip_opt(nxgep, NULL, 5136 NULL, (char *)pr_val, 5137 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5138 5139 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5140 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5141 pr_name, result)); 5142 5143 return (err); 5144 } 5145 5146 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5147 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 5148 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5149 "==> nxge_set_priv_prop: name %s (busy)", pr_name)); 5150 err = EBUSY; 5151 return (err); 5152 } 5153 if (pr_val == NULL) { 5154 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5155 "==> nxge_set_priv_prop: name %s (null)", pr_name)); 5156 err = EINVAL; 5157 return (err); 5158 } 5159 5160 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5161 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5162 "<== nxge_set_priv_prop: name %s " 5163 "(lso %d pr_val %s value %d)", 5164 pr_name, nxgep->soft_lso_enable, pr_val, result)); 5165 5166 if (result > 1 || result < 0) { 5167 err = EINVAL; 5168 } else { 5169 if (nxgep->soft_lso_enable == (uint32_t)result) { 5170 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5171 "no change (%d %d)", 5172 nxgep->soft_lso_enable, result)); 5173 return (0); 5174 } 5175 } 5176 5177 nxgep->soft_lso_enable = (int)result; 5178 5179 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5180 "<== nxge_set_priv_prop: name %s (value %d)", 5181 pr_name, result)); 5182 5183 return (err); 5184 } 5185 /* 5186 * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 5187 * following code to be executed. 5188 */ 5189 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5190 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 5191 (caddr_t)¶m_arr[param_anar_10gfdx]); 5192 return (err); 5193 } 5194 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5195 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 5196 (caddr_t)¶m_arr[param_anar_pause]); 5197 return (err); 5198 } 5199 5200 return (EINVAL); 5201 } 5202 5203 static int 5204 nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 5205 uint_t pr_valsize, void *pr_val) 5206 { 5207 p_nxge_param_t param_arr = nxgep->param_arr; 5208 char valstr[MAXNAMELEN]; 5209 int err = EINVAL; 5210 uint_t strsize; 5211 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 5212 5213 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5214 "==> nxge_get_priv_prop: property %s", pr_name)); 5215 5216 /* function number */ 5217 if (strcmp(pr_name, "_function_number") == 0) { 5218 if (is_default) 5219 return (ENOTSUP); 5220 (void) snprintf(valstr, sizeof (valstr), "%d", 5221 nxgep->function_num); 5222 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5223 "==> nxge_get_priv_prop: name %s " 5224 "(value %d valstr %s)", 5225 pr_name, nxgep->function_num, valstr)); 5226 5227 err = 0; 5228 goto done; 5229 } 5230 5231 /* Neptune firmware version */ 5232 if (strcmp(pr_name, "_fw_version") == 0) { 5233 if (is_default) 5234 return (ENOTSUP); 5235 (void) snprintf(valstr, sizeof (valstr), "%s", 5236 nxgep->vpd_info.ver); 5237 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5238 "==> nxge_get_priv_prop: name %s " 5239 "(value %d valstr %s)", 5240 pr_name, nxgep->vpd_info.ver, valstr)); 5241 5242 err = 0; 5243 goto done; 5244 } 5245 5246 /* port PHY mode */ 5247 if (strcmp(pr_name, "_port_mode") == 0) { 5248 if (is_default) 5249 return (ENOTSUP); 5250 switch (nxgep->mac.portmode) { 5251 case PORT_1G_COPPER: 5252 (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 5253 nxgep->hot_swappable_phy ? 5254 "[Hot Swappable]" : ""); 5255 break; 5256 case PORT_1G_FIBER: 5257 (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 5258 nxgep->hot_swappable_phy ? 5259 "[hot swappable]" : ""); 5260 break; 5261 case PORT_10G_COPPER: 5262 (void) snprintf(valstr, sizeof (valstr), 5263 "10G copper %s", 5264 nxgep->hot_swappable_phy ? 5265 "[hot swappable]" : ""); 5266 break; 5267 case PORT_10G_FIBER: 5268 (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 5269 nxgep->hot_swappable_phy ? 5270 "[hot swappable]" : ""); 5271 break; 5272 case PORT_10G_SERDES: 5273 (void) snprintf(valstr, sizeof (valstr), 5274 "10G serdes %s", nxgep->hot_swappable_phy ? 5275 "[hot swappable]" : ""); 5276 break; 5277 case PORT_1G_SERDES: 5278 (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 5279 nxgep->hot_swappable_phy ? 5280 "[hot swappable]" : ""); 5281 break; 5282 case PORT_1G_TN1010: 5283 (void) snprintf(valstr, sizeof (valstr), 5284 "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 5285 "[hot swappable]" : ""); 5286 break; 5287 case PORT_10G_TN1010: 5288 (void) snprintf(valstr, sizeof (valstr), 5289 "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 5290 "[hot swappable]" : ""); 5291 break; 5292 case PORT_1G_RGMII_FIBER: 5293 (void) snprintf(valstr, sizeof (valstr), 5294 "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 5295 "[hot swappable]" : ""); 5296 break; 5297 case PORT_HSP_MODE: 5298 (void) snprintf(valstr, sizeof (valstr), 5299 "phy not present[hot swappable]"); 5300 break; 5301 default: 5302 (void) snprintf(valstr, sizeof (valstr), "unknown %s", 5303 nxgep->hot_swappable_phy ? 5304 "[hot swappable]" : ""); 5305 break; 5306 } 5307 5308 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5309 "==> nxge_get_priv_prop: name %s (value %s)", 5310 pr_name, valstr)); 5311 5312 err = 0; 5313 goto done; 5314 } 5315 5316 /* Hot swappable PHY */ 5317 if (strcmp(pr_name, "_hot_swap_phy") == 0) { 5318 if (is_default) 5319 return (ENOTSUP); 5320 (void) snprintf(valstr, sizeof (valstr), "%s", 5321 nxgep->hot_swappable_phy ? 5322 "yes" : "no"); 5323 5324 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5325 "==> nxge_get_priv_prop: name %s " 5326 "(value %d valstr %s)", 5327 pr_name, nxgep->hot_swappable_phy, valstr)); 5328 5329 err = 0; 5330 goto done; 5331 } 5332 5333 5334 /* accept jumbo */ 5335 if (strcmp(pr_name, "_accept_jumbo") == 0) { 5336 if (is_default) 5337 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5338 else 5339 (void) snprintf(valstr, sizeof (valstr), 5340 "%d", nxgep->mac.is_jumbo); 5341 err = 0; 5342 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5343 "==> nxge_get_priv_prop: name %s (value %d (%d, %d))", 5344 pr_name, 5345 (uint32_t)param_arr[param_accept_jumbo].value, 5346 nxgep->mac.is_jumbo, 5347 nxge_jumbo_enable)); 5348 5349 goto done; 5350 } 5351 5352 /* Receive Interrupt Blanking Parameters */ 5353 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 5354 err = 0; 5355 if (is_default) { 5356 (void) snprintf(valstr, sizeof (valstr), 5357 "%d", RXDMA_RCR_TO_DEFAULT); 5358 goto done; 5359 } 5360 5361 (void) snprintf(valstr, sizeof (valstr), "%d", 5362 nxgep->intr_timeout); 5363 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5364 "==> nxge_get_priv_prop: name %s (value %d)", 5365 pr_name, 5366 (uint32_t)nxgep->intr_timeout)); 5367 goto done; 5368 } 5369 5370 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 5371 err = 0; 5372 if (is_default) { 5373 (void) snprintf(valstr, sizeof (valstr), 5374 "%d", RXDMA_RCR_PTHRES_DEFAULT); 5375 goto done; 5376 } 5377 (void) snprintf(valstr, sizeof (valstr), "%d", 5378 nxgep->intr_threshold); 5379 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5380 "==> nxge_get_priv_prop: name %s (value %d)", 5381 pr_name, (uint32_t)nxgep->intr_threshold)); 5382 5383 goto done; 5384 } 5385 5386 /* Classification and Load Distribution Configuration */ 5387 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 5388 if (is_default) { 5389 (void) snprintf(valstr, sizeof (valstr), "%x", 5390 NXGE_CLASS_FLOW_GEN_SERVER); 5391 err = 0; 5392 goto done; 5393 } 5394 err = nxge_dld_get_ip_opt(nxgep, 5395 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 5396 5397 (void) snprintf(valstr, sizeof (valstr), "%x", 5398 (int)param_arr[param_class_opt_ipv4_tcp].value); 5399 5400 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5401 "==> nxge_get_priv_prop: %s", valstr)); 5402 goto done; 5403 } 5404 5405 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5406 if (is_default) { 5407 (void) snprintf(valstr, sizeof (valstr), "%x", 5408 NXGE_CLASS_FLOW_GEN_SERVER); 5409 err = 0; 5410 goto done; 5411 } 5412 err = nxge_dld_get_ip_opt(nxgep, 5413 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5414 5415 (void) snprintf(valstr, sizeof (valstr), "%x", 5416 (int)param_arr[param_class_opt_ipv4_udp].value); 5417 5418 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5419 "==> nxge_get_priv_prop: %s", valstr)); 5420 goto done; 5421 } 5422 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5423 if (is_default) { 5424 (void) snprintf(valstr, sizeof (valstr), "%x", 5425 NXGE_CLASS_FLOW_GEN_SERVER); 5426 err = 0; 5427 goto done; 5428 } 5429 err = nxge_dld_get_ip_opt(nxgep, 5430 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5431 5432 (void) snprintf(valstr, sizeof (valstr), "%x", 5433 (int)param_arr[param_class_opt_ipv4_ah].value); 5434 5435 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5436 "==> nxge_get_priv_prop: %s", valstr)); 5437 goto done; 5438 } 5439 5440 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5441 if (is_default) { 5442 (void) snprintf(valstr, sizeof (valstr), "%x", 5443 NXGE_CLASS_FLOW_GEN_SERVER); 5444 err = 0; 5445 goto done; 5446 } 5447 err = nxge_dld_get_ip_opt(nxgep, 5448 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5449 5450 (void) snprintf(valstr, sizeof (valstr), "%x", 5451 (int)param_arr[param_class_opt_ipv4_sctp].value); 5452 5453 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5454 "==> nxge_get_priv_prop: %s", valstr)); 5455 goto done; 5456 } 5457 5458 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5459 if (is_default) { 5460 (void) snprintf(valstr, sizeof (valstr), "%x", 5461 NXGE_CLASS_FLOW_GEN_SERVER); 5462 err = 0; 5463 goto done; 5464 } 5465 err = nxge_dld_get_ip_opt(nxgep, 5466 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5467 5468 (void) snprintf(valstr, sizeof (valstr), "%x", 5469 (int)param_arr[param_class_opt_ipv6_tcp].value); 5470 5471 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5472 "==> nxge_get_priv_prop: %s", valstr)); 5473 goto done; 5474 } 5475 5476 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5477 if (is_default) { 5478 (void) snprintf(valstr, sizeof (valstr), "%x", 5479 NXGE_CLASS_FLOW_GEN_SERVER); 5480 err = 0; 5481 goto done; 5482 } 5483 err = nxge_dld_get_ip_opt(nxgep, 5484 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5485 5486 (void) snprintf(valstr, sizeof (valstr), "%x", 5487 (int)param_arr[param_class_opt_ipv6_udp].value); 5488 5489 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5490 "==> nxge_get_priv_prop: %s", valstr)); 5491 goto done; 5492 } 5493 5494 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5495 if (is_default) { 5496 (void) snprintf(valstr, sizeof (valstr), "%x", 5497 NXGE_CLASS_FLOW_GEN_SERVER); 5498 err = 0; 5499 goto done; 5500 } 5501 err = nxge_dld_get_ip_opt(nxgep, 5502 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5503 5504 (void) snprintf(valstr, sizeof (valstr), "%x", 5505 (int)param_arr[param_class_opt_ipv6_ah].value); 5506 5507 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5508 "==> nxge_get_priv_prop: %s", valstr)); 5509 goto done; 5510 } 5511 5512 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5513 if (is_default) { 5514 (void) snprintf(valstr, sizeof (valstr), "%x", 5515 NXGE_CLASS_FLOW_GEN_SERVER); 5516 err = 0; 5517 goto done; 5518 } 5519 err = nxge_dld_get_ip_opt(nxgep, 5520 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5521 5522 (void) snprintf(valstr, sizeof (valstr), "%x", 5523 (int)param_arr[param_class_opt_ipv6_sctp].value); 5524 5525 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5526 "==> nxge_get_priv_prop: %s", valstr)); 5527 goto done; 5528 } 5529 5530 /* Software LSO */ 5531 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5532 if (is_default) { 5533 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5534 err = 0; 5535 goto done; 5536 } 5537 (void) snprintf(valstr, sizeof (valstr), 5538 "%d", nxgep->soft_lso_enable); 5539 err = 0; 5540 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5541 "==> nxge_get_priv_prop: name %s (value %d)", 5542 pr_name, nxgep->soft_lso_enable)); 5543 5544 goto done; 5545 } 5546 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5547 err = 0; 5548 if (is_default || 5549 nxgep->param_arr[param_anar_10gfdx].value != 0) { 5550 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5551 goto done; 5552 } else { 5553 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5554 goto done; 5555 } 5556 } 5557 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5558 err = 0; 5559 if (is_default || 5560 nxgep->param_arr[param_anar_pause].value != 0) { 5561 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5562 goto done; 5563 } else { 5564 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5565 goto done; 5566 } 5567 } 5568 5569 done: 5570 if (err == 0) { 5571 strsize = (uint_t)strlen(valstr); 5572 if (pr_valsize < strsize) { 5573 err = ENOBUFS; 5574 } else { 5575 (void) strlcpy(pr_val, valstr, pr_valsize); 5576 } 5577 } 5578 5579 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5580 "<== nxge_get_priv_prop: return %d", err)); 5581 return (err); 5582 } 5583 5584 /* 5585 * Module loading and removing entry points. 5586 */ 5587 5588 DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 5589 nodev, NULL, D_MP, NULL, nxge_quiesce); 5590 5591 #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 5592 5593 /* 5594 * Module linkage information for the kernel. 5595 */ 5596 static struct modldrv nxge_modldrv = { 5597 &mod_driverops, 5598 NXGE_DESC_VER, 5599 &nxge_dev_ops 5600 }; 5601 5602 static struct modlinkage modlinkage = { 5603 MODREV_1, (void *) &nxge_modldrv, NULL 5604 }; 5605 5606 int 5607 _init(void) 5608 { 5609 int status; 5610 5611 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 5612 mac_init_ops(&nxge_dev_ops, "nxge"); 5613 status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 5614 if (status != 0) { 5615 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 5616 "failed to init device soft state")); 5617 goto _init_exit; 5618 } 5619 status = mod_install(&modlinkage); 5620 if (status != 0) { 5621 ddi_soft_state_fini(&nxge_list); 5622 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 5623 goto _init_exit; 5624 } 5625 5626 MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 5627 5628 _init_exit: 5629 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status)); 5630 5631 return (status); 5632 } 5633 5634 int 5635 _fini(void) 5636 { 5637 int status; 5638 5639 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 5640 5641 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5642 5643 if (nxge_mblks_pending) 5644 return (EBUSY); 5645 5646 status = mod_remove(&modlinkage); 5647 if (status != DDI_SUCCESS) { 5648 NXGE_DEBUG_MSG((NULL, MOD_CTL, 5649 "Module removal failed 0x%08x", 5650 status)); 5651 goto _fini_exit; 5652 } 5653 5654 mac_fini_ops(&nxge_dev_ops); 5655 5656 ddi_soft_state_fini(&nxge_list); 5657 5658 MUTEX_DESTROY(&nxge_common_lock); 5659 _fini_exit: 5660 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status)); 5661 5662 return (status); 5663 } 5664 5665 int 5666 _info(struct modinfo *modinfop) 5667 { 5668 int status; 5669 5670 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 5671 status = mod_info(&modlinkage, modinfop); 5672 NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 5673 5674 return (status); 5675 } 5676 5677 /*ARGSUSED*/ 5678 static nxge_status_t 5679 nxge_add_intrs(p_nxge_t nxgep) 5680 { 5681 5682 int intr_types; 5683 int type = 0; 5684 int ddi_status = DDI_SUCCESS; 5685 nxge_status_t status = NXGE_OK; 5686 5687 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 5688 5689 nxgep->nxge_intr_type.intr_registered = B_FALSE; 5690 nxgep->nxge_intr_type.intr_enabled = B_FALSE; 5691 nxgep->nxge_intr_type.msi_intx_cnt = 0; 5692 nxgep->nxge_intr_type.intr_added = 0; 5693 nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 5694 nxgep->nxge_intr_type.intr_type = 0; 5695 5696 if (nxgep->niu_type == N2_NIU) { 5697 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5698 } else if (nxge_msi_enable) { 5699 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5700 } 5701 5702 /* Get the supported interrupt types */ 5703 if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 5704 != DDI_SUCCESS) { 5705 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 5706 "ddi_intr_get_supported_types failed: status 0x%08x", 5707 ddi_status)); 5708 return (NXGE_ERROR | NXGE_DDI_FAILED); 5709 } 5710 nxgep->nxge_intr_type.intr_types = intr_types; 5711 5712 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5713 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5714 5715 /* 5716 * Solaris MSIX is not supported yet. use MSI for now. 5717 * nxge_msi_enable (1): 5718 * 1 - MSI 2 - MSI-X others - FIXED 5719 */ 5720 switch (nxge_msi_enable) { 5721 default: 5722 type = DDI_INTR_TYPE_FIXED; 5723 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5724 "use fixed (intx emulation) type %08x", 5725 type)); 5726 break; 5727 5728 case 2: 5729 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5730 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5731 if (intr_types & DDI_INTR_TYPE_MSIX) { 5732 type = DDI_INTR_TYPE_MSIX; 5733 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5734 "ddi_intr_get_supported_types: MSIX 0x%08x", 5735 type)); 5736 } else if (intr_types & DDI_INTR_TYPE_MSI) { 5737 type = DDI_INTR_TYPE_MSI; 5738 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5739 "ddi_intr_get_supported_types: MSI 0x%08x", 5740 type)); 5741 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5742 type = DDI_INTR_TYPE_FIXED; 5743 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5744 "ddi_intr_get_supported_types: MSXED0x%08x", 5745 type)); 5746 } 5747 break; 5748 5749 case 1: 5750 if (intr_types & DDI_INTR_TYPE_MSI) { 5751 type = DDI_INTR_TYPE_MSI; 5752 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5753 "ddi_intr_get_supported_types: MSI 0x%08x", 5754 type)); 5755 } else if (intr_types & DDI_INTR_TYPE_MSIX) { 5756 type = DDI_INTR_TYPE_MSIX; 5757 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5758 "ddi_intr_get_supported_types: MSIX 0x%08x", 5759 type)); 5760 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5761 type = DDI_INTR_TYPE_FIXED; 5762 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5763 "ddi_intr_get_supported_types: MSXED0x%08x", 5764 type)); 5765 } 5766 } 5767 5768 nxgep->nxge_intr_type.intr_type = type; 5769 if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 5770 type == DDI_INTR_TYPE_FIXED) && 5771 nxgep->nxge_intr_type.niu_msi_enable) { 5772 if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 5773 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5774 " nxge_add_intrs: " 5775 " nxge_add_intrs_adv failed: status 0x%08x", 5776 status)); 5777 return (status); 5778 } else { 5779 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5780 "interrupts registered : type %d", type)); 5781 nxgep->nxge_intr_type.intr_registered = B_TRUE; 5782 5783 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 5784 "\nAdded advanced nxge add_intr_adv " 5785 "intr type 0x%x\n", type)); 5786 5787 return (status); 5788 } 5789 } 5790 5791 if (!nxgep->nxge_intr_type.intr_registered) { 5792 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 5793 "failed to register interrupts")); 5794 return (NXGE_ERROR | NXGE_DDI_FAILED); 5795 } 5796 5797 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 5798 return (status); 5799 } 5800 5801 /*ARGSUSED*/ 5802 static nxge_status_t 5803 nxge_add_soft_intrs(p_nxge_t nxgep) 5804 { 5805 5806 int ddi_status = DDI_SUCCESS; 5807 nxge_status_t status = NXGE_OK; 5808 5809 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_soft_intrs")); 5810 5811 nxgep->resched_id = NULL; 5812 nxgep->resched_running = B_FALSE; 5813 ddi_status = ddi_add_softintr(nxgep->dip, DDI_SOFTINT_LOW, 5814 &nxgep->resched_id, 5815 NULL, NULL, nxge_reschedule, (caddr_t)nxgep); 5816 if (ddi_status != DDI_SUCCESS) { 5817 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_soft_intrs: " 5818 "ddi_add_softintrs failed: status 0x%08x", 5819 ddi_status)); 5820 return (NXGE_ERROR | NXGE_DDI_FAILED); 5821 } 5822 5823 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_ddi_add_soft_intrs")); 5824 5825 return (status); 5826 } 5827 5828 static nxge_status_t 5829 nxge_add_intrs_adv(p_nxge_t nxgep) 5830 { 5831 int intr_type; 5832 p_nxge_intr_t intrp; 5833 5834 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 5835 5836 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5837 intr_type = intrp->intr_type; 5838 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 5839 intr_type)); 5840 5841 switch (intr_type) { 5842 case DDI_INTR_TYPE_MSI: /* 0x2 */ 5843 case DDI_INTR_TYPE_MSIX: /* 0x4 */ 5844 return (nxge_add_intrs_adv_type(nxgep, intr_type)); 5845 5846 case DDI_INTR_TYPE_FIXED: /* 0x1 */ 5847 return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 5848 5849 default: 5850 return (NXGE_ERROR); 5851 } 5852 } 5853 5854 5855 /*ARGSUSED*/ 5856 static nxge_status_t 5857 nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 5858 { 5859 dev_info_t *dip = nxgep->dip; 5860 p_nxge_ldg_t ldgp; 5861 p_nxge_intr_t intrp; 5862 uint_t *inthandler; 5863 void *arg1, *arg2; 5864 int behavior; 5865 int nintrs, navail, nrequest; 5866 int nactual, nrequired; 5867 int inum = 0; 5868 int x, y; 5869 int ddi_status = DDI_SUCCESS; 5870 nxge_status_t status = NXGE_OK; 5871 5872 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 5873 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5874 intrp->start_inum = 0; 5875 5876 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 5877 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 5878 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5879 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 5880 "nintrs: %d", ddi_status, nintrs)); 5881 return (NXGE_ERROR | NXGE_DDI_FAILED); 5882 } 5883 5884 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 5885 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 5886 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5887 "ddi_intr_get_navail() failed, status: 0x%x%, " 5888 "nintrs: %d", ddi_status, navail)); 5889 return (NXGE_ERROR | NXGE_DDI_FAILED); 5890 } 5891 5892 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5893 "ddi_intr_get_navail() returned: nintrs %d, navail %d", 5894 nintrs, navail)); 5895 5896 /* PSARC/2007/453 MSI-X interrupt limit override */ 5897 if (int_type == DDI_INTR_TYPE_MSIX) { 5898 nrequest = nxge_create_msi_property(nxgep); 5899 if (nrequest < navail) { 5900 navail = nrequest; 5901 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5902 "nxge_add_intrs_adv_type: nintrs %d " 5903 "navail %d (nrequest %d)", 5904 nintrs, navail, nrequest)); 5905 } 5906 } 5907 5908 if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 5909 /* MSI must be power of 2 */ 5910 if ((navail & 16) == 16) { 5911 navail = 16; 5912 } else if ((navail & 8) == 8) { 5913 navail = 8; 5914 } else if ((navail & 4) == 4) { 5915 navail = 4; 5916 } else if ((navail & 2) == 2) { 5917 navail = 2; 5918 } else { 5919 navail = 1; 5920 } 5921 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5922 "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 5923 "navail %d", nintrs, navail)); 5924 } 5925 5926 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 5927 DDI_INTR_ALLOC_NORMAL); 5928 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 5929 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 5930 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 5931 navail, &nactual, behavior); 5932 if (ddi_status != DDI_SUCCESS || nactual == 0) { 5933 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5934 " ddi_intr_alloc() failed: %d", 5935 ddi_status)); 5936 kmem_free(intrp->htable, intrp->intr_size); 5937 return (NXGE_ERROR | NXGE_DDI_FAILED); 5938 } 5939 5940 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 5941 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 5942 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5943 " ddi_intr_get_pri() failed: %d", 5944 ddi_status)); 5945 /* Free already allocated interrupts */ 5946 for (y = 0; y < nactual; y++) { 5947 (void) ddi_intr_free(intrp->htable[y]); 5948 } 5949 5950 kmem_free(intrp->htable, intrp->intr_size); 5951 return (NXGE_ERROR | NXGE_DDI_FAILED); 5952 } 5953 5954 nrequired = 0; 5955 switch (nxgep->niu_type) { 5956 default: 5957 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 5958 break; 5959 5960 case N2_NIU: 5961 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 5962 break; 5963 } 5964 5965 if (status != NXGE_OK) { 5966 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5967 "nxge_add_intrs_adv_typ:nxge_ldgv_init " 5968 "failed: 0x%x", status)); 5969 /* Free already allocated interrupts */ 5970 for (y = 0; y < nactual; y++) { 5971 (void) ddi_intr_free(intrp->htable[y]); 5972 } 5973 5974 kmem_free(intrp->htable, intrp->intr_size); 5975 return (status); 5976 } 5977 5978 ldgp = nxgep->ldgvp->ldgp; 5979 for (x = 0; x < nrequired; x++, ldgp++) { 5980 ldgp->vector = (uint8_t)x; 5981 ldgp->intdata = SID_DATA(ldgp->func, x); 5982 arg1 = ldgp->ldvp; 5983 arg2 = nxgep; 5984 if (ldgp->nldvs == 1) { 5985 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 5986 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5987 "nxge_add_intrs_adv_type: " 5988 "arg1 0x%x arg2 0x%x: " 5989 "1-1 int handler (entry %d intdata 0x%x)\n", 5990 arg1, arg2, 5991 x, ldgp->intdata)); 5992 } else if (ldgp->nldvs > 1) { 5993 inthandler = (uint_t *)ldgp->sys_intr_handler; 5994 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5995 "nxge_add_intrs_adv_type: " 5996 "arg1 0x%x arg2 0x%x: " 5997 "nldevs %d int handler " 5998 "(entry %d intdata 0x%x)\n", 5999 arg1, arg2, 6000 ldgp->nldvs, x, ldgp->intdata)); 6001 } 6002 6003 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6004 "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 6005 "htable 0x%llx", x, intrp->htable[x])); 6006 6007 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6008 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6009 != DDI_SUCCESS) { 6010 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6011 "==> nxge_add_intrs_adv_type: failed #%d " 6012 "status 0x%x", x, ddi_status)); 6013 for (y = 0; y < intrp->intr_added; y++) { 6014 (void) ddi_intr_remove_handler( 6015 intrp->htable[y]); 6016 } 6017 /* Free already allocated intr */ 6018 for (y = 0; y < nactual; y++) { 6019 (void) ddi_intr_free(intrp->htable[y]); 6020 } 6021 kmem_free(intrp->htable, intrp->intr_size); 6022 6023 (void) nxge_ldgv_uninit(nxgep); 6024 6025 return (NXGE_ERROR | NXGE_DDI_FAILED); 6026 } 6027 intrp->intr_added++; 6028 } 6029 6030 intrp->msi_intx_cnt = nactual; 6031 6032 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6033 "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 6034 navail, nactual, 6035 intrp->msi_intx_cnt, 6036 intrp->intr_added)); 6037 6038 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6039 6040 (void) nxge_intr_ldgv_init(nxgep); 6041 6042 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 6043 6044 return (status); 6045 } 6046 6047 /*ARGSUSED*/ 6048 static nxge_status_t 6049 nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 6050 { 6051 dev_info_t *dip = nxgep->dip; 6052 p_nxge_ldg_t ldgp; 6053 p_nxge_intr_t intrp; 6054 uint_t *inthandler; 6055 void *arg1, *arg2; 6056 int behavior; 6057 int nintrs, navail; 6058 int nactual, nrequired; 6059 int inum = 0; 6060 int x, y; 6061 int ddi_status = DDI_SUCCESS; 6062 nxge_status_t status = NXGE_OK; 6063 6064 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 6065 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6066 intrp->start_inum = 0; 6067 6068 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 6069 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 6070 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6071 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 6072 "nintrs: %d", status, nintrs)); 6073 return (NXGE_ERROR | NXGE_DDI_FAILED); 6074 } 6075 6076 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 6077 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 6078 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6079 "ddi_intr_get_navail() failed, status: 0x%x%, " 6080 "nintrs: %d", ddi_status, navail)); 6081 return (NXGE_ERROR | NXGE_DDI_FAILED); 6082 } 6083 6084 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6085 "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 6086 nintrs, navail)); 6087 6088 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 6089 DDI_INTR_ALLOC_NORMAL); 6090 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 6091 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 6092 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 6093 navail, &nactual, behavior); 6094 if (ddi_status != DDI_SUCCESS || nactual == 0) { 6095 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6096 " ddi_intr_alloc() failed: %d", 6097 ddi_status)); 6098 kmem_free(intrp->htable, intrp->intr_size); 6099 return (NXGE_ERROR | NXGE_DDI_FAILED); 6100 } 6101 6102 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 6103 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 6104 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6105 " ddi_intr_get_pri() failed: %d", 6106 ddi_status)); 6107 /* Free already allocated interrupts */ 6108 for (y = 0; y < nactual; y++) { 6109 (void) ddi_intr_free(intrp->htable[y]); 6110 } 6111 6112 kmem_free(intrp->htable, intrp->intr_size); 6113 return (NXGE_ERROR | NXGE_DDI_FAILED); 6114 } 6115 6116 nrequired = 0; 6117 switch (nxgep->niu_type) { 6118 default: 6119 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 6120 break; 6121 6122 case N2_NIU: 6123 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 6124 break; 6125 } 6126 6127 if (status != NXGE_OK) { 6128 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6129 "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 6130 "failed: 0x%x", status)); 6131 /* Free already allocated interrupts */ 6132 for (y = 0; y < nactual; y++) { 6133 (void) ddi_intr_free(intrp->htable[y]); 6134 } 6135 6136 kmem_free(intrp->htable, intrp->intr_size); 6137 return (status); 6138 } 6139 6140 ldgp = nxgep->ldgvp->ldgp; 6141 for (x = 0; x < nrequired; x++, ldgp++) { 6142 ldgp->vector = (uint8_t)x; 6143 if (nxgep->niu_type != N2_NIU) { 6144 ldgp->intdata = SID_DATA(ldgp->func, x); 6145 } 6146 6147 arg1 = ldgp->ldvp; 6148 arg2 = nxgep; 6149 if (ldgp->nldvs == 1) { 6150 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 6151 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6152 "nxge_add_intrs_adv_type_fix: " 6153 "1-1 int handler(%d) ldg %d ldv %d " 6154 "arg1 $%p arg2 $%p\n", 6155 x, ldgp->ldg, ldgp->ldvp->ldv, 6156 arg1, arg2)); 6157 } else if (ldgp->nldvs > 1) { 6158 inthandler = (uint_t *)ldgp->sys_intr_handler; 6159 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6160 "nxge_add_intrs_adv_type_fix: " 6161 "shared ldv %d int handler(%d) ldv %d ldg %d" 6162 "arg1 0x%016llx arg2 0x%016llx\n", 6163 x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 6164 arg1, arg2)); 6165 } 6166 6167 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6168 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6169 != DDI_SUCCESS) { 6170 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6171 "==> nxge_add_intrs_adv_type_fix: failed #%d " 6172 "status 0x%x", x, ddi_status)); 6173 for (y = 0; y < intrp->intr_added; y++) { 6174 (void) ddi_intr_remove_handler( 6175 intrp->htable[y]); 6176 } 6177 for (y = 0; y < nactual; y++) { 6178 (void) ddi_intr_free(intrp->htable[y]); 6179 } 6180 /* Free already allocated intr */ 6181 kmem_free(intrp->htable, intrp->intr_size); 6182 6183 (void) nxge_ldgv_uninit(nxgep); 6184 6185 return (NXGE_ERROR | NXGE_DDI_FAILED); 6186 } 6187 intrp->intr_added++; 6188 } 6189 6190 intrp->msi_intx_cnt = nactual; 6191 6192 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6193 6194 status = nxge_intr_ldgv_init(nxgep); 6195 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 6196 6197 return (status); 6198 } 6199 6200 static void 6201 nxge_remove_intrs(p_nxge_t nxgep) 6202 { 6203 int i, inum; 6204 p_nxge_intr_t intrp; 6205 6206 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 6207 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6208 if (!intrp->intr_registered) { 6209 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6210 "<== nxge_remove_intrs: interrupts not registered")); 6211 return; 6212 } 6213 6214 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 6215 6216 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6217 (void) ddi_intr_block_disable(intrp->htable, 6218 intrp->intr_added); 6219 } else { 6220 for (i = 0; i < intrp->intr_added; i++) { 6221 (void) ddi_intr_disable(intrp->htable[i]); 6222 } 6223 } 6224 6225 for (inum = 0; inum < intrp->intr_added; inum++) { 6226 if (intrp->htable[inum]) { 6227 (void) ddi_intr_remove_handler(intrp->htable[inum]); 6228 } 6229 } 6230 6231 for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 6232 if (intrp->htable[inum]) { 6233 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6234 "nxge_remove_intrs: ddi_intr_free inum %d " 6235 "msi_intx_cnt %d intr_added %d", 6236 inum, 6237 intrp->msi_intx_cnt, 6238 intrp->intr_added)); 6239 6240 (void) ddi_intr_free(intrp->htable[inum]); 6241 } 6242 } 6243 6244 kmem_free(intrp->htable, intrp->intr_size); 6245 intrp->intr_registered = B_FALSE; 6246 intrp->intr_enabled = B_FALSE; 6247 intrp->msi_intx_cnt = 0; 6248 intrp->intr_added = 0; 6249 6250 (void) nxge_ldgv_uninit(nxgep); 6251 6252 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6253 "#msix-request"); 6254 6255 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 6256 } 6257 6258 /*ARGSUSED*/ 6259 static void 6260 nxge_remove_soft_intrs(p_nxge_t nxgep) 6261 { 6262 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_soft_intrs")); 6263 if (nxgep->resched_id) { 6264 ddi_remove_softintr(nxgep->resched_id); 6265 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6266 "==> nxge_remove_soft_intrs: removed")); 6267 nxgep->resched_id = NULL; 6268 } 6269 6270 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_soft_intrs")); 6271 } 6272 6273 /*ARGSUSED*/ 6274 static void 6275 nxge_intrs_enable(p_nxge_t nxgep) 6276 { 6277 p_nxge_intr_t intrp; 6278 int i; 6279 int status; 6280 6281 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 6282 6283 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6284 6285 if (!intrp->intr_registered) { 6286 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 6287 "interrupts are not registered")); 6288 return; 6289 } 6290 6291 if (intrp->intr_enabled) { 6292 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6293 "<== nxge_intrs_enable: already enabled")); 6294 return; 6295 } 6296 6297 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6298 status = ddi_intr_block_enable(intrp->htable, 6299 intrp->intr_added); 6300 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6301 "block enable - status 0x%x total inums #%d\n", 6302 status, intrp->intr_added)); 6303 } else { 6304 for (i = 0; i < intrp->intr_added; i++) { 6305 status = ddi_intr_enable(intrp->htable[i]); 6306 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6307 "ddi_intr_enable:enable - status 0x%x " 6308 "total inums %d enable inum #%d\n", 6309 status, intrp->intr_added, i)); 6310 if (status == DDI_SUCCESS) { 6311 intrp->intr_enabled = B_TRUE; 6312 } 6313 } 6314 } 6315 6316 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 6317 } 6318 6319 /*ARGSUSED*/ 6320 static void 6321 nxge_intrs_disable(p_nxge_t nxgep) 6322 { 6323 p_nxge_intr_t intrp; 6324 int i; 6325 6326 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 6327 6328 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6329 6330 if (!intrp->intr_registered) { 6331 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 6332 "interrupts are not registered")); 6333 return; 6334 } 6335 6336 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6337 (void) ddi_intr_block_disable(intrp->htable, 6338 intrp->intr_added); 6339 } else { 6340 for (i = 0; i < intrp->intr_added; i++) { 6341 (void) ddi_intr_disable(intrp->htable[i]); 6342 } 6343 } 6344 6345 intrp->intr_enabled = B_FALSE; 6346 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 6347 } 6348 6349 static nxge_status_t 6350 nxge_mac_register(p_nxge_t nxgep) 6351 { 6352 mac_register_t *macp; 6353 int status; 6354 6355 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 6356 6357 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 6358 return (NXGE_ERROR); 6359 6360 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 6361 macp->m_driver = nxgep; 6362 macp->m_dip = nxgep->dip; 6363 macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 6364 macp->m_callbacks = &nxge_m_callbacks; 6365 macp->m_min_sdu = 0; 6366 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 6367 NXGE_EHEADER_VLAN_CRC; 6368 macp->m_max_sdu = nxgep->mac.default_mtu; 6369 macp->m_margin = VLAN_TAGSZ; 6370 macp->m_priv_props = nxge_priv_props; 6371 macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 6372 6373 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6374 "==> nxge_mac_register: instance %d " 6375 "max_sdu %d margin %d maxframe %d (header %d)", 6376 nxgep->instance, 6377 macp->m_max_sdu, macp->m_margin, 6378 nxgep->mac.maxframesize, 6379 NXGE_EHEADER_VLAN_CRC)); 6380 6381 status = mac_register(macp, &nxgep->mach); 6382 mac_free(macp); 6383 6384 if (status != 0) { 6385 cmn_err(CE_WARN, 6386 "!nxge_mac_register failed (status %d instance %d)", 6387 status, nxgep->instance); 6388 return (NXGE_ERROR); 6389 } 6390 6391 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 6392 "(instance %d)", nxgep->instance)); 6393 6394 return (NXGE_OK); 6395 } 6396 6397 void 6398 nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 6399 { 6400 ssize_t size; 6401 mblk_t *nmp; 6402 uint8_t blk_id; 6403 uint8_t chan; 6404 uint32_t err_id; 6405 err_inject_t *eip; 6406 6407 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 6408 6409 size = 1024; 6410 nmp = mp->b_cont; 6411 eip = (err_inject_t *)nmp->b_rptr; 6412 blk_id = eip->blk_id; 6413 err_id = eip->err_id; 6414 chan = eip->chan; 6415 cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 6416 cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 6417 cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 6418 switch (blk_id) { 6419 case MAC_BLK_ID: 6420 break; 6421 case TXMAC_BLK_ID: 6422 break; 6423 case RXMAC_BLK_ID: 6424 break; 6425 case MIF_BLK_ID: 6426 break; 6427 case IPP_BLK_ID: 6428 nxge_ipp_inject_err(nxgep, err_id); 6429 break; 6430 case TXC_BLK_ID: 6431 nxge_txc_inject_err(nxgep, err_id); 6432 break; 6433 case TXDMA_BLK_ID: 6434 nxge_txdma_inject_err(nxgep, err_id, chan); 6435 break; 6436 case RXDMA_BLK_ID: 6437 nxge_rxdma_inject_err(nxgep, err_id, chan); 6438 break; 6439 case ZCP_BLK_ID: 6440 nxge_zcp_inject_err(nxgep, err_id); 6441 break; 6442 case ESPC_BLK_ID: 6443 break; 6444 case FFLP_BLK_ID: 6445 break; 6446 case PHY_BLK_ID: 6447 break; 6448 case ETHER_SERDES_BLK_ID: 6449 break; 6450 case PCIE_SERDES_BLK_ID: 6451 break; 6452 case VIR_BLK_ID: 6453 break; 6454 } 6455 6456 nmp->b_wptr = nmp->b_rptr + size; 6457 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 6458 6459 miocack(wq, mp, (int)size, 0); 6460 } 6461 6462 static int 6463 nxge_init_common_dev(p_nxge_t nxgep) 6464 { 6465 p_nxge_hw_list_t hw_p; 6466 dev_info_t *p_dip; 6467 6468 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 6469 6470 p_dip = nxgep->p_dip; 6471 MUTEX_ENTER(&nxge_common_lock); 6472 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6473 "==> nxge_init_common_dev:func # %d", 6474 nxgep->function_num)); 6475 /* 6476 * Loop through existing per neptune hardware list. 6477 */ 6478 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6479 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6480 "==> nxge_init_common_device:func # %d " 6481 "hw_p $%p parent dip $%p", 6482 nxgep->function_num, 6483 hw_p, 6484 p_dip)); 6485 if (hw_p->parent_devp == p_dip) { 6486 nxgep->nxge_hw_p = hw_p; 6487 hw_p->ndevs++; 6488 hw_p->nxge_p[nxgep->function_num] = nxgep; 6489 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6490 "==> nxge_init_common_device:func # %d " 6491 "hw_p $%p parent dip $%p " 6492 "ndevs %d (found)", 6493 nxgep->function_num, 6494 hw_p, 6495 p_dip, 6496 hw_p->ndevs)); 6497 break; 6498 } 6499 } 6500 6501 if (hw_p == NULL) { 6502 6503 char **prop_val; 6504 uint_t prop_len; 6505 int i; 6506 6507 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6508 "==> nxge_init_common_device:func # %d " 6509 "parent dip $%p (new)", 6510 nxgep->function_num, 6511 p_dip)); 6512 hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 6513 hw_p->parent_devp = p_dip; 6514 hw_p->magic = NXGE_NEPTUNE_MAGIC; 6515 nxgep->nxge_hw_p = hw_p; 6516 hw_p->ndevs++; 6517 hw_p->nxge_p[nxgep->function_num] = nxgep; 6518 hw_p->next = nxge_hw_list; 6519 if (nxgep->niu_type == N2_NIU) { 6520 hw_p->niu_type = N2_NIU; 6521 hw_p->platform_type = P_NEPTUNE_NIU; 6522 } else { 6523 hw_p->niu_type = NIU_TYPE_NONE; 6524 hw_p->platform_type = P_NEPTUNE_NONE; 6525 } 6526 6527 MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 6528 MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 6529 MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 6530 MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 6531 6532 nxge_hw_list = hw_p; 6533 6534 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0, 6535 "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 6536 for (i = 0; i < prop_len; i++) { 6537 if ((strcmp((caddr_t)prop_val[i], 6538 NXGE_ROCK_COMPATIBLE) == 0)) { 6539 hw_p->platform_type = P_NEPTUNE_ROCK; 6540 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6541 "ROCK hw_p->platform_type %d", 6542 hw_p->platform_type)); 6543 break; 6544 } 6545 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6546 "nxge_init_common_dev: read compatible" 6547 " property[%d] val[%s]", 6548 i, (caddr_t)prop_val[i])); 6549 } 6550 } 6551 6552 ddi_prop_free(prop_val); 6553 6554 (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 6555 } 6556 6557 MUTEX_EXIT(&nxge_common_lock); 6558 6559 nxgep->platform_type = hw_p->platform_type; 6560 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxgep->platform_type %d", 6561 nxgep->platform_type)); 6562 if (nxgep->niu_type != N2_NIU) { 6563 nxgep->niu_type = hw_p->niu_type; 6564 } 6565 6566 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6567 "==> nxge_init_common_device (nxge_hw_list) $%p", 6568 nxge_hw_list)); 6569 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 6570 6571 return (NXGE_OK); 6572 } 6573 6574 static void 6575 nxge_uninit_common_dev(p_nxge_t nxgep) 6576 { 6577 p_nxge_hw_list_t hw_p, h_hw_p; 6578 p_nxge_dma_pt_cfg_t p_dma_cfgp; 6579 p_nxge_hw_pt_cfg_t p_cfgp; 6580 dev_info_t *p_dip; 6581 6582 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 6583 if (nxgep->nxge_hw_p == NULL) { 6584 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6585 "<== nxge_uninit_common_device (no common)")); 6586 return; 6587 } 6588 6589 MUTEX_ENTER(&nxge_common_lock); 6590 h_hw_p = nxge_hw_list; 6591 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6592 p_dip = hw_p->parent_devp; 6593 if (nxgep->nxge_hw_p == hw_p && 6594 p_dip == nxgep->p_dip && 6595 nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 6596 hw_p->magic == NXGE_NEPTUNE_MAGIC) { 6597 6598 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6599 "==> nxge_uninit_common_device:func # %d " 6600 "hw_p $%p parent dip $%p " 6601 "ndevs %d (found)", 6602 nxgep->function_num, 6603 hw_p, 6604 p_dip, 6605 hw_p->ndevs)); 6606 6607 /* 6608 * Release the RDC table, a shared resoruce 6609 * of the nxge hardware. The RDC table was 6610 * assigned to this instance of nxge in 6611 * nxge_use_cfg_dma_config(). 6612 */ 6613 if (!isLDOMguest(nxgep)) { 6614 p_dma_cfgp = 6615 (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 6616 p_cfgp = 6617 (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 6618 (void) nxge_fzc_rdc_tbl_unbind(nxgep, 6619 p_cfgp->def_mac_rxdma_grpid); 6620 6621 /* Cleanup any outstanding groups. */ 6622 nxge_grp_cleanup(nxgep); 6623 } 6624 6625 if (hw_p->ndevs) { 6626 hw_p->ndevs--; 6627 } 6628 hw_p->nxge_p[nxgep->function_num] = NULL; 6629 if (!hw_p->ndevs) { 6630 MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 6631 MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 6632 MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 6633 MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 6634 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6635 "==> nxge_uninit_common_device: " 6636 "func # %d " 6637 "hw_p $%p parent dip $%p " 6638 "ndevs %d (last)", 6639 nxgep->function_num, 6640 hw_p, 6641 p_dip, 6642 hw_p->ndevs)); 6643 6644 nxge_hio_uninit(nxgep); 6645 6646 if (hw_p == nxge_hw_list) { 6647 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6648 "==> nxge_uninit_common_device:" 6649 "remove head func # %d " 6650 "hw_p $%p parent dip $%p " 6651 "ndevs %d (head)", 6652 nxgep->function_num, 6653 hw_p, 6654 p_dip, 6655 hw_p->ndevs)); 6656 nxge_hw_list = hw_p->next; 6657 } else { 6658 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6659 "==> nxge_uninit_common_device:" 6660 "remove middle func # %d " 6661 "hw_p $%p parent dip $%p " 6662 "ndevs %d (middle)", 6663 nxgep->function_num, 6664 hw_p, 6665 p_dip, 6666 hw_p->ndevs)); 6667 h_hw_p->next = hw_p->next; 6668 } 6669 6670 nxgep->nxge_hw_p = NULL; 6671 KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 6672 } 6673 break; 6674 } else { 6675 h_hw_p = hw_p; 6676 } 6677 } 6678 6679 MUTEX_EXIT(&nxge_common_lock); 6680 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6681 "==> nxge_uninit_common_device (nxge_hw_list) $%p", 6682 nxge_hw_list)); 6683 6684 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 6685 } 6686 6687 /* 6688 * Determines the number of ports from the niu_type or the platform type. 6689 * Returns the number of ports, or returns zero on failure. 6690 */ 6691 6692 int 6693 nxge_get_nports(p_nxge_t nxgep) 6694 { 6695 int nports = 0; 6696 6697 switch (nxgep->niu_type) { 6698 case N2_NIU: 6699 case NEPTUNE_2_10GF: 6700 nports = 2; 6701 break; 6702 case NEPTUNE_4_1GC: 6703 case NEPTUNE_2_10GF_2_1GC: 6704 case NEPTUNE_1_10GF_3_1GC: 6705 case NEPTUNE_1_1GC_1_10GF_2_1GC: 6706 case NEPTUNE_2_10GF_2_1GRF: 6707 nports = 4; 6708 break; 6709 default: 6710 switch (nxgep->platform_type) { 6711 case P_NEPTUNE_NIU: 6712 case P_NEPTUNE_ATLAS_2PORT: 6713 nports = 2; 6714 break; 6715 case P_NEPTUNE_ATLAS_4PORT: 6716 case P_NEPTUNE_MARAMBA_P0: 6717 case P_NEPTUNE_MARAMBA_P1: 6718 case P_NEPTUNE_ROCK: 6719 case P_NEPTUNE_ALONSO: 6720 nports = 4; 6721 break; 6722 default: 6723 break; 6724 } 6725 break; 6726 } 6727 6728 return (nports); 6729 } 6730 6731 /* 6732 * The following two functions are to support 6733 * PSARC/2007/453 MSI-X interrupt limit override. 6734 */ 6735 static int 6736 nxge_create_msi_property(p_nxge_t nxgep) 6737 { 6738 int nmsi; 6739 extern int ncpus; 6740 6741 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6742 6743 switch (nxgep->mac.portmode) { 6744 case PORT_10G_COPPER: 6745 case PORT_10G_FIBER: 6746 case PORT_10G_TN1010: 6747 (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6748 DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6749 /* 6750 * The maximum MSI-X requested will be 8. 6751 * If the # of CPUs is less than 8, we will reqeust 6752 * # MSI-X based on the # of CPUs. 6753 */ 6754 if (ncpus >= NXGE_MSIX_REQUEST_10G) { 6755 nmsi = NXGE_MSIX_REQUEST_10G; 6756 } else { 6757 nmsi = ncpus; 6758 } 6759 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6760 "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6761 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6762 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6763 break; 6764 6765 default: 6766 nmsi = NXGE_MSIX_REQUEST_1G; 6767 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6768 "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6769 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6770 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6771 break; 6772 } 6773 6774 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6775 return (nmsi); 6776 } 6777 6778 /* ARGSUSED */ 6779 static int 6780 nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 6781 void *pr_val) 6782 { 6783 int err = 0; 6784 link_flowctrl_t fl; 6785 6786 switch (pr_num) { 6787 case MAC_PROP_AUTONEG: 6788 *(uint8_t *)pr_val = 1; 6789 break; 6790 case MAC_PROP_FLOWCTRL: 6791 if (pr_valsize < sizeof (link_flowctrl_t)) 6792 return (EINVAL); 6793 fl = LINK_FLOWCTRL_RX; 6794 bcopy(&fl, pr_val, sizeof (fl)); 6795 break; 6796 case MAC_PROP_ADV_1000FDX_CAP: 6797 case MAC_PROP_EN_1000FDX_CAP: 6798 *(uint8_t *)pr_val = 1; 6799 break; 6800 case MAC_PROP_ADV_100FDX_CAP: 6801 case MAC_PROP_EN_100FDX_CAP: 6802 *(uint8_t *)pr_val = 1; 6803 break; 6804 default: 6805 err = ENOTSUP; 6806 break; 6807 } 6808 return (err); 6809 } 6810 6811 6812 /* 6813 * The following is a software around for the Neptune hardware's 6814 * interrupt bugs; The Neptune hardware may generate spurious interrupts when 6815 * an interrupr handler is removed. 6816 */ 6817 #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 6818 #define NXGE_PIM_RESET (1ULL << 29) 6819 #define NXGE_GLU_RESET (1ULL << 30) 6820 #define NXGE_NIU_RESET (1ULL << 31) 6821 #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 6822 NXGE_GLU_RESET | \ 6823 NXGE_NIU_RESET) 6824 6825 #define NXGE_WAIT_QUITE_TIME 200000 6826 #define NXGE_WAIT_QUITE_RETRY 40 6827 #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 6828 6829 static void 6830 nxge_niu_peu_reset(p_nxge_t nxgep) 6831 { 6832 uint32_t rvalue; 6833 p_nxge_hw_list_t hw_p; 6834 p_nxge_t fnxgep; 6835 int i, j; 6836 6837 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 6838 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 6839 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6840 "==> nxge_niu_peu_reset: NULL hardware pointer")); 6841 return; 6842 } 6843 6844 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6845 "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 6846 hw_p->flags, nxgep->nxge_link_poll_timerid, 6847 nxgep->nxge_timerid)); 6848 6849 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 6850 /* 6851 * Make sure other instances from the same hardware 6852 * stop sending PIO and in quiescent state. 6853 */ 6854 for (i = 0; i < NXGE_MAX_PORTS; i++) { 6855 fnxgep = hw_p->nxge_p[i]; 6856 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6857 "==> nxge_niu_peu_reset: checking entry %d " 6858 "nxgep $%p", i, fnxgep)); 6859 #ifdef NXGE_DEBUG 6860 if (fnxgep) { 6861 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6862 "==> nxge_niu_peu_reset: entry %d (function %d) " 6863 "link timer id %d hw timer id %d", 6864 i, fnxgep->function_num, 6865 fnxgep->nxge_link_poll_timerid, 6866 fnxgep->nxge_timerid)); 6867 } 6868 #endif 6869 if (fnxgep && fnxgep != nxgep && 6870 (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 6871 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6872 "==> nxge_niu_peu_reset: checking $%p " 6873 "(function %d) timer ids", 6874 fnxgep, fnxgep->function_num)); 6875 for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 6876 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6877 "==> nxge_niu_peu_reset: waiting")); 6878 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6879 if (!fnxgep->nxge_timerid && 6880 !fnxgep->nxge_link_poll_timerid) { 6881 break; 6882 } 6883 } 6884 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6885 if (fnxgep->nxge_timerid || 6886 fnxgep->nxge_link_poll_timerid) { 6887 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6888 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6889 "<== nxge_niu_peu_reset: cannot reset " 6890 "hardware (devices are still in use)")); 6891 return; 6892 } 6893 } 6894 } 6895 6896 if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 6897 hw_p->flags |= COMMON_RESET_NIU_PCI; 6898 rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 6899 NXGE_PCI_PORT_LOGIC_OFFSET); 6900 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6901 "nxge_niu_peu_reset: read offset 0x%x (%d) " 6902 "(data 0x%x)", 6903 NXGE_PCI_PORT_LOGIC_OFFSET, 6904 NXGE_PCI_PORT_LOGIC_OFFSET, 6905 rvalue)); 6906 6907 rvalue |= NXGE_PCI_RESET_ALL; 6908 pci_config_put32(nxgep->dev_regs->nxge_pciregh, 6909 NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 6910 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6911 "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 6912 rvalue)); 6913 6914 NXGE_DELAY(NXGE_PCI_RESET_WAIT); 6915 } 6916 6917 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6918 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 6919 } 6920 6921 static void 6922 nxge_set_pci_replay_timeout(p_nxge_t nxgep) 6923 { 6924 p_dev_regs_t dev_regs; 6925 uint32_t value; 6926 6927 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 6928 6929 if (!nxge_set_replay_timer) { 6930 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6931 "==> nxge_set_pci_replay_timeout: will not change " 6932 "the timeout")); 6933 return; 6934 } 6935 6936 dev_regs = nxgep->dev_regs; 6937 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6938 "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 6939 dev_regs, dev_regs->nxge_pciregh)); 6940 6941 if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 6942 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6943 "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 6944 "no PCI handle", 6945 dev_regs)); 6946 return; 6947 } 6948 value = (pci_config_get32(dev_regs->nxge_pciregh, 6949 PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 6950 (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 6951 6952 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6953 "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 6954 "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 6955 pci_config_get32(dev_regs->nxge_pciregh, 6956 PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 6957 PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 6958 6959 pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 6960 value); 6961 6962 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6963 "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 6964 pci_config_get32(dev_regs->nxge_pciregh, 6965 PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 6966 6967 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 6968 } 6969 6970 /* 6971 * quiesce(9E) entry point. 6972 * 6973 * This function is called when the system is single-threaded at high 6974 * PIL with preemption disabled. Therefore, this function must not be 6975 * blocked. 6976 * 6977 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6978 * DDI_FAILURE indicates an error condition and should almost never happen. 6979 */ 6980 static int 6981 nxge_quiesce(dev_info_t *dip) 6982 { 6983 int instance = ddi_get_instance(dip); 6984 p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 6985 6986 if (nxgep == NULL) 6987 return (DDI_FAILURE); 6988 6989 /* Turn off debugging */ 6990 nxge_debug_level = NO_DEBUG; 6991 nxgep->nxge_debug_level = NO_DEBUG; 6992 npi_debug_level = NO_DEBUG; 6993 6994 /* 6995 * Stop link monitor only when linkchkmod is interrupt based 6996 */ 6997 if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 6998 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 6999 } 7000 7001 (void) nxge_intr_hw_disable(nxgep); 7002 7003 /* 7004 * Reset the receive MAC side. 7005 */ 7006 (void) nxge_rx_mac_disable(nxgep); 7007 7008 /* Disable and soft reset the IPP */ 7009 if (!isLDOMguest(nxgep)) 7010 (void) nxge_ipp_disable(nxgep); 7011 7012 /* 7013 * Reset the transmit/receive DMA side. 7014 */ 7015 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 7016 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 7017 7018 /* 7019 * Reset the transmit MAC side. 7020 */ 7021 (void) nxge_tx_mac_disable(nxgep); 7022 7023 return (DDI_SUCCESS); 7024 } 7025