1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "nge.h" 30 31 /* 32 * Describes the chip's DMA engine 33 */ 34 35 static ddi_dma_attr_t hot_dma_attr = { 36 DMA_ATTR_V0, /* dma_attr version */ 37 0x0000000000000000ull, /* dma_attr_addr_lo */ 38 0x000000FFFFFFFFFFull, /* dma_attr_addr_hi */ 39 0x000000007FFFFFFFull, /* dma_attr_count_max */ 40 0x0000000000000010ull, /* dma_attr_align */ 41 0x00000FFF, /* dma_attr_burstsizes */ 42 0x00000001, /* dma_attr_minxfer */ 43 0x000000000000FFFFull, /* dma_attr_maxxfer */ 44 0x000000FFFFFFFFFFull, /* dma_attr_seg */ 45 1, /* dma_attr_sgllen */ 46 0x00000001, /* dma_attr_granular */ 47 0 48 }; 49 50 static ddi_dma_attr_t hot_tx_dma_attr = { 51 DMA_ATTR_V0, /* dma_attr version */ 52 0x0000000000000000ull, /* dma_attr_addr_lo */ 53 0x000000FFFFFFFFFFull, /* dma_attr_addr_hi */ 54 0x0000000000003FFFull, /* dma_attr_count_max */ 55 0x0000000000000010ull, /* dma_attr_align */ 56 0x00000FFF, /* dma_attr_burstsizes */ 57 0x00000001, /* dma_attr_minxfer */ 58 0x0000000000003FFFull, /* dma_attr_maxxfer */ 59 0x000000FFFFFFFFFFull, /* dma_attr_seg */ 60 NGE_MAX_COOKIES, /* dma_attr_sgllen */ 61 1, /* dma_attr_granular */ 62 0 63 }; 64 65 static ddi_dma_attr_t sum_dma_attr = { 66 DMA_ATTR_V0, /* dma_attr version */ 67 0x0000000000000000ull, /* dma_attr_addr_lo */ 68 0x00000000FFFFFFFFull, /* dma_attr_addr_hi */ 69 0x000000007FFFFFFFull, /* dma_attr_count_max */ 70 0x0000000000000010ull, /* dma_attr_align */ 71 0x00000FFF, /* dma_attr_burstsizes */ 72 0x00000001, /* dma_attr_minxfer */ 73 0x000000000000FFFFull, /* dma_attr_maxxfer */ 74 0x00000000FFFFFFFFull, /* dma_attr_seg */ 75 1, /* dma_attr_sgllen */ 76 0x00000001, /* dma_attr_granular */ 77 0 78 }; 79 80 static ddi_dma_attr_t sum_tx_dma_attr = { 81 DMA_ATTR_V0, /* dma_attr version */ 82 0x0000000000000000ull, /* dma_attr_addr_lo */ 83 0x00000000FFFFFFFFull, /* dma_attr_addr_hi */ 84 0x0000000000003FFFull, /* dma_attr_count_max */ 85 0x0000000000000010ull, /* dma_attr_align */ 86 0x00000FFF, /* dma_attr_burstsizes */ 87 0x00000001, /* dma_attr_minxfer */ 88 0x0000000000003FFFull, /* dma_attr_maxxfer */ 89 0x00000000FFFFFFFFull, /* dma_attr_seg */ 90 NGE_MAX_COOKIES, /* dma_attr_sgllen */ 91 1, /* dma_attr_granular */ 92 0 93 }; 94 95 /* 96 * DMA access attributes for data. 97 */ 98 ddi_device_acc_attr_t nge_data_accattr = { 99 DDI_DEVICE_ATTR_V0, 100 DDI_STRUCTURE_LE_ACC, 101 DDI_STRICTORDER_ACC, 102 DDI_DEFAULT_ACC 103 }; 104 105 /* 106 * DMA access attributes for descriptors. 107 */ 108 static ddi_device_acc_attr_t nge_desc_accattr = { 109 DDI_DEVICE_ATTR_V0, 110 DDI_STRUCTURE_LE_ACC, 111 DDI_STRICTORDER_ACC, 112 DDI_DEFAULT_ACC 113 }; 114 115 /* 116 * PIO access attributes for registers 117 */ 118 static ddi_device_acc_attr_t nge_reg_accattr = { 119 DDI_DEVICE_ATTR_V0, 120 DDI_STRUCTURE_LE_ACC, 121 DDI_STRICTORDER_ACC, 122 DDI_DEFAULT_ACC 123 }; 124 125 /* 126 * NIC DESC MODE 2 127 */ 128 129 static const nge_desc_attr_t nge_sum_desc = { 130 131 sizeof (sum_rx_bd), 132 sizeof (sum_tx_bd), 133 &sum_dma_attr, 134 &sum_tx_dma_attr, 135 nge_sum_rxd_fill, 136 nge_sum_rxd_check, 137 nge_sum_txd_fill, 138 nge_sum_txd_check, 139 }; 140 141 /* 142 * NIC DESC MODE 3 143 */ 144 145 static const nge_desc_attr_t nge_hot_desc = { 146 147 sizeof (hot_rx_bd), 148 sizeof (hot_tx_bd), 149 &hot_dma_attr, 150 &hot_tx_dma_attr, 151 nge_hot_rxd_fill, 152 nge_hot_rxd_check, 153 nge_hot_txd_fill, 154 nge_hot_txd_check, 155 }; 156 157 static char nge_ident[] = "nVidia 1Gb Ethernet"; 158 static char clsize_propname[] = "cache-line-size"; 159 static char latency_propname[] = "latency-timer"; 160 static char debug_propname[] = "nge-debug-flags"; 161 static char intr_moderation[] = "intr-moderation"; 162 static char rx_data_hw[] = "rx-data-hw"; 163 static char rx_prd_lw[] = "rx-prd-lw"; 164 static char rx_prd_hw[] = "rx-prd-hw"; 165 static char sw_intr_intv[] = "sw-intr-intvl"; 166 static char nge_desc_mode[] = "desc-mode"; 167 static char default_mtu[] = "default_mtu"; 168 static char low_memory_mode[] = "minimal-memory-usage"; 169 extern kmutex_t nge_log_mutex[1]; 170 171 static int nge_m_start(void *); 172 static void nge_m_stop(void *); 173 static int nge_m_promisc(void *, boolean_t); 174 static int nge_m_multicst(void *, boolean_t, const uint8_t *); 175 static int nge_m_unicst(void *, const uint8_t *); 176 static void nge_m_ioctl(void *, queue_t *, mblk_t *); 177 static boolean_t nge_m_getcapab(void *, mac_capab_t, void *); 178 static int nge_m_setprop(void *, const char *, mac_prop_id_t, 179 uint_t, const void *); 180 static int nge_m_getprop(void *, const char *, mac_prop_id_t, 181 uint_t, uint_t, void *); 182 static int nge_set_priv_prop(nge_t *, const char *, uint_t, 183 const void *); 184 static int nge_get_priv_prop(nge_t *, const char *, uint_t, 185 uint_t, void *); 186 187 #define NGE_M_CALLBACK_FLAGS\ 188 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 189 190 static mac_callbacks_t nge_m_callbacks = { 191 NGE_M_CALLBACK_FLAGS, 192 nge_m_stat, 193 nge_m_start, 194 nge_m_stop, 195 nge_m_promisc, 196 nge_m_multicst, 197 nge_m_unicst, 198 nge_m_tx, 199 NULL, 200 nge_m_ioctl, 201 nge_m_getcapab, 202 NULL, 203 NULL, 204 nge_m_setprop, 205 nge_m_getprop 206 }; 207 208 mac_priv_prop_t nge_priv_props[] = { 209 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 210 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 211 {"_recv_max_packet", MAC_PROP_PERM_RW}, 212 {"_poll_quiet_time", MAC_PROP_PERM_RW}, 213 {"_poll_busy_time", MAC_PROP_PERM_RW}, 214 {"_rx_intr_hwater", MAC_PROP_PERM_RW}, 215 {"_rx_intr_lwater", MAC_PROP_PERM_RW}, 216 {"_adv_pause_cap", MAC_PROP_PERM_RW}, 217 {"_adv_asym_pause_cap", MAC_PROP_PERM_RW}, 218 {"_tx_n_intr", MAC_PROP_PERM_RW} 219 }; 220 221 #define NGE_MAX_PRIV_PROPS \ 222 (sizeof (nge_priv_props)/sizeof (mac_priv_prop_t)) 223 224 static int nge_add_intrs(nge_t *, int); 225 static void nge_rem_intrs(nge_t *); 226 static int nge_register_intrs_and_init_locks(nge_t *); 227 228 /* 229 * NGE MSI tunable: 230 */ 231 boolean_t nge_enable_msi = B_FALSE; 232 233 static enum ioc_reply 234 nge_set_loop_mode(nge_t *ngep, uint32_t mode) 235 { 236 /* 237 * If the mode isn't being changed, there's nothing to do ... 238 */ 239 if (mode == ngep->param_loop_mode) 240 return (IOC_ACK); 241 242 /* 243 * Validate the requested mode and prepare a suitable message 244 * to explain the link down/up cycle that the change will 245 * probably induce ... 246 */ 247 switch (mode) { 248 default: 249 return (IOC_INVAL); 250 251 case NGE_LOOP_NONE: 252 case NGE_LOOP_EXTERNAL_100: 253 case NGE_LOOP_EXTERNAL_10: 254 case NGE_LOOP_INTERNAL_PHY: 255 break; 256 } 257 258 /* 259 * All OK; tell the caller to reprogram 260 * the PHY and/or MAC for the new mode ... 261 */ 262 ngep->param_loop_mode = mode; 263 return (IOC_RESTART_ACK); 264 } 265 266 #undef NGE_DBG 267 #define NGE_DBG NGE_DBG_INIT 268 269 /* 270 * Utility routine to carve a slice off a chunk of allocated memory, 271 * updating the chunk descriptor accordingly. The size of the slice 272 * is given by the product of the <qty> and <size> parameters. 273 */ 274 void 275 nge_slice_chunk(dma_area_t *slice, dma_area_t *chunk, 276 uint32_t qty, uint32_t size) 277 { 278 size_t totsize; 279 280 totsize = qty*size; 281 ASSERT(size > 0); 282 ASSERT(totsize <= chunk->alength); 283 284 *slice = *chunk; 285 slice->nslots = qty; 286 slice->size = size; 287 slice->alength = totsize; 288 289 chunk->mem_va = (caddr_t)chunk->mem_va + totsize; 290 chunk->alength -= totsize; 291 chunk->offset += totsize; 292 chunk->cookie.dmac_laddress += totsize; 293 chunk->cookie.dmac_size -= totsize; 294 } 295 296 /* 297 * Allocate an area of memory and a DMA handle for accessing it 298 */ 299 int 300 nge_alloc_dma_mem(nge_t *ngep, size_t memsize, ddi_device_acc_attr_t *attr_p, 301 uint_t dma_flags, dma_area_t *dma_p) 302 { 303 int err; 304 caddr_t va; 305 306 NGE_TRACE(("nge_alloc_dma_mem($%p, %ld, $%p, 0x%x, $%p)", 307 (void *)ngep, memsize, attr_p, dma_flags, dma_p)); 308 /* 309 * Allocate handle 310 */ 311 err = ddi_dma_alloc_handle(ngep->devinfo, ngep->desc_attr.dma_attr, 312 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_hdl); 313 if (err != DDI_SUCCESS) 314 goto fail; 315 316 /* 317 * Allocate memory 318 */ 319 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 320 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 321 DDI_DMA_DONTWAIT, NULL, &va, &dma_p->alength, &dma_p->acc_hdl); 322 if (err != DDI_SUCCESS) 323 goto fail; 324 325 /* 326 * Bind the two together 327 */ 328 dma_p->mem_va = va; 329 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 330 va, dma_p->alength, dma_flags, DDI_DMA_DONTWAIT, NULL, 331 &dma_p->cookie, &dma_p->ncookies); 332 333 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) 334 goto fail; 335 336 dma_p->nslots = ~0U; 337 dma_p->size = ~0U; 338 dma_p->offset = 0; 339 340 return (DDI_SUCCESS); 341 342 fail: 343 nge_free_dma_mem(dma_p); 344 NGE_DEBUG(("nge_alloc_dma_mem: fail to alloc dma memory!")); 345 346 return (DDI_FAILURE); 347 } 348 349 /* 350 * Free one allocated area of DMAable memory 351 */ 352 void 353 nge_free_dma_mem(dma_area_t *dma_p) 354 { 355 if (dma_p->dma_hdl != NULL) { 356 if (dma_p->ncookies) { 357 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 358 dma_p->ncookies = 0; 359 } 360 } 361 if (dma_p->acc_hdl != NULL) { 362 ddi_dma_mem_free(&dma_p->acc_hdl); 363 dma_p->acc_hdl = NULL; 364 } 365 if (dma_p->dma_hdl != NULL) { 366 ddi_dma_free_handle(&dma_p->dma_hdl); 367 dma_p->dma_hdl = NULL; 368 } 369 } 370 371 #define ALLOC_TX_BUF 0x1 372 #define ALLOC_TX_DESC 0x2 373 #define ALLOC_RX_DESC 0x4 374 375 int 376 nge_alloc_bufs(nge_t *ngep) 377 { 378 int err; 379 int split; 380 int progress; 381 size_t txbuffsize; 382 size_t rxdescsize; 383 size_t txdescsize; 384 385 txbuffsize = ngep->tx_desc * ngep->buf_size; 386 rxdescsize = ngep->rx_desc; 387 txdescsize = ngep->tx_desc; 388 rxdescsize *= ngep->desc_attr.rxd_size; 389 txdescsize *= ngep->desc_attr.txd_size; 390 progress = 0; 391 392 NGE_TRACE(("nge_alloc_bufs($%p)", (void *)ngep)); 393 /* 394 * Allocate memory & handles for TX buffers 395 */ 396 ASSERT((txbuffsize % ngep->nge_split) == 0); 397 for (split = 0; split < ngep->nge_split; ++split) { 398 err = nge_alloc_dma_mem(ngep, txbuffsize/ngep->nge_split, 399 &nge_data_accattr, DDI_DMA_WRITE | NGE_DMA_MODE, 400 &ngep->send->buf[split]); 401 if (err != DDI_SUCCESS) 402 goto fail; 403 } 404 405 progress |= ALLOC_TX_BUF; 406 407 /* 408 * Allocate memory & handles for receive return rings and 409 * buffer (producer) descriptor rings 410 */ 411 err = nge_alloc_dma_mem(ngep, rxdescsize, &nge_desc_accattr, 412 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &ngep->recv->desc); 413 if (err != DDI_SUCCESS) 414 goto fail; 415 progress |= ALLOC_RX_DESC; 416 417 /* 418 * Allocate memory & handles for TX descriptor rings, 419 */ 420 err = nge_alloc_dma_mem(ngep, txdescsize, &nge_desc_accattr, 421 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &ngep->send->desc); 422 if (err != DDI_SUCCESS) 423 goto fail; 424 return (DDI_SUCCESS); 425 426 fail: 427 if (progress & ALLOC_RX_DESC) 428 nge_free_dma_mem(&ngep->recv->desc); 429 if (progress & ALLOC_TX_BUF) { 430 for (split = 0; split < ngep->nge_split; ++split) 431 nge_free_dma_mem(&ngep->send->buf[split]); 432 } 433 434 return (DDI_FAILURE); 435 } 436 437 /* 438 * This routine frees the transmit and receive buffers and descriptors. 439 * Make sure the chip is stopped before calling it! 440 */ 441 void 442 nge_free_bufs(nge_t *ngep) 443 { 444 int split; 445 446 NGE_TRACE(("nge_free_bufs($%p)", (void *)ngep)); 447 448 nge_free_dma_mem(&ngep->recv->desc); 449 nge_free_dma_mem(&ngep->send->desc); 450 451 for (split = 0; split < ngep->nge_split; ++split) 452 nge_free_dma_mem(&ngep->send->buf[split]); 453 } 454 455 /* 456 * Clean up initialisation done above before the memory is freed 457 */ 458 static void 459 nge_fini_send_ring(nge_t *ngep) 460 { 461 uint32_t slot; 462 size_t dmah_num; 463 send_ring_t *srp; 464 sw_tx_sbd_t *ssbdp; 465 466 srp = ngep->send; 467 ssbdp = srp->sw_sbds; 468 469 NGE_TRACE(("nge_fini_send_ring($%p)", (void *)ngep)); 470 471 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 472 473 for (slot = 0; slot < dmah_num; ++slot) { 474 if (srp->dmahndl[slot].hndl) { 475 (void) ddi_dma_unbind_handle(srp->dmahndl[slot].hndl); 476 ddi_dma_free_handle(&srp->dmahndl[slot].hndl); 477 srp->dmahndl[slot].hndl = NULL; 478 srp->dmahndl[slot].next = NULL; 479 } 480 } 481 482 srp->dmah_free.head = NULL; 483 srp->dmah_free.tail = NULL; 484 485 kmem_free(ssbdp, srp->desc.nslots*sizeof (*ssbdp)); 486 487 } 488 489 /* 490 * Initialise the specified Send Ring, using the information in the 491 * <dma_area> descriptors that it contains to set up all the other 492 * fields. This routine should be called only once for each ring. 493 */ 494 static int 495 nge_init_send_ring(nge_t *ngep) 496 { 497 size_t dmah_num; 498 uint32_t nslots; 499 uint32_t err; 500 uint32_t slot; 501 uint32_t split; 502 send_ring_t *srp; 503 sw_tx_sbd_t *ssbdp; 504 dma_area_t desc; 505 dma_area_t pbuf; 506 507 srp = ngep->send; 508 srp->desc.nslots = ngep->tx_desc; 509 nslots = srp->desc.nslots; 510 511 NGE_TRACE(("nge_init_send_ring($%p)", (void *)ngep)); 512 /* 513 * Other one-off initialisation of per-ring data 514 */ 515 srp->ngep = ngep; 516 517 /* 518 * Allocate the array of s/w Send Buffer Descriptors 519 */ 520 ssbdp = kmem_zalloc(nslots*sizeof (*ssbdp), KM_SLEEP); 521 srp->sw_sbds = ssbdp; 522 523 /* 524 * Now initialise each array element once and for all 525 */ 526 desc = srp->desc; 527 for (split = 0; split < ngep->nge_split; ++split) { 528 pbuf = srp->buf[split]; 529 for (slot = 0; slot < nslots/ngep->nge_split; ++ssbdp, ++slot) { 530 nge_slice_chunk(&ssbdp->desc, &desc, 1, 531 ngep->desc_attr.txd_size); 532 nge_slice_chunk(&ssbdp->pbuf, &pbuf, 1, 533 ngep->buf_size); 534 } 535 ASSERT(pbuf.alength == 0); 536 } 537 ASSERT(desc.alength == 0); 538 539 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 540 541 /* preallocate dma handles for tx buffer */ 542 for (slot = 0; slot < dmah_num; ++slot) { 543 544 err = ddi_dma_alloc_handle(ngep->devinfo, 545 ngep->desc_attr.tx_dma_attr, DDI_DMA_DONTWAIT, 546 NULL, &srp->dmahndl[slot].hndl); 547 548 if (err != DDI_SUCCESS) { 549 nge_fini_send_ring(ngep); 550 nge_error(ngep, 551 "nge_init_send_ring: alloc dma handle fails"); 552 return (DDI_FAILURE); 553 } 554 srp->dmahndl[slot].next = srp->dmahndl + slot + 1; 555 } 556 557 srp->dmah_free.head = srp->dmahndl; 558 srp->dmah_free.tail = srp->dmahndl + dmah_num - 1; 559 srp->dmah_free.tail->next = NULL; 560 561 return (DDI_SUCCESS); 562 } 563 564 /* 565 * Intialize the tx recycle pointer and tx sending pointer of tx ring 566 * and set the type of tx's data descriptor by default. 567 */ 568 static void 569 nge_reinit_send_ring(nge_t *ngep) 570 { 571 size_t dmah_num; 572 uint32_t slot; 573 send_ring_t *srp; 574 sw_tx_sbd_t *ssbdp; 575 576 srp = ngep->send; 577 578 /* 579 * Reinitialise control variables ... 580 */ 581 582 srp->tx_hwmark = NGE_DESC_MIN; 583 srp->tx_lwmark = NGE_DESC_MIN; 584 585 srp->tx_next = 0; 586 srp->tx_free = srp->desc.nslots; 587 srp->tc_next = 0; 588 589 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 590 591 for (slot = 0; slot - dmah_num != 0; ++slot) 592 srp->dmahndl[slot].next = srp->dmahndl + slot + 1; 593 594 srp->dmah_free.head = srp->dmahndl; 595 srp->dmah_free.tail = srp->dmahndl + dmah_num - 1; 596 srp->dmah_free.tail->next = NULL; 597 598 /* 599 * Zero and sync all the h/w Send Buffer Descriptors 600 */ 601 for (slot = 0; slot < srp->desc.nslots; ++slot) { 602 ssbdp = &srp->sw_sbds[slot]; 603 ssbdp->flags = HOST_OWN; 604 } 605 606 DMA_ZERO(srp->desc); 607 DMA_SYNC(srp->desc, DDI_DMA_SYNC_FORDEV); 608 } 609 610 /* 611 * Initialize the slot number of rx's ring 612 */ 613 static void 614 nge_init_recv_ring(nge_t *ngep) 615 { 616 recv_ring_t *rrp; 617 618 rrp = ngep->recv; 619 rrp->desc.nslots = ngep->rx_desc; 620 rrp->ngep = ngep; 621 } 622 623 /* 624 * Intialize the rx recycle pointer and rx sending pointer of rx ring 625 */ 626 static void 627 nge_reinit_recv_ring(nge_t *ngep) 628 { 629 recv_ring_t *rrp; 630 631 rrp = ngep->recv; 632 633 /* 634 * Reinitialise control variables ... 635 */ 636 rrp->prod_index = 0; 637 /* 638 * Zero and sync all the h/w Send Buffer Descriptors 639 */ 640 DMA_ZERO(rrp->desc); 641 DMA_SYNC(rrp->desc, DDI_DMA_SYNC_FORDEV); 642 } 643 644 /* 645 * Clean up initialisation done above before the memory is freed 646 */ 647 static void 648 nge_fini_buff_ring(nge_t *ngep) 649 { 650 uint32_t i; 651 buff_ring_t *brp; 652 dma_area_t *bufp; 653 sw_rx_sbd_t *bsbdp; 654 655 brp = ngep->buff; 656 bsbdp = brp->sw_rbds; 657 658 NGE_DEBUG(("nge_fini_buff_ring($%p)", (void *)ngep)); 659 660 mutex_enter(brp->recycle_lock); 661 brp->buf_sign++; 662 mutex_exit(brp->recycle_lock); 663 for (i = 0; i < ngep->rx_desc; i++, ++bsbdp) { 664 if (bsbdp->bufp) { 665 if (bsbdp->bufp->mp) 666 freemsg(bsbdp->bufp->mp); 667 nge_free_dma_mem(bsbdp->bufp); 668 kmem_free(bsbdp->bufp, sizeof (dma_area_t)); 669 bsbdp->bufp = NULL; 670 } 671 } 672 while (brp->free_list != NULL) { 673 bufp = brp->free_list; 674 brp->free_list = bufp->next; 675 bufp->next = NULL; 676 if (bufp->mp) 677 freemsg(bufp->mp); 678 nge_free_dma_mem(bufp); 679 kmem_free(bufp, sizeof (dma_area_t)); 680 } 681 while (brp->recycle_list != NULL) { 682 bufp = brp->recycle_list; 683 brp->recycle_list = bufp->next; 684 bufp->next = NULL; 685 if (bufp->mp) 686 freemsg(bufp->mp); 687 nge_free_dma_mem(bufp); 688 kmem_free(bufp, sizeof (dma_area_t)); 689 } 690 691 692 kmem_free(brp->sw_rbds, (ngep->rx_desc * sizeof (*bsbdp))); 693 brp->sw_rbds = NULL; 694 } 695 696 /* 697 * Intialize the Rx's data ring and free ring 698 */ 699 static int 700 nge_init_buff_ring(nge_t *ngep) 701 { 702 uint32_t err; 703 uint32_t slot; 704 uint32_t nslots_buff; 705 uint32_t nslots_recv; 706 buff_ring_t *brp; 707 recv_ring_t *rrp; 708 dma_area_t desc; 709 dma_area_t *bufp; 710 sw_rx_sbd_t *bsbdp; 711 712 rrp = ngep->recv; 713 brp = ngep->buff; 714 brp->nslots = ngep->rx_buf; 715 brp->rx_bcopy = B_FALSE; 716 nslots_recv = rrp->desc.nslots; 717 nslots_buff = brp->nslots; 718 brp->ngep = ngep; 719 720 NGE_TRACE(("nge_init_buff_ring($%p)", (void *)ngep)); 721 722 /* 723 * Allocate the array of s/w Recv Buffer Descriptors 724 */ 725 bsbdp = kmem_zalloc(nslots_recv *sizeof (*bsbdp), KM_SLEEP); 726 brp->sw_rbds = bsbdp; 727 brp->free_list = NULL; 728 brp->recycle_list = NULL; 729 for (slot = 0; slot < nslots_buff; ++slot) { 730 bufp = kmem_zalloc(sizeof (dma_area_t), KM_SLEEP); 731 err = nge_alloc_dma_mem(ngep, (ngep->buf_size 732 + NGE_HEADROOM), 733 &nge_data_accattr, DDI_DMA_READ | NGE_DMA_MODE, bufp); 734 if (err != DDI_SUCCESS) { 735 kmem_free(bufp, sizeof (dma_area_t)); 736 return (DDI_FAILURE); 737 } 738 739 bufp->alength -= NGE_HEADROOM; 740 bufp->offset += NGE_HEADROOM; 741 bufp->private = (caddr_t)ngep; 742 bufp->rx_recycle.free_func = nge_recv_recycle; 743 bufp->rx_recycle.free_arg = (caddr_t)bufp; 744 bufp->signature = brp->buf_sign; 745 bufp->rx_delivered = B_FALSE; 746 bufp->mp = desballoc(DMA_VPTR(*bufp), 747 ngep->buf_size + NGE_HEADROOM, 748 0, &bufp->rx_recycle); 749 750 if (bufp->mp == NULL) { 751 return (DDI_FAILURE); 752 } 753 bufp->next = brp->free_list; 754 brp->free_list = bufp; 755 } 756 757 /* 758 * Now initialise each array element once and for all 759 */ 760 desc = rrp->desc; 761 for (slot = 0; slot < nslots_recv; ++slot, ++bsbdp) { 762 nge_slice_chunk(&bsbdp->desc, &desc, 1, 763 ngep->desc_attr.rxd_size); 764 bufp = brp->free_list; 765 brp->free_list = bufp->next; 766 bsbdp->bufp = bufp; 767 bsbdp->flags = CONTROLER_OWN; 768 bufp->next = NULL; 769 } 770 771 ASSERT(desc.alength == 0); 772 return (DDI_SUCCESS); 773 } 774 775 /* 776 * Fill the host address of data in rx' descriptor 777 * and initialize free pointers of rx free ring 778 */ 779 static int 780 nge_reinit_buff_ring(nge_t *ngep) 781 { 782 uint32_t slot; 783 uint32_t nslots_recv; 784 buff_ring_t *brp; 785 recv_ring_t *rrp; 786 sw_rx_sbd_t *bsbdp; 787 void *hw_bd_p; 788 789 brp = ngep->buff; 790 rrp = ngep->recv; 791 bsbdp = brp->sw_rbds; 792 nslots_recv = rrp->desc.nslots; 793 for (slot = 0; slot < nslots_recv; ++bsbdp, ++slot) { 794 hw_bd_p = DMA_VPTR(bsbdp->desc); 795 /* 796 * There is a scenario: When the traffic of small tcp 797 * packet is heavy, suspending the tcp traffic will 798 * cause the preallocated buffers for rx not to be 799 * released in time by tcp taffic and cause rx's buffer 800 * pointers not to be refilled in time. 801 * 802 * At this point, if we reinitialize the driver, the bufp 803 * pointer for rx's traffic will be NULL. 804 * So the result of the reinitializion fails. 805 */ 806 if (bsbdp->bufp == NULL) 807 return (DDI_FAILURE); 808 809 ngep->desc_attr.rxd_fill(hw_bd_p, &bsbdp->bufp->cookie, 810 bsbdp->bufp->alength); 811 } 812 return (DDI_SUCCESS); 813 } 814 815 static void 816 nge_init_ring_param_lock(nge_t *ngep) 817 { 818 buff_ring_t *brp; 819 send_ring_t *srp; 820 821 srp = ngep->send; 822 brp = ngep->buff; 823 824 /* Init the locks for send ring */ 825 mutex_init(srp->tx_lock, NULL, MUTEX_DRIVER, 826 DDI_INTR_PRI(ngep->intr_pri)); 827 mutex_init(srp->tc_lock, NULL, MUTEX_DRIVER, 828 DDI_INTR_PRI(ngep->intr_pri)); 829 mutex_init(&srp->dmah_lock, NULL, MUTEX_DRIVER, 830 DDI_INTR_PRI(ngep->intr_pri)); 831 832 /* Init parameters of buffer ring */ 833 brp->free_list = NULL; 834 brp->recycle_list = NULL; 835 brp->rx_hold = 0; 836 brp->buf_sign = 0; 837 838 /* Init recycle list lock */ 839 mutex_init(brp->recycle_lock, NULL, MUTEX_DRIVER, 840 DDI_INTR_PRI(ngep->intr_pri)); 841 } 842 843 int 844 nge_init_rings(nge_t *ngep) 845 { 846 uint32_t err; 847 848 err = nge_init_send_ring(ngep); 849 if (err != DDI_SUCCESS) { 850 return (err); 851 } 852 nge_init_recv_ring(ngep); 853 854 err = nge_init_buff_ring(ngep); 855 if (err != DDI_SUCCESS) { 856 nge_fini_send_ring(ngep); 857 return (DDI_FAILURE); 858 } 859 860 return (err); 861 } 862 863 static int 864 nge_reinit_ring(nge_t *ngep) 865 { 866 int err; 867 868 nge_reinit_recv_ring(ngep); 869 nge_reinit_send_ring(ngep); 870 err = nge_reinit_buff_ring(ngep); 871 return (err); 872 } 873 874 875 void 876 nge_fini_rings(nge_t *ngep) 877 { 878 /* 879 * For receive ring, nothing need to be finished. 880 * So only finish buffer ring and send ring here. 881 */ 882 nge_fini_buff_ring(ngep); 883 nge_fini_send_ring(ngep); 884 } 885 886 /* 887 * Loopback ioctl code 888 */ 889 890 static lb_property_t loopmodes[] = { 891 { normal, "normal", NGE_LOOP_NONE }, 892 { external, "100Mbps", NGE_LOOP_EXTERNAL_100 }, 893 { external, "10Mbps", NGE_LOOP_EXTERNAL_10 }, 894 { internal, "PHY", NGE_LOOP_INTERNAL_PHY }, 895 }; 896 897 enum ioc_reply 898 nge_loop_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp) 899 { 900 int cmd; 901 uint32_t *lbmp; 902 lb_info_sz_t *lbsp; 903 lb_property_t *lbpp; 904 905 /* 906 * Validate format of ioctl 907 */ 908 if (mp->b_cont == NULL) 909 return (IOC_INVAL); 910 911 cmd = iocp->ioc_cmd; 912 913 switch (cmd) { 914 default: 915 return (IOC_INVAL); 916 917 case LB_GET_INFO_SIZE: 918 if (iocp->ioc_count != sizeof (lb_info_sz_t)) 919 return (IOC_INVAL); 920 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 921 *lbsp = sizeof (loopmodes); 922 return (IOC_REPLY); 923 924 case LB_GET_INFO: 925 if (iocp->ioc_count != sizeof (loopmodes)) 926 return (IOC_INVAL); 927 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 928 bcopy(loopmodes, lbpp, sizeof (loopmodes)); 929 return (IOC_REPLY); 930 931 case LB_GET_MODE: 932 if (iocp->ioc_count != sizeof (uint32_t)) 933 return (IOC_INVAL); 934 lbmp = (uint32_t *)mp->b_cont->b_rptr; 935 *lbmp = ngep->param_loop_mode; 936 return (IOC_REPLY); 937 938 case LB_SET_MODE: 939 if (iocp->ioc_count != sizeof (uint32_t)) 940 return (IOC_INVAL); 941 lbmp = (uint32_t *)mp->b_cont->b_rptr; 942 return (nge_set_loop_mode(ngep, *lbmp)); 943 } 944 } 945 946 #undef NGE_DBG 947 #define NGE_DBG NGE_DBG_NEMO 948 949 950 static void 951 nge_check_desc_prop(nge_t *ngep) 952 { 953 if (ngep->desc_mode != DESC_HOT && ngep->desc_mode != DESC_OFFLOAD) 954 ngep->desc_mode = DESC_HOT; 955 956 if (ngep->desc_mode == DESC_OFFLOAD) { 957 958 ngep->desc_attr = nge_sum_desc; 959 960 } else if (ngep->desc_mode == DESC_HOT) { 961 962 ngep->desc_attr = nge_hot_desc; 963 } 964 } 965 966 /* 967 * nge_get_props -- get the parameters to tune the driver 968 */ 969 static void 970 nge_get_props(nge_t *ngep) 971 { 972 chip_info_t *infop; 973 dev_info_t *devinfo; 974 nge_dev_spec_param_t *dev_param_p; 975 976 devinfo = ngep->devinfo; 977 infop = (chip_info_t *)&ngep->chipinfo; 978 dev_param_p = &ngep->dev_spec_param; 979 980 infop->clsize = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 981 DDI_PROP_DONTPASS, clsize_propname, 32); 982 983 infop->latency = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 984 DDI_PROP_DONTPASS, latency_propname, 64); 985 ngep->intr_moderation = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 986 DDI_PROP_DONTPASS, intr_moderation, NGE_SET); 987 ngep->rx_datahwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 988 DDI_PROP_DONTPASS, rx_data_hw, 0x20); 989 ngep->rx_prdlwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 990 DDI_PROP_DONTPASS, rx_prd_lw, 0x4); 991 ngep->rx_prdhwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 992 DDI_PROP_DONTPASS, rx_prd_hw, 0xc); 993 994 ngep->sw_intr_intv = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 995 DDI_PROP_DONTPASS, sw_intr_intv, SWTR_ITC); 996 ngep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 997 DDI_PROP_DONTPASS, debug_propname, NGE_DBG_CHIP); 998 ngep->desc_mode = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 999 DDI_PROP_DONTPASS, nge_desc_mode, dev_param_p->desc_type); 1000 ngep->lowmem_mode = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1001 DDI_PROP_DONTPASS, low_memory_mode, 0); 1002 1003 if (dev_param_p->jumbo) { 1004 ngep->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1005 DDI_PROP_DONTPASS, default_mtu, ETHERMTU); 1006 } else 1007 ngep->default_mtu = ETHERMTU; 1008 1009 if (ngep->default_mtu > ETHERMTU && 1010 ngep->default_mtu <= NGE_MTU_2500) { 1011 ngep->buf_size = NGE_JB2500_BUFSZ; 1012 ngep->tx_desc = NGE_SEND_JB2500_SLOTS_DESC; 1013 ngep->rx_desc = NGE_RECV_JB2500_SLOTS_DESC; 1014 ngep->rx_buf = NGE_RECV_JB2500_SLOTS_DESC * 2; 1015 ngep->nge_split = NGE_SPLIT_256; 1016 } else if (ngep->default_mtu > NGE_MTU_2500 && 1017 ngep->default_mtu <= NGE_MTU_4500) { 1018 ngep->buf_size = NGE_JB4500_BUFSZ; 1019 ngep->tx_desc = NGE_SEND_JB4500_SLOTS_DESC; 1020 ngep->rx_desc = NGE_RECV_JB4500_SLOTS_DESC; 1021 ngep->rx_buf = NGE_RECV_JB4500_SLOTS_DESC * 2; 1022 ngep->nge_split = NGE_SPLIT_256; 1023 } else if (ngep->default_mtu > NGE_MTU_4500 && 1024 ngep->default_mtu <= NGE_MAX_MTU) { 1025 ngep->buf_size = NGE_JB9000_BUFSZ; 1026 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1027 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1028 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1029 ngep->nge_split = NGE_SPLIT_256; 1030 } else if (ngep->default_mtu > NGE_MAX_MTU) { 1031 ngep->default_mtu = NGE_MAX_MTU; 1032 ngep->buf_size = NGE_JB9000_BUFSZ; 1033 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1034 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1035 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1036 ngep->nge_split = NGE_SPLIT_256; 1037 } else if (ngep->lowmem_mode != 0) { 1038 ngep->default_mtu = ETHERMTU; 1039 ngep->buf_size = NGE_STD_BUFSZ; 1040 ngep->tx_desc = NGE_SEND_LOWMEM_SLOTS_DESC; 1041 ngep->rx_desc = NGE_RECV_LOWMEM_SLOTS_DESC; 1042 ngep->rx_buf = NGE_RECV_LOWMEM_SLOTS_DESC * 2; 1043 ngep->nge_split = NGE_SPLIT_32; 1044 } else { 1045 ngep->default_mtu = ETHERMTU; 1046 ngep->buf_size = NGE_STD_BUFSZ; 1047 ngep->tx_desc = dev_param_p->tx_desc_num; 1048 ngep->rx_desc = dev_param_p->rx_desc_num; 1049 ngep->rx_buf = dev_param_p->rx_desc_num * 2; 1050 ngep->nge_split = dev_param_p->nge_split; 1051 } 1052 1053 nge_check_desc_prop(ngep); 1054 } 1055 1056 1057 static int 1058 nge_reset(nge_t *ngep) 1059 { 1060 int err; 1061 nge_mul_addr1 maddr1; 1062 nge_sw_statistics_t *sw_stp; 1063 sw_stp = &ngep->statistics.sw_statistics; 1064 send_ring_t *srp = ngep->send; 1065 1066 ASSERT(mutex_owned(ngep->genlock)); 1067 mutex_enter(srp->tc_lock); 1068 mutex_enter(srp->tx_lock); 1069 1070 nge_tx_recycle_all(ngep); 1071 err = nge_reinit_ring(ngep); 1072 if (err == DDI_FAILURE) { 1073 mutex_exit(srp->tx_lock); 1074 mutex_exit(srp->tc_lock); 1075 return (err); 1076 } 1077 err = nge_chip_reset(ngep); 1078 /* 1079 * Clear the Multicast mac address table 1080 */ 1081 nge_reg_put32(ngep, NGE_MUL_ADDR0, 0); 1082 maddr1.addr_val = nge_reg_get32(ngep, NGE_MUL_ADDR1); 1083 maddr1.addr_bits.addr = 0; 1084 nge_reg_put32(ngep, NGE_MUL_ADDR1, maddr1.addr_val); 1085 1086 mutex_exit(srp->tx_lock); 1087 mutex_exit(srp->tc_lock); 1088 if (err == DDI_FAILURE) 1089 return (err); 1090 ngep->watchdog = 0; 1091 ngep->resched_needed = B_FALSE; 1092 ngep->promisc = B_FALSE; 1093 ngep->param_loop_mode = NGE_LOOP_NONE; 1094 ngep->factotum_flag = 0; 1095 ngep->resched_needed = 0; 1096 ngep->nge_mac_state = NGE_MAC_RESET; 1097 ngep->max_sdu = ngep->default_mtu + ETHER_HEAD_LEN + ETHERFCSL; 1098 ngep->max_sdu += VTAG_SIZE; 1099 ngep->rx_def = 0x16; 1100 1101 /* Clear the software statistics */ 1102 sw_stp->recv_count = 0; 1103 sw_stp->xmit_count = 0; 1104 sw_stp->rbytes = 0; 1105 sw_stp->obytes = 0; 1106 1107 return (DDI_SUCCESS); 1108 } 1109 1110 static void 1111 nge_m_stop(void *arg) 1112 { 1113 nge_t *ngep = arg; /* private device info */ 1114 1115 NGE_TRACE(("nge_m_stop($%p)", arg)); 1116 1117 /* 1118 * Just stop processing, then record new MAC state 1119 */ 1120 mutex_enter(ngep->genlock); 1121 /* If suspended, the adapter is already stopped, just return. */ 1122 if (ngep->suspended) { 1123 ASSERT(ngep->nge_mac_state == NGE_MAC_STOPPED); 1124 mutex_exit(ngep->genlock); 1125 return; 1126 } 1127 rw_enter(ngep->rwlock, RW_WRITER); 1128 1129 (void) nge_chip_stop(ngep, B_FALSE); 1130 ngep->nge_mac_state = NGE_MAC_STOPPED; 1131 1132 /* Recycle all the TX BD */ 1133 nge_tx_recycle_all(ngep); 1134 nge_fini_rings(ngep); 1135 nge_free_bufs(ngep); 1136 1137 NGE_DEBUG(("nge_m_stop($%p) done", arg)); 1138 1139 rw_exit(ngep->rwlock); 1140 mutex_exit(ngep->genlock); 1141 } 1142 1143 static int 1144 nge_m_start(void *arg) 1145 { 1146 int err; 1147 nge_t *ngep = arg; 1148 1149 NGE_TRACE(("nge_m_start($%p)", arg)); 1150 1151 /* 1152 * Start processing and record new MAC state 1153 */ 1154 mutex_enter(ngep->genlock); 1155 /* 1156 * If suspended, don't start, as the resume processing 1157 * will recall this function with the suspended flag off. 1158 */ 1159 if (ngep->suspended) { 1160 mutex_exit(ngep->genlock); 1161 return (EIO); 1162 } 1163 rw_enter(ngep->rwlock, RW_WRITER); 1164 err = nge_alloc_bufs(ngep); 1165 if (err != DDI_SUCCESS) { 1166 nge_problem(ngep, "nge_m_start: DMA buffer allocation failed"); 1167 goto finish; 1168 } 1169 err = nge_init_rings(ngep); 1170 if (err != DDI_SUCCESS) { 1171 nge_free_bufs(ngep); 1172 nge_problem(ngep, "nge_init_rings() failed,err=%x", err); 1173 goto finish; 1174 } 1175 err = nge_restart(ngep); 1176 1177 NGE_DEBUG(("nge_m_start($%p) done", arg)); 1178 finish: 1179 rw_exit(ngep->rwlock); 1180 mutex_exit(ngep->genlock); 1181 1182 return (err == DDI_SUCCESS ? 0 : EIO); 1183 } 1184 1185 static int 1186 nge_m_unicst(void *arg, const uint8_t *macaddr) 1187 { 1188 nge_t *ngep = arg; 1189 1190 NGE_TRACE(("nge_m_unicst($%p)", arg)); 1191 /* 1192 * Remember the new current address in the driver state 1193 * Sync the chip's idea of the address too ... 1194 */ 1195 mutex_enter(ngep->genlock); 1196 1197 ethaddr_copy(macaddr, ngep->cur_uni_addr.addr); 1198 ngep->cur_uni_addr.set = 1; 1199 1200 /* 1201 * If we are suspended, we want to quit now, and not update 1202 * the chip. Doing so might put it in a bad state, but the 1203 * resume will get the unicast address installed. 1204 */ 1205 if (ngep->suspended) { 1206 mutex_exit(ngep->genlock); 1207 return (DDI_SUCCESS); 1208 } 1209 nge_chip_sync(ngep); 1210 1211 NGE_DEBUG(("nge_m_unicst($%p) done", arg)); 1212 mutex_exit(ngep->genlock); 1213 1214 return (0); 1215 } 1216 1217 static int 1218 nge_m_promisc(void *arg, boolean_t on) 1219 { 1220 nge_t *ngep = arg; 1221 1222 NGE_TRACE(("nge_m_promisc($%p)", arg)); 1223 1224 /* 1225 * Store specified mode and pass to chip layer to update h/w 1226 */ 1227 mutex_enter(ngep->genlock); 1228 /* 1229 * If suspended, there is no need to do anything, even 1230 * recording the promiscuious mode is not neccessary, as 1231 * it won't be properly set on resume. Just return failing. 1232 */ 1233 if (ngep->suspended) { 1234 mutex_exit(ngep->genlock); 1235 return (DDI_FAILURE); 1236 } 1237 if (ngep->promisc == on) { 1238 mutex_exit(ngep->genlock); 1239 NGE_DEBUG(("nge_m_promisc($%p) done", arg)); 1240 return (0); 1241 } 1242 ngep->promisc = on; 1243 nge_chip_sync(ngep); 1244 NGE_DEBUG(("nge_m_promisc($%p) done", arg)); 1245 mutex_exit(ngep->genlock); 1246 1247 return (0); 1248 } 1249 1250 static void nge_mulparam(nge_t *ngep) 1251 { 1252 uint8_t number; 1253 ether_addr_t pand; 1254 ether_addr_t por; 1255 mul_item *plist; 1256 1257 for (number = 0; number < ETHERADDRL; number++) { 1258 pand[number] = 0x00; 1259 por[number] = 0x00; 1260 } 1261 for (plist = ngep->pcur_mulist; plist != NULL; plist = plist->next) { 1262 for (number = 0; number < ETHERADDRL; number++) { 1263 pand[number] &= plist->mul_addr[number]; 1264 por[number] |= plist->mul_addr[number]; 1265 } 1266 } 1267 for (number = 0; number < ETHERADDRL; number++) { 1268 ngep->cur_mul_addr.addr[number] 1269 = pand[number] & por[number]; 1270 ngep->cur_mul_mask.addr[number] 1271 = pand [number] | (~por[number]); 1272 } 1273 } 1274 static int 1275 nge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 1276 { 1277 boolean_t update; 1278 boolean_t b_eq; 1279 nge_t *ngep = arg; 1280 mul_item *plist; 1281 mul_item *plist_prev; 1282 mul_item *pitem; 1283 1284 NGE_TRACE(("nge_m_multicst($%p, %s, %s)", arg, 1285 (add) ? "add" : "remove", ether_sprintf((void *)mca))); 1286 1287 update = B_FALSE; 1288 plist = plist_prev = NULL; 1289 mutex_enter(ngep->genlock); 1290 if (add) { 1291 if (ngep->pcur_mulist != NULL) { 1292 for (plist = ngep->pcur_mulist; plist != NULL; 1293 plist = plist->next) { 1294 b_eq = ether_eq(plist->mul_addr, mca); 1295 if (b_eq) { 1296 plist->ref_cnt++; 1297 break; 1298 } 1299 plist_prev = plist; 1300 } 1301 } 1302 1303 if (plist == NULL) { 1304 pitem = kmem_zalloc(sizeof (mul_item), KM_SLEEP); 1305 ether_copy(mca, pitem->mul_addr); 1306 pitem ->ref_cnt++; 1307 pitem ->next = NULL; 1308 if (plist_prev == NULL) 1309 ngep->pcur_mulist = pitem; 1310 else 1311 plist_prev->next = pitem; 1312 update = B_TRUE; 1313 } 1314 } else { 1315 if (ngep->pcur_mulist != NULL) { 1316 for (plist = ngep->pcur_mulist; plist != NULL; 1317 plist = plist->next) { 1318 b_eq = ether_eq(plist->mul_addr, mca); 1319 if (b_eq) { 1320 update = B_TRUE; 1321 break; 1322 } 1323 plist_prev = plist; 1324 } 1325 1326 if (update) { 1327 if ((plist_prev == NULL) && 1328 (plist->next == NULL)) 1329 ngep->pcur_mulist = NULL; 1330 else if ((plist_prev == NULL) && 1331 (plist->next != NULL)) 1332 ngep->pcur_mulist = plist->next; 1333 else 1334 plist_prev->next = plist->next; 1335 kmem_free(plist, sizeof (mul_item)); 1336 } 1337 } 1338 } 1339 1340 if (update && !ngep->suspended) { 1341 nge_mulparam(ngep); 1342 nge_chip_sync(ngep); 1343 } 1344 NGE_DEBUG(("nge_m_multicst($%p) done", arg)); 1345 mutex_exit(ngep->genlock); 1346 1347 return (0); 1348 } 1349 1350 static void 1351 nge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1352 { 1353 int err; 1354 int cmd; 1355 nge_t *ngep = arg; 1356 struct iocblk *iocp; 1357 enum ioc_reply status; 1358 boolean_t need_privilege; 1359 1360 /* 1361 * If suspended, we might actually be able to do some of 1362 * these ioctls, but it is harder to make sure they occur 1363 * without actually putting the hardware in an undesireable 1364 * state. So just NAK it. 1365 */ 1366 mutex_enter(ngep->genlock); 1367 if (ngep->suspended) { 1368 miocnak(wq, mp, 0, EINVAL); 1369 mutex_exit(ngep->genlock); 1370 return; 1371 } 1372 mutex_exit(ngep->genlock); 1373 1374 /* 1375 * Validate the command before bothering with the mutex ... 1376 */ 1377 iocp = (struct iocblk *)mp->b_rptr; 1378 iocp->ioc_error = 0; 1379 need_privilege = B_TRUE; 1380 cmd = iocp->ioc_cmd; 1381 1382 NGE_DEBUG(("nge_m_ioctl: cmd 0x%x", cmd)); 1383 switch (cmd) { 1384 default: 1385 NGE_LDB(NGE_DBG_BADIOC, 1386 ("nge_m_ioctl: unknown cmd 0x%x", cmd)); 1387 1388 miocnak(wq, mp, 0, EINVAL); 1389 return; 1390 1391 case NGE_MII_READ: 1392 case NGE_MII_WRITE: 1393 case NGE_SEE_READ: 1394 case NGE_SEE_WRITE: 1395 case NGE_DIAG: 1396 case NGE_PEEK: 1397 case NGE_POKE: 1398 case NGE_PHY_RESET: 1399 case NGE_SOFT_RESET: 1400 case NGE_HARD_RESET: 1401 break; 1402 1403 case LB_GET_INFO_SIZE: 1404 case LB_GET_INFO: 1405 case LB_GET_MODE: 1406 need_privilege = B_FALSE; 1407 break; 1408 case LB_SET_MODE: 1409 break; 1410 } 1411 1412 if (need_privilege) { 1413 /* 1414 * Check for specific net_config privilege. 1415 */ 1416 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 1417 if (err != 0) { 1418 NGE_DEBUG(("nge_m_ioctl: rejected cmd 0x%x, err %d", 1419 cmd, err)); 1420 miocnak(wq, mp, 0, err); 1421 return; 1422 } 1423 } 1424 1425 mutex_enter(ngep->genlock); 1426 1427 switch (cmd) { 1428 default: 1429 _NOTE(NOTREACHED) 1430 status = IOC_INVAL; 1431 break; 1432 1433 case NGE_MII_READ: 1434 case NGE_MII_WRITE: 1435 case NGE_SEE_READ: 1436 case NGE_SEE_WRITE: 1437 case NGE_DIAG: 1438 case NGE_PEEK: 1439 case NGE_POKE: 1440 case NGE_PHY_RESET: 1441 case NGE_SOFT_RESET: 1442 case NGE_HARD_RESET: 1443 status = nge_chip_ioctl(ngep, mp, iocp); 1444 break; 1445 1446 case LB_GET_INFO_SIZE: 1447 case LB_GET_INFO: 1448 case LB_GET_MODE: 1449 case LB_SET_MODE: 1450 status = nge_loop_ioctl(ngep, mp, iocp); 1451 break; 1452 1453 } 1454 1455 /* 1456 * Do we need to reprogram the PHY and/or the MAC? 1457 * Do it now, while we still have the mutex. 1458 * 1459 * Note: update the PHY first, 'cos it controls the 1460 * speed/duplex parameters that the MAC code uses. 1461 */ 1462 1463 NGE_DEBUG(("nge_m_ioctl: cmd 0x%x status %d", cmd, status)); 1464 1465 switch (status) { 1466 case IOC_RESTART_REPLY: 1467 case IOC_RESTART_ACK: 1468 (*ngep->physops->phys_update)(ngep); 1469 nge_chip_sync(ngep); 1470 break; 1471 1472 default: 1473 break; 1474 } 1475 1476 mutex_exit(ngep->genlock); 1477 1478 /* 1479 * Finally, decide how to reply 1480 */ 1481 switch (status) { 1482 1483 default: 1484 case IOC_INVAL: 1485 miocnak(wq, mp, 0, iocp->ioc_error == 0 ? 1486 EINVAL : iocp->ioc_error); 1487 break; 1488 1489 case IOC_DONE: 1490 break; 1491 1492 case IOC_RESTART_ACK: 1493 case IOC_ACK: 1494 miocack(wq, mp, 0, 0); 1495 break; 1496 1497 case IOC_RESTART_REPLY: 1498 case IOC_REPLY: 1499 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1500 M_IOCACK : M_IOCNAK; 1501 qreply(wq, mp); 1502 break; 1503 } 1504 } 1505 1506 static boolean_t 1507 nge_param_locked(mac_prop_id_t pr_num) 1508 { 1509 /* 1510 * All adv_* parameters are locked (read-only) while 1511 * the device is in any sort of loopback mode ... 1512 */ 1513 switch (pr_num) { 1514 case MAC_PROP_ADV_1000FDX_CAP: 1515 case MAC_PROP_EN_1000FDX_CAP: 1516 case MAC_PROP_ADV_1000HDX_CAP: 1517 case MAC_PROP_EN_1000HDX_CAP: 1518 case MAC_PROP_ADV_100FDX_CAP: 1519 case MAC_PROP_EN_100FDX_CAP: 1520 case MAC_PROP_ADV_100HDX_CAP: 1521 case MAC_PROP_EN_100HDX_CAP: 1522 case MAC_PROP_ADV_10FDX_CAP: 1523 case MAC_PROP_EN_10FDX_CAP: 1524 case MAC_PROP_ADV_10HDX_CAP: 1525 case MAC_PROP_EN_10HDX_CAP: 1526 case MAC_PROP_AUTONEG: 1527 case MAC_PROP_FLOWCTRL: 1528 return (B_TRUE); 1529 } 1530 return (B_FALSE); 1531 } 1532 1533 /* 1534 * callback functions for set/get of properties 1535 */ 1536 static int 1537 nge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 1538 uint_t pr_valsize, const void *pr_val) 1539 { 1540 nge_t *ngep = barg; 1541 int err = 0; 1542 uint32_t cur_mtu, new_mtu; 1543 link_flowctrl_t fl; 1544 1545 mutex_enter(ngep->genlock); 1546 if (ngep->param_loop_mode != NGE_LOOP_NONE && 1547 nge_param_locked(pr_num)) { 1548 /* 1549 * All adv_* parameters are locked (read-only) 1550 * while the device is in any sort of loopback mode. 1551 */ 1552 mutex_exit(ngep->genlock); 1553 return (EBUSY); 1554 } 1555 switch (pr_num) { 1556 case MAC_PROP_EN_1000FDX_CAP: 1557 ngep->param_en_1000fdx = *(uint8_t *)pr_val; 1558 ngep->param_adv_1000fdx = *(uint8_t *)pr_val; 1559 goto reprogram; 1560 case MAC_PROP_EN_100FDX_CAP: 1561 ngep->param_en_100fdx = *(uint8_t *)pr_val; 1562 ngep->param_adv_100fdx = *(uint8_t *)pr_val; 1563 goto reprogram; 1564 case MAC_PROP_EN_100HDX_CAP: 1565 ngep->param_en_100hdx = *(uint8_t *)pr_val; 1566 ngep->param_adv_100hdx = *(uint8_t *)pr_val; 1567 goto reprogram; 1568 case MAC_PROP_EN_10FDX_CAP: 1569 ngep->param_en_10fdx = *(uint8_t *)pr_val; 1570 ngep->param_adv_10fdx = *(uint8_t *)pr_val; 1571 goto reprogram; 1572 case MAC_PROP_EN_10HDX_CAP: 1573 ngep->param_en_10hdx = *(uint8_t *)pr_val; 1574 ngep->param_adv_10hdx = *(uint8_t *)pr_val; 1575 reprogram: 1576 (*ngep->physops->phys_update)(ngep); 1577 nge_chip_sync(ngep); 1578 break; 1579 1580 case MAC_PROP_ADV_1000FDX_CAP: 1581 case MAC_PROP_ADV_1000HDX_CAP: 1582 case MAC_PROP_ADV_100FDX_CAP: 1583 case MAC_PROP_ADV_100HDX_CAP: 1584 case MAC_PROP_ADV_10FDX_CAP: 1585 case MAC_PROP_ADV_10HDX_CAP: 1586 case MAC_PROP_STATUS: 1587 case MAC_PROP_SPEED: 1588 case MAC_PROP_DUPLEX: 1589 case MAC_PROP_EN_1000HDX_CAP: 1590 err = ENOTSUP; /* read-only prop. Can't set this */ 1591 break; 1592 case MAC_PROP_AUTONEG: 1593 ngep->param_adv_autoneg = *(uint8_t *)pr_val; 1594 (*ngep->physops->phys_update)(ngep); 1595 nge_chip_sync(ngep); 1596 break; 1597 case MAC_PROP_MTU: 1598 cur_mtu = ngep->default_mtu; 1599 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 1600 if (new_mtu == cur_mtu) { 1601 err = 0; 1602 break; 1603 } 1604 if (new_mtu < ETHERMTU || 1605 new_mtu > NGE_MAX_MTU) { 1606 err = EINVAL; 1607 break; 1608 } 1609 if ((new_mtu > ETHERMTU) && 1610 (!ngep->dev_spec_param.jumbo)) { 1611 err = EINVAL; 1612 break; 1613 } 1614 if (ngep->nge_mac_state == NGE_MAC_STARTED) { 1615 err = EBUSY; 1616 break; 1617 } 1618 1619 ngep->default_mtu = new_mtu; 1620 if (ngep->default_mtu > ETHERMTU && 1621 ngep->default_mtu <= NGE_MTU_2500) { 1622 ngep->buf_size = NGE_JB2500_BUFSZ; 1623 ngep->tx_desc = NGE_SEND_JB2500_SLOTS_DESC; 1624 ngep->rx_desc = NGE_RECV_JB2500_SLOTS_DESC; 1625 ngep->rx_buf = NGE_RECV_JB2500_SLOTS_DESC * 2; 1626 ngep->nge_split = NGE_SPLIT_256; 1627 } else if (ngep->default_mtu > NGE_MTU_2500 && 1628 ngep->default_mtu <= NGE_MTU_4500) { 1629 ngep->buf_size = NGE_JB4500_BUFSZ; 1630 ngep->tx_desc = NGE_SEND_JB4500_SLOTS_DESC; 1631 ngep->rx_desc = NGE_RECV_JB4500_SLOTS_DESC; 1632 ngep->rx_buf = NGE_RECV_JB4500_SLOTS_DESC * 2; 1633 ngep->nge_split = NGE_SPLIT_256; 1634 } else if (ngep->default_mtu > NGE_MTU_4500 && 1635 ngep->default_mtu <= NGE_MAX_MTU) { 1636 ngep->buf_size = NGE_JB9000_BUFSZ; 1637 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1638 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1639 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1640 ngep->nge_split = NGE_SPLIT_256; 1641 } else if (ngep->default_mtu > NGE_MAX_MTU) { 1642 ngep->default_mtu = NGE_MAX_MTU; 1643 ngep->buf_size = NGE_JB9000_BUFSZ; 1644 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1645 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1646 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1647 ngep->nge_split = NGE_SPLIT_256; 1648 } else if (ngep->lowmem_mode != 0) { 1649 ngep->default_mtu = ETHERMTU; 1650 ngep->buf_size = NGE_STD_BUFSZ; 1651 ngep->tx_desc = NGE_SEND_LOWMEM_SLOTS_DESC; 1652 ngep->rx_desc = NGE_RECV_LOWMEM_SLOTS_DESC; 1653 ngep->rx_buf = NGE_RECV_LOWMEM_SLOTS_DESC * 2; 1654 ngep->nge_split = NGE_SPLIT_32; 1655 } else { 1656 ngep->default_mtu = ETHERMTU; 1657 ngep->buf_size = NGE_STD_BUFSZ; 1658 ngep->tx_desc = 1659 ngep->dev_spec_param.tx_desc_num; 1660 ngep->rx_desc = 1661 ngep->dev_spec_param.rx_desc_num; 1662 ngep->rx_buf = 1663 ngep->dev_spec_param.rx_desc_num * 2; 1664 ngep->nge_split = 1665 ngep->dev_spec_param.nge_split; 1666 } 1667 1668 err = mac_maxsdu_update(ngep->mh, ngep->default_mtu); 1669 1670 break; 1671 case MAC_PROP_FLOWCTRL: 1672 bcopy(pr_val, &fl, sizeof (fl)); 1673 switch (fl) { 1674 default: 1675 err = ENOTSUP; 1676 break; 1677 case LINK_FLOWCTRL_NONE: 1678 ngep->param_adv_pause = 0; 1679 ngep->param_adv_asym_pause = 0; 1680 1681 ngep->param_link_rx_pause = B_FALSE; 1682 ngep->param_link_tx_pause = B_FALSE; 1683 break; 1684 case LINK_FLOWCTRL_RX: 1685 if (!((ngep->param_lp_pause == 0) && 1686 (ngep->param_lp_asym_pause == 1))) { 1687 err = EINVAL; 1688 break; 1689 } 1690 ngep->param_adv_pause = 1; 1691 ngep->param_adv_asym_pause = 1; 1692 1693 ngep->param_link_rx_pause = B_TRUE; 1694 ngep->param_link_tx_pause = B_FALSE; 1695 break; 1696 case LINK_FLOWCTRL_TX: 1697 if (!((ngep->param_lp_pause == 1) && 1698 (ngep->param_lp_asym_pause == 1))) { 1699 err = EINVAL; 1700 break; 1701 } 1702 ngep->param_adv_pause = 0; 1703 ngep->param_adv_asym_pause = 1; 1704 1705 ngep->param_link_rx_pause = B_FALSE; 1706 ngep->param_link_tx_pause = B_TRUE; 1707 break; 1708 case LINK_FLOWCTRL_BI: 1709 if (ngep->param_lp_pause != 1) { 1710 err = EINVAL; 1711 break; 1712 } 1713 ngep->param_adv_pause = 1; 1714 1715 ngep->param_link_rx_pause = B_TRUE; 1716 ngep->param_link_tx_pause = B_TRUE; 1717 break; 1718 } 1719 1720 if (err == 0) { 1721 (*ngep->physops->phys_update)(ngep); 1722 nge_chip_sync(ngep); 1723 } 1724 1725 break; 1726 case MAC_PROP_PRIVATE: 1727 err = nge_set_priv_prop(ngep, pr_name, pr_valsize, 1728 pr_val); 1729 if (err == 0) { 1730 (*ngep->physops->phys_update)(ngep); 1731 nge_chip_sync(ngep); 1732 } 1733 break; 1734 default: 1735 err = ENOTSUP; 1736 } 1737 mutex_exit(ngep->genlock); 1738 return (err); 1739 } 1740 1741 static int 1742 nge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 1743 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 1744 { 1745 nge_t *ngep = barg; 1746 int err = 0; 1747 link_flowctrl_t fl; 1748 uint64_t speed; 1749 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 1750 1751 if (pr_valsize == 0) 1752 return (EINVAL); 1753 1754 bzero(pr_val, pr_valsize); 1755 switch (pr_num) { 1756 case MAC_PROP_DUPLEX: 1757 if (pr_valsize >= sizeof (link_duplex_t)) { 1758 bcopy(&ngep->param_link_duplex, pr_val, 1759 sizeof (link_duplex_t)); 1760 } else 1761 err = EINVAL; 1762 break; 1763 case MAC_PROP_SPEED: 1764 if (pr_valsize >= sizeof (uint64_t)) { 1765 speed = ngep->param_link_speed * 1000000ull; 1766 bcopy(&speed, pr_val, sizeof (speed)); 1767 } else 1768 err = EINVAL; 1769 break; 1770 case MAC_PROP_AUTONEG: 1771 if (is_default) { 1772 *(uint8_t *)pr_val = 1; 1773 } else { 1774 *(uint8_t *)pr_val = ngep->param_adv_autoneg; 1775 } 1776 break; 1777 case MAC_PROP_FLOWCTRL: 1778 if (pr_valsize >= sizeof (link_flowctrl_t)) { 1779 if (pr_flags & MAC_PROP_DEFAULT) { 1780 fl = LINK_FLOWCTRL_BI; 1781 bcopy(&fl, pr_val, sizeof (fl)); 1782 break; 1783 } 1784 if (ngep->param_link_rx_pause && 1785 !ngep->param_link_tx_pause) 1786 fl = LINK_FLOWCTRL_RX; 1787 1788 if (!ngep->param_link_rx_pause && 1789 !ngep->param_link_tx_pause) 1790 fl = LINK_FLOWCTRL_NONE; 1791 1792 if (!ngep->param_link_rx_pause && 1793 ngep->param_link_tx_pause) 1794 fl = LINK_FLOWCTRL_TX; 1795 1796 if (ngep->param_link_rx_pause && 1797 ngep->param_link_tx_pause) 1798 fl = LINK_FLOWCTRL_BI; 1799 bcopy(&fl, pr_val, sizeof (fl)); 1800 } else 1801 err = EINVAL; 1802 break; 1803 case MAC_PROP_ADV_1000FDX_CAP: 1804 if (is_default) { 1805 *(uint8_t *)pr_val = 1; 1806 } else { 1807 *(uint8_t *)pr_val = ngep->param_adv_1000fdx; 1808 } 1809 break; 1810 case MAC_PROP_EN_1000FDX_CAP: 1811 if (is_default) { 1812 *(uint8_t *)pr_val = 1; 1813 } else { 1814 *(uint8_t *)pr_val = ngep->param_en_1000fdx; 1815 } 1816 break; 1817 case MAC_PROP_ADV_1000HDX_CAP: 1818 if (is_default) { 1819 *(uint8_t *)pr_val = 0; 1820 } else { 1821 *(uint8_t *)pr_val = ngep->param_adv_1000hdx; 1822 } 1823 break; 1824 case MAC_PROP_EN_1000HDX_CAP: 1825 if (is_default) { 1826 *(uint8_t *)pr_val = 0; 1827 } else { 1828 *(uint8_t *)pr_val = ngep->param_en_1000hdx; 1829 } 1830 break; 1831 case MAC_PROP_ADV_100FDX_CAP: 1832 if (is_default) { 1833 *(uint8_t *)pr_val = 1; 1834 } else { 1835 *(uint8_t *)pr_val = ngep->param_adv_100fdx; 1836 } 1837 break; 1838 case MAC_PROP_EN_100FDX_CAP: 1839 if (is_default) { 1840 *(uint8_t *)pr_val = 1; 1841 } else { 1842 *(uint8_t *)pr_val = ngep->param_en_100fdx; 1843 } 1844 break; 1845 case MAC_PROP_ADV_100HDX_CAP: 1846 if (is_default) { 1847 *(uint8_t *)pr_val = 1; 1848 } else { 1849 *(uint8_t *)pr_val = ngep->param_adv_100hdx; 1850 } 1851 break; 1852 case MAC_PROP_EN_100HDX_CAP: 1853 if (is_default) { 1854 *(uint8_t *)pr_val = 1; 1855 } else { 1856 *(uint8_t *)pr_val = ngep->param_en_100hdx; 1857 } 1858 break; 1859 case MAC_PROP_ADV_10FDX_CAP: 1860 if (is_default) { 1861 *(uint8_t *)pr_val = 1; 1862 } else { 1863 *(uint8_t *)pr_val = ngep->param_adv_10fdx; 1864 } 1865 break; 1866 case MAC_PROP_EN_10FDX_CAP: 1867 if (is_default) { 1868 *(uint8_t *)pr_val = 1; 1869 } else { 1870 *(uint8_t *)pr_val = ngep->param_en_10fdx; 1871 } 1872 break; 1873 case MAC_PROP_ADV_10HDX_CAP: 1874 if (is_default) { 1875 *(uint8_t *)pr_val = 1; 1876 } else { 1877 *(uint8_t *)pr_val = ngep->param_adv_10hdx; 1878 } 1879 break; 1880 case MAC_PROP_EN_10HDX_CAP: 1881 if (is_default) { 1882 *(uint8_t *)pr_val = 1; 1883 } else { 1884 *(uint8_t *)pr_val = ngep->param_en_10hdx; 1885 } 1886 break; 1887 case MAC_PROP_ADV_100T4_CAP: 1888 case MAC_PROP_EN_100T4_CAP: 1889 *(uint8_t *)pr_val = 0; 1890 break; 1891 case MAC_PROP_PRIVATE: 1892 err = nge_get_priv_prop(ngep, pr_name, pr_flags, 1893 pr_valsize, pr_val); 1894 break; 1895 default: 1896 err = ENOTSUP; 1897 } 1898 return (err); 1899 } 1900 1901 /* ARGSUSED */ 1902 static int 1903 nge_set_priv_prop(nge_t *ngep, const char *pr_name, uint_t pr_valsize, 1904 const void *pr_val) 1905 { 1906 int err = 0; 1907 long result; 1908 1909 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 1910 if (pr_val == NULL) { 1911 err = EINVAL; 1912 return (err); 1913 } 1914 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1915 if (result < 0 || result > NGE_MAX_SDU) { 1916 err = EINVAL; 1917 } else { 1918 ngep->param_txbcopy_threshold = (uint32_t)result; 1919 goto reprogram; 1920 } 1921 return (err); 1922 } 1923 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 1924 if (pr_val == NULL) { 1925 err = EINVAL; 1926 return (err); 1927 } 1928 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1929 if (result < 0 || result > NGE_MAX_SDU) { 1930 err = EINVAL; 1931 } else { 1932 ngep->param_rxbcopy_threshold = (uint32_t)result; 1933 goto reprogram; 1934 } 1935 return (err); 1936 } 1937 if (strcmp(pr_name, "_recv_max_packet") == 0) { 1938 if (pr_val == NULL) { 1939 err = EINVAL; 1940 return (err); 1941 } 1942 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1943 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 1944 err = EINVAL; 1945 } else { 1946 ngep->param_recv_max_packet = (uint32_t)result; 1947 goto reprogram; 1948 } 1949 return (err); 1950 } 1951 if (strcmp(pr_name, "_poll_quiet_time") == 0) { 1952 if (pr_val == NULL) { 1953 err = EINVAL; 1954 return (err); 1955 } 1956 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1957 if (result < 0 || result > 10000) { 1958 err = EINVAL; 1959 } else { 1960 ngep->param_poll_quiet_time = (uint32_t)result; 1961 goto reprogram; 1962 } 1963 return (err); 1964 } 1965 if (strcmp(pr_name, "_poll_busy_time") == 0) { 1966 if (pr_val == NULL) { 1967 err = EINVAL; 1968 return (err); 1969 } 1970 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1971 if (result < 0 || result > 10000) { 1972 err = EINVAL; 1973 } else { 1974 ngep->param_poll_busy_time = (uint32_t)result; 1975 goto reprogram; 1976 } 1977 return (err); 1978 } 1979 if (strcmp(pr_name, "_rx_intr_hwater") == 0) { 1980 if (pr_val == NULL) { 1981 err = EINVAL; 1982 return (err); 1983 } 1984 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1985 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 1986 err = EINVAL; 1987 } else { 1988 ngep->param_rx_intr_hwater = (uint32_t)result; 1989 goto reprogram; 1990 } 1991 return (err); 1992 } 1993 if (strcmp(pr_name, "_rx_intr_lwater") == 0) { 1994 if (pr_val == NULL) { 1995 err = EINVAL; 1996 return (err); 1997 } 1998 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1999 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 2000 err = EINVAL; 2001 } else { 2002 ngep->param_rx_intr_lwater = (uint32_t)result; 2003 goto reprogram; 2004 } 2005 return (err); 2006 } 2007 if (strcmp(pr_name, "_tx_n_intr") == 0) { 2008 if (pr_val == NULL) { 2009 err = EINVAL; 2010 return (err); 2011 } 2012 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2013 if (result < 1 || result > 10000) { 2014 err = EINVAL; 2015 } else { 2016 ngep->param_tx_n_intr = (uint32_t)result; 2017 goto reprogram; 2018 } 2019 return (err); 2020 } 2021 2022 err = ENOTSUP; 2023 return (err); 2024 2025 reprogram: 2026 if (err == 0) { 2027 (*ngep->physops->phys_update)(ngep); 2028 nge_chip_sync(ngep); 2029 } 2030 2031 return (err); 2032 } 2033 2034 static int 2035 nge_get_priv_prop(nge_t *ngep, const char *pr_name, uint_t pr_flags, 2036 uint_t pr_valsize, void *pr_val) 2037 { 2038 int err = ENOTSUP; 2039 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 2040 int value; 2041 2042 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 2043 value = (is_default ? 1 : ngep->param_adv_pause); 2044 err = 0; 2045 goto done; 2046 } 2047 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 2048 value = (is_default ? 1 : ngep->param_adv_asym_pause); 2049 err = 0; 2050 goto done; 2051 } 2052 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2053 value = (is_default ? NGE_TX_COPY_SIZE : 2054 ngep->param_txbcopy_threshold); 2055 err = 0; 2056 goto done; 2057 } 2058 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2059 value = (is_default ? NGE_RX_COPY_SIZE : 2060 ngep->param_rxbcopy_threshold); 2061 err = 0; 2062 goto done; 2063 } 2064 if (strcmp(pr_name, "_recv_max_packet") == 0) { 2065 value = (is_default ? 128 : ngep->param_recv_max_packet); 2066 err = 0; 2067 goto done; 2068 } 2069 if (strcmp(pr_name, "_poll_quiet_time") == 0) { 2070 value = (is_default ? NGE_POLL_QUIET_TIME : 2071 ngep->param_poll_quiet_time); 2072 err = 0; 2073 goto done; 2074 } 2075 if (strcmp(pr_name, "_poll_busy_time") == 0) { 2076 value = (is_default ? NGE_POLL_BUSY_TIME : 2077 ngep->param_poll_busy_time); 2078 err = 0; 2079 goto done; 2080 } 2081 if (strcmp(pr_name, "_rx_intr_hwater") == 0) { 2082 value = (is_default ? 1 : ngep->param_rx_intr_hwater); 2083 err = 0; 2084 goto done; 2085 } 2086 if (strcmp(pr_name, "_rx_intr_lwater") == 0) { 2087 value = (is_default ? 8 : ngep->param_rx_intr_lwater); 2088 err = 0; 2089 goto done; 2090 } 2091 if (strcmp(pr_name, "_tx_n_intr") == 0) { 2092 value = (is_default ? NGE_TX_N_INTR : 2093 ngep->param_tx_n_intr); 2094 err = 0; 2095 goto done; 2096 } 2097 2098 done: 2099 if (err == 0) { 2100 (void) snprintf(pr_val, pr_valsize, "%d", value); 2101 } 2102 return (err); 2103 } 2104 2105 /* ARGSUSED */ 2106 static boolean_t 2107 nge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2108 { 2109 nge_t *ngep = arg; 2110 nge_dev_spec_param_t *dev_param_p; 2111 2112 dev_param_p = &ngep->dev_spec_param; 2113 2114 switch (cap) { 2115 case MAC_CAPAB_HCKSUM: { 2116 uint32_t *hcksum_txflags = cap_data; 2117 2118 if (dev_param_p->tx_hw_checksum) { 2119 *hcksum_txflags = dev_param_p->tx_hw_checksum; 2120 } else 2121 return (B_FALSE); 2122 break; 2123 } 2124 case MAC_CAPAB_POLL: 2125 /* 2126 * There's nothing for us to fill in, simply returning 2127 * B_TRUE, stating that we support polling is sufficient. 2128 */ 2129 break; 2130 default: 2131 return (B_FALSE); 2132 } 2133 return (B_TRUE); 2134 } 2135 2136 #undef NGE_DBG 2137 #define NGE_DBG NGE_DBG_INIT /* debug flag for this code */ 2138 int 2139 nge_restart(nge_t *ngep) 2140 { 2141 int err = 0; 2142 err = nge_reset(ngep); 2143 nge_chip_sync(ngep); 2144 if (!err) 2145 err = nge_chip_start(ngep); 2146 2147 if (err) { 2148 ngep->nge_mac_state = NGE_MAC_STOPPED; 2149 return (DDI_FAILURE); 2150 } else { 2151 ngep->nge_mac_state = NGE_MAC_STARTED; 2152 return (DDI_SUCCESS); 2153 } 2154 } 2155 2156 void 2157 nge_wake_factotum(nge_t *ngep) 2158 { 2159 mutex_enter(ngep->softlock); 2160 if (ngep->factotum_flag == 0) { 2161 ngep->factotum_flag = 1; 2162 (void) ddi_intr_trigger_softint(ngep->factotum_hdl, NULL); 2163 } 2164 mutex_exit(ngep->softlock); 2165 } 2166 2167 /* 2168 * High-level cyclic handler 2169 * 2170 * This routine schedules a (low-level) softint callback to the 2171 * factotum. 2172 */ 2173 2174 static void 2175 nge_chip_cyclic(void *arg) 2176 { 2177 nge_t *ngep; 2178 2179 ngep = (nge_t *)arg; 2180 2181 switch (ngep->nge_chip_state) { 2182 default: 2183 return; 2184 2185 case NGE_CHIP_RUNNING: 2186 break; 2187 2188 case NGE_CHIP_FAULT: 2189 case NGE_CHIP_ERROR: 2190 break; 2191 } 2192 2193 nge_wake_factotum(ngep); 2194 } 2195 2196 static void 2197 nge_unattach(nge_t *ngep) 2198 { 2199 send_ring_t *srp; 2200 buff_ring_t *brp; 2201 2202 srp = ngep->send; 2203 brp = ngep->buff; 2204 NGE_TRACE(("nge_unattach($%p)", (void *)ngep)); 2205 2206 /* 2207 * Flag that no more activity may be initiated 2208 */ 2209 ngep->progress &= ~PROGRESS_READY; 2210 ngep->nge_mac_state = NGE_MAC_UNATTACH; 2211 2212 /* 2213 * Quiesce the PHY and MAC (leave it reset but still powered). 2214 * Clean up and free all NGE data structures 2215 */ 2216 if (ngep->periodic_id != NULL) { 2217 ddi_periodic_delete(ngep->periodic_id); 2218 ngep->periodic_id = NULL; 2219 } 2220 2221 if (ngep->progress & PROGRESS_KSTATS) 2222 nge_fini_kstats(ngep); 2223 2224 if (ngep->progress & PROGRESS_HWINT) { 2225 mutex_enter(ngep->genlock); 2226 nge_restore_mac_addr(ngep); 2227 (void) nge_chip_stop(ngep, B_FALSE); 2228 mutex_exit(ngep->genlock); 2229 } 2230 2231 if (ngep->progress & PROGRESS_SWINT) 2232 nge_rem_intrs(ngep); 2233 2234 if (ngep->progress & PROGRESS_FACTOTUM) 2235 (void) ddi_intr_remove_softint(ngep->factotum_hdl); 2236 2237 if (ngep->progress & PROGRESS_RESCHED) 2238 (void) ddi_intr_remove_softint(ngep->resched_hdl); 2239 2240 if (ngep->progress & PROGRESS_INTR) { 2241 mutex_destroy(srp->tx_lock); 2242 mutex_destroy(srp->tc_lock); 2243 mutex_destroy(&srp->dmah_lock); 2244 mutex_destroy(brp->recycle_lock); 2245 2246 mutex_destroy(ngep->genlock); 2247 mutex_destroy(ngep->softlock); 2248 rw_destroy(ngep->rwlock); 2249 } 2250 2251 if (ngep->progress & PROGRESS_REGS) 2252 ddi_regs_map_free(&ngep->io_handle); 2253 2254 if (ngep->progress & PROGRESS_CFG) 2255 pci_config_teardown(&ngep->cfg_handle); 2256 2257 ddi_remove_minor_node(ngep->devinfo, NULL); 2258 2259 kmem_free(ngep, sizeof (*ngep)); 2260 } 2261 2262 static int 2263 nge_resume(dev_info_t *devinfo) 2264 { 2265 nge_t *ngep; 2266 chip_info_t *infop; 2267 int err; 2268 2269 ASSERT(devinfo != NULL); 2270 2271 ngep = ddi_get_driver_private(devinfo); 2272 err = 0; 2273 2274 /* 2275 * If there are state inconsistancies, this is bad. Returning 2276 * DDI_FAILURE here will eventually cause the machine to panic, 2277 * so it is best done here so that there is a possibility of 2278 * debugging the problem. 2279 */ 2280 if (ngep == NULL) 2281 cmn_err(CE_PANIC, 2282 "nge: ngep returned from ddi_get_driver_private was NULL"); 2283 infop = (chip_info_t *)&ngep->chipinfo; 2284 2285 if (ngep->devinfo != devinfo) 2286 cmn_err(CE_PANIC, 2287 "nge: passed devinfo not the same as saved devinfo"); 2288 2289 mutex_enter(ngep->genlock); 2290 rw_enter(ngep->rwlock, RW_WRITER); 2291 2292 /* 2293 * Fetch the config space. Even though we have most of it cached, 2294 * some values *might* change across a suspend/resume. 2295 */ 2296 nge_chip_cfg_init(ngep, infop, B_FALSE); 2297 2298 /* 2299 * Only in one case, this conditional branch can be executed: the port 2300 * hasn't been plumbed. 2301 */ 2302 if (ngep->suspended == B_FALSE) { 2303 rw_exit(ngep->rwlock); 2304 mutex_exit(ngep->genlock); 2305 return (DDI_SUCCESS); 2306 } 2307 2308 nge_tx_recycle_all(ngep); 2309 err = nge_reinit_ring(ngep); 2310 if (!err) { 2311 err = nge_chip_reset(ngep); 2312 if (!err) 2313 err = nge_chip_start(ngep); 2314 } 2315 2316 if (err) { 2317 /* 2318 * We note the failure, but return success, as the 2319 * system is still usable without this controller. 2320 */ 2321 cmn_err(CE_WARN, "nge: resume: failed to restart controller"); 2322 } else { 2323 ngep->nge_mac_state = NGE_MAC_STARTED; 2324 } 2325 ngep->suspended = B_FALSE; 2326 2327 rw_exit(ngep->rwlock); 2328 mutex_exit(ngep->genlock); 2329 2330 return (DDI_SUCCESS); 2331 } 2332 2333 /* 2334 * attach(9E) -- Attach a device to the system 2335 * 2336 * Called once for each board successfully probed. 2337 */ 2338 static int 2339 nge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2340 { 2341 int err; 2342 int i; 2343 int instance; 2344 caddr_t regs; 2345 nge_t *ngep; 2346 chip_info_t *infop; 2347 mac_register_t *macp; 2348 2349 switch (cmd) { 2350 default: 2351 return (DDI_FAILURE); 2352 2353 case DDI_RESUME: 2354 return (nge_resume(devinfo)); 2355 2356 case DDI_ATTACH: 2357 break; 2358 } 2359 2360 ngep = kmem_zalloc(sizeof (*ngep), KM_SLEEP); 2361 instance = ddi_get_instance(devinfo); 2362 ddi_set_driver_private(devinfo, ngep); 2363 ngep->devinfo = devinfo; 2364 2365 (void) snprintf(ngep->ifname, sizeof (ngep->ifname), "%s%d", 2366 NGE_DRIVER_NAME, instance); 2367 err = pci_config_setup(devinfo, &ngep->cfg_handle); 2368 if (err != DDI_SUCCESS) { 2369 nge_problem(ngep, "nge_attach: pci_config_setup() failed"); 2370 goto attach_fail; 2371 } 2372 /* 2373 * param_txbcopy_threshold and param_rxbcopy_threshold are tx/rx bcopy 2374 * thresholds. Bounds: min 0, max NGE_MAX_SDU 2375 */ 2376 ngep->param_txbcopy_threshold = NGE_TX_COPY_SIZE; 2377 ngep->param_rxbcopy_threshold = NGE_RX_COPY_SIZE; 2378 2379 /* 2380 * param_recv_max_packet is max packet received per interupt. 2381 * Bounds: min 0, max NGE_RECV_SLOTS_DESC_1024 2382 */ 2383 ngep->param_recv_max_packet = 128; 2384 2385 /* 2386 * param_poll_quiet_time and param_poll_busy_time are quiet/busy time 2387 * switch from per packet interrupt to polling interrupt. 2388 * Bounds: min 0, max 10000 2389 */ 2390 ngep->param_poll_quiet_time = NGE_POLL_QUIET_TIME; 2391 ngep->param_poll_busy_time = NGE_POLL_BUSY_TIME; 2392 2393 /* 2394 * param_rx_intr_hwater/param_rx_intr_lwater: ackets received 2395 * to trigger the poll_quiet_time/poll_busy_time counter. 2396 * Bounds: min 0, max NGE_RECV_SLOTS_DESC_1024. 2397 */ 2398 ngep->param_rx_intr_hwater = 1; 2399 ngep->param_rx_intr_lwater = 8; 2400 2401 /* 2402 * param_tx_n_intr: Per N tx packets to do tx recycle in poll mode. 2403 * Bounds: min 1, max 10000. 2404 */ 2405 ngep->param_tx_n_intr = NGE_TX_N_INTR; 2406 2407 infop = (chip_info_t *)&ngep->chipinfo; 2408 nge_chip_cfg_init(ngep, infop, B_FALSE); 2409 nge_init_dev_spec_param(ngep); 2410 nge_get_props(ngep); 2411 ngep->progress |= PROGRESS_CFG; 2412 2413 err = ddi_regs_map_setup(devinfo, NGE_PCI_OPREGS_RNUMBER, 2414 ®s, 0, 0, &nge_reg_accattr, &ngep->io_handle); 2415 if (err != DDI_SUCCESS) { 2416 nge_problem(ngep, "nge_attach: ddi_regs_map_setup() failed"); 2417 goto attach_fail; 2418 } 2419 ngep->io_regs = regs; 2420 ngep->progress |= PROGRESS_REGS; 2421 2422 err = nge_register_intrs_and_init_locks(ngep); 2423 if (err != DDI_SUCCESS) { 2424 nge_problem(ngep, "nge_attach:" 2425 " register intrs and init locks failed"); 2426 goto attach_fail; 2427 } 2428 nge_init_ring_param_lock(ngep); 2429 ngep->progress |= PROGRESS_INTR; 2430 2431 mutex_enter(ngep->genlock); 2432 2433 /* 2434 * Initialise link state variables 2435 * Stop, reset & reinitialise the chip. 2436 * Initialise the (internal) PHY. 2437 */ 2438 nge_phys_init(ngep); 2439 err = nge_chip_reset(ngep); 2440 if (err != DDI_SUCCESS) { 2441 nge_problem(ngep, "nge_attach: nge_chip_reset() failed"); 2442 mutex_exit(ngep->genlock); 2443 goto attach_fail; 2444 } 2445 nge_chip_sync(ngep); 2446 2447 /* 2448 * Now that mutex locks are initialized, enable interrupts. 2449 */ 2450 if (ngep->intr_cap & DDI_INTR_FLAG_BLOCK) { 2451 /* Call ddi_intr_block_enable() for MSI interrupts */ 2452 (void) ddi_intr_block_enable(ngep->htable, 2453 ngep->intr_actual_cnt); 2454 } else { 2455 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 2456 for (i = 0; i < ngep->intr_actual_cnt; i++) { 2457 (void) ddi_intr_enable(ngep->htable[i]); 2458 } 2459 } 2460 2461 ngep->link_state = LINK_STATE_UNKNOWN; 2462 ngep->progress |= PROGRESS_HWINT; 2463 2464 /* 2465 * Register NDD-tweakable parameters 2466 */ 2467 if (nge_nd_init(ngep)) { 2468 nge_problem(ngep, "nge_attach: nge_nd_init() failed"); 2469 mutex_exit(ngep->genlock); 2470 goto attach_fail; 2471 } 2472 ngep->progress |= PROGRESS_NDD; 2473 2474 /* 2475 * Create & initialise named kstats 2476 */ 2477 nge_init_kstats(ngep, instance); 2478 ngep->progress |= PROGRESS_KSTATS; 2479 2480 mutex_exit(ngep->genlock); 2481 2482 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 2483 goto attach_fail; 2484 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 2485 macp->m_driver = ngep; 2486 macp->m_dip = devinfo; 2487 macp->m_src_addr = infop->vendor_addr.addr; 2488 macp->m_callbacks = &nge_m_callbacks; 2489 macp->m_min_sdu = 0; 2490 macp->m_max_sdu = ngep->default_mtu; 2491 macp->m_margin = VTAG_SIZE; 2492 macp->m_priv_props = nge_priv_props; 2493 macp->m_priv_prop_count = NGE_MAX_PRIV_PROPS; 2494 /* 2495 * Finally, we're ready to register ourselves with the mac 2496 * interface; if this succeeds, we're all ready to start() 2497 */ 2498 err = mac_register(macp, &ngep->mh); 2499 mac_free(macp); 2500 if (err != 0) 2501 goto attach_fail; 2502 2503 /* 2504 * Register a periodical handler. 2505 * nge_chip_cyclic() is invoked in kernel context. 2506 */ 2507 ngep->periodic_id = ddi_periodic_add(nge_chip_cyclic, ngep, 2508 NGE_CYCLIC_PERIOD, DDI_IPL_0); 2509 2510 ngep->progress |= PROGRESS_READY; 2511 return (DDI_SUCCESS); 2512 2513 attach_fail: 2514 nge_unattach(ngep); 2515 return (DDI_FAILURE); 2516 } 2517 2518 static int 2519 nge_suspend(nge_t *ngep) 2520 { 2521 mutex_enter(ngep->genlock); 2522 rw_enter(ngep->rwlock, RW_WRITER); 2523 2524 /* if the port hasn't been plumbed, just return */ 2525 if (ngep->nge_mac_state != NGE_MAC_STARTED) { 2526 rw_exit(ngep->rwlock); 2527 mutex_exit(ngep->genlock); 2528 return (DDI_SUCCESS); 2529 } 2530 ngep->suspended = B_TRUE; 2531 (void) nge_chip_stop(ngep, B_FALSE); 2532 ngep->nge_mac_state = NGE_MAC_STOPPED; 2533 2534 rw_exit(ngep->rwlock); 2535 mutex_exit(ngep->genlock); 2536 return (DDI_SUCCESS); 2537 } 2538 2539 /* 2540 * detach(9E) -- Detach a device from the system 2541 */ 2542 static int 2543 nge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2544 { 2545 int i; 2546 nge_t *ngep; 2547 mul_item *p, *nextp; 2548 buff_ring_t *brp; 2549 2550 NGE_GTRACE(("nge_detach($%p, %d)", (void *)devinfo, cmd)); 2551 2552 ngep = ddi_get_driver_private(devinfo); 2553 brp = ngep->buff; 2554 2555 switch (cmd) { 2556 default: 2557 return (DDI_FAILURE); 2558 2559 case DDI_SUSPEND: 2560 /* 2561 * Stop the NIC 2562 * Note: This driver doesn't currently support WOL, but 2563 * should it in the future, it is important to 2564 * make sure the PHY remains powered so that the 2565 * wakeup packet can actually be recieved. 2566 */ 2567 return (nge_suspend(ngep)); 2568 2569 case DDI_DETACH: 2570 break; 2571 } 2572 2573 /* Try to wait all the buffer post to upper layer be released */ 2574 for (i = 0; i < 1000; i++) { 2575 if (brp->rx_hold == 0) 2576 break; 2577 drv_usecwait(1000); 2578 } 2579 2580 /* If there is any posted buffer, reject to detach */ 2581 if (brp->rx_hold != 0) 2582 return (DDI_FAILURE); 2583 2584 /* 2585 * Unregister from the GLD subsystem. This can fail, in 2586 * particular if there are DLPI style-2 streams still open - 2587 * in which case we just return failure without shutting 2588 * down chip operations. 2589 */ 2590 if (mac_unregister(ngep->mh) != DDI_SUCCESS) 2591 return (DDI_FAILURE); 2592 2593 /* 2594 * Recycle the multicast table. mac_unregister() should be called 2595 * before it to ensure the multicast table can be used even if 2596 * mac_unregister() fails. 2597 */ 2598 for (p = ngep->pcur_mulist; p != NULL; p = nextp) { 2599 nextp = p->next; 2600 kmem_free(p, sizeof (mul_item)); 2601 } 2602 ngep->pcur_mulist = NULL; 2603 2604 /* 2605 * All activity stopped, so we can clean up & exit 2606 */ 2607 nge_unattach(ngep); 2608 return (DDI_SUCCESS); 2609 } 2610 2611 2612 /* 2613 * ========== Module Loading Data & Entry Points ========== 2614 */ 2615 2616 DDI_DEFINE_STREAM_OPS(nge_dev_ops, nulldev, nulldev, nge_attach, nge_detach, 2617 nodev, NULL, D_MP, NULL); 2618 2619 2620 static struct modldrv nge_modldrv = { 2621 &mod_driverops, /* Type of module. This one is a driver */ 2622 nge_ident, /* short description */ 2623 &nge_dev_ops /* driver specific ops */ 2624 }; 2625 2626 static struct modlinkage modlinkage = { 2627 MODREV_1, (void *)&nge_modldrv, NULL 2628 }; 2629 2630 2631 int 2632 _info(struct modinfo *modinfop) 2633 { 2634 return (mod_info(&modlinkage, modinfop)); 2635 } 2636 2637 int 2638 _init(void) 2639 { 2640 int status; 2641 2642 mac_init_ops(&nge_dev_ops, "nge"); 2643 status = mod_install(&modlinkage); 2644 if (status != DDI_SUCCESS) 2645 mac_fini_ops(&nge_dev_ops); 2646 else 2647 mutex_init(nge_log_mutex, NULL, MUTEX_DRIVER, NULL); 2648 2649 return (status); 2650 } 2651 2652 int 2653 _fini(void) 2654 { 2655 int status; 2656 2657 status = mod_remove(&modlinkage); 2658 if (status == DDI_SUCCESS) { 2659 mac_fini_ops(&nge_dev_ops); 2660 mutex_destroy(nge_log_mutex); 2661 } 2662 2663 return (status); 2664 } 2665 2666 /* 2667 * ============ Init MSI/Fixed/SoftInterrupt routines ============== 2668 */ 2669 2670 /* 2671 * Register interrupts and initialize each mutex and condition variables 2672 */ 2673 2674 static int 2675 nge_register_intrs_and_init_locks(nge_t *ngep) 2676 { 2677 int err; 2678 int intr_types; 2679 uint_t soft_prip; 2680 nge_msi_mask msi_mask; 2681 nge_msi_map0_vec map0_vec; 2682 nge_msi_map1_vec map1_vec; 2683 2684 /* 2685 * Add the softint handlers: 2686 * 2687 * Both of these handlers are used to avoid restrictions on the 2688 * context and/or mutexes required for some operations. In 2689 * particular, the hardware interrupt handler and its subfunctions 2690 * can detect a number of conditions that we don't want to handle 2691 * in that context or with that set of mutexes held. So, these 2692 * softints are triggered instead: 2693 * 2694 * the <resched> softint is triggered if if we have previously 2695 * had to refuse to send a packet because of resource shortage 2696 * (we've run out of transmit buffers), but the send completion 2697 * interrupt handler has now detected that more buffers have 2698 * become available. Its only purpose is to call gld_sched() 2699 * to retry the pending transmits (we're not allowed to hold 2700 * driver-defined mutexes across gld_sched()). 2701 * 2702 * the <factotum> is triggered if the h/w interrupt handler 2703 * sees the <link state changed> or <error> bits in the status 2704 * block. It's also triggered periodically to poll the link 2705 * state, just in case we aren't getting link status change 2706 * interrupts ... 2707 */ 2708 err = ddi_intr_add_softint(ngep->devinfo, &ngep->resched_hdl, 2709 DDI_INTR_SOFTPRI_MIN, nge_reschedule, (caddr_t)ngep); 2710 if (err != DDI_SUCCESS) { 2711 nge_problem(ngep, 2712 "nge_attach: add nge_reschedule softintr failed"); 2713 2714 return (DDI_FAILURE); 2715 } 2716 ngep->progress |= PROGRESS_RESCHED; 2717 err = ddi_intr_add_softint(ngep->devinfo, &ngep->factotum_hdl, 2718 DDI_INTR_SOFTPRI_MIN, nge_chip_factotum, (caddr_t)ngep); 2719 if (err != DDI_SUCCESS) { 2720 nge_problem(ngep, 2721 "nge_attach: add nge_chip_factotum softintr failed!"); 2722 2723 return (DDI_FAILURE); 2724 } 2725 if (ddi_intr_get_softint_pri(ngep->factotum_hdl, &soft_prip) 2726 != DDI_SUCCESS) { 2727 nge_problem(ngep, "nge_attach: get softintr priority failed\n"); 2728 2729 return (DDI_FAILURE); 2730 } 2731 ngep->soft_pri = soft_prip; 2732 2733 ngep->progress |= PROGRESS_FACTOTUM; 2734 /* Get supported interrupt types */ 2735 if (ddi_intr_get_supported_types(ngep->devinfo, &intr_types) 2736 != DDI_SUCCESS) { 2737 nge_error(ngep, "ddi_intr_get_supported_types failed\n"); 2738 2739 return (DDI_FAILURE); 2740 } 2741 2742 NGE_DEBUG(("ddi_intr_get_supported_types() returned: %x", 2743 intr_types)); 2744 2745 if ((intr_types & DDI_INTR_TYPE_MSI) && nge_enable_msi) { 2746 2747 /* MSI Configurations for mcp55 chipset */ 2748 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 2749 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 2750 2751 2752 /* Enable the 8 vectors */ 2753 msi_mask.msi_mask_val = 2754 nge_reg_get32(ngep, NGE_MSI_MASK); 2755 msi_mask.msi_msk_bits.vec0 = NGE_SET; 2756 msi_mask.msi_msk_bits.vec1 = NGE_SET; 2757 msi_mask.msi_msk_bits.vec2 = NGE_SET; 2758 msi_mask.msi_msk_bits.vec3 = NGE_SET; 2759 msi_mask.msi_msk_bits.vec4 = NGE_SET; 2760 msi_mask.msi_msk_bits.vec5 = NGE_SET; 2761 msi_mask.msi_msk_bits.vec6 = NGE_SET; 2762 msi_mask.msi_msk_bits.vec7 = NGE_SET; 2763 nge_reg_put32(ngep, NGE_MSI_MASK, 2764 msi_mask.msi_mask_val); 2765 2766 /* 2767 * Remapping the MSI MAP0 and MAP1. MCP55 2768 * is default mapping all the interrupt to 0 vector. 2769 * Software needs to remapping this. 2770 * This mapping is same as CK804. 2771 */ 2772 map0_vec.msi_map0_val = 2773 nge_reg_get32(ngep, NGE_MSI_MAP0); 2774 map1_vec.msi_map1_val = 2775 nge_reg_get32(ngep, NGE_MSI_MAP1); 2776 map0_vec.vecs_bits.reint_vec = 0; 2777 map0_vec.vecs_bits.rcint_vec = 0; 2778 map0_vec.vecs_bits.miss_vec = 3; 2779 map0_vec.vecs_bits.teint_vec = 5; 2780 map0_vec.vecs_bits.tcint_vec = 5; 2781 map0_vec.vecs_bits.stint_vec = 2; 2782 map0_vec.vecs_bits.mint_vec = 6; 2783 map0_vec.vecs_bits.rfint_vec = 0; 2784 map1_vec.vecs_bits.tfint_vec = 5; 2785 map1_vec.vecs_bits.feint_vec = 6; 2786 map1_vec.vecs_bits.resv8_11 = 3; 2787 map1_vec.vecs_bits.resv12_15 = 1; 2788 map1_vec.vecs_bits.resv16_19 = 0; 2789 map1_vec.vecs_bits.resv20_23 = 7; 2790 map1_vec.vecs_bits.resv24_31 = 0xff; 2791 nge_reg_put32(ngep, NGE_MSI_MAP0, 2792 map0_vec.msi_map0_val); 2793 nge_reg_put32(ngep, NGE_MSI_MAP1, 2794 map1_vec.msi_map1_val); 2795 } 2796 if (nge_add_intrs(ngep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) { 2797 NGE_DEBUG(("MSI registration failed, " 2798 "trying FIXED interrupt type\n")); 2799 } else { 2800 nge_log(ngep, "Using MSI interrupt type\n"); 2801 2802 ngep->intr_type = DDI_INTR_TYPE_MSI; 2803 ngep->progress |= PROGRESS_SWINT; 2804 } 2805 } 2806 2807 if (!(ngep->progress & PROGRESS_SWINT) && 2808 (intr_types & DDI_INTR_TYPE_FIXED)) { 2809 if (nge_add_intrs(ngep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) { 2810 nge_error(ngep, "FIXED interrupt " 2811 "registration failed\n"); 2812 2813 return (DDI_FAILURE); 2814 } 2815 2816 nge_log(ngep, "Using FIXED interrupt type\n"); 2817 2818 ngep->intr_type = DDI_INTR_TYPE_FIXED; 2819 ngep->progress |= PROGRESS_SWINT; 2820 } 2821 2822 2823 if (!(ngep->progress & PROGRESS_SWINT)) { 2824 nge_error(ngep, "No interrupts registered\n"); 2825 2826 return (DDI_FAILURE); 2827 } 2828 mutex_init(ngep->genlock, NULL, MUTEX_DRIVER, 2829 DDI_INTR_PRI(ngep->intr_pri)); 2830 mutex_init(ngep->softlock, NULL, MUTEX_DRIVER, 2831 DDI_INTR_PRI(ngep->soft_pri)); 2832 rw_init(ngep->rwlock, NULL, RW_DRIVER, 2833 DDI_INTR_PRI(ngep->intr_pri)); 2834 2835 return (DDI_SUCCESS); 2836 } 2837 2838 /* 2839 * nge_add_intrs: 2840 * 2841 * Register FIXED or MSI interrupts. 2842 */ 2843 static int 2844 nge_add_intrs(nge_t *ngep, int intr_type) 2845 { 2846 dev_info_t *dip = ngep->devinfo; 2847 int avail, actual, intr_size, count = 0; 2848 int i, flag, ret; 2849 2850 NGE_DEBUG(("nge_add_intrs: interrupt type 0x%x\n", intr_type)); 2851 2852 /* Get number of interrupts */ 2853 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 2854 if ((ret != DDI_SUCCESS) || (count == 0)) { 2855 nge_error(ngep, "ddi_intr_get_nintrs() failure, ret: %d, " 2856 "count: %d", ret, count); 2857 2858 return (DDI_FAILURE); 2859 } 2860 2861 /* Get number of available interrupts */ 2862 ret = ddi_intr_get_navail(dip, intr_type, &avail); 2863 if ((ret != DDI_SUCCESS) || (avail == 0)) { 2864 nge_error(ngep, "ddi_intr_get_navail() failure, " 2865 "ret: %d, avail: %d\n", ret, avail); 2866 2867 return (DDI_FAILURE); 2868 } 2869 2870 if (avail < count) { 2871 NGE_DEBUG(("nitrs() returned %d, navail returned %d\n", 2872 count, avail)); 2873 } 2874 flag = DDI_INTR_ALLOC_NORMAL; 2875 2876 /* Allocate an array of interrupt handles */ 2877 intr_size = count * sizeof (ddi_intr_handle_t); 2878 ngep->htable = kmem_alloc(intr_size, KM_SLEEP); 2879 2880 /* Call ddi_intr_alloc() */ 2881 ret = ddi_intr_alloc(dip, ngep->htable, intr_type, 0, 2882 count, &actual, flag); 2883 2884 if ((ret != DDI_SUCCESS) || (actual == 0)) { 2885 nge_error(ngep, "ddi_intr_alloc() failed %d\n", ret); 2886 2887 kmem_free(ngep->htable, intr_size); 2888 return (DDI_FAILURE); 2889 } 2890 2891 if (actual < count) { 2892 NGE_DEBUG(("Requested: %d, Received: %d\n", 2893 count, actual)); 2894 } 2895 2896 ngep->intr_actual_cnt = actual; 2897 ngep->intr_req_cnt = count; 2898 2899 /* 2900 * Get priority for first msi, assume remaining are all the same 2901 */ 2902 if ((ret = ddi_intr_get_pri(ngep->htable[0], &ngep->intr_pri)) != 2903 DDI_SUCCESS) { 2904 nge_error(ngep, "ddi_intr_get_pri() failed %d\n", ret); 2905 2906 /* Free already allocated intr */ 2907 for (i = 0; i < actual; i++) { 2908 (void) ddi_intr_free(ngep->htable[i]); 2909 } 2910 2911 kmem_free(ngep->htable, intr_size); 2912 2913 return (DDI_FAILURE); 2914 } 2915 /* Test for high level mutex */ 2916 if (ngep->intr_pri >= ddi_intr_get_hilevel_pri()) { 2917 nge_error(ngep, "nge_add_intrs:" 2918 "Hi level interrupt not supported"); 2919 2920 for (i = 0; i < actual; i++) 2921 (void) ddi_intr_free(ngep->htable[i]); 2922 2923 kmem_free(ngep->htable, intr_size); 2924 2925 return (DDI_FAILURE); 2926 } 2927 2928 2929 /* Call ddi_intr_add_handler() */ 2930 for (i = 0; i < actual; i++) { 2931 if ((ret = ddi_intr_add_handler(ngep->htable[i], nge_chip_intr, 2932 (caddr_t)ngep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 2933 nge_error(ngep, "ddi_intr_add_handler() " 2934 "failed %d\n", ret); 2935 2936 /* Free already allocated intr */ 2937 for (i = 0; i < actual; i++) { 2938 (void) ddi_intr_free(ngep->htable[i]); 2939 } 2940 2941 kmem_free(ngep->htable, intr_size); 2942 2943 return (DDI_FAILURE); 2944 } 2945 } 2946 2947 if ((ret = ddi_intr_get_cap(ngep->htable[0], &ngep->intr_cap)) 2948 != DDI_SUCCESS) { 2949 nge_error(ngep, "ddi_intr_get_cap() failed %d\n", ret); 2950 2951 for (i = 0; i < actual; i++) { 2952 (void) ddi_intr_remove_handler(ngep->htable[i]); 2953 (void) ddi_intr_free(ngep->htable[i]); 2954 } 2955 2956 kmem_free(ngep->htable, intr_size); 2957 2958 return (DDI_FAILURE); 2959 } 2960 2961 return (DDI_SUCCESS); 2962 } 2963 2964 /* 2965 * nge_rem_intrs: 2966 * 2967 * Unregister FIXED or MSI interrupts 2968 */ 2969 static void 2970 nge_rem_intrs(nge_t *ngep) 2971 { 2972 int i; 2973 2974 NGE_DEBUG(("nge_rem_intrs\n")); 2975 2976 /* Disable all interrupts */ 2977 if (ngep->intr_cap & DDI_INTR_FLAG_BLOCK) { 2978 /* Call ddi_intr_block_disable() */ 2979 (void) ddi_intr_block_disable(ngep->htable, 2980 ngep->intr_actual_cnt); 2981 } else { 2982 for (i = 0; i < ngep->intr_actual_cnt; i++) { 2983 (void) ddi_intr_disable(ngep->htable[i]); 2984 } 2985 } 2986 2987 /* Call ddi_intr_remove_handler() */ 2988 for (i = 0; i < ngep->intr_actual_cnt; i++) { 2989 (void) ddi_intr_remove_handler(ngep->htable[i]); 2990 (void) ddi_intr_free(ngep->htable[i]); 2991 } 2992 2993 kmem_free(ngep->htable, 2994 ngep->intr_req_cnt * sizeof (ddi_intr_handle_t)); 2995 } 2996