1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * This file may contain confidential information of Nvidia 8 * and should not be distributed in source form without approval 9 * from Sun Legal. 10 */ 11 12 #ifndef _SYS_NGE_CHIP_H 13 #define _SYS_NGE_CHIP_H 14 15 #pragma ident "%Z%%M% %I% %E% SMI" 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 #include "nge.h" 22 23 #define VENDOR_ID_NVIDIA 0x10de 24 25 #define DEVICE_ID_MCP04_37 0x37 26 #define DEVICE_ID_MCP04_38 0x38 27 #define DEVICE_ID_CK804_56 0x56 28 #define DEVICE_ID_CK804_57 0x57 29 #define DEVICE_ID_MCP51_269 0x269 30 #define DEVICE_ID_MCP51_268 0x268 31 #define DEVICE_ID_MCP55_373 0x373 32 #define DEVICE_ID_MCP55_372 0x372 33 #define DEVICE_ID_MCP61_3EE 0x3ee 34 #define DEVICE_ID_MCP61_3EF 0x3ef 35 #define DEVICE_ID_NF3_E6 0xe6 36 #define DEVICE_ID_NF3_DF 0xdf 37 38 /* Private PCI configuration register for bus config of ck804/mcp55 */ 39 #define PCI_CONF_HT_INTERNAL 0x4c 40 41 typedef union _nge_interbus_conf { 42 uint32_t conf_val; 43 struct { 44 uint32_t unit_id:5; 45 uint32_t resv5_23:19; 46 uint32_t aux_val:3; 47 uint32_t resv27:1; 48 uint32_t msi_off:1; 49 uint32_t msix_off:1; /* mcp55 only */ 50 uint32_t resv30_31:2; 51 } conf_bits; 52 } nge_interbus_conf; 53 54 /* Private PCI configuration register for MSI mask of mcp55 */ 55 #define PCI_CONF_HT_MSI_MASK 0x60 56 57 typedef union _nge_msi_mask_conf { 58 uint32_t msi_mask_conf_val; 59 struct { 60 uint32_t vec0_off:1; 61 uint32_t vec1_off:1; 62 uint32_t vec2_off:1; 63 uint32_t vec3_off:1; 64 uint32_t vec4_off:1; 65 uint32_t vec5_off:1; 66 uint32_t vec6_off:1; 67 uint32_t vec7_off:1; 68 uint32_t resv8_31:24; 69 } msi_mask_bits; 70 } nge_msi_mask_conf; 71 72 /* Private PCI configuration register for MSI map capability of mcp55 */ 73 #define PCI_CONF_HT_MSI_MAP_CAP 0x6c 74 75 typedef union _nge_msi_map_cap_conf { 76 uint32_t msi_map_cap_conf_val; 77 struct { 78 uint32_t cap_id:8; 79 uint32_t next_ptr:8; 80 uint32_t map_en:1; 81 uint32_t map_fixed:1; 82 uint32_t resv18_26:9; 83 uint32_t cap_type:5; 84 } map_cap_conf_bits; 85 } nge_msi_map_cap_conf; 86 87 /* 88 * Master interrupt 89 */ 90 #define NGE_INTR_SRC 0x000 91 #define INTR_SRC_ALL 0x00007fff 92 typedef union _nge_intr_src { 93 uint32_t intr_val; 94 struct { 95 uint32_t reint:1; 96 uint32_t rcint:1; 97 uint32_t miss:1; 98 uint32_t teint:1; 99 uint32_t tcint:1; 100 uint32_t stint:1; 101 uint32_t mint:1; 102 uint32_t rfint:1; 103 uint32_t tfint:1; 104 uint32_t feint:1; 105 uint32_t resv10:1; 106 uint32_t resv11:1; 107 uint32_t resv12:1; 108 uint32_t resv13:1; 109 uint32_t phyint:1; 110 uint32_t resv15_31:17; 111 } int_bits; 112 } nge_intr_src; 113 114 /* 115 * Master interrupt Mask 116 */ 117 #define NGE_INTR_MASK 0x004 118 #define NGE_INTR_ALL_EN 0x00007fff 119 typedef union _nge_intr_mask { 120 uint32_t mask_val; 121 struct { 122 uint32_t reint:1; 123 uint32_t rcint:1; 124 uint32_t miss:1; 125 uint32_t teint:1; 126 uint32_t tcint:1; 127 uint32_t stint:1; 128 uint32_t mint:1; 129 uint32_t rfint:1; 130 uint32_t tfint:1; 131 uint32_t feint:1; 132 uint32_t resv10:1; 133 uint32_t resv11:1; 134 uint32_t resv12:1; 135 uint32_t resv13:1; 136 uint32_t phyint:1; 137 uint32_t resv15_31:17; 138 } mask_bits; 139 } nge_intr_mask; 140 141 /* 142 * Software timer control register 143 */ 144 #define NGE_SWTR_CNTL 0x008 145 typedef union _nge_swtr_cntl { 146 uint8_t ctrl_val; 147 struct { 148 uint8_t stren:1; 149 uint8_t sten:1; 150 uint8_t resv2_7:6; 151 } cntl_bits; 152 } nge_swtr_cntl; 153 154 /* 155 * Software Timer Interval 156 */ 157 #define NGE_SWTR_ITC 0x00c 158 #define POLL_LWATER 0x10 159 #define INTR_HWATER 0x5 160 #define SWTR_ITC 0x10 161 typedef union _nge_itc { 162 uint32_t itc_val; 163 struct { 164 uint32_t sw_intv:16; 165 uint32_t sw_cur_val:16; 166 } itc_bits; 167 } nge_itc; 168 169 /* 170 * Fatal error register 171 */ 172 #define NGE_REG010 0x010 173 typedef union _nge_reg010 { 174 uint32_t reg010_val; 175 struct { 176 uint32_t resv0:1; 177 uint32_t resv1:1; 178 uint32_t resv2:1; 179 uint32_t resv3:1; 180 uint32_t resv4:1; 181 uint32_t resv5:1; 182 uint32_t resv6:1; 183 uint32_t resv7:1; 184 uint32_t resv8:1; 185 uint32_t resv9:1; 186 uint32_t resv10:1; 187 uint32_t resv11_31:21; 188 } reg010_bits; 189 } nge_reg010; 190 191 /* 192 * MSI vector map register 0 193 */ 194 #define NGE_MSI_MAP0 0x020 195 typedef union _nge_msi_map0_vec { 196 uint32_t msi_map0_val; 197 struct { 198 uint32_t reint_vec:4; 199 uint32_t rcint_vec:4; 200 uint32_t miss_vec:4; 201 uint32_t teint_vec:4; 202 uint32_t tcint_vec:4; 203 uint32_t stint_vec:4; 204 uint32_t mint_vec:4; 205 uint32_t rfint_vec:4; 206 } vecs_bits; 207 } nge_msi_map0_vec; 208 209 /* 210 * MSI vector map register 1 211 */ 212 #define NGE_MSI_MAP1 0x024 213 typedef union _nge_msi_map1_vec { 214 uint32_t msi_map1_val; 215 struct { 216 uint32_t tfint_vec:4; 217 uint32_t feint_vec:4; 218 uint32_t resv8_11:4; 219 uint32_t resv12_15:4; 220 uint32_t resv16_19:4; 221 uint32_t resv20_23:4; 222 uint32_t resv24_31:8; 223 } vecs_bits; 224 } nge_msi_map1_vec; 225 226 227 /* 228 * MSI vector map register 2 229 */ 230 #define NGE_MSI_MAP2 0x028 231 232 /* 233 * MSI vector map register 2 234 */ 235 #define NGE_MSI_MAP3 0x02c 236 237 /* 238 * MSI mask register for mcp55 239 */ 240 #define NGE_MSI_MASK 0x30 241 typedef union _nge_msi_mask { 242 uint32_t msi_mask_val; 243 struct { 244 uint32_t vec0:1; 245 uint32_t vec1:1; 246 uint32_t vec2:1; 247 uint32_t vec3:1; 248 uint32_t vec4:1; 249 uint32_t vec5:1; 250 uint32_t vec6:1; 251 uint32_t vec7:1; 252 uint32_t resv8_31:24; 253 }msi_msk_bits; 254 }nge_msi_mask; 255 256 /* 257 * Software misc register for mcp51 258 */ 259 #define NGE_SOFT_MISC 0x034 260 typedef union _nge_soft_misc { 261 uint32_t misc_val; 262 struct { 263 uint32_t rx_clk_vx_rst:1; 264 uint32_t tx_clk_vx_rst:1; 265 uint32_t clk12m_vx_rst:1; 266 uint32_t fpci_clk_vx_rst:1; 267 uint32_t rx_clk_vc_rst:1; 268 uint32_t tx_clk_vc_rst:1; 269 uint32_t fs_clk_vc_rst:1; 270 uint32_t rst_ex_m2pintf:1; 271 uint32_t resv8_31:24; 272 } misc_bits; 273 } nge_soft_misc; 274 275 /* 276 * DMA configuration 277 */ 278 #define NGE_DMA_CFG 0x040 279 typedef union _nge_dma_cfg { 280 uint32_t cfg_val; 281 struct { 282 uint32_t tx_start_pri:3; 283 uint32_t tx_start_pri_flag:1; 284 uint32_t tx_prd_rpri:3; 285 uint32_t tx_prd_rpri_flag:1; 286 uint32_t tx_prd_wpri:3; 287 uint32_t tx_prd_wpri_flag:1; 288 uint32_t rx_start_pri:3; 289 uint32_t rx_start_pri_flag:1; 290 uint32_t rx_prd_rpri:3; 291 uint32_t rx_prd_rpri_flag:1; 292 uint32_t rx_prd_wpri:3; 293 uint32_t rx_prd_wpri_flag:1; 294 uint32_t dma_max_pri:3; 295 uint32_t dma_wrr_disable:1; 296 uint32_t dma_pri_disable:1; 297 } cfg_bits; 298 } nge_dma_cfg; 299 300 /* 301 * Request DMA configuration 302 */ 303 #define NGE_DMA_RCFG 0x044 304 typedef union _nge_dma_rcfg { 305 uint32_t dma_rcfg_val; 306 struct { 307 uint32_t tx_prd_coh_state:2; 308 uint32_t tx_data_coh_state:2; 309 uint32_t rx_prd_coh_state:2; 310 uint32_t rx_data_coh_state:2; 311 uint32_t max_roffset:5; 312 uint32_t resv13_31:19; 313 } rcfg_bis; 314 } nge_dma_rcfg; 315 316 /* 317 * Hot DMA configuration 318 */ 319 #define NGE_DMA_HOT_CFG 0x048 320 typedef union _nge_dma_hcfg { 321 uint32_t dma_hcfg_val; 322 struct { 323 uint32_t resv0_3:4; 324 uint32_t noti_wstart_pri:3; 325 uint32_t noti_wstart_pri_flag:1; 326 uint32_t cmd_rstart_pri:3; 327 uint32_t cmd_rstart_pri_flag:1; 328 uint32_t cmd_wstart_pri:3; 329 uint32_t cmd_wstart_pri_flag:1; 330 uint32_t resv16_31:16; 331 } hcfg_bits; 332 } nge_dma_hcfg; 333 334 /* 335 * PMU control register 0 for mcp51 336 */ 337 #define NGE_PMU_CNTL0 0x060 338 #define NGE_PMU_CORE_SPD10_BUSY 0x8 339 #define NGE_PMU_CORE_SPD10_IDLE 0xB 340 #define NGE_PMU_CORE_SPD100_BUSY 0x4 341 #define NGE_PMU_CORE_SPD100_IDLE 0x7 342 #define NGE_PMU_CORE_SPD1000_BUSY 0x0 343 #define NGE_PMU_CORE_SPD1000_IDLE 0x3 344 345 typedef union _nge_pmu_cntl0 { 346 uint32_t cntl0_val; 347 struct { 348 uint32_t core_spd10_fp:4; 349 uint32_t core_spd10_idle:4; 350 uint32_t core_spd100_fp:4; 351 uint32_t core_spd100_idle:4; 352 uint32_t core_spd1000_fp:4; 353 uint32_t core_spd1000_idle:4; 354 uint32_t core_sts_cur:8; 355 } cntl0_bits; 356 } nge_pmu_cntl0; 357 358 /* 359 * PMU control register 1 for mcp51 360 */ 361 #define NGE_PMU_CNTL1 0x064 362 typedef union _nge_pmu_cntl1 { 363 uint32_t cntl1_val; 364 struct { 365 uint32_t dev_fp:4; 366 uint32_t dev_idle:4; 367 uint32_t resv8_27:20; 368 uint32_t dev_sts_cur:4; 369 } cntl1_bits; 370 } nge_pmu_cntl1; 371 372 /* 373 * PMU control register 2 for mcp51 374 */ 375 #define NGE_PMU_CNTL2 0x068 376 typedef union _nge_pmu_cntl2 { 377 uint32_t cntl2_val; 378 struct { 379 uint32_t core_override:4; 380 uint32_t resv4_7:4; 381 uint32_t dev_override:4; 382 uint32_t resv12_15:4; 383 uint32_t core_override_en:1; 384 uint32_t dev_override_en:1; 385 uint32_t core_enable:1; 386 uint32_t dev_enable:1; 387 uint32_t rx_wake_dis:1; 388 uint32_t cidle_timer:1; 389 uint32_t didle_timer:1; 390 uint32_t resv23_31:9; 391 } cntl2_bits; 392 } nge_pmu_cntl2; 393 394 /* 395 * PMU core idle limit register for mcp51 396 */ 397 #define NGE_PMU_CIDLE_LIMIT 0x06c 398 #define NGE_PMU_CIDLE_LIMIT_DEF 0xffff 399 400 /* 401 * PMU device idle limit register for mcp51 402 */ 403 #define NGE_PMU_DIDLE_LIMIT 0x070 404 #define NGE_PMU_DIDLE_LIMIT_DEF 0xffff 405 406 /* 407 * PMU core idle count value register for mcp51 408 */ 409 #define NGE_PMU_CIDLE_COUNT 0x074 410 #define NGE_PMU_CIDEL_COUNT_DEF 0xffff 411 412 /* 413 * PMU device idle count value register for mcp51 414 */ 415 #define NGE_PMU_DIDLE_COUNT 0x078 416 #define NGE_PMU_DIDEL_COUNT_DEF 0xffff 417 418 /* 419 * Transmit control 420 */ 421 #define NGE_TX_CNTL 0x080 422 typedef union _nge_tx_cntl { 423 uint32_t cntl_val; 424 struct { 425 uint32_t paen:1; /* only for mcp55, otherwise reserve */ 426 uint32_t resv1:1; 427 uint32_t retry_en:1; 428 uint32_t pad_en:1; 429 uint32_t fappend_en:1; 430 uint32_t two_def_en:1; 431 uint32_t resv6_7:2; 432 uint32_t max_retry:4; 433 uint32_t burst_en:1; 434 uint32_t resv13_15:3; 435 uint32_t retry_emask:1; 436 uint32_t exdef_mask:1; 437 uint32_t def_mask:1; 438 uint32_t lcar_mask:1; 439 uint32_t tlcol_mask:1; 440 uint32_t uflo_err_mask:1; 441 uint32_t resv22_23:2; 442 uint32_t jam_seq_en:1; 443 uint32_t resv25_31:7; 444 } cntl_bits; 445 } nge_tx_cntl; 446 447 /* 448 * Transmit enable 449 * Note: for ck804 or mcp51, this is 8-bit register; 450 * for mcp55, it is a 32-bit register. 451 */ 452 #define NGE_TX_EN 0x084 453 typedef union _nge_tx_en { 454 uint8_t val; 455 struct { 456 uint8_t tx_en:1; 457 uint8_t resv1_7:7; 458 } bits; 459 } nge_tx_en; 460 461 /* 462 * Transmit status 463 */ 464 #define NGE_TX_STA 0x088 465 typedef union _nge_tx_sta { 466 uint32_t sta_val; 467 struct { 468 uint32_t tx_chan_sta:1; 469 uint32_t resv1_15:15; 470 uint32_t retry_err:1; 471 uint32_t exdef:1; 472 uint32_t def:1; 473 uint32_t lcar:1; 474 uint32_t tlcol:1; 475 uint32_t uflo:1; 476 uint32_t resv22_31:10; 477 } sta_bits; 478 } nge_tx_sta; 479 480 /* 481 * Receive control 482 */ 483 #define NGE_RX_CNTL0 0x08c 484 typedef union _nge_rx_cntrl0 { 485 uint32_t cntl_val; 486 struct { 487 uint32_t resv0:1; 488 uint32_t padsen:1; 489 uint32_t fcsren:1; 490 uint32_t paen:1; 491 uint32_t lben:1; 492 uint32_t afen:1; 493 uint32_t runten:1; 494 uint32_t brdis:1; 495 uint32_t rdfen:1; 496 uint32_t slfb:1; 497 uint32_t resv10_15:6; 498 uint32_t runtm:1; 499 uint32_t rlcolm:1; 500 uint32_t maxerm:1; 501 uint32_t lferm:1; 502 uint32_t crcm:1; 503 uint32_t ofolm:1; 504 uint32_t framerm:1; 505 uint32_t resv23_31:9; 506 } cntl_bits; 507 } nge_rx_cntrl0; 508 509 /* 510 * Maximum receive Frame size 511 */ 512 #define NGE_RX_CNTL1 0x090 513 typedef union _nge_rx_cntl1 { 514 uint32_t cntl_val; 515 struct { 516 uint32_t length:14; 517 uint32_t resv14_31:18; 518 } cntl_bits; 519 } nge_rx_cntl1; 520 521 /* 522 * Receive enable register 523 * Note: for ck804 and mcp51, this is a 8-bit register; 524 * for mcp55, it is a 32-bit register. 525 */ 526 #define NGE_RX_EN 0x094 527 typedef union _nge_rx_en { 528 uint8_t val; 529 struct { 530 uint8_t rx_en:1; 531 uint8_t resv1_7:7; 532 } bits; 533 } nge_rx_en; 534 535 /* 536 * Receive status register 537 */ 538 #define NGE_RX_STA 0x098 539 typedef union _nge_rx_sta { 540 uint32_t sta_val; 541 struct { 542 uint32_t rx_chan_sta:1; 543 uint32_t resv1_15:15; 544 uint32_t runt_sta:1; 545 uint32_t rlcol_sta:1; 546 uint32_t mlen_err:1; 547 uint32_t lf_err:1; 548 uint32_t crc_err:1; 549 uint32_t ofol_err:1; 550 uint32_t fram_err:1; 551 uint32_t resv23_31:9; 552 } sta_bits; 553 } nge_rx_sta; 554 555 /* 556 * Backoff Control 557 */ 558 #define NGE_BKOFF_CNTL 0x09c 559 #define BKOFF_RSEED 0x8 560 #define BKOFF_SLIM_GMII 0x3ff 561 #define BKOFF_SLIM_MII 0x7f 562 typedef union _nge_bkoff_cntl { 563 uint32_t cntl_val; 564 struct { 565 uint32_t rseed:8; 566 uint32_t sltm:10; 567 uint32_t resv18_30:13; 568 uint32_t leg_bk_en:1; 569 } bkoff_bits; 570 } nge_bkoff_cntl; 571 572 /* 573 * Transmit defferral timing 574 */ 575 #define NGE_TX_DEF 0x0a0 576 #define TX_TIFG_MII 0x15 577 #define TX_IFG_RGMII_1000_FD 0x14 578 #define TX_IFG_RGMII_OTHER 0x16 579 #define TX_IFG2_MII 0x5 580 #define TX_IFG2_RGMII_10_100 0x7 581 #define TX_IFG2_RGMII_1000 0x5 582 #define TX_IFG2_DEFAULT 0X0 583 #define TX_IFG1_DEFAULT 0xf 584 typedef union _nge_tx_def { 585 uint32_t def_val; 586 struct { 587 uint32_t ifg1_def:8; 588 uint32_t ifg2_def:8; 589 uint32_t if_def:8; 590 uint32_t resv24_31:8; 591 } def_bits; 592 } nge_tx_def; 593 594 /* 595 * Receive defferral timing 596 */ 597 #define NGE_RX_DEf 0x0a4 598 #define RX_DEF_DEFAULT 0x16 599 typedef union _nge_rx_def { 600 uint8_t def_val; 601 struct { 602 uint8_t rifg; 603 } def_bits; 604 } nge_rx_def; 605 606 /* 607 * Low 32 bit unicast address 608 */ 609 #define NGE_UNI_ADDR0 0x0a8 610 union { 611 uint32_t addr_val; 612 struct { 613 uint32_t addr; 614 } addr_bits; 615 } nge_uni_addr0; 616 617 /* 618 * High 32 bit unicast address 619 */ 620 #define NGE_UNI_ADDR1 0x0ac 621 typedef union _nge_uni_addr1 { 622 uint32_t addr_val; 623 struct { 624 uint32_t addr:16; 625 uint32_t resv16_31:16; 626 } addr_bits; 627 } nge_uni_addr1; 628 629 /* 630 * Low 32 bit multicast address 631 */ 632 #define NGE_MUL_ADDR0 0x0b0 633 union { 634 uint32_t addr_val; 635 struct { 636 uint32_t addr; 637 }addr_bits; 638 }nge_mul_addr0; 639 640 /* 641 * High 32 bit multicast address 642 */ 643 #define NGE_MUL_ADDR1 0x0b4 644 typedef union _nge_mul_addr1 { 645 uint32_t addr_val; 646 struct { 647 uint32_t addr:16; 648 uint32_t resv16_31:16; 649 }addr_bits; 650 }nge_mul_addr1; 651 652 /* 653 * Low 32 bit multicast mask 654 */ 655 #define NGE_MUL_MASK 0x0b8 656 union { 657 uint32_t mask_val; 658 struct { 659 uint32_t mask; 660 } mask_bits; 661 } nge_mul_mask0; 662 663 /* 664 * High 32 bit multicast mask 665 */ 666 #define NGE_MUL_MASK1 0x0bc 667 union { 668 uint32_t mask_val; 669 struct { 670 uint32_t mask:16; 671 uint32_t resv16_31:16; 672 } mask_bits; 673 } nge_mul_mask1; 674 675 /* 676 * Mac-to Phy Interface 677 */ 678 #define NGE_MAC2PHY 0x0c0 679 #define low_speed 0x0 680 #define fast_speed 0x1 681 #define giga_speed 0x2 682 #define err_speed 0x4 683 #define MII_IN 0x0 684 #define RGMII_IN 0x1 685 #define ERR_IN1 0x3 686 #define ERR_IN2 0x4 687 typedef union _nge_mac2phy { 688 uint32_t m2p_val; 689 struct { 690 uint32_t speed:2; 691 uint32_t resv2_7:6; 692 uint32_t hdup_en:1; 693 uint32_t resv9:1; 694 uint32_t phyintr:1; /* for mcp55 only */ 695 uint32_t phyintrlvl:1; /* for mcp55 only */ 696 uint32_t resv12_27:16; 697 uint32_t in_type:2; 698 uint32_t resv30_31:2; 699 } m2p_bits; 700 } nge_mac2phy; 701 702 /* 703 * Transmit Descriptor Ring address 704 */ 705 #define NGE_TX_DADR 0x100 706 typedef union _nge_tx_addr { 707 uint32_t addr_val; 708 struct { 709 uint32_t resv0_2:3; 710 uint32_t addr:29; 711 } addr_bits; 712 } nge_tx_addr; 713 714 /* 715 * Receive Descriptor Ring address 716 */ 717 #define NGE_RX_DADR 0x104 718 typedef union _nge_rx_addr { 719 uint32_t addr_val; 720 struct { 721 uint32_t resv0_2:3; 722 uint32_t addr:29; 723 } addr_bits; 724 } nge_rx_addr; 725 726 /* 727 * Rx/tx descriptor ring leng 728 * Note: for mcp55, tdlen/rdlen are 14 bit. 729 */ 730 #define NGE_RXTX_DLEN 0x108 731 typedef union _nge_rxtx_dlen { 732 uint32_t dlen_val; 733 struct { 734 uint32_t tdlen:14; 735 uint32_t resv14_15:2; 736 uint32_t rdlen:14; 737 uint32_t resv30_31:2; 738 } dlen_bits; 739 } nge_rxtx_dlen; 740 741 /* 742 * Transmit polling register 743 */ 744 #define NGE_TX_POLL 0x10c 745 #define TX_POLL_INTV_1G 10 746 #define TX_POLL_INTV_100M 100 747 #define TX_POLL_INTV_10M 1000 748 749 typedef union _nge_tx_poll { 750 uint32_t poll_val; 751 struct { 752 uint32_t tpi:16; 753 uint32_t tpen:1; 754 uint32_t resv17_31:15; 755 } poll_bits; 756 } nge_tx_poll; 757 758 /* 759 * Receive polling register 760 */ 761 #define NGE_RX_POLL 0x110 762 #define RX_POLL_INTV_1G 10 763 #define RX_POLL_INTV_100M 100 764 #define RX_POLL_INTV_10M 1000 765 typedef union _nge_rx_poll { 766 uint32_t poll_val; 767 struct { 768 uint32_t rpi:16; 769 uint32_t rpen:1; 770 uint32_t resv17_31:15; 771 } poll_bits; 772 } nge_rx_poll; 773 774 /* 775 * Transmit polling count 776 */ 777 #define NGE_TX_PCNT 0x114 778 union { 779 uint32_t cnt_val; 780 struct { 781 uint32_t pcnt:32; 782 } cnt_bits; 783 } nge_tx_pcnt; 784 785 /* 786 * Receive polling count 787 */ 788 #define NGE_RX_PCNT 0x118 789 union { 790 uint32_t cnt_val; 791 struct { 792 uint32_t pcnt:32; 793 } cnt_bits; 794 } nge_rx_pcnt; 795 796 797 /* 798 * Current tx's descriptor address 799 */ 800 #define NGE_TX_CUR_DADR 0x11c 801 union { 802 uint32_t addr_val; 803 struct { 804 uint32_t resv0_2:3; 805 uint32_t addr:29; 806 } addr_bits; 807 } nge_tx_cur_addr; 808 809 /* 810 * Current rx's descriptor address 811 */ 812 #define NGE_RX_CUR_DADR 0x120 813 union { 814 uint32_t addr_val; 815 struct { 816 uint32_t resv0_2:3; 817 uint32_t addr:29; 818 } addr_bits; 819 } nge_rx_cur_addr; 820 821 /* 822 * Current tx's data buffer address 823 */ 824 #define NGE_TX_CUR_PRD0 0x124 825 union { 826 uint32_t prd0_val; 827 struct { 828 uint32_t prd0:32; 829 } prd0_bits; 830 } nge_tx_cur_prd0; 831 832 /* 833 * Current tx's data buffer status 834 */ 835 #define NGE_TX_CUR_PRD1 0x128 836 union { 837 uint32_t prd1_val; 838 struct { 839 uint32_t rebytes:16; 840 uint32_t status:16; 841 } prd1_bits; 842 } nge_tx_cur_prd1; 843 844 /* 845 * Current rx's data buffer address 846 */ 847 #define NGE_RX_CUR_PRD0 0x12c 848 union { 849 uint32_t prd0_val; 850 struct { 851 uint32_t prd0:32; 852 }prd0_bits; 853 }nge_rx_cur_prd0; 854 855 /* 856 * Current rx's data buffer status 857 */ 858 #define NGE_RX_CUR_PRD1 0x130 859 860 /* 861 * Next tx's descriptor address 862 */ 863 #define NGE_TX_NXT_DADR 0x134 864 union { 865 uint32_t dadr_val; 866 struct { 867 uint32_t addr:32; 868 }addr_bits; 869 }nge_tx_nxt_dadr; 870 871 /* 872 * Next rx's descriptor address 873 */ 874 #define NGE_RX_NXT_DADR 0x138 875 union { 876 uint32_t dadr_val; 877 struct { 878 uint32_t addr:32; 879 } addr_bits; 880 } nge_rx_nxt_dadr; 881 882 /* 883 * Transmit fifo watermark 884 */ 885 #define NGE_TX_FIFO_WM 0x13c 886 #define TX_FIFO_TBFW 0 887 #define TX_FIFO_NOB_WM_MII 1 888 #define TX_FIFO_NOB_WM_GMII 8 889 #define TX_FIFO_DATA_LWM 0x20 890 #define TX_FIFO_PRD_LWM 0x8 891 #define TX_FIFO_PRD_HWM 0x38 892 typedef union _nge_tx_fifo_wm { 893 uint32_t wm_val; 894 struct { 895 uint32_t data_lwm:9; 896 uint32_t resv8_11:3; 897 uint32_t prd_lwm:6; 898 uint32_t uprd_hwm:6; 899 uint32_t nbfb_wm:4; 900 uint32_t fb_wm:4; 901 } wm_bits; 902 } nge_tx_fifo_wm; 903 904 /* 905 * Receive fifo watermark 906 */ 907 #define NGE_RX_FIFO_WM 0x140 908 typedef union _nge_rx_fifo_wm { 909 uint32_t wm_val; 910 struct { 911 uint32_t data_hwm:9; 912 uint32_t resv9_11:3; 913 uint32_t prd_lwm:4; 914 uint32_t resv16_17:2; 915 uint32_t prd_hwm:4; 916 uint32_t resv22_31:10; 917 } wm_bits; 918 } nge_rx_fifo_wm; 919 920 /* 921 * Chip mode control 922 */ 923 #define NGE_MODE_CNTL 0x144 924 #define DESC_MCP1 0x0 925 #define DESC_OFFLOAD 0x1 926 #define DESC_HOT 0x2 927 #define DESC_RESV 0x3 928 #define MACHINE_BUSY 0x0 929 #define MACHINE_IDLE 0x1 930 typedef union _nge_mode_cntl { 931 uint32_t mode_val; 932 struct { 933 uint32_t txdm:1; 934 uint32_t rxdm:1; 935 uint32_t dma_dis:1; 936 uint32_t dma_status:1; 937 uint32_t bm_reset:1; 938 uint32_t resv5:1; 939 uint32_t vlan_strip:1; /* mcp55 chip only */ 940 uint32_t vlan_ins:1; /* mcp55 chip only */ 941 uint32_t desc_type:2; 942 uint32_t rx_sum_en:1; 943 uint32_t tx_prd_cu_en:1; 944 uint32_t w64_dis:1; 945 uint32_t tx_rcom_en:1; 946 uint32_t rx_filter_en:1; 947 uint32_t resv15:1; 948 uint32_t resv16:1; /* ck804 and mcp51 only */ 949 uint32_t resv17:1; /* ck804 and mcp51 only */ 950 uint32_t resv18:1; /* ck804 and mcp51 only */ 951 uint32_t resv19_21:3; 952 uint32_t tx_fetch_prd:1; /* mcp51/mcp55 only */ 953 uint32_t rx_fetch_prd:1; /* mcp51/mcp55 only */ 954 uint32_t resv24_29:6; 955 uint32_t rx_status:1; 956 uint32_t tx_status:1; 957 } mode_bits; 958 } nge_mode_cntl; 959 960 #define NGE_TX_DADR_HI 0x148 961 #define NGE_RX_DADR_HI 0x14c 962 963 /* 964 * Mii interrupt register 965 * Note: for mcp55, this is a 32-bit register. 966 */ 967 #define NGE_MINTR_SRC 0x180 968 typedef union _nge_mintr_src { 969 uint8_t src_val; 970 struct { 971 uint8_t mrei:1; 972 uint8_t mcc2:1; 973 uint8_t mcc1:1; 974 uint8_t mapi:1; 975 uint8_t mpdi:1; 976 uint8_t resv5_7:3; 977 } src_bits; 978 } nge_mintr_src; 979 980 /* 981 * Mii interrupt mask 982 * Note: for mcp55, this is a 32-bit register. 983 */ 984 #define NGE_MINTR_MASK 0x184 985 typedef union _nge_mintr_mask { 986 uint8_t mask_val; 987 struct { 988 uint8_t mrei:1; 989 uint8_t mcc2:1; 990 uint8_t mcc1:1; 991 uint8_t mapi:1; 992 uint8_t mpdi:1; 993 uint8_t resv5_7:3; 994 } mask_bits; 995 } nge_mintr_mask; 996 997 /* 998 * Mii control and status 999 */ 1000 #define NGE_MII_CS 0x188 1001 #define MII_POLL_INTV 0x4 1002 typedef union _nge_mii_cs { 1003 uint32_t cs_val; 1004 struct { 1005 uint32_t excap:1; 1006 uint32_t jab_dec:1; 1007 uint32_t lk_up:1; 1008 uint32_t ana_cap:1; 1009 uint32_t rfault:1; 1010 uint32_t auto_neg:1; 1011 uint32_t mfps:1; 1012 uint32_t resv7:1; 1013 uint32_t exst:1; 1014 uint32_t hdup_100m_t2:1; 1015 uint32_t fdup_100m_t2:1; 1016 uint32_t hdup_10m:1; 1017 uint32_t fdup_10m:1; 1018 uint32_t hdup_100m_x:1; 1019 uint32_t fdup_100m_x:1; 1020 uint32_t cap_100m_t4:1; 1021 uint32_t ap_intv:4; 1022 uint32_t ap_en:1; 1023 uint32_t resv21_23:3; 1024 uint32_t ap_paddr:5; 1025 uint32_t resv29_31:3; 1026 } cs_bits; 1027 } nge_mii_cs; 1028 1029 /* 1030 * Mii Clock timer register 1031 */ 1032 #define NGE_MII_TM 0x18c 1033 typedef union _nge_mii_tm { 1034 uint16_t tm_val; 1035 struct { 1036 uint16_t timer_interv:8; 1037 uint16_t timer_en:1; 1038 uint16_t resv9_14:6; 1039 uint16_t timer_status:1; 1040 } tm_bits; 1041 } nge_mii_tm; 1042 1043 /* 1044 * Mdio address 1045 */ 1046 #define NGE_MDIO_ADR 0x190 1047 typedef union _nge_mdio_adr { 1048 uint16_t adr_val; 1049 struct { 1050 uint16_t phy_reg:5; 1051 uint16_t phy_adr:5; 1052 uint16_t mdio_rw:1; 1053 uint16_t resv11_14:4; 1054 uint16_t mdio_clc:1; 1055 } adr_bits; 1056 } nge_mdio_adr; 1057 1058 /* 1059 * Mdio data 1060 */ 1061 #define NGE_MDIO_DATA 0x194 1062 1063 /* 1064 * Power Management and Control 1065 */ 1066 #define NGE_PM_CNTL 0x200 1067 typedef union _nge_pm_cntl { 1068 uint32_t cntl_val; 1069 struct { 1070 /* 1071 * mp_en: Magic Packet Enable 1072 * pm_en: Pattern Match Enable 1073 * lc_en: Link Change Enable 1074 */ 1075 uint32_t mp_en_d0:1; 1076 uint32_t pm_en_d0:1; 1077 uint32_t lc_en_d0:1; 1078 uint32_t resv3:1; 1079 uint32_t mp_en_d1:1; 1080 uint32_t pm_en_d1:1; 1081 uint32_t lc_en_d1:1; 1082 uint32_t resv7:1; 1083 uint32_t mp_en_d2:1; 1084 uint32_t pm_en_d2:1; 1085 uint32_t lc_en_d2:1; 1086 uint32_t resv11:1; 1087 uint32_t mp_en_d3:1; 1088 uint32_t pm_en_d3:1; 1089 uint32_t lc_en_d3:1; 1090 uint32_t resv15:1; 1091 uint32_t pat_match_en:5; 1092 uint32_t resv21_23:3; 1093 uint32_t pat_match_stat:5; 1094 uint32_t magic_status:1; 1095 uint32_t netman_status:1; 1096 uint32_t resv31:1; 1097 } cntl_bits; 1098 } nge_pm_cntl; 1099 1100 #define NGE_MPT_CRC0 0x204 1101 #define NGE_PMC_MK00 0x208 1102 #define NGE_PMC_MK01 0x20C 1103 #define NGE_PMC_MK02 0x210 1104 #define NGE_PMC_MK03 0x214 1105 #define NGE_MPT_CRC1 0x218 1106 #define NGE_PMC_MK10 0x21c 1107 #define NGE_PMC_MK11 0x220 1108 #define NGE_PMC_MK12 0x224 1109 #define NGE_PMC_MK13 0x228 1110 #define NGE_MPT_CRC2 0x22c 1111 #define NGE_PMC_MK20 0x230 1112 #define NGE_PMC_MK21 0x234 1113 #define NGE_PMC_MK22 0x238 1114 #define NGE_PMC_MK23 0x23c 1115 #define NGE_MPT_CRC3 0x240 1116 #define NGE_PMC_MK30 0x244 1117 #define NGE_PMC_MK31 0x248 1118 #define NGE_PMC_MK32 0x24c 1119 #define NGE_PMC_MK33 0x250 1120 #define NGE_MPT_CRC4 0x254 1121 #define NGE_PMC_MK40 0x258 1122 #define NGE_PMC_MK41 0x25c 1123 #define NGE_PMC_MK42 0x260 1124 #define NGE_PMC_MK43 0x264 1125 #define NGE_PMC_ALIAS 0x268 1126 #define NGE_PMCSR_ALIAS 0x26c 1127 1128 /* 1129 * Seeprom control 1130 */ 1131 #define NGE_EP_CNTL 0x500 1132 #define EEPROM_CLKDIV 249 1133 #define EEPROM_WAITCLK 0x7 1134 typedef union _nge_cp_cntl { 1135 uint32_t cntl_val; 1136 struct { 1137 uint32_t clkdiv:8; 1138 uint32_t rom_size:3; 1139 uint32_t resv11:1; 1140 uint32_t word_wid:1; 1141 uint32_t resv13_15:3; 1142 uint32_t wait_slots:4; 1143 uint32_t resv20_31:12; 1144 } cntl_bits; 1145 } nge_cp_cntl; 1146 1147 /* 1148 * Seeprom cmd control 1149 */ 1150 #define NGE_EP_CMD 0x504 1151 #define SEEPROM_CMD_READ 0x0 1152 #define SEEPROM_CMD_WRITE_ENABLE 0x1 1153 #define SEEPROM_CMD_ERASE 0x2 1154 #define SEEPROM_CMD_WRITE 0x3 1155 #define SEEPROM_CMD_ERALSE_ALL 0x4 1156 #define SEEPROM_CMD_WRITE_ALL 0x5 1157 #define SEEPROM_CMD_WRITE_DIS 0x6 1158 #define SEEPROM_READY 0x1 1159 typedef union _nge_ep_cmd { 1160 uint32_t cmd_val; 1161 struct { 1162 uint32_t addr:16; 1163 uint32_t cmd:3; 1164 uint32_t resv19_30:12; 1165 uint32_t sts:1; 1166 } cmd_bits; 1167 } nge_ep_cmd; 1168 1169 /* 1170 * Seeprom data register 1171 */ 1172 #define NGE_EP_DATA 0x508 1173 typedef union _nge_ep_data { 1174 uint32_t data_val; 1175 struct { 1176 uint32_t data:16; 1177 uint32_t resv16_31:16; 1178 } data_bits; 1179 } nge_ep_data; 1180 1181 /* 1182 * Power management control 2nd register (since MCP51) 1183 */ 1184 #define NGE_PM_CNTL2 0x600 1185 typedef union _nge_pm_cntl2 { 1186 uint32_t cntl_val; 1187 struct { 1188 uint32_t phy_coma_set:1; 1189 uint32_t phy_coma_status:1; 1190 uint32_t resv2_3:2; 1191 uint32_t resv4:1; 1192 uint32_t resv5_7:3; 1193 uint32_t resv8_11:4; 1194 uint32_t resv12_15:4; 1195 uint32_t pmt5_en:1; 1196 uint32_t pmt6_en:1; 1197 uint32_t pmt7_en:1; 1198 uint32_t resv19_23:5; 1199 uint32_t pmt5_status:1; 1200 uint32_t pmt6_status:1; 1201 uint32_t pmt7_status:1; 1202 uint32_t resv27_31:5; 1203 } cntl_bits; 1204 } nge_pm_cntl2; 1205 1206 1207 /* 1208 * ASF RAM 0x800-0xfff 1209 */ 1210 1211 /* 1212 * Hardware-defined Statistics Block Offsets 1213 * 1214 * These are given in the manual as addresses in NIC memory, starting 1215 * from the NIC statistics area base address of 0x2000; 1216 */ 1217 1218 #define KS_BASE 0x0280 1219 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint32_t)) 1220 1221 typedef enum { 1222 KS_ifHOutOctets = KS_ADDR(0x0280), 1223 KS_ifHOutZeroRetranCount, 1224 KS_ifHOutOneRetranCount, 1225 KS_ifHOutMoreRetranCount, 1226 KS_ifHOutColCount, 1227 KS_ifHOutFifoovCount, 1228 KS_ifHOutLOCCount, 1229 KS_ifHOutExDecCount, 1230 KS_ifHOutRetryCount, 1231 1232 KS_ifHInFrameErrCount, 1233 KS_ifHInExtraOctErrCount, 1234 KS_ifHInLColErrCount, 1235 KS_ifHInRuntCount, 1236 KS_ifHInOversizeErrCount, 1237 KS_ifHInFovErrCount, 1238 KS_ifHInFCSErrCount, 1239 KS_ifHInAlignErrCount, 1240 KS_ifHInLenErrCount, 1241 KS_ifHInUniPktsCount, 1242 KS_ifHInBroadPksCount, 1243 KS_ifHInMulPksCount, 1244 KS_STATS_SIZE = KS_ADDR(0x2d0) 1245 1246 } nge_stats_offset_t; 1247 1248 /* 1249 * Hardware-defined Statistics Block 1250 * 1251 * Another view of the statistic block, as a array and a structure ... 1252 */ 1253 1254 typedef union { 1255 uint32_t a[KS_STATS_SIZE]; 1256 struct { 1257 uint32_t OutOctets; 1258 uint32_t OutZeroRetranCount; 1259 uint32_t OutOneRetranCount; 1260 uint32_t OutMoreRetranCount; 1261 uint32_t OutColCount; 1262 uint32_t OutFifoovCount; 1263 uint32_t OutLOCCount; 1264 uint32_t OutExDecCount; 1265 uint32_t OutRetryCount; 1266 1267 uint32_t InFrameErrCount; 1268 uint32_t InExtraOctErrCount; 1269 uint32_t InLColErrCount; 1270 uint32_t InRuntCount; 1271 uint32_t InOversizeErrCount; 1272 uint32_t InFovErrCount; 1273 uint32_t InFCSErrCount; 1274 uint32_t InAlignErrCount; 1275 uint32_t InLenErrCount; 1276 uint32_t InUniPktsCount; 1277 uint32_t InBroadPksCount; 1278 uint32_t InMulPksCount; 1279 } s; 1280 } nge_hw_statistics_t; 1281 1282 /* 1283 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1284 */ 1285 1286 #define NGE_PHY_NUMBER 32 1287 #define MII_LP_ASYM_PAUSE 0x0800 1288 #define MII_LP_PAUSE 0x0400 1289 1290 #define MII_100BASE_T4 0x0200 1291 #define MII_100BASET_FD 0x0100 1292 #define MII_100BASET_HD 0x0080 1293 #define MII_10BASET_FD 0x0040 1294 #define MII_10BASET_HD 0x0020 1295 1296 #define MII_ID_MARVELL 0x5043 1297 #define MII_ID_CICADA 0x03f1 1298 #define MII_IDL_MASK 0xfc00 1299 #define MII_AN_LPNXTPG 8 1300 1301 1302 #define MII_IEEE_EXT_STATUS 15 1303 1304 /* 1305 * New bits in the MII_CONTROL register 1306 */ 1307 #define MII_CONTROL_1000MB 0x0040 1308 1309 /* 1310 * New bits in the MII_AN_ADVERT register 1311 */ 1312 #define MII_ABILITY_ASYM_PAUSE 0x0800 1313 #define MII_ABILITY_PAUSE 0x0400 1314 1315 /* 1316 * Values for the <selector> field of the MII_AN_ADVERT register 1317 */ 1318 #define MII_AN_SELECTOR_8023 0x0001 1319 1320 /* 1321 * Bits in the MII_1000BASE_T_CONTROL register 1322 * 1323 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1324 * (otherwise, roles are automatically negotiated). When this bit is set, 1325 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1326 */ 1327 #define MII_1000BASE_T_CONTROL 9 1328 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1329 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1330 #define MII_1000BT_CTL_ADV_FDX 0x0200 1331 #define MII_1000BT_CTL_ADV_HDX 0x0100 1332 1333 /* 1334 * Bits in the MII_1000BASE_T_STATUS register 1335 */ 1336 #define MII_1000BASE_T_STATUS 10 1337 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1338 #define MII_1000BT_STAT_MASTER_MODE 0x4000 1339 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1340 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1341 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1342 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1343 1344 #define MII_CICADA_BYPASS_CONTROL MII_VENDOR(2) 1345 #define CICADA_125MHZ_CLOCK_ENABLE 0x0001 1346 1347 #define MII_CICADA_10BASET_CONTROL MII_VENDOR(6) 1348 #define MII_CICADA_DISABLE_ECHO_MODE 0x2000 1349 1350 #define MII_CICADA_EXT_CONTROL MII_VENDOR(7) 1351 #define MII_CICADA_MODE_SELECT_BITS 0xf000 1352 #define MII_CICADA_MODE_SELECT_RGMII 0x1000 1353 #define MII_CICADA_POWER_SUPPLY_BITS 0x0e00 1354 #define MII_CICADA_POWER_SUPPLY_3_3V 0x0000 1355 #define MII_CICADA_POWER_SUPPLY_2_5V 0x0200 1356 1357 #define MII_CICADA_AUXCTRL_STATUS MII_VENDOR(12) 1358 #define MII_CICADA_PIN_PRORITY_SETTING 0x0004 1359 #define MII_CICADA_PIN_PRORITY_DEFAULT 0x0000 1360 1361 1362 #define NGE_REG_SIZE 0xfff 1363 #define NGE_MII_SIZE 0x20 1364 #define NGE_SEEROM_SIZE 0x800 1365 /* 1366 * Legacy rx's bd which does not support 1367 * any hardware offload 1368 */ 1369 typedef struct _legacy_rx_bd { 1370 uint32_t host_buf_addr; 1371 union { 1372 uint32_t cntl_val; 1373 struct { 1374 uint32_t bcnt:16; 1375 uint32_t end:1; 1376 uint32_t miss:1; 1377 uint32_t extra:1; 1378 uint32_t inten:1; 1379 uint32_t bam:1; 1380 uint32_t mam:1; 1381 uint32_t pam:1; 1382 uint32_t runt:1; 1383 uint32_t lcol:1; 1384 uint32_t max:1; 1385 uint32_t lfer:1; 1386 uint32_t crc:1; 1387 uint32_t ofol:1; 1388 uint32_t fram:1; 1389 uint32_t err:1; 1390 uint32_t own:1; 1391 } cntl_bits; 1392 } cntl_status; 1393 } legacy_rx_bd, *plegacy_rx_bd; 1394 1395 /* 1396 * Stand offload rx's bd which supports hareware checksum 1397 * for tcp/ip 1398 */ 1399 #define CK8G_NO_HSUM 0x0 1400 #define CK8G_TCP_SUM_ERR 0x1 1401 #define CK8G_UDP_SUM_ERR 0x2 1402 #define CK8G_IP_HSUM_ERR 0x3 1403 #define CK8G_IP_HSUM 0x4 1404 #define CK8G_TCP_SUM 0x5 1405 #define CK8G_UDP_SUM 0x6 1406 #define CK8G_RESV 0x7 1407 typedef struct _sum_rx_bd { 1408 uint32_t host_buf_addr; 1409 union { 1410 uint32_t cntl_val; 1411 struct { 1412 uint32_t bcnt:14; 1413 uint32_t resv14_29:16; 1414 uint32_t inten:1; 1415 uint32_t own:1; 1416 } control_bits; 1417 struct { 1418 uint32_t bcnt:14; 1419 uint32_t resv14:1; 1420 uint32_t bam:1; 1421 uint32_t mam:1; 1422 uint32_t pam:1; 1423 uint32_t runt:1; 1424 uint32_t lcol:1; 1425 uint32_t max:1; 1426 uint32_t lfer:1; 1427 uint32_t crc:1; 1428 uint32_t ofol:1; 1429 uint32_t fram:1; 1430 uint32_t extra:1; 1431 uint32_t l3_l4_sum:3; 1432 uint32_t rend:1; 1433 uint32_t err:1; 1434 uint32_t own:1; 1435 } status_bits; 1436 } cntl_status; 1437 } sum_rx_bd, *psum_rx_bd; 1438 /* 1439 * Hot offload rx's bd which support 64bit access and 1440 * full-tcp hardware offload 1441 */ 1442 typedef struct _hot_rx_bd { 1443 uint32_t host_buf_addr_hi; 1444 uint32_t host_buf_addr_lo; 1445 uint32_t sw_tag; 1446 union { 1447 uint32_t cntl_val; 1448 struct { 1449 uint32_t bcnt:14; 1450 uint32_t resv14_29:16; 1451 uint32_t inten:1; 1452 uint32_t own:1; 1453 } control_bits; 1454 1455 struct { 1456 uint32_t bcnt:14; 1457 uint32_t ctmach_rd:1; 1458 uint32_t bam:1; 1459 uint32_t mam:1; 1460 uint32_t pam:1; 1461 uint32_t runt:1; 1462 uint32_t lcol:1; 1463 uint32_t max:1; 1464 uint32_t lfer:1; 1465 uint32_t crc:1; 1466 uint32_t ofol:1; 1467 uint32_t fram:1; 1468 uint32_t extra:1; 1469 uint32_t l3_l4_sum:3; 1470 uint32_t rend:1; 1471 uint32_t err:1; 1472 uint32_t own:1; 1473 } status_bits_legacy; 1474 } cntl_status; 1475 } hot_rx_bd, *phot_rx_bd; 1476 1477 /* 1478 * Legacy tx's bd which does not support 1479 * any hardware offload 1480 */ 1481 typedef struct _legacy_tx_bd { 1482 uint32_t host_buf_addr; 1483 union { 1484 uint32_t cntl_val; 1485 struct { 1486 uint32_t bcnt:16; 1487 uint32_t end:1; 1488 uint32_t resv17_23:7; 1489 uint32_t inten:1; 1490 uint32_t resv25_30:6; 1491 uint32_t own:1; 1492 } control_bits; 1493 1494 struct { 1495 uint32_t bcnt:16; 1496 uint32_t end:1; 1497 uint32_t rtry:1; 1498 uint32_t trc:4; 1499 uint32_t inten:1; 1500 uint32_t exdef:1; 1501 uint32_t def:1; 1502 uint32_t lcar:1; 1503 uint32_t lcol:1; 1504 uint32_t uflo:1; 1505 uint32_t err:1; 1506 uint32_t own:1; 1507 } status_bits; 1508 } cntl_status; 1509 } legacy_tx_bd, *plegacy_tx_bd; 1510 1511 /* 1512 * Stand offload tx's bd which supports hareware checksum 1513 * for tcp/ip 1514 */ 1515 typedef struct _sum_tx_bd { 1516 uint32_t host_buf_addr; 1517 union { 1518 uint32_t cntl_val; 1519 struct { 1520 uint32_t bcnt:14; 1521 uint32_t resv14_25:12; 1522 uint32_t tcp_hsum:1; 1523 uint32_t ip_hsum:1; 1524 uint32_t segen:1; 1525 uint32_t end:1; 1526 uint32_t inten:1; 1527 uint32_t own:1; 1528 } control_sum_bits; 1529 1530 struct { 1531 uint32_t bcnt:14; 1532 uint32_t mss:14; 1533 uint32_t segen:1; 1534 uint32_t end:1; 1535 uint32_t inten:1; 1536 uint32_t own:1; 1537 } control_tso_bits; 1538 1539 struct { 1540 uint32_t bcnt:14; 1541 uint32_t resv14_17:4; 1542 uint32_t rtry:1; 1543 uint32_t trc:4; 1544 uint32_t inten:1; 1545 uint32_t exdef:1; 1546 uint32_t def:1; 1547 uint32_t lcar:1; 1548 uint32_t lcol:1; 1549 uint32_t uflo:1; 1550 uint32_t end:1; 1551 uint32_t err:1; 1552 uint32_t own:1; 1553 } status_bits; 1554 } control_status; 1555 } sum_tx_bd, *psum_tx_bd; 1556 1557 /* 1558 * Hot offload tx's bd which support 64bit access and 1559 * full-tcp hardware offload 1560 */ 1561 1562 typedef struct _hot_tx_bd { 1563 uint32_t host_buf_addr_hi; 1564 uint32_t host_buf_addr_lo; 1565 union { 1566 uint32_t parm_val; 1567 struct { 1568 uint32_t resv0_15:16; 1569 uint32_t resv16:1; 1570 uint32_t resv17:1; 1571 uint32_t resv18_31:14; 1572 } parm_bits; 1573 } hot_parms; 1574 1575 union { 1576 uint32_t cntl_val; 1577 struct { 1578 uint32_t bcnt:14; 1579 uint32_t resv14_25:12; 1580 uint32_t tcp_hsum:1; 1581 uint32_t ip_hsum:1; 1582 uint32_t segen:1; 1583 uint32_t end:1; 1584 uint32_t inten:1; 1585 uint32_t own:1; 1586 } control_sum_bits; 1587 1588 struct { 1589 uint32_t bcnt:14; 1590 uint32_t mss:14; 1591 uint32_t segen:1; 1592 uint32_t end:1; 1593 uint32_t inten:1; 1594 uint32_t own:1; 1595 } control_tso_bits; 1596 1597 struct { 1598 uint32_t bcnt:14; 1599 uint32_t resv14_17:4; 1600 uint32_t rtry:1; 1601 uint32_t trc:4; 1602 uint32_t inten:1; 1603 uint32_t exdef:1; 1604 uint32_t def:1; 1605 uint32_t lcar:1; 1606 uint32_t lcol:1; 1607 uint32_t uflo:1; 1608 uint32_t end:1; 1609 uint32_t err:1; 1610 uint32_t own:1; 1611 } status_bits; 1612 } control_status; 1613 } hot_tx_bd, *phot_tx_bd; 1614 1615 #ifdef __cplusplus 1616 } 1617 #endif 1618 1619 #endif /* _SYS_NGE_CHIP_H */ 1620