xref: /titanic_44/usr/src/uts/common/io/nge/nge_chip.c (revision 88ecc943b4eb72f7c4fbbd8435997b85ef171fc3)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #include "nge.h"
28 static uint32_t	nge_watchdog_count	= 1 << 29;
29 extern boolean_t nge_enable_msi;
30 static void nge_sync_mac_modes(nge_t *);
31 
32 #undef NGE_DBG
33 #define	NGE_DBG		NGE_DBG_CHIP
34 
35 /*
36  * Operating register get/set access routines
37  */
38 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno);
39 #pragma	inline(nge_reg_get8)
40 
41 uint8_t
42 nge_reg_get8(nge_t *ngep, nge_regno_t regno)
43 {
44 	NGE_TRACE(("nge_reg_get8($%p, 0x%lx)", (void *)ngep, regno));
45 
46 	return (ddi_get8(ngep->io_handle, PIO_ADDR(ngep, regno)));
47 }
48 
49 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data);
50 #pragma	inline(nge_reg_put8)
51 
52 void
53 nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data)
54 {
55 	NGE_TRACE(("nge_reg_put8($%p, 0x%lx, 0x%x)",
56 	    (void *)ngep, regno, data));
57 	ddi_put8(ngep->io_handle, PIO_ADDR(ngep, regno), data);
58 
59 }
60 
61 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno);
62 #pragma	inline(nge_reg_get16)
63 
64 uint16_t
65 nge_reg_get16(nge_t *ngep, nge_regno_t regno)
66 {
67 	NGE_TRACE(("nge_reg_get16($%p, 0x%lx)", (void *)ngep, regno));
68 	return (ddi_get16(ngep->io_handle, PIO_ADDR(ngep, regno)));
69 }
70 
71 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data);
72 #pragma	inline(nge_reg_put16)
73 
74 void
75 nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data)
76 {
77 	NGE_TRACE(("nge_reg_put16($%p, 0x%lx, 0x%x)",
78 	    (void *)ngep, regno, data));
79 	ddi_put16(ngep->io_handle, PIO_ADDR(ngep, regno), data);
80 
81 }
82 
83 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno);
84 #pragma	inline(nge_reg_get32)
85 
86 uint32_t
87 nge_reg_get32(nge_t *ngep, nge_regno_t regno)
88 {
89 	NGE_TRACE(("nge_reg_get32($%p, 0x%lx)", (void *)ngep, regno));
90 	return (ddi_get32(ngep->io_handle, PIO_ADDR(ngep, regno)));
91 }
92 
93 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data);
94 #pragma	inline(nge_reg_put32)
95 
96 void
97 nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data)
98 {
99 	NGE_TRACE(("nge_reg_put32($%p, 0x%lx, 0x%x)",
100 	    (void *)ngep, regno, data));
101 	ddi_put32(ngep->io_handle, PIO_ADDR(ngep, regno), data);
102 
103 }
104 
105 
106 static int nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd);
107 #pragma	no_inline(nge_chip_peek_cfg)
108 
109 static int
110 nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd)
111 {
112 	int err;
113 	uint64_t regval;
114 	uint64_t regno;
115 
116 	NGE_TRACE(("nge_chip_peek_cfg($%p, $%p)",
117 	    (void *)ngep, (void *)ppd));
118 
119 	err = DDI_SUCCESS;
120 	regno = ppd->pp_acc_offset;
121 
122 	switch (ppd->pp_acc_size) {
123 	case 1:
124 		regval = pci_config_get8(ngep->cfg_handle, regno);
125 		break;
126 
127 	case 2:
128 		regval = pci_config_get16(ngep->cfg_handle, regno);
129 		break;
130 
131 	case 4:
132 		regval = pci_config_get32(ngep->cfg_handle, regno);
133 		break;
134 
135 	case 8:
136 		regval = pci_config_get64(ngep->cfg_handle, regno);
137 		break;
138 	}
139 	ppd->pp_acc_data = regval;
140 	return (err);
141 }
142 
143 static int nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd);
144 
145 static int
146 nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd)
147 {
148 	int err;
149 	uint64_t regval;
150 	uint64_t regno;
151 
152 	NGE_TRACE(("nge_chip_poke_cfg($%p, $%p)",
153 	    (void *)ngep, (void *)ppd));
154 
155 	err = DDI_SUCCESS;
156 	regno = ppd->pp_acc_offset;
157 	regval = ppd->pp_acc_data;
158 
159 	switch (ppd->pp_acc_size) {
160 	case 1:
161 		pci_config_put8(ngep->cfg_handle, regno, regval);
162 		break;
163 
164 	case 2:
165 		pci_config_put16(ngep->cfg_handle, regno, regval);
166 		break;
167 
168 	case 4:
169 		pci_config_put32(ngep->cfg_handle, regno, regval);
170 		break;
171 
172 	case 8:
173 		pci_config_put64(ngep->cfg_handle, regno, regval);
174 		break;
175 	}
176 
177 	return (err);
178 
179 }
180 
181 static int nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd);
182 
183 static int
184 nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd)
185 {
186 	int err;
187 	uint64_t regval;
188 	void *regaddr;
189 
190 	NGE_TRACE(("nge_chip_peek_reg($%p, $%p)",
191 	    (void *)ngep, (void *)ppd));
192 
193 	err = DDI_SUCCESS;
194 	regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset);
195 
196 	switch (ppd->pp_acc_size) {
197 	case 1:
198 		regval = ddi_get8(ngep->io_handle, regaddr);
199 	break;
200 
201 	case 2:
202 		regval = ddi_get16(ngep->io_handle, regaddr);
203 	break;
204 
205 	case 4:
206 		regval = ddi_get32(ngep->io_handle, regaddr);
207 	break;
208 
209 	case 8:
210 		regval = ddi_get64(ngep->io_handle, regaddr);
211 	break;
212 
213 	default:
214 		regval = 0x0ull;
215 	break;
216 	}
217 	ppd->pp_acc_data = regval;
218 	return (err);
219 }
220 
221 static int nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd);
222 
223 static int
224 nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd)
225 {
226 	int err;
227 	uint64_t regval;
228 	void *regaddr;
229 
230 	NGE_TRACE(("nge_chip_poke_reg($%p, $%p)",
231 	    (void *)ngep, (void *)ppd));
232 
233 	err = DDI_SUCCESS;
234 	regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset);
235 	regval = ppd->pp_acc_data;
236 
237 	switch (ppd->pp_acc_size) {
238 	case 1:
239 		ddi_put8(ngep->io_handle, regaddr, regval);
240 		break;
241 
242 	case 2:
243 		ddi_put16(ngep->io_handle, regaddr, regval);
244 		break;
245 
246 	case 4:
247 		ddi_put32(ngep->io_handle, regaddr, regval);
248 		break;
249 
250 	case 8:
251 		ddi_put64(ngep->io_handle, regaddr, regval);
252 		break;
253 	}
254 	return (err);
255 }
256 
257 static int nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd);
258 #pragma	no_inline(nge_chip_peek_mii)
259 
260 static int
261 nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd)
262 {
263 	int err;
264 
265 	err = DDI_SUCCESS;
266 	ppd->pp_acc_data = nge_mii_get16(ngep, ppd->pp_acc_offset/2);
267 	return (err);
268 }
269 
270 static int nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd);
271 #pragma	no_inline(nge_chip_poke_mii)
272 
273 static int
274 nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd)
275 {
276 	int err;
277 	err = DDI_SUCCESS;
278 	nge_mii_put16(ngep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
279 	return (err);
280 }
281 
282 /*
283  * Basic SEEPROM get/set access routine
284  *
285  * This uses the chip's SEEPROM auto-access method, controlled by the
286  * Serial EEPROM Address/Data Registers at 0x504h, so the CPU
287  * doesn't have to fiddle with the individual bits.
288  *
289  * The caller should hold <genlock> and *also* have already acquired
290  * the right to access the SEEPROM.
291  *
292  * Return value:
293  *	0 on success,
294  *	ENODATA on access timeout (maybe retryable: device may just be busy)
295  *	EPROTO on other h/w or s/w errors.
296  *
297  * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
298  * from a (successful) SEEPROM_ACCESS_READ.
299  */
300 
301 static int
302 nge_seeprom_access(nge_t *ngep, uint32_t cmd, nge_regno_t addr, uint16_t *dp)
303 {
304 	uint32_t tries;
305 	nge_ep_cmd cmd_reg;
306 	nge_ep_data data_reg;
307 
308 	NGE_TRACE(("nge_seeprom_access($%p, %d, %x, $%p)",
309 	    (void *)ngep, cmd, addr, (void *)dp));
310 
311 	ASSERT(mutex_owned(ngep->genlock));
312 
313 	/*
314 	 * Check there's no command in progress.
315 	 *
316 	 * Note: this *shouldn't* ever find that there is a command
317 	 * in progress, because we already hold the <genlock> mutex.
318 	 * Also, to ensure we don't have a conflict with the chip's
319 	 * internal firmware or a process accessing the same (shared)
320 	 * So this is just a final consistency check: we shouldn't
321 	 * see EITHER the START bit (command started but not complete)
322 	 * OR the COMPLETE bit (command completed but not cleared).
323 	 */
324 	cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
325 	for (tries = 0; tries < 30; tries++) {
326 		if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
327 			break;
328 		drv_usecwait(10);
329 		cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
330 	}
331 
332 	/*
333 	 * This should not happen. If so, we have to restart eeprom
334 	 *  state machine
335 	 */
336 	if (tries == 30) {
337 		cmd_reg.cmd_bits.sts = SEEPROM_READY;
338 		nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val);
339 		drv_usecwait(10);
340 		/*
341 		 * Polling the status bit to make assure the eeprom is ready
342 		 */
343 		cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
344 		for (tries = 0; tries < 30; tries++) {
345 			if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
346 				break;
347 			drv_usecwait(10);
348 			cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
349 		}
350 	}
351 
352 	/*
353 	 * Assemble the command ...
354 	 */
355 	cmd_reg.cmd_bits.addr = (uint32_t)addr;
356 	cmd_reg.cmd_bits.cmd = cmd;
357 	cmd_reg.cmd_bits.sts = 0;
358 
359 	nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val);
360 
361 	/*
362 	 * Polling whether the access is successful.
363 	 *
364 	 */
365 	cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
366 	for (tries = 0; tries < 30; tries++) {
367 		if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
368 			break;
369 		drv_usecwait(10);
370 		cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
371 	}
372 
373 	if (tries == 30) {
374 		nge_report(ngep, NGE_HW_ROM);
375 		return (DDI_FAILURE);
376 	}
377 	switch (cmd) {
378 	default:
379 	case SEEPROM_CMD_WRITE_ENABLE:
380 	case SEEPROM_CMD_ERASE:
381 	case SEEPROM_CMD_ERALSE_ALL:
382 	case SEEPROM_CMD_WRITE_DIS:
383 	break;
384 
385 	case SEEPROM_CMD_READ:
386 		data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA);
387 		*dp = data_reg.data_bits.data;
388 	break;
389 
390 	case SEEPROM_CMD_WRITE:
391 		data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA);
392 		data_reg.data_bits.data = *dp;
393 		nge_reg_put32(ngep, NGE_EP_DATA, data_reg.data_val);
394 	break;
395 	}
396 
397 	return (DDI_SUCCESS);
398 }
399 
400 
401 static int
402 nge_chip_peek_seeprom(nge_t *ngep, nge_peekpoke_t *ppd)
403 {
404 	uint16_t data;
405 	int err;
406 
407 	err = nge_seeprom_access(ngep, SEEPROM_CMD_READ,
408 	    ppd->pp_acc_offset, &data);
409 	ppd->pp_acc_data =  data;
410 	return (err);
411 }
412 
413 static int
414 nge_chip_poke_seeprom(nge_t *ngep, nge_peekpoke_t *ppd)
415 {
416 	uint16_t data;
417 	int err;
418 
419 	data = ppd->pp_acc_data;
420 	err = nge_seeprom_access(ngep, SEEPROM_CMD_WRITE,
421 	    ppd->pp_acc_offset, &data);
422 	return (err);
423 }
424 
425 void
426 nge_init_dev_spec_param(nge_t *ngep)
427 {
428 	nge_dev_spec_param_t	*dev_param_p;
429 	chip_info_t	*infop;
430 
431 	dev_param_p = &ngep->dev_spec_param;
432 	infop = (chip_info_t *)&ngep->chipinfo;
433 
434 	switch (infop->device) {
435 	case DEVICE_ID_NF3_E6:
436 	case DEVICE_ID_NF3_DF:
437 	case DEVICE_ID_MCP04_37:
438 	case DEVICE_ID_MCP04_38:
439 		dev_param_p->msi = B_FALSE;
440 		dev_param_p->msi_x = B_FALSE;
441 		dev_param_p->vlan = B_FALSE;
442 		dev_param_p->advanced_pm = B_FALSE;
443 		dev_param_p->mac_addr_order = B_FALSE;
444 		dev_param_p->tx_pause_frame = B_FALSE;
445 		dev_param_p->rx_pause_frame = B_FALSE;
446 		dev_param_p->jumbo = B_FALSE;
447 		dev_param_p->tx_rx_64byte = B_FALSE;
448 		dev_param_p->rx_hw_checksum = B_FALSE;
449 		dev_param_p->tx_hw_checksum = 0;
450 		dev_param_p->desc_type = DESC_OFFLOAD;
451 		dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
452 		dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
453 		dev_param_p->nge_split = NGE_SPLIT_32;
454 		break;
455 
456 	case DEVICE_ID_CK804_56:
457 	case DEVICE_ID_CK804_57:
458 		dev_param_p->msi = B_TRUE;
459 		dev_param_p->msi_x = B_TRUE;
460 		dev_param_p->vlan = B_FALSE;
461 		dev_param_p->advanced_pm = B_FALSE;
462 		dev_param_p->mac_addr_order = B_FALSE;
463 		dev_param_p->tx_pause_frame = B_FALSE;
464 		dev_param_p->rx_pause_frame = B_TRUE;
465 		dev_param_p->jumbo = B_TRUE;
466 		dev_param_p->tx_rx_64byte = B_FALSE;
467 		dev_param_p->rx_hw_checksum = B_TRUE;
468 		dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM;
469 		dev_param_p->desc_type = DESC_HOT;
470 		dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072;
471 		dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072;
472 		dev_param_p->nge_split = NGE_SPLIT_96;
473 		break;
474 
475 	case DEVICE_ID_MCP51_268:
476 	case DEVICE_ID_MCP51_269:
477 		dev_param_p->msi = B_FALSE;
478 		dev_param_p->msi_x = B_FALSE;
479 		dev_param_p->vlan = B_FALSE;
480 		dev_param_p->advanced_pm = B_TRUE;
481 		dev_param_p->mac_addr_order = B_FALSE;
482 		dev_param_p->tx_pause_frame = B_FALSE;
483 		dev_param_p->rx_pause_frame = B_FALSE;
484 		dev_param_p->jumbo = B_FALSE;
485 		dev_param_p->tx_rx_64byte = B_TRUE;
486 		dev_param_p->rx_hw_checksum = B_FALSE;
487 		dev_param_p->tx_hw_checksum = 0;
488 		dev_param_p->desc_type = DESC_OFFLOAD;
489 		dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
490 		dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
491 		dev_param_p->nge_split = NGE_SPLIT_32;
492 		break;
493 
494 	case DEVICE_ID_MCP55_372:
495 	case DEVICE_ID_MCP55_373:
496 		dev_param_p->msi = B_TRUE;
497 		dev_param_p->msi_x = B_TRUE;
498 		dev_param_p->vlan = B_TRUE;
499 		dev_param_p->advanced_pm = B_TRUE;
500 		dev_param_p->mac_addr_order = B_FALSE;
501 		dev_param_p->tx_pause_frame = B_TRUE;
502 		dev_param_p->rx_pause_frame = B_TRUE;
503 		dev_param_p->jumbo = B_TRUE;
504 		dev_param_p->tx_rx_64byte = B_TRUE;
505 		dev_param_p->rx_hw_checksum = B_TRUE;
506 		dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM;
507 		dev_param_p->desc_type = DESC_HOT;
508 		dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072;
509 		dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072;
510 		dev_param_p->nge_split = NGE_SPLIT_96;
511 		break;
512 
513 	case DEVICE_ID_MCP61_3EE:
514 	case DEVICE_ID_MCP61_3EF:
515 		dev_param_p->msi = B_FALSE;
516 		dev_param_p->msi_x = B_FALSE;
517 		dev_param_p->vlan = B_FALSE;
518 		dev_param_p->advanced_pm = B_TRUE;
519 		dev_param_p->mac_addr_order = B_TRUE;
520 		dev_param_p->tx_pause_frame = B_FALSE;
521 		dev_param_p->rx_pause_frame = B_FALSE;
522 		dev_param_p->jumbo = B_FALSE;
523 		dev_param_p->tx_rx_64byte = B_TRUE;
524 		dev_param_p->rx_hw_checksum = B_FALSE;
525 		dev_param_p->tx_hw_checksum = 0;
526 		dev_param_p->desc_type = DESC_OFFLOAD;
527 		dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
528 		dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
529 		dev_param_p->nge_split = NGE_SPLIT_32;
530 		break;
531 
532 	case DEVICE_ID_MCP77_760:
533 	case DEVICE_ID_MCP79_AB0:
534 		dev_param_p->msi = B_FALSE;
535 		dev_param_p->msi_x = B_FALSE;
536 		dev_param_p->vlan = B_FALSE;
537 		dev_param_p->advanced_pm = B_TRUE;
538 		dev_param_p->mac_addr_order = B_TRUE;
539 		dev_param_p->tx_pause_frame = B_FALSE;
540 		dev_param_p->rx_pause_frame = B_FALSE;
541 		dev_param_p->jumbo = B_FALSE;
542 		dev_param_p->tx_rx_64byte = B_TRUE;
543 		dev_param_p->rx_hw_checksum = B_FALSE;
544 		dev_param_p->tx_hw_checksum = 0;
545 		dev_param_p->desc_type = DESC_HOT;
546 		dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
547 		dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
548 		dev_param_p->nge_split = NGE_SPLIT_32;
549 		break;
550 
551 	default:
552 		dev_param_p->msi = B_FALSE;
553 		dev_param_p->msi_x = B_FALSE;
554 		dev_param_p->vlan = B_FALSE;
555 		dev_param_p->advanced_pm = B_FALSE;
556 		dev_param_p->mac_addr_order = B_FALSE;
557 		dev_param_p->tx_pause_frame = B_FALSE;
558 		dev_param_p->rx_pause_frame = B_FALSE;
559 		dev_param_p->jumbo = B_FALSE;
560 		dev_param_p->tx_rx_64byte = B_FALSE;
561 		dev_param_p->rx_hw_checksum = B_FALSE;
562 		dev_param_p->tx_hw_checksum = 0;
563 		dev_param_p->desc_type = DESC_OFFLOAD;
564 		dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
565 		dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
566 		dev_param_p->nge_split = NGE_SPLIT_32;
567 		return;
568 	}
569 }
570 /*
571  * Perform first-stage chip (re-)initialisation, using only config-space
572  * accesses:
573  *
574  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
575  *   returning the data in the structure pointed to by <infop>.
576  */
577 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset);
578 #pragma	no_inline(nge_chip_cfg_init)
579 
580 void
581 nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset)
582 {
583 	uint16_t command;
584 	ddi_acc_handle_t handle;
585 	nge_interbus_conf interbus_conf;
586 	nge_msi_mask_conf msi_mask_conf;
587 	nge_msi_map_cap_conf cap_conf;
588 
589 	NGE_TRACE(("nge_chip_cfg_init($%p, $%p, %d)",
590 	    (void *)ngep, (void *)infop, reset));
591 
592 	/*
593 	 * save PCI cache line size and subsystem vendor ID
594 	 *
595 	 * Read all the config-space registers that characterise the
596 	 * chip, specifically vendor/device/revision/subsystem vendor
597 	 * and subsystem device id.  We expect (but don't check) that
598 	 */
599 	handle = ngep->cfg_handle;
600 	/* reading the vendor information once */
601 	if (reset == B_FALSE) {
602 		infop->command = pci_config_get16(handle,
603 		    PCI_CONF_COMM);
604 		infop->vendor = pci_config_get16(handle,
605 		    PCI_CONF_VENID);
606 		infop->device = pci_config_get16(handle,
607 		    PCI_CONF_DEVID);
608 		infop->subven = pci_config_get16(handle,
609 		    PCI_CONF_SUBVENID);
610 		infop->subdev = pci_config_get16(handle,
611 		    PCI_CONF_SUBSYSID);
612 		infop->class_code = pci_config_get8(handle,
613 		    PCI_CONF_BASCLASS);
614 		infop->revision = pci_config_get8(handle,
615 		    PCI_CONF_REVID);
616 		infop->clsize = pci_config_get8(handle,
617 		    PCI_CONF_CACHE_LINESZ);
618 		infop->latency = pci_config_get8(handle,
619 		    PCI_CONF_LATENCY_TIMER);
620 	}
621 	if (nge_enable_msi) {
622 		/* Disable the hidden for MSI support */
623 		interbus_conf.conf_val = pci_config_get32(handle,
624 		    PCI_CONF_HT_INTERNAL);
625 		if ((infop->device == DEVICE_ID_MCP55_373) ||
626 		    (infop->device == DEVICE_ID_MCP55_372))
627 			interbus_conf.conf_bits.msix_off = NGE_SET;
628 		interbus_conf.conf_bits.msi_off = NGE_CLEAR;
629 		pci_config_put32(handle, PCI_CONF_HT_INTERNAL,
630 		    interbus_conf.conf_val);
631 
632 		if ((infop->device == DEVICE_ID_MCP55_373) ||
633 		    (infop->device == DEVICE_ID_MCP55_372)) {
634 
635 			/* Disable the vector off for mcp55 */
636 			msi_mask_conf.msi_mask_conf_val =
637 			    pci_config_get32(handle, PCI_CONF_HT_MSI_MASK);
638 			msi_mask_conf.msi_mask_bits.vec0_off = NGE_CLEAR;
639 			msi_mask_conf.msi_mask_bits.vec1_off = NGE_CLEAR;
640 			msi_mask_conf.msi_mask_bits.vec2_off = NGE_CLEAR;
641 			msi_mask_conf.msi_mask_bits.vec3_off = NGE_CLEAR;
642 			msi_mask_conf.msi_mask_bits.vec4_off = NGE_CLEAR;
643 			msi_mask_conf.msi_mask_bits.vec5_off = NGE_CLEAR;
644 			msi_mask_conf.msi_mask_bits.vec6_off = NGE_CLEAR;
645 			msi_mask_conf.msi_mask_bits.vec7_off = NGE_CLEAR;
646 			pci_config_put32(handle, PCI_CONF_HT_MSI_MASK,
647 			    msi_mask_conf.msi_mask_conf_val);
648 
649 			/* Enable the MSI mapping */
650 			cap_conf.msi_map_cap_conf_val =
651 			    pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP);
652 			cap_conf.map_cap_conf_bits.map_en = NGE_SET;
653 			pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP,
654 			    cap_conf.msi_map_cap_conf_val);
655 		}
656 	} else {
657 		interbus_conf.conf_val = pci_config_get32(handle,
658 		    PCI_CONF_HT_INTERNAL);
659 		interbus_conf.conf_bits.msi_off = NGE_SET;
660 		pci_config_put32(handle, PCI_CONF_HT_INTERNAL,
661 		    interbus_conf.conf_val);
662 	}
663 	command = infop->command | PCI_COMM_MAE;
664 	command &= ~PCI_COMM_MEMWR_INVAL;
665 	command |= PCI_COMM_ME;
666 	pci_config_put16(handle, PCI_CONF_COMM, command);
667 	pci_config_put16(handle, PCI_CONF_STAT, ~0);
668 
669 }
670 
671 int
672 nge_chip_stop(nge_t *ngep, boolean_t fault)
673 {
674 	int err;
675 	uint32_t reg_val;
676 	uint32_t	tries;
677 	nge_mintr_src mintr_src;
678 	nge_mii_cs mii_cs;
679 	nge_rx_poll rx_poll;
680 	nge_tx_poll tx_poll;
681 	nge_rx_en rx_en;
682 	nge_tx_en tx_en;
683 	nge_tx_sta tx_sta;
684 	nge_rx_sta rx_sta;
685 	nge_mode_cntl mode;
686 	nge_pmu_cntl2 pmu_cntl2;
687 
688 	NGE_TRACE(("nge_chip_stop($%p, %d)", (void *)ngep, fault));
689 
690 	err = DDI_SUCCESS;
691 
692 	/* Clear any pending PHY interrupt */
693 	mintr_src.src_val = nge_reg_get8(ngep, NGE_MINTR_SRC);
694 	nge_reg_put8(ngep, NGE_MINTR_SRC, mintr_src.src_val);
695 
696 	/* Mask all interrupts */
697 	reg_val = nge_reg_get32(ngep, NGE_INTR_MASK);
698 	reg_val &= ~NGE_INTR_ALL_EN;
699 	nge_reg_put32(ngep, NGE_INTR_MASK, reg_val);
700 
701 	/* Disable auto-polling of phy */
702 	mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS);
703 	mii_cs.cs_bits.ap_en = NGE_CLEAR;
704 	nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val);
705 
706 	/* Reset buffer management & DMA */
707 	mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
708 	mode.mode_bits.dma_dis = NGE_SET;
709 	mode.mode_bits.desc_type = ngep->desc_mode;
710 	nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val);
711 
712 	for (tries = 0; tries < 10000; tries++) {
713 		drv_usecwait(10);
714 		mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
715 		if (mode.mode_bits.dma_status == NGE_SET)
716 			break;
717 	}
718 	if (tries == 10000) {
719 		ngep->nge_chip_state = NGE_CHIP_ERROR;
720 		return (DDI_FAILURE);
721 	}
722 
723 	/* Disable rx's machine */
724 	rx_en.val = nge_reg_get8(ngep, NGE_RX_EN);
725 	rx_en.bits.rx_en = NGE_CLEAR;
726 	nge_reg_put8(ngep, NGE_RX_EN, rx_en.val);
727 
728 	/* Disable tx's machine */
729 	tx_en.val = nge_reg_get8(ngep, NGE_TX_EN);
730 	tx_en.bits.tx_en = NGE_CLEAR;
731 	nge_reg_put8(ngep, NGE_TX_EN, tx_en.val);
732 
733 	/*
734 	 * Clean the status of tx's state machine
735 	 * and Make assure the tx's channel is idle
736 	 */
737 	tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA);
738 	for (tries = 0; tries < 1000; tries++) {
739 		if (tx_sta.sta_bits.tx_chan_sta == NGE_CLEAR)
740 			break;
741 		drv_usecwait(10);
742 		tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA);
743 	}
744 	if (tries == 1000) {
745 		ngep->nge_chip_state = NGE_CHIP_ERROR;
746 		return (DDI_FAILURE);
747 	}
748 	nge_reg_put32(ngep, NGE_TX_STA,  tx_sta.sta_val);
749 
750 	/*
751 	 * Clean the status of rx's state machine
752 	 * and Make assure the tx's channel is idle
753 	 */
754 	rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA);
755 	for (tries = 0; tries < 1000; tries++) {
756 		if (rx_sta.sta_bits.rx_chan_sta == NGE_CLEAR)
757 			break;
758 		drv_usecwait(10);
759 		rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA);
760 	}
761 	if (tries == 1000) {
762 		ngep->nge_chip_state = NGE_CHIP_ERROR;
763 		return (DDI_FAILURE);
764 	}
765 	nge_reg_put32(ngep, NGE_RX_STA, rx_sta.sta_val);
766 
767 	/* Disable auto-poll of rx's state machine */
768 	rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL);
769 	rx_poll.poll_bits.rpen = NGE_CLEAR;
770 	rx_poll.poll_bits.rpi = NGE_CLEAR;
771 	nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val);
772 
773 	/* Disable auto-polling of tx's  state machine */
774 	tx_poll.poll_val = nge_reg_get32(ngep, NGE_TX_POLL);
775 	tx_poll.poll_bits.tpen = NGE_CLEAR;
776 	tx_poll.poll_bits.tpi = NGE_CLEAR;
777 	nge_reg_put32(ngep, NGE_TX_POLL, tx_poll.poll_val);
778 
779 	/* Restore buffer management */
780 	mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
781 	mode.mode_bits.bm_reset = NGE_SET;
782 	mode.mode_bits.tx_rcom_en = NGE_SET;
783 	nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val);
784 
785 	if (ngep->dev_spec_param.advanced_pm) {
786 
787 		nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 0);
788 		nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 0);
789 
790 		pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2);
791 		pmu_cntl2.cntl2_bits.cidle_timer = NGE_CLEAR;
792 		pmu_cntl2.cntl2_bits.didle_timer = NGE_CLEAR;
793 		nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val);
794 	}
795 	if (fault)
796 		ngep->nge_chip_state = NGE_CHIP_FAULT;
797 	else
798 		ngep->nge_chip_state = NGE_CHIP_STOPPED;
799 
800 	return (err);
801 }
802 
803 static void
804 nge_rx_setup(nge_t *ngep)
805 {
806 	uint64_t desc_addr;
807 	nge_rxtx_dlen dlen;
808 	nge_rx_poll rx_poll;
809 
810 	/*
811 	 * Filling the address and length of rx's descriptors
812 	 */
813 	desc_addr = ngep->recv->desc.cookie.dmac_laddress;
814 	nge_reg_put32(ngep, NGE_RX_DADR, desc_addr);
815 	nge_reg_put32(ngep, NGE_RX_DADR_HI, desc_addr >> 32);
816 	dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN);
817 	dlen.dlen_bits.rdlen = ngep->recv->desc.nslots - 1;
818 	nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val);
819 
820 	rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL);
821 	rx_poll.poll_bits.rpi = RX_POLL_INTV_1G;
822 	rx_poll.poll_bits.rpen = NGE_SET;
823 	nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val);
824 }
825 
826 static void
827 nge_tx_setup(nge_t *ngep)
828 {
829 	uint64_t desc_addr;
830 	nge_rxtx_dlen dlen;
831 
832 	/*
833 	 * Filling the address and length of tx's descriptors
834 	 */
835 	desc_addr = ngep->send->desc.cookie.dmac_laddress;
836 	nge_reg_put32(ngep, NGE_TX_DADR, desc_addr);
837 	nge_reg_put32(ngep, NGE_TX_DADR_HI, desc_addr >> 32);
838 	dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN);
839 	dlen.dlen_bits.tdlen = ngep->send->desc.nslots - 1;
840 	nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val);
841 }
842 
843 static int
844 nge_buff_setup(nge_t *ngep)
845 {
846 	nge_mode_cntl mode_cntl;
847 	nge_dev_spec_param_t	*dev_param_p;
848 
849 	dev_param_p = &ngep->dev_spec_param;
850 
851 	/*
852 	 * Configure Rx&Tx's buffer
853 	 */
854 	nge_rx_setup(ngep);
855 	nge_tx_setup(ngep);
856 
857 	/*
858 	 * Configure buffer attribute
859 	 */
860 	mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
861 
862 	/*
863 	 * Enable Dma access request
864 	 */
865 	mode_cntl.mode_bits.dma_dis = NGE_CLEAR;
866 
867 	/*
868 	 * Enbale Buffer management
869 	 */
870 	mode_cntl.mode_bits.bm_reset = NGE_CLEAR;
871 
872 	/*
873 	 * Support Standoffload Descriptor
874 	 */
875 	mode_cntl.mode_bits.desc_type = ngep->desc_mode;
876 
877 	/*
878 	 * Support receive hardware checksum
879 	 */
880 	if (dev_param_p->rx_hw_checksum) {
881 		mode_cntl.mode_bits.rx_sum_en = NGE_SET;
882 	} else
883 		mode_cntl.mode_bits.rx_sum_en = NGE_CLEAR;
884 
885 	/*
886 	 * Disable Tx PRD coarse update
887 	 */
888 	mode_cntl.mode_bits.tx_prd_cu_en = NGE_CLEAR;
889 
890 	/*
891 	 * Disable 64-byte access
892 	 */
893 	mode_cntl.mode_bits.w64_dis = NGE_SET;
894 
895 	/*
896 	 * Skip Rx Error Frame is not supported and if
897 	 * enable it, jumbo frame does not work any more.
898 	 */
899 	mode_cntl.mode_bits.rx_filter_en = NGE_CLEAR;
900 
901 	/*
902 	 * Can not support hot mode now
903 	 */
904 	mode_cntl.mode_bits.resv15 = NGE_CLEAR;
905 
906 	if (dev_param_p->vlan) {
907 		/* Disable the vlan strip for devices which support vlan */
908 		mode_cntl.mode_bits.vlan_strip = NGE_CLEAR;
909 
910 		/* Disable the vlan insert for devices which supprot vlan */
911 		mode_cntl.mode_bits.vlan_ins = NGE_CLEAR;
912 	}
913 
914 	if (dev_param_p->tx_rx_64byte) {
915 
916 		/* Set the maximum TX PRD fetch size to 64 bytes */
917 		mode_cntl.mode_bits.tx_fetch_prd = NGE_SET;
918 
919 		/* Set the maximum RX PRD fetch size to 64 bytes */
920 		mode_cntl.mode_bits.rx_fetch_prd = NGE_SET;
921 	}
922 	/*
923 	 * Upload Rx data as it arrives, rather than waiting for full frame
924 	 */
925 	mode_cntl.mode_bits.resv16 = NGE_CLEAR;
926 
927 	/*
928 	 * Normal HOT table accesses
929 	 */
930 	mode_cntl.mode_bits.resv17 = NGE_CLEAR;
931 
932 	/*
933 	 * Normal HOT buffer requesting
934 	 */
935 	mode_cntl.mode_bits.resv18 = NGE_CLEAR;
936 	nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val);
937 
938 	/*
939 	 * Signal controller to check for new Rx descriptors
940 	 */
941 	mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
942 	mode_cntl.mode_bits.rxdm = NGE_SET;
943 	mode_cntl.mode_bits.tx_rcom_en = NGE_SET;
944 	nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val);
945 
946 
947 	return (DDI_SUCCESS);
948 }
949 
950 /*
951  * When chipset resets, the chipset can not restore  the orignial
952  * mac address to the mac address registers.
953  *
954  * When the driver is dettached, the function will write the orignial
955  * mac address to the mac address registers.
956  */
957 
958 void
959 nge_restore_mac_addr(nge_t *ngep)
960 {
961 	uint32_t mac_addr;
962 
963 	mac_addr = (uint32_t)ngep->chipinfo.hw_mac_addr;
964 	nge_reg_put32(ngep, NGE_UNI_ADDR0, mac_addr);
965 	mac_addr = (uint32_t)(ngep->chipinfo.hw_mac_addr >> 32);
966 	nge_reg_put32(ngep, NGE_UNI_ADDR1, mac_addr);
967 }
968 
969 int
970 nge_chip_reset(nge_t *ngep)
971 {
972 	int err;
973 	uint8_t i;
974 	uint32_t regno;
975 	uint64_t mac = 0;
976 	nge_uni_addr1 uaddr1;
977 	nge_cp_cntl ee_cntl;
978 	nge_soft_misc soft_misc;
979 	nge_pmu_cntl0 pmu_cntl0;
980 	nge_pmu_cntl2 pmu_cntl2;
981 	nge_pm_cntl2 pm_cntl2;
982 	const nge_ksindex_t *ksip;
983 
984 	NGE_TRACE(("nge_chip_reset($%p)", (void *)ngep));
985 
986 	/*
987 	 * Clear the statistics by reading the statistics register
988 	 */
989 	for (ksip = nge_statistics; ksip->name != NULL; ++ksip) {
990 		regno = KS_BASE + ksip->index * sizeof (uint32_t);
991 		(void) nge_reg_get32(ngep, regno);
992 	}
993 
994 	/*
995 	 * Setup seeprom control
996 	 */
997 	ee_cntl.cntl_val = nge_reg_get32(ngep, NGE_EP_CNTL);
998 	ee_cntl.cntl_bits.clkdiv = EEPROM_CLKDIV;
999 	ee_cntl.cntl_bits.rom_size = EEPROM_32K;
1000 	ee_cntl.cntl_bits.word_wid = ACCESS_16BIT;
1001 	ee_cntl.cntl_bits.wait_slots = EEPROM_WAITCLK;
1002 	nge_reg_put32(ngep, NGE_EP_CNTL, ee_cntl.cntl_val);
1003 
1004 	/*
1005 	 * Reading the unicast mac address table
1006 	 */
1007 	if (ngep->nge_chip_state == NGE_CHIP_INITIAL) {
1008 		uaddr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1);
1009 		mac = uaddr1.addr_bits.addr;
1010 		mac <<= 32;
1011 		mac |= nge_reg_get32(ngep, NGE_UNI_ADDR0);
1012 			ngep->chipinfo.hw_mac_addr = mac;
1013 			if (ngep->dev_spec_param.mac_addr_order) {
1014 				for (i = 0; i < ETHERADDRL; i++) {
1015 					ngep->chipinfo.vendor_addr.addr[i] =
1016 					    (uchar_t)mac;
1017 					ngep->cur_uni_addr.addr[i] =
1018 					    (uchar_t)mac;
1019 					mac >>= 8;
1020 				}
1021 			} else {
1022 				for (i = ETHERADDRL; i-- != 0; ) {
1023 					ngep->chipinfo.vendor_addr.addr[i] =
1024 					    (uchar_t)mac;
1025 					ngep->cur_uni_addr.addr[i] =
1026 					    (uchar_t)mac;
1027 					mac >>= 8;
1028 				}
1029 			}
1030 			ngep->chipinfo.vendor_addr.set = 1;
1031 	}
1032 	pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ,
1033 	    ngep->chipinfo.clsize);
1034 	pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER,
1035 	    ngep->chipinfo.latency);
1036 
1037 
1038 	if (ngep->dev_spec_param.advanced_pm) {
1039 
1040 		/* Program software misc register */
1041 		soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC);
1042 		soft_misc.misc_bits.rx_clk_vx_rst = NGE_SET;
1043 		soft_misc.misc_bits.tx_clk_vx_rst = NGE_SET;
1044 		soft_misc.misc_bits.clk12m_vx_rst = NGE_SET;
1045 		soft_misc.misc_bits.fpci_clk_vx_rst = NGE_SET;
1046 		soft_misc.misc_bits.rx_clk_vc_rst = NGE_SET;
1047 		soft_misc.misc_bits.tx_clk_vc_rst = NGE_SET;
1048 		soft_misc.misc_bits.fs_clk_vc_rst = NGE_SET;
1049 		soft_misc.misc_bits.rst_ex_m2pintf = NGE_SET;
1050 		nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val);
1051 
1052 		/* wait for 32 us */
1053 		drv_usecwait(32);
1054 
1055 		soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC);
1056 		soft_misc.misc_bits.rx_clk_vx_rst = NGE_CLEAR;
1057 		soft_misc.misc_bits.tx_clk_vx_rst = NGE_CLEAR;
1058 		soft_misc.misc_bits.clk12m_vx_rst = NGE_CLEAR;
1059 		soft_misc.misc_bits.fpci_clk_vx_rst = NGE_CLEAR;
1060 		soft_misc.misc_bits.rx_clk_vc_rst = NGE_CLEAR;
1061 		soft_misc.misc_bits.tx_clk_vc_rst = NGE_CLEAR;
1062 		soft_misc.misc_bits.fs_clk_vc_rst = NGE_CLEAR;
1063 		soft_misc.misc_bits.rst_ex_m2pintf = NGE_CLEAR;
1064 		nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val);
1065 
1066 		/* Program PMU registers */
1067 		pmu_cntl0.cntl0_val = nge_reg_get32(ngep, NGE_PMU_CNTL0);
1068 		pmu_cntl0.cntl0_bits.core_spd10_fp =
1069 		    NGE_PMU_CORE_SPD10_BUSY;
1070 		pmu_cntl0.cntl0_bits.core_spd10_idle =
1071 		    NGE_PMU_CORE_SPD10_IDLE;
1072 		pmu_cntl0.cntl0_bits.core_spd100_fp =
1073 		    NGE_PMU_CORE_SPD100_BUSY;
1074 		pmu_cntl0.cntl0_bits.core_spd100_idle =
1075 		    NGE_PMU_CORE_SPD100_IDLE;
1076 		pmu_cntl0.cntl0_bits.core_spd1000_fp =
1077 		    NGE_PMU_CORE_SPD1000_BUSY;
1078 		pmu_cntl0.cntl0_bits.core_spd1000_idle =
1079 		    NGE_PMU_CORE_SPD100_IDLE;
1080 		pmu_cntl0.cntl0_bits.core_spd10_idle =
1081 		    NGE_PMU_CORE_SPD10_IDLE;
1082 		nge_reg_put32(ngep, NGE_PMU_CNTL0, pmu_cntl0.cntl0_val);
1083 
1084 		/* Set the core idle limit value */
1085 		nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT,
1086 		    NGE_PMU_CIDLE_LIMIT_DEF);
1087 
1088 		/* Set the device idle limit value */
1089 		nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT,
1090 		    NGE_PMU_DIDLE_LIMIT_DEF);
1091 
1092 		/* Enable the core/device idle timer in PMU control 2 */
1093 		pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2);
1094 		pmu_cntl2.cntl2_bits.cidle_timer = NGE_SET;
1095 		pmu_cntl2.cntl2_bits.didle_timer = NGE_SET;
1096 		pmu_cntl2.cntl2_bits.core_enable = NGE_SET;
1097 		pmu_cntl2.cntl2_bits.dev_enable = NGE_SET;
1098 		nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val);
1099 	}
1100 	/*
1101 	 * Stop the chipset and clear buffer management
1102 	 */
1103 	err = nge_chip_stop(ngep, B_FALSE);
1104 	if (err == DDI_FAILURE)
1105 		return (err);
1106 	/*
1107 	 * Clear the power state bits for phy since interface no longer
1108 	 * works after rebooting from Windows on a multi-boot machine
1109 	 */
1110 	if (ngep->chipinfo.device == DEVICE_ID_MCP51_268 ||
1111 	    ngep->chipinfo.device == DEVICE_ID_MCP51_269 ||
1112 	    ngep->chipinfo.device == DEVICE_ID_MCP55_372 ||
1113 	    ngep->chipinfo.device == DEVICE_ID_MCP55_373 ||
1114 	    ngep->chipinfo.device == DEVICE_ID_MCP61_3EE ||
1115 	    ngep->chipinfo.device == DEVICE_ID_MCP61_3EF ||
1116 	    ngep->chipinfo.device == DEVICE_ID_MCP77_760 ||
1117 	    ngep->chipinfo.device == DEVICE_ID_MCP79_AB0) {
1118 
1119 		pm_cntl2.cntl_val = nge_reg_get32(ngep, NGE_PM_CNTL2);
1120 		/* bring phy out of coma mode */
1121 		pm_cntl2.cntl_bits.phy_coma_set = NGE_CLEAR;
1122 		/* disable auto reset coma bits */
1123 		pm_cntl2.cntl_bits.resv4 = NGE_CLEAR;
1124 		/* restore power to gated clocks */
1125 		pm_cntl2.cntl_bits.resv8_11 = NGE_CLEAR;
1126 		nge_reg_put32(ngep, NGE_PM_CNTL2, pm_cntl2.cntl_val);
1127 	}
1128 
1129 	ngep->nge_chip_state = NGE_CHIP_RESET;
1130 	return (DDI_SUCCESS);
1131 }
1132 
1133 int
1134 nge_chip_start(nge_t *ngep)
1135 {
1136 	int err;
1137 	nge_itc itc;
1138 	nge_tx_cntl tx_cntl;
1139 	nge_rx_cntrl0 rx_cntl0;
1140 	nge_rx_cntl1 rx_cntl1;
1141 	nge_tx_en tx_en;
1142 	nge_rx_en rx_en;
1143 	nge_mii_cs mii_cs;
1144 	nge_swtr_cntl swtr_cntl;
1145 	nge_rx_fifo_wm rx_fifo;
1146 	nge_intr_mask intr_mask;
1147 	nge_mintr_mask mintr_mask;
1148 	nge_dev_spec_param_t	*dev_param_p;
1149 
1150 	NGE_TRACE(("nge_chip_start($%p)", (void *)ngep));
1151 
1152 	/*
1153 	 * Setup buffer management
1154 	 */
1155 	err = nge_buff_setup(ngep);
1156 	if (err == DDI_FAILURE)
1157 		return (err);
1158 
1159 	dev_param_p = &ngep->dev_spec_param;
1160 
1161 	/*
1162 	 * Enable polling attribute
1163 	 */
1164 	mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS);
1165 	mii_cs.cs_bits.ap_paddr = ngep->phy_xmii_addr;
1166 	mii_cs.cs_bits.ap_en = NGE_SET;
1167 	mii_cs.cs_bits.ap_intv = MII_POLL_INTV;
1168 	nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val);
1169 
1170 	/*
1171 	 * Setup link
1172 	 */
1173 	(*ngep->physops->phys_update)(ngep);
1174 
1175 	/*
1176 	 * Configure the tx's parameters
1177 	 */
1178 	tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL);
1179 	if (dev_param_p->tx_pause_frame)
1180 		tx_cntl.cntl_bits.paen = NGE_SET;
1181 	else
1182 		tx_cntl.cntl_bits.paen = NGE_CLEAR;
1183 	tx_cntl.cntl_bits.retry_en = NGE_SET;
1184 	tx_cntl.cntl_bits.pad_en = NGE_SET;
1185 	tx_cntl.cntl_bits.fappend_en = NGE_SET;
1186 	tx_cntl.cntl_bits.two_def_en = NGE_SET;
1187 	tx_cntl.cntl_bits.max_retry = 15;
1188 	tx_cntl.cntl_bits.burst_en = NGE_CLEAR;
1189 	tx_cntl.cntl_bits.uflo_err_mask = NGE_CLEAR;
1190 	tx_cntl.cntl_bits.tlcol_mask = NGE_CLEAR;
1191 	tx_cntl.cntl_bits.lcar_mask = NGE_CLEAR;
1192 	tx_cntl.cntl_bits.def_mask = NGE_CLEAR;
1193 	tx_cntl.cntl_bits.exdef_mask = NGE_SET;
1194 	tx_cntl.cntl_bits.lcar_mask = NGE_SET;
1195 	tx_cntl.cntl_bits.tlcol_mask = NGE_SET;
1196 	tx_cntl.cntl_bits.uflo_err_mask = NGE_SET;
1197 	tx_cntl.cntl_bits.jam_seq_en = NGE_CLEAR;
1198 	nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
1199 
1200 
1201 	/*
1202 	 * Configure the parameters of Rx's state machine
1203 	 * Enabe the parameters:
1204 	 * 1). Pad Strip
1205 	 * 2). FCS Relay
1206 	 * 3). Pause
1207 	 * 4). Address filter
1208 	 * 5). Runt Packet receive
1209 	 * 6). Broadcast
1210 	 * 7). Receive Deferral
1211 	 *
1212 	 * Disable the following parameters for decreasing
1213 	 * the number of interrupts:
1214 	 * 1). Runt Inerrupt.
1215 	 * 2). Rx's Late Collision interrupt.
1216 	 * 3). Rx's Max length Error Interrupt.
1217 	 * 4). Rx's Length Field error Interrupt.
1218 	 * 5). Rx's FCS error interrupt.
1219 	 * 6). Rx's overflow error interrupt.
1220 	 * 7). Rx's Frame alignment error interrupt.
1221 	 */
1222 	rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
1223 	rx_cntl0.cntl_bits.padsen = NGE_CLEAR;
1224 	rx_cntl0.cntl_bits.fcsren = NGE_CLEAR;
1225 	if (dev_param_p->rx_pause_frame)
1226 		rx_cntl0.cntl_bits.paen = NGE_SET;
1227 	else
1228 		rx_cntl0.cntl_bits.paen = NGE_CLEAR;
1229 	rx_cntl0.cntl_bits.lben = NGE_CLEAR;
1230 	rx_cntl0.cntl_bits.afen = NGE_SET;
1231 	rx_cntl0.cntl_bits.runten = NGE_CLEAR;
1232 	rx_cntl0.cntl_bits.brdis = NGE_CLEAR;
1233 	rx_cntl0.cntl_bits.rdfen = NGE_CLEAR;
1234 	rx_cntl0.cntl_bits.runtm = NGE_CLEAR;
1235 	rx_cntl0.cntl_bits.slfb = NGE_CLEAR;
1236 	rx_cntl0.cntl_bits.rlcolm = NGE_CLEAR;
1237 	rx_cntl0.cntl_bits.maxerm = NGE_CLEAR;
1238 	rx_cntl0.cntl_bits.lferm = NGE_CLEAR;
1239 	rx_cntl0.cntl_bits.crcm = NGE_CLEAR;
1240 	rx_cntl0.cntl_bits.ofolm = NGE_CLEAR;
1241 	rx_cntl0.cntl_bits.framerm = NGE_CLEAR;
1242 	nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
1243 
1244 	/*
1245 	 * Configure the watermark for the rx's statemachine
1246 	 */
1247 	rx_fifo.wm_val = nge_reg_get32(ngep, NGE_RX_FIFO_WM);
1248 	rx_fifo.wm_bits.data_hwm = ngep->rx_datahwm;
1249 	rx_fifo.wm_bits.prd_lwm = ngep->rx_prdlwm;
1250 	rx_fifo.wm_bits.prd_hwm = ngep->rx_prdhwm;
1251 	nge_reg_put32(ngep, NGE_RX_FIFO_WM, rx_fifo.wm_val);
1252 
1253 	/*
1254 	 * Configure the deffer time slot for rx's state machine
1255 	 */
1256 	nge_reg_put8(ngep, NGE_RX_DEf, ngep->rx_def);
1257 
1258 	/*
1259 	 * Configure the length of rx's packet
1260 	 */
1261 	rx_cntl1.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL1);
1262 	rx_cntl1.cntl_bits.length = ngep->max_sdu;
1263 	nge_reg_put32(ngep, NGE_RX_CNTL1, rx_cntl1.cntl_val);
1264 	/*
1265 	 * Enable Tx's state machine
1266 	 */
1267 	tx_en.val = nge_reg_get8(ngep, NGE_TX_EN);
1268 	tx_en.bits.tx_en = NGE_SET;
1269 	nge_reg_put8(ngep, NGE_TX_EN, tx_en.val);
1270 
1271 	/*
1272 	 * Enable Rx's state machine
1273 	 */
1274 	rx_en.val = nge_reg_get8(ngep, NGE_RX_EN);
1275 	rx_en.bits.rx_en = NGE_SET;
1276 	nge_reg_put8(ngep, NGE_RX_EN, rx_en.val);
1277 
1278 	itc.itc_val = nge_reg_get32(ngep, NGE_SWTR_ITC);
1279 	itc.itc_bits.sw_intv = ngep->sw_intr_intv;
1280 	nge_reg_put32(ngep, NGE_SWTR_ITC, itc.itc_val);
1281 
1282 	swtr_cntl.ctrl_val = nge_reg_get8(ngep, NGE_SWTR_CNTL);
1283 	swtr_cntl.cntl_bits.sten = NGE_SET;
1284 	swtr_cntl.cntl_bits.stren = NGE_SET;
1285 	nge_reg_put32(ngep, NGE_SWTR_CNTL, swtr_cntl.ctrl_val);
1286 
1287 	/*
1288 	 * Disable all mii read/write operation Interrupt
1289 	 */
1290 	mintr_mask.mask_val = nge_reg_get8(ngep, NGE_MINTR_MASK);
1291 	mintr_mask.mask_bits.mrei = NGE_CLEAR;
1292 	mintr_mask.mask_bits.mcc2 = NGE_CLEAR;
1293 	mintr_mask.mask_bits.mcc1 = NGE_CLEAR;
1294 	mintr_mask.mask_bits.mapi = NGE_SET;
1295 	mintr_mask.mask_bits.mpdi = NGE_SET;
1296 	nge_reg_put8(ngep, NGE_MINTR_MASK, mintr_mask.mask_val);
1297 
1298 	/*
1299 	 * Enable all interrupt event
1300 	 */
1301 	intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
1302 	intr_mask.mask_bits.reint = NGE_SET;
1303 	intr_mask.mask_bits.rcint = NGE_SET;
1304 	intr_mask.mask_bits.miss = NGE_SET;
1305 	intr_mask.mask_bits.teint = NGE_CLEAR;
1306 	intr_mask.mask_bits.tcint = NGE_SET;
1307 	intr_mask.mask_bits.stint = NGE_CLEAR;
1308 	intr_mask.mask_bits.mint = NGE_CLEAR;
1309 	intr_mask.mask_bits.rfint = NGE_CLEAR;
1310 	intr_mask.mask_bits.tfint = NGE_CLEAR;
1311 	intr_mask.mask_bits.feint = NGE_SET;
1312 	intr_mask.mask_bits.resv10 = NGE_CLEAR;
1313 	intr_mask.mask_bits.resv11 = NGE_CLEAR;
1314 	intr_mask.mask_bits.resv12 = NGE_CLEAR;
1315 	intr_mask.mask_bits.resv13 = NGE_CLEAR;
1316 	intr_mask.mask_bits.phyint = NGE_CLEAR;
1317 	ngep->intr_masks = intr_mask.mask_val;
1318 	nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
1319 	ngep->nge_chip_state = NGE_CHIP_RUNNING;
1320 	return (DDI_SUCCESS);
1321 }
1322 
1323 /*
1324  * nge_chip_sync() -- program the chip with the unicast MAC address,
1325  * the multicast hash table, the required level of promiscuity.
1326  */
1327 void
1328 nge_chip_sync(nge_t *ngep)
1329 {
1330 	uint8_t i;
1331 	uint64_t macaddr;
1332 	uint64_t mul_addr;
1333 	uint64_t mul_mask;
1334 	nge_rx_cntrl0 rx_cntl;
1335 	nge_uni_addr1 uni_adr1;
1336 
1337 	NGE_TRACE(("nge_chip_sync($%p)", (void *)ngep));
1338 
1339 	macaddr = 0x0ull;
1340 	mul_addr = 0x0ull;
1341 	mul_mask = 0x0ull;
1342 	rx_cntl.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
1343 
1344 	if (ngep->promisc) {
1345 		rx_cntl.cntl_bits.afen = NGE_CLEAR;
1346 		rx_cntl.cntl_bits.brdis = NGE_SET;
1347 	} else {
1348 		rx_cntl.cntl_bits.afen = NGE_SET;
1349 		rx_cntl.cntl_bits.brdis = NGE_CLEAR;
1350 	}
1351 
1352 	/*
1353 	 * Transform the MAC address from host to chip format, the unicast
1354 	 * MAC address(es) ...
1355 	 */
1356 	for (i = ETHERADDRL, macaddr = 0ull; i != 0; --i) {
1357 		macaddr |= ngep->cur_uni_addr.addr[i-1];
1358 		macaddr <<= (i > 1) ? 8 : 0;
1359 	}
1360 
1361 	nge_reg_put32(ngep, NGE_UNI_ADDR0, (uint32_t)macaddr);
1362 	macaddr = macaddr >>32;
1363 	uni_adr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1);
1364 	uni_adr1.addr_bits.addr = (uint16_t)macaddr;
1365 	uni_adr1.addr_bits.resv16_31 = (uint16_t)0;
1366 	nge_reg_put32(ngep, NGE_UNI_ADDR1, uni_adr1.addr_val);
1367 
1368 	/*
1369 	 * Reprogram the  multicast address table ...
1370 	 */
1371 	for (i = ETHERADDRL, mul_addr = 0ull; i != 0; --i) {
1372 		mul_addr |= ngep->cur_mul_addr.addr[i-1];
1373 		mul_addr <<= (i > 1) ? 8 : 0;
1374 		mul_mask |= ngep->cur_mul_mask.addr[i-1];
1375 		mul_mask <<= (i > 1) ? 8 : 0;
1376 	}
1377 	nge_reg_put32(ngep, NGE_MUL_ADDR0, (uint32_t)mul_addr);
1378 	mul_addr >>= 32;
1379 	nge_reg_put32(ngep, NGE_MUL_ADDR1, mul_addr);
1380 	nge_reg_put32(ngep, NGE_MUL_MASK, (uint32_t)mul_mask);
1381 	mul_mask >>= 32;
1382 	nge_reg_put32(ngep, NGE_MUL_MASK1, mul_mask);
1383 	/*
1384 	 * Set or clear the PROMISCUOUS mode bit
1385 	 */
1386 	nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl.cntl_val);
1387 	/*
1388 	 * For internal PHY loopback, the link will
1389 	 * not be up, so it need to sync mac modes directly.
1390 	 */
1391 	if (ngep->param_loop_mode == NGE_LOOP_INTERNAL_PHY)
1392 		nge_sync_mac_modes(ngep);
1393 }
1394 
1395 static void
1396 nge_chip_err(nge_t *ngep)
1397 {
1398 	nge_reg010 reg010_ins;
1399 	nge_sw_statistics_t *psw_stat;
1400 	nge_intr_mask intr_mask;
1401 
1402 	NGE_TRACE(("nge_chip_err($%p)", (void *)ngep));
1403 
1404 	psw_stat = (nge_sw_statistics_t *)&ngep->statistics.sw_statistics;
1405 	reg010_ins.reg010_val = nge_reg_get32(ngep, NGE_REG010);
1406 	if (reg010_ins.reg010_bits.resv0)
1407 		psw_stat->fe_err.tso_err_mss ++;
1408 
1409 	if (reg010_ins.reg010_bits.resv1)
1410 		psw_stat->fe_err.tso_dis ++;
1411 
1412 	if (reg010_ins.reg010_bits.resv2)
1413 		psw_stat->fe_err.tso_err_nosum ++;
1414 
1415 	if (reg010_ins.reg010_bits.resv3)
1416 		psw_stat->fe_err.tso_err_hov ++;
1417 
1418 	if (reg010_ins.reg010_bits.resv4)
1419 		psw_stat->fe_err.tso_err_huf ++;
1420 
1421 	if (reg010_ins.reg010_bits.resv5)
1422 		psw_stat->fe_err.tso_err_l2 ++;
1423 
1424 	if (reg010_ins.reg010_bits.resv6)
1425 		psw_stat->fe_err.tso_err_ip ++;
1426 
1427 	if (reg010_ins.reg010_bits.resv7)
1428 		psw_stat->fe_err.tso_err_l4 ++;
1429 
1430 	if (reg010_ins.reg010_bits.resv8)
1431 		psw_stat->fe_err.tso_err_tcp ++;
1432 
1433 	if (reg010_ins.reg010_bits.resv9)
1434 		psw_stat->fe_err.hsum_err_ip ++;
1435 
1436 	if (reg010_ins.reg010_bits.resv10)
1437 		psw_stat->fe_err.hsum_err_l4 ++;
1438 
1439 	if (reg010_ins.reg010_val != 0) {
1440 
1441 		/*
1442 		 * Fatal error is triggered by malformed driver commands.
1443 		 * Disable unless debugging.
1444 		 */
1445 		intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
1446 		intr_mask.mask_bits.feint = NGE_CLEAR;
1447 		nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
1448 		ngep->intr_masks = intr_mask.mask_val;
1449 
1450 	}
1451 }
1452 
1453 static void
1454 nge_sync_mac_modes(nge_t *ngep)
1455 {
1456 	nge_tx_def tx_def;
1457 	nge_tx_fifo_wm tx_fifo;
1458 	nge_bkoff_cntl bk_cntl;
1459 	nge_mac2phy m2p;
1460 	nge_rx_cntrl0 rx_cntl0;
1461 	nge_tx_cntl tx_cntl;
1462 	nge_dev_spec_param_t	*dev_param_p;
1463 
1464 	dev_param_p = &ngep->dev_spec_param;
1465 
1466 	tx_def.def_val = nge_reg_get32(ngep, NGE_TX_DEF);
1467 	m2p.m2p_val = nge_reg_get32(ngep, NGE_MAC2PHY);
1468 	tx_fifo.wm_val = nge_reg_get32(ngep, NGE_TX_FIFO_WM);
1469 	bk_cntl.cntl_val = nge_reg_get32(ngep, NGE_BKOFF_CNTL);
1470 	bk_cntl.bkoff_bits.rseed = BKOFF_RSEED;
1471 	switch (ngep->param_link_speed) {
1472 	case 10:
1473 		m2p.m2p_bits.speed = low_speed;
1474 		tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
1475 		if (ngep->phy_mode == RGMII_IN) {
1476 			tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100;
1477 			tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
1478 		} else {
1479 			tx_def.def_bits.if_def = TX_TIFG_MII;
1480 			tx_def.def_bits.ifg2_def = TX_IFG2_MII;
1481 		}
1482 		tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII;
1483 		bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII;
1484 		break;
1485 
1486 	case 100:
1487 		m2p.m2p_bits.speed = fast_speed;
1488 		tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
1489 		if (ngep->phy_mode == RGMII_IN) {
1490 			tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100;
1491 			tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
1492 		} else {
1493 			tx_def.def_bits.if_def = TX_TIFG_MII;
1494 			tx_def.def_bits.ifg2_def = TX_IFG2_MII;
1495 		}
1496 		tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII;
1497 		bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII;
1498 		break;
1499 
1500 	case 1000:
1501 		m2p.m2p_bits.speed = giga_speed;
1502 		tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
1503 		if (ngep->param_link_duplex == LINK_DUPLEX_FULL) {
1504 			tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000;
1505 			tx_def.def_bits.if_def = TX_IFG_RGMII_1000_FD;
1506 		} else {
1507 			tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000;
1508 			tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
1509 		}
1510 
1511 		tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_GMII;
1512 		bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_GMII;
1513 		break;
1514 	}
1515 
1516 	if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 ||
1517 	    ngep->chipinfo.device == DEVICE_ID_MCP55_372) {
1518 		m2p.m2p_bits.phyintr = NGE_CLEAR;
1519 		m2p.m2p_bits.phyintrlvl = NGE_CLEAR;
1520 	}
1521 	if (ngep->param_link_duplex == LINK_DUPLEX_HALF) {
1522 		m2p.m2p_bits.hdup_en = NGE_SET;
1523 	}
1524 	else
1525 		m2p.m2p_bits.hdup_en = NGE_CLEAR;
1526 	nge_reg_put32(ngep, NGE_MAC2PHY, m2p.m2p_val);
1527 	nge_reg_put32(ngep, NGE_TX_DEF, tx_def.def_val);
1528 
1529 	tx_fifo.wm_bits.data_lwm = TX_FIFO_DATA_LWM;
1530 	tx_fifo.wm_bits.prd_lwm = TX_FIFO_PRD_LWM;
1531 	tx_fifo.wm_bits.uprd_hwm = TX_FIFO_PRD_HWM;
1532 	tx_fifo.wm_bits.fb_wm = TX_FIFO_TBFW;
1533 	nge_reg_put32(ngep, NGE_TX_FIFO_WM, tx_fifo.wm_val);
1534 
1535 	nge_reg_put32(ngep, NGE_BKOFF_CNTL, bk_cntl.cntl_val);
1536 
1537 	rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
1538 	if (ngep->param_link_rx_pause && dev_param_p->rx_pause_frame) {
1539 		if (rx_cntl0.cntl_bits.paen == NGE_CLEAR) {
1540 			rx_cntl0.cntl_bits.paen = NGE_SET;
1541 			nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
1542 	}
1543 	} else {
1544 		if (rx_cntl0.cntl_bits.paen == NGE_SET) {
1545 			rx_cntl0.cntl_bits.paen = NGE_CLEAR;
1546 			nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
1547 		}
1548 	}
1549 
1550 	tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL);
1551 	if (ngep->param_link_tx_pause && dev_param_p->tx_pause_frame) {
1552 		if (tx_cntl.cntl_bits.paen == NGE_CLEAR) {
1553 			tx_cntl.cntl_bits.paen = NGE_SET;
1554 			nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
1555 		}
1556 	} else {
1557 		if (tx_cntl.cntl_bits.paen == NGE_SET) {
1558 			tx_cntl.cntl_bits.paen = NGE_CLEAR;
1559 			nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
1560 		}
1561 	}
1562 }
1563 
1564 /*
1565  * Handler for hardware link state change.
1566  *
1567  * When this routine is called, the hardware link state has changed
1568  * and the new state is reflected in the param_* variables.  Here
1569  * we must update the softstate, reprogram the MAC to match, and
1570  * record the change in the log and/or on the console.
1571  */
1572 static void
1573 nge_factotum_link_handler(nge_t *ngep)
1574 {
1575 	/*
1576 	 * Update the s/w link_state
1577 	 */
1578 	if (ngep->param_link_up)
1579 		ngep->link_state = LINK_STATE_UP;
1580 	else
1581 		ngep->link_state = LINK_STATE_DOWN;
1582 
1583 	/*
1584 	 * Reprogram the MAC modes to match
1585 	 */
1586 	nge_sync_mac_modes(ngep);
1587 }
1588 
1589 static boolean_t
1590 nge_factotum_link_check(nge_t *ngep)
1591 {
1592 	boolean_t lchg;
1593 	boolean_t check;
1594 
1595 	ASSERT(mutex_owned(ngep->genlock));
1596 
1597 	(*ngep->physops->phys_check)(ngep);
1598 	switch (ngep->link_state) {
1599 	case LINK_STATE_UP:
1600 		lchg = (ngep->param_link_up == B_FALSE);
1601 		check = (ngep->param_link_up == B_FALSE);
1602 		break;
1603 
1604 	case LINK_STATE_DOWN:
1605 		lchg = (ngep->param_link_up == B_TRUE);
1606 		check = (ngep->param_link_up == B_TRUE);
1607 		break;
1608 
1609 	default:
1610 		check = B_TRUE;
1611 		break;
1612 	}
1613 
1614 	/*
1615 	 * If <check> is false, we're sure the link hasn't changed.
1616 	 * If true, however, it's not yet definitive; we have to call
1617 	 * nge_phys_check() to determine whether the link has settled
1618 	 * into a new state yet ... and if it has, then call the link
1619 	 * state change handler.But when the chip is 5700 in Dell 6650
1620 	 * ,even if check is false, the link may have changed.So we
1621 	 * have to call nge_phys_check() to determine the link state.
1622 	 */
1623 	if (check)
1624 		nge_factotum_link_handler(ngep);
1625 
1626 	return (lchg);
1627 }
1628 
1629 /*
1630  * Factotum routine to check for Tx stall, using the 'watchdog' counter
1631  */
1632 static boolean_t nge_factotum_stall_check(nge_t *ngep);
1633 
1634 static boolean_t
1635 nge_factotum_stall_check(nge_t *ngep)
1636 {
1637 	uint32_t dogval;
1638 	/*
1639 	 * Specific check for Tx stall ...
1640 	 *
1641 	 * The 'watchdog' counter is incremented whenever a packet
1642 	 * is queued, reset to 1 when some (but not all) buffers
1643 	 * are reclaimed, reset to 0 (disabled) when all buffers
1644 	 * are reclaimed, and shifted left here.  If it exceeds the
1645 	 * threshold value, the chip is assumed to have stalled and
1646 	 * is put into the ERROR state.  The factotum will then reset
1647 	 * it on the next pass.
1648 	 *
1649 	 * All of which should ensure that we don't get into a state
1650 	 * where packets are left pending indefinitely!
1651 	 */
1652 	dogval = nge_atomic_shl32(&ngep->watchdog, 1);
1653 	if (dogval < nge_watchdog_count) {
1654 		ngep->stall_cknum = 0;
1655 	} else {
1656 		ngep->stall_cknum++;
1657 	}
1658 	if (ngep->stall_cknum < 16) {
1659 		return (B_FALSE);
1660 	} else {
1661 		ngep->stall_cknum = 0;
1662 		ngep->statistics.sw_statistics.tx_stall++;
1663 		return (B_TRUE);
1664 	}
1665 }
1666 
1667 
1668 
1669 /*
1670  * The factotum is woken up when there's something to do that we'd rather
1671  * not do from inside a hardware interrupt handler or high-level cyclic.
1672  * Its two main tasks are:
1673  *	reset & restart the chip after an error
1674  *	check the link status whenever necessary
1675  */
1676 /* ARGSUSED */
1677 uint_t
1678 nge_chip_factotum(caddr_t args1, caddr_t args2)
1679 {
1680 	uint_t result;
1681 	nge_t *ngep;
1682 	boolean_t err;
1683 	boolean_t linkchg;
1684 
1685 	ngep = (nge_t *)args1;
1686 
1687 	NGE_TRACE(("nge_chip_factotum($%p)", (void *)ngep));
1688 
1689 	mutex_enter(ngep->softlock);
1690 	if (ngep->factotum_flag == 0) {
1691 		mutex_exit(ngep->softlock);
1692 		return (DDI_INTR_UNCLAIMED);
1693 	}
1694 	ngep->factotum_flag = 0;
1695 	mutex_exit(ngep->softlock);
1696 	err = B_FALSE;
1697 	linkchg = B_FALSE;
1698 	result = DDI_INTR_CLAIMED;
1699 
1700 	mutex_enter(ngep->genlock);
1701 	switch (ngep->nge_chip_state) {
1702 	default:
1703 		break;
1704 
1705 	case NGE_CHIP_RUNNING:
1706 		linkchg = nge_factotum_link_check(ngep);
1707 		err = nge_factotum_stall_check(ngep);
1708 		break;
1709 
1710 	case NGE_CHIP_FAULT:
1711 		(void) nge_restart(ngep);
1712 		NGE_REPORT((ngep, "automatic recovery activated"));
1713 		break;
1714 	}
1715 
1716 	if (err)
1717 		(void) nge_chip_stop(ngep, B_TRUE);
1718 	mutex_exit(ngep->genlock);
1719 
1720 	/*
1721 	 * If the link state changed, tell the world about it (if
1722 	 * this version of MAC supports link state notification).
1723 	 * Note: can't do this while still holding the mutex.
1724 	 */
1725 	if (linkchg)
1726 		mac_link_update(ngep->mh, ngep->link_state);
1727 
1728 	return (result);
1729 
1730 }
1731 
1732 static void
1733 nge_intr_handle(nge_t *ngep, nge_intr_src *pintr_src)
1734 {
1735 	boolean_t brx;
1736 	boolean_t btx;
1737 	nge_mintr_src mintr_src;
1738 
1739 	brx = B_FALSE;
1740 	btx = B_FALSE;
1741 	ngep->statistics.sw_statistics.intr_count++;
1742 	ngep->statistics.sw_statistics.intr_lval = pintr_src->intr_val;
1743 	brx = (pintr_src->int_bits.reint | pintr_src->int_bits.miss
1744 	    | pintr_src->int_bits.rcint | pintr_src->int_bits.stint)
1745 	    != 0 ? B_TRUE : B_FALSE;
1746 	if (pintr_src->int_bits.reint)
1747 		ngep->statistics.sw_statistics.rx_err++;
1748 	if (pintr_src->int_bits.miss)
1749 		ngep->statistics.sw_statistics.rx_nobuffer++;
1750 
1751 	btx = (pintr_src->int_bits.teint | pintr_src->int_bits.tcint)
1752 	    != 0 ? B_TRUE : B_FALSE;
1753 	if (pintr_src->int_bits.stint && ngep->poll)
1754 		ngep->stint_count ++;
1755 	if (ngep->poll && (ngep->stint_count % ngep->param_tx_n_intr == 0))
1756 		btx = B_TRUE;
1757 	if (btx)
1758 		nge_tx_recycle(ngep, B_TRUE);
1759 	if (brx)
1760 		nge_receive(ngep);
1761 	if (pintr_src->int_bits.teint)
1762 		ngep->statistics.sw_statistics.tx_stop_err++;
1763 	if (ngep->intr_moderation && brx) {
1764 		if (ngep->poll) {
1765 			if (ngep->recv_count < ngep->param_rx_intr_hwater) {
1766 				ngep->quiet_time++;
1767 				if (ngep->quiet_time ==
1768 				    ngep->param_poll_quiet_time) {
1769 					ngep->poll = B_FALSE;
1770 					ngep->quiet_time = 0;
1771 					ngep->stint_count = 0;
1772 					nge_tx_recycle(ngep, B_TRUE);
1773 				}
1774 			} else
1775 				ngep->quiet_time = 0;
1776 		} else {
1777 			if (ngep->recv_count > ngep->param_rx_intr_lwater) {
1778 				ngep->busy_time++;
1779 				if (ngep->busy_time ==
1780 				    ngep->param_poll_busy_time) {
1781 					ngep->poll = B_TRUE;
1782 					ngep->busy_time = 0;
1783 				}
1784 			} else
1785 				ngep->busy_time = 0;
1786 		}
1787 	}
1788 	ngep->recv_count = 0;
1789 	if (pintr_src->int_bits.feint)
1790 		nge_chip_err(ngep);
1791 	/* link interrupt, check the link state */
1792 	if (pintr_src->int_bits.mint) {
1793 		mintr_src.src_val = nge_reg_get32(ngep, NGE_MINTR_SRC);
1794 		nge_reg_put32(ngep, NGE_MINTR_SRC, mintr_src.src_val);
1795 		nge_wake_factotum(ngep);
1796 	}
1797 }
1798 
1799 /*
1800  *	nge_chip_intr() -- handle chip interrupts
1801  */
1802 /* ARGSUSED */
1803 uint_t
1804 nge_chip_intr(caddr_t arg1, caddr_t arg2)
1805 {
1806 	nge_t *ngep = (nge_t *)arg1;
1807 	nge_intr_src intr_src;
1808 	nge_intr_mask intr_mask;
1809 
1810 	mutex_enter(ngep->genlock);
1811 
1812 	if (ngep->suspended) {
1813 		mutex_exit(ngep->genlock);
1814 		return (DDI_INTR_UNCLAIMED);
1815 	}
1816 
1817 	/*
1818 	 * Check whether chip's says it's asserting #INTA;
1819 	 * if not, don't process or claim the interrupt.
1820 	 */
1821 	intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC);
1822 	if (intr_src.intr_val == 0) {
1823 		mutex_exit(ngep->genlock);
1824 		return (DDI_INTR_UNCLAIMED);
1825 	}
1826 	/*
1827 	 * Ack the interrupt
1828 	 */
1829 	nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val);
1830 
1831 	if (ngep->nge_chip_state != NGE_CHIP_RUNNING) {
1832 		mutex_exit(ngep->genlock);
1833 		return (DDI_INTR_CLAIMED);
1834 	}
1835 	nge_intr_handle(ngep, &intr_src);
1836 	if (ngep->poll && !ngep->ch_intr_mode) {
1837 		intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
1838 		intr_mask.mask_bits.stint = NGE_SET;
1839 		intr_mask.mask_bits.rcint = NGE_CLEAR;
1840 		intr_mask.mask_bits.reint = NGE_CLEAR;
1841 		intr_mask.mask_bits.tcint = NGE_CLEAR;
1842 		intr_mask.mask_bits.teint = NGE_CLEAR;
1843 		nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
1844 		ngep->ch_intr_mode = B_TRUE;
1845 	} else if ((ngep->ch_intr_mode) && (!ngep->poll)) {
1846 		nge_reg_put32(ngep, NGE_INTR_MASK, ngep->intr_masks);
1847 		ngep->ch_intr_mode = B_FALSE;
1848 	}
1849 	mutex_exit(ngep->genlock);
1850 	return (DDI_INTR_CLAIMED);
1851 }
1852 
1853 static enum ioc_reply
1854 nge_pp_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp)
1855 {
1856 	int err;
1857 	uint64_t sizemask;
1858 	uint64_t mem_va;
1859 	uint64_t maxoff;
1860 	boolean_t peek;
1861 	nge_peekpoke_t *ppd;
1862 	int (*ppfn)(nge_t *ngep, nge_peekpoke_t *ppd);
1863 
1864 	switch (cmd) {
1865 	default:
1866 		return (IOC_INVAL);
1867 
1868 	case NGE_PEEK:
1869 		peek = B_TRUE;
1870 		break;
1871 
1872 	case NGE_POKE:
1873 		peek = B_FALSE;
1874 		break;
1875 	}
1876 
1877 	/*
1878 	 * Validate format of ioctl
1879 	 */
1880 	if (iocp->ioc_count != sizeof (nge_peekpoke_t))
1881 		return (IOC_INVAL);
1882 	if (mp->b_cont == NULL)
1883 		return (IOC_INVAL);
1884 	ppd = (nge_peekpoke_t *)mp->b_cont->b_rptr;
1885 
1886 	/*
1887 	 * Validate request parameters
1888 	 */
1889 	switch (ppd->pp_acc_space) {
1890 	default:
1891 		return (IOC_INVAL);
1892 
1893 	case NGE_PP_SPACE_CFG:
1894 		/*
1895 		 * Config space
1896 		 */
1897 		sizemask = 8|4|2|1;
1898 		mem_va = 0;
1899 		maxoff = PCI_CONF_HDR_SIZE;
1900 		ppfn = peek ? nge_chip_peek_cfg : nge_chip_poke_cfg;
1901 		break;
1902 
1903 	case NGE_PP_SPACE_REG:
1904 		/*
1905 		 * Memory-mapped I/O space
1906 		 */
1907 		sizemask = 8|4|2|1;
1908 		mem_va = 0;
1909 		maxoff = NGE_REG_SIZE;
1910 		ppfn = peek ? nge_chip_peek_reg : nge_chip_poke_reg;
1911 		break;
1912 
1913 	case NGE_PP_SPACE_MII:
1914 		sizemask = 4|2|1;
1915 		mem_va = 0;
1916 		maxoff = NGE_MII_SIZE;
1917 		ppfn = peek ? nge_chip_peek_mii : nge_chip_poke_mii;
1918 		break;
1919 
1920 	case NGE_PP_SPACE_SEEPROM:
1921 		sizemask = 4|2|1;
1922 		mem_va = 0;
1923 		maxoff = NGE_SEEROM_SIZE;
1924 		ppfn = peek ? nge_chip_peek_seeprom : nge_chip_poke_seeprom;
1925 		break;
1926 	}
1927 
1928 	switch (ppd->pp_acc_size) {
1929 	default:
1930 		return (IOC_INVAL);
1931 
1932 	case 8:
1933 	case 4:
1934 	case 2:
1935 	case 1:
1936 		if ((ppd->pp_acc_size & sizemask) == 0)
1937 			return (IOC_INVAL);
1938 		break;
1939 	}
1940 
1941 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
1942 		return (IOC_INVAL);
1943 
1944 	if (ppd->pp_acc_offset >= maxoff)
1945 		return (IOC_INVAL);
1946 
1947 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
1948 		return (IOC_INVAL);
1949 
1950 	/*
1951 	 * All OK - go do it!
1952 	 */
1953 	ppd->pp_acc_offset += mem_va;
1954 	if (ppfn)
1955 		err = (*ppfn)(ngep, ppd);
1956 	if (err != DDI_SUCCESS)
1957 		return (IOC_INVAL);
1958 	return (peek ? IOC_REPLY : IOC_ACK);
1959 }
1960 
1961 static enum ioc_reply nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp,
1962 					struct iocblk *iocp);
1963 #pragma	no_inline(nge_diag_ioctl)
1964 
1965 static enum ioc_reply
1966 nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp)
1967 {
1968 	ASSERT(mutex_owned(ngep->genlock));
1969 
1970 	switch (cmd) {
1971 	default:
1972 		nge_error(ngep, "nge_diag_ioctl: invalid cmd 0x%x", cmd);
1973 		return (IOC_INVAL);
1974 
1975 	case NGE_DIAG:
1976 		return (IOC_ACK);
1977 
1978 	case NGE_PEEK:
1979 	case NGE_POKE:
1980 		return (nge_pp_ioctl(ngep, cmd, mp, iocp));
1981 
1982 	case NGE_PHY_RESET:
1983 		return (IOC_RESTART_ACK);
1984 
1985 	case NGE_SOFT_RESET:
1986 	case NGE_HARD_RESET:
1987 		return (IOC_ACK);
1988 	}
1989 
1990 	/* NOTREACHED */
1991 }
1992 
1993 enum ioc_reply
1994 nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp)
1995 {
1996 	int cmd;
1997 
1998 	ASSERT(mutex_owned(ngep->genlock));
1999 
2000 	cmd = iocp->ioc_cmd;
2001 
2002 	switch (cmd) {
2003 	default:
2004 		return (IOC_INVAL);
2005 
2006 	case NGE_DIAG:
2007 	case NGE_PEEK:
2008 	case NGE_POKE:
2009 	case NGE_PHY_RESET:
2010 	case NGE_SOFT_RESET:
2011 	case NGE_HARD_RESET:
2012 #if	NGE_DEBUGGING
2013 		return (nge_diag_ioctl(ngep, cmd, mp, iocp));
2014 #else
2015 		return (IOC_INVAL);
2016 #endif
2017 
2018 	case NGE_MII_READ:
2019 	case NGE_MII_WRITE:
2020 		return (IOC_INVAL);
2021 
2022 #if	NGE_SEE_IO32
2023 	case NGE_SEE_READ:
2024 	case NGE_SEE_WRITE:
2025 		return (IOC_INVAL);
2026 #endif
2027 
2028 #if	NGE_FLASH_IO32
2029 	case NGE_FLASH_READ:
2030 	case NGE_FLASH_WRITE:
2031 		return (IOC_INVAL);
2032 #endif
2033 	}
2034 }
2035