1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NGE_H 28 #define _SYS_NGE_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 37 #include <sys/types.h> 38 #include <sys/stream.h> 39 #include <sys/strsun.h> 40 #include <sys/strsubr.h> 41 #include <sys/stat.h> 42 #include <sys/pci.h> 43 #include <sys/note.h> 44 #include <sys/modctl.h> 45 #include <sys/kstat.h> 46 #include <sys/ethernet.h> 47 #include <sys/pattr.h> 48 #include <sys/errno.h> 49 #include <sys/dlpi.h> 50 #include <sys/devops.h> 51 #include <sys/debug.h> 52 #include <sys/conf.h> 53 #include <sys/callb.h> 54 55 #include <netinet/ip6.h> 56 57 #include <inet/common.h> 58 #include <inet/ip.h> 59 #include <netinet/udp.h> 60 #include <inet/mi.h> 61 #include <inet/nd.h> 62 63 #include <sys/ddi.h> 64 #include <sys/sunddi.h> 65 66 #include <sys/mac.h> 67 #include <sys/mac_ether.h> 68 69 /* 70 * Reconfiguring the network devices requires the net_config privilege 71 * in Solaris 10+. 72 */ 73 extern int secpolicy_net_config(const cred_t *, boolean_t); 74 75 #include <sys/netlb.h> 76 #include <sys/miiregs.h> 77 78 #include "nge_chip.h" 79 80 #define PIO_ADDR(ngep, offset) ((void *)((caddr_t)(ngep)->io_regs+(offset))) 81 /* 82 * Copy an ethernet address 83 */ 84 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL) 85 #define ether_eq(a, b) (bcmp((caddr_t)(a), (caddr_t)(b), (ETHERADDRL)) == 0) 86 87 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 88 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 89 #define UPORDOWN(x) ((x) ? "up" : "down") 90 91 #define NGE_DRIVER_NAME "nge" 92 93 /* 94 * 'Progress' bit flags ... 95 */ 96 #define PROGRESS_CFG 0x0001 /* config space mapped */ 97 #define PROGRESS_REGS 0x0002 /* registers mapped */ 98 #define PROGRESS_BUFS 0x0004 /* registers mapped */ 99 #define PROGRESS_RESCHED 0x0008 /* resched softint registered */ 100 #define PROGRESS_FACTOTUM 0x0010 /* factotum softint registered */ 101 #define PROGRESS_SWINT 0x0020 /* s/w interrupt registered */ 102 #define PROGRESS_INTR 0x0040 /* h/w interrupt registered */ 103 /* and mutexen initialised */ 104 #define PROGRESS_HWINT 0x0080 105 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 106 #define PROGRESS_NDD 0x0200 /* NDD parameters set up */ 107 #define PROGRESS_KSTATS 0x0400 /* kstats created */ 108 #define PROGRESS_READY 0x0800 /* ready for work */ 109 110 #define NGE_HW_ERR 0x00 111 #define NGE_HW_LINK 0x01 112 #define NGE_HW_BM 0x02 113 #define NGE_HW_RCHAN 0x03 114 #define NGE_HW_TCHAN 0x04 115 #define NGE_HW_ROM 0x05 116 #define NGE_SW_PROBLEM_ID 0x06 117 118 119 /* 120 * NOTES: 121 * 122 * #defines: 123 * 124 * NGE_PCI_CONFIG_RNUMBER and NGE_PCI_OPREGS_RNUMBER are the 125 * register-set numbers to use for the config space registers 126 * and the operating registers respectively. On an OBP-based 127 * machine, regset 0 refers to CONFIG space, and regset 1 will 128 * be the operating registers in MEMORY space. If an expansion 129 * ROM is fitted, it may appear as a further register set. 130 * 131 * NGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used 132 * for the data buffers. The descriptors are always set up 133 * in CONSISTENT mode. 134 * 135 * NGE_HEADROOM defines how much space we'll leave in allocated 136 * mblks before the first valid data byte. This should be chosen 137 * to be 2 modulo 4, so that once the ethernet header (14 bytes) 138 * has been stripped off, the packet data will be 4-byte aligned. 139 * The remaining space can be used by upstream modules to prepend 140 * any headers required. 141 */ 142 143 144 #define NGE_PCI_OPREGS_RNUMBER 1 145 #define NGE_DMA_MODE DDI_DMA_STREAMING 146 #define NGE_HEADROOM 6 147 #define ETHER_HEAD_LEN 14 148 #ifndef VTAG_SIZE 149 #define VTAG_SIZE 4 150 #endif 151 152 #define NGE_HALFTICK 268435456LL /* 2**28 ns! */ 153 #define NGE_CYCLIC_PERIOD (4*NGE_HALFTICK) /* ~0.5s */ 154 155 #define NGE_DEFAULT_MTU 1500 156 #define NGE_DEFAULT_SDU 1518 157 #define NGE_MTU_2500 2500 158 #define NGE_MTU_4500 4500 159 #define NGE_MAX_MTU 9000 160 #define NGE_MAX_SDU 9018 161 162 #define NGE_DESC_MIN 0x200 163 164 #define NGE_STD_BUFSZ 1792 165 #define NGE_JB2500_BUFSZ (3*1024) 166 #define NGE_JB4500_BUFSZ (5*1024) 167 #define NGE_JB9000_BUFSZ (9*1024) 168 169 #define NGE_SEND_SLOTS_DESC_1024 1024 170 #define NGE_SEND_SLOTS_DESC_3072 3072 171 #define NGE_SEND_JB2500_SLOTS_DESC 3072 172 #define NGE_SEND_JB4500_SLOTS_DESC 2048 173 #define NGE_SEND_JB9000_SLOTS_DESC 1024 174 #define NGE_SEND_LOWMEM_SLOTS_DESC 1024 175 #define NGE_SEND_SLOTS_BUF 3072 176 177 #define NGE_RECV_SLOTS_DESC_1024 1024 178 #define NGE_RECV_SLOTS_DESC_3072 3072 179 #define NGE_RECV_JB2500_SLOTS_DESC 3072 180 #define NGE_RECV_JB4500_SLOTS_DESC 2048 181 #define NGE_RECV_JB9000_SLOTS_DESC 1024 182 #define NGE_RECV_LOWMEM_SLOTS_DESC 1024 183 #define NGE_RECV_SLOTS_BUF 6144 184 185 #define NGE_SPLIT_32 32 186 #define NGE_SPLIT_96 96 187 #define NGE_SPLIT_256 256 188 189 #define NGE_RX_COPY_SIZE 512 190 #define NGE_TX_COPY_SIZE 512 191 #define NGE_MAP_FRAGS 3 192 #define NGE_MAX_COOKIES 3 193 #define NGE_MAX_DMA_HDR (4*1024) 194 195 /* Used by interrupt moderation */ 196 #define NGE_POLL_QUIET_TIME 100 197 #define NGE_POLL_BUSY_TIME 2 198 #define NGE_TX_N_INTR 128 199 200 /* 201 * NGE-specific ioctls ... 202 */ 203 #define NGE_IOC ((((('N' << 8) + 'G') << 8) + 'E') << 8) 204 205 /* 206 * PHY register read/write ioctls, used by cable test software 207 */ 208 #define NGE_MII_READ (NGE_IOC|1) 209 #define NGE_MII_WRITE (NGE_IOC|2) 210 211 /* 212 * SEEPROM read/write ioctls, for use by SEEPROM upgrade utility 213 * 214 * Note: SEEPROMs can only be accessed as 32-bit words, so <see_addr> 215 * must be a multiple of 4. Not all systems have a SEEPROM fitted! 216 */ 217 #define NGE_SEE_READ (NGE_IOC|3) 218 #define NGE_SEE_WRITE (NGE_IOC|4) 219 220 221 /* 222 * These diagnostic IOCTLS are enabled only in DEBUG drivers 223 */ 224 #define NGE_DIAG (NGE_IOC|5) /* currently a no-op */ 225 #define NGE_PEEK (NGE_IOC|6) 226 #define NGE_POKE (NGE_IOC|7) 227 #define NGE_PHY_RESET (NGE_IOC|8) 228 #define NGE_SOFT_RESET (NGE_IOC|9) 229 #define NGE_HARD_RESET (NGE_IOC|10) 230 231 232 enum NGE_HW_OP { 233 NGE_CLEAR = 0, 234 NGE_SET 235 }; 236 237 /* 238 * Required state according to GLD 239 */ 240 enum nge_mac_state { 241 NGE_MAC_UNKNOWN, 242 NGE_MAC_RESET, 243 NGE_MAC_STOPPED, 244 NGE_MAC_STARTED, 245 NGE_MAC_UNATTACH 246 }; 247 enum loop_type { 248 NGE_LOOP_NONE = 0, 249 NGE_LOOP_EXTERNAL_100, 250 NGE_LOOP_EXTERNAL_10, 251 NGE_LOOP_INTERNAL_PHY, 252 }; 253 254 /* 255 * (Internal) return values from send_msg subroutines 256 */ 257 enum send_status { 258 SEND_COPY_FAIL = -1, /* => GLD_NORESOURCES */ 259 SEND_MAP_FAIL, /* => GLD_NORESOURCES */ 260 SEND_COPY_SUCESS, /* OK, msg queued */ 261 SEND_MAP_SUCCESS /* OK, free msg */ 262 }; 263 264 265 /* 266 * NDD parameter indexes, divided into: 267 * 268 * read-only parameters describing the hardware's capabilities 269 * read-write parameters controlling the advertised capabilities 270 * read-only parameters describing the partner's capabilities 271 * read-only parameters describing the link state 272 */ 273 enum { 274 PARAM_AUTONEG_CAP, 275 PARAM_PAUSE_CAP, 276 PARAM_ASYM_PAUSE_CAP, 277 PARAM_1000FDX_CAP, 278 PARAM_1000HDX_CAP, 279 PARAM_100T4_CAP, 280 PARAM_100FDX_CAP, 281 PARAM_100HDX_CAP, 282 PARAM_10FDX_CAP, 283 PARAM_10HDX_CAP, 284 285 PARAM_ADV_AUTONEG_CAP, 286 PARAM_ADV_PAUSE_CAP, 287 PARAM_ADV_ASYM_PAUSE_CAP, 288 PARAM_ADV_1000FDX_CAP, 289 PARAM_ADV_1000HDX_CAP, 290 PARAM_ADV_100T4_CAP, 291 PARAM_ADV_100FDX_CAP, 292 PARAM_ADV_100HDX_CAP, 293 PARAM_ADV_10FDX_CAP, 294 PARAM_ADV_10HDX_CAP, 295 296 PARAM_LP_AUTONEG_CAP, 297 PARAM_LP_PAUSE_CAP, 298 PARAM_LP_ASYM_PAUSE_CAP, 299 PARAM_LP_1000FDX_CAP, 300 PARAM_LP_1000HDX_CAP, 301 PARAM_LP_100T4_CAP, 302 PARAM_LP_100FDX_CAP, 303 PARAM_LP_100HDX_CAP, 304 PARAM_LP_10FDX_CAP, 305 PARAM_LP_10HDX_CAP, 306 307 PARAM_LINK_STATUS, 308 PARAM_LINK_SPEED, 309 PARAM_LINK_DUPLEX, 310 311 PARAM_LINK_AUTONEG, 312 PARAM_LINK_RX_PAUSE, 313 PARAM_LINK_TX_PAUSE, 314 315 PARAM_LOOP_MODE, 316 PARAM_TXBCOPY_THRESHOLD, 317 PARAM_RXBCOPY_THRESHOLD, 318 PARAM_RECV_MAX_PACKET, 319 PARAM_POLL_QUIET_TIME, 320 PARAM_POLL_BUSY_TIME, 321 PARAM_RX_INTR_HWATER, 322 PARAM_RX_INTR_LWATER, 323 PARAM_TX_N_INTR, 324 325 PARAM_COUNT 326 }; 327 328 329 /* 330 * (Internal) return values from ioctl subroutines 331 */ 332 enum ioc_reply { 333 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 334 IOC_DONE, /* OK, reply sent */ 335 IOC_ACK, /* OK, just send ACK */ 336 IOC_REPLY, /* OK, just send reply */ 337 IOC_RESTART_ACK, /* OK, restart & ACK */ 338 IOC_RESTART_REPLY /* OK, restart & reply */ 339 }; 340 341 enum nge_pp_type { 342 NGE_PP_SPACE_CFG = 0, 343 NGE_PP_SPACE_REG, 344 NGE_PP_SPACE_NIC, 345 NGE_PP_SPACE_MII, 346 NGE_PP_SPACE_NGE, 347 NGE_PP_SPACE_TXDESC, 348 NGE_PP_SPACE_TXBUFF, 349 NGE_PP_SPACE_RXDESC, 350 NGE_PP_SPACE_RXBUFF, 351 NGE_PP_SPACE_STATISTICS, 352 NGE_PP_SPACE_SEEPROM, 353 NGE_PP_SPACE_FLASH 354 }; 355 356 /* 357 * Flag to kstat type 358 */ 359 enum nge_kstat_type { 360 NGE_KSTAT_RAW = 0, 361 NGE_KSTAT_STATS, 362 NGE_KSTAT_CHIPID, 363 NGE_KSTAT_DEBUG, 364 NGE_KSTAT_COUNT 365 }; 366 367 368 /* 369 * Actual state of the nvidia's chip 370 */ 371 enum nge_chip_state { 372 NGE_CHIP_FAULT = -2, /* fault, need reset */ 373 NGE_CHIP_ERROR, /* error, want reset */ 374 NGE_CHIP_INITIAL, /* Initial state only */ 375 NGE_CHIP_RESET, /* reset, need init */ 376 NGE_CHIP_STOPPED, /* Tx/Rx stopped */ 377 NGE_CHIP_RUNNING /* with interrupts */ 378 }; 379 380 enum nge_eeprom_size { 381 EEPROM_1K = 0, 382 EEPROM_2K, 383 EEPROM_4K, 384 EEPROM_8K, 385 EEPROM_16K, 386 EEPROM_32K, 387 EEPROM_64K 388 }; 389 390 enum nge_eeprom_access_wid { 391 ACCESS_8BIT = 0, 392 ACCESS_16BIT 393 }; 394 395 /* 396 * MDIO operation 397 */ 398 enum nge_mdio_operation { 399 NGE_MDIO_READ = 0, 400 NGE_MDIO_WRITE 401 }; 402 403 /* 404 * Speed selection 405 */ 406 enum nge_speed { 407 UNKOWN_SPEED = 0, 408 NGE_10M, 409 NGE_100M, 410 NGE_1000M 411 }; 412 413 /* 414 * Duplex selection 415 */ 416 enum nge_duplex { 417 UNKOWN_DUPLEX = 0, 418 NGE_HD, 419 NGE_FD 420 }; 421 422 typedef struct { 423 ether_addr_t addr; /* in canonical form */ 424 uint8_t spare; 425 uint8_t set; /* nonzero => valid */ 426 } nge_mac_addr_t; 427 428 struct nge; 429 430 /* 431 * Named Data (ND) Parameter Management Structure 432 */ 433 typedef struct { 434 int ndp_info; 435 int ndp_min; 436 int ndp_max; 437 int ndp_val; 438 char *ndp_name; 439 } nd_param_t; 440 441 442 #define CHIP_FLAG_COPPER 0x40 443 444 /* 445 * Collection of physical-layer functions to: 446 * (re)initialise the physical layer 447 * update it to match software settings 448 * check for link status change 449 */ 450 typedef struct { 451 void (*phys_restart)(struct nge *); 452 void (*phys_update)(struct nge *); 453 boolean_t (*phys_check)(struct nge *); 454 } phys_ops_t; 455 456 struct nge_see_rw { 457 uint32_t see_addr; /* Byte offset within SEEPROM */ 458 uint32_t see_data; /* Data read/data to write */ 459 }; 460 461 typedef struct { 462 uint64_t pp_acc_size; /* in bytes: 1,2,4,8 */ 463 uint64_t pp_acc_space; /* See #defines below */ 464 uint64_t pp_acc_offset; 465 uint64_t pp_acc_data; /* output for peek */ 466 /* input for poke */ 467 } nge_peekpoke_t; 468 469 typedef uintptr_t nge_regno_t; /* register # (offset) */ 470 471 typedef struct _mul_list { 472 struct _mul_list *next; 473 uint32_t ref_cnt; 474 ether_addr_t mul_addr; 475 }mul_item, *pmul_item; 476 477 /* 478 * Describes one chunk of allocated DMA-able memory 479 * 480 * In some cases, this is a single chunk as allocated from the system; 481 * but we also use this structure to represent slices carved off such 482 * a chunk. Even when we don't really need all the information, we 483 * use this structure as a convenient way of correlating the various 484 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 485 * handle+offset, etc). 486 */ 487 typedef struct dma_area 488 { 489 490 caddr_t private; /* pointer to nge */ 491 frtn_t rx_recycle; /* recycle function */ 492 mblk_t *mp; 493 ddi_acc_handle_t acc_hdl; /* handle for memory */ 494 void *mem_va; /* CPU VA of memory */ 495 uint32_t nslots; /* number of slots */ 496 uint32_t size; /* size per slot */ 497 size_t alength; /* allocated size */ 498 /* >= product of above */ 499 ddi_dma_handle_t dma_hdl; /* DMA handle */ 500 offset_t offset; /* relative to handle */ 501 ddi_dma_cookie_t cookie; /* associated cookie */ 502 uint32_t ncookies; 503 uint32_t signature; /* buffer signature */ 504 /* for deciding to free */ 505 /* or to reuse buffers */ 506 boolean_t rx_delivered; /* hold by upper layer */ 507 struct dma_area *next; 508 } dma_area_t; 509 510 #define HOST_OWN 0x00000000 511 #define CONTROLER_OWN 0x00000001 512 #define NGE_END_PACKET 0x00000002 513 514 515 typedef struct nge_dmah_node 516 { 517 struct nge_dmah_node *next; 518 ddi_dma_handle_t hndl; 519 } nge_dmah_node_t; 520 521 typedef struct nge_dmah_list 522 { 523 nge_dmah_node_t *head; 524 nge_dmah_node_t *tail; 525 } nge_dmah_list_t; 526 527 /* 528 * Software version of the Recv Descriptor 529 * There's one of these for each recv buffer (up to 512 per ring) 530 */ 531 typedef struct sw_rx_sbd { 532 533 dma_area_t desc; /* (const) related h/w */ 534 /* descriptor area */ 535 dma_area_t *bufp; /* (const) related */ 536 /* buffer area */ 537 uint8_t flags; 538 } sw_rx_sbd_t; 539 540 /* 541 * Software version of the send Buffer Descriptor 542 * There's one of these for each send buffer (up to 512 per ring) 543 */ 544 typedef struct sw_tx_sbd { 545 546 dma_area_t desc; /* (const) related h/w */ 547 /* descriptor area */ 548 dma_area_t pbuf; /* (const) related */ 549 /* buffer area */ 550 void (*tx_recycle)(struct sw_tx_sbd *); 551 uint32_t flags; 552 mblk_t *mp; /* related mblk, if any */ 553 nge_dmah_list_t mp_hndl; 554 uint32_t frags; 555 uint32_t ncookies; /* dma cookie number */ 556 557 } sw_tx_sbd_t; 558 559 /* 560 * Software Receive Buffer (Producer) Ring Control Block 561 * There's one of these for each receiver producer ring (up to 3), 562 * but each holds buffers of a different size. 563 */ 564 typedef struct buff_ring { 565 566 uint64_t nslots; /* descriptor area */ 567 struct nge *ngep; /* (const) containing */ 568 /* driver soft state */ 569 /* initialise same */ 570 uint64_t rx_hold; 571 sw_rx_sbd_t *sw_rbds; /* software descriptors */ 572 sw_rx_sbd_t *free_rbds; /* free ring */ 573 dma_area_t *free_list; /* available buffer queue */ 574 dma_area_t *recycle_list; /* recycling buffer queue */ 575 kmutex_t recycle_lock[1]; 576 uint32_t buf_sign; 577 boolean_t rx_bcopy; 578 } buff_ring_t; 579 580 /* 581 * Software Receive (Return) Ring Control Block 582 * There's one of these for each receiver return ring (up to 16). 583 */ 584 typedef struct recv_ring { 585 /* 586 * The elements flagged (const) in the comments below are 587 * set up once during initialiation and thereafter unchanged. 588 */ 589 dma_area_t desc; /* (const) related h/w */ 590 /* descriptor area */ 591 struct nge *ngep; /* (const) containing */ 592 /* driver soft state */ 593 uint16_t prod_index; /* (const) ptr to h/w */ 594 /* "producer index" */ 595 mac_resource_handle_t handle; 596 } recv_ring_t; 597 598 599 600 /* 601 * Software Send Ring Control Block 602 * There's one of these for each of (up to) 1 send rings 603 */ 604 typedef struct send_ring { 605 /* 606 * The elements flagged (const) in the comments below are 607 * set up once during initialiation and thereafter unchanged. 608 */ 609 dma_area_t desc; /* (const) related h/w */ 610 /* descriptor area */ 611 dma_area_t buf[NGE_SEND_SLOTS_BUF]; 612 /* buffer area(s) */ 613 struct nge *ngep; /* (const) containing */ 614 /* driver soft state */ 615 616 uint64_t tx_hwmark; 617 uint64_t tx_lwmark; 618 619 /* 620 * The tx_lock must be held when updating 621 * the s/w producer index 622 * (tx_next) 623 */ 624 kmutex_t tx_lock[1]; /* serialize h/w update */ 625 uint64_t tx_next; /* next slot to use */ 626 uint64_t tx_flow; 627 628 /* 629 * These counters/indexes are manipulated in the transmit 630 * path using atomics rather than mutexes for speed 631 */ 632 uint64_t tx_free; /* # of slots available */ 633 634 /* 635 * index (tc_next). 636 */ 637 kmutex_t tc_lock[1]; 638 uint64_t tc_next; /* next slot to recycle */ 639 /* ("consumer index") */ 640 641 sw_tx_sbd_t *sw_sbds; /* software descriptors */ 642 643 kmutex_t dmah_lock; 644 nge_dmah_list_t dmah_free; 645 nge_dmah_node_t dmahndl[NGE_MAX_DMA_HDR]; 646 647 } send_ring_t; 648 649 650 typedef struct { 651 uint32_t businfo; /* from private reg */ 652 uint16_t command; /* saved during attach */ 653 654 uint16_t vendor; /* vendor-id */ 655 uint16_t device; /* device-id */ 656 uint16_t subven; /* subsystem-vendor-id */ 657 uint16_t subdev; /* subsystem-id */ 658 uint8_t class_code; 659 uint8_t revision; /* revision-id */ 660 uint8_t clsize; /* cache-line-size */ 661 uint8_t latency; /* latency-timer */ 662 uint8_t flags; 663 664 uint16_t phy_type; /* Fiber module type */ 665 uint64_t hw_mac_addr; /* from chip register */ 666 nge_mac_addr_t vendor_addr; /* transform of same */ 667 } chip_info_t; 668 669 670 typedef struct { 671 offset_t index; 672 char *name; 673 } nge_ksindex_t; 674 675 typedef struct { 676 uint64_t tso_err_mss; 677 uint64_t tso_dis; 678 uint64_t tso_err_nosum; 679 uint64_t tso_err_hov; 680 uint64_t tso_err_huf; 681 uint64_t tso_err_l2; 682 uint64_t tso_err_ip; 683 uint64_t tso_err_l4; 684 uint64_t tso_err_tcp; 685 uint64_t hsum_err_ip; 686 uint64_t hsum_err_l4; 687 }fe_statistics_t; 688 689 /* 690 * statistics parameters to tune the driver 691 */ 692 typedef struct { 693 uint64_t intr_count; 694 uint64_t intr_lval; 695 uint64_t recv_realloc; 696 uint64_t poll_time; 697 uint64_t recy_free; 698 uint64_t recv_count; 699 uint64_t xmit_count; 700 uint64_t obytes; 701 uint64_t rbytes; 702 uint64_t mp_alloc_err; 703 uint64_t dma_alloc_err; 704 uint64_t kmem_alloc_err; 705 uint64_t load_context; 706 uint64_t ip_hwsum_err; 707 uint64_t tcp_hwsum_err; 708 uint64_t rx_nobuffer; 709 uint64_t rx_err; 710 uint64_t tx_stop_err; 711 uint64_t tx_stall; 712 uint64_t tx_rsrv_fail; 713 uint64_t tx_resched; 714 fe_statistics_t fe_err; 715 }nge_sw_statistics_t; 716 717 typedef struct { 718 nge_hw_statistics_t hw_statistics; 719 nge_sw_statistics_t sw_statistics; 720 }nge_statistics_t; 721 722 struct nge_desc_attr { 723 724 size_t rxd_size; 725 size_t txd_size; 726 727 ddi_dma_attr_t *dma_attr; 728 ddi_dma_attr_t *tx_dma_attr; 729 730 void (*rxd_fill)(void *, const ddi_dma_cookie_t *, size_t); 731 uint32_t (*rxd_check)(const void *, size_t *); 732 733 void (*txd_fill)(void *, const ddi_dma_cookie_t *, size_t, 734 uint32_t, boolean_t); 735 736 uint32_t (*txd_check)(const void *, size_t *); 737 }; 738 739 typedef struct nge_desc_attr nge_desc_attr_t; 740 741 /* 742 * Structure used to hold the device-specific config parameters. 743 * The setting of such parameters may not consistent with the 744 * hardware feature of the device. It's used for software purpose. 745 */ 746 typedef struct nge_dev_spec_param { 747 boolean_t msi; /* specifies msi support */ 748 boolean_t msi_x; /* specifies msi_x support */ 749 boolean_t vlan; /* specifies vlan support */ 750 boolean_t tx_pause_frame; /* specifies tx pause frame support */ 751 boolean_t rx_pause_frame; /* specifies rx pause frame support */ 752 boolean_t jumbo; /* jumbo frame support */ 753 boolean_t tx_rx_64byte; /* set the max tx/rx prd fetch size */ 754 boolean_t rx_hw_checksum; /* specifies tx hw checksum feature */ 755 uint32_t tx_hw_checksum; /* specifies rx hw checksum feature */ 756 uint32_t desc_type; /* specifies descriptor type */ 757 uint32_t rx_desc_num; /* specifies rx descriptor number */ 758 uint32_t tx_desc_num; /* specifies tx descriptor number */ 759 uint32_t nge_split; /* specifies the split number */ 760 } nge_dev_spec_param_t; 761 762 typedef struct nge { 763 /* 764 * These fields are set by attach() and unchanged thereafter ... 765 */ 766 dev_info_t *devinfo; /* device instance */ 767 mac_handle_t mh; /* mac module handle */ 768 chip_info_t chipinfo; 769 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 770 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 771 void *io_regs; /* mapped registers */ 772 773 ddi_periodic_t periodic_id; /* periodical callback */ 774 uint32_t factotum_flag; 775 ddi_softint_handle_t factotum_hdl; /* factotum callback */ 776 ddi_softint_handle_t resched_hdl; /* reschedule callback */ 777 uint_t soft_pri; 778 779 ddi_intr_handle_t *htable; /* for array of interrupts */ 780 int intr_type; /* type of interrupt */ 781 int intr_actual_cnt; /* alloc intrs count */ 782 int intr_req_cnt; /* request intrs count */ 783 uint_t intr_pri; /* interrupt priority */ 784 int intr_cap; /* interrupt capabilities */ 785 786 uint32_t progress; /* attach tracking */ 787 uint32_t debug; /* flag to debug function */ 788 789 char ifname[8]; /* "nge0" ... "nge999" */ 790 791 792 enum nge_mac_state nge_mac_state; /* definitions above */ 793 enum nge_chip_state nge_chip_state; /* definitions above */ 794 boolean_t promisc; 795 boolean_t suspended; 796 797 int resched_needed; 798 uint32_t default_mtu; 799 uint32_t max_sdu; 800 uint32_t buf_size; 801 uint32_t rx_desc; 802 uint32_t tx_desc; 803 uint32_t rx_buf; 804 uint32_t nge_split; 805 uint32_t watchdog; 806 uint32_t lowmem_mode; 807 808 809 /* 810 * Runtime read-write data starts here ... 811 * 1 Receive Rings 812 * 1 Send Rings 813 * 814 * Note: they're not necessarily all used. 815 */ 816 struct buff_ring buff[1]; 817 struct recv_ring recv[1]; 818 struct send_ring send[1]; 819 820 821 kmutex_t genlock[1]; 822 krwlock_t rwlock[1]; 823 kmutex_t softlock[1]; 824 uint32_t intr_masks; 825 boolean_t poll; 826 boolean_t ch_intr_mode; 827 boolean_t intr_moderation; 828 uint32_t recv_count; 829 uint32_t quiet_time; 830 uint32_t busy_time; 831 uint32_t stint_count; 832 uint32_t sw_intr_intv; 833 nge_mac_addr_t cur_uni_addr; 834 uint32_t rx_datahwm; 835 uint32_t rx_prdlwm; 836 uint32_t rx_prdhwm; 837 uint32_t rx_def; 838 uint32_t desc_mode; 839 840 mul_item *pcur_mulist; 841 nge_mac_addr_t cur_mul_addr; 842 nge_mac_addr_t cur_mul_mask; 843 844 nge_desc_attr_t desc_attr; 845 846 /* 847 * Link state data (protected by genlock) 848 */ 849 int32_t link_state; /* See GLD #defines */ 850 uint32_t stall_cknum; /* Stall check number */ 851 852 uint32_t phy_xmii_addr; 853 uint32_t phy_id; 854 uint32_t phy_mode; 855 const phys_ops_t *physops; 856 uint16_t phy_gen_status; 857 858 uint32_t param_loop_mode; 859 860 /* 861 * NDD parameters (protected by genlock) 862 */ 863 caddr_t nd_data_p; 864 nd_param_t nd_params[PARAM_COUNT]; 865 866 kstat_t *nge_kstats[NGE_KSTAT_COUNT]; 867 nge_statistics_t statistics; 868 869 nge_dev_spec_param_t dev_spec_param; 870 871 } nge_t; 872 873 extern const nge_ksindex_t nge_statistics[]; 874 875 /* 876 * Shorthand for the NDD parameters 877 */ 878 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 879 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 880 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 881 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 882 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 883 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 884 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 885 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 886 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 887 888 #define param_lp_autoneg nd_params[PARAM_LP_AUTONEG_CAP].ndp_val 889 #define param_lp_pause nd_params[PARAM_LP_PAUSE_CAP].ndp_val 890 #define param_lp_asym_pause nd_params[PARAM_LP_ASYM_PAUSE_CAP].ndp_val 891 #define param_lp_1000fdx nd_params[PARAM_LP_1000FDX_CAP].ndp_val 892 #define param_lp_1000hdx nd_params[PARAM_LP_1000HDX_CAP].ndp_val 893 #define param_lp_100fdx nd_params[PARAM_LP_100FDX_CAP].ndp_val 894 #define param_lp_100hdx nd_params[PARAM_LP_100HDX_CAP].ndp_val 895 #define param_lp_10fdx nd_params[PARAM_LP_10FDX_CAP].ndp_val 896 #define param_lp_10hdx nd_params[PARAM_LP_10HDX_CAP].ndp_val 897 898 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 899 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 900 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 901 902 #define param_link_autoneg nd_params[PARAM_LINK_AUTONEG].ndp_val 903 #define param_link_rx_pause nd_params[PARAM_LINK_RX_PAUSE].ndp_val 904 #define param_link_tx_pause nd_params[PARAM_LINK_TX_PAUSE].ndp_val 905 906 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 907 908 #define param_txbcopy_threshold nd_params[PARAM_TXBCOPY_THRESHOLD].ndp_val 909 #define param_rxbcopy_threshold nd_params[PARAM_RXBCOPY_THRESHOLD].ndp_val 910 #define param_recv_max_packet nd_params[PARAM_RECV_MAX_PACKET].ndp_val 911 #define param_poll_quiet_time nd_params[PARAM_POLL_QUIET_TIME].ndp_val 912 #define param_poll_busy_time nd_params[PARAM_POLL_BUSY_TIME].ndp_val 913 #define param_rx_intr_hwater nd_params[PARAM_RX_INTR_HWATER].ndp_val 914 #define param_rx_intr_lwater nd_params[PARAM_RX_INTR_LWATER].ndp_val 915 #define param_tx_n_intr nd_params[PARAM_TX_N_INTR].ndp_val 916 917 /* 918 * Sync a DMA area described by a dma_area_t 919 */ 920 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 921 (area).offset, (area).alength, (flag))) 922 923 /* 924 * Find the (kernel virtual) address of block of memory 925 * described by a dma_area_t 926 */ 927 #define DMA_VPTR(area) ((area).mem_va) 928 929 /* 930 * Zero a block of memory described by a dma_area_t 931 */ 932 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 933 934 /* 935 * Next/Prev value of a cyclic index 936 */ 937 #define NEXT(index, limit) ((index) + 1 < (limit) ? (index) + 1 : 0) 938 #define PREV(index, limit) (0 == (index) ? (limit - 1) : (index) - 1) 939 940 #define NEXT_INDEX(ndx, num, lim)\ 941 (((ndx) + (num) < (lim)) ? ((ndx) + (num)) : ((ndx) + (num) - (lim))) 942 943 944 /* 945 * Property lookups 946 */ 947 #define NGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 948 DDI_PROP_DONTPASS, (n)) 949 #define NGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 950 DDI_PROP_DONTPASS, (n), -1) 951 952 953 /* 954 * Debugging ... 955 */ 956 #ifdef DEBUG 957 #define NGE_DEBUGGING 1 958 #else 959 #define NGE_DEBUGGING 0 960 #endif /* DEBUG */ 961 962 /* 963 * Bit flags in the 'debug' word ... 964 */ 965 #define NGE_DBG_STOP 0x00000001 /* early debug_enter() */ 966 #define NGE_DBG_TRACE 0x00000002 /* general flow tracing */ 967 968 #define NGE_DBG_MII 0x00000010 /* low-level MII access */ 969 #define NGE_DBG_CHIP 0x00000020 /* low(ish)-level code */ 970 971 #define NGE_DBG_RECV 0x00000100 /* receive-side code */ 972 #define NGE_DBG_SEND 0x00000200 /* packet-send code */ 973 974 #define NGE_DBG_INIT 0x00100000 /* initialisation */ 975 #define NGE_DBG_NEMO 0x00200000 /* MAC layer entry points */ 976 #define NGE_DBG_STATS 0x00400000 /* statistics */ 977 978 #define NGE_DBG_BADIOC 0x01000000 /* unknown ioctls */ 979 980 #define NGE_DBG_NDD 0x10000000 /* NDD operations */ 981 982 983 984 /* 985 * 'Do-if-debugging' macro. The parameter <command> should be one or more 986 * C statements (but without the *final* semicolon), which will either be 987 * compiled inline or completely ignored, depending on the NGE_DEBUGGING 988 * compile-time flag. 989 * 990 * You should get a compile-time error (at least on a DEBUG build) if 991 * your statement isn't actually a statement, rather than unexpected 992 * run-time behaviour caused by unintended matching of if-then-elses etc. 993 * 994 * Note that the NGE_DDB() macro itself can only be used as a statement, 995 * not an expression, and should always be followed by a semicolon. 996 */ 997 #if NGE_DEBUGGING 998 #define NGE_DDB(command) do { \ 999 { command; } \ 1000 _NOTE(CONSTANTCONDITION) \ 1001 } while (0) 1002 #else /* NGE_DEBUGGING */ 1003 #define NGE_DDB(command) 1004 /* 1005 * Old way of debugging. This is a poor way, as it leeaves empty 1006 * statements that cause lint to croak. 1007 * #define NGE_DDB(command) do { \ 1008 * { _NOTE(EMPTY); } \ 1009 * _NOTE(CONSTANTCONDITION) \ 1010 * } while (0) 1011 */ 1012 #endif /* NGE_DEBUGGING */ 1013 1014 /* 1015 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 1016 * These provide the primitive conditional-call capability required. 1017 * Note: the parameter <args> is a parenthesised list of the actual 1018 * printf-style arguments to be passed to the debug function ... 1019 */ 1020 #define NGE_XDB(b, w, f, args) NGE_DDB(if ((b) & (w)) f args) 1021 #define NGE_GDB(b, args) NGE_XDB(b, nge_debug, (*nge_gdb()), args) 1022 #define NGE_LDB(b, args) NGE_XDB(b, ngep->debug, \ 1023 (*nge_db(ngep)), args) 1024 #define NGE_CDB(f, args) NGE_XDB(NGE_DBG, ngep->debug, f, args) 1025 1026 /* 1027 * Conditional-print macros. 1028 * 1029 * Define NGE_DBG to be the relevant member of the set of NGE_DBG_* values 1030 * above before using the NGE_GDEBUG() or NGE_DEBUG() macros. The 'G' 1031 * versions look at the Global debug flag word (nge_debug); the non-G 1032 * versions look in the per-instance data (ngep->debug) and so require a 1033 * variable called 'ngep' to be in scope (and initialised!) before use. 1034 * 1035 * You could redefine NGE_TRC too if you really need two different 1036 * flavours of debugging output in the same area of code, but I don't 1037 * really recommend it. 1038 * 1039 * Note: the parameter <args> is a parenthesised list of the actual 1040 * arguments to be passed to the debug function, usually a printf-style 1041 * format string and corresponding values to be formatted. 1042 */ 1043 1044 #define NGE_TRC NGE_DBG_TRACE 1045 1046 #define NGE_GTRACE(args) NGE_GDB(NGE_TRC, args) 1047 #define NGE_GDEBUG(args) NGE_GDB(NGE_DBG, args) 1048 #define NGE_TRACE(args) NGE_LDB(NGE_TRC, args) 1049 #define NGE_DEBUG(args) NGE_LDB(NGE_DBG, args) 1050 1051 /* 1052 * Debug-only action macros 1053 */ 1054 1055 1056 #define NGE_REPORT(args) NGE_DDB(nge_log args) 1057 1058 boolean_t nge_atomic_decrease(uint64_t *count_p, uint64_t n); 1059 void nge_atomic_increase(uint64_t *count_p, uint64_t n); 1060 1061 int nge_alloc_dma_mem(nge_t *ngep, size_t memsize, 1062 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p); 1063 void nge_free_dma_mem(dma_area_t *dma_p); 1064 int nge_restart(nge_t *ngep); 1065 void nge_wake_factotum(nge_t *ngep); 1066 1067 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno); 1068 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data); 1069 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno); 1070 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 1071 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno); 1072 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data); 1073 uint_t nge_chip_factotum(caddr_t args1, caddr_t args2); 1074 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset); 1075 void nge_init_dev_spec_param(nge_t *ngep); 1076 int nge_chip_stop(nge_t *ngep, boolean_t fault); 1077 void nge_restore_mac_addr(nge_t *ngep); 1078 int nge_chip_reset(nge_t *ngep); 1079 int nge_chip_start(nge_t *ngep); 1080 void nge_chip_sync(nge_t *ngep); 1081 1082 uint_t nge_chip_intr(caddr_t arg1, caddr_t arg2); 1083 enum ioc_reply nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp); 1084 1085 void nge_phys_init(nge_t *ngep); 1086 boolean_t nge_phy_reset(nge_t *ngep); 1087 uint16_t nge_mii_get16(nge_t *ngep, nge_regno_t regno); 1088 void nge_mii_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 1089 1090 void nge_recv_recycle(caddr_t arg); 1091 void nge_receive(nge_t *ngep); 1092 1093 uint_t nge_reschedule(caddr_t args1, caddr_t args2); 1094 mblk_t *nge_m_tx(void *arg, mblk_t *mp); 1095 1096 void nge_tx_recycle(nge_t *ngep, boolean_t is_intr); 1097 void nge_tx_recycle_all(nge_t *ngep); 1098 1099 enum ioc_reply nge_nd_ioctl(nge_t *ngep, queue_t *wq, 1100 mblk_t *mp, struct iocblk *iocp); 1101 int nge_nd_init(nge_t *ngep); 1102 void nge_nd_cleanup(nge_t *ngep); 1103 1104 1105 void nge_init_kstats(nge_t *ngep, int instance); 1106 void nge_fini_kstats(nge_t *ngep); 1107 int nge_m_stat(void *arg, uint_t stat, uint64_t *val); 1108 1109 uint32_t nge_atomic_shl32(uint32_t *sp, uint_t count); 1110 1111 void nge_log(nge_t *ngep, const char *fmt, ...); 1112 void nge_problem(nge_t *ngep, const char *fmt, ...); 1113 void nge_error(nge_t *ngep, const char *fmt, ...); 1114 void 1115 nge_report(nge_t *ngep, uint8_t error_id); 1116 1117 void (*nge_db(nge_t *ngep))(const char *fmt, ...); 1118 void (*nge_gdb(void))(const char *fmt, ...); 1119 extern uint32_t nge_debug; 1120 1121 /* 1122 * DESC MODE 2 1123 */ 1124 1125 extern void nge_sum_rxd_fill(void *, const ddi_dma_cookie_t *, size_t); 1126 extern uint32_t nge_sum_rxd_check(const void *, size_t *); 1127 1128 extern void nge_sum_txd_fill(void *, const ddi_dma_cookie_t *, 1129 size_t, uint32_t, boolean_t); 1130 extern uint32_t nge_sum_txd_check(const void *, size_t *); 1131 1132 /* 1133 * DESC MODE 3 1134 */ 1135 1136 extern void nge_hot_rxd_fill(void *, const ddi_dma_cookie_t *, size_t); 1137 extern uint32_t nge_hot_rxd_check(const void *, size_t *); 1138 1139 extern void nge_hot_txd_fill(void *, const ddi_dma_cookie_t *, 1140 size_t, uint32_t, boolean_t); 1141 extern uint32_t nge_hot_txd_check(const void *, size_t *); 1142 1143 #ifdef __cplusplus 1144 } 1145 #endif 1146 1147 #endif /* _SYS_NGE_H */ 1148