1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * This file may contain confidential information of Nvidia 8 * and should not be distributed in source form without approval 9 * from Sun Legal. 10 */ 11 12 #ifndef _SYS_NGE_H 13 #define _SYS_NGE_H 14 15 #pragma ident "%Z%%M% %I% %E% SMI" 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 22 #include <sys/types.h> 23 #include <sys/stream.h> 24 #include <sys/strsun.h> 25 #include <sys/strsubr.h> 26 #include <sys/stat.h> 27 #include <sys/pci.h> 28 #include <sys/note.h> 29 #include <sys/modctl.h> 30 #include <sys/kstat.h> 31 #include <sys/ethernet.h> 32 #include <sys/pattr.h> 33 #include <sys/errno.h> 34 #include <sys/dlpi.h> 35 #include <sys/devops.h> 36 #include <sys/debug.h> 37 #include <sys/conf.h> 38 #include <sys/callb.h> 39 40 #include <netinet/ip6.h> 41 42 #include <inet/common.h> 43 #include <inet/ip.h> 44 #include <netinet/udp.h> 45 #include <inet/mi.h> 46 #include <inet/nd.h> 47 48 #include <sys/ddi.h> 49 #include <sys/sunddi.h> 50 51 #include <sys/mac.h> 52 #include <sys/mac_ether.h> 53 54 /* 55 * Reconfiguring the network devices requires the net_config privilege 56 * in Solaris 10+. 57 */ 58 extern int secpolicy_net_config(const cred_t *, boolean_t); 59 60 #include <sys/netlb.h> 61 #include <sys/miiregs.h> 62 63 #include "nge_chip.h" 64 65 #define PIO_ADDR(ngep, offset) ((void *)((caddr_t)(ngep)->io_regs+(offset))) 66 /* 67 * Copy an ethernet address 68 */ 69 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL) 70 #define ether_eq(a, b) (bcmp((caddr_t)(a), (caddr_t)(b), (ETHERADDRL)) == 0) 71 72 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 73 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 74 #define UPORDOWN(x) ((x) ? "up" : "down") 75 76 #define NGE_DRIVER_NAME "nge" 77 78 /* 79 * 'Progress' bit flags ... 80 */ 81 #define PROGRESS_CFG 0x0001 /* config space mapped */ 82 #define PROGRESS_REGS 0x0002 /* registers mapped */ 83 #define PROGRESS_BUFS 0x0004 /* registers mapped */ 84 #define PROGRESS_RESCHED 0x0008 /* resched softint registered */ 85 #define PROGRESS_FACTOTUM 0x0010 /* factotum softint registered */ 86 #define PROGRESS_SWINT 0x0020 /* s/w interrupt registered */ 87 #define PROGRESS_INTR 0x0040 /* h/w interrupt registered */ 88 /* and mutexen initialised */ 89 #define PROGRESS_HWINT 0x0080 90 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 91 #define PROGRESS_NDD 0x0200 /* NDD parameters set up */ 92 #define PROGRESS_KSTATS 0x0400 /* kstats created */ 93 #define PROGRESS_READY 0x0800 /* ready for work */ 94 95 #define NGE_HW_ERR 0x00 96 #define NGE_HW_LINK 0x01 97 #define NGE_HW_BM 0x02 98 #define NGE_HW_RCHAN 0x03 99 #define NGE_HW_TCHAN 0x04 100 #define NGE_HW_ROM 0x05 101 #define NGE_SW_PROBLEM_ID 0x06 102 103 104 /* 105 * NOTES: 106 * 107 * #defines: 108 * 109 * NGE_PCI_CONFIG_RNUMBER and NGE_PCI_OPREGS_RNUMBER are the 110 * register-set numbers to use for the config space registers 111 * and the operating registers respectively. On an OBP-based 112 * machine, regset 0 refers to CONFIG space, and regset 1 will 113 * be the operating registers in MEMORY space. If an expansion 114 * ROM is fitted, it may appear as a further register set. 115 * 116 * NGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used 117 * for the data buffers. The descriptors are always set up 118 * in CONSISTENT mode. 119 * 120 * NGE_HEADROOM defines how much space we'll leave in allocated 121 * mblks before the first valid data byte. This should be chosen 122 * to be 2 modulo 4, so that once the ethernet header (14 bytes) 123 * has been stripped off, the packet data will be 4-byte aligned. 124 * The remaining space can be used by upstream modules to prepend 125 * any headers required. 126 */ 127 128 129 #define NGE_PCI_OPREGS_RNUMBER 1 130 #define NGE_DMA_MODE DDI_DMA_STREAMING 131 #define NGE_HEADROOM 6 132 #define ETHER_HEAD_LEN 14 133 #ifndef VTAG_SIZE 134 #define VTAG_SIZE 4 135 #endif 136 137 #define NGE_HALFTICK 268435456LL /* 2**28 ns! */ 138 #define NGE_CYCLIC_PERIOD (4*NGE_HALFTICK) /* ~0.5s */ 139 140 #define NGE_DEFAULT_MTU 1500 141 #define NGE_DEFAULT_SDU 1518 142 #define NGE_MTU_2500 2500 143 #define NGE_MTU_4500 4500 144 #define NGE_MAX_MTU 9000 145 #define NGE_MAX_SDU 9018 146 147 #define NGE_DESC_MIN 0x100 148 149 #define NGE_STD_BUFSZ 1792 150 #define NGE_JB2500_BUFSZ (3*1024) 151 #define NGE_JB4500_BUFSZ (5*1024) 152 #define NGE_JB9000_BUFSZ (9*1024) 153 154 #define NGE_SEND_SLOTS_DESC_1024 1024 155 #define NGE_SEND_SLOTS_DESC_3072 3072 156 #define NGE_SEND_JB2500_SLOTS_DESC 3072 157 #define NGE_SEND_JB4500_SLOTS_DESC 2048 158 #define NGE_SEND_JB9000_SLOTS_DESC 1024 159 #define NGE_SEND_LOWMEM_SLOTS_DESC 1024 160 #define NGE_SEND_SLOTS_BUF 3072 161 162 #define NGE_RECV_SLOTS_DESC_1024 1024 163 #define NGE_RECV_SLOTS_DESC_3072 3072 164 #define NGE_RECV_JB2500_SLOTS_DESC 3072 165 #define NGE_RECV_JB4500_SLOTS_DESC 2048 166 #define NGE_RECV_JB9000_SLOTS_DESC 1024 167 #define NGE_RECV_LOWMEM_SLOTS_DESC 1024 168 #define NGE_RECV_SLOTS_BUF 6144 169 170 #define NGE_SPLIT_32 32 171 #define NGE_SPLIT_96 96 172 #define NGE_SPLIT_256 256 173 174 #define NGE_RX_COPY_SIZE 512 175 #define NGE_TX_COPY_SIZE 512 176 #define NGE_MAP_FRAGS 3 177 #define NGE_MAX_COOKIES 3 178 #define NGE_MAX_DMA_HDR (4*1024) 179 180 /* Used by interrupt blank */ 181 #define NGE_TICKS_CNT 128 182 #define NGE_RX_PKT_CNT 8 183 184 /* 185 * NGE-specific ioctls ... 186 */ 187 #define NGE_IOC ((((('N' << 8) + 'G') << 8) + 'E') << 8) 188 189 /* 190 * PHY register read/write ioctls, used by cable test software 191 */ 192 #define NGE_MII_READ (NGE_IOC|1) 193 #define NGE_MII_WRITE (NGE_IOC|2) 194 195 /* 196 * SEEPROM read/write ioctls, for use by SEEPROM upgrade utility 197 * 198 * Note: SEEPROMs can only be accessed as 32-bit words, so <see_addr> 199 * must be a multiple of 4. Not all systems have a SEEPROM fitted! 200 */ 201 #define NGE_SEE_READ (NGE_IOC|3) 202 #define NGE_SEE_WRITE (NGE_IOC|4) 203 204 205 /* 206 * These diagnostic IOCTLS are enabled only in DEBUG drivers 207 */ 208 #define NGE_DIAG (NGE_IOC|5) /* currently a no-op */ 209 #define NGE_PEEK (NGE_IOC|6) 210 #define NGE_POKE (NGE_IOC|7) 211 #define NGE_PHY_RESET (NGE_IOC|8) 212 #define NGE_SOFT_RESET (NGE_IOC|9) 213 #define NGE_HARD_RESET (NGE_IOC|10) 214 215 216 enum NGE_HW_OP { 217 NGE_CLEAR = 0, 218 NGE_SET 219 }; 220 221 /* 222 * Required state according to GLD 223 */ 224 enum nge_mac_state { 225 NGE_MAC_UNKNOWN, 226 NGE_MAC_RESET, 227 NGE_MAC_STOPPED, 228 NGE_MAC_STARTED, 229 NGE_MAC_UNATTACH 230 }; 231 enum loop_type { 232 NGE_LOOP_NONE = 0, 233 NGE_LOOP_EXTERNAL_100, 234 NGE_LOOP_EXTERNAL_10, 235 NGE_LOOP_INTERNAL_PHY, 236 }; 237 238 /* 239 * (Internal) return values from send_msg subroutines 240 */ 241 enum send_status { 242 SEND_COPY_FAIL = -1, /* => GLD_NORESOURCES */ 243 SEND_MAP_FAIL, /* => GLD_NORESOURCES */ 244 SEND_COPY_SUCESS, /* OK, msg queued */ 245 SEND_MAP_SUCCESS /* OK, free msg */ 246 }; 247 248 249 /* 250 * NDD parameter indexes, divided into: 251 * 252 * read-only parameters describing the hardware's capabilities 253 * read-write parameters controlling the advertised capabilities 254 * read-only parameters describing the partner's capabilities 255 * read-only parameters describing the link state 256 */ 257 enum { 258 PARAM_AUTONEG_CAP, 259 PARAM_PAUSE_CAP, 260 PARAM_ASYM_PAUSE_CAP, 261 PARAM_1000FDX_CAP, 262 PARAM_1000HDX_CAP, 263 PARAM_100T4_CAP, 264 PARAM_100FDX_CAP, 265 PARAM_100HDX_CAP, 266 PARAM_10FDX_CAP, 267 PARAM_10HDX_CAP, 268 269 PARAM_ADV_AUTONEG_CAP, 270 PARAM_ADV_PAUSE_CAP, 271 PARAM_ADV_ASYM_PAUSE_CAP, 272 PARAM_ADV_1000FDX_CAP, 273 PARAM_ADV_1000HDX_CAP, 274 PARAM_ADV_100T4_CAP, 275 PARAM_ADV_100FDX_CAP, 276 PARAM_ADV_100HDX_CAP, 277 PARAM_ADV_10FDX_CAP, 278 PARAM_ADV_10HDX_CAP, 279 280 PARAM_LP_AUTONEG_CAP, 281 PARAM_LP_PAUSE_CAP, 282 PARAM_LP_ASYM_PAUSE_CAP, 283 PARAM_LP_1000FDX_CAP, 284 PARAM_LP_1000HDX_CAP, 285 PARAM_LP_100T4_CAP, 286 PARAM_LP_100FDX_CAP, 287 PARAM_LP_100HDX_CAP, 288 PARAM_LP_10FDX_CAP, 289 PARAM_LP_10HDX_CAP, 290 291 PARAM_LINK_STATUS, 292 PARAM_LINK_SPEED, 293 PARAM_LINK_DUPLEX, 294 295 PARAM_LINK_AUTONEG, 296 PARAM_LINK_RX_PAUSE, 297 PARAM_LINK_TX_PAUSE, 298 299 PARAM_LOOP_MODE, 300 PARAM_TXBCOPY_THRESHOLD, 301 PARAM_RXBCOPY_THRESHOLD, 302 PARAM_RECV_MAX_PACKET, 303 304 PARAM_COUNT 305 }; 306 307 308 /* 309 * (Internal) return values from ioctl subroutines 310 */ 311 enum ioc_reply { 312 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 313 IOC_DONE, /* OK, reply sent */ 314 IOC_ACK, /* OK, just send ACK */ 315 IOC_REPLY, /* OK, just send reply */ 316 IOC_RESTART_ACK, /* OK, restart & ACK */ 317 IOC_RESTART_REPLY /* OK, restart & reply */ 318 }; 319 320 enum nge_pp_type { 321 NGE_PP_SPACE_CFG = 0, 322 NGE_PP_SPACE_REG, 323 NGE_PP_SPACE_NIC, 324 NGE_PP_SPACE_MII, 325 NGE_PP_SPACE_NGE, 326 NGE_PP_SPACE_TXDESC, 327 NGE_PP_SPACE_TXBUFF, 328 NGE_PP_SPACE_RXDESC, 329 NGE_PP_SPACE_RXBUFF, 330 NGE_PP_SPACE_STATISTICS, 331 NGE_PP_SPACE_SEEPROM, 332 NGE_PP_SPACE_FLASH 333 }; 334 335 /* 336 * Flag to kstat type 337 */ 338 enum nge_kstat_type { 339 NGE_KSTAT_RAW = 0, 340 NGE_KSTAT_STATS, 341 NGE_KSTAT_CHIPID, 342 NGE_KSTAT_DEBUG, 343 NGE_KSTAT_COUNT 344 }; 345 346 347 /* 348 * Actual state of the nvidia's chip 349 */ 350 enum nge_chip_state { 351 NGE_CHIP_FAULT = -2, /* fault, need reset */ 352 NGE_CHIP_ERROR, /* error, want reset */ 353 NGE_CHIP_INITIAL, /* Initial state only */ 354 NGE_CHIP_RESET, /* reset, need init */ 355 NGE_CHIP_STOPPED, /* Tx/Rx stopped */ 356 NGE_CHIP_RUNNING /* with interrupts */ 357 }; 358 359 enum nge_eeprom_size { 360 EEPROM_1K = 0, 361 EEPROM_2K, 362 EEPROM_4K, 363 EEPROM_8K, 364 EEPROM_16K, 365 EEPROM_32K, 366 EEPROM_64K 367 }; 368 369 enum nge_eeprom_access_wid { 370 ACCESS_8BIT = 0, 371 ACCESS_16BIT 372 }; 373 374 /* 375 * MDIO operation 376 */ 377 enum nge_mdio_operation { 378 NGE_MDIO_READ = 0, 379 NGE_MDIO_WRITE 380 }; 381 382 /* 383 * Speed selection 384 */ 385 enum nge_speed { 386 UNKOWN_SPEED = 0, 387 NGE_10M, 388 NGE_100M, 389 NGE_1000M 390 }; 391 392 /* 393 * Duplex selection 394 */ 395 enum nge_duplex { 396 UNKOWN_DUPLEX = 0, 397 NGE_HD, 398 NGE_FD 399 }; 400 401 typedef struct { 402 ether_addr_t addr; /* in canonical form */ 403 uint8_t spare; 404 uint8_t set; /* nonzero => valid */ 405 } nge_mac_addr_t; 406 407 struct nge; 408 409 /* 410 * Named Data (ND) Parameter Management Structure 411 */ 412 typedef struct { 413 int ndp_info; 414 int ndp_min; 415 int ndp_max; 416 int ndp_val; 417 char *ndp_name; 418 } nd_param_t; 419 420 421 #define CHIP_FLAG_COPPER 0x40 422 423 /* 424 * Collection of physical-layer functions to: 425 * (re)initialise the physical layer 426 * update it to match software settings 427 * check for link status change 428 */ 429 typedef struct { 430 void (*phys_restart)(struct nge *); 431 void (*phys_update)(struct nge *); 432 boolean_t (*phys_check)(struct nge *); 433 } phys_ops_t; 434 435 struct nge_see_rw { 436 uint32_t see_addr; /* Byte offset within SEEPROM */ 437 uint32_t see_data; /* Data read/data to write */ 438 }; 439 440 typedef struct { 441 uint64_t pp_acc_size; /* in bytes: 1,2,4,8 */ 442 uint64_t pp_acc_space; /* See #defines below */ 443 uint64_t pp_acc_offset; 444 uint64_t pp_acc_data; /* output for peek */ 445 /* input for poke */ 446 } nge_peekpoke_t; 447 448 typedef uintptr_t nge_regno_t; /* register # (offset) */ 449 450 typedef struct _mul_list { 451 struct _mul_list *next; 452 uint32_t ref_cnt; 453 ether_addr_t mul_addr; 454 }mul_item, *pmul_item; 455 456 /* 457 * Describes one chunk of allocated DMA-able memory 458 * 459 * In some cases, this is a single chunk as allocated from the system; 460 * but we also use this structure to represent slices carved off such 461 * a chunk. Even when we don't really need all the information, we 462 * use this structure as a convenient way of correlating the various 463 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 464 * handle+offset, etc). 465 */ 466 typedef struct dma_area 467 { 468 469 caddr_t private; /* pointer to nge */ 470 frtn_t rx_recycle; /* recycle function */ 471 mblk_t *mp; 472 ddi_acc_handle_t acc_hdl; /* handle for memory */ 473 void *mem_va; /* CPU VA of memory */ 474 uint32_t nslots; /* number of slots */ 475 uint32_t size; /* size per slot */ 476 size_t alength; /* allocated size */ 477 /* >= product of above */ 478 ddi_dma_handle_t dma_hdl; /* DMA handle */ 479 offset_t offset; /* relative to handle */ 480 ddi_dma_cookie_t cookie; /* associated cookie */ 481 uint32_t ncookies; 482 uint32_t signature; /* buffer signature */ 483 /* for deciding to free */ 484 /* or to reuse buffers */ 485 boolean_t rx_delivered; /* hold by upper layer */ 486 struct dma_area *next; 487 } dma_area_t; 488 489 #define HOST_OWN 0x00000000 490 #define CONTROLER_OWN 0x00000001 491 #define NGE_END_PACKET 0x00000002 492 493 494 typedef struct nge_dmah_node 495 { 496 struct nge_dmah_node *next; 497 ddi_dma_handle_t hndl; 498 } nge_dmah_node_t; 499 500 typedef struct nge_dmah_list 501 { 502 nge_dmah_node_t *head; 503 nge_dmah_node_t *tail; 504 } nge_dmah_list_t; 505 506 /* 507 * Software version of the Recv Descriptor 508 * There's one of these for each recv buffer (up to 512 per ring) 509 */ 510 typedef struct sw_rx_sbd { 511 512 dma_area_t desc; /* (const) related h/w */ 513 /* descriptor area */ 514 dma_area_t *bufp; /* (const) related */ 515 /* buffer area */ 516 uint8_t flags; 517 } sw_rx_sbd_t; 518 519 /* 520 * Software version of the send Buffer Descriptor 521 * There's one of these for each send buffer (up to 512 per ring) 522 */ 523 typedef struct sw_tx_sbd { 524 525 dma_area_t desc; /* (const) related h/w */ 526 /* descriptor area */ 527 dma_area_t pbuf; /* (const) related */ 528 /* buffer area */ 529 void (*tx_recycle)(struct sw_tx_sbd *); 530 uint32_t flags; 531 mblk_t *mp; /* related mblk, if any */ 532 nge_dmah_list_t mp_hndl; 533 uint32_t frags; 534 uint32_t ncookies; /* dma cookie number */ 535 536 } sw_tx_sbd_t; 537 538 /* 539 * Software Receive Buffer (Producer) Ring Control Block 540 * There's one of these for each receiver producer ring (up to 3), 541 * but each holds buffers of a different size. 542 */ 543 typedef struct buff_ring { 544 545 uint64_t nslots; /* descriptor area */ 546 struct nge *ngep; /* (const) containing */ 547 /* driver soft state */ 548 /* initialise same */ 549 uint64_t rx_hold; 550 sw_rx_sbd_t *sw_rbds; /* software descriptors */ 551 sw_rx_sbd_t *free_rbds; /* free ring */ 552 dma_area_t *free_list; /* available buffer queue */ 553 dma_area_t *recycle_list; /* recycling buffer queue */ 554 kmutex_t recycle_lock[1]; 555 uint32_t buf_sign; 556 boolean_t rx_bcopy; 557 } buff_ring_t; 558 559 /* 560 * Software Receive (Return) Ring Control Block 561 * There's one of these for each receiver return ring (up to 16). 562 */ 563 typedef struct recv_ring { 564 /* 565 * The elements flagged (const) in the comments below are 566 * set up once during initialiation and thereafter unchanged. 567 */ 568 dma_area_t desc; /* (const) related h/w */ 569 /* descriptor area */ 570 struct nge *ngep; /* (const) containing */ 571 /* driver soft state */ 572 uint16_t prod_index; /* (const) ptr to h/w */ 573 /* "producer index" */ 574 mac_resource_handle_t handle; 575 } recv_ring_t; 576 577 578 579 /* 580 * Software Send Ring Control Block 581 * There's one of these for each of (up to) 1 send rings 582 */ 583 typedef struct send_ring { 584 /* 585 * The elements flagged (const) in the comments below are 586 * set up once during initialiation and thereafter unchanged. 587 */ 588 dma_area_t desc; /* (const) related h/w */ 589 /* descriptor area */ 590 dma_area_t buf[NGE_SEND_SLOTS_BUF]; 591 /* buffer area(s) */ 592 struct nge *ngep; /* (const) containing */ 593 /* driver soft state */ 594 595 uint64_t tx_hwmark; 596 uint64_t tx_lwmark; 597 598 /* 599 * The tx_lock must be held when updating 600 * the s/w producer index 601 * (tx_next) 602 */ 603 kmutex_t tx_lock[1]; /* serialize h/w update */ 604 uint64_t tx_next; /* next slot to use */ 605 uint64_t tx_flow; 606 607 /* 608 * These counters/indexes are manipulated in the transmit 609 * path using atomics rather than mutexes for speed 610 */ 611 uint64_t tx_free; /* # of slots available */ 612 613 /* 614 * index (tc_next). 615 */ 616 kmutex_t tc_lock[1]; 617 uint64_t tc_next; /* next slot to recycle */ 618 /* ("consumer index") */ 619 620 sw_tx_sbd_t *sw_sbds; /* software descriptors */ 621 622 kmutex_t dmah_lock; 623 nge_dmah_list_t dmah_free; 624 nge_dmah_node_t dmahndl[NGE_MAX_DMA_HDR]; 625 626 } send_ring_t; 627 628 629 typedef struct { 630 uint32_t businfo; /* from private reg */ 631 uint16_t command; /* saved during attach */ 632 633 uint16_t vendor; /* vendor-id */ 634 uint16_t device; /* device-id */ 635 uint16_t subven; /* subsystem-vendor-id */ 636 uint16_t subdev; /* subsystem-id */ 637 uint8_t class_code; 638 uint8_t revision; /* revision-id */ 639 uint8_t clsize; /* cache-line-size */ 640 uint8_t latency; /* latency-timer */ 641 uint8_t flags; 642 643 uint16_t phy_type; /* Fiber module type */ 644 uint64_t hw_mac_addr; /* from chip register */ 645 nge_mac_addr_t vendor_addr; /* transform of same */ 646 } chip_info_t; 647 648 649 typedef struct { 650 offset_t index; 651 char *name; 652 } nge_ksindex_t; 653 654 typedef struct { 655 uint64_t tso_err_mss; 656 uint64_t tso_dis; 657 uint64_t tso_err_nosum; 658 uint64_t tso_err_hov; 659 uint64_t tso_err_huf; 660 uint64_t tso_err_l2; 661 uint64_t tso_err_ip; 662 uint64_t tso_err_l4; 663 uint64_t tso_err_tcp; 664 uint64_t hsum_err_ip; 665 uint64_t hsum_err_l4; 666 }fe_statistics_t; 667 668 /* 669 * statistics parameters to tune the driver 670 */ 671 typedef struct { 672 uint64_t intr_count; 673 uint64_t intr_lval; 674 uint64_t recv_realloc; 675 uint64_t poll_time; 676 uint64_t recy_free; 677 uint64_t recv_count; 678 uint64_t xmit_count; 679 uint64_t obytes; 680 uint64_t rbytes; 681 uint64_t mp_alloc_err; 682 uint64_t dma_alloc_err; 683 uint64_t kmem_alloc_err; 684 uint64_t load_context; 685 uint64_t ip_hwsum_err; 686 uint64_t tcp_hwsum_err; 687 uint64_t rx_nobuffer; 688 uint64_t rx_err; 689 uint64_t tx_stop_err; 690 uint64_t tx_stall; 691 uint64_t tx_rsrv_fail; 692 uint64_t tx_resched; 693 fe_statistics_t fe_err; 694 }nge_sw_statistics_t; 695 696 typedef struct { 697 nge_hw_statistics_t hw_statistics; 698 nge_sw_statistics_t sw_statistics; 699 }nge_statistics_t; 700 701 struct nge_desc_attr { 702 703 size_t rxd_size; 704 size_t txd_size; 705 706 ddi_dma_attr_t *dma_attr; 707 ddi_dma_attr_t *tx_dma_attr; 708 709 void (*rxd_fill)(void *, const ddi_dma_cookie_t *, size_t); 710 uint32_t (*rxd_check)(const void *, size_t *); 711 712 void (*txd_fill)(void *, const ddi_dma_cookie_t *, size_t, 713 uint32_t, boolean_t); 714 715 uint32_t (*txd_check)(const void *, size_t *); 716 }; 717 718 typedef struct nge_desc_attr nge_desc_attr_t; 719 720 /* 721 * Structure used to hold the device-specific config parameters. 722 * The setting of such parameters may not consistent with the 723 * hardware feature of the device. It's used for software purpose. 724 */ 725 typedef struct nge_dev_spec_param { 726 boolean_t msi; /* specifies msi support */ 727 boolean_t msi_x; /* specifies msi_x support */ 728 boolean_t vlan; /* specifies vlan support */ 729 boolean_t tx_pause_frame; /* specifies tx pause frame support */ 730 boolean_t rx_pause_frame; /* specifies rx pause frame support */ 731 boolean_t jumbo; /* jumbo frame support */ 732 boolean_t tx_rx_64byte; /* set the max tx/rx prd fetch size */ 733 boolean_t rx_hw_checksum; /* specifies tx hw checksum feature */ 734 uint32_t tx_hw_checksum; /* specifies rx hw checksum feature */ 735 uint32_t desc_type; /* specifies descriptor type */ 736 uint32_t rx_desc_num; /* specifies rx descriptor number */ 737 uint32_t tx_desc_num; /* specifies tx descriptor number */ 738 uint32_t nge_split; /* specifies the split number */ 739 } nge_dev_spec_param_t; 740 741 typedef struct nge { 742 /* 743 * These fields are set by attach() and unchanged thereafter ... 744 */ 745 dev_info_t *devinfo; /* device instance */ 746 mac_handle_t mh; /* mac module handle */ 747 chip_info_t chipinfo; 748 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 749 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 750 void *io_regs; /* mapped registers */ 751 752 ddi_periodic_t periodic_id; /* periodical callback */ 753 uint32_t factotum_flag; 754 ddi_softint_handle_t factotum_hdl; /* factotum callback */ 755 ddi_softint_handle_t resched_hdl; /* reschedule callback */ 756 uint_t soft_pri; 757 758 ddi_intr_handle_t *htable; /* for array of interrupts */ 759 int intr_type; /* type of interrupt */ 760 int intr_actual_cnt; /* alloc intrs count */ 761 int intr_req_cnt; /* request intrs count */ 762 uint_t intr_pri; /* interrupt priority */ 763 int intr_cap; /* interrupt capabilities */ 764 765 uint32_t progress; /* attach tracking */ 766 uint32_t debug; /* flag to debug function */ 767 768 char ifname[8]; /* "nge0" ... "nge999" */ 769 770 771 enum nge_mac_state nge_mac_state; /* definitions above */ 772 enum nge_chip_state nge_chip_state; /* definitions above */ 773 boolean_t promisc; 774 boolean_t suspended; 775 776 int resched_needed; 777 uint32_t default_mtu; 778 uint32_t max_sdu; 779 uint32_t buf_size; 780 uint32_t rx_desc; 781 uint32_t tx_desc; 782 uint32_t rx_buf; 783 uint32_t nge_split; 784 uint32_t watchdog; 785 uint32_t lowmem_mode; 786 787 788 /* 789 * Runtime read-write data starts here ... 790 * 1 Receive Rings 791 * 1 Send Rings 792 * 793 * Note: they're not necessarily all used. 794 */ 795 struct buff_ring buff[1]; 796 struct recv_ring recv[1]; 797 struct send_ring send[1]; 798 799 800 kmutex_t genlock[1]; 801 krwlock_t rwlock[1]; 802 kmutex_t softlock[1]; 803 uint32_t intr_masks; 804 boolean_t poll; 805 boolean_t ch_intr_mode; 806 uint32_t recv_count; 807 uint32_t poll_time; 808 uint32_t sw_intr_intv; 809 nge_mac_addr_t cur_uni_addr; 810 uint32_t rx_datahwm; 811 uint32_t rx_prdlwm; 812 uint32_t rx_prdhwm; 813 uint32_t rx_def; 814 uint32_t desc_mode; 815 816 mul_item *pcur_mulist; 817 nge_mac_addr_t cur_mul_addr; 818 nge_mac_addr_t cur_mul_mask; 819 820 nge_desc_attr_t desc_attr; 821 822 /* 823 * Link state data (protected by genlock) 824 */ 825 int32_t link_state; /* See GLD #defines */ 826 uint32_t stall_cknum; /* Stall check number */ 827 828 uint32_t phy_xmii_addr; 829 uint32_t phy_id; 830 uint32_t phy_mode; 831 const phys_ops_t *physops; 832 uint16_t phy_gen_status; 833 834 uint32_t param_loop_mode; 835 836 /* 837 * NDD parameters (protected by genlock) 838 */ 839 caddr_t nd_data_p; 840 nd_param_t nd_params[PARAM_COUNT]; 841 842 kstat_t *nge_kstats[NGE_KSTAT_COUNT]; 843 nge_statistics_t statistics; 844 845 nge_dev_spec_param_t dev_spec_param; 846 847 } nge_t; 848 849 extern const nge_ksindex_t nge_statistics[]; 850 851 /* 852 * Shorthand for the NDD parameters 853 */ 854 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 855 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 856 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 857 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 858 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 859 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 860 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 861 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 862 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 863 864 #define param_lp_autoneg nd_params[PARAM_LP_AUTONEG_CAP].ndp_val 865 #define param_lp_pause nd_params[PARAM_LP_PAUSE_CAP].ndp_val 866 #define param_lp_asym_pause nd_params[PARAM_LP_ASYM_PAUSE_CAP].ndp_val 867 #define param_lp_1000fdx nd_params[PARAM_LP_1000FDX_CAP].ndp_val 868 #define param_lp_1000hdx nd_params[PARAM_LP_1000HDX_CAP].ndp_val 869 #define param_lp_100fdx nd_params[PARAM_LP_100FDX_CAP].ndp_val 870 #define param_lp_100hdx nd_params[PARAM_LP_100HDX_CAP].ndp_val 871 #define param_lp_10fdx nd_params[PARAM_LP_10FDX_CAP].ndp_val 872 #define param_lp_10hdx nd_params[PARAM_LP_10HDX_CAP].ndp_val 873 874 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 875 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 876 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 877 878 #define param_link_autoneg nd_params[PARAM_LINK_AUTONEG].ndp_val 879 #define param_link_rx_pause nd_params[PARAM_LINK_RX_PAUSE].ndp_val 880 #define param_link_tx_pause nd_params[PARAM_LINK_TX_PAUSE].ndp_val 881 882 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 883 884 #define param_txbcopy_threshold nd_params[PARAM_TXBCOPY_THRESHOLD].ndp_val 885 #define param_rxbcopy_threshold nd_params[PARAM_RXBCOPY_THRESHOLD].ndp_val 886 #define param_recv_max_packet nd_params[PARAM_RECV_MAX_PACKET].ndp_val 887 888 /* 889 * Sync a DMA area described by a dma_area_t 890 */ 891 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 892 (area).offset, (area).alength, (flag))) 893 894 /* 895 * Find the (kernel virtual) address of block of memory 896 * described by a dma_area_t 897 */ 898 #define DMA_VPTR(area) ((area).mem_va) 899 900 /* 901 * Zero a block of memory described by a dma_area_t 902 */ 903 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 904 905 /* 906 * Next/Prev value of a cyclic index 907 */ 908 #define NEXT(index, limit) ((index) + 1 < (limit) ? (index) + 1 : 0) 909 #define PREV(index, limit) (0 == (index) ? (limit - 1) : (index) - 1) 910 911 #define NEXT_INDEX(ndx, num, lim)\ 912 (((ndx) + (num) < (lim)) ? ((ndx) + (num)) : ((ndx) + (num) - (lim))) 913 914 915 /* 916 * Property lookups 917 */ 918 #define NGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 919 DDI_PROP_DONTPASS, (n)) 920 #define NGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 921 DDI_PROP_DONTPASS, (n), -1) 922 923 924 /* 925 * Debugging ... 926 */ 927 #ifdef DEBUG 928 #define NGE_DEBUGGING 1 929 #else 930 #define NGE_DEBUGGING 0 931 #endif /* DEBUG */ 932 933 /* 934 * Bit flags in the 'debug' word ... 935 */ 936 #define NGE_DBG_STOP 0x00000001 /* early debug_enter() */ 937 #define NGE_DBG_TRACE 0x00000002 /* general flow tracing */ 938 939 #define NGE_DBG_MII 0x00000010 /* low-level MII access */ 940 #define NGE_DBG_CHIP 0x00000020 /* low(ish)-level code */ 941 942 #define NGE_DBG_RECV 0x00000100 /* receive-side code */ 943 #define NGE_DBG_SEND 0x00000200 /* packet-send code */ 944 945 #define NGE_DBG_INIT 0x00100000 /* initialisation */ 946 #define NGE_DBG_NEMO 0x00200000 /* MAC layer entry points */ 947 #define NGE_DBG_STATS 0x00400000 /* statistics */ 948 949 #define NGE_DBG_BADIOC 0x01000000 /* unknown ioctls */ 950 951 #define NGE_DBG_NDD 0x10000000 /* NDD operations */ 952 953 954 955 /* 956 * 'Do-if-debugging' macro. The parameter <command> should be one or more 957 * C statements (but without the *final* semicolon), which will either be 958 * compiled inline or completely ignored, depending on the NGE_DEBUGGING 959 * compile-time flag. 960 * 961 * You should get a compile-time error (at least on a DEBUG build) if 962 * your statement isn't actually a statement, rather than unexpected 963 * run-time behaviour caused by unintended matching of if-then-elses etc. 964 * 965 * Note that the NGE_DDB() macro itself can only be used as a statement, 966 * not an expression, and should always be followed by a semicolon. 967 */ 968 #if NGE_DEBUGGING 969 #define NGE_DDB(command) do { \ 970 { command; } \ 971 _NOTE(CONSTANTCONDITION) \ 972 } while (0) 973 #else /* NGE_DEBUGGING */ 974 #define NGE_DDB(command) 975 /* 976 * Old way of debugging. This is a poor way, as it leeaves empty 977 * statements that cause lint to croak. 978 * #define NGE_DDB(command) do { \ 979 * { _NOTE(EMPTY); } \ 980 * _NOTE(CONSTANTCONDITION) \ 981 * } while (0) 982 */ 983 #endif /* NGE_DEBUGGING */ 984 985 /* 986 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 987 * These provide the primitive conditional-call capability required. 988 * Note: the parameter <args> is a parenthesised list of the actual 989 * printf-style arguments to be passed to the debug function ... 990 */ 991 #define NGE_XDB(b, w, f, args) NGE_DDB(if ((b) & (w)) f args) 992 #define NGE_GDB(b, args) NGE_XDB(b, nge_debug, (*nge_gdb()), args) 993 #define NGE_LDB(b, args) NGE_XDB(b, ngep->debug, \ 994 (*nge_db(ngep)), args) 995 #define NGE_CDB(f, args) NGE_XDB(NGE_DBG, ngep->debug, f, args) 996 997 /* 998 * Conditional-print macros. 999 * 1000 * Define NGE_DBG to be the relevant member of the set of NGE_DBG_* values 1001 * above before using the NGE_GDEBUG() or NGE_DEBUG() macros. The 'G' 1002 * versions look at the Global debug flag word (nge_debug); the non-G 1003 * versions look in the per-instance data (ngep->debug) and so require a 1004 * variable called 'ngep' to be in scope (and initialised!) before use. 1005 * 1006 * You could redefine NGE_TRC too if you really need two different 1007 * flavours of debugging output in the same area of code, but I don't 1008 * really recommend it. 1009 * 1010 * Note: the parameter <args> is a parenthesised list of the actual 1011 * arguments to be passed to the debug function, usually a printf-style 1012 * format string and corresponding values to be formatted. 1013 */ 1014 1015 #define NGE_TRC NGE_DBG_TRACE 1016 1017 #define NGE_GTRACE(args) NGE_GDB(NGE_TRC, args) 1018 #define NGE_GDEBUG(args) NGE_GDB(NGE_DBG, args) 1019 #define NGE_TRACE(args) NGE_LDB(NGE_TRC, args) 1020 #define NGE_DEBUG(args) NGE_LDB(NGE_DBG, args) 1021 1022 /* 1023 * Debug-only action macros 1024 */ 1025 1026 1027 #define NGE_REPORT(args) NGE_DDB(nge_log args) 1028 1029 boolean_t nge_atomic_decrease(uint64_t *count_p, uint64_t n); 1030 void nge_atomic_increase(uint64_t *count_p, uint64_t n); 1031 1032 int nge_alloc_dma_mem(nge_t *ngep, size_t memsize, 1033 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p); 1034 void nge_free_dma_mem(dma_area_t *dma_p); 1035 int nge_restart(nge_t *ngep); 1036 void nge_wake_factotum(nge_t *ngep); 1037 1038 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno); 1039 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data); 1040 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno); 1041 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 1042 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno); 1043 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data); 1044 uint_t nge_chip_factotum(caddr_t args1, caddr_t args2); 1045 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset); 1046 void nge_init_dev_spec_param(nge_t *ngep); 1047 int nge_chip_stop(nge_t *ngep, boolean_t fault); 1048 void nge_restore_mac_addr(nge_t *ngep); 1049 int nge_chip_reset(nge_t *ngep); 1050 int nge_chip_start(nge_t *ngep); 1051 void nge_chip_sync(nge_t *ngep); 1052 1053 uint_t nge_chip_intr(caddr_t arg1, caddr_t arg2); 1054 enum ioc_reply nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp); 1055 1056 void nge_phys_init(nge_t *ngep); 1057 boolean_t nge_phy_reset(nge_t *ngep); 1058 uint16_t nge_mii_get16(nge_t *ngep, nge_regno_t regno); 1059 void nge_mii_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 1060 1061 void nge_recv_recycle(caddr_t arg); 1062 void nge_receive(nge_t *ngep); 1063 1064 uint_t nge_reschedule(caddr_t args1, caddr_t args2); 1065 mblk_t *nge_m_tx(void *arg, mblk_t *mp); 1066 1067 void nge_tx_recycle(nge_t *ngep, boolean_t is_intr); 1068 void nge_tx_recycle_all(nge_t *ngep); 1069 1070 enum ioc_reply nge_nd_ioctl(nge_t *ngep, queue_t *wq, 1071 mblk_t *mp, struct iocblk *iocp); 1072 int nge_nd_init(nge_t *ngep); 1073 void nge_nd_cleanup(nge_t *ngep); 1074 1075 1076 void nge_init_kstats(nge_t *ngep, int instance); 1077 void nge_fini_kstats(nge_t *ngep); 1078 int nge_m_stat(void *arg, uint_t stat, uint64_t *val); 1079 1080 uint32_t nge_atomic_shl32(uint32_t *sp, uint_t count); 1081 1082 void nge_log(nge_t *ngep, const char *fmt, ...); 1083 void nge_problem(nge_t *ngep, const char *fmt, ...); 1084 void nge_error(nge_t *ngep, const char *fmt, ...); 1085 void 1086 nge_report(nge_t *ngep, uint8_t error_id); 1087 1088 void (*nge_db(nge_t *ngep))(const char *fmt, ...); 1089 void (*nge_gdb(void))(const char *fmt, ...); 1090 extern uint32_t nge_debug; 1091 1092 /* 1093 * DESC MODE 2 1094 */ 1095 1096 extern void nge_sum_rxd_fill(void *, const ddi_dma_cookie_t *, size_t); 1097 extern uint32_t nge_sum_rxd_check(const void *, size_t *); 1098 1099 extern void nge_sum_txd_fill(void *, const ddi_dma_cookie_t *, 1100 size_t, uint32_t, boolean_t); 1101 extern uint32_t nge_sum_txd_check(const void *, size_t *); 1102 1103 /* 1104 * DESC MODE 3 1105 */ 1106 1107 extern void nge_hot_rxd_fill(void *, const ddi_dma_cookie_t *, size_t); 1108 extern uint32_t nge_hot_rxd_check(const void *, size_t *); 1109 1110 extern void nge_hot_txd_fill(void *, const ddi_dma_cookie_t *, 1111 size_t, uint32_t, boolean_t); 1112 extern uint32_t nge_hot_txd_check(const void *, size_t *); 1113 1114 #ifdef __cplusplus 1115 } 1116 #endif 1117 1118 #endif /* _SYS_NGE_H */ 1119