1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #ifndef _IXGBE_OSDEP_H 29 #define _IXGBE_OSDEP_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/byteorder.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/ddi.h> 48 #include <sys/dditypes.h> 49 #include <sys/sunddi.h> 50 #include <sys/pci.h> 51 #include <sys/atomic.h> 52 #include <sys/note.h> 53 #include "ixgbe_debug.h" 54 55 /* function declarations */ 56 struct ixgbe_hw; 57 uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t); 58 void ixgbe_write_pci_cfg(struct ixgbe_hw *, uint32_t, uint32_t); 59 60 #define usec_delay(x) drv_usecwait(x) 61 #define msec_delay(x) drv_usecwait(x * 1000) 62 63 #define OS_DEP(hw) ((struct ixgbe_osdep *)((hw)->back)) 64 65 #define false B_FALSE 66 #define true B_TRUE 67 68 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg 69 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg 70 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 71 #define PCI_COMMAND_REGISTER 0x04 72 #define PCI_EX_CONF_CAP 0xE0 73 #define SPEED_10GB 10000 74 #define SPEED_1GB 1000 75 #define SPEED_100 100 76 #define FULL_DUPLEX 2 77 78 #define IXGBE_WRITE_FLUSH(a) (void) IXGBE_READ_REG(a, IXGBE_STATUS) 79 80 #define IXGBE_WRITE_REG(a, reg, value) \ 81 ddi_put32((OS_DEP(a))->reg_handle, \ 82 (uint32_t *)((uintptr_t)(a)->hw_addr + reg), (value)) 83 84 #define IXGBE_READ_REG(a, reg) \ 85 ddi_get32((OS_DEP(a))->reg_handle, \ 86 (uint32_t *)((uintptr_t)(a)->hw_addr + reg)) 87 88 #define IXGBE_WRITE_REG64(hw, reg, value) \ 89 do { \ 90 IXGBE_WRITE_REG(hw, reg, (u32) value); \ 91 IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \ 92 _NOTE(CONSTCOND) \ 93 } while (0) 94 95 #define msec_delay_irq msec_delay 96 #define IXGBE_HTONL htonl 97 98 #define UNREFERENCED_PARAMETER(x) _NOTE(ARGUNUSED(x)) 99 100 typedef int8_t s8; 101 typedef int16_t s16; 102 typedef int32_t s32; 103 typedef int64_t s64; 104 typedef uint8_t u8; 105 typedef uint16_t u16; 106 typedef uint32_t u32; 107 typedef uint64_t u64; 108 typedef boolean_t bool; 109 110 struct ixgbe_osdep { 111 ddi_acc_handle_t reg_handle; 112 ddi_acc_handle_t cfg_handle; 113 struct ixgbe *ixgbe; 114 }; 115 116 #ifdef __cplusplus 117 } 118 #endif 119 120 #endif /* _IXGBE_OSDEP_H */ 121