1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2009, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Copyright (c) 2006 13 * Copyright (c) 2007 14 * Damien Bergamini <damien.bergamini@free.fr> 15 * 16 * Permission to use, copy, modify, and distribute this software for any 17 * purpose with or without fee is hereby granted, provided that the above 18 * copyright notice and this permission notice appear in all copies. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27 */ 28 29 #ifndef _IWH_VAR_H 30 #define _IWH_VAR_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define IWH_DMA_SYNC(area, flag) \ 37 (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 38 (area).alength, (flag)) 39 40 #define IWH_CHK_FAST_RECOVER(sc) \ 41 (sc->sc_ic.ic_state == IEEE80211_S_RUN && \ 42 sc->sc_ic.ic_opmode == IEEE80211_M_STA) 43 44 typedef struct iwh_dma_area { 45 ddi_acc_handle_t acc_hdl; /* handle for memory */ 46 caddr_t mem_va; /* CPU VA of memory */ 47 uint32_t nslots; /* number of slots */ 48 uint32_t size; /* size per slot */ 49 size_t alength; /* allocated size */ 50 /* >= product of above */ 51 ddi_dma_handle_t dma_hdl; /* DMA handle */ 52 offset_t offset; /* relative to handle */ 53 ddi_dma_cookie_t cookie; /* associated cookie */ 54 uint32_t ncookies; 55 uint32_t token; /* arbitrary identifier */ 56 } iwh_dma_t; 57 58 typedef struct iwh_tx_data { 59 iwh_dma_t dma_data; /* for sending frames */ 60 iwh_tx_desc_t *desc; 61 uint32_t paddr_desc; 62 iwh_cmd_t *cmd; 63 uint32_t paddr_cmd; 64 } iwh_tx_data_t; 65 66 typedef struct iwh_tx_ring { 67 iwh_dma_t dma_desc; /* for descriptor itself */ 68 iwh_dma_t dma_cmd; /* for command to ucode */ 69 iwh_tx_data_t *data; 70 int qid; /* ID of queue */ 71 int count; 72 int window; 73 int queued; 74 int cur; 75 int desc_cur; 76 } iwh_tx_ring_t; 77 78 typedef struct iwh_rx_data { 79 iwh_dma_t dma_data; 80 } iwh_rx_data_t; 81 82 typedef struct iwh_rx_ring { 83 iwh_dma_t dma_desc; 84 uint32_t *desc; 85 iwh_rx_data_t data[RX_QUEUE_SIZE]; 86 int cur; 87 } iwh_rx_ring_t; 88 89 90 typedef struct iwh_amrr { 91 ieee80211_node_t in; 92 uint32_t txcnt; 93 uint32_t retrycnt; 94 uint32_t success; 95 uint32_t success_threshold; 96 int recovery; 97 volatile uint32_t ht_mcs_idx; 98 } iwh_amrr_t; 99 100 struct iwh_phy_rx { 101 uint8_t flag; 102 uint8_t reserved[3]; 103 uint8_t buf[128]; 104 }; 105 106 struct iwh_beacon_missed { 107 uint32_t consecutive; 108 uint32_t total; 109 uint32_t expected; 110 uint32_t received; 111 }; 112 113 typedef struct iwh_softc { 114 struct ieee80211com sc_ic; 115 dev_info_t *sc_dip; 116 int (*sc_newstate)(struct ieee80211com *, 117 enum ieee80211_state, int); 118 void (*sc_recv_action)(ieee80211_node_t *, 119 const uint8_t *, const uint8_t *); 120 int (*sc_send_action)(ieee80211_node_t *, 121 int, int, uint16_t[4]); 122 volatile uint32_t sc_cmd_flag; 123 volatile uint32_t sc_cmd_accum; 124 125 enum ieee80211_state sc_ostate; 126 kmutex_t sc_glock; 127 kmutex_t sc_mt_lock; 128 kmutex_t sc_tx_lock; 129 kmutex_t sc_suspend_lock; 130 kcondvar_t sc_mt_cv; 131 kcondvar_t sc_tx_cv; 132 kcondvar_t sc_cmd_cv; 133 kcondvar_t sc_fw_cv; 134 kcondvar_t sc_put_seg_cv; 135 kcondvar_t sc_ucode_cv; 136 137 kthread_t *sc_mf_thread; 138 volatile uint32_t sc_mf_thread_switch; 139 140 volatile uint32_t sc_flags; 141 uint32_t sc_dmabuf_sz; 142 uint16_t sc_clsz; 143 uint8_t sc_rev; 144 uint8_t sc_resv; 145 uint16_t sc_assoc_id; 146 uint16_t sc_reserved0; 147 148 /* shared area */ 149 iwh_dma_t sc_dma_sh; 150 iwh_shared_t *sc_shared; 151 /* keep warm area */ 152 iwh_dma_t sc_dma_kw; 153 /* tx scheduler base address */ 154 uint32_t sc_scd_base_addr; 155 156 uint32_t sc_hw_rev; 157 struct iwh_phy_rx sc_rx_phy_res; 158 159 iwh_tx_ring_t sc_txq[IWH_NUM_QUEUES]; 160 iwh_rx_ring_t sc_rxq; 161 162 /* firmware dma */ 163 iwh_firmware_hdr_t *sc_hdr; 164 char *sc_boot; 165 iwh_dma_t sc_dma_fw_text; 166 iwh_dma_t sc_dma_fw_init_text; 167 iwh_dma_t sc_dma_fw_data; 168 iwh_dma_t sc_dma_fw_data_bak; 169 iwh_dma_t sc_dma_fw_init_data; 170 171 ddi_acc_handle_t sc_cfg_handle; 172 caddr_t sc_cfg_base; 173 ddi_acc_handle_t sc_handle; 174 caddr_t sc_base; 175 ddi_intr_handle_t *sc_intr_htable; 176 uint_t sc_intr_pri; 177 178 iwh_rxon_cmd_t sc_config; 179 iwh_rxon_cmd_t sc_config_save; 180 181 uint8_t sc_eep_map[IWH_SP_EEPROM_SIZE]; 182 struct iwh_eep_calibration *sc_eep_calib; 183 struct iwh_calib_results sc_calib_results; 184 uint32_t sc_scd_base; 185 186 struct iwh_alive_resp sc_card_alive_run; 187 struct iwh_init_alive_resp sc_card_alive_init; 188 iwh_ht_conf_t sc_ht_conf; 189 uint16_t sc_dev_id; 190 191 uint32_t sc_tx_timer; 192 uint32_t sc_scan_pending; 193 uint8_t *sc_fw_bin; 194 195 ddi_softint_handle_t sc_soft_hdl; 196 197 uint32_t sc_rx_softint_pending; 198 uint32_t sc_need_reschedule; 199 200 clock_t sc_clk; 201 202 /* kstats */ 203 uint32_t sc_tx_nobuf; 204 uint32_t sc_rx_nobuf; 205 uint32_t sc_tx_err; 206 uint32_t sc_rx_err; 207 uint32_t sc_tx_retries; 208 } iwh_sc_t; 209 210 #define SC_CMD_FLG_NONE (0) 211 #define SC_CMD_FLG_PENDING (1) 212 #define SC_CMD_FLG_DONE (2) 213 214 #define IWH_F_ATTACHED (1 << 0) 215 #define IWH_F_CMD_DONE (1 << 1) 216 #define IWH_F_FW_INIT (1 << 2) 217 #define IWH_F_HW_ERR_RECOVER (1 << 3) 218 #define IWH_F_RATE_AUTO_CTL (1 << 4) 219 #define IWH_F_RUNNING (1 << 5) 220 #define IWH_F_SCANNING (1 << 6) 221 #define IWH_F_SUSPEND (1 << 7) 222 #define IWH_F_RADIO_OFF (1 << 8) 223 #define IWH_F_STATISTICS (1 << 9) 224 #define IWH_F_READY (1 << 10) 225 #define IWH_F_PUT_SEG (1 << 11) 226 #define IWH_F_QUIESCED (1 << 12) 227 #define IWH_F_LAZY_RESUME (1 << 13) 228 229 #define IWH_SUCCESS 0 230 #define IWH_FAIL EIO 231 232 /* 233 * Interaction steps for 802.11e/n between net80211 module 234 * and iwh driver: 235 * -- setup link with 802.11n AP: net80211 module is responsible 236 * for setup link with 802.11n AP. iwh driver monitors current 237 * state and make relevant configurations according work mode. 238 * -- QoS parameter updating: net80211 module is responsible for 239 * extract EDCA parameters from the fram of AP, iwh driver get 240 * these parameters and make relevant configuration to HW. 241 * -- TX queue management: iwh driver place a frame into suitable 242 * TX queue according to frame type and user priority extracted 243 * from frame head. 244 * -- MIMO: iwh driver make relevant configurations in TX and RX 245 * direction according to AP mode from net80211 module. 246 * -- Link aggregation: AMSDU is implemented by net80211 module and 247 * AMPDU is implemented by both iwh driver and net80211 module. 248 * iwh driver distinguish frames in one AMPDU frame and net80211 249 * module is responsible reordering every frame. 250 * -- Block ACK: net80211 module is responsible for setup agreement 251 * with AP and iwh driver is responsible for realistic ACK. 252 * -- Rate scaling: This function is implemented independently by 253 * iwh driver. 254 * -- HT protection: This feature is also implemented by iwh driver 255 * no interaction with net80211 module. 256 */ 257 258 #ifdef __cplusplus 259 } 260 #endif 261 262 #endif /* _IWH_VAR_H */ 263