1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 #include "igb_sw.h" 32 33 static boolean_t igb_tx(igb_tx_ring_t *, mblk_t *); 34 static int igb_tx_copy(igb_tx_ring_t *, tx_control_block_t *, mblk_t *, 35 uint32_t, boolean_t); 36 static int igb_tx_bind(igb_tx_ring_t *, tx_control_block_t *, mblk_t *, 37 uint32_t); 38 static int igb_tx_fill_ring(igb_tx_ring_t *, link_list_t *, hcksum_context_t *); 39 static void igb_save_desc(tx_control_block_t *, uint64_t, size_t); 40 static tx_control_block_t *igb_get_free_list(igb_tx_ring_t *); 41 42 static void igb_get_hcksum_context(mblk_t *, hcksum_context_t *); 43 static boolean_t igb_check_hcksum_context(igb_tx_ring_t *, hcksum_context_t *); 44 static void igb_fill_hcksum_context(struct e1000_adv_tx_context_desc *, 45 hcksum_context_t *, uint32_t); 46 47 #ifndef IGB_DEBUG 48 #pragma inline(igb_save_desc) 49 #pragma inline(igb_get_hcksum_context) 50 #pragma inline(igb_check_hcksum_context) 51 #pragma inline(igb_fill_hcksum_context) 52 #endif 53 54 mblk_t * 55 igb_tx_ring_send(void *arg, mblk_t *mp) 56 { 57 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg; 58 59 ASSERT(tx_ring != NULL); 60 61 return ((igb_tx(tx_ring, mp)) ? NULL : mp); 62 } 63 64 /* 65 * igb_tx - Main transmit processing 66 * 67 * Called from igb_m_tx with an mblk ready to transmit. this 68 * routine sets up the transmit descriptors and sends data to 69 * the wire. 70 * 71 * One mblk can consist of several fragments, each fragment 72 * will be processed with different methods based on the size. 73 * For the fragments with size less than the bcopy threshold, 74 * they will be processed by using bcopy; otherwise, they will 75 * be processed by using DMA binding. 76 * 77 * To process the mblk, a tx control block is got from the 78 * free list. One tx control block contains one tx buffer, which 79 * is used to copy mblk fragments' data; and one tx DMA handle, 80 * which is used to bind a mblk fragment with DMA resource. 81 * 82 * Several small mblk fragments can be copied into one tx control 83 * block's buffer, and then the buffer will be transmitted with 84 * one tx descriptor. 85 * 86 * A large fragment only binds with one tx control block's DMA 87 * handle, and it can span several tx descriptors for transmitting. 88 * 89 * So to transmit a packet (mblk), several tx control blocks can 90 * be used. After the processing, those tx control blocks will 91 * be put to the work list. 92 */ 93 static boolean_t 94 igb_tx(igb_tx_ring_t *tx_ring, mblk_t *mp) 95 { 96 igb_t *igb = tx_ring->igb; 97 tx_type_t current_flag, next_flag; 98 uint32_t current_len, next_len; 99 uint32_t desc_total; 100 size_t mbsize; 101 int desc_num; 102 boolean_t copy_done, eop; 103 mblk_t *current_mp, *next_mp, *nmp; 104 tx_control_block_t *tcb; 105 hcksum_context_t hcksum_context, *hcksum; 106 link_list_t pending_list; 107 108 /* Get the mblk size */ 109 mbsize = 0; 110 for (nmp = mp; nmp != NULL; nmp = nmp->b_cont) { 111 mbsize += MBLK_LEN(nmp); 112 } 113 114 /* 115 * If the mblk size exceeds the max frame size, 116 * discard this mblk, and return B_TRUE 117 */ 118 if (mbsize > (igb->max_frame_size - ETHERFCSL)) { 119 freemsg(mp); 120 IGB_DEBUGLOG_0(igb, "igb_tx: packet oversize"); 121 return (B_TRUE); 122 } 123 124 /* 125 * Check and recycle tx descriptors. 126 * The recycle threshold here should be selected carefully 127 */ 128 if (tx_ring->tbd_free < tx_ring->recycle_thresh) 129 tx_ring->tx_recycle(tx_ring); 130 131 /* 132 * After the recycling, if the tbd_free is less than the 133 * overload_threshold, assert overload, return B_FALSE; 134 * and we need to re-schedule the tx again. 135 */ 136 if (tx_ring->tbd_free < tx_ring->overload_thresh) { 137 tx_ring->reschedule = B_TRUE; 138 IGB_DEBUG_STAT(tx_ring->stat_overload); 139 return (B_FALSE); 140 } 141 142 /* 143 * The pending_list is a linked list that is used to save 144 * the tx control blocks that have packet data processed 145 * but have not put the data to the tx descriptor ring. 146 * It is used to reduce the lock contention of the tx_lock. 147 */ 148 LINK_LIST_INIT(&pending_list); 149 desc_num = 0; 150 desc_total = 0; 151 152 current_mp = mp; 153 current_len = MBLK_LEN(current_mp); 154 /* 155 * Decide which method to use for the first fragment 156 */ 157 current_flag = (current_len <= tx_ring->copy_thresh) ? 158 USE_COPY : USE_DMA; 159 /* 160 * If the mblk includes several contiguous small fragments, 161 * they may be copied into one buffer. This flag is used to 162 * indicate whether there are pending fragments that need to 163 * be copied to the current tx buffer. 164 * 165 * If this flag is B_TRUE, it indicates that a new tx control 166 * block is needed to process the next fragment using either 167 * copy or DMA binding. 168 * 169 * Otherwise, it indicates that the next fragment will be 170 * copied to the current tx buffer that is maintained by the 171 * current tx control block. No new tx control block is needed. 172 */ 173 copy_done = B_TRUE; 174 while (current_mp) { 175 next_mp = current_mp->b_cont; 176 eop = (next_mp == NULL); /* Last fragment of the packet? */ 177 next_len = eop ? 0: MBLK_LEN(next_mp); 178 179 /* 180 * When the current fragment is an empty fragment, if 181 * the next fragment will still be copied to the current 182 * tx buffer, we cannot skip this fragment here. Because 183 * the copy processing is pending for completion. We have 184 * to process this empty fragment in the tx_copy routine. 185 * 186 * If the copy processing is completed or a DMA binding 187 * processing is just completed, we can just skip this 188 * empty fragment. 189 */ 190 if ((current_len == 0) && (copy_done)) { 191 current_mp = next_mp; 192 current_len = next_len; 193 current_flag = (current_len <= tx_ring->copy_thresh) ? 194 USE_COPY : USE_DMA; 195 continue; 196 } 197 198 if (copy_done) { 199 /* 200 * Get a new tx control block from the free list 201 */ 202 tcb = igb_get_free_list(tx_ring); 203 204 if (tcb == NULL) { 205 IGB_DEBUG_STAT(tx_ring->stat_fail_no_tcb); 206 goto tx_failure; 207 } 208 209 /* 210 * Push the tx control block to the pending list 211 * to avoid using lock too early 212 */ 213 LIST_PUSH_TAIL(&pending_list, &tcb->link); 214 } 215 216 if (current_flag == USE_COPY) { 217 /* 218 * Check whether to use bcopy or DMA binding to process 219 * the next fragment, and if using bcopy, whether we 220 * need to continue copying the next fragment into the 221 * current tx buffer. 222 */ 223 ASSERT((tcb->tx_buf.len + current_len) <= 224 tcb->tx_buf.size); 225 226 if (eop) { 227 /* 228 * This is the last fragment of the packet, so 229 * the copy processing will be completed with 230 * this fragment. 231 */ 232 next_flag = USE_NONE; 233 copy_done = B_TRUE; 234 } else if ((tcb->tx_buf.len + current_len + next_len) > 235 tcb->tx_buf.size) { 236 /* 237 * If the next fragment is too large to be 238 * copied to the current tx buffer, we need 239 * to complete the current copy processing. 240 */ 241 next_flag = (next_len > tx_ring->copy_thresh) ? 242 USE_DMA: USE_COPY; 243 copy_done = B_TRUE; 244 } else if (next_len > tx_ring->copy_thresh) { 245 /* 246 * The next fragment needs to be processed with 247 * DMA binding. So the copy prcessing will be 248 * completed with the current fragment. 249 */ 250 next_flag = USE_DMA; 251 copy_done = B_TRUE; 252 } else { 253 /* 254 * Continue to copy the next fragment to the 255 * current tx buffer. 256 */ 257 next_flag = USE_COPY; 258 copy_done = B_FALSE; 259 } 260 261 desc_num = igb_tx_copy(tx_ring, tcb, current_mp, 262 current_len, copy_done); 263 } else { 264 /* 265 * Check whether to use bcopy or DMA binding to process 266 * the next fragment. 267 */ 268 next_flag = (next_len > tx_ring->copy_thresh) ? 269 USE_DMA: USE_COPY; 270 ASSERT(copy_done == B_TRUE); 271 272 desc_num = igb_tx_bind(tx_ring, tcb, current_mp, 273 current_len); 274 } 275 276 if (desc_num > 0) 277 desc_total += desc_num; 278 else if (desc_num < 0) 279 goto tx_failure; 280 281 current_mp = next_mp; 282 current_len = next_len; 283 current_flag = next_flag; 284 } 285 286 /* 287 * Attach the mblk to the last tx control block 288 */ 289 ASSERT(tcb); 290 ASSERT(tcb->mp == NULL); 291 tcb->mp = mp; 292 293 if (igb->tx_hcksum_enable) { 294 /* 295 * Retrieve checksum context information from the mblk that will 296 * be used to decide whether/how to fill the context descriptor. 297 */ 298 hcksum = &hcksum_context; 299 igb_get_hcksum_context(mp, hcksum); 300 } else { 301 hcksum = NULL; 302 } 303 304 /* 305 * Before fill the tx descriptor ring with the data, we need to 306 * ensure there are adequate free descriptors for transmit 307 * (including one context descriptor). 308 */ 309 if (tx_ring->tbd_free < (desc_total + 1)) { 310 tx_ring->tx_recycle(tx_ring); 311 } 312 313 mutex_enter(&tx_ring->tx_lock); 314 315 /* 316 * If the number of free tx descriptors is not enough for transmit 317 * then return failure. 318 * 319 * Note: we must put this check under the mutex protection to 320 * ensure the correctness when multiple threads access it in 321 * parallel. 322 */ 323 if (tx_ring->tbd_free < (desc_total + 1)) { 324 IGB_DEBUG_STAT(tx_ring->stat_fail_no_tbd); 325 mutex_exit(&tx_ring->tx_lock); 326 goto tx_failure; 327 } 328 329 desc_num = igb_tx_fill_ring(tx_ring, &pending_list, hcksum); 330 331 ASSERT((desc_num == desc_total) || (desc_num == (desc_total + 1))); 332 333 mutex_exit(&tx_ring->tx_lock); 334 335 return (B_TRUE); 336 337 tx_failure: 338 /* 339 * Discard the mblk and free the used resources 340 */ 341 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 342 while (tcb) { 343 tcb->mp = NULL; 344 345 igb_free_tcb(tcb); 346 347 tcb = (tx_control_block_t *) 348 LIST_GET_NEXT(&pending_list, &tcb->link); 349 } 350 351 /* 352 * Return the tx control blocks in the pending list to the free list. 353 */ 354 igb_put_free_list(tx_ring, &pending_list); 355 356 /* Transmit failed, do not drop the mblk, rechedule the transmit */ 357 tx_ring->reschedule = B_TRUE; 358 359 return (B_FALSE); 360 } 361 362 /* 363 * igb_tx_copy 364 * 365 * Copy the mblk fragment to the pre-allocated tx buffer 366 */ 367 static int 368 igb_tx_copy(igb_tx_ring_t *tx_ring, tx_control_block_t *tcb, mblk_t *mp, 369 uint32_t len, boolean_t copy_done) 370 { 371 dma_buffer_t *tx_buf; 372 uint32_t desc_num; 373 _NOTE(ARGUNUSED(tx_ring)); 374 375 tx_buf = &tcb->tx_buf; 376 377 /* 378 * Copy the packet data of the mblk fragment into the 379 * pre-allocated tx buffer, which is maintained by the 380 * tx control block. 381 * 382 * Several mblk fragments can be copied into one tx buffer. 383 * The destination address of the current copied fragment in 384 * the tx buffer is next to the end of the previous copied 385 * fragment. 386 */ 387 if (len > 0) { 388 bcopy(mp->b_rptr, tx_buf->address + tx_buf->len, len); 389 390 tx_buf->len += len; 391 tcb->frag_num++; 392 } 393 394 desc_num = 0; 395 396 /* 397 * If it is the last fragment copied to the current tx buffer, 398 * in other words, if there's no remaining fragment or the remaining 399 * fragment requires a new tx control block to process, we need to 400 * complete the current copy processing by syncing up the current 401 * DMA buffer and saving the descriptor data. 402 */ 403 if (copy_done) { 404 /* 405 * Sync the DMA buffer of the packet data 406 */ 407 DMA_SYNC(tx_buf, DDI_DMA_SYNC_FORDEV); 408 409 tcb->tx_type = USE_COPY; 410 411 /* 412 * Save the address and length to the private data structure 413 * of the tx control block, which will be used to fill the 414 * tx descriptor ring after all the fragments are processed. 415 */ 416 igb_save_desc(tcb, tx_buf->dma_address, tx_buf->len); 417 desc_num++; 418 } 419 420 return (desc_num); 421 } 422 423 /* 424 * igb_tx_bind 425 * 426 * Bind the mblk fragment with DMA 427 */ 428 static int 429 igb_tx_bind(igb_tx_ring_t *tx_ring, tx_control_block_t *tcb, mblk_t *mp, 430 uint32_t len) 431 { 432 int status, i; 433 ddi_dma_cookie_t dma_cookie; 434 uint_t ncookies; 435 int desc_num; 436 437 /* 438 * Use DMA binding to process the mblk fragment 439 */ 440 status = ddi_dma_addr_bind_handle(tcb->tx_dma_handle, NULL, 441 (caddr_t)mp->b_rptr, len, 442 DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, 443 0, &dma_cookie, &ncookies); 444 445 if (status != DDI_DMA_MAPPED) { 446 IGB_DEBUG_STAT(tx_ring->stat_fail_dma_bind); 447 return (-1); 448 } 449 450 tcb->frag_num++; 451 tcb->tx_type = USE_DMA; 452 /* 453 * Each fragment can span several cookies. One cookie will have 454 * one tx descriptor to transmit. 455 */ 456 desc_num = 0; 457 for (i = ncookies; i > 0; i--) { 458 /* 459 * Save the address and length to the private data structure 460 * of the tx control block, which will be used to fill the 461 * tx descriptor ring after all the fragments are processed. 462 */ 463 igb_save_desc(tcb, 464 dma_cookie.dmac_laddress, 465 dma_cookie.dmac_size); 466 467 desc_num++; 468 469 if (i > 1) 470 ddi_dma_nextcookie(tcb->tx_dma_handle, &dma_cookie); 471 } 472 473 return (desc_num); 474 } 475 476 /* 477 * igb_get_hcksum_context 478 * 479 * Get the hcksum context information from the mblk 480 */ 481 static void 482 igb_get_hcksum_context(mblk_t *mp, hcksum_context_t *hcksum) 483 { 484 uint32_t start; 485 uint32_t flags; 486 uint32_t len; 487 uint32_t size; 488 uint32_t offset; 489 unsigned char *pos; 490 ushort_t etype; 491 uint32_t mac_hdr_len; 492 uint32_t l4_proto; 493 494 ASSERT(mp != NULL); 495 496 hcksum_retrieve(mp, NULL, NULL, &start, NULL, NULL, NULL, &flags); 497 498 hcksum->hcksum_flags = flags; 499 500 if (flags == 0) 501 return; 502 503 etype = 0; 504 mac_hdr_len = 0; 505 l4_proto = 0; 506 507 /* 508 * Firstly get the position of the ether_type/ether_tpid. 509 * Here we don't assume the ether (VLAN) header is fully included 510 * in one mblk fragment, so we go thourgh the fragments to parse 511 * the ether type. 512 */ 513 size = len = MBLK_LEN(mp); 514 offset = offsetof(struct ether_header, ether_type); 515 while (size <= offset) { 516 mp = mp->b_cont; 517 ASSERT(mp != NULL); 518 len = MBLK_LEN(mp); 519 size += len; 520 } 521 pos = mp->b_rptr + offset + len - size; 522 523 etype = ntohs(*(ushort_t *)(uintptr_t)pos); 524 if (etype == ETHERTYPE_VLAN) { 525 /* 526 * Get the position of the ether_type in VLAN header 527 */ 528 offset = offsetof(struct ether_vlan_header, ether_type); 529 while (size <= offset) { 530 mp = mp->b_cont; 531 ASSERT(mp != NULL); 532 len = MBLK_LEN(mp); 533 size += len; 534 } 535 pos = mp->b_rptr + offset + len - size; 536 537 etype = ntohs(*(ushort_t *)(uintptr_t)pos); 538 mac_hdr_len = sizeof (struct ether_vlan_header); 539 } else { 540 mac_hdr_len = sizeof (struct ether_header); 541 } 542 543 /* 544 * Here we don't assume the IP(V6) header is fully included in 545 * one mblk fragment, so we go thourgh the fragments to parse 546 * the protocol type. 547 */ 548 switch (etype) { 549 case ETHERTYPE_IP: 550 offset = offsetof(ipha_t, ipha_protocol) + mac_hdr_len; 551 while (size <= offset) { 552 mp = mp->b_cont; 553 ASSERT(mp != NULL); 554 len = MBLK_LEN(mp); 555 size += len; 556 } 557 pos = mp->b_rptr + offset + len - size; 558 559 l4_proto = *(uint8_t *)pos; 560 break; 561 case ETHERTYPE_IPV6: 562 offset = offsetof(ip6_t, ip6_nxt) + mac_hdr_len; 563 while (size <= offset) { 564 mp = mp->b_cont; 565 ASSERT(mp != NULL); 566 len = MBLK_LEN(mp); 567 size += len; 568 } 569 pos = mp->b_rptr + offset + len - size; 570 571 l4_proto = *(uint8_t *)pos; 572 break; 573 default: 574 /* Unrecoverable error */ 575 IGB_DEBUGLOG_0(NULL, "Ether type error with tx hcksum"); 576 return; 577 } 578 579 hcksum->mac_hdr_len = mac_hdr_len; 580 hcksum->ip_hdr_len = start; 581 hcksum->l4_proto = l4_proto; 582 } 583 584 /* 585 * igb_check_hcksum_context 586 * 587 * Check if a new context descriptor is needed 588 */ 589 static boolean_t 590 igb_check_hcksum_context(igb_tx_ring_t *tx_ring, hcksum_context_t *hcksum) 591 { 592 hcksum_context_t *last; 593 594 if (hcksum == NULL) 595 return (B_FALSE); 596 597 /* 598 * Compare the checksum data retrieved from the mblk and the 599 * stored checksum data of the last context descriptor. The data 600 * need to be checked are: 601 * hcksum_flags 602 * l4_proto 603 * mac_hdr_len 604 * ip_hdr_len 605 * Either one of the above data is changed, a new context descriptor 606 * will be needed. 607 */ 608 last = &tx_ring->hcksum_context; 609 610 if (hcksum->hcksum_flags != 0) { 611 if ((hcksum->hcksum_flags != last->hcksum_flags) || 612 (hcksum->l4_proto != last->l4_proto) || 613 (hcksum->mac_hdr_len != last->mac_hdr_len) || 614 (hcksum->ip_hdr_len != last->ip_hdr_len)) { 615 616 return (B_TRUE); 617 } 618 } 619 620 return (B_FALSE); 621 } 622 623 /* 624 * igb_fill_hcksum_context 625 * 626 * Fill the context descriptor with hardware checksum informations 627 */ 628 static void 629 igb_fill_hcksum_context(struct e1000_adv_tx_context_desc *ctx_tbd, 630 hcksum_context_t *hcksum, uint32_t ring_index) 631 { 632 /* 633 * Fill the context descriptor with the checksum 634 * context information we've got 635 */ 636 ctx_tbd->vlan_macip_lens = hcksum->ip_hdr_len; 637 ctx_tbd->vlan_macip_lens |= hcksum->mac_hdr_len << 638 E1000_ADVTXD_MACLEN_SHIFT; 639 640 ctx_tbd->type_tucmd_mlhl = 641 E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 642 643 if (hcksum->hcksum_flags & HCK_IPV4_HDRCKSUM) 644 ctx_tbd->type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 645 646 if (hcksum->hcksum_flags & HCK_PARTIALCKSUM) { 647 switch (hcksum->l4_proto) { 648 case IPPROTO_TCP: 649 ctx_tbd->type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 650 break; 651 case IPPROTO_UDP: 652 /* 653 * We don't have to explicitly set: 654 * ctx_tbd->type_tucmd_mlhl |= 655 * E1000_ADVTXD_TUCMD_L4T_UDP; 656 * Because E1000_ADVTXD_TUCMD_L4T_UDP == 0b 657 */ 658 break; 659 default: 660 /* Unrecoverable error */ 661 IGB_DEBUGLOG_0(NULL, "L4 type error with tx hcksum"); 662 break; 663 } 664 } 665 666 ctx_tbd->seqnum_seed = 0; 667 ctx_tbd->mss_l4len_idx = ring_index << 4; 668 } 669 670 /* 671 * igb_tx_fill_ring 672 * 673 * Fill the tx descriptor ring with the data 674 */ 675 static int 676 igb_tx_fill_ring(igb_tx_ring_t *tx_ring, link_list_t *pending_list, 677 hcksum_context_t *hcksum) 678 { 679 struct e1000_hw *hw = &tx_ring->igb->hw; 680 boolean_t load_context; 681 uint32_t index, tcb_index, desc_num; 682 union e1000_adv_tx_desc *tbd, *first_tbd; 683 tx_control_block_t *tcb, *first_tcb; 684 uint32_t hcksum_flags; 685 int i; 686 igb_t *igb = tx_ring->igb; 687 688 ASSERT(mutex_owned(&tx_ring->tx_lock)); 689 690 tbd = NULL; 691 first_tbd = NULL; 692 first_tcb = NULL; 693 desc_num = 0; 694 hcksum_flags = 0; 695 load_context = B_FALSE; 696 697 /* 698 * Get the index of the first tx descriptor that will be filled, 699 * and the index of the first work list item that will be attached 700 * with the first used tx control block in the pending list. 701 * Note: the two indexes are the same. 702 */ 703 index = tx_ring->tbd_tail; 704 tcb_index = tx_ring->tbd_tail; 705 706 if (hcksum != NULL) { 707 hcksum_flags = hcksum->hcksum_flags; 708 709 /* 710 * Check if a new context descriptor is needed for this packet 711 */ 712 load_context = igb_check_hcksum_context(tx_ring, hcksum); 713 if (load_context) { 714 first_tcb = (tx_control_block_t *) 715 LIST_GET_HEAD(pending_list); 716 tbd = &tx_ring->tbd_ring[index]; 717 718 /* 719 * Fill the context descriptor with the 720 * hardware checksum offload informations. 721 */ 722 igb_fill_hcksum_context( 723 (struct e1000_adv_tx_context_desc *)tbd, hcksum, 724 tx_ring->index); 725 726 index = NEXT_INDEX(index, 1, tx_ring->ring_size); 727 desc_num++; 728 729 /* 730 * Store the checksum context data if 731 * a new context descriptor is added 732 */ 733 tx_ring->hcksum_context = *hcksum; 734 } 735 } 736 737 first_tbd = &tx_ring->tbd_ring[index]; 738 739 /* 740 * Fill tx data descriptors with the data saved in the pending list. 741 * The tx control blocks in the pending list are added to the work list 742 * at the same time. 743 * 744 * The work list is strictly 1:1 corresponding to the descriptor ring. 745 * One item of the work list corresponds to one tx descriptor. Because 746 * one tx control block can span multiple tx descriptors, the tx 747 * control block will be added to the first work list item that 748 * corresponds to the first tx descriptor generated from that tx 749 * control block. 750 */ 751 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 752 while (tcb != NULL) { 753 754 for (i = 0; i < tcb->desc_num; i++) { 755 tbd = &tx_ring->tbd_ring[index]; 756 757 tbd->read.buffer_addr = tcb->desc[i].address; 758 tbd->read.cmd_type_len = tcb->desc[i].length; 759 760 tbd->read.cmd_type_len |= E1000_ADVTXD_DCMD_RS | 761 E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_DATA; 762 763 tbd->read.olinfo_status = 0; 764 765 index = NEXT_INDEX(index, 1, tx_ring->ring_size); 766 desc_num++; 767 } 768 769 if (first_tcb != NULL) { 770 /* 771 * Count the checksum context descriptor for 772 * the first tx control block. 773 */ 774 first_tcb->desc_num++; 775 first_tcb = NULL; 776 } 777 778 /* 779 * Add the tx control block to the work list 780 */ 781 ASSERT(tx_ring->work_list[tcb_index] == NULL); 782 tx_ring->work_list[tcb_index] = tcb; 783 784 tcb_index = index; 785 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 786 } 787 788 /* 789 * The Insert Ethernet CRC (IFCS) bit and the checksum fields are only 790 * valid in the first descriptor of the packet. 791 */ 792 ASSERT(first_tbd != NULL); 793 first_tbd->read.cmd_type_len |= E1000_ADVTXD_DCMD_IFCS; 794 795 /* Set hardware checksum bits */ 796 if (hcksum_flags != 0) { 797 if (hcksum_flags & HCK_IPV4_HDRCKSUM) 798 first_tbd->read.olinfo_status |= 799 E1000_TXD_POPTS_IXSM << 8; 800 if (hcksum_flags & HCK_PARTIALCKSUM) 801 first_tbd->read.olinfo_status |= 802 E1000_TXD_POPTS_TXSM << 8; 803 first_tbd->read.olinfo_status |= tx_ring->index << 4; 804 } 805 806 /* 807 * The last descriptor of packet needs End Of Packet (EOP), 808 * and Report Status (RS) bits set 809 */ 810 ASSERT(tbd != NULL); 811 tbd->read.cmd_type_len |= 812 E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS; 813 814 IGB_DEBUG_STAT(tx_ring->stat_pkt_cnt); 815 816 /* 817 * Sync the DMA buffer of the tx descriptor ring 818 */ 819 DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORDEV); 820 821 /* 822 * Update the number of the free tx descriptors. 823 * The mutual exclusion between the transmission and the recycling 824 * (for the tx descriptor ring and the work list) is implemented 825 * with the atomic operation on the number of the free tx descriptors. 826 * 827 * Note: we should always decrement the counter tbd_free before 828 * advancing the hardware TDT pointer to avoid the race condition - 829 * before the counter tbd_free is decremented, the transmit of the 830 * tx descriptors has done and the counter tbd_free is increased by 831 * the tx recycling. 832 */ 833 i = igb_atomic_reserve(&tx_ring->tbd_free, desc_num); 834 ASSERT(i >= 0); 835 836 tx_ring->tbd_tail = index; 837 838 /* 839 * Advance the hardware TDT pointer of the tx descriptor ring 840 */ 841 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), index); 842 843 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 844 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 845 } 846 847 return (desc_num); 848 } 849 850 /* 851 * igb_save_desc 852 * 853 * Save the address/length pair to the private array 854 * of the tx control block. The address/length pairs 855 * will be filled into the tx descriptor ring later. 856 */ 857 static void 858 igb_save_desc(tx_control_block_t *tcb, uint64_t address, size_t length) 859 { 860 sw_desc_t *desc; 861 862 desc = &tcb->desc[tcb->desc_num]; 863 desc->address = address; 864 desc->length = length; 865 866 tcb->desc_num++; 867 } 868 869 /* 870 * igb_tx_recycle_legacy 871 * 872 * Recycle the tx descriptors and tx control blocks. 873 * 874 * The work list is traversed to check if the corresponding 875 * tx descriptors have been transmitted. If so, the resources 876 * bound to the tx control blocks will be freed, and those 877 * tx control blocks will be returned to the free list. 878 */ 879 uint32_t 880 igb_tx_recycle_legacy(igb_tx_ring_t *tx_ring) 881 { 882 uint32_t index, last_index; 883 int desc_num; 884 boolean_t desc_done; 885 tx_control_block_t *tcb; 886 link_list_t pending_list; 887 igb_t *igb = tx_ring->igb; 888 889 /* 890 * The mutex_tryenter() is used to avoid unnecessary 891 * lock contention. 892 */ 893 if (mutex_tryenter(&tx_ring->recycle_lock) == 0) 894 return (0); 895 896 ASSERT(tx_ring->tbd_free <= tx_ring->ring_size); 897 898 if (tx_ring->tbd_free == tx_ring->ring_size) { 899 tx_ring->recycle_fail = 0; 900 tx_ring->stall_watchdog = 0; 901 mutex_exit(&tx_ring->recycle_lock); 902 return (0); 903 } 904 905 /* 906 * Sync the DMA buffer of the tx descriptor ring 907 */ 908 DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORKERNEL); 909 910 if (igb_check_dma_handle( 911 tx_ring->tbd_area.dma_handle) != DDI_FM_OK) { 912 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 913 } 914 915 LINK_LIST_INIT(&pending_list); 916 desc_num = 0; 917 index = tx_ring->tbd_head; /* Index of next tbd/tcb to recycle */ 918 919 tcb = tx_ring->work_list[index]; 920 ASSERT(tcb != NULL); 921 922 desc_done = B_TRUE; 923 while (desc_done && (tcb != NULL)) { 924 925 /* 926 * Get the last tx descriptor of the tx control block. 927 * If the last tx descriptor is done, it is done with 928 * all the tx descriptors of the tx control block. 929 * Then the tx control block and all the corresponding 930 * tx descriptors can be recycled. 931 */ 932 last_index = NEXT_INDEX(index, tcb->desc_num - 1, 933 tx_ring->ring_size); 934 935 /* 936 * Check if the Descriptor Done bit is set 937 */ 938 desc_done = tx_ring->tbd_ring[last_index].wb.status & 939 E1000_TXD_STAT_DD; 940 if (desc_done) { 941 /* 942 * Strip off the tx control block from the work list, 943 * and add it to the pending list. 944 */ 945 tx_ring->work_list[index] = NULL; 946 LIST_PUSH_TAIL(&pending_list, &tcb->link); 947 948 /* 949 * Count the total number of the tx descriptors recycled 950 */ 951 desc_num += tcb->desc_num; 952 953 /* 954 * Advance the index of the tx descriptor ring 955 */ 956 index = NEXT_INDEX(last_index, 1, tx_ring->ring_size); 957 958 tcb = tx_ring->work_list[index]; 959 } 960 } 961 962 /* 963 * If no tx descriptors are recycled, no need to do more processing 964 */ 965 if (desc_num == 0) { 966 tx_ring->recycle_fail++; 967 mutex_exit(&tx_ring->recycle_lock); 968 return (0); 969 } 970 971 tx_ring->recycle_fail = 0; 972 tx_ring->stall_watchdog = 0; 973 974 /* 975 * Update the head index of the tx descriptor ring 976 */ 977 tx_ring->tbd_head = index; 978 979 /* 980 * Update the number of the free tx descriptors with atomic operations 981 */ 982 atomic_add_32(&tx_ring->tbd_free, desc_num); 983 984 mutex_exit(&tx_ring->recycle_lock); 985 986 /* 987 * Free the resources used by the tx control blocks 988 * in the pending list 989 */ 990 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 991 while (tcb != NULL) { 992 /* 993 * Release the resources occupied by the tx control block 994 */ 995 igb_free_tcb(tcb); 996 997 tcb = (tx_control_block_t *) 998 LIST_GET_NEXT(&pending_list, &tcb->link); 999 } 1000 1001 /* 1002 * Add the tx control blocks in the pending list to the free list. 1003 */ 1004 igb_put_free_list(tx_ring, &pending_list); 1005 1006 return (desc_num); 1007 } 1008 1009 /* 1010 * igb_tx_recycle_head_wb 1011 * 1012 * Check the head write-back, and recycle all the transmitted 1013 * tx descriptors and tx control blocks. 1014 */ 1015 uint32_t 1016 igb_tx_recycle_head_wb(igb_tx_ring_t *tx_ring) 1017 { 1018 uint32_t index; 1019 uint32_t head_wb; 1020 int desc_num; 1021 tx_control_block_t *tcb; 1022 link_list_t pending_list; 1023 igb_t *igb = tx_ring->igb; 1024 1025 /* 1026 * The mutex_tryenter() is used to avoid unnecessary 1027 * lock contention. 1028 */ 1029 if (mutex_tryenter(&tx_ring->recycle_lock) == 0) 1030 return (0); 1031 1032 ASSERT(tx_ring->tbd_free <= tx_ring->ring_size); 1033 1034 if (tx_ring->tbd_free == tx_ring->ring_size) { 1035 tx_ring->recycle_fail = 0; 1036 tx_ring->stall_watchdog = 0; 1037 mutex_exit(&tx_ring->recycle_lock); 1038 return (0); 1039 } 1040 1041 /* 1042 * Sync the DMA buffer of the tx descriptor ring 1043 * 1044 * Note: For head write-back mode, the tx descriptors will not 1045 * be written back, but the head write-back value is stored at 1046 * the last extra tbd at the end of the DMA area, we still need 1047 * to sync the head write-back value for kernel. 1048 * 1049 * DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORKERNEL); 1050 */ 1051 (void) ddi_dma_sync(tx_ring->tbd_area.dma_handle, 1052 sizeof (union e1000_adv_tx_desc) * tx_ring->ring_size, 1053 sizeof (uint32_t), 1054 DDI_DMA_SYNC_FORKERNEL); 1055 1056 if (igb_check_dma_handle( 1057 tx_ring->tbd_area.dma_handle) != DDI_FM_OK) { 1058 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 1059 } 1060 1061 LINK_LIST_INIT(&pending_list); 1062 desc_num = 0; 1063 index = tx_ring->tbd_head; /* Next index to clean */ 1064 1065 /* 1066 * Get the value of head write-back 1067 */ 1068 head_wb = *tx_ring->tbd_head_wb; 1069 while (index != head_wb) { 1070 tcb = tx_ring->work_list[index]; 1071 ASSERT(tcb != NULL); 1072 1073 if (OFFSET(index, head_wb, tx_ring->ring_size) < 1074 tcb->desc_num) { 1075 /* 1076 * The current tx control block is not 1077 * completely transmitted, stop recycling 1078 */ 1079 break; 1080 } 1081 1082 /* 1083 * Strip off the tx control block from the work list, 1084 * and add it to the pending list. 1085 */ 1086 tx_ring->work_list[index] = NULL; 1087 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1088 1089 /* 1090 * Advance the index of the tx descriptor ring 1091 */ 1092 index = NEXT_INDEX(index, tcb->desc_num, tx_ring->ring_size); 1093 1094 /* 1095 * Count the total number of the tx descriptors recycled 1096 */ 1097 desc_num += tcb->desc_num; 1098 } 1099 1100 /* 1101 * If no tx descriptors are recycled, no need to do more processing 1102 */ 1103 if (desc_num == 0) { 1104 tx_ring->recycle_fail++; 1105 mutex_exit(&tx_ring->recycle_lock); 1106 return (0); 1107 } 1108 1109 tx_ring->recycle_fail = 0; 1110 tx_ring->stall_watchdog = 0; 1111 1112 /* 1113 * Update the head index of the tx descriptor ring 1114 */ 1115 tx_ring->tbd_head = index; 1116 1117 /* 1118 * Update the number of the free tx descriptors with atomic operations 1119 */ 1120 atomic_add_32(&tx_ring->tbd_free, desc_num); 1121 1122 mutex_exit(&tx_ring->recycle_lock); 1123 1124 /* 1125 * Free the resources used by the tx control blocks 1126 * in the pending list 1127 */ 1128 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 1129 while (tcb) { 1130 /* 1131 * Release the resources occupied by the tx control block 1132 */ 1133 igb_free_tcb(tcb); 1134 1135 tcb = (tx_control_block_t *) 1136 LIST_GET_NEXT(&pending_list, &tcb->link); 1137 } 1138 1139 /* 1140 * Add the tx control blocks in the pending list to the free list. 1141 */ 1142 igb_put_free_list(tx_ring, &pending_list); 1143 1144 return (desc_num); 1145 } 1146 1147 /* 1148 * igb_free_tcb - free up the tx control block 1149 * 1150 * Free the resources of the tx control block, including 1151 * unbind the previously bound DMA handle, and reset other 1152 * control fields. 1153 */ 1154 void 1155 igb_free_tcb(tx_control_block_t *tcb) 1156 { 1157 switch (tcb->tx_type) { 1158 case USE_COPY: 1159 /* 1160 * Reset the buffer length that is used for copy 1161 */ 1162 tcb->tx_buf.len = 0; 1163 break; 1164 case USE_DMA: 1165 /* 1166 * Release the DMA resource that is used for 1167 * DMA binding. 1168 */ 1169 (void) ddi_dma_unbind_handle(tcb->tx_dma_handle); 1170 break; 1171 default: 1172 break; 1173 } 1174 1175 /* 1176 * Free the mblk 1177 */ 1178 if (tcb->mp != NULL) { 1179 freemsg(tcb->mp); 1180 tcb->mp = NULL; 1181 } 1182 1183 tcb->tx_type = USE_NONE; 1184 tcb->frag_num = 0; 1185 tcb->desc_num = 0; 1186 } 1187 1188 /* 1189 * igb_get_free_list - Get a free tx control block from the free list 1190 * 1191 * The atomic operation on the number of the available tx control block 1192 * in the free list is used to keep this routine mutual exclusive with 1193 * the routine igb_put_check_list. 1194 */ 1195 static tx_control_block_t * 1196 igb_get_free_list(igb_tx_ring_t *tx_ring) 1197 { 1198 tx_control_block_t *tcb; 1199 1200 /* 1201 * Check and update the number of the free tx control block 1202 * in the free list. 1203 */ 1204 if (igb_atomic_reserve(&tx_ring->tcb_free, 1) < 0) 1205 return (NULL); 1206 1207 mutex_enter(&tx_ring->tcb_head_lock); 1208 1209 tcb = tx_ring->free_list[tx_ring->tcb_head]; 1210 ASSERT(tcb != NULL); 1211 tx_ring->free_list[tx_ring->tcb_head] = NULL; 1212 tx_ring->tcb_head = NEXT_INDEX(tx_ring->tcb_head, 1, 1213 tx_ring->free_list_size); 1214 1215 mutex_exit(&tx_ring->tcb_head_lock); 1216 1217 return (tcb); 1218 } 1219 1220 /* 1221 * igb_put_free_list 1222 * 1223 * Put a list of used tx control blocks back to the free list 1224 * 1225 * A mutex is used here to ensure the serialization. The mutual exclusion 1226 * between igb_get_free_list and igb_put_free_list is implemented with 1227 * the atomic operation on the counter tcb_free. 1228 */ 1229 void 1230 igb_put_free_list(igb_tx_ring_t *tx_ring, link_list_t *pending_list) 1231 { 1232 uint32_t index; 1233 int tcb_num; 1234 tx_control_block_t *tcb; 1235 1236 mutex_enter(&tx_ring->tcb_tail_lock); 1237 1238 index = tx_ring->tcb_tail; 1239 1240 tcb_num = 0; 1241 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 1242 while (tcb != NULL) { 1243 ASSERT(tx_ring->free_list[index] == NULL); 1244 tx_ring->free_list[index] = tcb; 1245 1246 tcb_num++; 1247 1248 index = NEXT_INDEX(index, 1, tx_ring->free_list_size); 1249 1250 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 1251 } 1252 1253 tx_ring->tcb_tail = index; 1254 1255 /* 1256 * Update the number of the free tx control block 1257 * in the free list. This operation must be placed 1258 * under the protection of the lock. 1259 */ 1260 atomic_add_32(&tx_ring->tcb_free, tcb_num); 1261 1262 mutex_exit(&tx_ring->tcb_tail_lock); 1263 } 1264