1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _IGB_SW_H 30 #define _IGB_SW_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strsun.h> 42 #include <sys/strlog.h> 43 #include <sys/kmem.h> 44 #include <sys/stat.h> 45 #include <sys/kstat.h> 46 #include <sys/modctl.h> 47 #include <sys/errno.h> 48 #include <sys/dlpi.h> 49 #include <sys/mac_provider.h> 50 #include <sys/mac_ether.h> 51 #include <sys/vlan.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/pci.h> 55 #include <sys/pcie.h> 56 #include <sys/sdt.h> 57 #include <sys/ethernet.h> 58 #include <sys/pattr.h> 59 #include <sys/strsubr.h> 60 #include <sys/netlb.h> 61 #include <sys/random.h> 62 #include <inet/common.h> 63 #include <inet/tcp.h> 64 #include <inet/ip.h> 65 #include <inet/mi.h> 66 #include <inet/nd.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/fm/io/ddi.h> 71 #include "igb_api.h" 72 #include "igb_82575.h" 73 74 75 #define MODULE_NAME "igb" /* module name */ 76 77 #define IGB_SUCCESS DDI_SUCCESS 78 #define IGB_FAILURE DDI_FAILURE 79 80 #define IGB_UNKNOWN 0x00 81 #define IGB_INITIALIZED 0x01 82 #define IGB_STARTED 0x02 83 #define IGB_SUSPENDED 0x04 84 85 #define IGB_INTR_NONE 0 86 #define IGB_INTR_MSIX 1 87 #define IGB_INTR_MSI 2 88 #define IGB_INTR_LEGACY 3 89 90 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 91 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 92 93 #define IGB_NO_POLL -1 94 #define IGB_NO_FREE_SLOT -1 95 96 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 97 #define MCAST_ALLOC_COUNT 256 98 #define MAX_COOKIE 18 99 #define MIN_NUM_TX_DESC 2 100 101 /* 102 * Number of settings for interrupt throttle rate (ITR). There is one of 103 * these per msi-x vector and it needs to be the maximum of all silicon 104 * types supported by this driver. 105 */ 106 #define MAX_NUM_EITR 25 107 108 /* 109 * Maximum values for user configurable parameters 110 */ 111 #define MAX_TX_RING_SIZE 4096 112 #define MAX_RX_RING_SIZE 4096 113 #define MAX_RX_GROUP_NUM 4 114 115 #define MAX_MTU 9000 116 #define MAX_RX_LIMIT_PER_INTR 4096 117 #define MAX_RX_INTR_DELAY 65535 118 #define MAX_RX_INTR_ABS_DELAY 65535 119 #define MAX_TX_INTR_DELAY 65535 120 #define MAX_TX_INTR_ABS_DELAY 65535 121 122 #define MAX_RX_COPY_THRESHOLD 9216 123 #define MAX_TX_COPY_THRESHOLD 9216 124 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 125 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 126 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 127 #define MAX_MCAST_NUM 8192 128 129 /* 130 * Minimum values for user configurable parameters 131 */ 132 #define MIN_TX_RING_SIZE 64 133 #define MIN_RX_RING_SIZE 64 134 #define MIN_RX_GROUP_NUM 1 135 136 #define MIN_MTU ETHERMIN 137 #define MIN_RX_LIMIT_PER_INTR 16 138 #define MIN_RX_INTR_DELAY 0 139 #define MIN_RX_INTR_ABS_DELAY 0 140 #define MIN_TX_INTR_DELAY 0 141 #define MIN_TX_INTR_ABS_DELAY 0 142 #define MIN_RX_COPY_THRESHOLD 0 143 #define MIN_TX_COPY_THRESHOLD 0 144 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 145 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 146 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 147 #define MIN_MCAST_NUM 8 148 149 /* 150 * Default values for user configurable parameters 151 */ 152 #define DEFAULT_TX_RING_SIZE 512 153 #define DEFAULT_RX_RING_SIZE 512 154 #define DEFAULT_RX_GROUP_NUM 1 155 156 #define DEFAULT_MTU ETHERMTU 157 #define DEFAULT_RX_LIMIT_PER_INTR 256 158 #define DEFAULT_RX_INTR_DELAY 0 159 #define DEFAULT_RX_INTR_ABS_DELAY 0 160 #define DEFAULT_TX_INTR_DELAY 300 161 #define DEFAULT_TX_INTR_ABS_DELAY 0 162 #define DEFAULT_RX_COPY_THRESHOLD 128 163 #define DEFAULT_TX_COPY_THRESHOLD 512 164 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 165 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 166 #define DEFAULT_TX_RESCHED_THRESHOLD 128 167 #define DEFAULT_MCAST_NUM 4096 168 169 #define IGB_LSO_MAXLEN 65535 170 171 #define TX_DRAIN_TIME 200 172 #define RX_DRAIN_TIME 200 173 174 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 175 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 176 177 /* 178 * Defined for IP header alignment. 179 */ 180 #define IPHDR_ALIGN_ROOM 2 181 182 /* 183 * Bit flags for attach_progress 184 */ 185 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 186 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 187 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 188 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 189 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 190 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 191 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 192 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 193 #define ATTACH_PROGRESS_ALLOC_DMA 0x0100 /* DMA resources allocated */ 194 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 195 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 196 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 197 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 198 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 199 200 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 201 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 202 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 203 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 204 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 205 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 206 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 207 #define PROP_DEFAULT_MTU "default_mtu" 208 #define PROP_FLOW_CONTROL "flow_control" 209 #define PROP_TX_RING_SIZE "tx_ring_size" 210 #define PROP_RX_RING_SIZE "rx_ring_size" 211 #define PROP_MR_ENABLE "mr_enable" 212 #define PROP_RX_GROUP_NUM "rx_group_number" 213 214 #define PROP_INTR_FORCE "intr_force" 215 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 216 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 217 #define PROP_LSO_ENABLE "lso_enable" 218 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 219 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 220 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 221 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 222 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 223 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 224 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 225 #define PROP_INTR_THROTTLING "intr_throttling" 226 #define PROP_MCAST_MAX_NUM "mcast_max_num" 227 228 #define IGB_LB_NONE 0 229 #define IGB_LB_EXTERNAL 1 230 #define IGB_LB_INTERNAL_MAC 2 231 #define IGB_LB_INTERNAL_PHY 3 232 #define IGB_LB_INTERNAL_SERDES 4 233 234 /* 235 * Shorthand for the NDD parameters 236 */ 237 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 238 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 239 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 240 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 241 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 242 #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 243 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 244 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 245 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 246 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 247 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 248 249 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 250 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 251 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 252 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 253 #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 254 #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 255 #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 256 #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 257 #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 258 #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 259 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 260 261 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 262 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 263 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 264 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 265 #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 266 #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 267 #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 268 #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 269 #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 270 #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 271 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 272 273 enum ioc_reply { 274 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 275 IOC_DONE, /* OK, reply sent */ 276 IOC_ACK, /* OK, just send ACK */ 277 IOC_REPLY /* OK, just send reply */ 278 }; 279 280 /* 281 * For s/w context extraction from a tx frame 282 */ 283 #define TX_CXT_SUCCESS 0 284 #define TX_CXT_E_LSO_CSUM (-1) 285 #define TX_CXT_E_ETHER_TYPE (-2) 286 287 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 288 0, 0, (flag))) 289 290 /* 291 * Defined for ring index operations 292 * ASSERT(index < limit) 293 * ASSERT(step < limit) 294 * ASSERT(index1 < limit) 295 * ASSERT(index2 < limit) 296 */ 297 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 298 (index) + (step) : (index) + (step) - (limit)) 299 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 300 (index) - (step) : (index) + (limit) - (step)) 301 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 302 (index2) - (index1) : (index2) + (limit) - (index1)) 303 304 #define LINK_LIST_INIT(_LH) \ 305 (_LH)->head = (_LH)->tail = NULL 306 307 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 308 309 #define LIST_POP_HEAD(_LH) \ 310 (single_link_t *)(_LH)->head; \ 311 { \ 312 if ((_LH)->head != NULL) { \ 313 (_LH)->head = (_LH)->head->link; \ 314 if ((_LH)->head == NULL) \ 315 (_LH)->tail = NULL; \ 316 } \ 317 } 318 319 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 320 321 #define LIST_PUSH_TAIL(_LH, _E) \ 322 if ((_LH)->tail != NULL) { \ 323 (_LH)->tail->link = (single_link_t *)(_E); \ 324 (_LH)->tail = (single_link_t *)(_E); \ 325 } else { \ 326 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 327 } \ 328 (_E)->link = NULL; 329 330 #define LIST_GET_NEXT(_LH, _E) \ 331 (((_LH)->tail == (single_link_t *)(_E)) ? \ 332 NULL : ((single_link_t *)(_E))->link) 333 334 335 typedef struct single_link { 336 struct single_link *link; 337 } single_link_t; 338 339 typedef struct link_list { 340 single_link_t *head; 341 single_link_t *tail; 342 } link_list_t; 343 344 /* 345 * Property lookups 346 */ 347 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 348 DDI_PROP_DONTPASS, (n)) 349 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 350 DDI_PROP_DONTPASS, (n), -1) 351 352 353 /* capability/feature flags */ 354 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 355 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 356 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 357 358 /* function pointer for nic-specific functions */ 359 typedef void (*igb_nic_func_t)(struct igb *); 360 361 /* adapter-specific info for each supported device type */ 362 typedef struct adapter_info { 363 /* limits */ 364 uint32_t max_rx_que_num; /* maximum number of rx queues */ 365 uint32_t min_rx_que_num; /* minimum number of rx queues */ 366 uint32_t def_rx_que_num; /* default number of rx queues */ 367 uint32_t max_tx_que_num; /* maximum number of tx queues */ 368 uint32_t min_tx_que_num; /* minimum number of tx queues */ 369 uint32_t def_tx_que_num; /* default number of tx queues */ 370 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 371 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 372 uint32_t def_intr_throttle; /* default interrupt throttle */ 373 /* function pointers */ 374 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 375 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 376 /* capabilities */ 377 uint32_t flags; /* capability flags */ 378 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 379 } adapter_info_t; 380 381 /* 382 * Named Data (ND) Parameter Management Structure 383 */ 384 typedef struct { 385 struct igb *private; 386 uint32_t info; 387 uint32_t min; 388 uint32_t max; 389 uint32_t val; 390 char *name; 391 } nd_param_t; 392 393 /* 394 * NDD parameter indexes, divided into: 395 * 396 * read-only parameters describing the hardware's capabilities 397 * read-write parameters controlling the advertised capabilities 398 * read-only parameters describing the partner's capabilities 399 * read-write parameters controlling the force speed and duplex 400 * read-only parameters describing the link state 401 * read-only parameters describing the driver properties 402 * read-write parameters controlling the driver properties 403 */ 404 enum { 405 PARAM_AUTONEG_CAP, 406 PARAM_PAUSE_CAP, 407 PARAM_ASYM_PAUSE_CAP, 408 PARAM_1000FDX_CAP, 409 PARAM_1000HDX_CAP, 410 PARAM_100T4_CAP, 411 PARAM_100FDX_CAP, 412 PARAM_100HDX_CAP, 413 PARAM_10FDX_CAP, 414 PARAM_10HDX_CAP, 415 PARAM_REM_FAULT, 416 417 PARAM_ADV_AUTONEG_CAP, 418 PARAM_ADV_PAUSE_CAP, 419 PARAM_ADV_ASYM_PAUSE_CAP, 420 PARAM_ADV_1000FDX_CAP, 421 PARAM_ADV_1000HDX_CAP, 422 PARAM_ADV_100T4_CAP, 423 PARAM_ADV_100FDX_CAP, 424 PARAM_ADV_100HDX_CAP, 425 PARAM_ADV_10FDX_CAP, 426 PARAM_ADV_10HDX_CAP, 427 PARAM_ADV_REM_FAULT, 428 429 PARAM_LP_AUTONEG_CAP, 430 PARAM_LP_PAUSE_CAP, 431 PARAM_LP_ASYM_PAUSE_CAP, 432 PARAM_LP_1000FDX_CAP, 433 PARAM_LP_1000HDX_CAP, 434 PARAM_LP_100T4_CAP, 435 PARAM_LP_100FDX_CAP, 436 PARAM_LP_100HDX_CAP, 437 PARAM_LP_10FDX_CAP, 438 PARAM_LP_10HDX_CAP, 439 PARAM_LP_REM_FAULT, 440 441 PARAM_LINK_STATUS, 442 PARAM_LINK_SPEED, 443 PARAM_LINK_DUPLEX, 444 445 PARAM_COUNT 446 }; 447 448 typedef union igb_ether_addr { 449 struct { 450 uint32_t high; 451 uint32_t low; 452 } reg; 453 struct { 454 uint8_t set; 455 uint8_t group_index; 456 uint8_t addr[ETHERADDRL]; 457 } mac; 458 } igb_ether_addr_t; 459 460 typedef enum { 461 USE_NONE, 462 USE_COPY, 463 USE_DMA 464 } tx_type_t; 465 466 typedef enum { 467 RCB_FREE, 468 RCB_SENDUP 469 } rcb_state_t; 470 471 typedef struct tx_context { 472 uint32_t hcksum_flags; 473 uint32_t ip_hdr_len; 474 uint32_t mac_hdr_len; 475 uint32_t l4_proto; 476 uint32_t mss; 477 uint32_t l4_hdr_len; 478 boolean_t lso_flag; 479 } tx_context_t; 480 481 /* Hold address/length of each DMA segment */ 482 typedef struct sw_desc { 483 uint64_t address; 484 size_t length; 485 } sw_desc_t; 486 487 /* Handles and addresses of DMA buffer */ 488 typedef struct dma_buffer { 489 caddr_t address; /* Virtual address */ 490 uint64_t dma_address; /* DMA (Hardware) address */ 491 ddi_acc_handle_t acc_handle; /* Data access handle */ 492 ddi_dma_handle_t dma_handle; /* DMA handle */ 493 size_t size; /* Buffer size */ 494 size_t len; /* Data length in the buffer */ 495 } dma_buffer_t; 496 497 /* 498 * Tx Control Block 499 */ 500 typedef struct tx_control_block { 501 single_link_t link; 502 uint32_t frag_num; 503 uint32_t desc_num; 504 mblk_t *mp; 505 tx_type_t tx_type; 506 ddi_dma_handle_t tx_dma_handle; 507 dma_buffer_t tx_buf; 508 sw_desc_t desc[MAX_COOKIE]; 509 } tx_control_block_t; 510 511 /* 512 * RX Control Block 513 */ 514 typedef struct rx_control_block { 515 mblk_t *mp; 516 rcb_state_t state; 517 dma_buffer_t rx_buf; 518 frtn_t free_rtn; 519 struct igb_rx_ring *rx_ring; 520 } rx_control_block_t; 521 522 /* 523 * Software Data Structure for Tx Ring 524 */ 525 typedef struct igb_tx_ring { 526 uint32_t index; /* Ring index */ 527 uint32_t intr_vector; /* Interrupt vector index */ 528 529 /* 530 * Mutexes 531 */ 532 kmutex_t tx_lock; 533 kmutex_t recycle_lock; 534 kmutex_t tcb_head_lock; 535 kmutex_t tcb_tail_lock; 536 537 /* 538 * Tx descriptor ring definitions 539 */ 540 dma_buffer_t tbd_area; 541 union e1000_adv_tx_desc *tbd_ring; 542 uint32_t tbd_head; /* Index of next tbd to recycle */ 543 uint32_t tbd_tail; /* Index of next tbd to transmit */ 544 uint32_t tbd_free; /* Number of free tbd */ 545 546 /* 547 * Tx control block list definitions 548 */ 549 tx_control_block_t *tcb_area; 550 tx_control_block_t **work_list; 551 tx_control_block_t **free_list; 552 uint32_t tcb_head; /* Head index of free list */ 553 uint32_t tcb_tail; /* Tail index of free list */ 554 uint32_t tcb_free; /* Number of free tcb in free list */ 555 556 uint32_t *tbd_head_wb; /* Head write-back */ 557 uint32_t (*tx_recycle)(struct igb_tx_ring *); 558 559 /* 560 * s/w context structure for TCP/UDP checksum offload and LSO. 561 */ 562 tx_context_t tx_context; 563 564 /* 565 * Tx ring settings and status 566 */ 567 uint32_t ring_size; /* Tx descriptor ring size */ 568 uint32_t free_list_size; /* Tx free list size */ 569 uint32_t copy_thresh; 570 uint32_t recycle_thresh; 571 uint32_t overload_thresh; 572 uint32_t resched_thresh; 573 574 boolean_t reschedule; 575 uint32_t recycle_fail; 576 uint32_t stall_watchdog; 577 578 #ifdef IGB_DEBUG 579 /* 580 * Debug statistics 581 */ 582 uint32_t stat_overload; 583 uint32_t stat_fail_no_tbd; 584 uint32_t stat_fail_no_tcb; 585 uint32_t stat_fail_dma_bind; 586 uint32_t stat_reschedule; 587 uint32_t stat_pkt_cnt; 588 #endif 589 590 /* 591 * Pointer to the igb struct 592 */ 593 struct igb *igb; 594 mac_ring_handle_t ring_handle; /* call back ring handle */ 595 } igb_tx_ring_t; 596 597 /* 598 * Software Receive Ring 599 */ 600 typedef struct igb_rx_ring { 601 uint32_t index; /* Ring index */ 602 uint32_t intr_vector; /* Interrupt vector index */ 603 604 /* 605 * Mutexes 606 */ 607 kmutex_t rx_lock; /* Rx access lock */ 608 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 609 610 /* 611 * Rx descriptor ring definitions 612 */ 613 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 614 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 615 uint32_t rbd_next; /* Index of next rx desc */ 616 617 /* 618 * Rx control block list definitions 619 */ 620 rx_control_block_t *rcb_area; 621 rx_control_block_t **work_list; /* Work list of rcbs */ 622 rx_control_block_t **free_list; /* Free list of rcbs */ 623 uint32_t rcb_head; /* Index of next free rcb */ 624 uint32_t rcb_tail; /* Index to put recycled rcb */ 625 uint32_t rcb_free; /* Number of free rcbs */ 626 627 /* 628 * Rx ring settings and status 629 */ 630 uint32_t ring_size; /* Rx descriptor ring size */ 631 uint32_t free_list_size; /* Rx free list size */ 632 uint32_t limit_per_intr; /* Max packets per interrupt */ 633 uint32_t copy_thresh; 634 635 #ifdef IGB_DEBUG 636 /* 637 * Debug statistics 638 */ 639 uint32_t stat_frame_error; 640 uint32_t stat_cksum_error; 641 uint32_t stat_exceed_pkt; 642 uint32_t stat_pkt_cnt; 643 #endif 644 645 struct igb *igb; /* Pointer to igb struct */ 646 mac_ring_handle_t ring_handle; /* call back ring handle */ 647 uint32_t group_index; /* group index */ 648 uint64_t ring_gen_num; 649 } igb_rx_ring_t; 650 651 /* 652 * Software Receive Ring Group 653 */ 654 typedef struct igb_rx_group { 655 uint32_t index; /* Group index */ 656 mac_group_handle_t group_handle; /* call back group handle */ 657 struct igb *igb; /* Pointer to igb struct */ 658 } igb_rx_group_t; 659 660 typedef struct igb { 661 int instance; 662 mac_handle_t mac_hdl; 663 dev_info_t *dip; 664 struct e1000_hw hw; 665 struct igb_osdep osdep; 666 667 adapter_info_t *capab; /* adapter capabilities */ 668 669 uint32_t igb_state; 670 link_state_t link_state; 671 uint32_t link_speed; 672 uint32_t link_duplex; 673 uint32_t link_down_timeout; 674 675 uint32_t reset_count; 676 uint32_t attach_progress; 677 uint32_t loopback_mode; 678 uint32_t max_frame_size; 679 uint32_t dout_sync; 680 681 uint32_t mr_enable; /* Enable multiple rings */ 682 uint32_t vmdq_mode; /* Mode of VMDq */ 683 684 /* 685 * Receive Rings and Groups 686 */ 687 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 688 uint32_t num_rx_rings; /* Number of rx rings in use */ 689 uint32_t rx_ring_size; /* Rx descriptor ring size */ 690 uint32_t rx_buf_size; /* Rx buffer size */ 691 igb_rx_group_t *rx_groups; /* Array of rx groups */ 692 uint32_t num_rx_groups; /* Number of rx groups in use */ 693 694 /* 695 * Transmit Rings 696 */ 697 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 698 uint32_t num_tx_rings; /* Number of tx rings in use */ 699 uint32_t tx_ring_size; /* Tx descriptor ring size */ 700 uint32_t tx_buf_size; /* Tx buffer size */ 701 702 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 703 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 704 boolean_t lso_enable; /* Large Segment Offload */ 705 uint32_t tx_copy_thresh; /* Tx copy threshold */ 706 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 707 uint32_t tx_overload_thresh; /* Tx overload threshold */ 708 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 709 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 710 uint32_t rx_copy_thresh; /* Rx copy threshold */ 711 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 712 713 uint32_t intr_throttling[MAX_NUM_EITR]; 714 uint32_t intr_force; 715 716 int intr_type; 717 int intr_cnt; 718 int intr_cap; 719 size_t intr_size; 720 uint_t intr_pri; 721 ddi_intr_handle_t *htable; 722 uint32_t eims_mask; 723 uint32_t ims_mask; 724 725 kmutex_t gen_lock; /* General lock for device access */ 726 kmutex_t watchdog_lock; 727 728 boolean_t watchdog_enable; 729 boolean_t watchdog_start; 730 timeout_id_t watchdog_tid; 731 732 boolean_t unicst_init; 733 uint32_t unicst_avail; 734 uint32_t unicst_total; 735 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 736 uint32_t mcast_count; 737 uint32_t mcast_alloc_count; 738 uint32_t mcast_max_num; 739 struct ether_addr *mcast_table; 740 741 /* 742 * Kstat definitions 743 */ 744 kstat_t *igb_ks; 745 746 /* 747 * NDD definitions 748 */ 749 caddr_t nd_data; 750 nd_param_t nd_params[PARAM_COUNT]; 751 752 /* 753 * FMA capabilities 754 */ 755 int fm_capabilities; 756 757 ulong_t page_size; 758 } igb_t; 759 760 typedef struct igb_stat { 761 762 kstat_named_t link_speed; /* Link Speed */ 763 kstat_named_t reset_count; /* Reset Count */ 764 kstat_named_t dout_sync; /* DMA out of sync */ 765 #ifdef IGB_DEBUG 766 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 767 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 768 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 769 770 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 771 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 772 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 773 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 774 kstat_named_t tx_reschedule; /* Tx Reschedule */ 775 776 kstat_named_t gprc; /* Good Packets Received Count */ 777 kstat_named_t gptc; /* Good Packets Xmitted Count */ 778 kstat_named_t gor; /* Good Octets Received Count */ 779 kstat_named_t got; /* Good Octets Xmitd Count */ 780 kstat_named_t prc64; /* Packets Received - 64b */ 781 kstat_named_t prc127; /* Packets Received - 65-127b */ 782 kstat_named_t prc255; /* Packets Received - 127-255b */ 783 kstat_named_t prc511; /* Packets Received - 256-511b */ 784 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 785 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 786 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 787 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 788 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 789 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 790 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 791 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 792 #endif 793 kstat_named_t crcerrs; /* CRC Error Count */ 794 kstat_named_t symerrs; /* Symbol Error Count */ 795 kstat_named_t mpc; /* Missed Packet Count */ 796 kstat_named_t scc; /* Single Collision Count */ 797 kstat_named_t ecol; /* Excessive Collision Count */ 798 kstat_named_t mcc; /* Multiple Collision Count */ 799 kstat_named_t latecol; /* Late Collision Count */ 800 kstat_named_t colc; /* Collision Count */ 801 kstat_named_t dc; /* Defer Count */ 802 kstat_named_t sec; /* Sequence Error Count */ 803 kstat_named_t rlec; /* Receive Length Error Count */ 804 kstat_named_t xonrxc; /* XON Received Count */ 805 kstat_named_t xontxc; /* XON Xmitted Count */ 806 kstat_named_t xoffrxc; /* XOFF Received Count */ 807 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 808 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 809 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 810 kstat_named_t mprc; /* Multicast Pkts Received Count */ 811 kstat_named_t rnbc; /* Receive No Buffers Count */ 812 kstat_named_t ruc; /* Receive Undersize Count */ 813 kstat_named_t rfc; /* Receive Frag Count */ 814 kstat_named_t roc; /* Receive Oversize Count */ 815 kstat_named_t rjc; /* Receive Jabber Count */ 816 kstat_named_t tor; /* Total Octets Recvd Count */ 817 kstat_named_t tot; /* Total Octets Xmted Count */ 818 kstat_named_t tpr; /* Total Packets Received */ 819 kstat_named_t tpt; /* Total Packets Xmitted */ 820 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 821 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 822 kstat_named_t algnerrc; /* Alignment Error count */ 823 kstat_named_t rxerrc; /* Rx Error Count */ 824 kstat_named_t tncrs; /* Transmit with no CRS */ 825 kstat_named_t cexterr; /* Carrier Extension Error count */ 826 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 827 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 828 } igb_stat_t; 829 830 /* 831 * Function prototypes in e1000_osdep.c 832 */ 833 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 834 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 835 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 836 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 837 void e1000_rar_clear(struct e1000_hw *hw, uint32_t); 838 void e1000_rar_set_vmdq(struct e1000_hw *hw, const uint8_t *, uint32_t, 839 uint32_t, uint8_t); 840 841 /* 842 * Function prototypes in igb_buf.c 843 */ 844 int igb_alloc_dma(igb_t *); 845 void igb_free_dma(igb_t *); 846 847 /* 848 * Function prototypes in igb_main.c 849 */ 850 int igb_start(igb_t *); 851 void igb_stop(igb_t *); 852 int igb_setup_link(igb_t *, boolean_t); 853 int igb_unicst_find(igb_t *, const uint8_t *); 854 int igb_unicst_set(igb_t *, const uint8_t *, int); 855 int igb_multicst_add(igb_t *, const uint8_t *); 856 int igb_multicst_remove(igb_t *, const uint8_t *); 857 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 858 void igb_enable_watchdog_timer(igb_t *); 859 void igb_disable_watchdog_timer(igb_t *); 860 int igb_atomic_reserve(uint32_t *, uint32_t); 861 int igb_check_acc_handle(ddi_acc_handle_t); 862 int igb_check_dma_handle(ddi_dma_handle_t); 863 void igb_fm_ereport(igb_t *, char *); 864 void igb_set_fma_flags(int, int); 865 866 /* 867 * Function prototypes in igb_gld.c 868 */ 869 int igb_m_start(void *); 870 void igb_m_stop(void *); 871 int igb_m_promisc(void *, boolean_t); 872 int igb_m_multicst(void *, boolean_t, const uint8_t *); 873 int igb_m_unicst(void *, const uint8_t *); 874 int igb_m_stat(void *, uint_t, uint64_t *); 875 void igb_m_resources(void *); 876 void igb_m_ioctl(void *, queue_t *, mblk_t *); 877 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 878 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 879 mac_ring_info_t *, mac_ring_handle_t); 880 void igb_fill_group(void *arg, mac_ring_type_t, const int, 881 mac_group_info_t *, mac_group_handle_t); 882 int igb_rx_ring_intr_enable(mac_intr_handle_t); 883 int igb_rx_ring_intr_disable(mac_intr_handle_t); 884 885 /* 886 * Function prototypes in igb_rx.c 887 */ 888 mblk_t *igb_rx(igb_rx_ring_t *, int); 889 void igb_rx_recycle(caddr_t arg); 890 891 /* 892 * Function prototypes in igb_tx.c 893 */ 894 void igb_free_tcb(tx_control_block_t *); 895 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 896 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 897 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 898 899 /* 900 * Function prototypes in igb_log.c 901 */ 902 void igb_notice(void *, const char *, ...); 903 void igb_log(void *, const char *, ...); 904 void igb_error(void *, const char *, ...); 905 906 /* 907 * Function prototypes in igb_ndd.c 908 */ 909 int igb_nd_init(igb_t *); 910 void igb_nd_cleanup(igb_t *); 911 enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 912 913 /* 914 * Function prototypes in igb_stat.c 915 */ 916 int igb_init_stats(igb_t *); 917 918 mblk_t *igb_rx_ring_poll(void *, int); 919 mblk_t *igb_tx_ring_send(void *, mblk_t *); 920 921 #ifdef __cplusplus 922 } 923 #endif 924 925 #endif /* _IGB_SW_H */ 926