1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 */ 29 30 #ifndef _IGB_SW_H 31 #define _IGB_SW_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #include <sys/types.h> 38 #include <sys/conf.h> 39 #include <sys/debug.h> 40 #include <sys/stropts.h> 41 #include <sys/stream.h> 42 #include <sys/strsun.h> 43 #include <sys/strlog.h> 44 #include <sys/kmem.h> 45 #include <sys/stat.h> 46 #include <sys/kstat.h> 47 #include <sys/modctl.h> 48 #include <sys/errno.h> 49 #include <sys/dlpi.h> 50 #include <sys/mac_provider.h> 51 #include <sys/mac_ether.h> 52 #include <sys/vlan.h> 53 #include <sys/ddi.h> 54 #include <sys/sunddi.h> 55 #include <sys/pci.h> 56 #include <sys/pcie.h> 57 #include <sys/sdt.h> 58 #include <sys/ethernet.h> 59 #include <sys/pattr.h> 60 #include <sys/strsubr.h> 61 #include <sys/netlb.h> 62 #include <sys/random.h> 63 #include <inet/common.h> 64 #include <inet/tcp.h> 65 #include <inet/ip.h> 66 #include <inet/mi.h> 67 #include <inet/nd.h> 68 #include <sys/ddifm.h> 69 #include <sys/fm/protocol.h> 70 #include <sys/fm/util.h> 71 #include <sys/fm/io/ddi.h> 72 #include "igb_api.h" 73 #include "igb_82575.h" 74 75 76 #define MODULE_NAME "igb" /* module name */ 77 78 #define IGB_SUCCESS DDI_SUCCESS 79 #define IGB_FAILURE DDI_FAILURE 80 81 #define IGB_UNKNOWN 0x00 82 #define IGB_INITIALIZED 0x01 83 #define IGB_STARTED 0x02 84 #define IGB_SUSPENDED 0x04 85 #define IGB_STALL 0x08 86 #define IGB_ERROR 0x80 87 88 #define IGB_RX_STOPPED 0x1 89 90 #define IGB_INTR_NONE 0 91 #define IGB_INTR_MSIX 1 92 #define IGB_INTR_MSI 2 93 #define IGB_INTR_LEGACY 3 94 95 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 96 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 97 98 #define IGB_NO_POLL -1 99 #define IGB_NO_FREE_SLOT -1 100 101 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 102 #define MCAST_ALLOC_COUNT 256 103 #define MAX_COOKIE 18 104 #define MIN_NUM_TX_DESC 2 105 106 /* 107 * Number of settings for interrupt throttle rate (ITR). There is one of 108 * these per msi-x vector and it needs to be the maximum of all silicon 109 * types supported by this driver. 110 */ 111 #define MAX_NUM_EITR 25 112 113 /* 114 * Maximum values for user configurable parameters 115 */ 116 #define MAX_TX_RING_SIZE 4096 117 #define MAX_RX_RING_SIZE 4096 118 #define MAX_RX_GROUP_NUM 4 119 120 #define MAX_MTU 9000 121 #define MAX_RX_LIMIT_PER_INTR 4096 122 123 #define MAX_RX_COPY_THRESHOLD 9216 124 #define MAX_TX_COPY_THRESHOLD 9216 125 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 126 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 127 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 128 #define MAX_MCAST_NUM 8192 129 130 /* 131 * Minimum values for user configurable parameters 132 */ 133 #define MIN_TX_RING_SIZE 64 134 #define MIN_RX_RING_SIZE 64 135 #define MIN_RX_GROUP_NUM 1 136 137 #define MIN_MTU ETHERMIN 138 #define MIN_RX_LIMIT_PER_INTR 16 139 140 #define MIN_RX_COPY_THRESHOLD 0 141 #define MIN_TX_COPY_THRESHOLD 0 142 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 143 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 144 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 145 #define MIN_MCAST_NUM 8 146 147 /* 148 * Default values for user configurable parameters 149 */ 150 #define DEFAULT_TX_RING_SIZE 512 151 #define DEFAULT_RX_RING_SIZE 512 152 #define DEFAULT_RX_GROUP_NUM 1 153 154 #define DEFAULT_MTU ETHERMTU 155 #define DEFAULT_RX_LIMIT_PER_INTR 256 156 157 #define DEFAULT_RX_COPY_THRESHOLD 128 158 #define DEFAULT_TX_COPY_THRESHOLD 512 159 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 160 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 161 #define DEFAULT_TX_RESCHED_THRESHOLD 128 162 #define DEFAULT_MCAST_NUM 4096 163 164 #define IGB_LSO_MAXLEN 65535 165 166 #define TX_DRAIN_TIME 200 167 #define RX_DRAIN_TIME 200 168 169 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 170 171 /* 172 * Defined for IP header alignment. 173 */ 174 #define IPHDR_ALIGN_ROOM 2 175 176 /* 177 * Bit flags for attach_progress 178 */ 179 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 180 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 181 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 182 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 183 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 184 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 185 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 186 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 187 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 188 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 189 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 190 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 191 192 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 193 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 194 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 195 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 196 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 197 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 198 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 199 #define PROP_DEFAULT_MTU "default_mtu" 200 #define PROP_FLOW_CONTROL "flow_control" 201 #define PROP_TX_RING_SIZE "tx_ring_size" 202 #define PROP_RX_RING_SIZE "rx_ring_size" 203 #define PROP_MR_ENABLE "mr_enable" 204 #define PROP_RX_GROUP_NUM "rx_group_number" 205 206 #define PROP_INTR_FORCE "intr_force" 207 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 208 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 209 #define PROP_LSO_ENABLE "lso_enable" 210 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 211 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 212 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 213 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 214 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 215 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 216 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 217 #define PROP_INTR_THROTTLING "intr_throttling" 218 #define PROP_MCAST_MAX_NUM "mcast_max_num" 219 220 #define IGB_LB_NONE 0 221 #define IGB_LB_EXTERNAL 1 222 #define IGB_LB_INTERNAL_PHY 3 223 #define IGB_LB_INTERNAL_SERDES 4 224 225 enum ioc_reply { 226 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 227 IOC_DONE, /* OK, reply sent */ 228 IOC_ACK, /* OK, just send ACK */ 229 IOC_REPLY /* OK, just send reply */ 230 }; 231 232 /* 233 * For s/w context extraction from a tx frame 234 */ 235 #define TX_CXT_SUCCESS 0 236 #define TX_CXT_E_LSO_CSUM (-1) 237 #define TX_CXT_E_ETHER_TYPE (-2) 238 239 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 240 0, 0, (flag))) 241 242 /* 243 * Defined for ring index operations 244 * ASSERT(index < limit) 245 * ASSERT(step < limit) 246 * ASSERT(index1 < limit) 247 * ASSERT(index2 < limit) 248 */ 249 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 250 (index) + (step) : (index) + (step) - (limit)) 251 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 252 (index) - (step) : (index) + (limit) - (step)) 253 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 254 (index2) - (index1) : (index2) + (limit) - (index1)) 255 256 #define LINK_LIST_INIT(_LH) \ 257 (_LH)->head = (_LH)->tail = NULL 258 259 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 260 261 #define LIST_POP_HEAD(_LH) \ 262 (single_link_t *)(_LH)->head; \ 263 { \ 264 if ((_LH)->head != NULL) { \ 265 (_LH)->head = (_LH)->head->link; \ 266 if ((_LH)->head == NULL) \ 267 (_LH)->tail = NULL; \ 268 } \ 269 } 270 271 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 272 273 #define LIST_PUSH_TAIL(_LH, _E) \ 274 if ((_LH)->tail != NULL) { \ 275 (_LH)->tail->link = (single_link_t *)(_E); \ 276 (_LH)->tail = (single_link_t *)(_E); \ 277 } else { \ 278 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 279 } \ 280 (_E)->link = NULL; 281 282 #define LIST_GET_NEXT(_LH, _E) \ 283 (((_LH)->tail == (single_link_t *)(_E)) ? \ 284 NULL : ((single_link_t *)(_E))->link) 285 286 287 typedef struct single_link { 288 struct single_link *link; 289 } single_link_t; 290 291 typedef struct link_list { 292 single_link_t *head; 293 single_link_t *tail; 294 } link_list_t; 295 296 /* 297 * Property lookups 298 */ 299 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 300 DDI_PROP_DONTPASS, (n)) 301 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 302 DDI_PROP_DONTPASS, (n), -1) 303 304 305 /* capability/feature flags */ 306 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 307 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 308 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 309 310 /* function pointer for nic-specific functions */ 311 typedef void (*igb_nic_func_t)(struct igb *); 312 313 /* adapter-specific info for each supported device type */ 314 typedef struct adapter_info { 315 /* limits */ 316 uint32_t max_rx_que_num; /* maximum number of rx queues */ 317 uint32_t min_rx_que_num; /* minimum number of rx queues */ 318 uint32_t def_rx_que_num; /* default number of rx queues */ 319 uint32_t max_tx_que_num; /* maximum number of tx queues */ 320 uint32_t min_tx_que_num; /* minimum number of tx queues */ 321 uint32_t def_tx_que_num; /* default number of tx queues */ 322 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 323 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 324 uint32_t def_intr_throttle; /* default interrupt throttle */ 325 /* function pointers */ 326 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 327 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 328 /* capabilities */ 329 uint32_t flags; /* capability flags */ 330 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 331 } adapter_info_t; 332 333 typedef union igb_ether_addr { 334 struct { 335 uint32_t high; 336 uint32_t low; 337 } reg; 338 struct { 339 uint8_t set; 340 uint8_t group_index; 341 uint8_t addr[ETHERADDRL]; 342 } mac; 343 } igb_ether_addr_t; 344 345 typedef enum { 346 USE_NONE, 347 USE_COPY, 348 USE_DMA 349 } tx_type_t; 350 351 typedef struct tx_context { 352 uint32_t hcksum_flags; 353 uint32_t ip_hdr_len; 354 uint32_t mac_hdr_len; 355 uint32_t l4_proto; 356 uint32_t mss; 357 uint32_t l4_hdr_len; 358 boolean_t lso_flag; 359 } tx_context_t; 360 361 /* Hold address/length of each DMA segment */ 362 typedef struct sw_desc { 363 uint64_t address; 364 size_t length; 365 } sw_desc_t; 366 367 /* Handles and addresses of DMA buffer */ 368 typedef struct dma_buffer { 369 caddr_t address; /* Virtual address */ 370 uint64_t dma_address; /* DMA (Hardware) address */ 371 ddi_acc_handle_t acc_handle; /* Data access handle */ 372 ddi_dma_handle_t dma_handle; /* DMA handle */ 373 size_t size; /* Buffer size */ 374 size_t len; /* Data length in the buffer */ 375 } dma_buffer_t; 376 377 /* 378 * Tx Control Block 379 */ 380 typedef struct tx_control_block { 381 single_link_t link; 382 uint32_t frag_num; 383 uint32_t desc_num; 384 mblk_t *mp; 385 tx_type_t tx_type; 386 ddi_dma_handle_t tx_dma_handle; 387 dma_buffer_t tx_buf; 388 sw_desc_t desc[MAX_COOKIE]; 389 } tx_control_block_t; 390 391 /* 392 * RX Control Block 393 */ 394 typedef struct rx_control_block { 395 mblk_t *mp; 396 uint32_t ref_cnt; 397 dma_buffer_t rx_buf; 398 frtn_t free_rtn; 399 struct igb_rx_data *rx_data; 400 } rx_control_block_t; 401 402 /* 403 * Software Data Structure for Tx Ring 404 */ 405 typedef struct igb_tx_ring { 406 uint32_t index; /* Ring index */ 407 uint32_t intr_vector; /* Interrupt vector index */ 408 409 /* 410 * Mutexes 411 */ 412 kmutex_t tx_lock; 413 kmutex_t recycle_lock; 414 kmutex_t tcb_head_lock; 415 kmutex_t tcb_tail_lock; 416 417 /* 418 * Tx descriptor ring definitions 419 */ 420 dma_buffer_t tbd_area; 421 union e1000_adv_tx_desc *tbd_ring; 422 uint32_t tbd_head; /* Index of next tbd to recycle */ 423 uint32_t tbd_tail; /* Index of next tbd to transmit */ 424 uint32_t tbd_free; /* Number of free tbd */ 425 426 /* 427 * Tx control block list definitions 428 */ 429 tx_control_block_t *tcb_area; 430 tx_control_block_t **work_list; 431 tx_control_block_t **free_list; 432 uint32_t tcb_head; /* Head index of free list */ 433 uint32_t tcb_tail; /* Tail index of free list */ 434 uint32_t tcb_free; /* Number of free tcb in free list */ 435 436 uint32_t *tbd_head_wb; /* Head write-back */ 437 uint32_t (*tx_recycle)(struct igb_tx_ring *); 438 439 /* 440 * s/w context structure for TCP/UDP checksum offload and LSO. 441 */ 442 tx_context_t tx_context; 443 444 /* 445 * Tx ring settings and status 446 */ 447 uint32_t ring_size; /* Tx descriptor ring size */ 448 uint32_t free_list_size; /* Tx free list size */ 449 450 boolean_t reschedule; 451 uint32_t recycle_fail; 452 uint32_t stall_watchdog; 453 454 /* 455 * Per-ring statistics 456 */ 457 uint64_t tx_pkts; /* Packets Transmitted Count */ 458 uint64_t tx_bytes; /* Bytes Transmitted Count */ 459 460 #ifdef IGB_DEBUG 461 /* 462 * Debug statistics 463 */ 464 uint32_t stat_overload; 465 uint32_t stat_fail_no_tbd; 466 uint32_t stat_fail_no_tcb; 467 uint32_t stat_fail_dma_bind; 468 uint32_t stat_reschedule; 469 uint32_t stat_pkt_cnt; 470 #endif 471 472 /* 473 * Pointer to the igb struct 474 */ 475 struct igb *igb; 476 mac_ring_handle_t ring_handle; /* call back ring handle */ 477 } igb_tx_ring_t; 478 479 /* 480 * Software Receive Ring 481 */ 482 typedef struct igb_rx_data { 483 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 484 485 /* 486 * Rx descriptor ring definitions 487 */ 488 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 489 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 490 uint32_t rbd_next; /* Index of next rx desc */ 491 492 /* 493 * Rx control block list definitions 494 */ 495 rx_control_block_t *rcb_area; 496 rx_control_block_t **work_list; /* Work list of rcbs */ 497 rx_control_block_t **free_list; /* Free list of rcbs */ 498 uint32_t rcb_head; /* Index of next free rcb */ 499 uint32_t rcb_tail; /* Index to put recycled rcb */ 500 uint32_t rcb_free; /* Number of free rcbs */ 501 502 /* 503 * Rx sw ring settings and status 504 */ 505 uint32_t ring_size; /* Rx descriptor ring size */ 506 uint32_t free_list_size; /* Rx free list size */ 507 508 uint32_t rcb_pending; 509 uint32_t flag; 510 511 struct igb_rx_ring *rx_ring; /* Pointer to rx ring */ 512 } igb_rx_data_t; 513 514 /* 515 * Software Data Structure for Rx Ring 516 */ 517 typedef struct igb_rx_ring { 518 uint32_t index; /* Ring index */ 519 uint32_t intr_vector; /* Interrupt vector index */ 520 521 igb_rx_data_t *rx_data; /* Rx software ring */ 522 523 kmutex_t rx_lock; /* Rx access lock */ 524 525 /* 526 * Per-ring statistics 527 */ 528 uint64_t rx_pkts; /* Packets Received Count */ 529 uint64_t rx_bytes; /* Bytes Received Count */ 530 531 #ifdef IGB_DEBUG 532 /* 533 * Debug statistics 534 */ 535 uint32_t stat_frame_error; 536 uint32_t stat_cksum_error; 537 uint32_t stat_exceed_pkt; 538 uint32_t stat_pkt_cnt; 539 #endif 540 541 struct igb *igb; /* Pointer to igb struct */ 542 mac_ring_handle_t ring_handle; /* call back ring handle */ 543 uint32_t group_index; /* group index */ 544 uint64_t ring_gen_num; 545 } igb_rx_ring_t; 546 547 /* 548 * Software Receive Ring Group 549 */ 550 typedef struct igb_rx_group { 551 uint32_t index; /* Group index */ 552 mac_group_handle_t group_handle; /* call back group handle */ 553 struct igb *igb; /* Pointer to igb struct */ 554 } igb_rx_group_t; 555 556 typedef struct igb { 557 int instance; 558 mac_handle_t mac_hdl; 559 dev_info_t *dip; 560 struct e1000_hw hw; 561 struct igb_osdep osdep; 562 563 adapter_info_t *capab; /* adapter capabilities */ 564 565 uint32_t igb_state; 566 link_state_t link_state; 567 uint32_t link_speed; 568 uint32_t link_duplex; 569 boolean_t link_complete; 570 timeout_id_t link_tid; 571 572 uint32_t reset_count; 573 uint32_t attach_progress; 574 uint32_t loopback_mode; 575 uint32_t default_mtu; 576 uint32_t max_frame_size; 577 uint32_t dout_sync; 578 579 uint32_t rcb_pending; 580 581 uint32_t mr_enable; /* Enable multiple rings */ 582 uint32_t vmdq_mode; /* Mode of VMDq */ 583 584 /* 585 * Receive Rings and Groups 586 */ 587 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 588 uint32_t num_rx_rings; /* Number of rx rings in use */ 589 uint32_t rx_ring_size; /* Rx descriptor ring size */ 590 uint32_t rx_buf_size; /* Rx buffer size */ 591 igb_rx_group_t *rx_groups; /* Array of rx groups */ 592 uint32_t num_rx_groups; /* Number of rx groups in use */ 593 594 /* 595 * Transmit Rings 596 */ 597 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 598 uint32_t num_tx_rings; /* Number of tx rings in use */ 599 uint32_t tx_ring_size; /* Tx descriptor ring size */ 600 uint32_t tx_buf_size; /* Tx buffer size */ 601 602 boolean_t tx_ring_init; 603 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 604 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 605 boolean_t lso_enable; /* Large Segment Offload */ 606 uint32_t tx_copy_thresh; /* Tx copy threshold */ 607 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 608 uint32_t tx_overload_thresh; /* Tx overload threshold */ 609 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 610 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 611 uint32_t rx_copy_thresh; /* Rx copy threshold */ 612 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 613 614 uint32_t intr_throttling[MAX_NUM_EITR]; 615 uint32_t intr_force; 616 617 int intr_type; 618 int intr_cnt; 619 int intr_cap; 620 size_t intr_size; 621 uint_t intr_pri; 622 ddi_intr_handle_t *htable; 623 uint32_t eims_mask; 624 uint32_t ims_mask; 625 626 kmutex_t gen_lock; /* General lock for device access */ 627 kmutex_t watchdog_lock; 628 kmutex_t link_lock; 629 kmutex_t rx_pending_lock; 630 631 boolean_t watchdog_enable; 632 boolean_t watchdog_start; 633 timeout_id_t watchdog_tid; 634 635 boolean_t unicst_init; 636 uint32_t unicst_avail; 637 uint32_t unicst_total; 638 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 639 uint32_t mcast_count; 640 uint32_t mcast_alloc_count; 641 uint32_t mcast_max_num; 642 struct ether_addr *mcast_table; 643 644 /* 645 * Kstat definitions 646 */ 647 kstat_t *igb_ks; 648 649 uint32_t param_en_1000fdx_cap:1, 650 param_en_1000hdx_cap:1, 651 param_en_100t4_cap:1, 652 param_en_100fdx_cap:1, 653 param_en_100hdx_cap:1, 654 param_en_10fdx_cap:1, 655 param_en_10hdx_cap:1, 656 param_1000fdx_cap:1, 657 param_1000hdx_cap:1, 658 param_100t4_cap:1, 659 param_100fdx_cap:1, 660 param_100hdx_cap:1, 661 param_10fdx_cap:1, 662 param_10hdx_cap:1, 663 param_autoneg_cap:1, 664 param_pause_cap:1, 665 param_asym_pause_cap:1, 666 param_rem_fault:1, 667 param_adv_1000fdx_cap:1, 668 param_adv_1000hdx_cap:1, 669 param_adv_100t4_cap:1, 670 param_adv_100fdx_cap:1, 671 param_adv_100hdx_cap:1, 672 param_adv_10fdx_cap:1, 673 param_adv_10hdx_cap:1, 674 param_adv_autoneg_cap:1, 675 param_adv_pause_cap:1, 676 param_adv_asym_pause_cap:1, 677 param_adv_rem_fault:1, 678 param_lp_1000fdx_cap:1, 679 param_lp_1000hdx_cap:1, 680 param_lp_100t4_cap:1; 681 682 uint32_t param_lp_100fdx_cap:1, 683 param_lp_100hdx_cap:1, 684 param_lp_10fdx_cap:1, 685 param_lp_10hdx_cap:1, 686 param_lp_autoneg_cap:1, 687 param_lp_pause_cap:1, 688 param_lp_asym_pause_cap:1, 689 param_lp_rem_fault:1, 690 param_pad_to_32:24; 691 692 /* 693 * FMA capabilities 694 */ 695 int fm_capabilities; 696 697 ulong_t page_size; 698 } igb_t; 699 700 typedef struct igb_stat { 701 702 kstat_named_t link_speed; /* Link Speed */ 703 kstat_named_t reset_count; /* Reset Count */ 704 kstat_named_t dout_sync; /* DMA out of sync */ 705 #ifdef IGB_DEBUG 706 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 707 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 708 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 709 710 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 711 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 712 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 713 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 714 kstat_named_t tx_reschedule; /* Tx Reschedule */ 715 716 kstat_named_t gprc; /* Good Packets Received Count */ 717 kstat_named_t gptc; /* Good Packets Xmitted Count */ 718 kstat_named_t gor; /* Good Octets Received Count */ 719 kstat_named_t got; /* Good Octets Xmitd Count */ 720 kstat_named_t prc64; /* Packets Received - 64b */ 721 kstat_named_t prc127; /* Packets Received - 65-127b */ 722 kstat_named_t prc255; /* Packets Received - 127-255b */ 723 kstat_named_t prc511; /* Packets Received - 256-511b */ 724 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 725 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 726 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 727 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 728 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 729 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 730 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 731 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 732 #endif 733 kstat_named_t crcerrs; /* CRC Error Count */ 734 kstat_named_t symerrs; /* Symbol Error Count */ 735 kstat_named_t mpc; /* Missed Packet Count */ 736 kstat_named_t scc; /* Single Collision Count */ 737 kstat_named_t ecol; /* Excessive Collision Count */ 738 kstat_named_t mcc; /* Multiple Collision Count */ 739 kstat_named_t latecol; /* Late Collision Count */ 740 kstat_named_t colc; /* Collision Count */ 741 kstat_named_t dc; /* Defer Count */ 742 kstat_named_t sec; /* Sequence Error Count */ 743 kstat_named_t rlec; /* Receive Length Error Count */ 744 kstat_named_t xonrxc; /* XON Received Count */ 745 kstat_named_t xontxc; /* XON Xmitted Count */ 746 kstat_named_t xoffrxc; /* XOFF Received Count */ 747 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 748 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 749 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 750 kstat_named_t mprc; /* Multicast Pkts Received Count */ 751 kstat_named_t rnbc; /* Receive No Buffers Count */ 752 kstat_named_t ruc; /* Receive Undersize Count */ 753 kstat_named_t rfc; /* Receive Frag Count */ 754 kstat_named_t roc; /* Receive Oversize Count */ 755 kstat_named_t rjc; /* Receive Jabber Count */ 756 kstat_named_t tor; /* Total Octets Recvd Count */ 757 kstat_named_t tot; /* Total Octets Xmted Count */ 758 kstat_named_t tpr; /* Total Packets Received */ 759 kstat_named_t tpt; /* Total Packets Xmitted */ 760 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 761 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 762 kstat_named_t algnerrc; /* Alignment Error count */ 763 kstat_named_t rxerrc; /* Rx Error Count */ 764 kstat_named_t tncrs; /* Transmit with no CRS */ 765 kstat_named_t cexterr; /* Carrier Extension Error count */ 766 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 767 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 768 } igb_stat_t; 769 770 /* 771 * Function prototypes in e1000_osdep.c 772 */ 773 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 774 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 775 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 776 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 777 void e1000_rar_clear(struct e1000_hw *, uint32_t); 778 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 779 uint32_t, uint8_t); 780 781 /* 782 * Function prototypes in igb_buf.c 783 */ 784 int igb_alloc_dma(igb_t *); 785 void igb_free_dma(igb_t *); 786 void igb_free_dma_buffer(dma_buffer_t *); 787 int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring); 788 void igb_free_rx_ring_data(igb_rx_data_t *rx_data); 789 790 /* 791 * Function prototypes in igb_main.c 792 */ 793 int igb_start(igb_t *, boolean_t); 794 void igb_stop(igb_t *, boolean_t); 795 int igb_setup_link(igb_t *, boolean_t); 796 int igb_unicst_find(igb_t *, const uint8_t *); 797 int igb_unicst_set(igb_t *, const uint8_t *, int); 798 int igb_multicst_add(igb_t *, const uint8_t *); 799 int igb_multicst_remove(igb_t *, const uint8_t *); 800 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 801 void igb_enable_watchdog_timer(igb_t *); 802 void igb_disable_watchdog_timer(igb_t *); 803 int igb_atomic_reserve(uint32_t *, uint32_t); 804 int igb_check_acc_handle(ddi_acc_handle_t); 805 int igb_check_dma_handle(ddi_dma_handle_t); 806 void igb_fm_ereport(igb_t *, char *); 807 void igb_set_fma_flags(int); 808 809 /* 810 * Function prototypes in igb_gld.c 811 */ 812 int igb_m_start(void *); 813 void igb_m_stop(void *); 814 int igb_m_promisc(void *, boolean_t); 815 int igb_m_multicst(void *, boolean_t, const uint8_t *); 816 int igb_m_unicst(void *, const uint8_t *); 817 int igb_m_stat(void *, uint_t, uint64_t *); 818 void igb_m_resources(void *); 819 void igb_m_ioctl(void *, queue_t *, mblk_t *); 820 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 821 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 822 mac_ring_info_t *, mac_ring_handle_t); 823 int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 824 int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 825 void igb_m_propinfo(void *, const char *, mac_prop_id_t, 826 mac_prop_info_handle_t); 827 int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *); 828 int igb_get_priv_prop(igb_t *, const char *, uint_t, void *); 829 void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t); 830 boolean_t igb_param_locked(mac_prop_id_t); 831 void igb_fill_group(void *arg, mac_ring_type_t, const int, 832 mac_group_info_t *, mac_group_handle_t); 833 int igb_rx_ring_intr_enable(mac_intr_handle_t); 834 int igb_rx_ring_intr_disable(mac_intr_handle_t); 835 int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *); 836 837 /* 838 * Function prototypes in igb_rx.c 839 */ 840 mblk_t *igb_rx(igb_rx_ring_t *, int); 841 void igb_rx_recycle(caddr_t arg); 842 843 /* 844 * Function prototypes in igb_tx.c 845 */ 846 void igb_free_tcb(tx_control_block_t *); 847 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 848 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 849 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 850 851 /* 852 * Function prototypes in igb_log.c 853 */ 854 void igb_notice(void *, const char *, ...); 855 void igb_log(void *, const char *, ...); 856 void igb_error(void *, const char *, ...); 857 858 /* 859 * Function prototypes in igb_stat.c 860 */ 861 int igb_init_stats(igb_t *); 862 863 mblk_t *igb_rx_ring_poll(void *, int); 864 mblk_t *igb_tx_ring_send(void *, mblk_t *); 865 int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 866 int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 867 868 #ifdef __cplusplus 869 } 870 #endif 871 872 #endif /* _IGB_SW_H */ 873