1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #ifndef _IGB_SW_H 29 #define _IGB_SW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/dlpi.h> 48 #include <sys/mac_provider.h> 49 #include <sys/mac_ether.h> 50 #include <sys/vlan.h> 51 #include <sys/ddi.h> 52 #include <sys/sunddi.h> 53 #include <sys/pci.h> 54 #include <sys/pcie.h> 55 #include <sys/sdt.h> 56 #include <sys/ethernet.h> 57 #include <sys/pattr.h> 58 #include <sys/strsubr.h> 59 #include <sys/netlb.h> 60 #include <sys/random.h> 61 #include <inet/common.h> 62 #include <inet/tcp.h> 63 #include <inet/ip.h> 64 #include <inet/mi.h> 65 #include <inet/nd.h> 66 #include <sys/ddifm.h> 67 #include <sys/fm/protocol.h> 68 #include <sys/fm/util.h> 69 #include <sys/fm/io/ddi.h> 70 #include "igb_api.h" 71 #include "igb_82575.h" 72 73 74 #define MODULE_NAME "igb" /* module name */ 75 76 #define IGB_SUCCESS DDI_SUCCESS 77 #define IGB_FAILURE DDI_FAILURE 78 79 #define IGB_UNKNOWN 0x00 80 #define IGB_INITIALIZED 0x01 81 #define IGB_STARTED 0x02 82 #define IGB_SUSPENDED 0x04 83 #define IGB_STALL 0x08 84 #define IGB_ERROR 0x80 85 86 #define IGB_RX_STOPPED 0x1 87 88 #define IGB_INTR_NONE 0 89 #define IGB_INTR_MSIX 1 90 #define IGB_INTR_MSI 2 91 #define IGB_INTR_LEGACY 3 92 93 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 94 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 95 96 #define IGB_NO_POLL -1 97 #define IGB_NO_FREE_SLOT -1 98 99 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 100 #define MCAST_ALLOC_COUNT 256 101 #define MAX_COOKIE 18 102 #define MIN_NUM_TX_DESC 2 103 104 /* 105 * Number of settings for interrupt throttle rate (ITR). There is one of 106 * these per msi-x vector and it needs to be the maximum of all silicon 107 * types supported by this driver. 108 */ 109 #define MAX_NUM_EITR 25 110 111 /* 112 * Maximum values for user configurable parameters 113 */ 114 #define MAX_TX_RING_SIZE 4096 115 #define MAX_RX_RING_SIZE 4096 116 #define MAX_RX_GROUP_NUM 4 117 118 #define MAX_MTU 9000 119 #define MAX_RX_LIMIT_PER_INTR 4096 120 121 #define MAX_RX_COPY_THRESHOLD 9216 122 #define MAX_TX_COPY_THRESHOLD 9216 123 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 124 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 125 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 126 #define MAX_MCAST_NUM 8192 127 128 /* 129 * Minimum values for user configurable parameters 130 */ 131 #define MIN_TX_RING_SIZE 64 132 #define MIN_RX_RING_SIZE 64 133 #define MIN_RX_GROUP_NUM 1 134 135 #define MIN_MTU ETHERMIN 136 #define MIN_RX_LIMIT_PER_INTR 16 137 138 #define MIN_RX_COPY_THRESHOLD 0 139 #define MIN_TX_COPY_THRESHOLD 0 140 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 141 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 142 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 143 #define MIN_MCAST_NUM 8 144 145 /* 146 * Default values for user configurable parameters 147 */ 148 #define DEFAULT_TX_RING_SIZE 512 149 #define DEFAULT_RX_RING_SIZE 512 150 #define DEFAULT_RX_GROUP_NUM 1 151 152 #define DEFAULT_MTU ETHERMTU 153 #define DEFAULT_RX_LIMIT_PER_INTR 256 154 155 #define DEFAULT_RX_COPY_THRESHOLD 128 156 #define DEFAULT_TX_COPY_THRESHOLD 512 157 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 158 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 159 #define DEFAULT_TX_RESCHED_THRESHOLD 128 160 #define DEFAULT_MCAST_NUM 4096 161 162 #define IGB_LSO_MAXLEN 65535 163 164 #define TX_DRAIN_TIME 200 165 #define RX_DRAIN_TIME 200 166 167 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 168 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 169 170 /* 171 * Defined for IP header alignment. 172 */ 173 #define IPHDR_ALIGN_ROOM 2 174 175 /* 176 * Bit flags for attach_progress 177 */ 178 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 179 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 180 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 181 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 182 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 183 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 184 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 185 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 186 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 187 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 188 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 189 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 190 191 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 192 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 193 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 194 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 195 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 196 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 197 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 198 #define PROP_DEFAULT_MTU "default_mtu" 199 #define PROP_FLOW_CONTROL "flow_control" 200 #define PROP_TX_RING_SIZE "tx_ring_size" 201 #define PROP_RX_RING_SIZE "rx_ring_size" 202 #define PROP_MR_ENABLE "mr_enable" 203 #define PROP_RX_GROUP_NUM "rx_group_number" 204 205 #define PROP_INTR_FORCE "intr_force" 206 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 207 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 208 #define PROP_LSO_ENABLE "lso_enable" 209 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 210 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 211 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 212 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 213 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 214 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 215 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 216 #define PROP_INTR_THROTTLING "intr_throttling" 217 #define PROP_MCAST_MAX_NUM "mcast_max_num" 218 219 #define IGB_LB_NONE 0 220 #define IGB_LB_EXTERNAL 1 221 #define IGB_LB_INTERNAL_PHY 3 222 #define IGB_LB_INTERNAL_SERDES 4 223 224 enum ioc_reply { 225 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 226 IOC_DONE, /* OK, reply sent */ 227 IOC_ACK, /* OK, just send ACK */ 228 IOC_REPLY /* OK, just send reply */ 229 }; 230 231 /* 232 * For s/w context extraction from a tx frame 233 */ 234 #define TX_CXT_SUCCESS 0 235 #define TX_CXT_E_LSO_CSUM (-1) 236 #define TX_CXT_E_ETHER_TYPE (-2) 237 238 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 239 0, 0, (flag))) 240 241 /* 242 * Defined for ring index operations 243 * ASSERT(index < limit) 244 * ASSERT(step < limit) 245 * ASSERT(index1 < limit) 246 * ASSERT(index2 < limit) 247 */ 248 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 249 (index) + (step) : (index) + (step) - (limit)) 250 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 251 (index) - (step) : (index) + (limit) - (step)) 252 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 253 (index2) - (index1) : (index2) + (limit) - (index1)) 254 255 #define LINK_LIST_INIT(_LH) \ 256 (_LH)->head = (_LH)->tail = NULL 257 258 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 259 260 #define LIST_POP_HEAD(_LH) \ 261 (single_link_t *)(_LH)->head; \ 262 { \ 263 if ((_LH)->head != NULL) { \ 264 (_LH)->head = (_LH)->head->link; \ 265 if ((_LH)->head == NULL) \ 266 (_LH)->tail = NULL; \ 267 } \ 268 } 269 270 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 271 272 #define LIST_PUSH_TAIL(_LH, _E) \ 273 if ((_LH)->tail != NULL) { \ 274 (_LH)->tail->link = (single_link_t *)(_E); \ 275 (_LH)->tail = (single_link_t *)(_E); \ 276 } else { \ 277 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 278 } \ 279 (_E)->link = NULL; 280 281 #define LIST_GET_NEXT(_LH, _E) \ 282 (((_LH)->tail == (single_link_t *)(_E)) ? \ 283 NULL : ((single_link_t *)(_E))->link) 284 285 286 typedef struct single_link { 287 struct single_link *link; 288 } single_link_t; 289 290 typedef struct link_list { 291 single_link_t *head; 292 single_link_t *tail; 293 } link_list_t; 294 295 /* 296 * Property lookups 297 */ 298 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 299 DDI_PROP_DONTPASS, (n)) 300 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 301 DDI_PROP_DONTPASS, (n), -1) 302 303 304 /* capability/feature flags */ 305 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 306 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 307 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 308 309 /* function pointer for nic-specific functions */ 310 typedef void (*igb_nic_func_t)(struct igb *); 311 312 /* adapter-specific info for each supported device type */ 313 typedef struct adapter_info { 314 /* limits */ 315 uint32_t max_rx_que_num; /* maximum number of rx queues */ 316 uint32_t min_rx_que_num; /* minimum number of rx queues */ 317 uint32_t def_rx_que_num; /* default number of rx queues */ 318 uint32_t max_tx_que_num; /* maximum number of tx queues */ 319 uint32_t min_tx_que_num; /* minimum number of tx queues */ 320 uint32_t def_tx_que_num; /* default number of tx queues */ 321 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 322 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 323 uint32_t def_intr_throttle; /* default interrupt throttle */ 324 /* function pointers */ 325 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 326 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 327 /* capabilities */ 328 uint32_t flags; /* capability flags */ 329 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 330 } adapter_info_t; 331 332 typedef union igb_ether_addr { 333 struct { 334 uint32_t high; 335 uint32_t low; 336 } reg; 337 struct { 338 uint8_t set; 339 uint8_t group_index; 340 uint8_t addr[ETHERADDRL]; 341 } mac; 342 } igb_ether_addr_t; 343 344 typedef enum { 345 USE_NONE, 346 USE_COPY, 347 USE_DMA 348 } tx_type_t; 349 350 typedef struct tx_context { 351 uint32_t hcksum_flags; 352 uint32_t ip_hdr_len; 353 uint32_t mac_hdr_len; 354 uint32_t l4_proto; 355 uint32_t mss; 356 uint32_t l4_hdr_len; 357 boolean_t lso_flag; 358 } tx_context_t; 359 360 /* Hold address/length of each DMA segment */ 361 typedef struct sw_desc { 362 uint64_t address; 363 size_t length; 364 } sw_desc_t; 365 366 /* Handles and addresses of DMA buffer */ 367 typedef struct dma_buffer { 368 caddr_t address; /* Virtual address */ 369 uint64_t dma_address; /* DMA (Hardware) address */ 370 ddi_acc_handle_t acc_handle; /* Data access handle */ 371 ddi_dma_handle_t dma_handle; /* DMA handle */ 372 size_t size; /* Buffer size */ 373 size_t len; /* Data length in the buffer */ 374 } dma_buffer_t; 375 376 /* 377 * Tx Control Block 378 */ 379 typedef struct tx_control_block { 380 single_link_t link; 381 uint32_t frag_num; 382 uint32_t desc_num; 383 mblk_t *mp; 384 tx_type_t tx_type; 385 ddi_dma_handle_t tx_dma_handle; 386 dma_buffer_t tx_buf; 387 sw_desc_t desc[MAX_COOKIE]; 388 } tx_control_block_t; 389 390 /* 391 * RX Control Block 392 */ 393 typedef struct rx_control_block { 394 mblk_t *mp; 395 uint32_t ref_cnt; 396 dma_buffer_t rx_buf; 397 frtn_t free_rtn; 398 struct igb_rx_data *rx_data; 399 } rx_control_block_t; 400 401 /* 402 * Software Data Structure for Tx Ring 403 */ 404 typedef struct igb_tx_ring { 405 uint32_t index; /* Ring index */ 406 uint32_t intr_vector; /* Interrupt vector index */ 407 408 /* 409 * Mutexes 410 */ 411 kmutex_t tx_lock; 412 kmutex_t recycle_lock; 413 kmutex_t tcb_head_lock; 414 kmutex_t tcb_tail_lock; 415 416 /* 417 * Tx descriptor ring definitions 418 */ 419 dma_buffer_t tbd_area; 420 union e1000_adv_tx_desc *tbd_ring; 421 uint32_t tbd_head; /* Index of next tbd to recycle */ 422 uint32_t tbd_tail; /* Index of next tbd to transmit */ 423 uint32_t tbd_free; /* Number of free tbd */ 424 425 /* 426 * Tx control block list definitions 427 */ 428 tx_control_block_t *tcb_area; 429 tx_control_block_t **work_list; 430 tx_control_block_t **free_list; 431 uint32_t tcb_head; /* Head index of free list */ 432 uint32_t tcb_tail; /* Tail index of free list */ 433 uint32_t tcb_free; /* Number of free tcb in free list */ 434 435 uint32_t *tbd_head_wb; /* Head write-back */ 436 uint32_t (*tx_recycle)(struct igb_tx_ring *); 437 438 /* 439 * s/w context structure for TCP/UDP checksum offload and LSO. 440 */ 441 tx_context_t tx_context; 442 443 /* 444 * Tx ring settings and status 445 */ 446 uint32_t ring_size; /* Tx descriptor ring size */ 447 uint32_t free_list_size; /* Tx free list size */ 448 449 boolean_t reschedule; 450 uint32_t recycle_fail; 451 uint32_t stall_watchdog; 452 453 /* 454 * Per-ring statistics 455 */ 456 uint64_t tx_pkts; /* Packets Transmitted Count */ 457 uint64_t tx_bytes; /* Bytes Transmitted Count */ 458 459 #ifdef IGB_DEBUG 460 /* 461 * Debug statistics 462 */ 463 uint32_t stat_overload; 464 uint32_t stat_fail_no_tbd; 465 uint32_t stat_fail_no_tcb; 466 uint32_t stat_fail_dma_bind; 467 uint32_t stat_reschedule; 468 uint32_t stat_pkt_cnt; 469 #endif 470 471 /* 472 * Pointer to the igb struct 473 */ 474 struct igb *igb; 475 mac_ring_handle_t ring_handle; /* call back ring handle */ 476 } igb_tx_ring_t; 477 478 /* 479 * Software Receive Ring 480 */ 481 typedef struct igb_rx_data { 482 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 483 484 /* 485 * Rx descriptor ring definitions 486 */ 487 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 488 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 489 uint32_t rbd_next; /* Index of next rx desc */ 490 491 /* 492 * Rx control block list definitions 493 */ 494 rx_control_block_t *rcb_area; 495 rx_control_block_t **work_list; /* Work list of rcbs */ 496 rx_control_block_t **free_list; /* Free list of rcbs */ 497 uint32_t rcb_head; /* Index of next free rcb */ 498 uint32_t rcb_tail; /* Index to put recycled rcb */ 499 uint32_t rcb_free; /* Number of free rcbs */ 500 501 /* 502 * Rx sw ring settings and status 503 */ 504 uint32_t ring_size; /* Rx descriptor ring size */ 505 uint32_t free_list_size; /* Rx free list size */ 506 507 uint32_t rcb_pending; 508 uint32_t flag; 509 510 struct igb_rx_ring *rx_ring; /* Pointer to rx ring */ 511 } igb_rx_data_t; 512 513 /* 514 * Software Data Structure for Rx Ring 515 */ 516 typedef struct igb_rx_ring { 517 uint32_t index; /* Ring index */ 518 uint32_t intr_vector; /* Interrupt vector index */ 519 520 igb_rx_data_t *rx_data; /* Rx software ring */ 521 522 kmutex_t rx_lock; /* Rx access lock */ 523 524 /* 525 * Per-ring statistics 526 */ 527 uint64_t rx_pkts; /* Packets Received Count */ 528 uint64_t rx_bytes; /* Bytes Received Count */ 529 530 #ifdef IGB_DEBUG 531 /* 532 * Debug statistics 533 */ 534 uint32_t stat_frame_error; 535 uint32_t stat_cksum_error; 536 uint32_t stat_exceed_pkt; 537 uint32_t stat_pkt_cnt; 538 #endif 539 540 struct igb *igb; /* Pointer to igb struct */ 541 mac_ring_handle_t ring_handle; /* call back ring handle */ 542 uint32_t group_index; /* group index */ 543 uint64_t ring_gen_num; 544 } igb_rx_ring_t; 545 546 /* 547 * Software Receive Ring Group 548 */ 549 typedef struct igb_rx_group { 550 uint32_t index; /* Group index */ 551 mac_group_handle_t group_handle; /* call back group handle */ 552 struct igb *igb; /* Pointer to igb struct */ 553 } igb_rx_group_t; 554 555 typedef struct igb { 556 int instance; 557 mac_handle_t mac_hdl; 558 dev_info_t *dip; 559 struct e1000_hw hw; 560 struct igb_osdep osdep; 561 562 adapter_info_t *capab; /* adapter capabilities */ 563 564 uint32_t igb_state; 565 link_state_t link_state; 566 uint32_t link_speed; 567 uint32_t link_duplex; 568 uint32_t link_down_timeout; 569 boolean_t link_complete; 570 timeout_id_t link_tid; 571 572 uint32_t reset_count; 573 uint32_t attach_progress; 574 uint32_t loopback_mode; 575 uint32_t default_mtu; 576 uint32_t max_frame_size; 577 uint32_t dout_sync; 578 579 uint32_t rcb_pending; 580 581 uint32_t mr_enable; /* Enable multiple rings */ 582 uint32_t vmdq_mode; /* Mode of VMDq */ 583 584 /* 585 * Receive Rings and Groups 586 */ 587 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 588 uint32_t num_rx_rings; /* Number of rx rings in use */ 589 uint32_t rx_ring_size; /* Rx descriptor ring size */ 590 uint32_t rx_buf_size; /* Rx buffer size */ 591 igb_rx_group_t *rx_groups; /* Array of rx groups */ 592 uint32_t num_rx_groups; /* Number of rx groups in use */ 593 594 /* 595 * Transmit Rings 596 */ 597 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 598 uint32_t num_tx_rings; /* Number of tx rings in use */ 599 uint32_t tx_ring_size; /* Tx descriptor ring size */ 600 uint32_t tx_buf_size; /* Tx buffer size */ 601 602 boolean_t tx_ring_init; 603 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 604 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 605 boolean_t lso_enable; /* Large Segment Offload */ 606 uint32_t tx_copy_thresh; /* Tx copy threshold */ 607 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 608 uint32_t tx_overload_thresh; /* Tx overload threshold */ 609 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 610 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 611 uint32_t rx_copy_thresh; /* Rx copy threshold */ 612 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 613 614 uint32_t intr_throttling[MAX_NUM_EITR]; 615 uint32_t intr_force; 616 617 int intr_type; 618 int intr_cnt; 619 int intr_cap; 620 size_t intr_size; 621 uint_t intr_pri; 622 ddi_intr_handle_t *htable; 623 uint32_t eims_mask; 624 uint32_t ims_mask; 625 626 kmutex_t gen_lock; /* General lock for device access */ 627 kmutex_t watchdog_lock; 628 kmutex_t link_lock; 629 kmutex_t rx_pending_lock; 630 631 boolean_t watchdog_enable; 632 boolean_t watchdog_start; 633 timeout_id_t watchdog_tid; 634 635 boolean_t unicst_init; 636 uint32_t unicst_avail; 637 uint32_t unicst_total; 638 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 639 uint32_t mcast_count; 640 uint32_t mcast_alloc_count; 641 uint32_t mcast_max_num; 642 struct ether_addr *mcast_table; 643 644 /* 645 * Kstat definitions 646 */ 647 kstat_t *igb_ks; 648 649 uint32_t param_en_1000fdx_cap:1, 650 param_en_1000hdx_cap:1, 651 param_en_100t4_cap:1, 652 param_en_100fdx_cap:1, 653 param_en_100hdx_cap:1, 654 param_en_10fdx_cap:1, 655 param_en_10hdx_cap:1, 656 param_1000fdx_cap:1, 657 param_1000hdx_cap:1, 658 param_100t4_cap:1, 659 param_100fdx_cap:1, 660 param_100hdx_cap:1, 661 param_10fdx_cap:1, 662 param_10hdx_cap:1, 663 param_autoneg_cap:1, 664 param_pause_cap:1, 665 param_asym_pause_cap:1, 666 param_rem_fault:1, 667 param_adv_1000fdx_cap:1, 668 param_adv_1000hdx_cap:1, 669 param_adv_100t4_cap:1, 670 param_adv_100fdx_cap:1, 671 param_adv_100hdx_cap:1, 672 param_adv_10fdx_cap:1, 673 param_adv_10hdx_cap:1, 674 param_adv_autoneg_cap:1, 675 param_adv_pause_cap:1, 676 param_adv_asym_pause_cap:1, 677 param_adv_rem_fault:1, 678 param_lp_1000fdx_cap:1, 679 param_lp_1000hdx_cap:1, 680 param_lp_100t4_cap:1; 681 682 uint32_t param_lp_100fdx_cap:1, 683 param_lp_100hdx_cap:1, 684 param_lp_10fdx_cap:1, 685 param_lp_10hdx_cap:1, 686 param_lp_autoneg_cap:1, 687 param_lp_pause_cap:1, 688 param_lp_asym_pause_cap:1, 689 param_lp_rem_fault:1, 690 param_pad_to_32:24; 691 692 /* 693 * FMA capabilities 694 */ 695 int fm_capabilities; 696 697 ulong_t page_size; 698 } igb_t; 699 700 typedef struct igb_stat { 701 702 kstat_named_t link_speed; /* Link Speed */ 703 kstat_named_t reset_count; /* Reset Count */ 704 kstat_named_t dout_sync; /* DMA out of sync */ 705 #ifdef IGB_DEBUG 706 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 707 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 708 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 709 710 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 711 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 712 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 713 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 714 kstat_named_t tx_reschedule; /* Tx Reschedule */ 715 716 kstat_named_t gprc; /* Good Packets Received Count */ 717 kstat_named_t gptc; /* Good Packets Xmitted Count */ 718 kstat_named_t gor; /* Good Octets Received Count */ 719 kstat_named_t got; /* Good Octets Xmitd Count */ 720 kstat_named_t prc64; /* Packets Received - 64b */ 721 kstat_named_t prc127; /* Packets Received - 65-127b */ 722 kstat_named_t prc255; /* Packets Received - 127-255b */ 723 kstat_named_t prc511; /* Packets Received - 256-511b */ 724 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 725 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 726 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 727 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 728 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 729 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 730 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 731 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 732 #endif 733 kstat_named_t crcerrs; /* CRC Error Count */ 734 kstat_named_t symerrs; /* Symbol Error Count */ 735 kstat_named_t mpc; /* Missed Packet Count */ 736 kstat_named_t scc; /* Single Collision Count */ 737 kstat_named_t ecol; /* Excessive Collision Count */ 738 kstat_named_t mcc; /* Multiple Collision Count */ 739 kstat_named_t latecol; /* Late Collision Count */ 740 kstat_named_t colc; /* Collision Count */ 741 kstat_named_t dc; /* Defer Count */ 742 kstat_named_t sec; /* Sequence Error Count */ 743 kstat_named_t rlec; /* Receive Length Error Count */ 744 kstat_named_t xonrxc; /* XON Received Count */ 745 kstat_named_t xontxc; /* XON Xmitted Count */ 746 kstat_named_t xoffrxc; /* XOFF Received Count */ 747 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 748 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 749 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 750 kstat_named_t mprc; /* Multicast Pkts Received Count */ 751 kstat_named_t rnbc; /* Receive No Buffers Count */ 752 kstat_named_t ruc; /* Receive Undersize Count */ 753 kstat_named_t rfc; /* Receive Frag Count */ 754 kstat_named_t roc; /* Receive Oversize Count */ 755 kstat_named_t rjc; /* Receive Jabber Count */ 756 kstat_named_t tor; /* Total Octets Recvd Count */ 757 kstat_named_t tot; /* Total Octets Xmted Count */ 758 kstat_named_t tpr; /* Total Packets Received */ 759 kstat_named_t tpt; /* Total Packets Xmitted */ 760 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 761 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 762 kstat_named_t algnerrc; /* Alignment Error count */ 763 kstat_named_t rxerrc; /* Rx Error Count */ 764 kstat_named_t tncrs; /* Transmit with no CRS */ 765 kstat_named_t cexterr; /* Carrier Extension Error count */ 766 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 767 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 768 } igb_stat_t; 769 770 /* 771 * Function prototypes in e1000_osdep.c 772 */ 773 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 774 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 775 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 776 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 777 void e1000_rar_clear(struct e1000_hw *, uint32_t); 778 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 779 uint32_t, uint8_t); 780 781 /* 782 * Function prototypes in igb_buf.c 783 */ 784 int igb_alloc_dma(igb_t *); 785 void igb_free_dma(igb_t *); 786 void igb_free_dma_buffer(dma_buffer_t *); 787 int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring); 788 void igb_free_rx_ring_data(igb_rx_data_t *rx_data); 789 790 /* 791 * Function prototypes in igb_main.c 792 */ 793 int igb_start(igb_t *, boolean_t); 794 void igb_stop(igb_t *, boolean_t); 795 int igb_setup_link(igb_t *, boolean_t); 796 int igb_unicst_find(igb_t *, const uint8_t *); 797 int igb_unicst_set(igb_t *, const uint8_t *, int); 798 int igb_multicst_add(igb_t *, const uint8_t *); 799 int igb_multicst_remove(igb_t *, const uint8_t *); 800 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 801 void igb_enable_watchdog_timer(igb_t *); 802 void igb_disable_watchdog_timer(igb_t *); 803 int igb_atomic_reserve(uint32_t *, uint32_t); 804 int igb_check_acc_handle(ddi_acc_handle_t); 805 int igb_check_dma_handle(ddi_dma_handle_t); 806 void igb_fm_ereport(igb_t *, char *); 807 void igb_set_fma_flags(int); 808 809 /* 810 * Function prototypes in igb_gld.c 811 */ 812 int igb_m_start(void *); 813 void igb_m_stop(void *); 814 int igb_m_promisc(void *, boolean_t); 815 int igb_m_multicst(void *, boolean_t, const uint8_t *); 816 int igb_m_unicst(void *, const uint8_t *); 817 int igb_m_stat(void *, uint_t, uint64_t *); 818 void igb_m_resources(void *); 819 void igb_m_ioctl(void *, queue_t *, mblk_t *); 820 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 821 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 822 mac_ring_info_t *, mac_ring_handle_t); 823 int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 824 int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 825 void igb_m_propinfo(void *, const char *, mac_prop_id_t, 826 mac_prop_info_handle_t); 827 int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *); 828 int igb_get_priv_prop(igb_t *, const char *, uint_t, void *); 829 void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t); 830 boolean_t igb_param_locked(mac_prop_id_t); 831 void igb_fill_group(void *arg, mac_ring_type_t, const int, 832 mac_group_info_t *, mac_group_handle_t); 833 int igb_rx_ring_intr_enable(mac_intr_handle_t); 834 int igb_rx_ring_intr_disable(mac_intr_handle_t); 835 int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *); 836 837 /* 838 * Function prototypes in igb_rx.c 839 */ 840 mblk_t *igb_rx(igb_rx_ring_t *, int); 841 void igb_rx_recycle(caddr_t arg); 842 843 /* 844 * Function prototypes in igb_tx.c 845 */ 846 void igb_free_tcb(tx_control_block_t *); 847 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 848 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 849 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 850 851 /* 852 * Function prototypes in igb_log.c 853 */ 854 void igb_notice(void *, const char *, ...); 855 void igb_log(void *, const char *, ...); 856 void igb_error(void *, const char *, ...); 857 858 /* 859 * Function prototypes in igb_stat.c 860 */ 861 int igb_init_stats(igb_t *); 862 863 mblk_t *igb_rx_ring_poll(void *, int); 864 mblk_t *igb_tx_ring_send(void *, mblk_t *); 865 int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 866 int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 867 868 #ifdef __cplusplus 869 } 870 #endif 871 872 #endif /* _IGB_SW_H */ 873