1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_osdep.h" 32 #include "igb_api.h" 33 34 35 s32 36 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size) 37 { 38 hw->dev_spec = kmem_zalloc(size, KM_SLEEP); 39 40 return (E1000_SUCCESS); 41 } 42 43 void 44 e1000_free_dev_spec_struct(struct e1000_hw *hw) 45 { 46 if (hw->dev_spec == NULL) 47 return; 48 49 kmem_free(hw->dev_spec, hw->dev_spec_size); 50 hw->dev_spec = NULL; 51 } 52 53 void 54 e1000_pci_set_mwi(struct e1000_hw *hw) 55 { 56 uint16_t val = hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE; 57 58 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 59 } 60 61 void 62 e1000_pci_clear_mwi(struct e1000_hw *hw) 63 { 64 uint16_t val = hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; 65 66 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 67 } 68 69 void 70 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 71 { 72 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value); 73 } 74 75 void 76 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 77 { 78 *value = 79 pci_config_get16(OS_DEP(hw)->cfg_handle, reg); 80 } 81 82 /* 83 * The real intent of this routine is to return the value from pci-e 84 * config space at offset reg into the capability space. 85 * ICH devices are "PCI Express"-ish. They have a configuration space, 86 * but do not contain PCI Express Capability registers, so this returns 87 * the equivalent of "not supported" 88 */ 89 int32_t 90 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 91 { 92 *value = pci_config_get16(OS_DEP(hw)->cfg_handle, 93 PCI_EX_CONF_CAP + reg); 94 95 return (0); 96 } 97 98 /* 99 * Enables PCI-Express master access. 100 * 101 * hw: Struct containing variables accessed by shared code 102 * 103 * returns: - none. 104 */ 105 void 106 e1000_enable_pciex_master(struct e1000_hw *hw) 107 { 108 uint32_t ctrl; 109 110 if (hw->bus.type != e1000_bus_type_pci_express) 111 return; 112 113 ctrl = E1000_READ_REG(hw, E1000_CTRL); 114 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 115 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 116 } 117