1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 */ 29 30 #include "igb_sw.h" 31 32 static char ident[] = "Intel 1Gb Ethernet"; 33 static char igb_version[] = "igb 1.1.15"; 34 35 /* 36 * Local function protoypes 37 */ 38 static int igb_register_mac(igb_t *); 39 static int igb_identify_hardware(igb_t *); 40 static int igb_regs_map(igb_t *); 41 static void igb_init_properties(igb_t *); 42 static int igb_init_driver_settings(igb_t *); 43 static void igb_init_locks(igb_t *); 44 static void igb_destroy_locks(igb_t *); 45 static int igb_init_mac_address(igb_t *); 46 static int igb_init(igb_t *); 47 static int igb_init_adapter(igb_t *); 48 static void igb_stop_adapter(igb_t *); 49 static int igb_reset(igb_t *); 50 static void igb_tx_clean(igb_t *); 51 static boolean_t igb_tx_drain(igb_t *); 52 static boolean_t igb_rx_drain(igb_t *); 53 static int igb_alloc_rings(igb_t *); 54 static int igb_alloc_rx_data(igb_t *); 55 static void igb_free_rx_data(igb_t *); 56 static void igb_free_rings(igb_t *); 57 static void igb_setup_rings(igb_t *); 58 static void igb_setup_rx(igb_t *); 59 static void igb_setup_tx(igb_t *); 60 static void igb_setup_rx_ring(igb_rx_ring_t *); 61 static void igb_setup_tx_ring(igb_tx_ring_t *); 62 static void igb_setup_rss(igb_t *); 63 static void igb_setup_mac_rss_classify(igb_t *); 64 static void igb_setup_mac_classify(igb_t *); 65 static void igb_init_unicst(igb_t *); 66 static void igb_setup_multicst(igb_t *); 67 static void igb_get_phy_state(igb_t *); 68 static void igb_param_sync(igb_t *); 69 static void igb_get_conf(igb_t *); 70 static int igb_get_prop(igb_t *, char *, int, int, int); 71 static boolean_t igb_is_link_up(igb_t *); 72 static boolean_t igb_link_check(igb_t *); 73 static void igb_local_timer(void *); 74 static void igb_link_timer(void *); 75 static void igb_arm_watchdog_timer(igb_t *); 76 static void igb_start_watchdog_timer(igb_t *); 77 static void igb_restart_watchdog_timer(igb_t *); 78 static void igb_stop_watchdog_timer(igb_t *); 79 static void igb_start_link_timer(igb_t *); 80 static void igb_stop_link_timer(igb_t *); 81 static void igb_disable_adapter_interrupts(igb_t *); 82 static void igb_enable_adapter_interrupts_82575(igb_t *); 83 static void igb_enable_adapter_interrupts_82576(igb_t *); 84 static void igb_enable_adapter_interrupts_82580(igb_t *); 85 static boolean_t is_valid_mac_addr(uint8_t *); 86 static boolean_t igb_stall_check(igb_t *); 87 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 88 static void igb_set_external_loopback(igb_t *); 89 static void igb_set_internal_phy_loopback(igb_t *); 90 static void igb_set_internal_serdes_loopback(igb_t *); 91 static boolean_t igb_find_mac_address(igb_t *); 92 static int igb_alloc_intrs(igb_t *); 93 static int igb_alloc_intr_handles(igb_t *, int); 94 static int igb_add_intr_handlers(igb_t *); 95 static void igb_rem_intr_handlers(igb_t *); 96 static void igb_rem_intrs(igb_t *); 97 static int igb_enable_intrs(igb_t *); 98 static int igb_disable_intrs(igb_t *); 99 static void igb_setup_msix_82575(igb_t *); 100 static void igb_setup_msix_82576(igb_t *); 101 static void igb_setup_msix_82580(igb_t *); 102 static uint_t igb_intr_legacy(void *, void *); 103 static uint_t igb_intr_msi(void *, void *); 104 static uint_t igb_intr_rx(void *, void *); 105 static uint_t igb_intr_tx(void *, void *); 106 static uint_t igb_intr_tx_other(void *, void *); 107 static void igb_intr_rx_work(igb_rx_ring_t *); 108 static void igb_intr_tx_work(igb_tx_ring_t *); 109 static void igb_intr_link_work(igb_t *); 110 static void igb_get_driver_control(struct e1000_hw *); 111 static void igb_release_driver_control(struct e1000_hw *); 112 113 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 114 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 115 static int igb_resume(dev_info_t *); 116 static int igb_suspend(dev_info_t *); 117 static int igb_quiesce(dev_info_t *); 118 static void igb_unconfigure(dev_info_t *, igb_t *); 119 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 120 const void *); 121 static void igb_fm_init(igb_t *); 122 static void igb_fm_fini(igb_t *); 123 static void igb_release_multicast(igb_t *); 124 125 char *igb_priv_props[] = { 126 "_tx_copy_thresh", 127 "_tx_recycle_thresh", 128 "_tx_overload_thresh", 129 "_tx_resched_thresh", 130 "_rx_copy_thresh", 131 "_rx_limit_per_intr", 132 "_intr_throttling", 133 "_adv_pause_cap", 134 "_adv_asym_pause_cap", 135 NULL 136 }; 137 138 static struct cb_ops igb_cb_ops = { 139 nulldev, /* cb_open */ 140 nulldev, /* cb_close */ 141 nodev, /* cb_strategy */ 142 nodev, /* cb_print */ 143 nodev, /* cb_dump */ 144 nodev, /* cb_read */ 145 nodev, /* cb_write */ 146 nodev, /* cb_ioctl */ 147 nodev, /* cb_devmap */ 148 nodev, /* cb_mmap */ 149 nodev, /* cb_segmap */ 150 nochpoll, /* cb_chpoll */ 151 ddi_prop_op, /* cb_prop_op */ 152 NULL, /* cb_stream */ 153 D_MP | D_HOTPLUG, /* cb_flag */ 154 CB_REV, /* cb_rev */ 155 nodev, /* cb_aread */ 156 nodev /* cb_awrite */ 157 }; 158 159 static struct dev_ops igb_dev_ops = { 160 DEVO_REV, /* devo_rev */ 161 0, /* devo_refcnt */ 162 NULL, /* devo_getinfo */ 163 nulldev, /* devo_identify */ 164 nulldev, /* devo_probe */ 165 igb_attach, /* devo_attach */ 166 igb_detach, /* devo_detach */ 167 nodev, /* devo_reset */ 168 &igb_cb_ops, /* devo_cb_ops */ 169 NULL, /* devo_bus_ops */ 170 ddi_power, /* devo_power */ 171 igb_quiesce, /* devo_quiesce */ 172 }; 173 174 static struct modldrv igb_modldrv = { 175 &mod_driverops, /* Type of module. This one is a driver */ 176 ident, /* Discription string */ 177 &igb_dev_ops, /* driver ops */ 178 }; 179 180 static struct modlinkage igb_modlinkage = { 181 MODREV_1, &igb_modldrv, NULL 182 }; 183 184 /* Access attributes for register mapping */ 185 ddi_device_acc_attr_t igb_regs_acc_attr = { 186 DDI_DEVICE_ATTR_V1, 187 DDI_STRUCTURE_LE_ACC, 188 DDI_STRICTORDER_ACC, 189 DDI_FLAGERR_ACC 190 }; 191 192 #define IGB_M_CALLBACK_FLAGS \ 193 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 194 195 static mac_callbacks_t igb_m_callbacks = { 196 IGB_M_CALLBACK_FLAGS, 197 igb_m_stat, 198 igb_m_start, 199 igb_m_stop, 200 igb_m_promisc, 201 igb_m_multicst, 202 NULL, 203 NULL, 204 NULL, 205 igb_m_ioctl, 206 igb_m_getcapab, 207 NULL, 208 NULL, 209 igb_m_setprop, 210 igb_m_getprop, 211 igb_m_propinfo 212 }; 213 214 /* 215 * Initialize capabilities of each supported adapter type 216 */ 217 static adapter_info_t igb_82575_cap = { 218 /* limits */ 219 4, /* maximum number of rx queues */ 220 1, /* minimum number of rx queues */ 221 4, /* default number of rx queues */ 222 4, /* maximum number of tx queues */ 223 1, /* minimum number of tx queues */ 224 4, /* default number of tx queues */ 225 65535, /* maximum interrupt throttle rate */ 226 0, /* minimum interrupt throttle rate */ 227 200, /* default interrupt throttle rate */ 228 229 /* function pointers */ 230 igb_enable_adapter_interrupts_82575, 231 igb_setup_msix_82575, 232 233 /* capabilities */ 234 (IGB_FLAG_HAS_DCA | /* capability flags */ 235 IGB_FLAG_VMDQ_POOL), 236 237 0xffc00000 /* mask for RXDCTL register */ 238 }; 239 240 static adapter_info_t igb_82576_cap = { 241 /* limits */ 242 16, /* maximum number of rx queues */ 243 1, /* minimum number of rx queues */ 244 4, /* default number of rx queues */ 245 16, /* maximum number of tx queues */ 246 1, /* minimum number of tx queues */ 247 4, /* default number of tx queues */ 248 65535, /* maximum interrupt throttle rate */ 249 0, /* minimum interrupt throttle rate */ 250 200, /* default interrupt throttle rate */ 251 252 /* function pointers */ 253 igb_enable_adapter_interrupts_82576, 254 igb_setup_msix_82576, 255 256 /* capabilities */ 257 (IGB_FLAG_HAS_DCA | /* capability flags */ 258 IGB_FLAG_VMDQ_POOL | 259 IGB_FLAG_NEED_CTX_IDX), 260 261 0xffe00000 /* mask for RXDCTL register */ 262 }; 263 264 static adapter_info_t igb_82580_cap = { 265 /* limits */ 266 8, /* maximum number of rx queues */ 267 1, /* minimum number of rx queues */ 268 4, /* default number of rx queues */ 269 8, /* maximum number of tx queues */ 270 1, /* minimum number of tx queues */ 271 4, /* default number of tx queues */ 272 65535, /* maximum interrupt throttle rate */ 273 0, /* minimum interrupt throttle rate */ 274 200, /* default interrupt throttle rate */ 275 276 /* function pointers */ 277 igb_enable_adapter_interrupts_82580, 278 igb_setup_msix_82580, 279 280 /* capabilities */ 281 (IGB_FLAG_HAS_DCA | /* capability flags */ 282 IGB_FLAG_VMDQ_POOL | 283 IGB_FLAG_NEED_CTX_IDX), 284 285 0xffe00000 /* mask for RXDCTL register */ 286 }; 287 288 /* 289 * Module Initialization Functions 290 */ 291 292 int 293 _init(void) 294 { 295 int status; 296 297 mac_init_ops(&igb_dev_ops, MODULE_NAME); 298 299 status = mod_install(&igb_modlinkage); 300 301 if (status != DDI_SUCCESS) { 302 mac_fini_ops(&igb_dev_ops); 303 } 304 305 return (status); 306 } 307 308 int 309 _fini(void) 310 { 311 int status; 312 313 status = mod_remove(&igb_modlinkage); 314 315 if (status == DDI_SUCCESS) { 316 mac_fini_ops(&igb_dev_ops); 317 } 318 319 return (status); 320 321 } 322 323 int 324 _info(struct modinfo *modinfop) 325 { 326 int status; 327 328 status = mod_info(&igb_modlinkage, modinfop); 329 330 return (status); 331 } 332 333 /* 334 * igb_attach - driver attach 335 * 336 * This function is the device specific initialization entry 337 * point. This entry point is required and must be written. 338 * The DDI_ATTACH command must be provided in the attach entry 339 * point. When attach() is called with cmd set to DDI_ATTACH, 340 * all normal kernel services (such as kmem_alloc(9F)) are 341 * available for use by the driver. 342 * 343 * The attach() function will be called once for each instance 344 * of the device on the system with cmd set to DDI_ATTACH. 345 * Until attach() succeeds, the only driver entry points which 346 * may be called are open(9E) and getinfo(9E). 347 */ 348 static int 349 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 350 { 351 igb_t *igb; 352 struct igb_osdep *osdep; 353 struct e1000_hw *hw; 354 int instance; 355 356 /* 357 * Check the command and perform corresponding operations 358 */ 359 switch (cmd) { 360 default: 361 return (DDI_FAILURE); 362 363 case DDI_RESUME: 364 return (igb_resume(devinfo)); 365 366 case DDI_ATTACH: 367 break; 368 } 369 370 /* Get the device instance */ 371 instance = ddi_get_instance(devinfo); 372 373 /* Allocate memory for the instance data structure */ 374 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 375 376 igb->dip = devinfo; 377 igb->instance = instance; 378 379 hw = &igb->hw; 380 osdep = &igb->osdep; 381 hw->back = osdep; 382 osdep->igb = igb; 383 384 /* Attach the instance pointer to the dev_info data structure */ 385 ddi_set_driver_private(devinfo, igb); 386 387 388 /* Initialize for fma support */ 389 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 390 0, 0x0f, 391 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 392 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 393 igb_fm_init(igb); 394 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 395 396 /* 397 * Map PCI config space registers 398 */ 399 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 400 igb_error(igb, "Failed to map PCI configurations"); 401 goto attach_fail; 402 } 403 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 404 405 /* 406 * Identify the chipset family 407 */ 408 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 409 igb_error(igb, "Failed to identify hardware"); 410 goto attach_fail; 411 } 412 413 /* 414 * Map device registers 415 */ 416 if (igb_regs_map(igb) != IGB_SUCCESS) { 417 igb_error(igb, "Failed to map device registers"); 418 goto attach_fail; 419 } 420 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 421 422 /* 423 * Initialize driver parameters 424 */ 425 igb_init_properties(igb); 426 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 427 428 /* 429 * Allocate interrupts 430 */ 431 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 432 igb_error(igb, "Failed to allocate interrupts"); 433 goto attach_fail; 434 } 435 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 436 437 /* 438 * Allocate rx/tx rings based on the ring numbers. 439 * The actual numbers of rx/tx rings are decided by the number of 440 * allocated interrupt vectors, so we should allocate the rings after 441 * interrupts are allocated. 442 */ 443 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 444 igb_error(igb, "Failed to allocate rx/tx rings or groups"); 445 goto attach_fail; 446 } 447 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 448 449 /* 450 * Add interrupt handlers 451 */ 452 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 453 igb_error(igb, "Failed to add interrupt handlers"); 454 goto attach_fail; 455 } 456 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 457 458 /* 459 * Initialize driver parameters 460 */ 461 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 462 igb_error(igb, "Failed to initialize driver settings"); 463 goto attach_fail; 464 } 465 466 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 467 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 468 goto attach_fail; 469 } 470 471 /* 472 * Initialize mutexes for this device. 473 * Do this before enabling the interrupt handler and 474 * register the softint to avoid the condition where 475 * interrupt handler can try using uninitialized mutex 476 */ 477 igb_init_locks(igb); 478 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 479 480 /* 481 * Initialize the adapter 482 */ 483 if (igb_init(igb) != IGB_SUCCESS) { 484 igb_error(igb, "Failed to initialize adapter"); 485 goto attach_fail; 486 } 487 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 488 489 /* 490 * Initialize statistics 491 */ 492 if (igb_init_stats(igb) != IGB_SUCCESS) { 493 igb_error(igb, "Failed to initialize statistics"); 494 goto attach_fail; 495 } 496 igb->attach_progress |= ATTACH_PROGRESS_STATS; 497 498 /* 499 * Register the driver to the MAC 500 */ 501 if (igb_register_mac(igb) != IGB_SUCCESS) { 502 igb_error(igb, "Failed to register MAC"); 503 goto attach_fail; 504 } 505 igb->attach_progress |= ATTACH_PROGRESS_MAC; 506 507 /* 508 * Now that mutex locks are initialized, and the chip is also 509 * initialized, enable interrupts. 510 */ 511 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 512 igb_error(igb, "Failed to enable DDI interrupts"); 513 goto attach_fail; 514 } 515 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 516 517 igb_log(igb, "%s", igb_version); 518 atomic_or_32(&igb->igb_state, IGB_INITIALIZED); 519 520 return (DDI_SUCCESS); 521 522 attach_fail: 523 igb_unconfigure(devinfo, igb); 524 return (DDI_FAILURE); 525 } 526 527 /* 528 * igb_detach - driver detach 529 * 530 * The detach() function is the complement of the attach routine. 531 * If cmd is set to DDI_DETACH, detach() is used to remove the 532 * state associated with a given instance of a device node 533 * prior to the removal of that instance from the system. 534 * 535 * The detach() function will be called once for each instance 536 * of the device for which there has been a successful attach() 537 * once there are no longer any opens on the device. 538 * 539 * Interrupts routine are disabled, All memory allocated by this 540 * driver are freed. 541 */ 542 static int 543 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 544 { 545 igb_t *igb; 546 547 /* 548 * Check detach command 549 */ 550 switch (cmd) { 551 default: 552 return (DDI_FAILURE); 553 554 case DDI_SUSPEND: 555 return (igb_suspend(devinfo)); 556 557 case DDI_DETACH: 558 break; 559 } 560 561 562 /* 563 * Get the pointer to the driver private data structure 564 */ 565 igb = (igb_t *)ddi_get_driver_private(devinfo); 566 if (igb == NULL) 567 return (DDI_FAILURE); 568 569 /* 570 * Unregister MAC. If failed, we have to fail the detach 571 */ 572 if (mac_unregister(igb->mac_hdl) != 0) { 573 igb_error(igb, "Failed to unregister MAC"); 574 return (DDI_FAILURE); 575 } 576 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 577 578 /* 579 * If the device is still running, it needs to be stopped first. 580 * This check is necessary because under some specific circumstances, 581 * the detach routine can be called without stopping the interface 582 * first. 583 */ 584 mutex_enter(&igb->gen_lock); 585 if (igb->igb_state & IGB_STARTED) { 586 atomic_and_32(&igb->igb_state, ~IGB_STARTED); 587 igb_stop(igb, B_TRUE); 588 mutex_exit(&igb->gen_lock); 589 /* Disable and stop the watchdog timer */ 590 igb_disable_watchdog_timer(igb); 591 } else 592 mutex_exit(&igb->gen_lock); 593 594 /* 595 * Check if there are still rx buffers held by the upper layer. 596 * If so, fail the detach. 597 */ 598 if (!igb_rx_drain(igb)) 599 return (DDI_FAILURE); 600 601 /* 602 * Do the remaining unconfigure routines 603 */ 604 igb_unconfigure(devinfo, igb); 605 606 return (DDI_SUCCESS); 607 } 608 609 /* 610 * quiesce(9E) entry point. 611 * 612 * This function is called when the system is single-threaded at high 613 * PIL with preemption disabled. Therefore, this function must not be 614 * blocked. 615 * 616 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 617 * DDI_FAILURE indicates an error condition and should almost never happen. 618 */ 619 static int 620 igb_quiesce(dev_info_t *devinfo) 621 { 622 igb_t *igb; 623 struct e1000_hw *hw; 624 625 igb = (igb_t *)ddi_get_driver_private(devinfo); 626 627 if (igb == NULL) 628 return (DDI_FAILURE); 629 630 hw = &igb->hw; 631 632 /* 633 * Disable the adapter interrupts 634 */ 635 igb_disable_adapter_interrupts(igb); 636 637 /* Tell firmware driver is no longer in control */ 638 igb_release_driver_control(hw); 639 640 /* 641 * Reset the chipset 642 */ 643 (void) e1000_reset_hw(hw); 644 645 /* 646 * Reset PHY if possible 647 */ 648 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 649 (void) e1000_phy_hw_reset(hw); 650 651 return (DDI_SUCCESS); 652 } 653 654 /* 655 * igb_unconfigure - release all resources held by this instance 656 */ 657 static void 658 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 659 { 660 /* 661 * Disable interrupt 662 */ 663 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 664 (void) igb_disable_intrs(igb); 665 } 666 667 /* 668 * Unregister MAC 669 */ 670 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 671 (void) mac_unregister(igb->mac_hdl); 672 } 673 674 /* 675 * Free statistics 676 */ 677 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 678 kstat_delete((kstat_t *)igb->igb_ks); 679 } 680 681 /* 682 * Remove interrupt handlers 683 */ 684 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 685 igb_rem_intr_handlers(igb); 686 } 687 688 /* 689 * Remove interrupts 690 */ 691 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 692 igb_rem_intrs(igb); 693 } 694 695 /* 696 * Remove driver properties 697 */ 698 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 699 (void) ddi_prop_remove_all(devinfo); 700 } 701 702 /* 703 * Stop the adapter 704 */ 705 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) { 706 mutex_enter(&igb->gen_lock); 707 igb_stop_adapter(igb); 708 mutex_exit(&igb->gen_lock); 709 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 710 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 711 } 712 713 /* 714 * Free multicast table 715 */ 716 igb_release_multicast(igb); 717 718 /* 719 * Free register handle 720 */ 721 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 722 if (igb->osdep.reg_handle != NULL) 723 ddi_regs_map_free(&igb->osdep.reg_handle); 724 } 725 726 /* 727 * Free PCI config handle 728 */ 729 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 730 if (igb->osdep.cfg_handle != NULL) 731 pci_config_teardown(&igb->osdep.cfg_handle); 732 } 733 734 /* 735 * Free locks 736 */ 737 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 738 igb_destroy_locks(igb); 739 } 740 741 /* 742 * Free the rx/tx rings 743 */ 744 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 745 igb_free_rings(igb); 746 } 747 748 /* 749 * Remove FMA 750 */ 751 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 752 igb_fm_fini(igb); 753 } 754 755 /* 756 * Free the driver data structure 757 */ 758 kmem_free(igb, sizeof (igb_t)); 759 760 ddi_set_driver_private(devinfo, NULL); 761 } 762 763 /* 764 * igb_register_mac - Register the driver and its function pointers with 765 * the GLD interface 766 */ 767 static int 768 igb_register_mac(igb_t *igb) 769 { 770 struct e1000_hw *hw = &igb->hw; 771 mac_register_t *mac; 772 int status; 773 774 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 775 return (IGB_FAILURE); 776 777 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 778 mac->m_driver = igb; 779 mac->m_dip = igb->dip; 780 mac->m_src_addr = hw->mac.addr; 781 mac->m_callbacks = &igb_m_callbacks; 782 mac->m_min_sdu = 0; 783 mac->m_max_sdu = igb->max_frame_size - 784 sizeof (struct ether_vlan_header) - ETHERFCSL; 785 mac->m_margin = VLAN_TAGSZ; 786 mac->m_priv_props = igb_priv_props; 787 mac->m_v12n = MAC_VIRT_LEVEL1; 788 789 status = mac_register(mac, &igb->mac_hdl); 790 791 mac_free(mac); 792 793 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 794 } 795 796 /* 797 * igb_identify_hardware - Identify the type of the chipset 798 */ 799 static int 800 igb_identify_hardware(igb_t *igb) 801 { 802 struct e1000_hw *hw = &igb->hw; 803 struct igb_osdep *osdep = &igb->osdep; 804 805 /* 806 * Get the device id 807 */ 808 hw->vendor_id = 809 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 810 hw->device_id = 811 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 812 hw->revision_id = 813 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 814 hw->subsystem_device_id = 815 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 816 hw->subsystem_vendor_id = 817 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 818 819 /* 820 * Set the mac type of the adapter based on the device id 821 */ 822 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 823 return (IGB_FAILURE); 824 } 825 826 /* 827 * Install adapter capabilities based on mac type 828 */ 829 switch (hw->mac.type) { 830 case e1000_82575: 831 igb->capab = &igb_82575_cap; 832 break; 833 case e1000_82576: 834 igb->capab = &igb_82576_cap; 835 break; 836 case e1000_82580: 837 igb->capab = &igb_82580_cap; 838 break; 839 default: 840 return (IGB_FAILURE); 841 } 842 843 return (IGB_SUCCESS); 844 } 845 846 /* 847 * igb_regs_map - Map the device registers 848 */ 849 static int 850 igb_regs_map(igb_t *igb) 851 { 852 dev_info_t *devinfo = igb->dip; 853 struct e1000_hw *hw = &igb->hw; 854 struct igb_osdep *osdep = &igb->osdep; 855 off_t mem_size; 856 857 /* 858 * First get the size of device registers to be mapped. 859 */ 860 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) != 861 DDI_SUCCESS) { 862 return (IGB_FAILURE); 863 } 864 865 /* 866 * Call ddi_regs_map_setup() to map registers 867 */ 868 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET, 869 (caddr_t *)&hw->hw_addr, 0, 870 mem_size, &igb_regs_acc_attr, 871 &osdep->reg_handle)) != DDI_SUCCESS) { 872 return (IGB_FAILURE); 873 } 874 875 return (IGB_SUCCESS); 876 } 877 878 /* 879 * igb_init_properties - Initialize driver properties 880 */ 881 static void 882 igb_init_properties(igb_t *igb) 883 { 884 /* 885 * Get conf file properties, including link settings 886 * jumbo frames, ring number, descriptor number, etc. 887 */ 888 igb_get_conf(igb); 889 } 890 891 /* 892 * igb_init_driver_settings - Initialize driver settings 893 * 894 * The settings include hardware function pointers, bus information, 895 * rx/tx rings settings, link state, and any other parameters that 896 * need to be setup during driver initialization. 897 */ 898 static int 899 igb_init_driver_settings(igb_t *igb) 900 { 901 struct e1000_hw *hw = &igb->hw; 902 igb_rx_ring_t *rx_ring; 903 igb_tx_ring_t *tx_ring; 904 uint32_t rx_size; 905 uint32_t tx_size; 906 int i; 907 908 /* 909 * Initialize chipset specific hardware function pointers 910 */ 911 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 912 return (IGB_FAILURE); 913 } 914 915 /* 916 * Get bus information 917 */ 918 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 919 return (IGB_FAILURE); 920 } 921 922 /* 923 * Get the system page size 924 */ 925 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1); 926 927 /* 928 * Set rx buffer size 929 * The IP header alignment room is counted in the calculation. 930 * The rx buffer size is in unit of 1K that is required by the 931 * chipset hardware. 932 */ 933 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 934 igb->rx_buf_size = ((rx_size >> 10) + 935 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 936 937 /* 938 * Set tx buffer size 939 */ 940 tx_size = igb->max_frame_size; 941 igb->tx_buf_size = ((tx_size >> 10) + 942 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 943 944 /* 945 * Initialize rx/tx rings parameters 946 */ 947 for (i = 0; i < igb->num_rx_rings; i++) { 948 rx_ring = &igb->rx_rings[i]; 949 rx_ring->index = i; 950 rx_ring->igb = igb; 951 } 952 953 for (i = 0; i < igb->num_tx_rings; i++) { 954 tx_ring = &igb->tx_rings[i]; 955 tx_ring->index = i; 956 tx_ring->igb = igb; 957 if (igb->tx_head_wb_enable) 958 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 959 else 960 tx_ring->tx_recycle = igb_tx_recycle_legacy; 961 962 tx_ring->ring_size = igb->tx_ring_size; 963 tx_ring->free_list_size = igb->tx_ring_size + 964 (igb->tx_ring_size >> 1); 965 } 966 967 /* 968 * Initialize values of interrupt throttling rates 969 */ 970 for (i = 1; i < MAX_NUM_EITR; i++) 971 igb->intr_throttling[i] = igb->intr_throttling[0]; 972 973 /* 974 * The initial link state should be "unknown" 975 */ 976 igb->link_state = LINK_STATE_UNKNOWN; 977 978 return (IGB_SUCCESS); 979 } 980 981 /* 982 * igb_init_locks - Initialize locks 983 */ 984 static void 985 igb_init_locks(igb_t *igb) 986 { 987 igb_rx_ring_t *rx_ring; 988 igb_tx_ring_t *tx_ring; 989 int i; 990 991 for (i = 0; i < igb->num_rx_rings; i++) { 992 rx_ring = &igb->rx_rings[i]; 993 mutex_init(&rx_ring->rx_lock, NULL, 994 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 995 } 996 997 for (i = 0; i < igb->num_tx_rings; i++) { 998 tx_ring = &igb->tx_rings[i]; 999 mutex_init(&tx_ring->tx_lock, NULL, 1000 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1001 mutex_init(&tx_ring->recycle_lock, NULL, 1002 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1003 mutex_init(&tx_ring->tcb_head_lock, NULL, 1004 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1005 mutex_init(&tx_ring->tcb_tail_lock, NULL, 1006 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1007 } 1008 1009 mutex_init(&igb->gen_lock, NULL, 1010 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1011 1012 mutex_init(&igb->watchdog_lock, NULL, 1013 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1014 1015 mutex_init(&igb->link_lock, NULL, 1016 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1017 } 1018 1019 /* 1020 * igb_destroy_locks - Destroy locks 1021 */ 1022 static void 1023 igb_destroy_locks(igb_t *igb) 1024 { 1025 igb_rx_ring_t *rx_ring; 1026 igb_tx_ring_t *tx_ring; 1027 int i; 1028 1029 for (i = 0; i < igb->num_rx_rings; i++) { 1030 rx_ring = &igb->rx_rings[i]; 1031 mutex_destroy(&rx_ring->rx_lock); 1032 } 1033 1034 for (i = 0; i < igb->num_tx_rings; i++) { 1035 tx_ring = &igb->tx_rings[i]; 1036 mutex_destroy(&tx_ring->tx_lock); 1037 mutex_destroy(&tx_ring->recycle_lock); 1038 mutex_destroy(&tx_ring->tcb_head_lock); 1039 mutex_destroy(&tx_ring->tcb_tail_lock); 1040 } 1041 1042 mutex_destroy(&igb->gen_lock); 1043 mutex_destroy(&igb->watchdog_lock); 1044 mutex_destroy(&igb->link_lock); 1045 } 1046 1047 static int 1048 igb_resume(dev_info_t *devinfo) 1049 { 1050 igb_t *igb; 1051 1052 igb = (igb_t *)ddi_get_driver_private(devinfo); 1053 if (igb == NULL) 1054 return (DDI_FAILURE); 1055 1056 mutex_enter(&igb->gen_lock); 1057 1058 if (igb->igb_state & IGB_STARTED) { 1059 if (igb_start(igb, B_FALSE) != IGB_SUCCESS) { 1060 mutex_exit(&igb->gen_lock); 1061 return (DDI_FAILURE); 1062 } 1063 1064 /* 1065 * Enable and start the watchdog timer 1066 */ 1067 igb_enable_watchdog_timer(igb); 1068 } 1069 1070 atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED); 1071 1072 mutex_exit(&igb->gen_lock); 1073 1074 return (DDI_SUCCESS); 1075 } 1076 1077 static int 1078 igb_suspend(dev_info_t *devinfo) 1079 { 1080 igb_t *igb; 1081 1082 igb = (igb_t *)ddi_get_driver_private(devinfo); 1083 if (igb == NULL) 1084 return (DDI_FAILURE); 1085 1086 mutex_enter(&igb->gen_lock); 1087 1088 atomic_or_32(&igb->igb_state, IGB_SUSPENDED); 1089 1090 if (!(igb->igb_state & IGB_STARTED)) { 1091 mutex_exit(&igb->gen_lock); 1092 return (DDI_SUCCESS); 1093 } 1094 1095 igb_stop(igb, B_FALSE); 1096 1097 mutex_exit(&igb->gen_lock); 1098 1099 /* 1100 * Disable and stop the watchdog timer 1101 */ 1102 igb_disable_watchdog_timer(igb); 1103 1104 return (DDI_SUCCESS); 1105 } 1106 1107 static int 1108 igb_init(igb_t *igb) 1109 { 1110 mutex_enter(&igb->gen_lock); 1111 1112 /* 1113 * Initilize the adapter 1114 */ 1115 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1116 mutex_exit(&igb->gen_lock); 1117 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1118 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1119 return (IGB_FAILURE); 1120 } 1121 1122 mutex_exit(&igb->gen_lock); 1123 1124 return (IGB_SUCCESS); 1125 } 1126 1127 /* 1128 * igb_init_mac_address - Initialize the default MAC address 1129 * 1130 * On success, the MAC address is entered in the igb->hw.mac.addr 1131 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive 1132 * address register. 1133 * 1134 * Important side effects: 1135 * 1. adapter is reset - this is required to put it in a known state. 1136 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where 1137 * MAC address and all default settings are stored, so a valid checksum 1138 * is required. 1139 */ 1140 static int 1141 igb_init_mac_address(igb_t *igb) 1142 { 1143 struct e1000_hw *hw = &igb->hw; 1144 1145 ASSERT(mutex_owned(&igb->gen_lock)); 1146 1147 /* 1148 * Reset chipset to put the hardware in a known state 1149 * before we try to get MAC address from NVM. 1150 */ 1151 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1152 igb_error(igb, "Adapter reset failed."); 1153 goto init_mac_fail; 1154 } 1155 1156 /* 1157 * NVM validation 1158 */ 1159 if (e1000_validate_nvm_checksum(hw) < 0) { 1160 /* 1161 * Some PCI-E parts fail the first check due to 1162 * the link being in sleep state. Call it again, 1163 * if it fails a second time its a real issue. 1164 */ 1165 if (e1000_validate_nvm_checksum(hw) < 0) { 1166 igb_error(igb, 1167 "Invalid NVM checksum. Please contact " 1168 "the vendor to update the NVM."); 1169 goto init_mac_fail; 1170 } 1171 } 1172 1173 /* 1174 * Get the mac address 1175 * This function should handle SPARC case correctly. 1176 */ 1177 if (!igb_find_mac_address(igb)) { 1178 igb_error(igb, "Failed to get the mac address"); 1179 goto init_mac_fail; 1180 } 1181 1182 /* Validate mac address */ 1183 if (!is_valid_mac_addr(hw->mac.addr)) { 1184 igb_error(igb, "Invalid mac address"); 1185 goto init_mac_fail; 1186 } 1187 1188 return (IGB_SUCCESS); 1189 1190 init_mac_fail: 1191 return (IGB_FAILURE); 1192 } 1193 1194 /* 1195 * igb_init_adapter - Initialize the adapter 1196 */ 1197 static int 1198 igb_init_adapter(igb_t *igb) 1199 { 1200 struct e1000_hw *hw = &igb->hw; 1201 uint32_t pba; 1202 uint32_t high_water; 1203 int i; 1204 1205 ASSERT(mutex_owned(&igb->gen_lock)); 1206 1207 /* 1208 * In order to obtain the default MAC address, this will reset the 1209 * adapter and validate the NVM that the address and many other 1210 * default settings come from. 1211 */ 1212 if (igb_init_mac_address(igb) != IGB_SUCCESS) { 1213 igb_error(igb, "Failed to initialize MAC address"); 1214 goto init_adapter_fail; 1215 } 1216 1217 /* 1218 * Setup flow control 1219 * 1220 * These parameters set thresholds for the adapter's generation(Tx) 1221 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1222 * settings. Flow control is enabled or disabled in the configuration 1223 * file. 1224 * High-water mark is set down from the top of the rx fifo (not 1225 * sensitive to max_frame_size) and low-water is set just below 1226 * high-water mark. 1227 * The high water mark must be low enough to fit one full frame above 1228 * it in the rx FIFO. Should be the lower of: 1229 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1230 * frame. 1231 */ 1232 /* 1233 * The default setting of PBA is correct for 82575 and other supported 1234 * adapters do not have the E1000_PBA register, so PBA value is only 1235 * used for calculation here and is never written to the adapter. 1236 */ 1237 if (hw->mac.type == e1000_82575) { 1238 pba = E1000_PBA_34K; 1239 } else { 1240 pba = E1000_PBA_64K; 1241 } 1242 1243 high_water = min(((pba << 10) * 9 / 10), 1244 ((pba << 10) - igb->max_frame_size)); 1245 1246 if (hw->mac.type == e1000_82575) { 1247 /* 8-byte granularity */ 1248 hw->fc.high_water = high_water & 0xFFF8; 1249 hw->fc.low_water = hw->fc.high_water - 8; 1250 } else { 1251 /* 16-byte granularity */ 1252 hw->fc.high_water = high_water & 0xFFF0; 1253 hw->fc.low_water = hw->fc.high_water - 16; 1254 } 1255 1256 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1257 hw->fc.send_xon = B_TRUE; 1258 1259 (void) e1000_validate_mdi_setting(hw); 1260 1261 /* 1262 * Reset the chipset hardware the second time to put PBA settings 1263 * into effect. 1264 */ 1265 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1266 igb_error(igb, "Second reset failed"); 1267 goto init_adapter_fail; 1268 } 1269 1270 /* 1271 * Don't wait for auto-negotiation to complete 1272 */ 1273 hw->phy.autoneg_wait_to_complete = B_FALSE; 1274 1275 /* 1276 * Copper options 1277 */ 1278 if (hw->phy.media_type == e1000_media_type_copper) { 1279 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1280 hw->phy.disable_polarity_correction = B_FALSE; 1281 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1282 } 1283 1284 /* 1285 * Initialize link settings 1286 */ 1287 (void) igb_setup_link(igb, B_FALSE); 1288 1289 /* 1290 * Configure/Initialize hardware 1291 */ 1292 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1293 igb_error(igb, "Failed to initialize hardware"); 1294 goto init_adapter_fail; 1295 } 1296 1297 /* 1298 * Start the link setup timer 1299 */ 1300 igb_start_link_timer(igb); 1301 1302 /* 1303 * Disable wakeup control by default 1304 */ 1305 E1000_WRITE_REG(hw, E1000_WUC, 0); 1306 1307 /* 1308 * Record phy info in hw struct 1309 */ 1310 (void) e1000_get_phy_info(hw); 1311 1312 /* 1313 * Make sure driver has control 1314 */ 1315 igb_get_driver_control(hw); 1316 1317 /* 1318 * Restore LED settings to the default from EEPROM 1319 * to meet the standard for Sun platforms. 1320 */ 1321 (void) e1000_cleanup_led(hw); 1322 1323 /* 1324 * Setup MSI-X interrupts 1325 */ 1326 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1327 igb->capab->setup_msix(igb); 1328 1329 /* 1330 * Initialize unicast addresses. 1331 */ 1332 igb_init_unicst(igb); 1333 1334 /* 1335 * Setup and initialize the mctable structures. 1336 */ 1337 igb_setup_multicst(igb); 1338 1339 /* 1340 * Set interrupt throttling rate 1341 */ 1342 for (i = 0; i < igb->intr_cnt; i++) 1343 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1344 1345 /* 1346 * Save the state of the phy 1347 */ 1348 igb_get_phy_state(igb); 1349 1350 igb_param_sync(igb); 1351 1352 return (IGB_SUCCESS); 1353 1354 init_adapter_fail: 1355 /* 1356 * Reset PHY if possible 1357 */ 1358 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1359 (void) e1000_phy_hw_reset(hw); 1360 1361 return (IGB_FAILURE); 1362 } 1363 1364 /* 1365 * igb_stop_adapter - Stop the adapter 1366 */ 1367 static void 1368 igb_stop_adapter(igb_t *igb) 1369 { 1370 struct e1000_hw *hw = &igb->hw; 1371 1372 ASSERT(mutex_owned(&igb->gen_lock)); 1373 1374 /* Stop the link setup timer */ 1375 igb_stop_link_timer(igb); 1376 1377 /* Tell firmware driver is no longer in control */ 1378 igb_release_driver_control(hw); 1379 1380 /* 1381 * Reset the chipset 1382 */ 1383 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1384 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1385 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1386 } 1387 1388 /* 1389 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient 1390 */ 1391 } 1392 1393 /* 1394 * igb_reset - Reset the chipset and restart the driver. 1395 * 1396 * It involves stopping and re-starting the chipset, 1397 * and re-configuring the rx/tx rings. 1398 */ 1399 static int 1400 igb_reset(igb_t *igb) 1401 { 1402 int i; 1403 1404 mutex_enter(&igb->gen_lock); 1405 1406 ASSERT(igb->igb_state & IGB_STARTED); 1407 atomic_and_32(&igb->igb_state, ~IGB_STARTED); 1408 1409 /* 1410 * Disable the adapter interrupts to stop any rx/tx activities 1411 * before draining pending data and resetting hardware. 1412 */ 1413 igb_disable_adapter_interrupts(igb); 1414 1415 /* 1416 * Drain the pending transmit packets 1417 */ 1418 (void) igb_tx_drain(igb); 1419 1420 for (i = 0; i < igb->num_rx_rings; i++) 1421 mutex_enter(&igb->rx_rings[i].rx_lock); 1422 for (i = 0; i < igb->num_tx_rings; i++) 1423 mutex_enter(&igb->tx_rings[i].tx_lock); 1424 1425 /* 1426 * Stop the adapter 1427 */ 1428 igb_stop_adapter(igb); 1429 1430 /* 1431 * Clean the pending tx data/resources 1432 */ 1433 igb_tx_clean(igb); 1434 1435 /* 1436 * Start the adapter 1437 */ 1438 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1439 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1440 goto reset_failure; 1441 } 1442 1443 /* 1444 * Setup the rx/tx rings 1445 */ 1446 igb->tx_ring_init = B_FALSE; 1447 igb_setup_rings(igb); 1448 1449 atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL)); 1450 1451 /* 1452 * Enable adapter interrupts 1453 * The interrupts must be enabled after the driver state is START 1454 */ 1455 igb->capab->enable_intr(igb); 1456 1457 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1458 goto reset_failure; 1459 1460 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1461 goto reset_failure; 1462 1463 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1464 mutex_exit(&igb->tx_rings[i].tx_lock); 1465 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1466 mutex_exit(&igb->rx_rings[i].rx_lock); 1467 1468 atomic_or_32(&igb->igb_state, IGB_STARTED); 1469 1470 mutex_exit(&igb->gen_lock); 1471 1472 return (IGB_SUCCESS); 1473 1474 reset_failure: 1475 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1476 mutex_exit(&igb->tx_rings[i].tx_lock); 1477 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1478 mutex_exit(&igb->rx_rings[i].rx_lock); 1479 1480 mutex_exit(&igb->gen_lock); 1481 1482 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1483 1484 return (IGB_FAILURE); 1485 } 1486 1487 /* 1488 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1489 */ 1490 static void 1491 igb_tx_clean(igb_t *igb) 1492 { 1493 igb_tx_ring_t *tx_ring; 1494 tx_control_block_t *tcb; 1495 link_list_t pending_list; 1496 uint32_t desc_num; 1497 int i, j; 1498 1499 LINK_LIST_INIT(&pending_list); 1500 1501 for (i = 0; i < igb->num_tx_rings; i++) { 1502 tx_ring = &igb->tx_rings[i]; 1503 1504 mutex_enter(&tx_ring->recycle_lock); 1505 1506 /* 1507 * Clean the pending tx data - the pending packets in the 1508 * work_list that have no chances to be transmitted again. 1509 * 1510 * We must ensure the chipset is stopped or the link is down 1511 * before cleaning the transmit packets. 1512 */ 1513 desc_num = 0; 1514 for (j = 0; j < tx_ring->ring_size; j++) { 1515 tcb = tx_ring->work_list[j]; 1516 if (tcb != NULL) { 1517 desc_num += tcb->desc_num; 1518 1519 tx_ring->work_list[j] = NULL; 1520 1521 igb_free_tcb(tcb); 1522 1523 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1524 } 1525 } 1526 1527 if (desc_num > 0) { 1528 atomic_add_32(&tx_ring->tbd_free, desc_num); 1529 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1530 1531 /* 1532 * Reset the head and tail pointers of the tbd ring; 1533 * Reset the head write-back if it is enabled. 1534 */ 1535 tx_ring->tbd_head = 0; 1536 tx_ring->tbd_tail = 0; 1537 if (igb->tx_head_wb_enable) 1538 *tx_ring->tbd_head_wb = 0; 1539 1540 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1541 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1542 } 1543 1544 mutex_exit(&tx_ring->recycle_lock); 1545 1546 /* 1547 * Add the tx control blocks in the pending list to 1548 * the free list. 1549 */ 1550 igb_put_free_list(tx_ring, &pending_list); 1551 } 1552 } 1553 1554 /* 1555 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1556 */ 1557 static boolean_t 1558 igb_tx_drain(igb_t *igb) 1559 { 1560 igb_tx_ring_t *tx_ring; 1561 boolean_t done; 1562 int i, j; 1563 1564 /* 1565 * Wait for a specific time to allow pending tx packets 1566 * to be transmitted. 1567 * 1568 * Check the counter tbd_free to see if transmission is done. 1569 * No lock protection is needed here. 1570 * 1571 * Return B_TRUE if all pending packets have been transmitted; 1572 * Otherwise return B_FALSE; 1573 */ 1574 for (i = 0; i < TX_DRAIN_TIME; i++) { 1575 1576 done = B_TRUE; 1577 for (j = 0; j < igb->num_tx_rings; j++) { 1578 tx_ring = &igb->tx_rings[j]; 1579 done = done && 1580 (tx_ring->tbd_free == tx_ring->ring_size); 1581 } 1582 1583 if (done) 1584 break; 1585 1586 msec_delay(1); 1587 } 1588 1589 return (done); 1590 } 1591 1592 /* 1593 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1594 */ 1595 static boolean_t 1596 igb_rx_drain(igb_t *igb) 1597 { 1598 boolean_t done; 1599 int i; 1600 1601 /* 1602 * Polling the rx free list to check if those rx buffers held by 1603 * the upper layer are released. 1604 * 1605 * Check the counter rcb_free to see if all pending buffers are 1606 * released. No lock protection is needed here. 1607 * 1608 * Return B_TRUE if all pending buffers have been released; 1609 * Otherwise return B_FALSE; 1610 */ 1611 for (i = 0; i < RX_DRAIN_TIME; i++) { 1612 done = (igb->rcb_pending == 0); 1613 1614 if (done) 1615 break; 1616 1617 msec_delay(1); 1618 } 1619 1620 return (done); 1621 } 1622 1623 /* 1624 * igb_start - Start the driver/chipset 1625 */ 1626 int 1627 igb_start(igb_t *igb, boolean_t alloc_buffer) 1628 { 1629 int i; 1630 1631 ASSERT(mutex_owned(&igb->gen_lock)); 1632 1633 if (alloc_buffer) { 1634 if (igb_alloc_rx_data(igb) != IGB_SUCCESS) { 1635 igb_error(igb, 1636 "Failed to allocate software receive rings"); 1637 return (IGB_FAILURE); 1638 } 1639 1640 /* Allocate buffers for all the rx/tx rings */ 1641 if (igb_alloc_dma(igb) != IGB_SUCCESS) { 1642 igb_error(igb, "Failed to allocate DMA resource"); 1643 return (IGB_FAILURE); 1644 } 1645 1646 igb->tx_ring_init = B_TRUE; 1647 } else { 1648 igb->tx_ring_init = B_FALSE; 1649 } 1650 1651 for (i = 0; i < igb->num_rx_rings; i++) 1652 mutex_enter(&igb->rx_rings[i].rx_lock); 1653 for (i = 0; i < igb->num_tx_rings; i++) 1654 mutex_enter(&igb->tx_rings[i].tx_lock); 1655 1656 /* 1657 * Start the adapter 1658 */ 1659 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) { 1660 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1661 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1662 goto start_failure; 1663 } 1664 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 1665 } 1666 1667 /* 1668 * Setup the rx/tx rings 1669 */ 1670 igb_setup_rings(igb); 1671 1672 /* 1673 * Enable adapter interrupts 1674 * The interrupts must be enabled after the driver state is START 1675 */ 1676 igb->capab->enable_intr(igb); 1677 1678 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1679 goto start_failure; 1680 1681 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1682 goto start_failure; 1683 1684 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1685 mutex_exit(&igb->tx_rings[i].tx_lock); 1686 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1687 mutex_exit(&igb->rx_rings[i].rx_lock); 1688 1689 return (IGB_SUCCESS); 1690 1691 start_failure: 1692 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1693 mutex_exit(&igb->tx_rings[i].tx_lock); 1694 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1695 mutex_exit(&igb->rx_rings[i].rx_lock); 1696 1697 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1698 1699 return (IGB_FAILURE); 1700 } 1701 1702 /* 1703 * igb_stop - Stop the driver/chipset 1704 */ 1705 void 1706 igb_stop(igb_t *igb, boolean_t free_buffer) 1707 { 1708 int i; 1709 1710 ASSERT(mutex_owned(&igb->gen_lock)); 1711 1712 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER; 1713 1714 /* 1715 * Disable the adapter interrupts 1716 */ 1717 igb_disable_adapter_interrupts(igb); 1718 1719 /* 1720 * Drain the pending tx packets 1721 */ 1722 (void) igb_tx_drain(igb); 1723 1724 for (i = 0; i < igb->num_rx_rings; i++) 1725 mutex_enter(&igb->rx_rings[i].rx_lock); 1726 for (i = 0; i < igb->num_tx_rings; i++) 1727 mutex_enter(&igb->tx_rings[i].tx_lock); 1728 1729 /* 1730 * Stop the adapter 1731 */ 1732 igb_stop_adapter(igb); 1733 1734 /* 1735 * Clean the pending tx data/resources 1736 */ 1737 igb_tx_clean(igb); 1738 1739 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1740 mutex_exit(&igb->tx_rings[i].tx_lock); 1741 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1742 mutex_exit(&igb->rx_rings[i].rx_lock); 1743 1744 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1745 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1746 1747 if (igb->link_state == LINK_STATE_UP) { 1748 igb->link_state = LINK_STATE_UNKNOWN; 1749 mac_link_update(igb->mac_hdl, igb->link_state); 1750 } 1751 1752 if (free_buffer) { 1753 /* 1754 * Release the DMA/memory resources of rx/tx rings 1755 */ 1756 igb_free_dma(igb); 1757 igb_free_rx_data(igb); 1758 } 1759 } 1760 1761 /* 1762 * igb_alloc_rings - Allocate memory space for rx/tx rings 1763 */ 1764 static int 1765 igb_alloc_rings(igb_t *igb) 1766 { 1767 /* 1768 * Allocate memory space for rx rings 1769 */ 1770 igb->rx_rings = kmem_zalloc( 1771 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1772 KM_NOSLEEP); 1773 1774 if (igb->rx_rings == NULL) { 1775 return (IGB_FAILURE); 1776 } 1777 1778 /* 1779 * Allocate memory space for tx rings 1780 */ 1781 igb->tx_rings = kmem_zalloc( 1782 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1783 KM_NOSLEEP); 1784 1785 if (igb->tx_rings == NULL) { 1786 kmem_free(igb->rx_rings, 1787 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1788 igb->rx_rings = NULL; 1789 return (IGB_FAILURE); 1790 } 1791 1792 /* 1793 * Allocate memory space for rx ring groups 1794 */ 1795 igb->rx_groups = kmem_zalloc( 1796 sizeof (igb_rx_group_t) * igb->num_rx_groups, 1797 KM_NOSLEEP); 1798 1799 if (igb->rx_groups == NULL) { 1800 kmem_free(igb->rx_rings, 1801 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1802 kmem_free(igb->tx_rings, 1803 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1804 igb->rx_rings = NULL; 1805 igb->tx_rings = NULL; 1806 return (IGB_FAILURE); 1807 } 1808 1809 return (IGB_SUCCESS); 1810 } 1811 1812 /* 1813 * igb_free_rings - Free the memory space of rx/tx rings. 1814 */ 1815 static void 1816 igb_free_rings(igb_t *igb) 1817 { 1818 if (igb->rx_rings != NULL) { 1819 kmem_free(igb->rx_rings, 1820 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1821 igb->rx_rings = NULL; 1822 } 1823 1824 if (igb->tx_rings != NULL) { 1825 kmem_free(igb->tx_rings, 1826 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1827 igb->tx_rings = NULL; 1828 } 1829 1830 if (igb->rx_groups != NULL) { 1831 kmem_free(igb->rx_groups, 1832 sizeof (igb_rx_group_t) * igb->num_rx_groups); 1833 igb->rx_groups = NULL; 1834 } 1835 } 1836 1837 static int 1838 igb_alloc_rx_data(igb_t *igb) 1839 { 1840 igb_rx_ring_t *rx_ring; 1841 int i; 1842 1843 for (i = 0; i < igb->num_rx_rings; i++) { 1844 rx_ring = &igb->rx_rings[i]; 1845 if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS) 1846 goto alloc_rx_rings_failure; 1847 } 1848 return (IGB_SUCCESS); 1849 1850 alloc_rx_rings_failure: 1851 igb_free_rx_data(igb); 1852 return (IGB_FAILURE); 1853 } 1854 1855 static void 1856 igb_free_rx_data(igb_t *igb) 1857 { 1858 igb_rx_ring_t *rx_ring; 1859 igb_rx_data_t *rx_data; 1860 int i; 1861 1862 for (i = 0; i < igb->num_rx_rings; i++) { 1863 rx_ring = &igb->rx_rings[i]; 1864 1865 mutex_enter(&igb->rx_pending_lock); 1866 rx_data = rx_ring->rx_data; 1867 1868 if (rx_data != NULL) { 1869 rx_data->flag |= IGB_RX_STOPPED; 1870 1871 if (rx_data->rcb_pending == 0) { 1872 igb_free_rx_ring_data(rx_data); 1873 rx_ring->rx_data = NULL; 1874 } 1875 } 1876 1877 mutex_exit(&igb->rx_pending_lock); 1878 } 1879 } 1880 1881 /* 1882 * igb_setup_rings - Setup rx/tx rings 1883 */ 1884 static void 1885 igb_setup_rings(igb_t *igb) 1886 { 1887 /* 1888 * Setup the rx/tx rings, including the following: 1889 * 1890 * 1. Setup the descriptor ring and the control block buffers; 1891 * 2. Initialize necessary registers for receive/transmit; 1892 * 3. Initialize software pointers/parameters for receive/transmit; 1893 */ 1894 igb_setup_rx(igb); 1895 1896 igb_setup_tx(igb); 1897 } 1898 1899 static void 1900 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1901 { 1902 igb_t *igb = rx_ring->igb; 1903 igb_rx_data_t *rx_data = rx_ring->rx_data; 1904 struct e1000_hw *hw = &igb->hw; 1905 rx_control_block_t *rcb; 1906 union e1000_adv_rx_desc *rbd; 1907 uint32_t size; 1908 uint32_t buf_low; 1909 uint32_t buf_high; 1910 uint32_t rxdctl; 1911 int i; 1912 1913 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1914 ASSERT(mutex_owned(&igb->gen_lock)); 1915 1916 /* 1917 * Initialize descriptor ring with buffer addresses 1918 */ 1919 for (i = 0; i < igb->rx_ring_size; i++) { 1920 rcb = rx_data->work_list[i]; 1921 rbd = &rx_data->rbd_ring[i]; 1922 1923 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1924 rbd->read.hdr_addr = NULL; 1925 } 1926 1927 /* 1928 * Initialize the base address registers 1929 */ 1930 buf_low = (uint32_t)rx_data->rbd_area.dma_address; 1931 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32); 1932 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1933 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1934 1935 /* 1936 * Initialize the length register 1937 */ 1938 size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc); 1939 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1940 1941 /* 1942 * Initialize buffer size & descriptor type 1943 */ 1944 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), 1945 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1946 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF)); 1947 1948 /* 1949 * Setup the Receive Descriptor Control Register (RXDCTL) 1950 */ 1951 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1952 rxdctl &= igb->capab->rxdctl_mask; 1953 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 1954 rxdctl |= 16; /* pthresh */ 1955 rxdctl |= 8 << 8; /* hthresh */ 1956 rxdctl |= 1 << 16; /* wthresh */ 1957 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl); 1958 1959 rx_data->rbd_next = 0; 1960 } 1961 1962 static void 1963 igb_setup_rx(igb_t *igb) 1964 { 1965 igb_rx_ring_t *rx_ring; 1966 igb_rx_data_t *rx_data; 1967 igb_rx_group_t *rx_group; 1968 struct e1000_hw *hw = &igb->hw; 1969 uint32_t rctl, rxcsum; 1970 uint32_t ring_per_group; 1971 int i; 1972 1973 /* 1974 * Setup the Receive Control Register (RCTL), and enable the 1975 * receiver. The initial configuration is to: enable the receiver, 1976 * accept broadcasts, discard bad packets, accept long packets, 1977 * disable VLAN filter checking, and set receive buffer size to 1978 * 2k. For 82575, also set the receive descriptor minimum 1979 * threshold size to 1/2 the ring. 1980 */ 1981 rctl = E1000_READ_REG(hw, E1000_RCTL); 1982 1983 /* 1984 * Clear the field used for wakeup control. This driver doesn't do 1985 * wakeup but leave this here for completeness. 1986 */ 1987 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 1988 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1989 1990 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 1991 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1992 E1000_RCTL_LPE | /* Large Packet Enable */ 1993 /* Multicast filter offset */ 1994 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1995 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */ 1996 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 1997 1998 for (i = 0; i < igb->num_rx_groups; i++) { 1999 rx_group = &igb->rx_groups[i]; 2000 rx_group->index = i; 2001 rx_group->igb = igb; 2002 } 2003 2004 /* 2005 * Set up all rx descriptor rings - must be called before receive unit 2006 * enabled. 2007 */ 2008 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2009 for (i = 0; i < igb->num_rx_rings; i++) { 2010 rx_ring = &igb->rx_rings[i]; 2011 igb_setup_rx_ring(rx_ring); 2012 2013 /* 2014 * Map a ring to a group by assigning a group index 2015 */ 2016 rx_ring->group_index = i / ring_per_group; 2017 } 2018 2019 /* 2020 * Setup the Rx Long Packet Max Length register 2021 */ 2022 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 2023 2024 /* 2025 * Hardware checksum settings 2026 */ 2027 if (igb->rx_hcksum_enable) { 2028 rxcsum = 2029 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 2030 E1000_RXCSUM_IPOFL; /* IP checksum */ 2031 2032 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2033 } 2034 2035 /* 2036 * Setup classify and RSS for multiple receive queues 2037 */ 2038 switch (igb->vmdq_mode) { 2039 case E1000_VMDQ_OFF: 2040 /* 2041 * One ring group, only RSS is needed when more than 2042 * one ring enabled. 2043 */ 2044 if (igb->num_rx_rings > 1) 2045 igb_setup_rss(igb); 2046 break; 2047 case E1000_VMDQ_MAC: 2048 /* 2049 * Multiple groups, each group has one ring, 2050 * only the MAC classification is needed. 2051 */ 2052 igb_setup_mac_classify(igb); 2053 break; 2054 case E1000_VMDQ_MAC_RSS: 2055 /* 2056 * Multiple groups and multiple rings, both 2057 * MAC classification and RSS are needed. 2058 */ 2059 igb_setup_mac_rss_classify(igb); 2060 break; 2061 } 2062 2063 /* 2064 * Enable the receive unit - must be done after all 2065 * the rx setup above. 2066 */ 2067 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2068 2069 /* 2070 * Initialize all adapter ring head & tail pointers - must 2071 * be done after receive unit is enabled 2072 */ 2073 for (i = 0; i < igb->num_rx_rings; i++) { 2074 rx_ring = &igb->rx_rings[i]; 2075 rx_data = rx_ring->rx_data; 2076 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 2077 E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1); 2078 } 2079 2080 /* 2081 * 82575 with manageability enabled needs a special flush to make 2082 * sure the fifos start clean. 2083 */ 2084 if ((hw->mac.type == e1000_82575) && 2085 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) { 2086 e1000_rx_fifo_flush_82575(hw); 2087 } 2088 } 2089 2090 static void 2091 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 2092 { 2093 igb_t *igb = tx_ring->igb; 2094 struct e1000_hw *hw = &igb->hw; 2095 uint32_t size; 2096 uint32_t buf_low; 2097 uint32_t buf_high; 2098 uint32_t reg_val; 2099 2100 ASSERT(mutex_owned(&tx_ring->tx_lock)); 2101 ASSERT(mutex_owned(&igb->gen_lock)); 2102 2103 2104 /* 2105 * Initialize the length register 2106 */ 2107 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 2108 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 2109 2110 /* 2111 * Initialize the base address registers 2112 */ 2113 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 2114 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 2115 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 2116 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 2117 2118 /* 2119 * Setup head & tail pointers 2120 */ 2121 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 2122 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 2123 2124 /* 2125 * Setup head write-back 2126 */ 2127 if (igb->tx_head_wb_enable) { 2128 /* 2129 * The memory of the head write-back is allocated using 2130 * the extra tbd beyond the tail of the tbd ring. 2131 */ 2132 tx_ring->tbd_head_wb = (uint32_t *) 2133 ((uintptr_t)tx_ring->tbd_area.address + size); 2134 *tx_ring->tbd_head_wb = 0; 2135 2136 buf_low = (uint32_t) 2137 (tx_ring->tbd_area.dma_address + size); 2138 buf_high = (uint32_t) 2139 ((tx_ring->tbd_area.dma_address + size) >> 32); 2140 2141 /* Set the head write-back enable bit */ 2142 buf_low |= E1000_TX_HEAD_WB_ENABLE; 2143 2144 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 2145 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 2146 2147 /* 2148 * Turn off relaxed ordering for head write back or it will 2149 * cause problems with the tx recycling 2150 */ 2151 reg_val = E1000_READ_REG(hw, 2152 E1000_DCA_TXCTRL(tx_ring->index)); 2153 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 2154 E1000_WRITE_REG(hw, 2155 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 2156 } else { 2157 tx_ring->tbd_head_wb = NULL; 2158 } 2159 2160 tx_ring->tbd_head = 0; 2161 tx_ring->tbd_tail = 0; 2162 tx_ring->tbd_free = tx_ring->ring_size; 2163 2164 if (igb->tx_ring_init == B_TRUE) { 2165 tx_ring->tcb_head = 0; 2166 tx_ring->tcb_tail = 0; 2167 tx_ring->tcb_free = tx_ring->free_list_size; 2168 } 2169 2170 /* 2171 * Enable TXDCTL per queue 2172 */ 2173 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); 2174 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; 2175 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); 2176 2177 /* 2178 * Initialize hardware checksum offload settings 2179 */ 2180 bzero(&tx_ring->tx_context, sizeof (tx_context_t)); 2181 } 2182 2183 static void 2184 igb_setup_tx(igb_t *igb) 2185 { 2186 igb_tx_ring_t *tx_ring; 2187 struct e1000_hw *hw = &igb->hw; 2188 uint32_t reg_val; 2189 int i; 2190 2191 for (i = 0; i < igb->num_tx_rings; i++) { 2192 tx_ring = &igb->tx_rings[i]; 2193 igb_setup_tx_ring(tx_ring); 2194 } 2195 2196 /* 2197 * Setup the Transmit Control Register (TCTL) 2198 */ 2199 reg_val = E1000_READ_REG(hw, E1000_TCTL); 2200 reg_val &= ~E1000_TCTL_CT; 2201 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2202 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2203 2204 /* Enable transmits */ 2205 reg_val |= E1000_TCTL_EN; 2206 2207 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 2208 } 2209 2210 /* 2211 * igb_setup_rss - Setup receive-side scaling feature 2212 */ 2213 static void 2214 igb_setup_rss(igb_t *igb) 2215 { 2216 struct e1000_hw *hw = &igb->hw; 2217 uint32_t i, mrqc, rxcsum; 2218 int shift = 0; 2219 uint32_t random; 2220 union e1000_reta { 2221 uint32_t dword; 2222 uint8_t bytes[4]; 2223 } reta; 2224 2225 /* Setup the Redirection Table */ 2226 if (hw->mac.type == e1000_82576) { 2227 shift = 3; 2228 } else if (hw->mac.type == e1000_82575) { 2229 shift = 6; 2230 } 2231 for (i = 0; i < (32 * 4); i++) { 2232 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 2233 if ((i & 3) == 3) { 2234 E1000_WRITE_REG(hw, 2235 (E1000_RETA(0) + (i & ~3)), reta.dword); 2236 } 2237 } 2238 2239 /* Fill out hash function seeds */ 2240 for (i = 0; i < 10; i++) { 2241 (void) random_get_pseudo_bytes((uint8_t *)&random, 2242 sizeof (uint32_t)); 2243 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2244 } 2245 2246 /* Setup the Multiple Receive Queue Control register */ 2247 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2248 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2249 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2250 E1000_MRQC_RSS_FIELD_IPV6 | 2251 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2252 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2253 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2254 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2255 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2256 2257 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2258 2259 /* 2260 * Disable Packet Checksum to enable RSS for multiple receive queues. 2261 * 2262 * The Packet Checksum is not ethernet CRC. It is another kind of 2263 * checksum offloading provided by the 82575 chipset besides the IP 2264 * header checksum offloading and the TCP/UDP checksum offloading. 2265 * The Packet Checksum is by default computed over the entire packet 2266 * from the first byte of the DA through the last byte of the CRC, 2267 * including the Ethernet and IP headers. 2268 * 2269 * It is a hardware limitation that Packet Checksum is mutually 2270 * exclusive with RSS. 2271 */ 2272 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2273 rxcsum |= E1000_RXCSUM_PCSD; 2274 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2275 } 2276 2277 /* 2278 * igb_setup_mac_rss_classify - Setup MAC classification and rss 2279 */ 2280 static void 2281 igb_setup_mac_rss_classify(igb_t *igb) 2282 { 2283 struct e1000_hw *hw = &igb->hw; 2284 uint32_t i, mrqc, vmdctl, rxcsum; 2285 uint32_t ring_per_group; 2286 int shift_group0, shift_group1; 2287 uint32_t random; 2288 union e1000_reta { 2289 uint32_t dword; 2290 uint8_t bytes[4]; 2291 } reta; 2292 2293 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2294 2295 /* Setup the Redirection Table, it is shared between two groups */ 2296 shift_group0 = 2; 2297 shift_group1 = 6; 2298 for (i = 0; i < (32 * 4); i++) { 2299 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) | 2300 ((ring_per_group + (i % ring_per_group)) << shift_group1); 2301 if ((i & 3) == 3) { 2302 E1000_WRITE_REG(hw, 2303 (E1000_RETA(0) + (i & ~3)), reta.dword); 2304 } 2305 } 2306 2307 /* Fill out hash function seeds */ 2308 for (i = 0; i < 10; i++) { 2309 (void) random_get_pseudo_bytes((uint8_t *)&random, 2310 sizeof (uint32_t)); 2311 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2312 } 2313 2314 /* 2315 * Setup the Multiple Receive Queue Control register, 2316 * enable VMDq based on packet destination MAC address and RSS. 2317 */ 2318 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP; 2319 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2320 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2321 E1000_MRQC_RSS_FIELD_IPV6 | 2322 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2323 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2324 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2325 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2326 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2327 2328 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2329 2330 2331 /* Define the default group and default queues */ 2332 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE; 2333 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl); 2334 2335 /* 2336 * Disable Packet Checksum to enable RSS for multiple receive queues. 2337 * 2338 * The Packet Checksum is not ethernet CRC. It is another kind of 2339 * checksum offloading provided by the 82575 chipset besides the IP 2340 * header checksum offloading and the TCP/UDP checksum offloading. 2341 * The Packet Checksum is by default computed over the entire packet 2342 * from the first byte of the DA through the last byte of the CRC, 2343 * including the Ethernet and IP headers. 2344 * 2345 * It is a hardware limitation that Packet Checksum is mutually 2346 * exclusive with RSS. 2347 */ 2348 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2349 rxcsum |= E1000_RXCSUM_PCSD; 2350 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2351 } 2352 2353 /* 2354 * igb_setup_mac_classify - Setup MAC classification feature 2355 */ 2356 static void 2357 igb_setup_mac_classify(igb_t *igb) 2358 { 2359 struct e1000_hw *hw = &igb->hw; 2360 uint32_t mrqc, rxcsum; 2361 2362 /* 2363 * Setup the Multiple Receive Queue Control register, 2364 * enable VMDq based on packet destination MAC address. 2365 */ 2366 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP; 2367 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2368 2369 /* 2370 * Disable Packet Checksum to enable RSS for multiple receive queues. 2371 * 2372 * The Packet Checksum is not ethernet CRC. It is another kind of 2373 * checksum offloading provided by the 82575 chipset besides the IP 2374 * header checksum offloading and the TCP/UDP checksum offloading. 2375 * The Packet Checksum is by default computed over the entire packet 2376 * from the first byte of the DA through the last byte of the CRC, 2377 * including the Ethernet and IP headers. 2378 * 2379 * It is a hardware limitation that Packet Checksum is mutually 2380 * exclusive with RSS. 2381 */ 2382 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2383 rxcsum |= E1000_RXCSUM_PCSD; 2384 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2385 2386 } 2387 2388 /* 2389 * igb_init_unicst - Initialize the unicast addresses 2390 */ 2391 static void 2392 igb_init_unicst(igb_t *igb) 2393 { 2394 struct e1000_hw *hw = &igb->hw; 2395 int slot; 2396 2397 /* 2398 * Here we should consider two situations: 2399 * 2400 * 1. Chipset is initialized the first time 2401 * Initialize the multiple unicast addresses, and 2402 * save the default MAC address. 2403 * 2404 * 2. Chipset is reset 2405 * Recover the multiple unicast addresses from the 2406 * software data structure to the RAR registers. 2407 */ 2408 2409 /* 2410 * Clear the default MAC address in the RAR0 rgister, 2411 * which is loaded from EEPROM when system boot or chipreset, 2412 * this will cause the conficts with add_mac/rem_mac entry 2413 * points when VMDq is enabled. For this reason, the RAR0 2414 * must be cleared for both cases mentioned above. 2415 */ 2416 e1000_rar_clear(hw, 0); 2417 2418 if (!igb->unicst_init) { 2419 2420 /* Initialize the multiple unicast addresses */ 2421 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2422 igb->unicst_avail = igb->unicst_total; 2423 2424 for (slot = 0; slot < igb->unicst_total; slot++) 2425 igb->unicst_addr[slot].mac.set = 0; 2426 2427 igb->unicst_init = B_TRUE; 2428 } else { 2429 /* Re-configure the RAR registers */ 2430 for (slot = 0; slot < igb->unicst_total; slot++) { 2431 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr, 2432 slot, igb->vmdq_mode, 2433 igb->unicst_addr[slot].mac.group_index); 2434 } 2435 } 2436 } 2437 2438 /* 2439 * igb_unicst_find - Find the slot for the specified unicast address 2440 */ 2441 int 2442 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr) 2443 { 2444 int slot; 2445 2446 ASSERT(mutex_owned(&igb->gen_lock)); 2447 2448 for (slot = 0; slot < igb->unicst_total; slot++) { 2449 if (bcmp(igb->unicst_addr[slot].mac.addr, 2450 mac_addr, ETHERADDRL) == 0) 2451 return (slot); 2452 } 2453 2454 return (-1); 2455 } 2456 2457 /* 2458 * igb_unicst_set - Set the unicast address to the specified slot 2459 */ 2460 int 2461 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2462 int slot) 2463 { 2464 struct e1000_hw *hw = &igb->hw; 2465 2466 ASSERT(mutex_owned(&igb->gen_lock)); 2467 2468 /* 2469 * Save the unicast address in the software data structure 2470 */ 2471 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2472 2473 /* 2474 * Set the unicast address to the RAR register 2475 */ 2476 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2477 2478 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2479 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2480 return (EIO); 2481 } 2482 2483 return (0); 2484 } 2485 2486 /* 2487 * igb_multicst_add - Add a multicst address 2488 */ 2489 int 2490 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2491 { 2492 struct ether_addr *new_table; 2493 size_t new_len; 2494 size_t old_len; 2495 2496 ASSERT(mutex_owned(&igb->gen_lock)); 2497 2498 if ((multiaddr[0] & 01) == 0) { 2499 igb_error(igb, "Illegal multicast address"); 2500 return (EINVAL); 2501 } 2502 2503 if (igb->mcast_count >= igb->mcast_max_num) { 2504 igb_error(igb, "Adapter requested more than %d mcast addresses", 2505 igb->mcast_max_num); 2506 return (ENOENT); 2507 } 2508 2509 if (igb->mcast_count == igb->mcast_alloc_count) { 2510 old_len = igb->mcast_alloc_count * 2511 sizeof (struct ether_addr); 2512 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) * 2513 sizeof (struct ether_addr); 2514 2515 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2516 if (new_table == NULL) { 2517 igb_error(igb, 2518 "Not enough memory to alloc mcast table"); 2519 return (ENOMEM); 2520 } 2521 2522 if (igb->mcast_table != NULL) { 2523 bcopy(igb->mcast_table, new_table, old_len); 2524 kmem_free(igb->mcast_table, old_len); 2525 } 2526 igb->mcast_alloc_count += MCAST_ALLOC_COUNT; 2527 igb->mcast_table = new_table; 2528 } 2529 2530 bcopy(multiaddr, 2531 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2532 igb->mcast_count++; 2533 2534 /* 2535 * Update the multicast table in the hardware 2536 */ 2537 igb_setup_multicst(igb); 2538 2539 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2540 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2541 return (EIO); 2542 } 2543 2544 return (0); 2545 } 2546 2547 /* 2548 * igb_multicst_remove - Remove a multicst address 2549 */ 2550 int 2551 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2552 { 2553 struct ether_addr *new_table; 2554 size_t new_len; 2555 size_t old_len; 2556 int i; 2557 2558 ASSERT(mutex_owned(&igb->gen_lock)); 2559 2560 for (i = 0; i < igb->mcast_count; i++) { 2561 if (bcmp(multiaddr, &igb->mcast_table[i], 2562 ETHERADDRL) == 0) { 2563 for (i++; i < igb->mcast_count; i++) { 2564 igb->mcast_table[i - 1] = 2565 igb->mcast_table[i]; 2566 } 2567 igb->mcast_count--; 2568 break; 2569 } 2570 } 2571 2572 if ((igb->mcast_alloc_count - igb->mcast_count) > 2573 MCAST_ALLOC_COUNT) { 2574 old_len = igb->mcast_alloc_count * 2575 sizeof (struct ether_addr); 2576 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) * 2577 sizeof (struct ether_addr); 2578 2579 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2580 if (new_table != NULL) { 2581 bcopy(igb->mcast_table, new_table, new_len); 2582 kmem_free(igb->mcast_table, old_len); 2583 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT; 2584 igb->mcast_table = new_table; 2585 } 2586 } 2587 2588 /* 2589 * Update the multicast table in the hardware 2590 */ 2591 igb_setup_multicst(igb); 2592 2593 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2594 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2595 return (EIO); 2596 } 2597 2598 return (0); 2599 } 2600 2601 static void 2602 igb_release_multicast(igb_t *igb) 2603 { 2604 if (igb->mcast_table != NULL) { 2605 kmem_free(igb->mcast_table, 2606 igb->mcast_alloc_count * sizeof (struct ether_addr)); 2607 igb->mcast_table = NULL; 2608 } 2609 } 2610 2611 /* 2612 * igb_setup_multicast - setup multicast data structures 2613 * 2614 * This routine initializes all of the multicast related structures 2615 * and save them in the hardware registers. 2616 */ 2617 static void 2618 igb_setup_multicst(igb_t *igb) 2619 { 2620 uint8_t *mc_addr_list; 2621 uint32_t mc_addr_count; 2622 struct e1000_hw *hw = &igb->hw; 2623 2624 ASSERT(mutex_owned(&igb->gen_lock)); 2625 ASSERT(igb->mcast_count <= igb->mcast_max_num); 2626 2627 mc_addr_list = (uint8_t *)igb->mcast_table; 2628 mc_addr_count = igb->mcast_count; 2629 2630 /* 2631 * Update the multicase addresses to the MTA registers 2632 */ 2633 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count); 2634 } 2635 2636 /* 2637 * igb_get_conf - Get driver configurations set in driver.conf 2638 * 2639 * This routine gets user-configured values out of the configuration 2640 * file igb.conf. 2641 * 2642 * For each configurable value, there is a minimum, a maximum, and a 2643 * default. 2644 * If user does not configure a value, use the default. 2645 * If user configures below the minimum, use the minumum. 2646 * If user configures above the maximum, use the maxumum. 2647 */ 2648 static void 2649 igb_get_conf(igb_t *igb) 2650 { 2651 struct e1000_hw *hw = &igb->hw; 2652 uint32_t default_mtu; 2653 uint32_t flow_control; 2654 uint32_t ring_per_group; 2655 int i; 2656 2657 /* 2658 * igb driver supports the following user configurations: 2659 * 2660 * Link configurations: 2661 * adv_autoneg_cap 2662 * adv_1000fdx_cap 2663 * adv_100fdx_cap 2664 * adv_100hdx_cap 2665 * adv_10fdx_cap 2666 * adv_10hdx_cap 2667 * Note: 1000hdx is not supported. 2668 * 2669 * Jumbo frame configuration: 2670 * default_mtu 2671 * 2672 * Ethernet flow control configuration: 2673 * flow_control 2674 * 2675 * Multiple rings configurations: 2676 * tx_queue_number 2677 * tx_ring_size 2678 * rx_queue_number 2679 * rx_ring_size 2680 * 2681 * Call igb_get_prop() to get the value for a specific 2682 * configuration parameter. 2683 */ 2684 2685 /* 2686 * Link configurations 2687 */ 2688 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2689 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2690 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2691 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2692 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2693 PROP_ADV_100FDX_CAP, 0, 1, 1); 2694 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2695 PROP_ADV_100HDX_CAP, 0, 1, 1); 2696 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2697 PROP_ADV_10FDX_CAP, 0, 1, 1); 2698 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2699 PROP_ADV_10HDX_CAP, 0, 1, 1); 2700 2701 /* 2702 * Jumbo frame configurations 2703 */ 2704 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2705 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2706 2707 igb->max_frame_size = default_mtu + 2708 sizeof (struct ether_vlan_header) + ETHERFCSL; 2709 2710 /* 2711 * Ethernet flow control configuration 2712 */ 2713 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2714 e1000_fc_none, 4, e1000_fc_full); 2715 if (flow_control == 4) 2716 flow_control = e1000_fc_default; 2717 2718 hw->fc.requested_mode = flow_control; 2719 2720 /* 2721 * Multiple rings configurations 2722 */ 2723 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2724 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2725 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2726 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2727 2728 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0); 2729 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM, 2730 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2731 /* 2732 * Currently we do not support VMDq for 82576 and 82580. 2733 * If it is e1000_82576, set num_rx_groups to 1. 2734 */ 2735 if (hw->mac.type >= e1000_82576) 2736 igb->num_rx_groups = 1; 2737 2738 if (igb->mr_enable) { 2739 igb->num_tx_rings = igb->capab->def_tx_que_num; 2740 igb->num_rx_rings = igb->capab->def_rx_que_num; 2741 } else { 2742 igb->num_tx_rings = 1; 2743 igb->num_rx_rings = 1; 2744 2745 if (igb->num_rx_groups > 1) { 2746 igb_error(igb, 2747 "Invalid rx groups number. Please enable multiple " 2748 "rings first"); 2749 igb->num_rx_groups = 1; 2750 } 2751 } 2752 2753 /* 2754 * Check the divisibility between rx rings and rx groups. 2755 */ 2756 for (i = igb->num_rx_groups; i > 0; i--) { 2757 if ((igb->num_rx_rings % i) == 0) 2758 break; 2759 } 2760 if (i != igb->num_rx_groups) { 2761 igb_error(igb, 2762 "Invalid rx groups number. Downgrade the rx group " 2763 "number to %d.", i); 2764 igb->num_rx_groups = i; 2765 } 2766 2767 /* 2768 * Get the ring number per group. 2769 */ 2770 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2771 2772 if (igb->num_rx_groups == 1) { 2773 /* 2774 * One rx ring group, the rx ring number is num_rx_rings. 2775 */ 2776 igb->vmdq_mode = E1000_VMDQ_OFF; 2777 } else if (ring_per_group == 1) { 2778 /* 2779 * Multiple rx groups, each group has one rx ring. 2780 */ 2781 igb->vmdq_mode = E1000_VMDQ_MAC; 2782 } else { 2783 /* 2784 * Multiple groups and multiple rings. 2785 */ 2786 igb->vmdq_mode = E1000_VMDQ_MAC_RSS; 2787 } 2788 2789 /* 2790 * Tunable used to force an interrupt type. The only use is 2791 * for testing of the lesser interrupt types. 2792 * 0 = don't force interrupt type 2793 * 1 = force interrupt type MSIX 2794 * 2 = force interrupt type MSI 2795 * 3 = force interrupt type Legacy 2796 */ 2797 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2798 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2799 2800 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2801 0, 1, 1); 2802 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2803 0, 1, 1); 2804 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2805 0, 1, 1); 2806 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2807 0, 1, 1); 2808 2809 /* 2810 * igb LSO needs the tx h/w checksum support. 2811 * Here LSO will be disabled if tx h/w checksum has been disabled. 2812 */ 2813 if (igb->tx_hcksum_enable == B_FALSE) 2814 igb->lso_enable = B_FALSE; 2815 2816 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2817 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2818 DEFAULT_TX_COPY_THRESHOLD); 2819 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2820 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2821 DEFAULT_TX_RECYCLE_THRESHOLD); 2822 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2823 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2824 DEFAULT_TX_OVERLOAD_THRESHOLD); 2825 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2826 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2827 DEFAULT_TX_RESCHED_THRESHOLD); 2828 2829 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2830 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2831 DEFAULT_RX_COPY_THRESHOLD); 2832 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2833 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2834 DEFAULT_RX_LIMIT_PER_INTR); 2835 2836 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2837 igb->capab->min_intr_throttle, 2838 igb->capab->max_intr_throttle, 2839 igb->capab->def_intr_throttle); 2840 2841 /* 2842 * Max number of multicast addresses 2843 */ 2844 igb->mcast_max_num = 2845 igb_get_prop(igb, PROP_MCAST_MAX_NUM, 2846 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM); 2847 } 2848 2849 /* 2850 * igb_get_prop - Get a property value out of the configuration file igb.conf 2851 * 2852 * Caller provides the name of the property, a default value, a minimum 2853 * value, and a maximum value. 2854 * 2855 * Return configured value of the property, with default, minimum and 2856 * maximum properly applied. 2857 */ 2858 static int 2859 igb_get_prop(igb_t *igb, 2860 char *propname, /* name of the property */ 2861 int minval, /* minimum acceptable value */ 2862 int maxval, /* maximim acceptable value */ 2863 int defval) /* default value */ 2864 { 2865 int value; 2866 2867 /* 2868 * Call ddi_prop_get_int() to read the conf settings 2869 */ 2870 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2871 DDI_PROP_DONTPASS, propname, defval); 2872 2873 if (value > maxval) 2874 value = maxval; 2875 2876 if (value < minval) 2877 value = minval; 2878 2879 return (value); 2880 } 2881 2882 /* 2883 * igb_setup_link - Using the link properties to setup the link 2884 */ 2885 int 2886 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2887 { 2888 struct e1000_mac_info *mac; 2889 struct e1000_phy_info *phy; 2890 boolean_t invalid; 2891 2892 mac = &igb->hw.mac; 2893 phy = &igb->hw.phy; 2894 invalid = B_FALSE; 2895 2896 if (igb->param_adv_autoneg_cap == 1) { 2897 mac->autoneg = B_TRUE; 2898 phy->autoneg_advertised = 0; 2899 2900 /* 2901 * 1000hdx is not supported for autonegotiation 2902 */ 2903 if (igb->param_adv_1000fdx_cap == 1) 2904 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2905 2906 if (igb->param_adv_100fdx_cap == 1) 2907 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2908 2909 if (igb->param_adv_100hdx_cap == 1) 2910 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2911 2912 if (igb->param_adv_10fdx_cap == 1) 2913 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2914 2915 if (igb->param_adv_10hdx_cap == 1) 2916 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2917 2918 if (phy->autoneg_advertised == 0) 2919 invalid = B_TRUE; 2920 } else { 2921 mac->autoneg = B_FALSE; 2922 2923 /* 2924 * 1000fdx and 1000hdx are not supported for forced link 2925 */ 2926 if (igb->param_adv_100fdx_cap == 1) 2927 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2928 else if (igb->param_adv_100hdx_cap == 1) 2929 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2930 else if (igb->param_adv_10fdx_cap == 1) 2931 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2932 else if (igb->param_adv_10hdx_cap == 1) 2933 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2934 else 2935 invalid = B_TRUE; 2936 } 2937 2938 if (invalid) { 2939 igb_notice(igb, "Invalid link settings. Setup link to " 2940 "autonegotiation with full link capabilities."); 2941 mac->autoneg = B_TRUE; 2942 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2943 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2944 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2945 } 2946 2947 if (setup_hw) { 2948 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2949 return (IGB_FAILURE); 2950 } 2951 2952 return (IGB_SUCCESS); 2953 } 2954 2955 2956 /* 2957 * igb_is_link_up - Check if the link is up 2958 */ 2959 static boolean_t 2960 igb_is_link_up(igb_t *igb) 2961 { 2962 struct e1000_hw *hw = &igb->hw; 2963 boolean_t link_up = B_FALSE; 2964 2965 ASSERT(mutex_owned(&igb->gen_lock)); 2966 2967 /* 2968 * get_link_status is set in the interrupt handler on link-status-change 2969 * or rx sequence error interrupt. get_link_status will stay 2970 * false until the e1000_check_for_link establishes link only 2971 * for copper adapters. 2972 */ 2973 switch (hw->phy.media_type) { 2974 case e1000_media_type_copper: 2975 if (hw->mac.get_link_status) { 2976 (void) e1000_check_for_link(hw); 2977 link_up = !hw->mac.get_link_status; 2978 } else { 2979 link_up = B_TRUE; 2980 } 2981 break; 2982 case e1000_media_type_fiber: 2983 (void) e1000_check_for_link(hw); 2984 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2985 break; 2986 case e1000_media_type_internal_serdes: 2987 (void) e1000_check_for_link(hw); 2988 link_up = hw->mac.serdes_has_link; 2989 break; 2990 } 2991 2992 return (link_up); 2993 } 2994 2995 /* 2996 * igb_link_check - Link status processing 2997 */ 2998 static boolean_t 2999 igb_link_check(igb_t *igb) 3000 { 3001 struct e1000_hw *hw = &igb->hw; 3002 uint16_t speed = 0, duplex = 0; 3003 boolean_t link_changed = B_FALSE; 3004 3005 ASSERT(mutex_owned(&igb->gen_lock)); 3006 3007 if (igb_is_link_up(igb)) { 3008 /* 3009 * The Link is up, check whether it was marked as down earlier 3010 */ 3011 if (igb->link_state != LINK_STATE_UP) { 3012 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3013 igb->link_speed = speed; 3014 igb->link_duplex = duplex; 3015 igb->link_state = LINK_STATE_UP; 3016 link_changed = B_TRUE; 3017 if (!igb->link_complete) 3018 igb_stop_link_timer(igb); 3019 } 3020 } else if (igb->link_complete) { 3021 if (igb->link_state != LINK_STATE_DOWN) { 3022 igb->link_speed = 0; 3023 igb->link_duplex = 0; 3024 igb->link_state = LINK_STATE_DOWN; 3025 link_changed = B_TRUE; 3026 } 3027 } 3028 3029 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3030 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3031 return (B_FALSE); 3032 } 3033 3034 return (link_changed); 3035 } 3036 3037 /* 3038 * igb_local_timer - driver watchdog function 3039 * 3040 * This function will handle the hardware stall check, link status 3041 * check and other routines. 3042 */ 3043 static void 3044 igb_local_timer(void *arg) 3045 { 3046 igb_t *igb = (igb_t *)arg; 3047 boolean_t link_changed = B_FALSE; 3048 3049 if (igb->igb_state & IGB_ERROR) { 3050 igb->reset_count++; 3051 if (igb_reset(igb) == IGB_SUCCESS) 3052 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED); 3053 3054 igb_restart_watchdog_timer(igb); 3055 return; 3056 } 3057 3058 if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) { 3059 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 3060 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 3061 igb->reset_count++; 3062 if (igb_reset(igb) == IGB_SUCCESS) 3063 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED); 3064 3065 igb_restart_watchdog_timer(igb); 3066 return; 3067 } 3068 3069 mutex_enter(&igb->gen_lock); 3070 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED)) 3071 link_changed = igb_link_check(igb); 3072 mutex_exit(&igb->gen_lock); 3073 3074 if (link_changed) 3075 mac_link_update(igb->mac_hdl, igb->link_state); 3076 3077 igb_restart_watchdog_timer(igb); 3078 } 3079 3080 /* 3081 * igb_link_timer - link setup timer function 3082 * 3083 * It is called when the timer for link setup is expired, which indicates 3084 * the completion of the link setup. The link state will not be updated 3085 * until the link setup is completed. And the link state will not be sent 3086 * to the upper layer through mac_link_update() in this function. It will 3087 * be updated in the local timer routine or the interrupts service routine 3088 * after the interface is started (plumbed). 3089 */ 3090 static void 3091 igb_link_timer(void *arg) 3092 { 3093 igb_t *igb = (igb_t *)arg; 3094 3095 mutex_enter(&igb->link_lock); 3096 igb->link_complete = B_TRUE; 3097 igb->link_tid = 0; 3098 mutex_exit(&igb->link_lock); 3099 } 3100 /* 3101 * igb_stall_check - check for transmit stall 3102 * 3103 * This function checks if the adapter is stalled (in transmit). 3104 * 3105 * It is called each time the watchdog timeout is invoked. 3106 * If the transmit descriptor reclaim continuously fails, 3107 * the watchdog value will increment by 1. If the watchdog 3108 * value exceeds the threshold, the igb is assumed to 3109 * have stalled and need to be reset. 3110 */ 3111 static boolean_t 3112 igb_stall_check(igb_t *igb) 3113 { 3114 igb_tx_ring_t *tx_ring; 3115 struct e1000_hw *hw = &igb->hw; 3116 boolean_t result; 3117 int i; 3118 3119 if (igb->link_state != LINK_STATE_UP) 3120 return (B_FALSE); 3121 3122 /* 3123 * If any tx ring is stalled, we'll reset the chipset 3124 */ 3125 result = B_FALSE; 3126 for (i = 0; i < igb->num_tx_rings; i++) { 3127 tx_ring = &igb->tx_rings[i]; 3128 3129 if (tx_ring->recycle_fail > 0) 3130 tx_ring->stall_watchdog++; 3131 else 3132 tx_ring->stall_watchdog = 0; 3133 3134 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 3135 result = B_TRUE; 3136 if (hw->mac.type == e1000_82580) { 3137 hw->dev_spec._82575.global_device_reset 3138 = B_TRUE; 3139 } 3140 break; 3141 } 3142 } 3143 3144 if (result) { 3145 tx_ring->stall_watchdog = 0; 3146 tx_ring->recycle_fail = 0; 3147 } 3148 3149 return (result); 3150 } 3151 3152 3153 /* 3154 * is_valid_mac_addr - Check if the mac address is valid 3155 */ 3156 static boolean_t 3157 is_valid_mac_addr(uint8_t *mac_addr) 3158 { 3159 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3160 const uint8_t addr_test2[6] = 3161 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3162 3163 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3164 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3165 return (B_FALSE); 3166 3167 return (B_TRUE); 3168 } 3169 3170 static boolean_t 3171 igb_find_mac_address(igb_t *igb) 3172 { 3173 struct e1000_hw *hw = &igb->hw; 3174 #ifdef __sparc 3175 uchar_t *bytes; 3176 struct ether_addr sysaddr; 3177 uint_t nelts; 3178 int err; 3179 boolean_t found = B_FALSE; 3180 3181 /* 3182 * The "vendor's factory-set address" may already have 3183 * been extracted from the chip, but if the property 3184 * "local-mac-address" is set we use that instead. 3185 * 3186 * We check whether it looks like an array of 6 3187 * bytes (which it should, if OBP set it). If we can't 3188 * make sense of it this way, we'll ignore it. 3189 */ 3190 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3191 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3192 if (err == DDI_PROP_SUCCESS) { 3193 if (nelts == ETHERADDRL) { 3194 while (nelts--) 3195 hw->mac.addr[nelts] = bytes[nelts]; 3196 found = B_TRUE; 3197 } 3198 ddi_prop_free(bytes); 3199 } 3200 3201 /* 3202 * Look up the OBP property "local-mac-address?". If the user has set 3203 * 'local-mac-address? = false', use "the system address" instead. 3204 */ 3205 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 3206 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3207 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3208 if (localetheraddr(NULL, &sysaddr) != 0) { 3209 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 3210 found = B_TRUE; 3211 } 3212 } 3213 ddi_prop_free(bytes); 3214 } 3215 3216 /* 3217 * Finally(!), if there's a valid "mac-address" property (created 3218 * if we netbooted from this interface), we must use this instead 3219 * of any of the above to ensure that the NFS/install server doesn't 3220 * get confused by the address changing as Solaris takes over! 3221 */ 3222 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3223 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3224 if (err == DDI_PROP_SUCCESS) { 3225 if (nelts == ETHERADDRL) { 3226 while (nelts--) 3227 hw->mac.addr[nelts] = bytes[nelts]; 3228 found = B_TRUE; 3229 } 3230 ddi_prop_free(bytes); 3231 } 3232 3233 if (found) { 3234 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 3235 return (B_TRUE); 3236 } 3237 #endif 3238 3239 /* 3240 * Read the device MAC address from the EEPROM 3241 */ 3242 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 3243 return (B_FALSE); 3244 3245 return (B_TRUE); 3246 } 3247 3248 #pragma inline(igb_arm_watchdog_timer) 3249 3250 static void 3251 igb_arm_watchdog_timer(igb_t *igb) 3252 { 3253 /* 3254 * Fire a watchdog timer 3255 */ 3256 igb->watchdog_tid = 3257 timeout(igb_local_timer, 3258 (void *)igb, 1 * drv_usectohz(1000000)); 3259 3260 } 3261 3262 /* 3263 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 3264 */ 3265 void 3266 igb_enable_watchdog_timer(igb_t *igb) 3267 { 3268 mutex_enter(&igb->watchdog_lock); 3269 3270 if (!igb->watchdog_enable) { 3271 igb->watchdog_enable = B_TRUE; 3272 igb->watchdog_start = B_TRUE; 3273 igb_arm_watchdog_timer(igb); 3274 } 3275 3276 mutex_exit(&igb->watchdog_lock); 3277 3278 } 3279 3280 /* 3281 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 3282 */ 3283 void 3284 igb_disable_watchdog_timer(igb_t *igb) 3285 { 3286 timeout_id_t tid; 3287 3288 mutex_enter(&igb->watchdog_lock); 3289 3290 igb->watchdog_enable = B_FALSE; 3291 igb->watchdog_start = B_FALSE; 3292 tid = igb->watchdog_tid; 3293 igb->watchdog_tid = 0; 3294 3295 mutex_exit(&igb->watchdog_lock); 3296 3297 if (tid != 0) 3298 (void) untimeout(tid); 3299 3300 } 3301 3302 /* 3303 * igb_start_watchdog_timer - Start the driver watchdog timer 3304 */ 3305 static void 3306 igb_start_watchdog_timer(igb_t *igb) 3307 { 3308 mutex_enter(&igb->watchdog_lock); 3309 3310 if (igb->watchdog_enable) { 3311 if (!igb->watchdog_start) { 3312 igb->watchdog_start = B_TRUE; 3313 igb_arm_watchdog_timer(igb); 3314 } 3315 } 3316 3317 mutex_exit(&igb->watchdog_lock); 3318 } 3319 3320 /* 3321 * igb_restart_watchdog_timer - Restart the driver watchdog timer 3322 */ 3323 static void 3324 igb_restart_watchdog_timer(igb_t *igb) 3325 { 3326 mutex_enter(&igb->watchdog_lock); 3327 3328 if (igb->watchdog_start) 3329 igb_arm_watchdog_timer(igb); 3330 3331 mutex_exit(&igb->watchdog_lock); 3332 } 3333 3334 /* 3335 * igb_stop_watchdog_timer - Stop the driver watchdog timer 3336 */ 3337 static void 3338 igb_stop_watchdog_timer(igb_t *igb) 3339 { 3340 timeout_id_t tid; 3341 3342 mutex_enter(&igb->watchdog_lock); 3343 3344 igb->watchdog_start = B_FALSE; 3345 tid = igb->watchdog_tid; 3346 igb->watchdog_tid = 0; 3347 3348 mutex_exit(&igb->watchdog_lock); 3349 3350 if (tid != 0) 3351 (void) untimeout(tid); 3352 } 3353 3354 /* 3355 * igb_start_link_timer - Start the link setup timer 3356 */ 3357 static void 3358 igb_start_link_timer(struct igb *igb) 3359 { 3360 struct e1000_hw *hw = &igb->hw; 3361 clock_t link_timeout; 3362 3363 if (hw->mac.autoneg) 3364 link_timeout = PHY_AUTO_NEG_LIMIT * 3365 drv_usectohz(100000); 3366 else 3367 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 3368 3369 mutex_enter(&igb->link_lock); 3370 if (hw->phy.autoneg_wait_to_complete) { 3371 igb->link_complete = B_TRUE; 3372 } else { 3373 igb->link_complete = B_FALSE; 3374 igb->link_tid = timeout(igb_link_timer, (void *)igb, 3375 link_timeout); 3376 } 3377 mutex_exit(&igb->link_lock); 3378 } 3379 3380 /* 3381 * igb_stop_link_timer - Stop the link setup timer 3382 */ 3383 static void 3384 igb_stop_link_timer(struct igb *igb) 3385 { 3386 timeout_id_t tid; 3387 3388 mutex_enter(&igb->link_lock); 3389 igb->link_complete = B_TRUE; 3390 tid = igb->link_tid; 3391 igb->link_tid = 0; 3392 mutex_exit(&igb->link_lock); 3393 3394 if (tid != 0) 3395 (void) untimeout(tid); 3396 } 3397 3398 /* 3399 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 3400 */ 3401 static void 3402 igb_disable_adapter_interrupts(igb_t *igb) 3403 { 3404 struct e1000_hw *hw = &igb->hw; 3405 3406 /* 3407 * Set the IMC register to mask all the interrupts, 3408 * including the tx interrupts. 3409 */ 3410 E1000_WRITE_REG(hw, E1000_IMC, ~0); 3411 E1000_WRITE_REG(hw, E1000_IAM, 0); 3412 3413 /* 3414 * Additional disabling for MSI-X 3415 */ 3416 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3417 E1000_WRITE_REG(hw, E1000_EIMC, ~0); 3418 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3419 E1000_WRITE_REG(hw, E1000_EIAM, 0); 3420 } 3421 3422 E1000_WRITE_FLUSH(hw); 3423 } 3424 3425 /* 3426 * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580 3427 */ 3428 static void 3429 igb_enable_adapter_interrupts_82580(igb_t *igb) 3430 { 3431 struct e1000_hw *hw = &igb->hw; 3432 3433 /* Clear any pending interrupts */ 3434 (void) E1000_READ_REG(hw, E1000_ICR); 3435 igb->ims_mask |= E1000_IMS_DRSTA; 3436 3437 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3438 3439 /* Interrupt enabling for MSI-X */ 3440 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3441 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3442 igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA); 3443 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask); 3444 } else { /* Interrupt enabling for MSI and legacy */ 3445 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3446 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3447 igb->ims_mask |= E1000_IMS_DRSTA; 3448 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask); 3449 } 3450 3451 /* Disable auto-mask for ICR interrupt bits */ 3452 E1000_WRITE_REG(hw, E1000_IAM, 0); 3453 3454 E1000_WRITE_FLUSH(hw); 3455 } 3456 3457 /* 3458 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576 3459 */ 3460 static void 3461 igb_enable_adapter_interrupts_82576(igb_t *igb) 3462 { 3463 struct e1000_hw *hw = &igb->hw; 3464 3465 /* Clear any pending interrupts */ 3466 (void) E1000_READ_REG(hw, E1000_ICR); 3467 3468 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3469 3470 /* Interrupt enabling for MSI-X */ 3471 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3472 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3473 igb->ims_mask = E1000_IMS_LSC; 3474 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3475 } else { 3476 /* Interrupt enabling for MSI and legacy */ 3477 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3478 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3479 E1000_WRITE_REG(hw, E1000_IMS, 3480 (IMS_ENABLE_MASK | E1000_IMS_TXQE)); 3481 } 3482 3483 /* Disable auto-mask for ICR interrupt bits */ 3484 E1000_WRITE_REG(hw, E1000_IAM, 0); 3485 3486 E1000_WRITE_FLUSH(hw); 3487 } 3488 3489 /* 3490 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575 3491 */ 3492 static void 3493 igb_enable_adapter_interrupts_82575(igb_t *igb) 3494 { 3495 struct e1000_hw *hw = &igb->hw; 3496 uint32_t reg; 3497 3498 /* Clear any pending interrupts */ 3499 (void) E1000_READ_REG(hw, E1000_ICR); 3500 3501 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3502 /* Interrupt enabling for MSI-X */ 3503 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3504 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3505 igb->ims_mask = E1000_IMS_LSC; 3506 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3507 3508 /* Enable MSI-X PBA support */ 3509 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3510 reg |= E1000_CTRL_EXT_PBA_CLR; 3511 3512 /* Non-selective interrupt clear-on-read */ 3513 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 3514 3515 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3516 } else { 3517 /* Interrupt enabling for MSI and legacy */ 3518 igb->ims_mask = IMS_ENABLE_MASK; 3519 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3520 } 3521 3522 E1000_WRITE_FLUSH(hw); 3523 } 3524 3525 /* 3526 * Loopback Support 3527 */ 3528 static lb_property_t lb_normal = 3529 { normal, "normal", IGB_LB_NONE }; 3530 static lb_property_t lb_external = 3531 { external, "External", IGB_LB_EXTERNAL }; 3532 static lb_property_t lb_phy = 3533 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 3534 static lb_property_t lb_serdes = 3535 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 3536 3537 enum ioc_reply 3538 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 3539 { 3540 lb_info_sz_t *lbsp; 3541 lb_property_t *lbpp; 3542 struct e1000_hw *hw; 3543 uint32_t *lbmp; 3544 uint32_t size; 3545 uint32_t value; 3546 3547 hw = &igb->hw; 3548 3549 if (mp->b_cont == NULL) 3550 return (IOC_INVAL); 3551 3552 switch (iocp->ioc_cmd) { 3553 default: 3554 return (IOC_INVAL); 3555 3556 case LB_GET_INFO_SIZE: 3557 size = sizeof (lb_info_sz_t); 3558 if (iocp->ioc_count != size) 3559 return (IOC_INVAL); 3560 3561 value = sizeof (lb_normal); 3562 if (hw->phy.media_type == e1000_media_type_copper) 3563 value += sizeof (lb_phy); 3564 else 3565 value += sizeof (lb_serdes); 3566 value += sizeof (lb_external); 3567 3568 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 3569 *lbsp = value; 3570 break; 3571 3572 case LB_GET_INFO: 3573 value = sizeof (lb_normal); 3574 if (hw->phy.media_type == e1000_media_type_copper) 3575 value += sizeof (lb_phy); 3576 else 3577 value += sizeof (lb_serdes); 3578 value += sizeof (lb_external); 3579 3580 size = value; 3581 if (iocp->ioc_count != size) 3582 return (IOC_INVAL); 3583 3584 value = 0; 3585 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 3586 3587 lbpp[value++] = lb_normal; 3588 if (hw->phy.media_type == e1000_media_type_copper) 3589 lbpp[value++] = lb_phy; 3590 else 3591 lbpp[value++] = lb_serdes; 3592 lbpp[value++] = lb_external; 3593 break; 3594 3595 case LB_GET_MODE: 3596 size = sizeof (uint32_t); 3597 if (iocp->ioc_count != size) 3598 return (IOC_INVAL); 3599 3600 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3601 *lbmp = igb->loopback_mode; 3602 break; 3603 3604 case LB_SET_MODE: 3605 size = 0; 3606 if (iocp->ioc_count != sizeof (uint32_t)) 3607 return (IOC_INVAL); 3608 3609 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3610 if (!igb_set_loopback_mode(igb, *lbmp)) 3611 return (IOC_INVAL); 3612 break; 3613 } 3614 3615 iocp->ioc_count = size; 3616 iocp->ioc_error = 0; 3617 3618 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3619 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3620 return (IOC_INVAL); 3621 } 3622 3623 return (IOC_REPLY); 3624 } 3625 3626 /* 3627 * igb_set_loopback_mode - Setup loopback based on the loopback mode 3628 */ 3629 static boolean_t 3630 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 3631 { 3632 struct e1000_hw *hw; 3633 int i; 3634 3635 if (mode == igb->loopback_mode) 3636 return (B_TRUE); 3637 3638 hw = &igb->hw; 3639 3640 igb->loopback_mode = mode; 3641 3642 if (mode == IGB_LB_NONE) { 3643 /* Reset the chip */ 3644 hw->phy.autoneg_wait_to_complete = B_TRUE; 3645 (void) igb_reset(igb); 3646 hw->phy.autoneg_wait_to_complete = B_FALSE; 3647 return (B_TRUE); 3648 } 3649 3650 mutex_enter(&igb->gen_lock); 3651 3652 switch (mode) { 3653 default: 3654 mutex_exit(&igb->gen_lock); 3655 return (B_FALSE); 3656 3657 case IGB_LB_EXTERNAL: 3658 igb_set_external_loopback(igb); 3659 break; 3660 3661 case IGB_LB_INTERNAL_PHY: 3662 igb_set_internal_phy_loopback(igb); 3663 break; 3664 3665 case IGB_LB_INTERNAL_SERDES: 3666 igb_set_internal_serdes_loopback(igb); 3667 break; 3668 } 3669 3670 mutex_exit(&igb->gen_lock); 3671 3672 /* 3673 * When external loopback is set, wait up to 1000ms to get the link up. 3674 * According to test, 1000ms can work and it's an experimental value. 3675 */ 3676 if (mode == IGB_LB_EXTERNAL) { 3677 for (i = 0; i <= 10; i++) { 3678 mutex_enter(&igb->gen_lock); 3679 (void) igb_link_check(igb); 3680 mutex_exit(&igb->gen_lock); 3681 3682 if (igb->link_state == LINK_STATE_UP) 3683 break; 3684 3685 msec_delay(100); 3686 } 3687 3688 if (igb->link_state != LINK_STATE_UP) { 3689 /* 3690 * Does not support external loopback. 3691 * Reset driver to loopback none. 3692 */ 3693 igb->loopback_mode = IGB_LB_NONE; 3694 3695 /* Reset the chip */ 3696 hw->phy.autoneg_wait_to_complete = B_TRUE; 3697 (void) igb_reset(igb); 3698 hw->phy.autoneg_wait_to_complete = B_FALSE; 3699 3700 IGB_DEBUGLOG_0(igb, "Set external loopback failed, " 3701 "reset to loopback none."); 3702 3703 return (B_FALSE); 3704 } 3705 } 3706 3707 return (B_TRUE); 3708 } 3709 3710 /* 3711 * igb_set_external_loopback - Set the external loopback mode 3712 */ 3713 static void 3714 igb_set_external_loopback(igb_t *igb) 3715 { 3716 struct e1000_hw *hw; 3717 3718 hw = &igb->hw; 3719 3720 /* Set phy to known state */ 3721 (void) e1000_phy_hw_reset(hw); 3722 3723 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3724 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 3725 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3726 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3727 } 3728 3729 /* 3730 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3731 */ 3732 static void 3733 igb_set_internal_phy_loopback(igb_t *igb) 3734 { 3735 struct e1000_hw *hw; 3736 uint32_t ctrl_ext; 3737 uint16_t phy_ctrl; 3738 uint16_t phy_pconf; 3739 3740 hw = &igb->hw; 3741 3742 /* Set link mode to PHY (00b) in the Extended Control register */ 3743 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3744 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3745 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3746 3747 /* 3748 * Set PHY control register (0x4140): 3749 * Set full duplex mode 3750 * Set loopback bit 3751 * Clear auto-neg enable bit 3752 * Set PHY speed 3753 */ 3754 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3755 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3756 3757 /* Set the link disable bit in the Port Configuration register */ 3758 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3759 phy_pconf |= (uint16_t)1 << 14; 3760 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3761 } 3762 3763 /* 3764 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3765 */ 3766 static void 3767 igb_set_internal_serdes_loopback(igb_t *igb) 3768 { 3769 struct e1000_hw *hw; 3770 uint32_t ctrl_ext; 3771 uint32_t ctrl; 3772 uint32_t pcs_lctl; 3773 uint32_t connsw; 3774 3775 hw = &igb->hw; 3776 3777 /* Set link mode to SerDes (11b) in the Extended Control register */ 3778 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3779 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3780 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3781 3782 /* Configure the SerDes to loopback */ 3783 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3784 3785 /* Set Device Control register */ 3786 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3787 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3788 E1000_CTRL_SLU); /* Force link up */ 3789 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3790 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3791 E1000_CTRL_LRST); /* Clear link reset */ 3792 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3793 3794 /* Set PCS Link Control register */ 3795 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3796 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3797 E1000_PCS_LCTL_FSD | 3798 E1000_PCS_LCTL_FDV_FULL | 3799 E1000_PCS_LCTL_FLV_LINK_UP); 3800 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3801 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3802 3803 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3804 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3805 connsw &= ~E1000_CONNSW_ENRGSRC; 3806 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3807 } 3808 3809 #pragma inline(igb_intr_rx_work) 3810 /* 3811 * igb_intr_rx_work - rx processing of ISR 3812 */ 3813 static void 3814 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3815 { 3816 mblk_t *mp; 3817 3818 mutex_enter(&rx_ring->rx_lock); 3819 mp = igb_rx(rx_ring, IGB_NO_POLL); 3820 mutex_exit(&rx_ring->rx_lock); 3821 3822 if (mp != NULL) 3823 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp, 3824 rx_ring->ring_gen_num); 3825 } 3826 3827 #pragma inline(igb_intr_tx_work) 3828 /* 3829 * igb_intr_tx_work - tx processing of ISR 3830 */ 3831 static void 3832 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3833 { 3834 igb_t *igb = tx_ring->igb; 3835 3836 /* Recycle the tx descriptors */ 3837 tx_ring->tx_recycle(tx_ring); 3838 3839 /* Schedule the re-transmit */ 3840 if (tx_ring->reschedule && 3841 (tx_ring->tbd_free >= igb->tx_resched_thresh)) { 3842 tx_ring->reschedule = B_FALSE; 3843 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle); 3844 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3845 } 3846 } 3847 3848 #pragma inline(igb_intr_link_work) 3849 /* 3850 * igb_intr_link_work - link-status-change processing of ISR 3851 */ 3852 static void 3853 igb_intr_link_work(igb_t *igb) 3854 { 3855 boolean_t link_changed; 3856 3857 igb_stop_watchdog_timer(igb); 3858 3859 mutex_enter(&igb->gen_lock); 3860 3861 /* 3862 * Because we got a link-status-change interrupt, force 3863 * e1000_check_for_link() to look at phy 3864 */ 3865 igb->hw.mac.get_link_status = B_TRUE; 3866 3867 /* igb_link_check takes care of link status change */ 3868 link_changed = igb_link_check(igb); 3869 3870 /* Get new phy state */ 3871 igb_get_phy_state(igb); 3872 3873 mutex_exit(&igb->gen_lock); 3874 3875 if (link_changed) 3876 mac_link_update(igb->mac_hdl, igb->link_state); 3877 3878 igb_start_watchdog_timer(igb); 3879 } 3880 3881 /* 3882 * igb_intr_legacy - Interrupt handler for legacy interrupts 3883 */ 3884 static uint_t 3885 igb_intr_legacy(void *arg1, void *arg2) 3886 { 3887 igb_t *igb = (igb_t *)arg1; 3888 igb_tx_ring_t *tx_ring; 3889 uint32_t icr; 3890 mblk_t *mp; 3891 boolean_t tx_reschedule; 3892 boolean_t link_changed; 3893 uint_t result; 3894 3895 _NOTE(ARGUNUSED(arg2)); 3896 3897 mutex_enter(&igb->gen_lock); 3898 3899 if (igb->igb_state & IGB_SUSPENDED) { 3900 mutex_exit(&igb->gen_lock); 3901 return (DDI_INTR_UNCLAIMED); 3902 } 3903 3904 mp = NULL; 3905 tx_reschedule = B_FALSE; 3906 link_changed = B_FALSE; 3907 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3908 3909 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3910 mutex_exit(&igb->gen_lock); 3911 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3912 atomic_or_32(&igb->igb_state, IGB_ERROR); 3913 return (DDI_INTR_UNCLAIMED); 3914 } 3915 3916 if (icr & E1000_ICR_INT_ASSERTED) { 3917 /* 3918 * E1000_ICR_INT_ASSERTED bit was set: 3919 * Read(Clear) the ICR, claim this interrupt, 3920 * look for work to do. 3921 */ 3922 ASSERT(igb->num_rx_rings == 1); 3923 ASSERT(igb->num_tx_rings == 1); 3924 3925 /* Make sure all interrupt causes cleared */ 3926 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 3927 3928 if (icr & E1000_ICR_RXT0) { 3929 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL); 3930 } 3931 3932 if (icr & E1000_ICR_TXDW) { 3933 tx_ring = &igb->tx_rings[0]; 3934 3935 /* Recycle the tx descriptors */ 3936 tx_ring->tx_recycle(tx_ring); 3937 3938 /* Schedule the re-transmit */ 3939 tx_reschedule = (tx_ring->reschedule && 3940 (tx_ring->tbd_free >= igb->tx_resched_thresh)); 3941 } 3942 3943 if (icr & E1000_ICR_LSC) { 3944 /* 3945 * Because we got a link-status-change interrupt, force 3946 * e1000_check_for_link() to look at phy 3947 */ 3948 igb->hw.mac.get_link_status = B_TRUE; 3949 3950 /* igb_link_check takes care of link status change */ 3951 link_changed = igb_link_check(igb); 3952 3953 /* Get new phy state */ 3954 igb_get_phy_state(igb); 3955 } 3956 3957 if (icr & E1000_ICR_DRSTA) { 3958 /* 82580 Full Device Reset needed */ 3959 atomic_or_32(&igb->igb_state, IGB_STALL); 3960 } 3961 3962 result = DDI_INTR_CLAIMED; 3963 } else { 3964 /* 3965 * E1000_ICR_INT_ASSERTED bit was not set: 3966 * Don't claim this interrupt. 3967 */ 3968 result = DDI_INTR_UNCLAIMED; 3969 } 3970 3971 mutex_exit(&igb->gen_lock); 3972 3973 /* 3974 * Do the following work outside of the gen_lock 3975 */ 3976 if (mp != NULL) 3977 mac_rx(igb->mac_hdl, NULL, mp); 3978 3979 if (tx_reschedule) { 3980 tx_ring->reschedule = B_FALSE; 3981 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle); 3982 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3983 } 3984 3985 if (link_changed) 3986 mac_link_update(igb->mac_hdl, igb->link_state); 3987 3988 return (result); 3989 } 3990 3991 /* 3992 * igb_intr_msi - Interrupt handler for MSI 3993 */ 3994 static uint_t 3995 igb_intr_msi(void *arg1, void *arg2) 3996 { 3997 igb_t *igb = (igb_t *)arg1; 3998 uint32_t icr; 3999 4000 _NOTE(ARGUNUSED(arg2)); 4001 4002 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4003 4004 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4005 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4006 atomic_or_32(&igb->igb_state, IGB_ERROR); 4007 return (DDI_INTR_CLAIMED); 4008 } 4009 4010 /* Make sure all interrupt causes cleared */ 4011 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 4012 4013 /* 4014 * For MSI interrupt, we have only one vector, 4015 * so we have only one rx ring and one tx ring enabled. 4016 */ 4017 ASSERT(igb->num_rx_rings == 1); 4018 ASSERT(igb->num_tx_rings == 1); 4019 4020 if (icr & E1000_ICR_RXT0) { 4021 igb_intr_rx_work(&igb->rx_rings[0]); 4022 } 4023 4024 if (icr & E1000_ICR_TXDW) { 4025 igb_intr_tx_work(&igb->tx_rings[0]); 4026 } 4027 4028 if (icr & E1000_ICR_LSC) { 4029 igb_intr_link_work(igb); 4030 } 4031 4032 if (icr & E1000_ICR_DRSTA) { 4033 /* 82580 Full Device Reset needed */ 4034 atomic_or_32(&igb->igb_state, IGB_STALL); 4035 } 4036 4037 return (DDI_INTR_CLAIMED); 4038 } 4039 4040 /* 4041 * igb_intr_rx - Interrupt handler for rx 4042 */ 4043 static uint_t 4044 igb_intr_rx(void *arg1, void *arg2) 4045 { 4046 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 4047 4048 _NOTE(ARGUNUSED(arg2)); 4049 4050 /* 4051 * Only used via MSI-X vector so don't check cause bits 4052 * and only clean the given ring. 4053 */ 4054 igb_intr_rx_work(rx_ring); 4055 4056 return (DDI_INTR_CLAIMED); 4057 } 4058 4059 /* 4060 * igb_intr_tx - Interrupt handler for tx 4061 */ 4062 static uint_t 4063 igb_intr_tx(void *arg1, void *arg2) 4064 { 4065 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1; 4066 4067 _NOTE(ARGUNUSED(arg2)); 4068 4069 /* 4070 * Only used via MSI-X vector so don't check cause bits 4071 * and only clean the given ring. 4072 */ 4073 igb_intr_tx_work(tx_ring); 4074 4075 return (DDI_INTR_CLAIMED); 4076 } 4077 4078 /* 4079 * igb_intr_tx_other - Interrupt handler for both tx and other 4080 * 4081 */ 4082 static uint_t 4083 igb_intr_tx_other(void *arg1, void *arg2) 4084 { 4085 igb_t *igb = (igb_t *)arg1; 4086 uint32_t icr; 4087 4088 _NOTE(ARGUNUSED(arg2)); 4089 4090 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4091 4092 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4093 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4094 atomic_or_32(&igb->igb_state, IGB_ERROR); 4095 return (DDI_INTR_CLAIMED); 4096 } 4097 4098 /* 4099 * Look for tx reclaiming work first. Remember, in the 4100 * case of only interrupt sharing, only one tx ring is 4101 * used 4102 */ 4103 igb_intr_tx_work(&igb->tx_rings[0]); 4104 4105 /* 4106 * Check for "other" causes. 4107 */ 4108 if (icr & E1000_ICR_LSC) { 4109 igb_intr_link_work(igb); 4110 } 4111 4112 /* 4113 * The DOUTSYNC bit indicates a tx packet dropped because 4114 * DMA engine gets "out of sync". There isn't a real fix 4115 * for this. The Intel recommendation is to count the number 4116 * of occurrences so user can detect when it is happening. 4117 * The issue is non-fatal and there's no recovery action 4118 * available. 4119 */ 4120 if (icr & E1000_ICR_DOUTSYNC) { 4121 IGB_STAT(igb->dout_sync); 4122 } 4123 4124 if (icr & E1000_ICR_DRSTA) { 4125 /* 82580 Full Device Reset needed */ 4126 atomic_or_32(&igb->igb_state, IGB_STALL); 4127 } 4128 4129 return (DDI_INTR_CLAIMED); 4130 } 4131 4132 /* 4133 * igb_alloc_intrs - Allocate interrupts for the driver 4134 * 4135 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 4136 * if not successful, try Legacy. 4137 * igb->intr_force can be used to force sequence to start with 4138 * any of the 3 types. 4139 * If MSI-X is not used, number of tx/rx rings is forced to 1. 4140 */ 4141 static int 4142 igb_alloc_intrs(igb_t *igb) 4143 { 4144 dev_info_t *devinfo; 4145 int intr_types; 4146 int rc; 4147 4148 devinfo = igb->dip; 4149 4150 /* Get supported interrupt types */ 4151 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4152 4153 if (rc != DDI_SUCCESS) { 4154 igb_log(igb, 4155 "Get supported interrupt types failed: %d", rc); 4156 return (IGB_FAILURE); 4157 } 4158 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 4159 4160 igb->intr_type = 0; 4161 4162 /* Install MSI-X interrupts */ 4163 if ((intr_types & DDI_INTR_TYPE_MSIX) && 4164 (igb->intr_force <= IGB_INTR_MSIX)) { 4165 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 4166 4167 if (rc == IGB_SUCCESS) 4168 return (IGB_SUCCESS); 4169 4170 igb_log(igb, 4171 "Allocate MSI-X failed, trying MSI interrupts..."); 4172 } 4173 4174 /* MSI-X not used, force rings to 1 */ 4175 igb->num_rx_rings = 1; 4176 igb->num_tx_rings = 1; 4177 igb_log(igb, 4178 "MSI-X not used, force rx and tx queue number to 1"); 4179 4180 /* Install MSI interrupts */ 4181 if ((intr_types & DDI_INTR_TYPE_MSI) && 4182 (igb->intr_force <= IGB_INTR_MSI)) { 4183 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 4184 4185 if (rc == IGB_SUCCESS) 4186 return (IGB_SUCCESS); 4187 4188 igb_log(igb, 4189 "Allocate MSI failed, trying Legacy interrupts..."); 4190 } 4191 4192 /* Install legacy interrupts */ 4193 if (intr_types & DDI_INTR_TYPE_FIXED) { 4194 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 4195 4196 if (rc == IGB_SUCCESS) 4197 return (IGB_SUCCESS); 4198 4199 igb_log(igb, 4200 "Allocate Legacy interrupts failed"); 4201 } 4202 4203 /* If none of the 3 types succeeded, return failure */ 4204 return (IGB_FAILURE); 4205 } 4206 4207 /* 4208 * igb_alloc_intr_handles - Allocate interrupt handles. 4209 * 4210 * For legacy and MSI, only 1 handle is needed. For MSI-X, 4211 * if fewer than 2 handles are available, return failure. 4212 * Upon success, this sets the number of Rx rings to a number that 4213 * matches the handles available for Rx interrupts. 4214 */ 4215 static int 4216 igb_alloc_intr_handles(igb_t *igb, int intr_type) 4217 { 4218 dev_info_t *devinfo; 4219 int orig, request, count, avail, actual; 4220 int diff, minimum; 4221 int rc; 4222 4223 devinfo = igb->dip; 4224 4225 switch (intr_type) { 4226 case DDI_INTR_TYPE_FIXED: 4227 request = 1; /* Request 1 legacy interrupt handle */ 4228 minimum = 1; 4229 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 4230 break; 4231 4232 case DDI_INTR_TYPE_MSI: 4233 request = 1; /* Request 1 MSI interrupt handle */ 4234 minimum = 1; 4235 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 4236 break; 4237 4238 case DDI_INTR_TYPE_MSIX: 4239 /* 4240 * Number of vectors for the adapter is 4241 * # rx rings + # tx rings 4242 * One of tx vectors is for tx & other 4243 */ 4244 request = igb->num_rx_rings + igb->num_tx_rings; 4245 orig = request; 4246 minimum = 2; 4247 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 4248 break; 4249 4250 default: 4251 igb_log(igb, 4252 "invalid call to igb_alloc_intr_handles(): %d\n", 4253 intr_type); 4254 return (IGB_FAILURE); 4255 } 4256 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 4257 request, minimum); 4258 4259 /* 4260 * Get number of supported interrupts 4261 */ 4262 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4263 if ((rc != DDI_SUCCESS) || (count < minimum)) { 4264 igb_log(igb, 4265 "Get supported interrupt number failed. " 4266 "Return: %d, count: %d", rc, count); 4267 return (IGB_FAILURE); 4268 } 4269 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 4270 4271 /* 4272 * Get number of available interrupts 4273 */ 4274 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4275 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 4276 igb_log(igb, 4277 "Get available interrupt number failed. " 4278 "Return: %d, available: %d", rc, avail); 4279 return (IGB_FAILURE); 4280 } 4281 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 4282 4283 if (avail < request) { 4284 igb_log(igb, "Request %d handles, %d available", 4285 request, avail); 4286 request = avail; 4287 } 4288 4289 actual = 0; 4290 igb->intr_cnt = 0; 4291 4292 /* 4293 * Allocate an array of interrupt handles 4294 */ 4295 igb->intr_size = request * sizeof (ddi_intr_handle_t); 4296 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 4297 4298 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 4299 request, &actual, DDI_INTR_ALLOC_NORMAL); 4300 if (rc != DDI_SUCCESS) { 4301 igb_log(igb, "Allocate interrupts failed. " 4302 "return: %d, request: %d, actual: %d", 4303 rc, request, actual); 4304 goto alloc_handle_fail; 4305 } 4306 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 4307 4308 igb->intr_cnt = actual; 4309 4310 if (actual < minimum) { 4311 igb_log(igb, "Insufficient interrupt handles allocated: %d", 4312 actual); 4313 goto alloc_handle_fail; 4314 } 4315 4316 /* 4317 * For MSI-X, actual might force us to reduce number of tx & rx rings 4318 */ 4319 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) { 4320 diff = orig - actual; 4321 if (diff < igb->num_tx_rings) { 4322 igb_log(igb, 4323 "MSI-X vectors force Tx queue number to %d", 4324 igb->num_tx_rings - diff); 4325 igb->num_tx_rings -= diff; 4326 } else { 4327 igb_log(igb, 4328 "MSI-X vectors force Tx queue number to 1"); 4329 igb->num_tx_rings = 1; 4330 4331 igb_log(igb, 4332 "MSI-X vectors force Rx queue number to %d", 4333 actual - 1); 4334 igb->num_rx_rings = actual - 1; 4335 } 4336 } 4337 4338 /* 4339 * Get priority for first vector, assume remaining are all the same 4340 */ 4341 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 4342 if (rc != DDI_SUCCESS) { 4343 igb_log(igb, 4344 "Get interrupt priority failed: %d", rc); 4345 goto alloc_handle_fail; 4346 } 4347 4348 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 4349 if (rc != DDI_SUCCESS) { 4350 igb_log(igb, 4351 "Get interrupt cap failed: %d", rc); 4352 goto alloc_handle_fail; 4353 } 4354 4355 igb->intr_type = intr_type; 4356 4357 return (IGB_SUCCESS); 4358 4359 alloc_handle_fail: 4360 igb_rem_intrs(igb); 4361 4362 return (IGB_FAILURE); 4363 } 4364 4365 /* 4366 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 4367 * 4368 * Before adding the interrupt handlers, the interrupt vectors have 4369 * been allocated, and the rx/tx rings have also been allocated. 4370 */ 4371 static int 4372 igb_add_intr_handlers(igb_t *igb) 4373 { 4374 igb_rx_ring_t *rx_ring; 4375 igb_tx_ring_t *tx_ring; 4376 int vector; 4377 int rc; 4378 int i; 4379 4380 vector = 0; 4381 4382 switch (igb->intr_type) { 4383 case DDI_INTR_TYPE_MSIX: 4384 /* Add interrupt handler for tx + other */ 4385 tx_ring = &igb->tx_rings[0]; 4386 rc = ddi_intr_add_handler(igb->htable[vector], 4387 (ddi_intr_handler_t *)igb_intr_tx_other, 4388 (void *)igb, NULL); 4389 4390 if (rc != DDI_SUCCESS) { 4391 igb_log(igb, 4392 "Add tx/other interrupt handler failed: %d", rc); 4393 return (IGB_FAILURE); 4394 } 4395 tx_ring->intr_vector = vector; 4396 vector++; 4397 4398 /* Add interrupt handler for each rx ring */ 4399 for (i = 0; i < igb->num_rx_rings; i++) { 4400 rx_ring = &igb->rx_rings[i]; 4401 4402 rc = ddi_intr_add_handler(igb->htable[vector], 4403 (ddi_intr_handler_t *)igb_intr_rx, 4404 (void *)rx_ring, NULL); 4405 4406 if (rc != DDI_SUCCESS) { 4407 igb_log(igb, 4408 "Add rx interrupt handler failed. " 4409 "return: %d, rx ring: %d", rc, i); 4410 for (vector--; vector >= 0; vector--) { 4411 (void) ddi_intr_remove_handler( 4412 igb->htable[vector]); 4413 } 4414 return (IGB_FAILURE); 4415 } 4416 4417 rx_ring->intr_vector = vector; 4418 4419 vector++; 4420 } 4421 4422 /* Add interrupt handler for each tx ring from 2nd ring */ 4423 for (i = 1; i < igb->num_tx_rings; i++) { 4424 tx_ring = &igb->tx_rings[i]; 4425 4426 rc = ddi_intr_add_handler(igb->htable[vector], 4427 (ddi_intr_handler_t *)igb_intr_tx, 4428 (void *)tx_ring, NULL); 4429 4430 if (rc != DDI_SUCCESS) { 4431 igb_log(igb, 4432 "Add tx interrupt handler failed. " 4433 "return: %d, tx ring: %d", rc, i); 4434 for (vector--; vector >= 0; vector--) { 4435 (void) ddi_intr_remove_handler( 4436 igb->htable[vector]); 4437 } 4438 return (IGB_FAILURE); 4439 } 4440 4441 tx_ring->intr_vector = vector; 4442 4443 vector++; 4444 } 4445 4446 break; 4447 4448 case DDI_INTR_TYPE_MSI: 4449 /* Add interrupt handlers for the only vector */ 4450 rc = ddi_intr_add_handler(igb->htable[vector], 4451 (ddi_intr_handler_t *)igb_intr_msi, 4452 (void *)igb, NULL); 4453 4454 if (rc != DDI_SUCCESS) { 4455 igb_log(igb, 4456 "Add MSI interrupt handler failed: %d", rc); 4457 return (IGB_FAILURE); 4458 } 4459 4460 rx_ring = &igb->rx_rings[0]; 4461 rx_ring->intr_vector = vector; 4462 4463 vector++; 4464 break; 4465 4466 case DDI_INTR_TYPE_FIXED: 4467 /* Add interrupt handlers for the only vector */ 4468 rc = ddi_intr_add_handler(igb->htable[vector], 4469 (ddi_intr_handler_t *)igb_intr_legacy, 4470 (void *)igb, NULL); 4471 4472 if (rc != DDI_SUCCESS) { 4473 igb_log(igb, 4474 "Add legacy interrupt handler failed: %d", rc); 4475 return (IGB_FAILURE); 4476 } 4477 4478 rx_ring = &igb->rx_rings[0]; 4479 rx_ring->intr_vector = vector; 4480 4481 vector++; 4482 break; 4483 4484 default: 4485 return (IGB_FAILURE); 4486 } 4487 4488 ASSERT(vector == igb->intr_cnt); 4489 4490 return (IGB_SUCCESS); 4491 } 4492 4493 /* 4494 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts 4495 * 4496 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 4497 */ 4498 static void 4499 igb_setup_msix_82575(igb_t *igb) 4500 { 4501 uint32_t eims = 0; 4502 int i, vector; 4503 struct e1000_hw *hw = &igb->hw; 4504 4505 /* 4506 * Set vector for tx ring 0 and other causes. 4507 * NOTE assumption that it is vector 0. 4508 */ 4509 vector = 0; 4510 4511 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 4512 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 4513 vector++; 4514 4515 for (i = 0; i < igb->num_rx_rings; i++) { 4516 /* 4517 * Set vector for each rx ring 4518 */ 4519 eims = (E1000_EICR_RX_QUEUE0 << i); 4520 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4521 4522 /* 4523 * Accumulate bits to enable in 4524 * igb_enable_adapter_interrupts_82575() 4525 */ 4526 igb->eims_mask |= eims; 4527 4528 vector++; 4529 } 4530 4531 for (i = 1; i < igb->num_tx_rings; i++) { 4532 /* 4533 * Set vector for each tx ring from 2nd tx ring 4534 */ 4535 eims = (E1000_EICR_TX_QUEUE0 << i); 4536 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4537 4538 /* 4539 * Accumulate bits to enable in 4540 * igb_enable_adapter_interrupts_82575() 4541 */ 4542 igb->eims_mask |= eims; 4543 4544 vector++; 4545 } 4546 4547 ASSERT(vector == igb->intr_cnt); 4548 4549 /* 4550 * Disable IAM for ICR interrupt bits 4551 */ 4552 E1000_WRITE_REG(hw, E1000_IAM, 0); 4553 E1000_WRITE_FLUSH(hw); 4554 } 4555 4556 /* 4557 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts 4558 * 4559 * 82576 uses a table based method for assigning vectors. Each queue has a 4560 * single entry in the table to which we write a vector number along with a 4561 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors 4562 * take a different position in the 4-byte register depending on whether 4563 * they are numbered above or below 8. 4564 */ 4565 static void 4566 igb_setup_msix_82576(igb_t *igb) 4567 { 4568 struct e1000_hw *hw = &igb->hw; 4569 uint32_t ivar, index, vector; 4570 int i; 4571 4572 /* must enable msi-x capability before IVAR settings */ 4573 E1000_WRITE_REG(hw, E1000_GPIE, 4574 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR)); 4575 4576 /* 4577 * Set vector for tx ring 0 and other causes. 4578 * NOTE assumption that it is vector 0. 4579 * This is also interdependent with installation of interrupt service 4580 * routines in igb_add_intr_handlers(). 4581 */ 4582 4583 /* assign "other" causes to vector 0 */ 4584 vector = 0; 4585 ivar = ((vector | E1000_IVAR_VALID) << 8); 4586 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4587 4588 /* assign tx ring 0 to vector 0 */ 4589 ivar = ((vector | E1000_IVAR_VALID) << 8); 4590 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4591 4592 /* prepare to enable tx & other interrupt causes */ 4593 igb->eims_mask = (1 << vector); 4594 4595 vector ++; 4596 for (i = 0; i < igb->num_rx_rings; i++) { 4597 /* 4598 * Set vector for each rx ring 4599 */ 4600 index = (i & 0x7); 4601 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4602 4603 if (i < 8) { 4604 /* vector goes into low byte of register */ 4605 ivar = ivar & 0xFFFFFF00; 4606 ivar |= (vector | E1000_IVAR_VALID); 4607 } else { 4608 /* vector goes into third byte of register */ 4609 ivar = ivar & 0xFF00FFFF; 4610 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4611 } 4612 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4613 4614 /* Accumulate interrupt-cause bits to enable */ 4615 igb->eims_mask |= (1 << vector); 4616 4617 vector ++; 4618 } 4619 4620 for (i = 1; i < igb->num_tx_rings; i++) { 4621 /* 4622 * Set vector for each tx ring from 2nd tx ring. 4623 * Note assumption that tx vectors numericall follow rx vectors. 4624 */ 4625 index = (i & 0x7); 4626 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4627 4628 if (i < 8) { 4629 /* vector goes into second byte of register */ 4630 ivar = ivar & 0xFFFF00FF; 4631 ivar |= ((vector | E1000_IVAR_VALID) << 8); 4632 } else { 4633 /* vector goes into fourth byte of register */ 4634 ivar = ivar & 0x00FFFFFF; 4635 ivar |= (vector | E1000_IVAR_VALID) << 24; 4636 } 4637 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4638 4639 /* Accumulate interrupt-cause bits to enable */ 4640 igb->eims_mask |= (1 << vector); 4641 4642 vector ++; 4643 } 4644 4645 ASSERT(vector == igb->intr_cnt); 4646 } 4647 4648 /* 4649 * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts 4650 * 4651 * 82580 uses same table approach at 82576 but has fewer entries. Each 4652 * queue has a single entry in the table to which we write a vector number 4653 * along with a "valid" bit. Vectors take a different position in the 4654 * register depending on * whether * they are numbered above or below 4. 4655 */ 4656 static void 4657 igb_setup_msix_82580(igb_t *igb) 4658 { 4659 struct e1000_hw *hw = &igb->hw; 4660 uint32_t ivar, index, vector; 4661 int i; 4662 4663 /* must enable msi-x capability before IVAR settings */ 4664 E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE | 4665 E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME)); 4666 /* 4667 * Set vector for tx ring 0 and other causes. 4668 * NOTE assumption that it is vector 0. 4669 * This is also interdependent with installation of interrupt service 4670 * routines in igb_add_intr_handlers(). 4671 */ 4672 4673 /* assign "other" causes to vector 0 */ 4674 vector = 0; 4675 ivar = ((vector | E1000_IVAR_VALID) << 8); 4676 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4677 4678 /* assign tx ring 0 to vector 0 */ 4679 ivar = ((vector | E1000_IVAR_VALID) << 8); 4680 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4681 4682 /* prepare to enable tx & other interrupt causes */ 4683 igb->eims_mask = (1 << vector); 4684 4685 vector ++; 4686 4687 for (i = 0; i < igb->num_rx_rings; i++) { 4688 /* 4689 * Set vector for each rx ring 4690 */ 4691 index = (i >> 1); 4692 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4693 4694 if (i & 1) { 4695 /* vector goes into third byte of register */ 4696 ivar = ivar & 0xFF00FFFF; 4697 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4698 } else { 4699 /* vector goes into low byte of register */ 4700 ivar = ivar & 0xFFFFFF00; 4701 ivar |= (vector | E1000_IVAR_VALID); 4702 } 4703 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4704 4705 /* Accumulate interrupt-cause bits to enable */ 4706 igb->eims_mask |= (1 << vector); 4707 4708 vector ++; 4709 } 4710 4711 for (i = 1; i < igb->num_tx_rings; i++) { 4712 /* 4713 * Set vector for each tx ring from 2nd tx ring. 4714 * Note assumption that tx vectors numericall follow rx vectors. 4715 */ 4716 index = (i >> 1); 4717 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4718 4719 if (i & 1) { 4720 /* vector goes into high byte of register */ 4721 ivar = ivar & 0x00FFFFFF; 4722 ivar |= ((vector | E1000_IVAR_VALID) << 24); 4723 } else { 4724 /* vector goes into second byte of register */ 4725 ivar = ivar & 0xFFFF00FF; 4726 ivar |= (vector | E1000_IVAR_VALID) << 8; 4727 } 4728 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4729 4730 /* Accumulate interrupt-cause bits to enable */ 4731 igb->eims_mask |= (1 << vector); 4732 4733 vector ++; 4734 } 4735 ASSERT(vector == igb->intr_cnt); 4736 } 4737 4738 /* 4739 * igb_rem_intr_handlers - remove the interrupt handlers 4740 */ 4741 static void 4742 igb_rem_intr_handlers(igb_t *igb) 4743 { 4744 int i; 4745 int rc; 4746 4747 for (i = 0; i < igb->intr_cnt; i++) { 4748 rc = ddi_intr_remove_handler(igb->htable[i]); 4749 if (rc != DDI_SUCCESS) { 4750 IGB_DEBUGLOG_1(igb, 4751 "Remove intr handler failed: %d", rc); 4752 } 4753 } 4754 } 4755 4756 /* 4757 * igb_rem_intrs - remove the allocated interrupts 4758 */ 4759 static void 4760 igb_rem_intrs(igb_t *igb) 4761 { 4762 int i; 4763 int rc; 4764 4765 for (i = 0; i < igb->intr_cnt; i++) { 4766 rc = ddi_intr_free(igb->htable[i]); 4767 if (rc != DDI_SUCCESS) { 4768 IGB_DEBUGLOG_1(igb, 4769 "Free intr failed: %d", rc); 4770 } 4771 } 4772 4773 kmem_free(igb->htable, igb->intr_size); 4774 igb->htable = NULL; 4775 } 4776 4777 /* 4778 * igb_enable_intrs - enable all the ddi interrupts 4779 */ 4780 static int 4781 igb_enable_intrs(igb_t *igb) 4782 { 4783 int i; 4784 int rc; 4785 4786 /* Enable interrupts */ 4787 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4788 /* Call ddi_intr_block_enable() for MSI */ 4789 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 4790 if (rc != DDI_SUCCESS) { 4791 igb_log(igb, 4792 "Enable block intr failed: %d", rc); 4793 return (IGB_FAILURE); 4794 } 4795 } else { 4796 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4797 for (i = 0; i < igb->intr_cnt; i++) { 4798 rc = ddi_intr_enable(igb->htable[i]); 4799 if (rc != DDI_SUCCESS) { 4800 igb_log(igb, 4801 "Enable intr failed: %d", rc); 4802 return (IGB_FAILURE); 4803 } 4804 } 4805 } 4806 4807 return (IGB_SUCCESS); 4808 } 4809 4810 /* 4811 * igb_disable_intrs - disable all the ddi interrupts 4812 */ 4813 static int 4814 igb_disable_intrs(igb_t *igb) 4815 { 4816 int i; 4817 int rc; 4818 4819 /* Disable all interrupts */ 4820 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4821 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 4822 if (rc != DDI_SUCCESS) { 4823 igb_log(igb, 4824 "Disable block intr failed: %d", rc); 4825 return (IGB_FAILURE); 4826 } 4827 } else { 4828 for (i = 0; i < igb->intr_cnt; i++) { 4829 rc = ddi_intr_disable(igb->htable[i]); 4830 if (rc != DDI_SUCCESS) { 4831 igb_log(igb, 4832 "Disable intr failed: %d", rc); 4833 return (IGB_FAILURE); 4834 } 4835 } 4836 } 4837 4838 return (IGB_SUCCESS); 4839 } 4840 4841 /* 4842 * igb_get_phy_state - Get and save the parameters read from PHY registers 4843 */ 4844 static void 4845 igb_get_phy_state(igb_t *igb) 4846 { 4847 struct e1000_hw *hw = &igb->hw; 4848 uint16_t phy_ctrl; 4849 uint16_t phy_status; 4850 uint16_t phy_an_adv; 4851 uint16_t phy_an_exp; 4852 uint16_t phy_ext_status; 4853 uint16_t phy_1000t_ctrl; 4854 uint16_t phy_1000t_status; 4855 uint16_t phy_lp_able; 4856 4857 ASSERT(mutex_owned(&igb->gen_lock)); 4858 4859 if (hw->phy.media_type == e1000_media_type_copper) { 4860 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4861 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 4862 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 4863 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 4864 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 4865 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 4866 (void) e1000_read_phy_reg(hw, 4867 PHY_1000T_STATUS, &phy_1000t_status); 4868 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 4869 4870 igb->param_autoneg_cap = 4871 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 4872 igb->param_pause_cap = 4873 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4874 igb->param_asym_pause_cap = 4875 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4876 igb->param_1000fdx_cap = 4877 ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4878 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 4879 igb->param_1000hdx_cap = 4880 ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 4881 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 4882 igb->param_100t4_cap = 4883 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 4884 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 4885 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 4886 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 4887 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 4888 igb->param_10fdx_cap = 4889 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 4890 igb->param_10hdx_cap = 4891 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 4892 igb->param_rem_fault = 4893 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 4894 4895 igb->param_adv_autoneg_cap = hw->mac.autoneg; 4896 igb->param_adv_pause_cap = 4897 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4898 igb->param_adv_asym_pause_cap = 4899 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4900 igb->param_adv_1000hdx_cap = 4901 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 4902 igb->param_adv_100t4_cap = 4903 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 4904 igb->param_adv_rem_fault = 4905 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 4906 if (igb->param_adv_autoneg_cap == 1) { 4907 igb->param_adv_1000fdx_cap = 4908 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 4909 igb->param_adv_100fdx_cap = 4910 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 4911 igb->param_adv_100hdx_cap = 4912 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 4913 igb->param_adv_10fdx_cap = 4914 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 4915 igb->param_adv_10hdx_cap = 4916 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 4917 } 4918 4919 igb->param_lp_autoneg_cap = 4920 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 4921 igb->param_lp_pause_cap = 4922 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 4923 igb->param_lp_asym_pause_cap = 4924 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 4925 igb->param_lp_1000fdx_cap = 4926 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 4927 igb->param_lp_1000hdx_cap = 4928 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 4929 igb->param_lp_100t4_cap = 4930 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 4931 igb->param_lp_100fdx_cap = 4932 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 4933 igb->param_lp_100hdx_cap = 4934 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 4935 igb->param_lp_10fdx_cap = 4936 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 4937 igb->param_lp_10hdx_cap = 4938 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 4939 igb->param_lp_rem_fault = 4940 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 4941 } else { 4942 /* 4943 * 1Gig Fiber adapter only offers 1Gig Full Duplex. 4944 */ 4945 igb->param_autoneg_cap = 0; 4946 igb->param_pause_cap = 1; 4947 igb->param_asym_pause_cap = 1; 4948 igb->param_1000fdx_cap = 1; 4949 igb->param_1000hdx_cap = 0; 4950 igb->param_100t4_cap = 0; 4951 igb->param_100fdx_cap = 0; 4952 igb->param_100hdx_cap = 0; 4953 igb->param_10fdx_cap = 0; 4954 igb->param_10hdx_cap = 0; 4955 4956 igb->param_adv_autoneg_cap = 0; 4957 igb->param_adv_pause_cap = 1; 4958 igb->param_adv_asym_pause_cap = 1; 4959 igb->param_adv_1000fdx_cap = 1; 4960 igb->param_adv_1000hdx_cap = 0; 4961 igb->param_adv_100t4_cap = 0; 4962 igb->param_adv_100fdx_cap = 0; 4963 igb->param_adv_100hdx_cap = 0; 4964 igb->param_adv_10fdx_cap = 0; 4965 igb->param_adv_10hdx_cap = 0; 4966 4967 igb->param_lp_autoneg_cap = 0; 4968 igb->param_lp_pause_cap = 0; 4969 igb->param_lp_asym_pause_cap = 0; 4970 igb->param_lp_1000fdx_cap = 0; 4971 igb->param_lp_1000hdx_cap = 0; 4972 igb->param_lp_100t4_cap = 0; 4973 igb->param_lp_100fdx_cap = 0; 4974 igb->param_lp_100hdx_cap = 0; 4975 igb->param_lp_10fdx_cap = 0; 4976 igb->param_lp_10hdx_cap = 0; 4977 igb->param_lp_rem_fault = 0; 4978 } 4979 } 4980 4981 /* 4982 * synchronize the adv* and en* parameters. 4983 * 4984 * See comments in <sys/dld.h> for details of the *_en_* 4985 * parameters. The usage of ndd for setting adv parameters will 4986 * synchronize all the en parameters with the e1000g parameters, 4987 * implicitly disabling any settings made via dladm. 4988 */ 4989 static void 4990 igb_param_sync(igb_t *igb) 4991 { 4992 igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap; 4993 igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap; 4994 igb->param_en_100t4_cap = igb->param_adv_100t4_cap; 4995 igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap; 4996 igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap; 4997 igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap; 4998 igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap; 4999 } 5000 5001 /* 5002 * igb_get_driver_control 5003 */ 5004 static void 5005 igb_get_driver_control(struct e1000_hw *hw) 5006 { 5007 uint32_t ctrl_ext; 5008 5009 /* Notify firmware that driver is in control of device */ 5010 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5011 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 5012 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5013 } 5014 5015 /* 5016 * igb_release_driver_control 5017 */ 5018 static void 5019 igb_release_driver_control(struct e1000_hw *hw) 5020 { 5021 uint32_t ctrl_ext; 5022 5023 /* Notify firmware that driver is no longer in control of device */ 5024 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5025 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 5026 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5027 } 5028 5029 /* 5030 * igb_atomic_reserve - Atomic decrease operation 5031 */ 5032 int 5033 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 5034 { 5035 uint32_t oldval; 5036 uint32_t newval; 5037 5038 /* ATOMICALLY */ 5039 do { 5040 oldval = *count_p; 5041 if (oldval < n) 5042 return (-1); 5043 newval = oldval - n; 5044 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 5045 5046 return (newval); 5047 } 5048 5049 /* 5050 * FMA support 5051 */ 5052 5053 int 5054 igb_check_acc_handle(ddi_acc_handle_t handle) 5055 { 5056 ddi_fm_error_t de; 5057 5058 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5059 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5060 return (de.fme_status); 5061 } 5062 5063 int 5064 igb_check_dma_handle(ddi_dma_handle_t handle) 5065 { 5066 ddi_fm_error_t de; 5067 5068 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5069 return (de.fme_status); 5070 } 5071 5072 /* 5073 * The IO fault service error handling callback function 5074 */ 5075 /*ARGSUSED*/ 5076 static int 5077 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5078 { 5079 /* 5080 * as the driver can always deal with an error in any dma or 5081 * access handle, we can just return the fme_status value. 5082 */ 5083 pci_ereport_post(dip, err, NULL); 5084 return (err->fme_status); 5085 } 5086 5087 static void 5088 igb_fm_init(igb_t *igb) 5089 { 5090 ddi_iblock_cookie_t iblk; 5091 int fma_dma_flag; 5092 5093 /* Only register with IO Fault Services if we have some capability */ 5094 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5095 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5096 } else { 5097 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5098 } 5099 5100 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5101 fma_dma_flag = 1; 5102 } else { 5103 fma_dma_flag = 0; 5104 } 5105 5106 (void) igb_set_fma_flags(fma_dma_flag); 5107 5108 if (igb->fm_capabilities) { 5109 5110 /* Register capabilities with IO Fault Services */ 5111 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 5112 5113 /* 5114 * Initialize pci ereport capabilities if ereport capable 5115 */ 5116 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 5117 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5118 pci_ereport_setup(igb->dip); 5119 5120 /* 5121 * Register error callback if error callback capable 5122 */ 5123 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5124 ddi_fm_handler_register(igb->dip, 5125 igb_fm_error_cb, (void*) igb); 5126 } 5127 } 5128 5129 static void 5130 igb_fm_fini(igb_t *igb) 5131 { 5132 /* Only unregister FMA capabilities if we registered some */ 5133 if (igb->fm_capabilities) { 5134 5135 /* 5136 * Release any resources allocated by pci_ereport_setup() 5137 */ 5138 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 5139 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5140 pci_ereport_teardown(igb->dip); 5141 5142 /* 5143 * Un-register error callback if error callback capable 5144 */ 5145 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5146 ddi_fm_handler_unregister(igb->dip); 5147 5148 /* Unregister from IO Fault Services */ 5149 ddi_fm_fini(igb->dip); 5150 } 5151 } 5152 5153 void 5154 igb_fm_ereport(igb_t *igb, char *detail) 5155 { 5156 uint64_t ena; 5157 char buf[FM_MAX_CLASS]; 5158 5159 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5160 ena = fm_ena_generate(0, FM_ENA_FMT1); 5161 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 5162 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 5163 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5164 } 5165 } 5166