1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _HXGE_PFC_H 28 #define _HXGE_PFC_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 0 and 4095 are reserved */ 37 #define VLAN_ID_MIN 1 38 #define VLAN_ID_MAX 4094 39 #define VLAN_ID_IMPLICIT 0 40 41 #define HXGE_MAC_DEFAULT_ADDR_SLOT 0 42 43 #define HASH_BITS 8 44 #define NMCFILTER_BITS (1 << HASH_BITS) 45 #define HASH_REG_WIDTH 16 46 #define NMCFILTER_REGS (NMCFILTER_BITS / HASH_REG_WIDTH) 47 /* Number of multicast filter regs */ 48 #define MAC_MAX_HASH_ENTRY NMCFILTER_REGS 49 50 #define REG_PIO_WRITE64(handle, offset, value) \ 51 HXGE_REG_WR64((handle), (offset), (value)) 52 #define REG_PIO_READ64(handle, offset, val_p) \ 53 HXGE_REG_RD64((handle), (offset), (val_p)) 54 55 #define TCAM_CTL_RWC_TCAM_WR 0x0 56 #define TCAM_CTL_RWC_TCAM_CMP 0x2 57 #define TCAM_CTL_RWC_RAM_WR 0x4 58 #define TCAM_CTL_RWC_RAM_RD 0x5 59 #define TCAM_CTL_RWC_RWC_STAT 0x1 60 #define TCAM_CTL_RWC_RWC_MATCH 0x1 61 62 #define WRITE_TCAM_REG_CTL(handle, ctl) \ 63 REG_PIO_WRITE64(handle, PFC_TCAM_CTRL, ctl) 64 65 #define READ_TCAM_REG_CTL(handle, val_p) \ 66 REG_PIO_READ64(handle, PFC_TCAM_CTRL, val_p) 67 68 #define WRITE_TCAM_REG_KEY0(handle, key) \ 69 REG_PIO_WRITE64(handle, PFC_TCAM_KEY0, key) 70 #define WRITE_TCAM_REG_KEY1(handle, key) \ 71 REG_PIO_WRITE64(handle, PFC_TCAM_KEY1, key) 72 #define WRITE_TCAM_REG_MASK0(handle, mask) \ 73 REG_PIO_WRITE64(handle, PFC_TCAM_MASK0, mask) 74 #define WRITE_TCAM_REG_MASK1(handle, mask) \ 75 REG_PIO_WRITE64(handle, PFC_TCAM_MASK1, mask) 76 77 #define READ_TCAM_REG_KEY0(handle, val_p) \ 78 REG_PIO_READ64(handle, PFC_TCAM_KEY0, val_p) 79 #define READ_TCAM_REG_KEY1(handle, val_p) \ 80 REG_PIO_READ64(handle, PFC_TCAM_KEY1, val_p) 81 #define READ_TCAM_REG_MASK0(handle, val_p) \ 82 REG_PIO_READ64(handle, PFC_TCAM_MASK0, val_p) 83 #define READ_TCAM_REG_MASK1(handle, val_p) \ 84 REG_PIO_READ64(handle, PFC_TCAM_MASK1, val_p) 85 86 typedef union _hxge_tcam_res_t { 87 uint64_t value; 88 struct { 89 #if defined(_BIG_ENDIAN) 90 uint64_t padding:34; 91 uint64_t reserved:15; 92 uint64_t parity:1; 93 uint64_t hit_count:4; 94 uint64_t channel_d:2; 95 uint64_t channel_c:2; 96 uint64_t channel_b:2; 97 uint64_t channel_a:2; 98 uint64_t source_hash:1; 99 uint64_t discard:1; 100 #else 101 uint64_t discard:1; 102 uint64_t source_hash:1; 103 uint64_t channel_a:2; 104 uint64_t channel_b:2; 105 uint64_t channel_c:2; 106 uint64_t channel_d:2; 107 uint64_t hit_count:4; 108 uint64_t parity:1; 109 uint64_t reserved:15; 110 uint64_t padding:34; 111 #endif 112 } bits; 113 } hxge_tcam_res_t, *p_hxge_tcam_res_t; 114 115 typedef struct tcam_reg { 116 #if defined(_BIG_ENDIAN) 117 uint64_t reg1; /* 99:64 */ 118 uint64_t reg0; /* 63:0 */ 119 #else 120 uint64_t reg0; /* 63:0 */ 121 uint64_t reg1; /* 99:64 */ 122 #endif 123 } hxge_tcam_reg_t; 124 125 typedef struct hxge_tcam_ipv4_S { 126 #if defined(_BIG_ENDIAN) 127 uint32_t class_code:5; /* 99:95 */ 128 uint32_t blade_id:4; /* 94:91 */ 129 uint32_t rsrvd2:2; /* 90:89 */ 130 uint32_t noport:1; /* 88 */ 131 uint32_t protocol:8; /* 87:80 */ 132 uint32_t l4_hdr; /* 79:48 */ 133 uint32_t rsrvd:16; /* 47:32 */ 134 uint32_t ip_daddr; /* 31:0 */ 135 #else 136 uint32_t ip_daddr; /* 31:0 */ 137 uint32_t rsrvd:16; /* 47:32 */ 138 uint32_t l4_hdr; /* 79:48 */ 139 uint32_t protocol:8; /* 87:80 */ 140 uint32_t noport:1; /* 88 */ 141 uint32_t rsrvd2:2; /* 90:89 */ 142 uint32_t blade_id:4; /* 94:91 */ 143 uint32_t class_code:5; /* 99:95 */ 144 #endif 145 } hxge_tcam_ipv4_t; 146 147 typedef struct hxge_tcam_ipv6_S { 148 #if defined(_BIG_ENDIAN) 149 uint32_t class_code:5; /* 99:95 */ 150 uint32_t blade_id:4; /* 94:91 */ 151 uint64_t rsrvd2:3; /* 90:88 */ 152 uint64_t protocol:8; /* 87:80 */ 153 uint64_t l4_hdr:32; /* 79:48 */ 154 uint64_t rsrvd:48; /* 47:0 */ 155 #else 156 uint64_t rsrvd:48; /* 47:0 */ 157 uint64_t l4_hdr:32; /* 79:48 */ 158 uint64_t protocol:8; /* 87:80 */ 159 uint64_t rsrvd2:3; /* 90:88 */ 160 uint32_t blade_id:4; /* 94:91 */ 161 uint32_t class_code:5; /* 99:95 */ 162 #endif 163 } hxge_tcam_ipv6_t; 164 165 typedef struct hxge_tcam_enet_S { 166 #if defined(_BIG_ENDIAN) 167 uint8_t class_code:5; /* 99:95 */ 168 uint8_t blade_id:4; /* 94:91 */ 169 uint8_t rsrvd:3; /* 90:88 */ 170 uint8_t eframe[11]; /* 87:0 */ 171 #else 172 uint8_t eframe[11]; /* 87:0 */ 173 uint8_t rsrvd:3; /* 90:88 */ 174 uint8_t blade_id:4; /* 94:91 */ 175 uint8_t class_code:5; /* 99:95 */ 176 #endif 177 } hxge_tcam_ether_t; 178 179 typedef struct hxge_tcam_spread_S { 180 #if defined(_BIG_ENDIAN) 181 uint64_t unused:28; /* 127:100 */ 182 uint64_t class_code:5; /* 99:95 */ 183 uint64_t blade_id:4; /* 94:91 */ 184 uint64_t wild1:27; /* 90:64 */ 185 uint64_t wild; /* 63:0 */ 186 #else 187 uint64_t wild; /* 63:0 */ 188 uint64_t wild1:27; /* 90:64 */ 189 uint64_t blade_id:4; /* 94:91 */ 190 uint64_t class_code:5; /* 99:95 */ 191 uint64_t unused:28; /* 127:100 */ 192 #endif 193 } hxge_tcam_spread_t; 194 195 typedef struct hxge_tcam_entry_S { 196 union _hxge_tcam_entry { 197 hxge_tcam_ipv4_t ipv4; 198 hxge_tcam_ipv6_t ipv6; 199 hxge_tcam_ether_t enet; 200 hxge_tcam_reg_t regs; 201 hxge_tcam_spread_t spread; 202 } key, mask; 203 hxge_tcam_res_t match_action; 204 uint16_t ether_type; 205 } hxge_tcam_entry_t; 206 207 #define key_reg0 key.regs.reg0 208 #define key_reg1 key.regs.reg1 209 #define mask_reg0 mask.regs.reg0 210 #define mask_reg1 mask.regs.reg1 211 212 #define key0 key.regs.reg0 213 #define key1 key.regs.reg1 214 #define mask0 mask.regs.reg0 215 #define mask1 mask.regs.reg1 216 217 #define ip4_class_key key.ipv4.class_code 218 #define ip4_blade_id_key key.ipv4.blade_id 219 #define ip4_noport_key key.ipv4.noport 220 #define ip4_proto_key key.ipv4.protocol 221 #define ip4_l4_hdr_key key.ipv4.l4_hdr 222 #define ip4_dest_key key.ipv4.ip_daddr 223 224 #define ip4_class_mask mask.ipv4.class_code 225 #define ip4_blade_id_mask mask.ipv4.blade_id 226 #define ip4_noport_mask mask.ipv4.noport 227 #define ip4_proto_mask mask.ipv4.protocol 228 #define ip4_l4_hdr_mask mask.ipv4.l4_hdr 229 #define ip4_dest_mask mask.ipv4.ip_daddr 230 231 #define ip6_class_key key.ipv6.class_code 232 #define ip6_blade_id_key key.ipv6.blade_id 233 #define ip6_proto_key key.ipv6.protocol 234 #define ip6_l4_hdr_key key.ipv6.l4_hdr 235 236 #define ip6_class_mask mask.ipv6.class_code 237 #define ip6_blade_id_mask mask.ipv6.blade_id 238 #define ip6_proto_mask mask.ipv6.protocol 239 #define ip6_l4_hdr_mask mask.ipv6.l4_hdr 240 241 #define ether_class_key key.enet.class_code 242 #define ether_blade_id_key key.enet.blade_id 243 #define ether_ethframe_key key.enet.eframe 244 245 #define ether_class_mask mask.enet.class_code 246 #define ether_blade_id_mask mask.enet.blade_id 247 #define ether_ethframe_mask mask.enet.eframe 248 249 typedef struct _pfc_errlog { 250 uint32_t tcp_ctrl_drop; /* pfc_drop_log */ 251 uint32_t l2_addr_drop; 252 uint32_t class_code_drop; 253 uint32_t tcam_drop; 254 uint32_t vlan_drop; 255 256 uint32_t vlan_par_err_log; /* pfc_vlan_par_err_log */ 257 uint32_t tcam_par_err_log; /* pfc_tcam_par_err_log */ 258 } pfc_errlog_t, *p_pfc_errlog_t; 259 260 typedef struct _pfc_stats { 261 uint32_t pkt_drop; /* pfc_int_status */ 262 uint32_t tcam_parity_err; 263 uint32_t vlan_parity_err; 264 265 uint32_t bad_cs_count; /* pfc_bad_cs_counter */ 266 uint32_t drop_count; /* pfc_drop_counter */ 267 pfc_errlog_t errlog; 268 } hxge_pfc_stats_t, *p_hxge_pfc_stats_t; 269 270 typedef enum pfc_tcam_class { 271 TCAM_CLASS_INVALID = 0, 272 TCAM_CLASS_DUMMY = 1, 273 TCAM_CLASS_ETYPE_1 = 2, 274 TCAM_CLASS_ETYPE_2, 275 TCAM_CLASS_RESERVED_4, 276 TCAM_CLASS_RESERVED_5, 277 TCAM_CLASS_RESERVED_6, 278 TCAM_CLASS_RESERVED_7, 279 TCAM_CLASS_TCP_IPV4, 280 TCAM_CLASS_UDP_IPV4, 281 TCAM_CLASS_AH_ESP_IPV4, 282 TCAM_CLASS_SCTP_IPV4, 283 TCAM_CLASS_TCP_IPV6, 284 TCAM_CLASS_UDP_IPV6, 285 TCAM_CLASS_AH_ESP_IPV6, 286 TCAM_CLASS_SCTP_IPV6, 287 TCAM_CLASS_ARP, 288 TCAM_CLASS_RARP, 289 TCAM_CLASS_DUMMY_12, 290 TCAM_CLASS_DUMMY_13, 291 TCAM_CLASS_DUMMY_14, 292 TCAM_CLASS_DUMMY_15, 293 TCAM_CLASS_MAX 294 } tcam_class_t; 295 296 typedef struct _tcam_key_cfg_t { 297 boolean_t lookup_enable; 298 boolean_t discard; 299 } tcam_key_cfg_t; 300 301 typedef struct _hash_filter_t { 302 uint_t hash_ref_cnt; 303 uint16_t hash_filter_regs[NMCFILTER_REGS]; 304 uint32_t hash_bit_ref_cnt[NMCFILTER_BITS]; 305 } hash_filter_t, *p_hash_filter_t; 306 307 #define HXGE_ETHER_FLOWS (FLOW_ETHER_DHOST | FLOW_ETHER_SHOST | \ 308 FLOW_ETHER_TYPE) 309 #define HXGE_VLAN_FLOWS (FLOW_ETHER_TPID | FLOW_ETHER_TCI) 310 #define HXGE_ETHERNET_FLOWS (HXGE_ETHER_FLOWS | HXGE_VLAN_FLOWS) 311 #define HXGE_PORT_FLOWS (FLOW_ULP_PORT_REMOTE | FLOW_ULP_PORT_LOCAL) 312 #define HXGE_ADDR_FLOWS (FLOW_IP_REMOTE | FLOW_IP_LOCAL) 313 #define HXGE_IP_FLOWS (FLOW_IP_VERSION | FLOW_IP_PROTOCOL | \ 314 HXGE_PORT_FLOWS | HXGE_ADDR_FLOWS) 315 #define HXGE_SUPPORTED_FLOWS (HXGE_ETHERNET_FLOWS | HXGE_IP_FLOWS) 316 317 #define CLS_CODE_MASK 0x1f 318 #define BLADE_ID_MASK 0xf 319 #define PID_MASK 0xff 320 #define IP_PORT_MASK 0xffff 321 322 #define IP_ADDR_SA_MASK 0xFFFFFFFF 323 #define IP_ADDR_DA_MASK IP_ADDR_SA_MASK 324 #define L4PT_SPI_MASK IP_ADDR_SA_MASK 325 326 #define BLADE_ID_OFFSET 127 /* Last entry in HCR_REG */ 327 328 #ifdef __cplusplus 329 } 330 #endif 331 332 #endif /* !_HXGE_PFC_H */ 333