1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_IMPL_H 27 #define _SYS_HXGE_HXGE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #ifndef _ASM 34 #include <sys/types.h> 35 #include <sys/byteorder.h> 36 #include <sys/debug.h> 37 #include <sys/stropts.h> 38 #include <sys/stream.h> 39 #include <sys/strlog.h> 40 #include <sys/strsubr.h> 41 #include <sys/cmn_err.h> 42 #include <sys/vtrace.h> 43 #include <sys/kmem.h> 44 #include <sys/ddi.h> 45 #include <sys/sunddi.h> 46 #include <sys/strsun.h> 47 #include <sys/stat.h> 48 #include <sys/cpu.h> 49 #include <sys/kstat.h> 50 #include <inet/common.h> 51 #include <inet/ip.h> 52 #include <inet/ip6.h> 53 #include <sys/dlpi.h> 54 #include <inet/nd.h> 55 #include <netinet/in.h> 56 #include <sys/ethernet.h> 57 #include <sys/vlan.h> 58 #include <sys/pci.h> 59 #include <sys/taskq.h> 60 #include <sys/atomic.h> 61 62 #include <hxge_defs.h> 63 #include <hxge_peu.h> 64 #include <hxge_pfc.h> 65 #include <hxge_pfc_hw.h> 66 #include <hxge_vmac.h> 67 #include <hxge_fm.h> 68 #include <sys/netlb.h> 69 #include <sys/ddi_intr.h> 70 71 #include <sys/mac_provider.h> 72 #include <sys/mac_ether.h> 73 74 /* 75 * Handy macros (taken from bge driver) 76 */ 77 #define RBR_SIZE 4 78 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 79 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 80 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 81 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 82 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 83 (area).offset, (area).alength, \ 84 (flag))) 85 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 86 ((void) ddi_dma_sync((area).dma_handle,\ 87 (area.offset + bufoffset), len, \ 88 (flag))) 89 90 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 91 #define NEXT_ENTRY_PTR(ptr, first, last) \ 92 ((ptr == last) ? first : (ptr + 1)) 93 94 /* 95 * HPI related macros 96 */ 97 #define HXGE_DEV_HPI_HANDLE(hxgep) (hxgep->hpi_handle) 98 99 #define HPI_PCI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_pci_handle.regh = ah) 100 #define HPI_PCI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_pci_handle.regp = ap) 101 102 #define HPI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_handle.regh = ah) 103 #define HPI_ADD_HANDLE_SET(hxgep, ap) \ 104 hxgep->hpi_handle.is_vraddr = B_FALSE; \ 105 hxgep->hpi_handle.function.instance = hxgep->instance; \ 106 hxgep->hpi_handle.function.function = 0; \ 107 hxgep->hpi_handle.hxgep = (void *) hxgep; \ 108 hxgep->hpi_handle.regp = ap; 109 110 #define HPI_REG_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_reg_handle.regh = ah) 111 #define HPI_REG_ADD_HANDLE_SET(hxgep, ap) \ 112 hxgep->hpi_reg_handle.is_vraddr = B_FALSE; \ 113 hxgep->hpi_handle.function.instance = hxgep->instance; \ 114 hxgep->hpi_handle.function.function = 0; \ 115 hxgep->hpi_reg_handle.hxgep = (void *) hxgep; \ 116 hxgep->hpi_reg_handle.regp = ap; 117 118 #define HPI_MSI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_msi_handle.regh = ah) 119 #define HPI_MSI_ADD_HANDLE_SET(hxgep, ap) \ 120 hxgep->hpi_msi_handle.is_vraddr = B_FALSE; \ 121 hxgep->hpi_msi_handle.function.instance = hxgep->instance; \ 122 hxgep->hpi_msi_handle.function.function = 0; \ 123 hxgep->hpi_msi_handle.hxgep = (void *) hxgep; \ 124 hxgep->hpi_msi_handle.regp = ap; 125 126 #define HPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->hpi_handle.regh = ah) 127 #define HPI_DMA_ACC_HANDLE_GET(dmap) (dmap->hpi_handle.regh) 128 129 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 130 131 typedef uint32_t hxge_status_t; 132 133 typedef enum { 134 DVMA, 135 DMA, 136 SDMA 137 } dma_method_t; 138 139 typedef enum { 140 BKSIZE_4K, 141 BKSIZE_8K, 142 BKSIZE_16K, 143 BKSIZE_32K 144 } hxge_rx_block_size_t; 145 146 #ifdef TX_ONE_BUF 147 #define TX_BCOPY_MAX 512 148 #else 149 #define TX_BCOPY_MAX 512 150 #define TX_BCOPY_SIZE 512 151 #endif 152 153 #define TX_STREAM_MIN 512 154 #define TX_FASTDVMA_MIN 1024 155 156 #define HXGE_RDC_RCR_THRESHOLD_MAX 256 157 #define HXGE_RDC_RCR_TIMEOUT_MAX 64 158 #define HXGE_RDC_RCR_THRESHOLD_MIN 1 159 #define HXGE_RDC_RCR_TIMEOUT_MIN 1 160 161 #define HXGE_IS_VLAN_PACKET(ptr) \ 162 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 163 htons(VLAN_ETHERTYPE)) 164 165 typedef enum { 166 USE_NONE, 167 USE_BCOPY, 168 USE_DVMA, 169 USE_DMA, 170 USE_SDMA 171 } dma_type_t; 172 173 struct _hxge_block_mv_t { 174 uint32_t msg_type; 175 dma_type_t dma_type; 176 }; 177 178 typedef struct _hxge_block_mv_t hxge_block_mv_t, *p_hxge_block_mv_t; 179 180 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 181 typedef struct ether_header ether_header_t, *p_ether_header_t; 182 typedef queue_t *p_queue_t; 183 typedef mblk_t *p_mblk_t; 184 185 /* 186 * Common DMA data elements. 187 */ 188 struct _hxge_dma_common_t { 189 uint16_t dma_channel; 190 void *kaddrp; 191 void *ioaddr_pp; 192 ddi_dma_cookie_t dma_cookie; 193 uint32_t ncookies; 194 195 ddi_dma_handle_t dma_handle; 196 hxge_os_acc_handle_t acc_handle; 197 hpi_handle_t hpi_handle; 198 199 size_t block_size; 200 uint32_t nblocks; 201 size_t alength; 202 uint_t offset; 203 uint_t dma_chunk_index; 204 void *orig_ioaddr_pp; 205 uint64_t orig_vatopa; 206 void *orig_kaddrp; 207 size_t orig_alength; 208 boolean_t contig_alloc_type; 209 }; 210 211 typedef struct _hxge_t hxge_t, *p_hxge_t; 212 typedef struct _hxge_dma_common_t hxge_dma_common_t, *p_hxge_dma_common_t; 213 214 typedef struct _hxge_dma_pool_t { 215 p_hxge_dma_common_t *dma_buf_pool_p; 216 uint32_t ndmas; 217 uint32_t *num_chunks; 218 boolean_t buf_allocated; 219 } hxge_dma_pool_t, *p_hxge_dma_pool_t; 220 221 /* 222 * Each logical device (69): 223 * - LDG # 224 * - flag bits 225 * - masks. 226 * - interrupt handler function. 227 * 228 * Generic system interrupt handler with two arguments: 229 * (hxge_sys_intr_t) 230 * Per device instance data structure 231 * Logical group data structure. 232 * 233 * Logical device interrupt handler with two arguments: 234 * (hxge_ldv_intr_t) 235 * Per device instance data structure 236 * Logical device number 237 */ 238 typedef struct _hxge_ldg_t hxge_ldg_t, *p_hxge_ldg_t; 239 typedef struct _hxge_ldv_t hxge_ldv_t, *p_hxge_ldv_t; 240 typedef uint_t (*hxge_sys_intr_t)(caddr_t arg1, caddr_t arg2); 241 typedef uint_t (*hxge_ldv_intr_t)(caddr_t arg1, caddr_t arg2); 242 243 /* 244 * Each logical device Group (64) needs to have the following 245 * configurations: 246 * - timer counter (6 bits) 247 * - timer resolution (20 bits, number of system clocks) 248 * - system data (7 bits) 249 */ 250 struct _hxge_ldg_t { 251 uint8_t ldg; /* logical group number */ 252 uint8_t vldg_index; 253 boolean_t arm; 254 boolean_t interrupted; 255 uint16_t ldg_timer; /* counter */ 256 uint8_t vector; 257 uint8_t nldvs; 258 p_hxge_ldv_t ldvp; 259 hxge_sys_intr_t sys_intr_handler; 260 p_hxge_t hxgep; 261 }; 262 263 struct _hxge_ldv_t { 264 uint8_t ldg_assigned; 265 uint8_t ldv; 266 boolean_t is_rxdma; 267 boolean_t is_txdma; 268 boolean_t is_vmac; 269 boolean_t is_syserr; 270 boolean_t is_pfc; 271 boolean_t use_timer; 272 uint8_t channel; 273 uint8_t vdma_index; 274 p_hxge_ldg_t ldgp; 275 uint8_t ldv_ldf_masks; 276 hxge_ldv_intr_t ldv_intr_handler; 277 p_hxge_t hxgep; 278 }; 279 280 typedef struct _pci_cfg_t { 281 uint16_t vendorid; 282 uint16_t devid; 283 uint16_t command; 284 uint16_t status; 285 uint8_t revid; 286 uint8_t res0; 287 uint16_t junk1; 288 uint8_t cache_line; 289 uint8_t latency; 290 uint8_t header; 291 uint8_t bist; 292 uint32_t base; 293 uint32_t base14; 294 uint32_t base18; 295 uint32_t base1c; 296 uint32_t base20; 297 uint32_t base24; 298 uint32_t base28; 299 uint32_t base2c; 300 uint32_t base30; 301 uint32_t res1[2]; 302 uint8_t int_line; 303 uint8_t int_pin; 304 uint8_t min_gnt; 305 uint8_t max_lat; 306 } pci_cfg_t, *p_pci_cfg_t; 307 308 typedef struct _dev_regs_t { 309 hxge_os_acc_handle_t hxge_pciregh; /* PCI config DDI IO handle */ 310 p_pci_cfg_t hxge_pciregp; /* mapped PCI registers */ 311 312 hxge_os_acc_handle_t hxge_regh; /* device DDI IO (BAR 0) */ 313 void *hxge_regp; /* mapped device registers */ 314 315 hxge_os_acc_handle_t hxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 316 void *hxge_msix_regp; /* MSI/X register */ 317 318 hxge_os_acc_handle_t hxge_romh; /* fcode rom handle */ 319 unsigned char *hxge_romp; /* fcode pointer */ 320 } dev_regs_t, *p_dev_regs_t; 321 322 #include <hxge_common_impl.h> 323 #include <hxge_common.h> 324 #include <hxge_rxdma.h> 325 #include <hxge_txdma.h> 326 #include <hxge_fzc.h> 327 #include <hxge_flow.h> 328 #include <hxge_virtual.h> 329 #include <hxge.h> 330 #include <sys/modctl.h> 331 #include <sys/pattr.h> 332 #include <hpi_vir.h> 333 334 /* 335 * Reconfiguring the network devices requires the net_config privilege 336 * in Solaris 10+. Prior to this, root privilege is required. In order 337 * that the driver binary can run on both S10+ and earlier versions, we 338 * make the decisiion as to which to use at runtime. These declarations 339 * allow for either (or both) to exist ... 340 */ 341 extern int secpolicy_net_config(const cred_t *, boolean_t); 342 extern void hxge_fm_report_error(p_hxge_t hxgep, 343 uint8_t err_chan, hxge_fm_ereport_id_t fm_ereport_id); 344 extern int fm_check_acc_handle(ddi_acc_handle_t); 345 extern int fm_check_dma_handle(ddi_dma_handle_t); 346 347 #pragma weak secpolicy_net_config 348 349 hxge_status_t hxge_classify_init(p_hxge_t hxgep); 350 hxge_status_t hxge_classify_uninit(p_hxge_t hxgep); 351 void hxge_put_tcam(p_hxge_t hxgep, p_mblk_t mp); 352 void hxge_get_tcam(p_hxge_t hxgep, p_mblk_t mp); 353 354 hxge_status_t hxge_classify_init_hw(p_hxge_t hxgep); 355 hxge_status_t hxge_classify_init_sw(p_hxge_t hxgep); 356 hxge_status_t hxge_classify_exit_sw(p_hxge_t hxgep); 357 hxge_status_t hxge_pfc_ip_class_config_all(p_hxge_t hxgep); 358 hxge_status_t hxge_pfc_ip_class_config(p_hxge_t hxgep, tcam_class_t l3_class, 359 uint32_t class_config); 360 hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t hxgep, 361 tcam_class_t l3_class, uint32_t *class_config); 362 363 hxge_status_t hxge_pfc_set_hash(p_hxge_t, uint32_t); 364 hxge_status_t hxge_pfc_config_tcam_enable(p_hxge_t); 365 hxge_status_t hxge_pfc_config_tcam_disable(p_hxge_t); 366 hxge_status_t hxge_pfc_ip_class_config(p_hxge_t, tcam_class_t, uint32_t); 367 hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t, tcam_class_t, uint32_t *); 368 hxge_status_t hxge_pfc_mac_addrs_get(p_hxge_t hxgep); 369 370 371 hxge_status_t hxge_pfc_hw_reset(p_hxge_t hxgep); 372 hxge_status_t hxge_pfc_handle_sys_errors(p_hxge_t hxgep); 373 374 /* hxge_kstats.c */ 375 void hxge_init_statsp(p_hxge_t); 376 void hxge_setup_kstats(p_hxge_t); 377 void hxge_destroy_kstats(p_hxge_t); 378 int hxge_port_kstat_update(kstat_t *, int); 379 380 int hxge_m_stat(void *arg, uint_t stat, uint64_t *val); 381 382 /* hxge_hw.c */ 383 void 384 hxge_hw_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 385 void hxge_loopback_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 386 void hxge_global_reset(p_hxge_t); 387 uint_t hxge_intr(caddr_t arg1, caddr_t arg2); 388 void hxge_intr_enable(p_hxge_t hxgep); 389 void hxge_intr_disable(p_hxge_t hxgep); 390 void hxge_hw_id_init(p_hxge_t hxgep); 391 void hxge_hw_init_niu_common(p_hxge_t hxgep); 392 void hxge_intr_hw_enable(p_hxge_t hxgep); 393 void hxge_intr_hw_disable(p_hxge_t hxgep); 394 void hxge_hw_stop(p_hxge_t hxgep); 395 void hxge_global_reset(p_hxge_t hxgep); 396 void hxge_check_hw_state(p_hxge_t hxgep); 397 398 /* hxge_send.c. */ 399 uint_t hxge_reschedule(caddr_t arg); 400 401 /* hxge_ndd.c */ 402 void hxge_get_param_soft_properties(p_hxge_t); 403 void hxge_setup_param(p_hxge_t); 404 void hxge_init_param(p_hxge_t); 405 void hxge_destroy_param(p_hxge_t); 406 boolean_t hxge_check_rxdma_port_member(p_hxge_t, uint8_t); 407 boolean_t hxge_check_txdma_port_member(p_hxge_t, uint8_t); 408 int hxge_param_get_generic(p_hxge_t, queue_t *, mblk_t *, caddr_t); 409 int hxge_param_set_generic(p_hxge_t, queue_t *, mblk_t *, char *, caddr_t); 410 int hxge_get_default(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 411 int hxge_set_default(p_hxge_t, queue_t *, p_mblk_t, char *, caddr_t); 412 int hxge_nd_get_names(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 413 int hxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size); 414 void hxge_param_ioctl(p_hxge_t hxgep, queue_t *, mblk_t *, struct iocblk *); 415 boolean_t hxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 416 void hxge_nd_free(caddr_t *); 417 int hxge_nd_getset(p_hxge_t, queue_t *, caddr_t, p_mblk_t); 418 boolean_t hxge_set_lb(p_hxge_t, queue_t *wq, p_mblk_t mp); 419 int hxge_param_rx_intr_pkts(p_hxge_t hxgep, queue_t *, mblk_t *, char *, 420 caddr_t); 421 int hxge_param_rx_intr_time(p_hxge_t hxgep, queue_t *, mblk_t *, char *, 422 caddr_t); 423 int hxge_param_set_ip_opt(p_hxge_t hxgep, queue_t *, mblk_t *, char *, caddr_t); 424 int hxge_param_get_ip_opt(p_hxge_t hxgep, queue_t *, mblk_t *, caddr_t); 425 426 /* hxge_virtual.c */ 427 hxge_status_t hxge_get_config_properties(p_hxge_t); 428 hxge_status_t hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel, 429 p_tx_ring_t tx_ring_p, p_tx_mbox_t mbox_p); 430 hxge_status_t hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 431 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p); 432 hxge_status_t hxge_init_fzc_rx_common(p_hxge_t hxgep); 433 hxge_status_t hxge_init_fzc_rxdma_channel_pages(p_hxge_t hxgep, 434 uint16_t channel, p_rx_rbr_ring_t rbr_p); 435 hxge_status_t hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, 436 uint16_t channel, p_tx_ring_t tx_ring_p); 437 hxge_status_t hxge_intr_mask_mgmt_set(p_hxge_t hxgep, boolean_t on); 438 439 /* MAC functions */ 440 hxge_status_t hxge_vmac_init(p_hxge_t hxgep); 441 hxge_status_t hxge_link_init(p_hxge_t hxgep); 442 hxge_status_t hxge_tx_vmac_init(p_hxge_t hxgep); 443 hxge_status_t hxge_rx_vmac_init(p_hxge_t hxgep); 444 hxge_status_t hxge_tx_vmac_enable(p_hxge_t hxgep); 445 hxge_status_t hxge_tx_vmac_disable(p_hxge_t hxgep); 446 hxge_status_t hxge_rx_vmac_enable(p_hxge_t hxgep); 447 hxge_status_t hxge_rx_vmac_disable(p_hxge_t hxgep); 448 hxge_status_t hxge_tx_vmac_reset(p_hxge_t hxgep); 449 hxge_status_t hxge_rx_vmac_reset(p_hxge_t hxgep); 450 hxge_status_t hxge_add_mcast_addr(p_hxge_t, struct ether_addr *); 451 hxge_status_t hxge_del_mcast_addr(p_hxge_t, struct ether_addr *); 452 hxge_status_t hxge_pfc_set_mac_address(p_hxge_t hxgep, uint32_t slot, 453 struct ether_addr *addrp); 454 hxge_status_t hxge_pfc_num_macs_get(p_hxge_t hxgep, uint8_t *nmacs); 455 hxge_status_t hxge_pfc_clear_mac_address(p_hxge_t, uint32_t slot); 456 hxge_status_t hxge_set_promisc(p_hxge_t hxgep, boolean_t on); 457 void hxge_save_cntrs(p_hxge_t hxgep); 458 int hxge_vmac_set_framesize(p_hxge_t hxgep); 459 460 void hxge_debug_msg(p_hxge_t, uint64_t, char *, ...); 461 462 #ifdef HXGE_DEBUG 463 char *hxge_dump_packet(char *addr, int size); 464 #endif 465 466 #endif /* !_ASM */ 467 468 #ifdef __cplusplus 469 } 470 #endif 471 472 #endif /* _SYS_HXGE_HXGE_IMPL_H */ 473