1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_IMPL_H 27 #define _SYS_HXGE_HXGE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #ifndef _ASM 34 #include <sys/types.h> 35 #include <sys/byteorder.h> 36 #include <sys/debug.h> 37 #include <sys/stropts.h> 38 #include <sys/stream.h> 39 #include <sys/strlog.h> 40 #include <sys/strsubr.h> 41 #include <sys/cmn_err.h> 42 #include <sys/vtrace.h> 43 #include <sys/kmem.h> 44 #include <sys/ddi.h> 45 #include <sys/sunddi.h> 46 #include <sys/strsun.h> 47 #include <sys/stat.h> 48 #include <sys/cpu.h> 49 #include <sys/kstat.h> 50 #include <inet/common.h> 51 #include <inet/ip.h> 52 #include <inet/ip6.h> 53 #include <sys/dlpi.h> 54 #include <inet/nd.h> 55 #include <netinet/in.h> 56 #include <sys/ethernet.h> 57 #include <sys/vlan.h> 58 #include <sys/pci.h> 59 #include <sys/taskq.h> 60 #include <sys/atomic.h> 61 62 #include <hxge_defs.h> 63 #include <hxge_peu.h> 64 #include <hxge_pfc.h> 65 #include <hxge_pfc_hw.h> 66 #include <hxge_vmac.h> 67 #include <hxge_fm.h> 68 #include <sys/netlb.h> 69 #include <sys/ddi_intr.h> 70 71 #include <sys/mac_provider.h> 72 #include <sys/mac_ether.h> 73 74 /* 75 * Handy macros (taken from bge driver) 76 */ 77 #define RBR_SIZE 4 78 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 79 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 80 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 81 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 82 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 83 (area).offset, (area).alength, \ 84 (flag))) 85 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 86 ((void) ddi_dma_sync((area).dma_handle,\ 87 (area.offset + bufoffset), len, \ 88 (flag))) 89 90 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 91 #define NEXT_ENTRY_PTR(ptr, first, last) \ 92 ((ptr == last) ? first : (ptr + 1)) 93 94 /* 95 * HPI related macros 96 */ 97 #define HXGE_DEV_HPI_HANDLE(hxgep) (hxgep->hpi_handle) 98 99 #define HPI_PCI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_pci_handle.regh = ah) 100 #define HPI_PCI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_pci_handle.regp = ap) 101 102 #define HPI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_handle.regh = ah) 103 #define HPI_ADD_HANDLE_SET(hxgep, ap) \ 104 hxgep->hpi_handle.is_vraddr = B_FALSE; \ 105 hxgep->hpi_handle.function.instance = hxgep->instance; \ 106 hxgep->hpi_handle.function.function = 0; \ 107 hxgep->hpi_handle.hxgep = (void *) hxgep; \ 108 hxgep->hpi_handle.regp = ap; 109 110 #define HPI_REG_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_reg_handle.regh = ah) 111 #define HPI_REG_ADD_HANDLE_SET(hxgep, ap) \ 112 hxgep->hpi_reg_handle.is_vraddr = B_FALSE; \ 113 hxgep->hpi_handle.function.instance = hxgep->instance; \ 114 hxgep->hpi_handle.function.function = 0; \ 115 hxgep->hpi_reg_handle.hxgep = (void *) hxgep; \ 116 hxgep->hpi_reg_handle.regp = ap; 117 118 #define HPI_MSI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_msi_handle.regh = ah) 119 #define HPI_MSI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_msi_handle.regp = ap) 120 121 #define HPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->hpi_handle.regh = ah) 122 #define HPI_DMA_ACC_HANDLE_GET(dmap) (dmap->hpi_handle.regh) 123 124 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 125 126 typedef uint32_t hxge_status_t; 127 128 typedef enum { 129 DVMA, 130 DMA, 131 SDMA 132 } dma_method_t; 133 134 typedef enum { 135 BKSIZE_4K, 136 BKSIZE_8K, 137 BKSIZE_16K, 138 BKSIZE_32K 139 } hxge_rx_block_size_t; 140 141 #ifdef TX_ONE_BUF 142 #define TX_BCOPY_MAX 1514 143 #else 144 #define TX_BCOPY_MAX 2048 145 #define TX_BCOPY_SIZE 2048 146 #endif 147 148 #define TX_STREAM_MIN 512 149 #define TX_FASTDVMA_MIN 1024 150 151 #define HXGE_RDC_RCR_THRESHOLD_MAX 256 152 #define HXGE_RDC_RCR_TIMEOUT_MAX 64 153 #define HXGE_RDC_RCR_THRESHOLD_MIN 1 154 #define HXGE_RDC_RCR_TIMEOUT_MIN 1 155 156 #define HXGE_IS_VLAN_PACKET(ptr) \ 157 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 158 htons(VLAN_ETHERTYPE)) 159 160 typedef enum { 161 USE_NONE, 162 USE_BCOPY, 163 USE_DVMA, 164 USE_DMA, 165 USE_SDMA 166 } dma_type_t; 167 168 struct _hxge_block_mv_t { 169 uint32_t msg_type; 170 dma_type_t dma_type; 171 }; 172 173 typedef struct _hxge_block_mv_t hxge_block_mv_t, *p_hxge_block_mv_t; 174 175 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 176 typedef struct ether_header ether_header_t, *p_ether_header_t; 177 typedef queue_t *p_queue_t; 178 typedef mblk_t *p_mblk_t; 179 180 /* 181 * Common DMA data elements. 182 */ 183 struct _hxge_dma_common_t { 184 uint16_t dma_channel; 185 void *kaddrp; 186 void *ioaddr_pp; 187 ddi_dma_cookie_t dma_cookie; 188 uint32_t ncookies; 189 190 ddi_dma_handle_t dma_handle; 191 hxge_os_acc_handle_t acc_handle; 192 hpi_handle_t hpi_handle; 193 194 size_t block_size; 195 uint32_t nblocks; 196 size_t alength; 197 uint_t offset; 198 uint_t dma_chunk_index; 199 void *orig_ioaddr_pp; 200 uint64_t orig_vatopa; 201 void *orig_kaddrp; 202 size_t orig_alength; 203 boolean_t contig_alloc_type; 204 }; 205 206 typedef struct _hxge_t hxge_t, *p_hxge_t; 207 typedef struct _hxge_dma_common_t hxge_dma_common_t, *p_hxge_dma_common_t; 208 209 typedef struct _hxge_dma_pool_t { 210 p_hxge_dma_common_t *dma_buf_pool_p; 211 uint32_t ndmas; 212 uint32_t *num_chunks; 213 boolean_t buf_allocated; 214 } hxge_dma_pool_t, *p_hxge_dma_pool_t; 215 216 /* 217 * Each logical device (69): 218 * - LDG # 219 * - flag bits 220 * - masks. 221 * - interrupt handler function. 222 * 223 * Generic system interrupt handler with two arguments: 224 * (hxge_sys_intr_t) 225 * Per device instance data structure 226 * Logical group data structure. 227 * 228 * Logical device interrupt handler with two arguments: 229 * (hxge_ldv_intr_t) 230 * Per device instance data structure 231 * Logical device number 232 */ 233 typedef struct _hxge_ldg_t hxge_ldg_t, *p_hxge_ldg_t; 234 typedef struct _hxge_ldv_t hxge_ldv_t, *p_hxge_ldv_t; 235 typedef uint_t (*hxge_sys_intr_t)(caddr_t arg1, caddr_t arg2); 236 typedef uint_t (*hxge_ldv_intr_t)(caddr_t arg1, caddr_t arg2); 237 238 /* 239 * Each logical device Group (64) needs to have the following 240 * configurations: 241 * - timer counter (6 bits) 242 * - timer resolution (20 bits, number of system clocks) 243 * - system data (7 bits) 244 */ 245 struct _hxge_ldg_t { 246 uint8_t ldg; /* logical group number */ 247 uint8_t vldg_index; 248 boolean_t arm; 249 boolean_t interrupted; 250 uint16_t ldg_timer; /* counter */ 251 uint8_t vector; 252 uint8_t nldvs; 253 p_hxge_ldv_t ldvp; 254 hxge_sys_intr_t sys_intr_handler; 255 p_hxge_t hxgep; 256 }; 257 258 struct _hxge_ldv_t { 259 uint8_t ldg_assigned; 260 uint8_t ldv; 261 boolean_t is_rxdma; 262 boolean_t is_txdma; 263 boolean_t is_vmac; 264 boolean_t is_syserr; 265 boolean_t is_pfc; 266 boolean_t use_timer; 267 uint8_t channel; 268 uint8_t vdma_index; 269 p_hxge_ldg_t ldgp; 270 uint8_t ldv_ldf_masks; 271 hxge_ldv_intr_t ldv_intr_handler; 272 p_hxge_t hxgep; 273 }; 274 275 typedef struct _pci_cfg_t { 276 uint16_t vendorid; 277 uint16_t devid; 278 uint16_t command; 279 uint16_t status; 280 uint8_t revid; 281 uint8_t res0; 282 uint16_t junk1; 283 uint8_t cache_line; 284 uint8_t latency; 285 uint8_t header; 286 uint8_t bist; 287 uint32_t base; 288 uint32_t base14; 289 uint32_t base18; 290 uint32_t base1c; 291 uint32_t base20; 292 uint32_t base24; 293 uint32_t base28; 294 uint32_t base2c; 295 uint32_t base30; 296 uint32_t res1[2]; 297 uint8_t int_line; 298 uint8_t int_pin; 299 uint8_t min_gnt; 300 uint8_t max_lat; 301 } pci_cfg_t, *p_pci_cfg_t; 302 303 typedef struct _dev_regs_t { 304 hxge_os_acc_handle_t hxge_pciregh; /* PCI config DDI IO handle */ 305 p_pci_cfg_t hxge_pciregp; /* mapped PCI registers */ 306 307 hxge_os_acc_handle_t hxge_regh; /* device DDI IO (BAR 0) */ 308 void *hxge_regp; /* mapped device registers */ 309 310 hxge_os_acc_handle_t hxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 311 void *hxge_msix_regp; /* MSI/X register */ 312 313 hxge_os_acc_handle_t hxge_romh; /* fcode rom handle */ 314 unsigned char *hxge_romp; /* fcode pointer */ 315 } dev_regs_t, *p_dev_regs_t; 316 317 #include <hxge_common_impl.h> 318 #include <hxge_common.h> 319 #include <hxge_rxdma.h> 320 #include <hxge_txdma.h> 321 #include <hxge_fzc.h> 322 #include <hxge_flow.h> 323 #include <hxge_virtual.h> 324 #include <hxge.h> 325 #include <sys/modctl.h> 326 #include <sys/pattr.h> 327 #include <hpi_vir.h> 328 329 /* 330 * Reconfiguring the network devices requires the net_config privilege 331 * in Solaris 10+. Prior to this, root privilege is required. In order 332 * that the driver binary can run on both S10+ and earlier versions, we 333 * make the decisiion as to which to use at runtime. These declarations 334 * allow for either (or both) to exist ... 335 */ 336 extern int secpolicy_net_config(const cred_t *, boolean_t); 337 extern void hxge_fm_report_error(p_hxge_t hxgep, 338 uint8_t err_chan, hxge_fm_ereport_id_t fm_ereport_id); 339 extern int fm_check_acc_handle(ddi_acc_handle_t); 340 extern int fm_check_dma_handle(ddi_dma_handle_t); 341 342 #pragma weak secpolicy_net_config 343 344 hxge_status_t hxge_classify_init(p_hxge_t hxgep); 345 hxge_status_t hxge_classify_uninit(p_hxge_t hxgep); 346 void hxge_put_tcam(p_hxge_t hxgep, p_mblk_t mp); 347 void hxge_get_tcam(p_hxge_t hxgep, p_mblk_t mp); 348 349 hxge_status_t hxge_classify_init_hw(p_hxge_t hxgep); 350 hxge_status_t hxge_classify_init_sw(p_hxge_t hxgep); 351 hxge_status_t hxge_classify_exit_sw(p_hxge_t hxgep); 352 hxge_status_t hxge_pfc_ip_class_config_all(p_hxge_t hxgep); 353 hxge_status_t hxge_pfc_ip_class_config(p_hxge_t hxgep, tcam_class_t l3_class, 354 uint32_t class_config); 355 hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t hxgep, 356 tcam_class_t l3_class, uint32_t *class_config); 357 358 hxge_status_t hxge_pfc_set_hash(p_hxge_t, uint32_t); 359 hxge_status_t hxge_pfc_config_tcam_enable(p_hxge_t); 360 hxge_status_t hxge_pfc_config_tcam_disable(p_hxge_t); 361 hxge_status_t hxge_pfc_ip_class_config(p_hxge_t, tcam_class_t, uint32_t); 362 hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t, tcam_class_t, uint32_t *); 363 hxge_status_t hxge_pfc_num_macs_get(p_hxge_t, uint32_t *); 364 hxge_status_t hxge_pfc_mac_addrs_get(p_hxge_t hxgep); 365 366 367 hxge_status_t hxge_pfc_hw_reset(p_hxge_t hxgep); 368 hxge_status_t hxge_pfc_handle_sys_errors(p_hxge_t hxgep); 369 370 /* hxge_kstats.c */ 371 void hxge_init_statsp(p_hxge_t); 372 void hxge_setup_kstats(p_hxge_t); 373 void hxge_destroy_kstats(p_hxge_t); 374 int hxge_port_kstat_update(kstat_t *, int); 375 376 int hxge_m_stat(void *arg, uint_t stat, uint64_t *val); 377 378 /* hxge_hw.c */ 379 void 380 hxge_hw_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 381 void hxge_loopback_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 382 void hxge_global_reset(p_hxge_t); 383 uint_t hxge_intr(caddr_t arg1, caddr_t arg2); 384 void hxge_intr_enable(p_hxge_t hxgep); 385 void hxge_intr_disable(p_hxge_t hxgep); 386 void hxge_hw_id_init(p_hxge_t hxgep); 387 void hxge_hw_init_niu_common(p_hxge_t hxgep); 388 void hxge_intr_hw_enable(p_hxge_t hxgep); 389 void hxge_intr_hw_disable(p_hxge_t hxgep); 390 void hxge_hw_stop(p_hxge_t hxgep); 391 void hxge_global_reset(p_hxge_t hxgep); 392 void hxge_check_hw_state(p_hxge_t hxgep); 393 394 /* hxge_send.c. */ 395 uint_t hxge_reschedule(caddr_t arg); 396 397 /* hxge_ndd.c */ 398 void hxge_get_param_soft_properties(p_hxge_t); 399 void hxge_setup_param(p_hxge_t); 400 void hxge_init_param(p_hxge_t); 401 void hxge_destroy_param(p_hxge_t); 402 boolean_t hxge_check_rxdma_port_member(p_hxge_t, uint8_t); 403 boolean_t hxge_check_txdma_port_member(p_hxge_t, uint8_t); 404 int hxge_param_get_generic(p_hxge_t, queue_t *, mblk_t *, caddr_t); 405 int hxge_param_set_generic(p_hxge_t, queue_t *, mblk_t *, char *, caddr_t); 406 int hxge_get_default(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 407 int hxge_set_default(p_hxge_t, queue_t *, p_mblk_t, char *, caddr_t); 408 int hxge_nd_get_names(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 409 int hxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size); 410 void hxge_param_ioctl(p_hxge_t hxgep, queue_t *, mblk_t *, struct iocblk *); 411 boolean_t hxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 412 void hxge_nd_free(caddr_t *); 413 int hxge_nd_getset(p_hxge_t, queue_t *, caddr_t, p_mblk_t); 414 boolean_t hxge_set_lb(p_hxge_t, queue_t *wq, p_mblk_t mp); 415 int hxge_param_rx_intr_pkts(p_hxge_t hxgep, queue_t *, mblk_t *, char *, 416 caddr_t); 417 int hxge_param_rx_intr_time(p_hxge_t hxgep, queue_t *, mblk_t *, char *, 418 caddr_t); 419 int hxge_param_set_ip_opt(p_hxge_t hxgep, queue_t *, mblk_t *, char *, caddr_t); 420 int hxge_param_get_ip_opt(p_hxge_t hxgep, queue_t *, mblk_t *, caddr_t); 421 422 /* hxge_virtual.c */ 423 hxge_status_t hxge_get_config_properties(p_hxge_t); 424 hxge_status_t hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel, 425 p_tx_ring_t tx_ring_p, p_tx_mbox_t mbox_p); 426 hxge_status_t hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 427 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p); 428 hxge_status_t hxge_init_fzc_rx_common(p_hxge_t hxgep); 429 hxge_status_t hxge_init_fzc_rxdma_channel_pages(p_hxge_t hxgep, 430 uint16_t channel, p_rx_rbr_ring_t rbr_p); 431 hxge_status_t hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, 432 uint16_t channel, p_tx_ring_t tx_ring_p); 433 hxge_status_t hxge_intr_mask_mgmt_set(p_hxge_t hxgep, boolean_t on); 434 435 /* MAC functions */ 436 hxge_status_t hxge_vmac_init(p_hxge_t hxgep); 437 hxge_status_t hxge_link_init(p_hxge_t hxgep); 438 hxge_status_t hxge_tx_vmac_init(p_hxge_t hxgep); 439 hxge_status_t hxge_rx_vmac_init(p_hxge_t hxgep); 440 hxge_status_t hxge_tx_vmac_enable(p_hxge_t hxgep); 441 hxge_status_t hxge_tx_vmac_disable(p_hxge_t hxgep); 442 hxge_status_t hxge_rx_vmac_enable(p_hxge_t hxgep); 443 hxge_status_t hxge_rx_vmac_disable(p_hxge_t hxgep); 444 hxge_status_t hxge_tx_vmac_reset(p_hxge_t hxgep); 445 hxge_status_t hxge_rx_vmac_reset(p_hxge_t hxgep); 446 hxge_status_t hxge_add_mcast_addr(p_hxge_t, struct ether_addr *); 447 hxge_status_t hxge_del_mcast_addr(p_hxge_t, struct ether_addr *); 448 hxge_status_t hxge_set_mac_addr(p_hxge_t hxgep, struct ether_addr *addr); 449 hxge_status_t hxge_set_promisc(p_hxge_t hxgep, boolean_t on); 450 void hxge_save_cntrs(p_hxge_t hxgep); 451 int hxge_vmac_set_framesize(p_hxge_t hxgep); 452 453 void hxge_debug_msg(p_hxge_t, uint64_t, char *, ...); 454 455 #ifdef HXGE_DEBUG 456 char *hxge_dump_packet(char *addr, int size); 457 #endif 458 459 #endif /* !_ASM */ 460 461 #ifdef __cplusplus 462 } 463 #endif 464 465 #endif /* _SYS_HXGE_HXGE_IMPL_H */ 466