1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_COMMON_H 27 #define _SYS_HXGE_HXGE_COMMON_H 28 29 #include <sys/types.h> 30 #include <hxge_defs.h> 31 #include <hxge_pfc.h> 32 #include <hxge_common_impl.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #define HXGE_DMA_START B_TRUE 39 #define HXGE_DMA_STOP B_FALSE 40 #define HXGE_TIMER_RESO 2 41 #define HXGE_TIMER_LDG 2 42 43 /* 44 * Receive and Transmit DMA definitions 45 */ 46 #ifdef _DMA_USES_VIRTADDR 47 #define HXGE_DMA_BLOCK 1 48 #else 49 #define HXGE_DMA_BLOCK (64 * 64) 50 #endif 51 52 #define HXGE_RBR_RBB_MIN 128 53 #define HXGE_RBR_RBB_MAX (64 * 128 -1) 54 #define HXGE_RBR_RBB_DEFAULT 2048 /* Number of RBR Blocks */ 55 #define HXGE_RCR_MIN (HXGE_RBR_RBB_MIN * 2) 56 #define HXGE_RCR_MAX 65504 /* 2^16 - 32 */ 57 58 #if defined(__sparc) 59 #define HXGE_RCR_SZ HXGE_RCR_MAX 60 #else 61 #define HXGE_RCR_SZ HXGE_RBR_RBB_DEFAULT * (4096 / 256) 62 #endif 63 64 #define HXGE_RCR_DEFAULT HXGE_RCR_SZ 65 66 #define HXGE_TX_RING_DEFAULT 2048 67 #define HXGE_TX_RING_MAX (64 * 128 - 1) 68 69 #define RBR_BKSIZE_4K 0 70 #define RBR_BKSIZE_8K 1 71 #define RBR_BKSIZE_4K_BYTES (4 * 1024) 72 73 #define RBR_BUFSZ2_2K 0 74 #define RBR_BUFSZ2_4K 1 75 #define RBR_BUFSZ2_2K_BYTES (2 * 1024) 76 #define RBR_BUFSZ2_4K_BYTES (4 * 1024) 77 78 #define RBR_BUFSZ1_1K 0 79 #define RBR_BUFSZ1_2K 1 80 #define RBR_BUFSZ1_1K_BYTES 1024 81 #define RBR_BUFSZ1_2K_BYTES (2 * 1024) 82 83 #define RBR_BUFSZ0_256B 0 84 #define RBR_BUFSZ0_512B 1 85 #define RBR_BUFSZ0_1K 2 86 #define RBR_BUFSZ0_256_BYTES 256 87 #define RBR_BUFSZ0_512B_BYTES 512 88 #define RBR_BUFSZ0_1K_BYTES 1024 89 90 /* 91 * VLAN table configuration 92 */ 93 typedef struct hxge_mv_cfg { 94 uint8_t flag; /* 0:unconfigure 1:configured */ 95 } hxge_mv_cfg_t, *p_hxge_mv_cfg_t; 96 97 typedef struct hxge_param_map { 98 #if defined(_BIG_ENDIAN) 99 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 100 uint32_t remove:1; /* [29] Remove */ 101 uint32_t pref:1; /* [28] preference */ 102 uint32_t rsrv:4; /* [27:24] preference */ 103 uint32_t map_to:8; /* [23:16] map to resource */ 104 uint32_t param_id:16; /* [15:0] Param ID */ 105 #else 106 uint32_t param_id:16; /* [15:0] Param ID */ 107 uint32_t map_to:8; /* [23:16] map to resource */ 108 uint32_t rsrv:4; /* [27:24] preference */ 109 uint32_t pref:1; /* [28] preference */ 110 uint32_t remove:1; /* [29] Remove */ 111 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 112 #endif 113 } hxge_param_map_t, *p_hxge_param_map_t; 114 115 typedef struct hxge_hw_pt_cfg { 116 uint32_t start_tdc; /* start TDC (0 - 3) */ 117 uint32_t max_tdcs; /* max TDC in sequence */ 118 uint32_t start_rdc; /* start RDC (0 - 3) */ 119 uint32_t max_rdcs; /* max rdc in sequence */ 120 uint32_t rx_full_header; /* select the header flag */ 121 uint32_t start_ldg; /* starting logical group # */ 122 uint32_t max_ldgs; /* max logical device group */ 123 uint32_t max_ldvs; /* max logical devices */ 124 } hxge_hw_pt_cfg_t, *p_hxge_hw_pt_cfg_t; 125 126 /* per port configuration */ 127 typedef struct hxge_dma_pt_cfg { 128 hxge_hw_pt_cfg_t hw_config; /* hardware configuration */ 129 130 uint32_t alloc_buf_size; 131 uint32_t rbr_size; 132 uint32_t rcr_size; 133 } hxge_dma_pt_cfg_t, *p_hxge_dma_pt_cfg_t; 134 135 /* classification configuration */ 136 typedef struct hxge_class_pt_cfg { 137 /* VLAN table */ 138 hxge_mv_cfg_t vlan_tbl[VLAN_ID_MAX + 1]; 139 /* class config value */ 140 uint32_t init_hash; 141 uint32_t class_cfg[TCAM_CLASS_MAX]; 142 } hxge_class_pt_cfg_t, *p_hxge_class_pt_cfg_t; 143 144 typedef struct hxge_hw_list { 145 struct hxge_hw_list *next; 146 hxge_os_mutex_t hxge_cfg_lock; 147 hxge_os_mutex_t hxge_tcam_lock; 148 hxge_os_mutex_t hxge_vlan_lock; 149 150 hxge_dev_info_t *parent_devp; 151 struct _hxge_t *hxge_p; 152 uint32_t ndevs; 153 uint32_t flags; 154 uint32_t magic; 155 } hxge_hw_list_t, *p_hxge_hw_list_t; 156 157 #ifdef __cplusplus 158 } 159 #endif 160 161 #endif /* _SYS_HXGE_HXGE_COMMON_H */ 162