1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * ********************************************************************** 37 * Module Name: * 38 * e1000g_sw.h * 39 * * 40 * Abstract: * 41 * This header file contains Software-related data structures * 42 * definitions. * 43 * * 44 * ********************************************************************** 45 */ 46 47 #include <sys/types.h> 48 #include <sys/conf.h> 49 #include <sys/debug.h> 50 #include <sys/stropts.h> 51 #include <sys/stream.h> 52 #include <sys/strsun.h> 53 #include <sys/strlog.h> 54 #include <sys/kmem.h> 55 #include <sys/stat.h> 56 #include <sys/kstat.h> 57 #include <sys/modctl.h> 58 #include <sys/errno.h> 59 #include <sys/mac.h> 60 #include <sys/mac_ether.h> 61 #include <sys/vlan.h> 62 #include <sys/ddi.h> 63 #include <sys/sunddi.h> 64 #include <sys/pci.h> 65 #include <sys/sdt.h> 66 #include <sys/ethernet.h> 67 #include <sys/pattr.h> 68 #include <sys/strsubr.h> 69 #include <sys/netlb.h> 70 #include <inet/common.h> 71 #include <inet/ip.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include "e1000_api.h" 75 76 77 #define JUMBO_FRAG_LENGTH 4096 78 79 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 80 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 81 #define MAX_NUM_MULTICAST_ADDRESSES 256 82 83 #define MAX_TX_DESC_PER_PACKET 16 84 85 /* 86 * constants used in setting flow control thresholds 87 */ 88 #define E1000_PBA_MASK 0xffff 89 #define E1000_PBA_SHIFT 10 90 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 91 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 92 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 93 94 #define MAX_NUM_TX_DESCRIPTOR 4096 95 #define MAX_NUM_RX_DESCRIPTOR 4096 96 #define MAX_NUM_RX_FREELIST 4096 97 #define MAX_NUM_TX_FREELIST 4096 98 #define MAX_RX_LIMIT_ON_INTR 4096 99 #define MAX_RX_INTR_DELAY 65535 100 #define MAX_RX_INTR_ABS_DELAY 65535 101 #define MAX_TX_INTR_DELAY 65535 102 #define MAX_TX_INTR_ABS_DELAY 65535 103 #define MAX_INTR_THROTTLING 65535 104 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 105 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 106 107 #define MIN_NUM_TX_DESCRIPTOR 80 108 #define MIN_NUM_RX_DESCRIPTOR 80 109 #define MIN_NUM_RX_FREELIST 64 110 #define MIN_NUM_TX_FREELIST 80 111 #define MIN_RX_LIMIT_ON_INTR 16 112 #define MIN_RX_INTR_DELAY 0 113 #define MIN_RX_INTR_ABS_DELAY 0 114 #define MIN_TX_INTR_DELAY 0 115 #define MIN_TX_INTR_ABS_DELAY 0 116 #define MIN_INTR_THROTTLING 0 117 #define MIN_RX_BCOPY_THRESHOLD 0 118 #define MIN_TX_BCOPY_THRESHOLD MINIMUM_ETHERNET_PACKET_SIZE 119 120 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 121 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 122 #define DEFAULT_NUM_RX_FREELIST 4096 123 #define DEFAULT_NUM_TX_FREELIST 2048 124 #define DEFAULT_RX_LIMIT_ON_INTR 256 125 #define DEFAULT_RX_INTR_DELAY 0 126 #define DEFAULT_RX_INTR_ABS_DELAY 0 127 #define DEFAULT_TX_INTR_DELAY 300 128 #define DEFAULT_TX_INTR_ABS_DELAY 0 129 #define DEFAULT_INTR_THROTTLING 0x225 130 #define DEFAULT_RX_BCOPY_THRESHOLD 0 131 #define DEFAULT_TX_BCOPY_THRESHOLD 512 132 133 #define DEFAULT_TX_RECYCLE_LOW_WATER 64 134 #define DEFAULT_TX_RECYCLE_NUM 128 135 #define DEFAULT_TX_INTR_ENABLE 1 136 #define DEFAULT_FLOW_CONTROL 3 137 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 138 /* which is normally 0x040 */ 139 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 140 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 141 142 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 143 144 /* 145 * The size of the receive/transmite buffers 146 */ 147 #define E1000_RX_BUFFER_SIZE_2K (2048) 148 #define E1000_RX_BUFFER_SIZE_4K (4096) 149 #define E1000_RX_BUFFER_SIZE_8K (8192) 150 #define E1000_RX_BUFFER_SIZE_16K (16384) 151 152 #define E1000_TX_BUFFER_SIZE_2K (2048) 153 #define E1000_TX_BUFFER_SIZE_4K (4096) 154 #define E1000_TX_BUFFER_SIZE_8K (8192) 155 #define E1000_TX_BUFFER_SIZE_16K (16384) 156 157 #define FORCE_BCOPY_EXCEED_FRAGS 0x1 158 #define FORCE_BCOPY_UNDER_SIZE 0x2 159 160 #define E1000G_RX_SW_FREE 0x0 161 #define E1000G_RX_SW_SENDUP 0x1 162 #define E1000G_RX_SW_STOP 0x2 163 #define E1000G_RX_SW_DETACH 0x3 164 165 /* 166 * definitions for smartspeed workaround 167 */ 168 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 169 /* or 30 seconds */ 170 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 171 /* or 6 seconds */ 172 173 /* 174 * Definitions for module_info. 175 */ 176 #define WSNAME "e1000g" /* module name */ 177 178 /* 179 * Defined for IP header alignment. We also need to preserve space for 180 * VLAN tag (4 bytes) 181 */ 182 #define E1000G_IPALIGNROOM 6 183 #define E1000G_IPALIGNPRESERVEROOM 64 184 185 #define E1000G_IMS_TX_INTR (E1000_IMS_TXDW | E1000_IMS_TXQE) 186 #define E1000G_ICR_TX_INTR (E1000_ICR_TXDW | E1000_ICR_TXQE) 187 188 /* 189 * bit flags for 'attach_progress' which is a member variable in struct e1000g 190 */ 191 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 192 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 193 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 194 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 195 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 196 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 197 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 198 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 199 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 200 #define ATTACH_PROGRESS_NDD 0x0200 /* NDD initialized */ 201 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 202 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 203 204 /* 205 * Speed and Duplex Settings 206 */ 207 #define GDIAG_10_HALF 1 208 #define GDIAG_10_FULL 2 209 #define GDIAG_100_HALF 3 210 #define GDIAG_100_FULL 4 211 #define GDIAG_1000_FULL 6 212 #define GDIAG_ANY 7 213 214 /* 215 * Coexist Workaround RP: 07/04/03 216 * 82544 Workaround : Co-existence 217 */ 218 #define MAX_TX_BUF_SIZE (8 * 1024) 219 220 #define ROUNDOFF 0x1000 221 222 /* 223 * Defines for Jumbo Frame 224 */ 225 #define FRAME_SIZE_UPTO_2K 2048 226 #define FRAME_SIZE_UPTO_4K 4096 227 #define FRAME_SIZE_UPTO_8K 8192 228 #define FRAME_SIZE_UPTO_16K 16384 229 #define FRAME_SIZE_UPTO_9K 9234 230 231 /* The sizes (in bytes) of a ethernet packet */ 232 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ 233 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 234 #define ETHERNET_FCS_SIZE 4 235 #define MAXIMUM_ETHERNET_PACKET_SIZE \ 236 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 237 #define MINIMUM_ETHERNET_PACKET_SIZE \ 238 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 239 #define CRC_LENGTH ETHERNET_FCS_SIZE 240 241 /* Defines for Tx stall check */ 242 #define E1000G_STALL_WATCHDOG_COUNT 8 243 244 #define MAX_TX_LINK_DOWN_TIMEOUT 8 245 246 /* Defines for DVMA */ 247 #ifdef __sparc 248 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 249 #endif 250 251 /* 252 * Loopback definitions 253 */ 254 #define E1000G_LB_NONE 0 255 #define E1000G_LB_EXTERNAL_1000 1 256 #define E1000G_LB_EXTERNAL_100 2 257 #define E1000G_LB_EXTERNAL_10 3 258 #define E1000G_LB_INTERNAL_PHY 4 259 260 /* 261 * Private dip list definitions 262 */ 263 #define E1000G_PRIV_DEVI_ATTACH 0x0 264 #define E1000G_PRIV_DEVI_DETACH 0x1 265 266 /* 267 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 268 */ 269 #define QUEUE_INIT_LIST(_LH) \ 270 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 271 272 /* 273 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 274 */ 275 #define IS_QUEUE_EMPTY(_LH) \ 276 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 277 278 /* 279 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 280 * not remove the head from the queue. 281 */ 282 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 283 284 /* 285 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 286 */ 287 #define QUEUE_REMOVE_HEAD(_LH) \ 288 { \ 289 PSINGLE_LIST_LINK ListElem; \ 290 if (ListElem = (_LH)->Flink) \ 291 { \ 292 if (!((_LH)->Flink = ListElem->Flink)) \ 293 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 294 } \ 295 } 296 297 /* 298 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 299 * and return it (this differs from QUEUE_REMOVE_HEAD only in 300 * the 1st line). 301 */ 302 #define QUEUE_POP_HEAD(_LH) \ 303 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 304 { \ 305 PSINGLE_LIST_LINK ListElem; \ 306 ListElem = (_LH)->Flink; \ 307 if (ListElem) \ 308 { \ 309 (_LH)->Flink = ListElem->Flink; \ 310 if (!(_LH)->Flink) \ 311 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 312 } \ 313 } 314 315 /* 316 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 317 * remove the tail from the queue. 318 */ 319 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 320 321 /* 322 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 323 */ 324 #define QUEUE_PUSH_TAIL(_LH, _E) \ 325 if ((_LH)->Blink) \ 326 { \ 327 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 328 (PSINGLE_LIST_LINK)(_E); \ 329 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 330 } else { \ 331 (_LH)->Flink = \ 332 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 333 } \ 334 (_E)->Flink = (PSINGLE_LIST_LINK)0; 335 336 /* 337 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 338 */ 339 #define QUEUE_PUSH_HEAD(_LH, _E) \ 340 if (!((_E)->Flink = (_LH)->Flink)) \ 341 { \ 342 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 343 } \ 344 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 345 346 /* 347 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 348 * current element. 349 */ 350 #define QUEUE_GET_NEXT(_LH, _E) \ 351 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 352 (0) : ((_E)->Flink)) 353 354 /* 355 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 356 */ 357 #define QUEUE_APPEND(_LH1, _LH2) \ 358 if ((_LH2)->Flink) { \ 359 if ((_LH1)->Flink) { \ 360 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 361 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 362 } else { \ 363 (_LH1)->Flink = \ 364 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 365 } \ 366 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 367 } 368 369 /* 370 * Property lookups 371 */ 372 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 373 DDI_PROP_DONTPASS, (n)) 374 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 375 DDI_PROP_DONTPASS, (n), -1) 376 377 /* 378 * Shorthand for the NDD parameters 379 */ 380 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 381 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 382 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 383 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 384 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 385 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 386 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 387 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 388 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 389 #define param_force_speed_duplex nd_params[PARAM_FORCE_SPEED_DUPLEX].ndp_val 390 391 #ifdef E1000G_DEBUG 392 /* 393 * E1000G-specific ioctls ... 394 */ 395 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 396 + 'K') << 4) + 'G') << 4) 397 398 /* 399 * These diagnostic IOCTLS are enabled only in DEBUG drivers 400 */ 401 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 402 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 403 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 404 405 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 406 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 407 408 typedef struct { 409 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 410 uint64_t pp_acc_space; /* See #defines below */ 411 uint64_t pp_acc_offset; /* See regs definition */ 412 uint64_t pp_acc_data; /* output for peek */ 413 /* input for poke */ 414 } e1000g_peekpoke_t; 415 #endif /* E1000G_DEBUG */ 416 417 /* 418 * (Internal) return values from ioctl subroutines 419 */ 420 enum ioc_reply { 421 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 422 IOC_DONE, /* OK, reply sent */ 423 IOC_ACK, /* OK, just send ACK */ 424 IOC_REPLY /* OK, just send reply */ 425 }; 426 427 /* 428 * Named Data (ND) Parameter Management Structure 429 */ 430 typedef struct { 431 uint32_t ndp_info; 432 uint32_t ndp_min; 433 uint32_t ndp_max; 434 uint32_t ndp_val; 435 struct e1000g *ndp_instance; 436 char *ndp_name; 437 } nd_param_t; 438 439 /* 440 * NDD parameter indexes, divided into: 441 * 442 * read-only parameters describing the hardware's capabilities 443 * read-write parameters controlling the advertised capabilities 444 * read-only parameters describing the partner's capabilities 445 * read-write parameters controlling the force speed and duplex 446 * read-only parameters describing the link state 447 * read-only parameters describing the driver properties 448 * read-write parameters controlling the driver properties 449 */ 450 enum { 451 PARAM_AUTONEG_CAP, 452 PARAM_PAUSE_CAP, 453 PARAM_ASYM_PAUSE_CAP, 454 PARAM_1000FDX_CAP, 455 PARAM_1000HDX_CAP, 456 PARAM_100T4_CAP, 457 PARAM_100FDX_CAP, 458 PARAM_100HDX_CAP, 459 PARAM_10FDX_CAP, 460 PARAM_10HDX_CAP, 461 462 PARAM_ADV_AUTONEG_CAP, 463 PARAM_ADV_PAUSE_CAP, 464 PARAM_ADV_ASYM_PAUSE_CAP, 465 PARAM_ADV_1000FDX_CAP, 466 PARAM_ADV_1000HDX_CAP, 467 PARAM_ADV_100T4_CAP, 468 PARAM_ADV_100FDX_CAP, 469 PARAM_ADV_100HDX_CAP, 470 PARAM_ADV_10FDX_CAP, 471 PARAM_ADV_10HDX_CAP, 472 473 PARAM_LP_AUTONEG_CAP, 474 PARAM_LP_PAUSE_CAP, 475 PARAM_LP_ASYM_PAUSE_CAP, 476 PARAM_LP_1000FDX_CAP, 477 PARAM_LP_1000HDX_CAP, 478 PARAM_LP_100T4_CAP, 479 PARAM_LP_100FDX_CAP, 480 PARAM_LP_100HDX_CAP, 481 PARAM_LP_10FDX_CAP, 482 PARAM_LP_10HDX_CAP, 483 484 PARAM_FORCE_SPEED_DUPLEX, 485 486 PARAM_LINK_STATUS, 487 PARAM_LINK_SPEED, 488 PARAM_LINK_DUPLEX, 489 PARAM_LINK_AUTONEG, 490 491 PARAM_MAX_FRAME_SIZE, 492 PARAM_LOOP_MODE, 493 PARAM_INTR_TYPE, 494 495 PARAM_TX_BCOPY_THRESHOLD, 496 PARAM_TX_INTR_ENABLE, 497 PARAM_TX_TIDV, 498 PARAM_TX_TADV, 499 PARAM_RX_BCOPY_THRESHOLD, 500 PARAM_RX_PKT_ON_INTR, 501 PARAM_RX_RDTR, 502 PARAM_RX_RADV, 503 504 PARAM_COUNT 505 }; 506 507 /* 508 * The entry of the private dip list 509 */ 510 typedef struct _private_devi_list { 511 dev_info_t *priv_dip; 512 uint16_t flag; 513 struct _private_devi_list *next; 514 } private_devi_list_t; 515 516 /* 517 * A structure that points to the next entry in the queue. 518 */ 519 typedef struct _SINGLE_LIST_LINK { 520 struct _SINGLE_LIST_LINK *Flink; 521 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 522 523 /* 524 * A "ListHead" structure that points to the head and tail of a queue 525 */ 526 typedef struct _LIST_DESCRIBER { 527 struct _SINGLE_LIST_LINK *volatile Flink; 528 struct _SINGLE_LIST_LINK *volatile Blink; 529 } LIST_DESCRIBER, *PLIST_DESCRIBER; 530 531 /* 532 * Address-Length pair structure that stores descriptor info 533 */ 534 typedef struct _sw_desc { 535 uint64_t address; 536 uint32_t length; 537 } sw_desc_t, *p_sw_desc_t; 538 539 typedef struct _desc_array { 540 sw_desc_t descriptor[4]; 541 uint32_t elements; 542 } desc_array_t, *p_desc_array_t; 543 544 typedef enum { 545 USE_NONE, 546 USE_BCOPY, 547 USE_DVMA, 548 USE_DMA 549 } dma_type_t; 550 551 typedef struct _dma_buffer { 552 caddr_t address; 553 uint64_t dma_address; 554 ddi_acc_handle_t acc_handle; 555 ddi_dma_handle_t dma_handle; 556 size_t size; 557 size_t len; 558 } dma_buffer_t, *p_dma_buffer_t; 559 560 /* 561 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 562 * structure stores the additional information that is 563 * associated with every packet to be transmitted. It stores the 564 * message block pointer and the TBD addresses associated with 565 * the m_blk and also the link to the next tcb in the chain 566 */ 567 typedef struct _tx_sw_packet { 568 /* Link to the next tx_sw_packet in the list */ 569 SINGLE_LIST_LINK Link; 570 mblk_t *mp; 571 uint32_t num_desc; 572 uint32_t num_mblk_frag; 573 dma_type_t dma_type; 574 dma_type_t data_transfer_type; 575 ddi_dma_handle_t tx_dma_handle; 576 dma_buffer_t tx_buf[1]; 577 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 578 } tx_sw_packet_t, *p_tx_sw_packet_t; 579 580 /* 581 * This structure is similar to the rx_sw_packet structure used 582 * for Ndis. This structure stores information about the 2k 583 * aligned receive buffer into which the FX1000 DMA's frames. 584 * This structure is maintained as a linked list of many 585 * receiver buffer pointers. 586 */ 587 typedef struct _rx_sw_packet { 588 /* Link to the next rx_sw_packet_t in the list */ 589 SINGLE_LIST_LINK Link; 590 struct _rx_sw_packet *next; 591 uint16_t flag; 592 mblk_t *mp; 593 caddr_t rx_ring; 594 dma_type_t dma_type; 595 frtn_t free_rtn; 596 dma_buffer_t rx_buf[1]; 597 } rx_sw_packet_t, *p_rx_sw_packet_t; 598 599 typedef struct _mblk_list { 600 mblk_t *head; 601 mblk_t *tail; 602 } mblk_list_t, *p_mblk_list_t; 603 604 typedef struct _cksum_data { 605 uint32_t ether_header_size; 606 uint32_t cksum_flags; 607 uint32_t cksum_start; 608 uint32_t cksum_stuff; 609 } cksum_data_t; 610 611 typedef union _e1000g_ether_addr { 612 struct { 613 uint32_t high; 614 uint32_t low; 615 } reg; 616 struct { 617 uint8_t set; 618 uint8_t redundant; 619 uint8_t addr[ETHERADDRL]; 620 } mac; 621 } e1000g_ether_addr_t; 622 623 typedef struct _e1000g_stat { 624 625 kstat_named_t link_speed; /* Link Speed */ 626 kstat_named_t reset_count; /* Reset Count */ 627 628 kstat_named_t rx_error; /* Rx Error in Packet */ 629 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 630 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 631 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 632 633 kstat_named_t tx_no_desc; /* Tx No Desc */ 634 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 635 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 636 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 637 kstat_named_t tx_reschedule; /* Tx Reschedule */ 638 639 #ifdef E1000G_DEBUG 640 kstat_named_t rx_none; /* Rx No Incoming Data */ 641 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 642 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 643 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 644 645 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 646 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 647 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 648 kstat_named_t tx_recycle; /* Tx Recycle */ 649 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 650 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 651 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 652 kstat_named_t tx_copy; /* Tx Send Copy */ 653 kstat_named_t tx_bind; /* Tx Send Bind */ 654 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 655 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 656 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 657 #endif 658 659 kstat_named_t Crcerrs; /* CRC Error Count */ 660 kstat_named_t Symerrs; /* Symbol Error Count */ 661 kstat_named_t Mpc; /* Missed Packet Count */ 662 kstat_named_t Scc; /* Single Collision Count */ 663 kstat_named_t Ecol; /* Excessive Collision Count */ 664 kstat_named_t Mcc; /* Multiple Collision Count */ 665 kstat_named_t Latecol; /* Late Collision Count */ 666 kstat_named_t Colc; /* Collision Count */ 667 kstat_named_t Dc; /* Defer Count */ 668 kstat_named_t Sec; /* Sequence Error Count */ 669 kstat_named_t Rlec; /* Receive Length Error Count */ 670 kstat_named_t Xonrxc; /* XON Received Count */ 671 kstat_named_t Xontxc; /* XON Xmitted Count */ 672 kstat_named_t Xoffrxc; /* XOFF Received Count */ 673 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 674 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 675 kstat_named_t Prc64; /* Packets Received - 64b */ 676 kstat_named_t Prc127; /* Packets Received - 65-127b */ 677 kstat_named_t Prc255; /* Packets Received - 127-255b */ 678 kstat_named_t Prc511; /* Packets Received - 256-511b */ 679 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 680 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 681 kstat_named_t Gprc; /* Good Packets Received Count */ 682 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 683 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 684 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 685 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 686 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 687 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 688 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 689 kstat_named_t Rnbc; /* Receive No Buffers Count */ 690 kstat_named_t Ruc; /* Receive Undersize Count */ 691 kstat_named_t Rfc; /* Receive Frag Count */ 692 kstat_named_t Roc; /* Receive Oversize Count */ 693 kstat_named_t Rjc; /* Receive Jabber Count */ 694 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 695 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 696 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 697 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 698 kstat_named_t Tpr; /* Total Packets Received */ 699 kstat_named_t Tpt; /* Total Packets Xmitted */ 700 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 701 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 702 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 703 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 704 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 705 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 706 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 707 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 708 kstat_named_t Algnerrc; /* Alignment Error count */ 709 kstat_named_t Tuc; /* Transmit Underrun count */ 710 kstat_named_t Rxerrc; /* Rx Error Count */ 711 kstat_named_t Tncrs; /* Transmit with no CRS */ 712 kstat_named_t Cexterr; /* Carrier Extension Error count */ 713 kstat_named_t Rutec; /* Receive DMA too Early count */ 714 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 715 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 716 } e1000g_stat_t, *p_e1000g_stat_t; 717 718 typedef struct _e1000g_tx_ring { 719 kmutex_t tx_lock; 720 kmutex_t freelist_lock; 721 kmutex_t usedlist_lock; 722 kmutex_t mblks_lock; 723 /* 724 * Descriptor queue definitions 725 */ 726 ddi_dma_handle_t tbd_dma_handle; 727 ddi_acc_handle_t tbd_acc_handle; 728 struct e1000_tx_desc *tbd_area; 729 uint64_t tbd_dma_addr; 730 struct e1000_tx_desc *tbd_first; 731 struct e1000_tx_desc *tbd_last; 732 struct e1000_tx_desc *tbd_oldest; 733 struct e1000_tx_desc *tbd_next; 734 uint32_t tbd_avail; 735 /* 736 * Software packet structures definitions 737 */ 738 p_tx_sw_packet_t packet_area; 739 LIST_DESCRIBER used_list; 740 LIST_DESCRIBER free_list; 741 /* 742 * TCP/UDP checksum offload 743 */ 744 cksum_data_t cksum_data; 745 /* 746 * Timer definitions for 82547 747 */ 748 timeout_id_t timer_id_82547; 749 boolean_t timer_enable_82547; 750 /* 751 * reschedule when tx resource is available 752 */ 753 boolean_t resched_needed; 754 uint32_t recycle_low_water; 755 uint32_t recycle_num; 756 uint32_t frags_limit; 757 uint32_t stall_watchdog; 758 uint32_t recycle_fail; 759 mblk_list_t mblks; 760 /* 761 * Statistics 762 */ 763 uint32_t stat_no_swpkt; 764 uint32_t stat_no_desc; 765 uint32_t stat_send_fail; 766 uint32_t stat_reschedule; 767 uint32_t stat_over_size; 768 #ifdef E1000G_DEBUG 769 uint32_t stat_under_size; 770 uint32_t stat_exceed_frags; 771 uint32_t stat_empty_frags; 772 uint32_t stat_recycle; 773 uint32_t stat_recycle_intr; 774 uint32_t stat_recycle_retry; 775 uint32_t stat_recycle_none; 776 uint32_t stat_copy; 777 uint32_t stat_bind; 778 uint32_t stat_multi_copy; 779 uint32_t stat_multi_cookie; 780 uint32_t stat_lack_desc; 781 #endif 782 /* 783 * Pointer to the adapter 784 */ 785 struct e1000g *adapter; 786 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 787 788 typedef struct _e1000g_rx_ring { 789 kmutex_t rx_lock; 790 kmutex_t freelist_lock; 791 /* 792 * Descriptor queue definitions 793 */ 794 ddi_dma_handle_t rbd_dma_handle; 795 ddi_acc_handle_t rbd_acc_handle; 796 struct e1000_rx_desc *rbd_area; 797 uint64_t rbd_dma_addr; 798 struct e1000_rx_desc *rbd_first; 799 struct e1000_rx_desc *rbd_last; 800 struct e1000_rx_desc *rbd_next; 801 /* 802 * Software packet structures definitions 803 */ 804 p_rx_sw_packet_t packet_area; 805 LIST_DESCRIBER recv_list; 806 LIST_DESCRIBER free_list; 807 808 p_rx_sw_packet_t pending_list; 809 uint32_t pending_count; 810 uint32_t avail_freepkt; 811 uint32_t rx_mblk_len; 812 mblk_t *rx_mblk; 813 mblk_t *rx_mblk_tail; 814 /* 815 * Statistics 816 */ 817 uint32_t stat_error; 818 uint32_t stat_esballoc_fail; 819 uint32_t stat_allocb_fail; 820 uint32_t stat_exceed_pkt; 821 #ifdef E1000G_DEBUG 822 uint32_t stat_none; 823 uint32_t stat_multi_desc; 824 uint32_t stat_no_freepkt; 825 #endif 826 /* 827 * Pointer to the adapter 828 */ 829 struct e1000g *adapter; 830 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 831 832 typedef struct e1000g { 833 int instance; 834 dev_info_t *dip; 835 dev_info_t *priv_dip; 836 mac_handle_t mh; 837 mac_resource_handle_t mrh; 838 struct e1000_hw shared; 839 struct e1000g_osdep osdep; 840 841 boolean_t started; 842 boolean_t e1000g_promisc; 843 boolean_t strip_crc; 844 boolean_t rx_buffer_setup; 845 link_state_t link_state; 846 uint32_t link_speed; 847 uint32_t link_duplex; 848 uint32_t master_latency_timer; 849 uint32_t smartspeed; /* smartspeed w/a counter */ 850 uint32_t init_count; 851 uint32_t reset_count; 852 uint32_t attach_progress; /* attach tracking */ 853 uint32_t loopback_mode; 854 855 uint32_t tx_desc_num; 856 uint32_t tx_freelist_num; 857 uint32_t rx_desc_num; 858 uint32_t rx_freelist_num; 859 uint32_t tx_buffer_size; 860 uint32_t rx_buffer_size; 861 862 uint32_t tx_link_down_timeout; 863 uint32_t tx_bcopy_thresh; 864 uint32_t rx_limit_onintr; 865 uint32_t rx_bcopy_thresh; 866 #ifndef NO_82542_SUPPORT 867 uint32_t rx_buf_align; 868 #endif 869 870 boolean_t intr_adaptive; 871 boolean_t tx_intr_enable; 872 uint32_t tx_intr_delay; 873 uint32_t tx_intr_abs_delay; 874 uint32_t rx_intr_delay; 875 uint32_t rx_intr_abs_delay; 876 uint32_t intr_throttling_rate; 877 878 boolean_t watchdog_timer_enabled; 879 boolean_t watchdog_timer_started; 880 timeout_id_t watchdog_tid; 881 boolean_t link_complete; 882 timeout_id_t link_tid; 883 884 e1000g_rx_ring_t rx_ring[1]; 885 e1000g_tx_ring_t tx_ring[1]; 886 887 /* 888 * The watchdog_lock must be held when updateing the 889 * timeout fields in struct e1000g, that is, 890 * watchdog_tid, watchdog_timer_started. 891 */ 892 kmutex_t watchdog_lock; 893 /* 894 * The link_lock protects the link fields in struct e1000g, 895 * such as link_state, link_speed, link_duplex, link_complete, and 896 * link_tid. 897 */ 898 kmutex_t link_lock; 899 /* 900 * The chip_lock assures that the Rx/Tx process must be 901 * stopped while other functions change the hardware 902 * configuration of e1000g card, such as e1000g_reset(), 903 * e1000g_reset_hw() etc are executed. 904 */ 905 krwlock_t chip_lock; 906 907 uint32_t unicst_avail; 908 uint32_t unicst_total; 909 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 910 911 uint32_t mcast_count; 912 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 913 914 #ifdef __sparc 915 ulong_t sys_page_sz; 916 uint_t dvma_page_num; 917 #endif 918 919 boolean_t msi_enabled; 920 int intr_type; 921 int intr_cnt; 922 int intr_cap; 923 size_t intr_size; 924 uint_t intr_pri; 925 ddi_intr_handle_t *htable; 926 927 int tx_softint_pri; 928 ddi_softint_handle_t tx_softint_handle; 929 930 kstat_t *e1000g_ksp; 931 932 /* 933 * NDD parameters 934 */ 935 caddr_t nd_data; 936 nd_param_t nd_params[PARAM_COUNT]; 937 938 } e1000g_t; 939 940 941 /* 942 * Function prototypes 943 */ 944 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 945 void e1000g_release_dma_resources(struct e1000g *Adapter); 946 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 947 void e1000g_tx_setup(struct e1000g *Adapter); 948 void e1000g_rx_setup(struct e1000g *Adapter); 949 void e1000g_setup_multicast(struct e1000g *Adapter); 950 boolean_t e1000g_reset(struct e1000g *Adapter); 951 952 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 953 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 954 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 955 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 956 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 957 mblk_t *e1000g_receive(struct e1000g *Adapter); 958 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 959 960 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 961 int e1000g_init_stats(struct e1000g *Adapter); 962 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 963 uint32_t frame_len, uint8_t *mac_addr); 964 enum ioc_reply e1000g_nd_ioctl(struct e1000g *Adapter, 965 queue_t *wq, mblk_t *mp, struct iocblk *iocp); 966 void e1000g_nd_cleanup(struct e1000g *Adapter); 967 int e1000g_nd_init(struct e1000g *Adapter); 968 969 void e1000g_clear_interrupt(struct e1000g *Adapter); 970 void e1000g_mask_interrupt(struct e1000g *Adapter); 971 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 972 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 973 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 974 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 975 void e1000_enable_pciex_master(struct e1000_hw *hw); 976 977 #pragma inline(e1000_rar_set) 978 979 /* 980 * Global variables 981 */ 982 extern boolean_t e1000g_force_detach; 983 extern uint32_t e1000g_mblks_pending; 984 extern krwlock_t e1000g_rx_detach_lock; 985 extern private_devi_list_t *e1000g_private_devi_list; 986 987 #ifdef __cplusplus 988 } 989 #endif 990 991 #endif /* _E1000G_SW_H */ 992