1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac_provider.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 /* Driver states */ 81 #define E1000G_UNKNOWN 0x00 82 #define E1000G_INITIALIZED 0x01 83 #define E1000G_STARTED 0x02 84 #define E1000G_SUSPENDED 0x04 85 #define E1000G_ERROR 0x80 86 87 #define JUMBO_FRAG_LENGTH 4096 88 89 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 90 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 91 #define MCAST_ALLOC_SIZE 256 92 93 /* 94 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 95 * + one for cross page split 96 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 97 * two for the workaround of the 82546 chip 98 */ 99 #define MAX_COOKIES 18 100 #define MAX_TX_DESC_PER_PACKET 21 101 102 /* 103 * constants used in setting flow control thresholds 104 */ 105 #define E1000_PBA_MASK 0xffff 106 #define E1000_PBA_SHIFT 10 107 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 108 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 109 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 110 111 #define MAX_NUM_TX_DESCRIPTOR 4096 112 #define MAX_NUM_RX_DESCRIPTOR 4096 113 #define MAX_NUM_RX_FREELIST 4096 114 #define MAX_NUM_TX_FREELIST 4096 115 #define MAX_RX_LIMIT_ON_INTR 4096 116 #define MAX_RX_INTR_DELAY 65535 117 #define MAX_RX_INTR_ABS_DELAY 65535 118 #define MAX_TX_INTR_DELAY 65535 119 #define MAX_TX_INTR_ABS_DELAY 65535 120 #define MAX_INTR_THROTTLING 65535 121 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 122 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 123 #define MAX_MCAST_NUM 8192 124 125 #define MIN_NUM_TX_DESCRIPTOR 80 126 #define MIN_NUM_RX_DESCRIPTOR 80 127 #define MIN_NUM_RX_FREELIST 64 128 #define MIN_NUM_TX_FREELIST 80 129 #define MIN_RX_LIMIT_ON_INTR 16 130 #define MIN_RX_INTR_DELAY 0 131 #define MIN_RX_INTR_ABS_DELAY 0 132 #define MIN_TX_INTR_DELAY 0 133 #define MIN_TX_INTR_ABS_DELAY 0 134 #define MIN_INTR_THROTTLING 0 135 #define MIN_RX_BCOPY_THRESHOLD 0 136 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 137 #define MIN_MCAST_NUM 8 138 139 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 140 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 141 #define DEFAULT_NUM_RX_FREELIST 4096 142 #define DEFAULT_NUM_TX_FREELIST 2304 143 #define DEFAULT_RX_LIMIT_ON_INTR 128 144 145 #ifdef __sparc 146 #define MAX_INTR_PER_SEC 7100 147 #define MIN_INTR_PER_SEC 3000 148 #define DEFAULT_INTR_PACKET_LOW 5 149 #define DEFAULT_INTR_PACKET_HIGH 128 150 #else 151 #define MAX_INTR_PER_SEC 15000 152 #define MIN_INTR_PER_SEC 4000 153 #define DEFAULT_INTR_PACKET_LOW 10 154 #define DEFAULT_INTR_PACKET_HIGH 48 155 #endif 156 157 #define DEFAULT_RX_INTR_DELAY 0 158 #define DEFAULT_RX_INTR_ABS_DELAY 64 159 #define DEFAULT_TX_INTR_DELAY 64 160 #define DEFAULT_TX_INTR_ABS_DELAY 64 161 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 162 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 163 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 164 165 #define DEFAULT_RX_BCOPY_THRESHOLD 128 166 #define DEFAULT_TX_BCOPY_THRESHOLD 512 167 #define DEFAULT_TX_UPDATE_THRESHOLD 256 168 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 169 170 #define DEFAULT_TX_INTR_ENABLE 1 171 #define DEFAULT_FLOW_CONTROL 3 172 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 173 /* which is normally 0x040 */ 174 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 175 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 176 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 177 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 178 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 179 180 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 181 #define RX_DRAIN_TIME (200) /* # milliseconds recv drain */ 182 183 #define TX_STALL_TIME_2S (200) /* in unit of tick */ 184 #define TX_STALL_TIME_8S (800) /* in unit of tick */ 185 186 /* 187 * The size of the receive/transmite buffers 188 */ 189 #define E1000_RX_BUFFER_SIZE_2K (2048) 190 #define E1000_RX_BUFFER_SIZE_4K (4096) 191 #define E1000_RX_BUFFER_SIZE_8K (8192) 192 #define E1000_RX_BUFFER_SIZE_16K (16384) 193 194 #define E1000_TX_BUFFER_SIZE_2K (2048) 195 #define E1000_TX_BUFFER_SIZE_4K (4096) 196 #define E1000_TX_BUFFER_SIZE_8K (8192) 197 #define E1000_TX_BUFFER_SIZE_16K (16384) 198 199 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 200 201 #define E1000G_RX_NORMAL 0x0 202 #define E1000G_RX_STOPPED 0x1 203 204 #define E1000G_CHAIN_NO_LIMIT 0 205 206 /* 207 * definitions for smartspeed workaround 208 */ 209 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 210 /* or 30 seconds */ 211 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 212 /* or 6 seconds */ 213 214 /* 215 * Definitions for module_info. 216 */ 217 #define WSNAME "e1000g" /* module name */ 218 219 /* 220 * Defined for IP header alignment. We also need to preserve space for 221 * VLAN tag (4 bytes) 222 */ 223 #define E1000G_IPALIGNROOM 6 224 #define E1000G_IPALIGNPRESERVEROOM 64 225 226 /* 227 * bit flags for 'attach_progress' which is a member variable in struct e1000g 228 */ 229 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 230 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 231 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 232 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 233 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 234 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 235 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 236 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 237 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 238 /* 0200 used to be PROGRESS_NDD. Now unused */ 239 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 240 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 241 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 242 243 /* 244 * Speed and Duplex Settings 245 */ 246 #define GDIAG_10_HALF 1 247 #define GDIAG_10_FULL 2 248 #define GDIAG_100_HALF 3 249 #define GDIAG_100_FULL 4 250 #define GDIAG_1000_FULL 6 251 #define GDIAG_ANY 7 252 253 /* 254 * Coexist Workaround RP: 07/04/03 255 * 82544 Workaround : Co-existence 256 */ 257 #define MAX_TX_BUF_SIZE (8 * 1024) 258 259 /* 260 * Defines for Jumbo Frame 261 */ 262 #define FRAME_SIZE_UPTO_2K 2048 263 #define FRAME_SIZE_UPTO_4K 4096 264 #define FRAME_SIZE_UPTO_8K 8192 265 #define FRAME_SIZE_UPTO_16K 16384 266 #define FRAME_SIZE_UPTO_9K 9234 267 268 #define DEFAULT_MTU ETHERMTU 269 #define MAXIMUM_MTU_4K 4096 270 #define MAXIMUM_MTU_9K 9216 271 272 #define DEFAULT_FRAME_SIZE \ 273 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 274 #define MAXIMUM_FRAME_SIZE \ 275 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 276 277 #define E1000_LSO_MAXLEN 65535 278 279 /* Defines for Tx stall check */ 280 #define E1000G_STALL_WATCHDOG_COUNT 8 281 282 #define MAX_TX_LINK_DOWN_TIMEOUT 8 283 284 /* Defines for DVMA */ 285 #ifdef __sparc 286 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 287 #endif 288 289 /* 290 * Loopback definitions 291 */ 292 #define E1000G_LB_NONE 0 293 #define E1000G_LB_EXTERNAL_1000 1 294 #define E1000G_LB_EXTERNAL_100 2 295 #define E1000G_LB_EXTERNAL_10 3 296 #define E1000G_LB_INTERNAL_PHY 4 297 298 /* 299 * Private dip list definitions 300 */ 301 #define E1000G_PRIV_DEVI_ATTACH 0x0 302 #define E1000G_PRIV_DEVI_DETACH 0x1 303 304 /* 305 * Tx descriptor LENGTH field mask 306 */ 307 #define E1000G_TBD_LENGTH_MASK 0x000fffff 308 309 #define E1000G_IS_VLAN_PACKET(ptr) \ 310 ((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) == \ 311 htons(ETHERTYPE_VLAN)) 312 313 /* 314 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 315 */ 316 #define QUEUE_INIT_LIST(_LH) \ 317 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 318 319 /* 320 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 321 */ 322 #define IS_QUEUE_EMPTY(_LH) \ 323 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 324 325 /* 326 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 327 * not remove the head from the queue. 328 */ 329 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 330 331 /* 332 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 333 */ 334 #define QUEUE_REMOVE_HEAD(_LH) \ 335 { \ 336 PSINGLE_LIST_LINK ListElem; \ 337 if (ListElem = (_LH)->Flink) \ 338 { \ 339 if (!((_LH)->Flink = ListElem->Flink)) \ 340 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 341 } \ 342 } 343 344 /* 345 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 346 * and return it (this differs from QUEUE_REMOVE_HEAD only in 347 * the 1st line). 348 */ 349 #define QUEUE_POP_HEAD(_LH) \ 350 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 351 { \ 352 PSINGLE_LIST_LINK ListElem; \ 353 ListElem = (_LH)->Flink; \ 354 if (ListElem) \ 355 { \ 356 (_LH)->Flink = ListElem->Flink; \ 357 if (!(_LH)->Flink) \ 358 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 359 } \ 360 } 361 362 /* 363 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 364 * remove the tail from the queue. 365 */ 366 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 367 368 /* 369 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 370 */ 371 #define QUEUE_PUSH_TAIL(_LH, _E) \ 372 if ((_LH)->Blink) \ 373 { \ 374 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 375 (PSINGLE_LIST_LINK)(_E); \ 376 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 377 } else { \ 378 (_LH)->Flink = \ 379 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 380 } \ 381 (_E)->Flink = (PSINGLE_LIST_LINK)0; 382 383 /* 384 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 385 */ 386 #define QUEUE_PUSH_HEAD(_LH, _E) \ 387 if (!((_E)->Flink = (_LH)->Flink)) \ 388 { \ 389 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 390 } \ 391 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 392 393 /* 394 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 395 * current element. 396 */ 397 #define QUEUE_GET_NEXT(_LH, _E) \ 398 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 399 (0) : ((_E)->Flink)) 400 401 /* 402 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 403 */ 404 #define QUEUE_APPEND(_LH1, _LH2) \ 405 if ((_LH2)->Flink) { \ 406 if ((_LH1)->Flink) { \ 407 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 408 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 409 } else { \ 410 (_LH1)->Flink = \ 411 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 412 } \ 413 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 414 } 415 416 417 #define QUEUE_SWITCH(_LH1, _LH2) \ 418 if ((_LH2)->Flink) { \ 419 (_LH1)->Flink = (_LH2)->Flink; \ 420 (_LH1)->Blink = (_LH2)->Blink; \ 421 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 422 } 423 424 /* 425 * Property lookups 426 */ 427 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 428 DDI_PROP_DONTPASS, (n)) 429 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 430 DDI_PROP_DONTPASS, (n), -1) 431 432 #ifdef E1000G_DEBUG 433 /* 434 * E1000G-specific ioctls ... 435 */ 436 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 437 + 'K') << 4) + 'G') << 4) 438 439 /* 440 * These diagnostic IOCTLS are enabled only in DEBUG drivers 441 */ 442 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 443 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 444 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 445 446 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 447 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 448 449 typedef struct { 450 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 451 uint64_t pp_acc_space; /* See #defines below */ 452 uint64_t pp_acc_offset; /* See regs definition */ 453 uint64_t pp_acc_data; /* output for peek */ 454 /* input for poke */ 455 } e1000g_peekpoke_t; 456 #endif /* E1000G_DEBUG */ 457 458 /* 459 * (Internal) return values from ioctl subroutines 460 */ 461 enum ioc_reply { 462 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 463 IOC_DONE, /* OK, reply sent */ 464 IOC_ACK, /* OK, just send ACK */ 465 IOC_REPLY /* OK, just send reply */ 466 }; 467 468 /* 469 * Named Data (ND) Parameter Management Structure 470 */ 471 typedef struct { 472 uint32_t ndp_info; 473 uint32_t ndp_min; 474 uint32_t ndp_max; 475 uint32_t ndp_val; 476 struct e1000g *ndp_instance; 477 char *ndp_name; 478 } nd_param_t; 479 480 /* 481 * The entry of the private dip list 482 */ 483 typedef struct _private_devi_list { 484 dev_info_t *priv_dip; 485 uint32_t flag; 486 uint32_t pending_rx_count; 487 struct _private_devi_list *prev; 488 struct _private_devi_list *next; 489 } private_devi_list_t; 490 491 /* 492 * A structure that points to the next entry in the queue. 493 */ 494 typedef struct _SINGLE_LIST_LINK { 495 struct _SINGLE_LIST_LINK *Flink; 496 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 497 498 /* 499 * A "ListHead" structure that points to the head and tail of a queue 500 */ 501 typedef struct _LIST_DESCRIBER { 502 struct _SINGLE_LIST_LINK *volatile Flink; 503 struct _SINGLE_LIST_LINK *volatile Blink; 504 } LIST_DESCRIBER, *PLIST_DESCRIBER; 505 506 /* 507 * Address-Length pair structure that stores descriptor info 508 */ 509 typedef struct _sw_desc { 510 uint64_t address; 511 uint32_t length; 512 } sw_desc_t, *p_sw_desc_t; 513 514 typedef struct _desc_array { 515 sw_desc_t descriptor[4]; 516 uint32_t elements; 517 } desc_array_t, *p_desc_array_t; 518 519 typedef enum { 520 USE_NONE, 521 USE_BCOPY, 522 USE_DVMA, 523 USE_DMA 524 } dma_type_t; 525 526 typedef struct _dma_buffer { 527 caddr_t address; 528 uint64_t dma_address; 529 ddi_acc_handle_t acc_handle; 530 ddi_dma_handle_t dma_handle; 531 size_t size; 532 size_t len; 533 } dma_buffer_t, *p_dma_buffer_t; 534 535 /* 536 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 537 * structure stores the additional information that is 538 * associated with every packet to be transmitted. It stores the 539 * message block pointer and the TBD addresses associated with 540 * the m_blk and also the link to the next tcb in the chain 541 */ 542 typedef struct _tx_sw_packet { 543 /* Link to the next tx_sw_packet in the list */ 544 SINGLE_LIST_LINK Link; 545 mblk_t *mp; 546 uint32_t num_desc; 547 uint32_t num_mblk_frag; 548 dma_type_t dma_type; 549 dma_type_t data_transfer_type; 550 ddi_dma_handle_t tx_dma_handle; 551 dma_buffer_t tx_buf[1]; 552 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 553 int64_t tickstamp; 554 } tx_sw_packet_t, *p_tx_sw_packet_t; 555 556 /* 557 * This structure is similar to the rx_sw_packet structure used 558 * for Ndis. This structure stores information about the 2k 559 * aligned receive buffer into which the FX1000 DMA's frames. 560 * This structure is maintained as a linked list of many 561 * receiver buffer pointers. 562 */ 563 typedef struct _rx_sw_packet { 564 /* Link to the next rx_sw_packet_t in the list */ 565 SINGLE_LIST_LINK Link; 566 struct _rx_sw_packet *next; 567 uint32_t ref_cnt; 568 mblk_t *mp; 569 caddr_t rx_data; 570 dma_type_t dma_type; 571 frtn_t free_rtn; 572 dma_buffer_t rx_buf[1]; 573 } rx_sw_packet_t, *p_rx_sw_packet_t; 574 575 typedef struct _mblk_list { 576 mblk_t *head; 577 mblk_t *tail; 578 } mblk_list_t, *p_mblk_list_t; 579 580 typedef struct _context_data { 581 uint32_t ether_header_size; 582 uint32_t cksum_flags; 583 uint32_t cksum_start; 584 uint32_t cksum_stuff; 585 uint16_t mss; 586 uint8_t hdr_len; 587 uint32_t pay_len; 588 boolean_t lso_flag; 589 } context_data_t; 590 591 typedef union _e1000g_ether_addr { 592 struct { 593 uint32_t high; 594 uint32_t low; 595 } reg; 596 struct { 597 uint8_t set; 598 uint8_t redundant; 599 uint8_t addr[ETHERADDRL]; 600 } mac; 601 } e1000g_ether_addr_t; 602 603 typedef struct _e1000g_stat { 604 605 kstat_named_t link_speed; /* Link Speed */ 606 kstat_named_t reset_count; /* Reset Count */ 607 608 kstat_named_t rx_error; /* Rx Error in Packet */ 609 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 610 kstat_named_t rx_size_error; /* Rx Size Error */ 611 612 kstat_named_t tx_no_desc; /* Tx No Desc */ 613 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 614 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 615 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 616 kstat_named_t tx_reschedule; /* Tx Reschedule */ 617 618 #ifdef E1000G_DEBUG 619 kstat_named_t rx_none; /* Rx No Incoming Data */ 620 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 621 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 622 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 623 624 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 625 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 626 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 627 kstat_named_t tx_recycle; /* Tx Recycle */ 628 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 629 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 630 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 631 kstat_named_t tx_copy; /* Tx Send Copy */ 632 kstat_named_t tx_bind; /* Tx Send Bind */ 633 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 634 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 635 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 636 #endif 637 638 kstat_named_t Crcerrs; /* CRC Error Count */ 639 kstat_named_t Symerrs; /* Symbol Error Count */ 640 kstat_named_t Mpc; /* Missed Packet Count */ 641 kstat_named_t Scc; /* Single Collision Count */ 642 kstat_named_t Ecol; /* Excessive Collision Count */ 643 kstat_named_t Mcc; /* Multiple Collision Count */ 644 kstat_named_t Latecol; /* Late Collision Count */ 645 kstat_named_t Colc; /* Collision Count */ 646 kstat_named_t Dc; /* Defer Count */ 647 kstat_named_t Sec; /* Sequence Error Count */ 648 kstat_named_t Rlec; /* Receive Length Error Count */ 649 kstat_named_t Xonrxc; /* XON Received Count */ 650 kstat_named_t Xontxc; /* XON Xmitted Count */ 651 kstat_named_t Xoffrxc; /* XOFF Received Count */ 652 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 653 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 654 #ifdef E1000G_DEBUG 655 kstat_named_t Prc64; /* Packets Received - 64b */ 656 kstat_named_t Prc127; /* Packets Received - 65-127b */ 657 kstat_named_t Prc255; /* Packets Received - 127-255b */ 658 kstat_named_t Prc511; /* Packets Received - 256-511b */ 659 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 660 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 661 #endif 662 kstat_named_t Gprc; /* Good Packets Received Count */ 663 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 664 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 665 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 666 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 667 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 668 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 669 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 670 kstat_named_t Rnbc; /* Receive No Buffers Count */ 671 kstat_named_t Ruc; /* Receive Undersize Count */ 672 kstat_named_t Rfc; /* Receive Frag Count */ 673 kstat_named_t Roc; /* Receive Oversize Count */ 674 kstat_named_t Rjc; /* Receive Jabber Count */ 675 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 676 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 677 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 678 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 679 kstat_named_t Tpr; /* Total Packets Received */ 680 kstat_named_t Tpt; /* Total Packets Xmitted */ 681 #ifdef E1000G_DEBUG 682 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 683 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 684 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 685 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 686 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 687 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 688 #endif 689 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 690 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 691 kstat_named_t Algnerrc; /* Alignment Error count */ 692 kstat_named_t Tuc; /* Transmit Underrun count */ 693 kstat_named_t Rxerrc; /* Rx Error Count */ 694 kstat_named_t Tncrs; /* Transmit with no CRS */ 695 kstat_named_t Cexterr; /* Carrier Extension Error count */ 696 kstat_named_t Rutec; /* Receive DMA too Early count */ 697 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 698 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 699 } e1000g_stat_t, *p_e1000g_stat_t; 700 701 typedef struct _e1000g_tx_ring { 702 kmutex_t tx_lock; 703 kmutex_t freelist_lock; 704 kmutex_t usedlist_lock; 705 /* 706 * Descriptor queue definitions 707 */ 708 ddi_dma_handle_t tbd_dma_handle; 709 ddi_acc_handle_t tbd_acc_handle; 710 struct e1000_tx_desc *tbd_area; 711 uint64_t tbd_dma_addr; 712 struct e1000_tx_desc *tbd_first; 713 struct e1000_tx_desc *tbd_last; 714 struct e1000_tx_desc *tbd_oldest; 715 struct e1000_tx_desc *tbd_next; 716 uint32_t tbd_avail; 717 /* 718 * Software packet structures definitions 719 */ 720 p_tx_sw_packet_t packet_area; 721 LIST_DESCRIBER used_list; 722 LIST_DESCRIBER free_list; 723 /* 724 * TCP/UDP Context Data Information 725 */ 726 context_data_t pre_context; 727 /* 728 * Timer definitions for 82547 729 */ 730 timeout_id_t timer_id_82547; 731 boolean_t timer_enable_82547; 732 /* 733 * reschedule when tx resource is available 734 */ 735 boolean_t resched_needed; 736 clock_t resched_timestamp; 737 mblk_list_t mblks; 738 /* 739 * Statistics 740 */ 741 uint32_t stat_no_swpkt; 742 uint32_t stat_no_desc; 743 uint32_t stat_send_fail; 744 uint32_t stat_reschedule; 745 uint32_t stat_timer_reschedule; 746 uint32_t stat_over_size; 747 #ifdef E1000G_DEBUG 748 uint32_t stat_under_size; 749 uint32_t stat_exceed_frags; 750 uint32_t stat_empty_frags; 751 uint32_t stat_recycle; 752 uint32_t stat_recycle_intr; 753 uint32_t stat_recycle_retry; 754 uint32_t stat_recycle_none; 755 uint32_t stat_copy; 756 uint32_t stat_bind; 757 uint32_t stat_multi_copy; 758 uint32_t stat_multi_cookie; 759 uint32_t stat_lack_desc; 760 uint32_t stat_lso_header_fail; 761 #endif 762 /* 763 * Pointer to the adapter 764 */ 765 struct e1000g *adapter; 766 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 767 768 typedef struct _e1000g_rx_data { 769 kmutex_t freelist_lock; 770 kmutex_t recycle_lock; 771 /* 772 * Descriptor queue definitions 773 */ 774 ddi_dma_handle_t rbd_dma_handle; 775 ddi_acc_handle_t rbd_acc_handle; 776 struct e1000_rx_desc *rbd_area; 777 uint64_t rbd_dma_addr; 778 struct e1000_rx_desc *rbd_first; 779 struct e1000_rx_desc *rbd_last; 780 struct e1000_rx_desc *rbd_next; 781 /* 782 * Software packet structures definitions 783 */ 784 p_rx_sw_packet_t packet_area; 785 LIST_DESCRIBER recv_list; 786 LIST_DESCRIBER free_list; 787 LIST_DESCRIBER recycle_list; 788 uint32_t flag; 789 790 uint32_t pending_count; 791 uint32_t avail_freepkt; 792 uint32_t recycle_freepkt; 793 uint32_t rx_mblk_len; 794 mblk_t *rx_mblk; 795 mblk_t *rx_mblk_tail; 796 797 private_devi_list_t *priv_devi_node; 798 struct _e1000g_rx_ring *rx_ring; 799 } e1000g_rx_data_t; 800 801 typedef struct _e1000g_rx_ring { 802 e1000g_rx_data_t *rx_data; 803 804 kmutex_t rx_lock; 805 806 mac_ring_handle_t mrh; 807 mac_ring_handle_t mrh_init; 808 uint64_t ring_gen_num; 809 boolean_t poll_flag; 810 811 /* 812 * Statistics 813 */ 814 uint32_t stat_error; 815 uint32_t stat_allocb_fail; 816 uint32_t stat_exceed_pkt; 817 uint32_t stat_size_error; 818 #ifdef E1000G_DEBUG 819 uint32_t stat_none; 820 uint32_t stat_multi_desc; 821 uint32_t stat_no_freepkt; 822 #endif 823 /* 824 * Pointer to the adapter 825 */ 826 struct e1000g *adapter; 827 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 828 829 typedef struct e1000g { 830 int instance; 831 dev_info_t *dip; 832 dev_info_t *priv_dip; 833 private_devi_list_t *priv_devi_node; 834 mac_handle_t mh; 835 mac_resource_handle_t mrh; 836 struct e1000_hw shared; 837 struct e1000g_osdep osdep; 838 839 uint32_t e1000g_state; 840 boolean_t e1000g_promisc; 841 boolean_t strip_crc; 842 boolean_t rx_buffer_setup; 843 boolean_t esb2_workaround; 844 link_state_t link_state; 845 uint32_t link_speed; 846 uint32_t link_duplex; 847 uint32_t master_latency_timer; 848 uint32_t smartspeed; /* smartspeed w/a counter */ 849 uint32_t init_count; 850 uint32_t reset_count; 851 boolean_t reset_flag; 852 uint32_t stall_threshold; 853 boolean_t stall_flag; 854 uint32_t attach_progress; /* attach tracking */ 855 uint32_t loopback_mode; 856 uint32_t pending_rx_count; 857 858 uint32_t tx_desc_num; 859 uint32_t tx_freelist_num; 860 uint32_t rx_desc_num; 861 uint32_t rx_freelist_num; 862 uint32_t tx_buffer_size; 863 uint32_t rx_buffer_size; 864 865 uint32_t tx_link_down_timeout; 866 uint32_t tx_bcopy_thresh; 867 uint32_t rx_limit_onintr; 868 uint32_t rx_bcopy_thresh; 869 uint32_t rx_buf_align; 870 uint32_t desc_align; 871 872 boolean_t intr_adaptive; 873 boolean_t tx_intr_enable; 874 uint32_t tx_intr_delay; 875 uint32_t tx_intr_abs_delay; 876 uint32_t rx_intr_delay; 877 uint32_t rx_intr_abs_delay; 878 uint32_t intr_throttling_rate; 879 880 uint32_t default_mtu; 881 uint32_t max_mtu; 882 uint32_t max_frame_size; 883 uint32_t min_frame_size; 884 885 boolean_t watchdog_timer_enabled; 886 boolean_t watchdog_timer_started; 887 timeout_id_t watchdog_tid; 888 boolean_t link_complete; 889 timeout_id_t link_tid; 890 891 e1000g_rx_ring_t rx_ring[1]; 892 e1000g_tx_ring_t tx_ring[1]; 893 mac_group_handle_t rx_group; 894 895 /* 896 * Rx and Tx packet count for interrupt adaptive setting 897 */ 898 uint32_t rx_pkt_cnt; 899 uint32_t tx_pkt_cnt; 900 901 /* 902 * The watchdog_lock must be held when updateing the 903 * timeout fields in struct e1000g, that is, 904 * watchdog_tid, watchdog_timer_started. 905 */ 906 kmutex_t watchdog_lock; 907 /* 908 * The link_lock protects the link fields in struct e1000g, 909 * such as link_state, link_speed, link_duplex, link_complete, and 910 * link_tid. 911 */ 912 kmutex_t link_lock; 913 /* 914 * The chip_lock assures that the Rx/Tx process must be 915 * stopped while other functions change the hardware 916 * configuration of e1000g card, such as e1000g_reset(), 917 * e1000g_reset_hw() etc are executed. 918 */ 919 krwlock_t chip_lock; 920 921 boolean_t unicst_init; 922 uint32_t unicst_avail; 923 uint32_t unicst_total; 924 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 925 926 uint32_t mcast_count; 927 uint32_t mcast_max_num; 928 uint32_t mcast_alloc_count; 929 struct ether_addr *mcast_table; 930 931 ulong_t sys_page_sz; 932 #ifdef __sparc 933 uint_t dvma_page_num; 934 #endif 935 936 boolean_t msi_enable; 937 boolean_t tx_hcksum_enable; 938 boolean_t lso_enable; 939 boolean_t lso_premature_issue; 940 boolean_t mem_workaround_82546; 941 int intr_type; 942 int intr_cnt; 943 int intr_cap; 944 size_t intr_size; 945 uint_t intr_pri; 946 ddi_intr_handle_t *htable; 947 948 int tx_softint_pri; 949 ddi_softint_handle_t tx_softint_handle; 950 951 kstat_t *e1000g_ksp; 952 953 boolean_t poll_mode; 954 955 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 956 uint16_t phy_status; /* contents of PHY_STATUS */ 957 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 958 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 959 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 960 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 961 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 962 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 963 964 /* 965 * FMA capabilities 966 */ 967 int fm_capabilities; 968 969 uint32_t param_en_1000fdx:1, 970 param_en_1000hdx:1, 971 param_en_100fdx:1, 972 param_en_100hdx:1, 973 param_en_10fdx:1, 974 param_en_10hdx:1, 975 param_autoneg_cap:1, 976 param_pause_cap:1, 977 param_asym_pause_cap:1, 978 param_1000fdx_cap:1, 979 param_1000hdx_cap:1, 980 param_100t4_cap:1, 981 param_100fdx_cap:1, 982 param_100hdx_cap:1, 983 param_10fdx_cap:1, 984 param_10hdx_cap:1, 985 param_adv_autoneg:1, 986 param_adv_pause:1, 987 param_adv_asym_pause:1, 988 param_adv_1000fdx:1, 989 param_adv_1000hdx:1, 990 param_adv_100t4:1, 991 param_adv_100fdx:1, 992 param_adv_100hdx:1, 993 param_adv_10fdx:1, 994 param_adv_10hdx:1, 995 param_lp_autoneg:1, 996 param_lp_pause:1, 997 param_lp_asym_pause:1, 998 param_lp_1000fdx:1, 999 param_lp_1000hdx:1, 1000 param_lp_100t4:1; 1001 1002 uint32_t param_lp_100fdx:1, 1003 param_lp_100hdx:1, 1004 param_lp_10fdx:1, 1005 param_lp_10hdx:1, 1006 param_pad_to_32:28; 1007 1008 } e1000g_t; 1009 1010 1011 /* 1012 * Function prototypes 1013 */ 1014 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node); 1015 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data); 1016 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data); 1017 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 1018 void e1000g_release_dma_resources(struct e1000g *Adapter); 1019 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release); 1020 void e1000g_tx_setup(struct e1000g *Adapter); 1021 void e1000g_rx_setup(struct e1000g *Adapter); 1022 1023 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 1024 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 1025 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 1026 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1027 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1028 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz); 1029 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1030 1031 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1032 int e1000g_init_stats(struct e1000g *Adapter); 1033 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1034 uint32_t frame_len, uint8_t *mac_addr); 1035 1036 void e1000g_clear_interrupt(struct e1000g *Adapter); 1037 void e1000g_mask_interrupt(struct e1000g *Adapter); 1038 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1039 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1040 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1041 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1042 void e1000_destroy_hw_mutex(struct e1000_hw *hw); 1043 void e1000_enable_pciex_master(struct e1000_hw *hw); 1044 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1045 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1046 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1047 void e1000g_set_fma_flags(int dma_flag); 1048 int e1000g_reset_link(struct e1000g *Adapter); 1049 1050 /* 1051 * Global variables 1052 */ 1053 extern boolean_t e1000g_force_detach; 1054 extern uint32_t e1000g_mblks_pending; 1055 extern kmutex_t e1000g_rx_detach_lock; 1056 extern private_devi_list_t *e1000g_private_devi_list; 1057 extern int e1000g_poll_mode; 1058 1059 #ifdef __cplusplus 1060 } 1061 #endif 1062 1063 #endif /* _E1000G_SW_H */ 1064