1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_rx.c * 33 * * 34 * Abstract: * 35 * This file contains some routines that take care of Receive * 36 * interrupt and also for the received packets it sends up to * 37 * upper layer. * 38 * It tries to do a zero copy if free buffers are available in * 39 * the pool. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static p_rx_sw_packet_t e1000g_get_buf(e1000g_rx_ring_t *rx_ring); 48 #pragma inline(e1000g_get_buf) 49 static void e1000g_priv_devi_list_clean(); 50 51 /* 52 * e1000g_rxfree_func - the call-back function to reclaim rx buffer 53 * 54 * This function is called when an mp is freed by the user thru 55 * freeb call (Only for mp constructed through desballoc call) 56 * It returns back the freed buffer to the freelist 57 */ 58 void 59 e1000g_rxfree_func(p_rx_sw_packet_t packet) 60 { 61 struct e1000g *Adapter; 62 e1000g_rx_ring_t *rx_ring; 63 64 rx_ring = (e1000g_rx_ring_t *)packet->rx_ring; 65 Adapter = rx_ring->adapter; 66 67 /* 68 * Here the rx recycling processes different rx packets in different 69 * threads, so we protect it with RW_READER to ensure it won't block 70 * other rx recycling threads. 71 */ 72 rw_enter(&e1000g_rx_detach_lock, RW_READER); 73 74 if (packet->flag == E1000G_RX_SW_FREE) { 75 rw_exit(&e1000g_rx_detach_lock); 76 return; 77 } 78 79 if (packet->flag == E1000G_RX_SW_STOP) { 80 packet->flag = E1000G_RX_SW_FREE; 81 rw_exit(&e1000g_rx_detach_lock); 82 83 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 84 rx_ring->pending_count--; 85 e1000g_mblks_pending--; 86 87 if (rx_ring->pending_count == 0) { 88 while (rx_ring->pending_list != NULL) { 89 packet = rx_ring->pending_list; 90 rx_ring->pending_list = 91 rx_ring->pending_list->next; 92 93 ASSERT(packet->mp == NULL); 94 e1000g_free_rx_sw_packet(packet); 95 } 96 } 97 98 /* 99 * If e1000g_force_detach is enabled, we need to clean up 100 * the idle priv_dip entries in the private dip list while 101 * e1000g_mblks_pending is zero. 102 */ 103 if (e1000g_force_detach && (e1000g_mblks_pending == 0)) 104 e1000g_priv_devi_list_clean(); 105 rw_exit(&e1000g_rx_detach_lock); 106 return; 107 } 108 109 if (packet->flag == E1000G_RX_SW_DETACH) { 110 packet->flag = E1000G_RX_SW_FREE; 111 rw_exit(&e1000g_rx_detach_lock); 112 113 ASSERT(packet->mp == NULL); 114 e1000g_free_rx_sw_packet(packet); 115 116 /* 117 * Here the e1000g_mblks_pending may be modified by different 118 * rx recycling threads simultaneously, so we need to protect 119 * it with RW_WRITER. 120 */ 121 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 122 e1000g_mblks_pending--; 123 124 /* 125 * If e1000g_force_detach is enabled, we need to clean up 126 * the idle priv_dip entries in the private dip list while 127 * e1000g_mblks_pending is zero. 128 */ 129 if (e1000g_force_detach && (e1000g_mblks_pending == 0)) 130 e1000g_priv_devi_list_clean(); 131 rw_exit(&e1000g_rx_detach_lock); 132 return; 133 } 134 135 packet->flag = E1000G_RX_SW_FREE; 136 137 if (packet->mp == NULL) { 138 /* 139 * Allocate a mblk that binds to the data buffer 140 */ 141 packet->mp = desballoc((unsigned char *) 142 packet->rx_buf->address - E1000G_IPALIGNROOM, 143 packet->rx_buf->size + E1000G_IPALIGNROOM, 144 BPRI_MED, &packet->free_rtn); 145 146 if (packet->mp != NULL) { 147 packet->mp->b_rptr += E1000G_IPALIGNROOM; 148 packet->mp->b_wptr += E1000G_IPALIGNROOM; 149 } else { 150 E1000G_STAT(rx_ring->stat_esballoc_fail); 151 } 152 } 153 154 mutex_enter(&rx_ring->freelist_lock); 155 QUEUE_PUSH_TAIL(&rx_ring->free_list, &packet->Link); 156 rx_ring->avail_freepkt++; 157 mutex_exit(&rx_ring->freelist_lock); 158 159 rw_exit(&e1000g_rx_detach_lock); 160 } 161 162 /* 163 * e1000g_priv_devi_list_clean - clean up e1000g_private_devi_list 164 * 165 * We will walk the e1000g_private_devi_list to free the entry marked 166 * with the E1000G_PRIV_DEVI_DETACH flag. 167 */ 168 static void 169 e1000g_priv_devi_list_clean() 170 { 171 private_devi_list_t *devi_node, *devi_del; 172 173 if (e1000g_private_devi_list == NULL) 174 return; 175 176 devi_node = e1000g_private_devi_list; 177 while ((devi_node != NULL) && 178 (devi_node->flag == E1000G_PRIV_DEVI_DETACH)) { 179 e1000g_private_devi_list = devi_node->next; 180 kmem_free(devi_node->priv_dip, 181 sizeof (struct dev_info)); 182 kmem_free(devi_node, 183 sizeof (private_devi_list_t)); 184 devi_node = e1000g_private_devi_list; 185 } 186 if (e1000g_private_devi_list == NULL) 187 return; 188 while (devi_node->next != NULL) { 189 if (devi_node->next->flag == E1000G_PRIV_DEVI_DETACH) { 190 devi_del = devi_node->next; 191 devi_node->next = devi_del->next; 192 kmem_free(devi_del->priv_dip, 193 sizeof (struct dev_info)); 194 kmem_free(devi_del, 195 sizeof (private_devi_list_t)); 196 } else { 197 devi_node = devi_node->next; 198 } 199 } 200 } 201 202 /* 203 * e1000g_rx_setup - setup rx data structures 204 * 205 * This routine initializes all of the receive related 206 * structures. This includes the receive descriptors, the 207 * actual receive buffers, and the rx_sw_packet software 208 * structures. 209 */ 210 void 211 e1000g_rx_setup(struct e1000g *Adapter) 212 { 213 struct e1000_hw *hw; 214 p_rx_sw_packet_t packet; 215 struct e1000_rx_desc *descriptor; 216 uint32_t buf_low; 217 uint32_t buf_high; 218 uint32_t reg_val; 219 int i; 220 int size; 221 e1000g_rx_ring_t *rx_ring; 222 223 hw = &Adapter->shared; 224 rx_ring = Adapter->rx_ring; 225 226 /* 227 * zero out all of the receive buffer descriptor memory 228 * assures any previous data or status is erased 229 */ 230 bzero(rx_ring->rbd_area, 231 sizeof (struct e1000_rx_desc) * Adapter->rx_desc_num); 232 233 if (!Adapter->rx_buffer_setup) { 234 /* Init the list of "Receive Buffer" */ 235 QUEUE_INIT_LIST(&rx_ring->recv_list); 236 237 /* Init the list of "Free Receive Buffer" */ 238 QUEUE_INIT_LIST(&rx_ring->free_list); 239 240 /* 241 * Setup Receive list and the Free list. Note that 242 * the both were allocated in one packet area. 243 */ 244 packet = rx_ring->packet_area; 245 descriptor = rx_ring->rbd_first; 246 247 for (i = 0; i < Adapter->rx_desc_num; 248 i++, packet = packet->next, descriptor++) { 249 ASSERT(packet != NULL); 250 ASSERT(descriptor != NULL); 251 descriptor->buffer_addr = 252 packet->rx_buf->dma_address; 253 254 /* Add this rx_sw_packet to the receive list */ 255 QUEUE_PUSH_TAIL(&rx_ring->recv_list, 256 &packet->Link); 257 } 258 259 for (i = 0; i < Adapter->rx_freelist_num; 260 i++, packet = packet->next) { 261 ASSERT(packet != NULL); 262 /* Add this rx_sw_packet to the free list */ 263 QUEUE_PUSH_TAIL(&rx_ring->free_list, 264 &packet->Link); 265 } 266 rx_ring->avail_freepkt = Adapter->rx_freelist_num; 267 268 Adapter->rx_buffer_setup = B_TRUE; 269 } else { 270 /* Setup the initial pointer to the first rx descriptor */ 271 packet = (p_rx_sw_packet_t) 272 QUEUE_GET_HEAD(&rx_ring->recv_list); 273 descriptor = rx_ring->rbd_first; 274 275 for (i = 0; i < Adapter->rx_desc_num; i++) { 276 ASSERT(packet != NULL); 277 ASSERT(descriptor != NULL); 278 descriptor->buffer_addr = 279 packet->rx_buf->dma_address; 280 281 /* Get next rx_sw_packet */ 282 packet = (p_rx_sw_packet_t) 283 QUEUE_GET_NEXT(&rx_ring->recv_list, &packet->Link); 284 descriptor++; 285 } 286 } 287 288 E1000_WRITE_REG(&Adapter->shared, E1000_RDTR, Adapter->rx_intr_delay); 289 E1000G_DEBUGLOG_1(Adapter, E1000G_INFO_LEVEL, 290 "E1000_RDTR: 0x%x\n", Adapter->rx_intr_delay); 291 if (hw->mac.type >= e1000_82540) { 292 E1000_WRITE_REG(&Adapter->shared, E1000_RADV, 293 Adapter->rx_intr_abs_delay); 294 E1000G_DEBUGLOG_1(Adapter, E1000G_INFO_LEVEL, 295 "E1000_RADV: 0x%x\n", Adapter->rx_intr_abs_delay); 296 } 297 298 /* 299 * Setup our descriptor pointers 300 */ 301 rx_ring->rbd_next = rx_ring->rbd_first; 302 303 size = Adapter->rx_desc_num * sizeof (struct e1000_rx_desc); 304 E1000_WRITE_REG(hw, E1000_RDLEN(0), size); 305 size = E1000_READ_REG(hw, E1000_RDLEN(0)); 306 307 /* To get lower order bits */ 308 buf_low = (uint32_t)rx_ring->rbd_dma_addr; 309 /* To get the higher order bits */ 310 buf_high = (uint32_t)(rx_ring->rbd_dma_addr >> 32); 311 312 E1000_WRITE_REG(hw, E1000_RDBAH(0), buf_high); 313 E1000_WRITE_REG(hw, E1000_RDBAL(0), buf_low); 314 315 /* 316 * Setup our HW Rx Head & Tail descriptor pointers 317 */ 318 E1000_WRITE_REG(hw, E1000_RDT(0), 319 (uint32_t)(rx_ring->rbd_last - rx_ring->rbd_first)); 320 E1000_WRITE_REG(hw, E1000_RDH(0), 0); 321 322 /* 323 * Setup the Receive Control Register (RCTL), and ENABLE the 324 * receiver. The initial configuration is to: Enable the receiver, 325 * accept broadcasts, discard bad packets (and long packets), 326 * disable VLAN filter checking, set the receive descriptor 327 * minimum threshold size to 1/2, and the receive buffer size to 328 * 2k. 329 */ 330 reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ 331 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 332 E1000_RCTL_LPE | /* Large Packet Enable bit */ 333 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 334 E1000_RCTL_RDMTS_HALF | 335 E1000_RCTL_LBM_NO; /* Loopback Mode = none */ 336 337 if (Adapter->strip_crc) 338 reg_val |= E1000_RCTL_SECRC; /* Strip Ethernet CRC */ 339 340 if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_2K) && 341 (Adapter->max_frame_size <= FRAME_SIZE_UPTO_4K)) 342 reg_val |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 343 else if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_4K) && 344 (Adapter->max_frame_size <= FRAME_SIZE_UPTO_8K)) 345 reg_val |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 346 else if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) && 347 (Adapter->max_frame_size <= FRAME_SIZE_UPTO_16K)) 348 reg_val |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 349 else 350 reg_val |= E1000_RCTL_SZ_2048; 351 352 if (e1000_tbi_sbp_enabled_82543(hw)) 353 reg_val |= E1000_RCTL_SBP; 354 355 /* 356 * Enable early receives on supported devices, only takes effect when 357 * packet size is equal or larger than the specified value (in 8 byte 358 * units), e.g. using jumbo frames when setting to E1000_ERT_2048 359 */ 360 if ((hw->mac.type == e1000_82573) || (hw->mac.type == e1000_ich9lan)) 361 E1000_WRITE_REG(hw, E1000_ERT, E1000_ERT_2048); 362 363 E1000_WRITE_REG(hw, E1000_RCTL, reg_val); 364 365 reg_val = 366 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum offload Enable */ 367 E1000_RXCSUM_IPOFL; /* IP checksum offload Enable */ 368 369 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); 370 } 371 372 /* 373 * e1000g_get_buf - get an rx sw packet from the free_list 374 */ 375 static p_rx_sw_packet_t 376 e1000g_get_buf(e1000g_rx_ring_t *rx_ring) 377 { 378 struct e1000g *Adapter; 379 p_rx_sw_packet_t packet; 380 381 Adapter = rx_ring->adapter; 382 383 mutex_enter(&rx_ring->freelist_lock); 384 packet = (p_rx_sw_packet_t) 385 QUEUE_POP_HEAD(&rx_ring->free_list); 386 if (packet != NULL) 387 rx_ring->avail_freepkt--; 388 mutex_exit(&rx_ring->freelist_lock); 389 390 return (packet); 391 } 392 393 /* 394 * e1000g_receive - main receive routine 395 * 396 * This routine will process packets received in an interrupt 397 */ 398 mblk_t * 399 e1000g_receive(struct e1000g *Adapter) 400 { 401 struct e1000_hw *hw; 402 mblk_t *nmp; 403 mblk_t *ret_mp; 404 mblk_t *ret_nmp; 405 struct e1000_rx_desc *current_desc; 406 struct e1000_rx_desc *last_desc; 407 p_rx_sw_packet_t packet; 408 p_rx_sw_packet_t newpkt; 409 USHORT length; 410 uint32_t pkt_count; 411 uint32_t desc_count; 412 boolean_t accept_frame; 413 boolean_t end_of_packet; 414 boolean_t need_copy; 415 e1000g_rx_ring_t *rx_ring; 416 dma_buffer_t *rx_buf; 417 uint16_t cksumflags; 418 419 ret_mp = NULL; 420 ret_nmp = NULL; 421 pkt_count = 0; 422 desc_count = 0; 423 cksumflags = 0; 424 425 hw = &Adapter->shared; 426 rx_ring = Adapter->rx_ring; 427 428 /* Sync the Rx descriptor DMA buffers */ 429 (void) ddi_dma_sync(rx_ring->rbd_dma_handle, 430 0, 0, DDI_DMA_SYNC_FORKERNEL); 431 432 if (e1000g_check_dma_handle(rx_ring->rbd_dma_handle) != DDI_FM_OK) { 433 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 434 Adapter->chip_state = E1000G_ERROR; 435 } 436 437 current_desc = rx_ring->rbd_next; 438 if (!(current_desc->status & E1000_RXD_STAT_DD)) { 439 /* 440 * don't send anything up. just clear the RFD 441 */ 442 E1000G_DEBUG_STAT(rx_ring->stat_none); 443 return (ret_mp); 444 } 445 446 /* 447 * Loop through the receive descriptors starting at the last known 448 * descriptor owned by the hardware that begins a packet. 449 */ 450 while ((current_desc->status & E1000_RXD_STAT_DD) && 451 (pkt_count < Adapter->rx_limit_onintr)) { 452 453 desc_count++; 454 /* 455 * Now this can happen in Jumbo frame situation. 456 */ 457 if (current_desc->status & E1000_RXD_STAT_EOP) { 458 /* packet has EOP set */ 459 end_of_packet = B_TRUE; 460 } else { 461 /* 462 * If this received buffer does not have the 463 * End-Of-Packet bit set, the received packet 464 * will consume multiple buffers. We won't send this 465 * packet upstack till we get all the related buffers. 466 */ 467 end_of_packet = B_FALSE; 468 } 469 470 /* 471 * Get a pointer to the actual receive buffer 472 * The mp->b_rptr is mapped to The CurrentDescriptor 473 * Buffer Address. 474 */ 475 packet = 476 (p_rx_sw_packet_t)QUEUE_GET_HEAD(&rx_ring->recv_list); 477 ASSERT(packet != NULL); 478 479 rx_buf = packet->rx_buf; 480 481 length = current_desc->length; 482 483 #ifdef __sparc 484 if (packet->dma_type == USE_DVMA) 485 dvma_sync(rx_buf->dma_handle, 0, 486 DDI_DMA_SYNC_FORKERNEL); 487 else 488 (void) ddi_dma_sync(rx_buf->dma_handle, 489 E1000G_IPALIGNROOM, length, 490 DDI_DMA_SYNC_FORKERNEL); 491 #else 492 (void) ddi_dma_sync(rx_buf->dma_handle, 493 E1000G_IPALIGNROOM, length, 494 DDI_DMA_SYNC_FORKERNEL); 495 #endif 496 497 if (e1000g_check_dma_handle( 498 rx_buf->dma_handle) != DDI_FM_OK) { 499 ddi_fm_service_impact(Adapter->dip, 500 DDI_SERVICE_DEGRADED); 501 Adapter->chip_state = E1000G_ERROR; 502 } 503 504 accept_frame = (current_desc->errors == 0) || 505 ((current_desc->errors & 506 (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) != 0); 507 508 if (hw->mac.type == e1000_82543) { 509 unsigned char last_byte; 510 511 last_byte = 512 *((unsigned char *)rx_buf->address + length - 1); 513 514 if (TBI_ACCEPT(hw, 515 current_desc->status, current_desc->errors, 516 current_desc->length, last_byte, 517 Adapter->min_frame_size, Adapter->max_frame_size)) { 518 519 e1000_tbi_adjust_stats(Adapter, 520 length, hw->mac.addr); 521 522 length--; 523 accept_frame = B_TRUE; 524 } else if (e1000_tbi_sbp_enabled_82543(hw) && 525 (current_desc->errors == E1000_RXD_ERR_CE)) { 526 accept_frame = B_TRUE; 527 } 528 } 529 530 /* 531 * Indicate the packet to the NOS if it was good. 532 * Normally, hardware will discard bad packets for us. 533 * Check for the packet to be a valid Ethernet packet 534 */ 535 if (!accept_frame) { 536 /* 537 * error in incoming packet, either the packet is not a 538 * ethernet size packet, or the packet has an error. In 539 * either case, the packet will simply be discarded. 540 */ 541 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 542 "Process Receive Interrupts: Error in Packet\n"); 543 544 E1000G_STAT(rx_ring->stat_error); 545 /* 546 * Returning here as we are done here. There is 547 * no point in waiting for while loop to elapse 548 * and the things which were done. More efficient 549 * and less error prone... 550 */ 551 goto rx_drop; 552 } 553 554 /* 555 * If the Ethernet CRC is not stripped by the hardware, 556 * we need to strip it before sending it up to the stack. 557 */ 558 if (end_of_packet && !Adapter->strip_crc) { 559 if (length > ETHERFCSL) { 560 length -= ETHERFCSL; 561 } else { 562 /* 563 * If the fragment is smaller than the CRC, 564 * drop this fragment, do the processing of 565 * the end of the packet. 566 */ 567 ASSERT(rx_ring->rx_mblk_tail != NULL); 568 rx_ring->rx_mblk_tail->b_wptr -= 569 ETHERFCSL - length; 570 rx_ring->rx_mblk_len -= 571 ETHERFCSL - length; 572 573 QUEUE_POP_HEAD(&rx_ring->recv_list); 574 575 goto rx_end_of_packet; 576 } 577 } 578 579 need_copy = B_TRUE; 580 581 if (length <= Adapter->rx_bcopy_thresh) 582 goto rx_copy; 583 584 /* 585 * Get the pre-constructed mblk that was associated 586 * to the receive data buffer. 587 */ 588 if (packet->mp == NULL) { 589 packet->mp = desballoc((unsigned char *) 590 rx_buf->address - E1000G_IPALIGNROOM, 591 length + E1000G_IPALIGNROOM, 592 BPRI_MED, &packet->free_rtn); 593 594 if (packet->mp != NULL) { 595 packet->mp->b_rptr += E1000G_IPALIGNROOM; 596 packet->mp->b_wptr += E1000G_IPALIGNROOM; 597 } else { 598 E1000G_STAT(rx_ring->stat_esballoc_fail); 599 } 600 } 601 602 if (packet->mp != NULL) { 603 /* 604 * We have two sets of buffer pool. One associated with 605 * the Rxdescriptors and other a freelist buffer pool. 606 * Each time we get a good packet, Try to get a buffer 607 * from the freelist pool using e1000g_get_buf. If we 608 * get free buffer, then replace the descriptor buffer 609 * address with the free buffer we just got, and pass 610 * the pre-constructed mblk upstack. (note no copying) 611 * 612 * If we failed to get a free buffer, then try to 613 * allocate a new buffer(mp) and copy the recv buffer 614 * content to our newly allocated buffer(mp). Don't 615 * disturb the desriptor buffer address. (note copying) 616 */ 617 newpkt = e1000g_get_buf(rx_ring); 618 619 if (newpkt != NULL) { 620 /* 621 * Get the mblk associated to the data, 622 * and strip it off the sw packet. 623 */ 624 nmp = packet->mp; 625 packet->mp = NULL; 626 packet->flag = E1000G_RX_SW_SENDUP; 627 628 /* 629 * Now replace old buffer with the new 630 * one we got from free list 631 * Both the RxSwPacket as well as the 632 * Receive Buffer Descriptor will now 633 * point to this new packet. 634 */ 635 packet = newpkt; 636 637 current_desc->buffer_addr = 638 newpkt->rx_buf->dma_address; 639 640 need_copy = B_FALSE; 641 } else { 642 E1000G_DEBUG_STAT(rx_ring->stat_no_freepkt); 643 } 644 } 645 646 rx_copy: 647 if (need_copy) { 648 /* 649 * No buffers available on free list, 650 * bcopy the data from the buffer and 651 * keep the original buffer. Dont want to 652 * do this.. Yack but no other way 653 */ 654 if ((nmp = allocb(length + E1000G_IPALIGNROOM, 655 BPRI_MED)) == NULL) { 656 /* 657 * The system has no buffers available 658 * to send up the incoming packet, hence 659 * the packet will have to be processed 660 * when there're more buffers available. 661 */ 662 E1000G_STAT(rx_ring->stat_allocb_fail); 663 goto rx_drop; 664 } 665 nmp->b_rptr += E1000G_IPALIGNROOM; 666 nmp->b_wptr += E1000G_IPALIGNROOM; 667 /* 668 * The free list did not have any buffers 669 * available, so, the received packet will 670 * have to be copied into a mp and the original 671 * buffer will have to be retained for future 672 * packet reception. 673 */ 674 bcopy(rx_buf->address, nmp->b_wptr, length); 675 } 676 677 /* 678 * The rx_sw_packet MUST be popped off the 679 * RxSwPacketList before either a putnext or freemsg 680 * is done on the mp that has now been created by the 681 * desballoc. If not, it is possible that the free 682 * routine will get called from the interrupt context 683 * and try to put this packet on the free list 684 */ 685 (p_rx_sw_packet_t)QUEUE_POP_HEAD(&rx_ring->recv_list); 686 687 ASSERT(nmp != NULL); 688 nmp->b_wptr += length; 689 690 if (rx_ring->rx_mblk == NULL) { 691 /* 692 * TCP/UDP checksum offload and 693 * IP checksum offload 694 */ 695 if (!(current_desc->status & E1000_RXD_STAT_IXSM)) { 696 /* 697 * Check TCP/UDP checksum 698 */ 699 if ((current_desc->status & 700 E1000_RXD_STAT_TCPCS) && 701 !(current_desc->errors & 702 E1000_RXD_ERR_TCPE)) 703 cksumflags |= HCK_FULLCKSUM | 704 HCK_FULLCKSUM_OK; 705 /* 706 * Check IP Checksum 707 */ 708 if ((current_desc->status & 709 E1000_RXD_STAT_IPCS) && 710 !(current_desc->errors & 711 E1000_RXD_ERR_IPE)) 712 cksumflags |= HCK_IPV4_HDRCKSUM; 713 } 714 } 715 716 /* 717 * We need to maintain our packet chain in the global 718 * Adapter structure, for the Rx processing can end 719 * with a fragment that has no EOP set. 720 */ 721 if (rx_ring->rx_mblk == NULL) { 722 /* Get the head of the message chain */ 723 rx_ring->rx_mblk = nmp; 724 rx_ring->rx_mblk_tail = nmp; 725 rx_ring->rx_mblk_len = length; 726 } else { /* Not the first packet */ 727 /* Continue adding buffers */ 728 rx_ring->rx_mblk_tail->b_cont = nmp; 729 rx_ring->rx_mblk_tail = nmp; 730 rx_ring->rx_mblk_len += length; 731 } 732 ASSERT(rx_ring->rx_mblk != NULL); 733 ASSERT(rx_ring->rx_mblk_tail != NULL); 734 ASSERT(rx_ring->rx_mblk_tail->b_cont == NULL); 735 736 /* 737 * Now this MP is ready to travel upwards but some more 738 * fragments are coming. 739 * We will send packet upwards as soon as we get EOP 740 * set on the packet. 741 */ 742 if (!end_of_packet) { 743 /* 744 * continue to get the next descriptor, 745 * Tail would be advanced at the end 746 */ 747 goto rx_next_desc; 748 } 749 750 rx_end_of_packet: 751 /* 752 * Found packet with EOP 753 * Process the last fragment. 754 */ 755 if (cksumflags != 0) { 756 (void) hcksum_assoc(rx_ring->rx_mblk, 757 NULL, NULL, 0, 0, 0, 0, cksumflags, 0); 758 cksumflags = 0; 759 } 760 761 /* 762 * Count packets that span multi-descriptors 763 */ 764 E1000G_DEBUG_STAT_COND(rx_ring->stat_multi_desc, 765 (rx_ring->rx_mblk->b_cont != NULL)); 766 767 /* 768 * Append to list to send upstream 769 */ 770 if (ret_mp == NULL) { 771 ret_mp = ret_nmp = rx_ring->rx_mblk; 772 } else { 773 ret_nmp->b_next = rx_ring->rx_mblk; 774 ret_nmp = rx_ring->rx_mblk; 775 } 776 ret_nmp->b_next = NULL; 777 778 rx_ring->rx_mblk = NULL; 779 rx_ring->rx_mblk_tail = NULL; 780 rx_ring->rx_mblk_len = 0; 781 782 pkt_count++; 783 784 rx_next_desc: 785 /* 786 * Zero out the receive descriptors status 787 */ 788 current_desc->status = 0; 789 790 if (current_desc == rx_ring->rbd_last) 791 rx_ring->rbd_next = rx_ring->rbd_first; 792 else 793 rx_ring->rbd_next++; 794 795 last_desc = current_desc; 796 current_desc = rx_ring->rbd_next; 797 798 /* 799 * Put the buffer that we just indicated back 800 * at the end of our list 801 */ 802 QUEUE_PUSH_TAIL(&rx_ring->recv_list, 803 &packet->Link); 804 } /* while loop */ 805 806 /* Sync the Rx descriptor DMA buffers */ 807 (void) ddi_dma_sync(rx_ring->rbd_dma_handle, 808 0, 0, DDI_DMA_SYNC_FORDEV); 809 810 /* 811 * Advance the E1000's Receive Queue #0 "Tail Pointer". 812 */ 813 E1000_WRITE_REG(hw, E1000_RDT(0), 814 (uint32_t)(last_desc - rx_ring->rbd_first)); 815 816 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 817 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 818 Adapter->chip_state = E1000G_ERROR; 819 } 820 821 Adapter->rx_pkt_cnt = pkt_count; 822 823 return (ret_mp); 824 825 rx_drop: 826 /* 827 * Zero out the receive descriptors status 828 */ 829 current_desc->status = 0; 830 831 /* Sync the Rx descriptor DMA buffers */ 832 (void) ddi_dma_sync(rx_ring->rbd_dma_handle, 833 0, 0, DDI_DMA_SYNC_FORDEV); 834 835 if (current_desc == rx_ring->rbd_last) 836 rx_ring->rbd_next = rx_ring->rbd_first; 837 else 838 rx_ring->rbd_next++; 839 840 last_desc = current_desc; 841 842 (p_rx_sw_packet_t)QUEUE_POP_HEAD(&rx_ring->recv_list); 843 844 QUEUE_PUSH_TAIL(&rx_ring->recv_list, &packet->Link); 845 /* 846 * Reclaim all old buffers already allocated during 847 * Jumbo receives.....for incomplete reception 848 */ 849 if (rx_ring->rx_mblk != NULL) { 850 freemsg(rx_ring->rx_mblk); 851 rx_ring->rx_mblk = NULL; 852 rx_ring->rx_mblk_tail = NULL; 853 rx_ring->rx_mblk_len = 0; 854 } 855 /* 856 * Advance the E1000's Receive Queue #0 "Tail Pointer". 857 */ 858 E1000_WRITE_REG(hw, E1000_RDT(0), 859 (uint32_t)(last_desc - rx_ring->rbd_first)); 860 861 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 862 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 863 Adapter->chip_state = E1000G_ERROR; 864 } 865 866 return (ret_mp); 867 } 868