1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 /* 26 * Copyright 2011 Nexenta Systems, Inc. All rights reserved. 27 */ 28 29 /* 30 * ********************************************************************** 31 * * 32 * Module Name: * 33 * e1000g_main.c * 34 * * 35 * Abstract: * 36 * This file contains the interface routines for the solaris OS. * 37 * It has all DDI entry point routines and GLD entry point routines. * 38 * * 39 * This file also contains routines that take care of initialization * 40 * uninit routine and interrupt routine. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/dlpi.h> 46 #include <sys/mac.h> 47 #include "e1000g_sw.h" 48 #include "e1000g_debug.h" 49 50 static char ident[] = "Intel PRO/1000 Ethernet"; 51 /* LINTED E_STATIC_UNUSED */ 52 static char e1000g_version[] = "Driver Ver. 5.3.24"; 53 54 /* 55 * Proto types for DDI entry points 56 */ 57 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 58 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 59 static int e1000g_quiesce(dev_info_t *); 60 61 /* 62 * init and intr routines prototype 63 */ 64 static int e1000g_resume(dev_info_t *); 65 static int e1000g_suspend(dev_info_t *); 66 static uint_t e1000g_intr_pciexpress(caddr_t); 67 static uint_t e1000g_intr(caddr_t); 68 static void e1000g_intr_work(struct e1000g *, uint32_t); 69 #pragma inline(e1000g_intr_work) 70 static int e1000g_init(struct e1000g *); 71 static int e1000g_start(struct e1000g *, boolean_t); 72 static void e1000g_stop(struct e1000g *, boolean_t); 73 static int e1000g_m_start(void *); 74 static void e1000g_m_stop(void *); 75 static int e1000g_m_promisc(void *, boolean_t); 76 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 77 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 78 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 79 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 80 uint_t, const void *); 81 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 82 uint_t, void *); 83 static void e1000g_m_propinfo(void *, const char *, mac_prop_id_t, 84 mac_prop_info_handle_t); 85 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 86 const void *); 87 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, void *); 88 static void e1000g_init_locks(struct e1000g *); 89 static void e1000g_destroy_locks(struct e1000g *); 90 static int e1000g_identify_hardware(struct e1000g *); 91 static int e1000g_regs_map(struct e1000g *); 92 static int e1000g_set_driver_params(struct e1000g *); 93 static void e1000g_set_bufsize(struct e1000g *); 94 static int e1000g_register_mac(struct e1000g *); 95 static boolean_t e1000g_rx_drain(struct e1000g *); 96 static boolean_t e1000g_tx_drain(struct e1000g *); 97 static void e1000g_init_unicst(struct e1000g *); 98 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 99 static int e1000g_alloc_rx_data(struct e1000g *); 100 static void e1000g_release_multicast(struct e1000g *); 101 static void e1000g_pch_limits(struct e1000g *); 102 static uint32_t e1000g_mtu2maxframe(uint32_t); 103 104 /* 105 * Local routines 106 */ 107 static boolean_t e1000g_reset_adapter(struct e1000g *); 108 static void e1000g_tx_clean(struct e1000g *); 109 static void e1000g_rx_clean(struct e1000g *); 110 static void e1000g_link_timer(void *); 111 static void e1000g_local_timer(void *); 112 static boolean_t e1000g_link_check(struct e1000g *); 113 static boolean_t e1000g_stall_check(struct e1000g *); 114 static void e1000g_smartspeed(struct e1000g *); 115 static void e1000g_get_conf(struct e1000g *); 116 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 117 int *); 118 static void enable_watchdog_timer(struct e1000g *); 119 static void disable_watchdog_timer(struct e1000g *); 120 static void start_watchdog_timer(struct e1000g *); 121 static void restart_watchdog_timer(struct e1000g *); 122 static void stop_watchdog_timer(struct e1000g *); 123 static void stop_link_timer(struct e1000g *); 124 static void stop_82547_timer(e1000g_tx_ring_t *); 125 static void e1000g_force_speed_duplex(struct e1000g *); 126 static void e1000g_setup_max_mtu(struct e1000g *); 127 static void e1000g_get_max_frame_size(struct e1000g *); 128 static boolean_t is_valid_mac_addr(uint8_t *); 129 static void e1000g_unattach(dev_info_t *, struct e1000g *); 130 static int e1000g_get_bar_info(dev_info_t *, int, bar_info_t *); 131 #ifdef E1000G_DEBUG 132 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 133 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 134 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 135 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 136 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 137 struct iocblk *, mblk_t *); 138 #endif 139 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 140 struct iocblk *, mblk_t *); 141 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 142 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 143 static void e1000g_set_internal_loopback(struct e1000g *); 144 static void e1000g_set_external_loopback_1000(struct e1000g *); 145 static void e1000g_set_external_loopback_100(struct e1000g *); 146 static void e1000g_set_external_loopback_10(struct e1000g *); 147 static int e1000g_add_intrs(struct e1000g *); 148 static int e1000g_intr_add(struct e1000g *, int); 149 static int e1000g_rem_intrs(struct e1000g *); 150 static int e1000g_enable_intrs(struct e1000g *); 151 static int e1000g_disable_intrs(struct e1000g *); 152 static boolean_t e1000g_link_up(struct e1000g *); 153 #ifdef __sparc 154 static boolean_t e1000g_find_mac_address(struct e1000g *); 155 #endif 156 static void e1000g_get_phy_state(struct e1000g *); 157 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 158 const void *impl_data); 159 static void e1000g_fm_init(struct e1000g *Adapter); 160 static void e1000g_fm_fini(struct e1000g *Adapter); 161 static void e1000g_param_sync(struct e1000g *); 162 static void e1000g_get_driver_control(struct e1000_hw *); 163 static void e1000g_release_driver_control(struct e1000_hw *); 164 static void e1000g_restore_promisc(struct e1000g *Adapter); 165 166 char *e1000g_priv_props[] = { 167 "_tx_bcopy_threshold", 168 "_tx_interrupt_enable", 169 "_tx_intr_delay", 170 "_tx_intr_abs_delay", 171 "_rx_bcopy_threshold", 172 "_max_num_rcv_packets", 173 "_rx_intr_delay", 174 "_rx_intr_abs_delay", 175 "_intr_throttling_rate", 176 "_intr_adaptive", 177 "_adv_pause_cap", 178 "_adv_asym_pause_cap", 179 NULL 180 }; 181 182 static struct cb_ops cb_ws_ops = { 183 nulldev, /* cb_open */ 184 nulldev, /* cb_close */ 185 nodev, /* cb_strategy */ 186 nodev, /* cb_print */ 187 nodev, /* cb_dump */ 188 nodev, /* cb_read */ 189 nodev, /* cb_write */ 190 nodev, /* cb_ioctl */ 191 nodev, /* cb_devmap */ 192 nodev, /* cb_mmap */ 193 nodev, /* cb_segmap */ 194 nochpoll, /* cb_chpoll */ 195 ddi_prop_op, /* cb_prop_op */ 196 NULL, /* cb_stream */ 197 D_MP | D_HOTPLUG, /* cb_flag */ 198 CB_REV, /* cb_rev */ 199 nodev, /* cb_aread */ 200 nodev /* cb_awrite */ 201 }; 202 203 static struct dev_ops ws_ops = { 204 DEVO_REV, /* devo_rev */ 205 0, /* devo_refcnt */ 206 NULL, /* devo_getinfo */ 207 nulldev, /* devo_identify */ 208 nulldev, /* devo_probe */ 209 e1000g_attach, /* devo_attach */ 210 e1000g_detach, /* devo_detach */ 211 nodev, /* devo_reset */ 212 &cb_ws_ops, /* devo_cb_ops */ 213 NULL, /* devo_bus_ops */ 214 ddi_power, /* devo_power */ 215 e1000g_quiesce /* devo_quiesce */ 216 }; 217 218 static struct modldrv modldrv = { 219 &mod_driverops, /* Type of module. This one is a driver */ 220 ident, /* Discription string */ 221 &ws_ops, /* driver ops */ 222 }; 223 224 static struct modlinkage modlinkage = { 225 MODREV_1, &modldrv, NULL 226 }; 227 228 /* Access attributes for register mapping */ 229 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 230 DDI_DEVICE_ATTR_V1, 231 DDI_STRUCTURE_LE_ACC, 232 DDI_STRICTORDER_ACC, 233 DDI_FLAGERR_ACC 234 }; 235 236 #define E1000G_M_CALLBACK_FLAGS \ 237 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 238 239 static mac_callbacks_t e1000g_m_callbacks = { 240 E1000G_M_CALLBACK_FLAGS, 241 e1000g_m_stat, 242 e1000g_m_start, 243 e1000g_m_stop, 244 e1000g_m_promisc, 245 e1000g_m_multicst, 246 NULL, 247 e1000g_m_tx, 248 NULL, 249 e1000g_m_ioctl, 250 e1000g_m_getcapab, 251 NULL, 252 NULL, 253 e1000g_m_setprop, 254 e1000g_m_getprop, 255 e1000g_m_propinfo 256 }; 257 258 /* 259 * Global variables 260 */ 261 uint32_t e1000g_jumbo_mtu = MAXIMUM_MTU_9K; 262 uint32_t e1000g_mblks_pending = 0; 263 /* 264 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 265 * Here we maintain a private dev_info list if e1000g_force_detach is 266 * enabled. If we force the driver to detach while there are still some 267 * rx buffers retained in the upper layer, we have to keep a copy of the 268 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 269 * structure will be freed after the driver is detached. However when we 270 * finally free those rx buffers released by the upper layer, we need to 271 * refer to the dev_info to free the dma buffers. So we save a copy of 272 * the dev_info for this purpose. On x86 platform, we assume this copy 273 * of dev_info is always valid, but on SPARC platform, it could be invalid 274 * after the system board level DR operation. For this reason, the global 275 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 276 */ 277 #ifdef __sparc 278 boolean_t e1000g_force_detach = B_FALSE; 279 #else 280 boolean_t e1000g_force_detach = B_TRUE; 281 #endif 282 private_devi_list_t *e1000g_private_devi_list = NULL; 283 284 /* 285 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 286 * the private dev_info list, and to serialize the processing of rx buffer 287 * freeing and rx buffer recycling. 288 */ 289 kmutex_t e1000g_rx_detach_lock; 290 /* 291 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 292 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 293 * If there are many e1000g instances, the system may run out of DVMA 294 * resources during the initialization of the instances, then the flag will 295 * be changed to "USE_DMA". Because different e1000g instances are initialized 296 * in parallel, we need to use this lock to protect the flag. 297 */ 298 krwlock_t e1000g_dma_type_lock; 299 300 /* 301 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 302 * Based on the information from Intel, the 82546 chipset has some hardware 303 * problem. When one port is being reset and the other port is trying to 304 * access the eeprom, it could cause system hang or panic. To workaround this 305 * hardware problem, we use a global mutex to prevent such operations from 306 * happening simultaneously on different instances. This workaround is applied 307 * to all the devices supported by this driver. 308 */ 309 kmutex_t e1000g_nvm_lock; 310 311 /* 312 * Loadable module configuration entry points for the driver 313 */ 314 315 /* 316 * _init - module initialization 317 */ 318 int 319 _init(void) 320 { 321 int status; 322 323 mac_init_ops(&ws_ops, WSNAME); 324 status = mod_install(&modlinkage); 325 if (status != DDI_SUCCESS) 326 mac_fini_ops(&ws_ops); 327 else { 328 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 329 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 330 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 331 } 332 333 return (status); 334 } 335 336 /* 337 * _fini - module finalization 338 */ 339 int 340 _fini(void) 341 { 342 int status; 343 344 if (e1000g_mblks_pending != 0) 345 return (EBUSY); 346 347 status = mod_remove(&modlinkage); 348 if (status == DDI_SUCCESS) { 349 mac_fini_ops(&ws_ops); 350 351 if (e1000g_force_detach) { 352 private_devi_list_t *devi_node; 353 354 mutex_enter(&e1000g_rx_detach_lock); 355 while (e1000g_private_devi_list != NULL) { 356 devi_node = e1000g_private_devi_list; 357 e1000g_private_devi_list = 358 e1000g_private_devi_list->next; 359 360 kmem_free(devi_node->priv_dip, 361 sizeof (struct dev_info)); 362 kmem_free(devi_node, 363 sizeof (private_devi_list_t)); 364 } 365 mutex_exit(&e1000g_rx_detach_lock); 366 } 367 368 mutex_destroy(&e1000g_rx_detach_lock); 369 rw_destroy(&e1000g_dma_type_lock); 370 mutex_destroy(&e1000g_nvm_lock); 371 } 372 373 return (status); 374 } 375 376 /* 377 * _info - module information 378 */ 379 int 380 _info(struct modinfo *modinfop) 381 { 382 return (mod_info(&modlinkage, modinfop)); 383 } 384 385 /* 386 * e1000g_attach - driver attach 387 * 388 * This function is the device-specific initialization entry 389 * point. This entry point is required and must be written. 390 * The DDI_ATTACH command must be provided in the attach entry 391 * point. When attach() is called with cmd set to DDI_ATTACH, 392 * all normal kernel services (such as kmem_alloc(9F)) are 393 * available for use by the driver. 394 * 395 * The attach() function will be called once for each instance 396 * of the device on the system with cmd set to DDI_ATTACH. 397 * Until attach() succeeds, the only driver entry points which 398 * may be called are open(9E) and getinfo(9E). 399 */ 400 static int 401 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 402 { 403 struct e1000g *Adapter; 404 struct e1000_hw *hw; 405 struct e1000g_osdep *osdep; 406 int instance; 407 408 switch (cmd) { 409 default: 410 e1000g_log(NULL, CE_WARN, 411 "Unsupported command send to e1000g_attach... "); 412 return (DDI_FAILURE); 413 414 case DDI_RESUME: 415 return (e1000g_resume(devinfo)); 416 417 case DDI_ATTACH: 418 break; 419 } 420 421 /* 422 * get device instance number 423 */ 424 instance = ddi_get_instance(devinfo); 425 426 /* 427 * Allocate soft data structure 428 */ 429 Adapter = 430 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 431 432 Adapter->dip = devinfo; 433 Adapter->instance = instance; 434 Adapter->tx_ring->adapter = Adapter; 435 Adapter->rx_ring->adapter = Adapter; 436 437 hw = &Adapter->shared; 438 osdep = &Adapter->osdep; 439 hw->back = osdep; 440 osdep->adapter = Adapter; 441 442 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 443 444 /* 445 * Initialize for fma support 446 */ 447 (void) e1000g_get_prop(Adapter, "fm-capable", 448 0, 0x0f, 449 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 450 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 451 &Adapter->fm_capabilities); 452 e1000g_fm_init(Adapter); 453 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 454 455 /* 456 * PCI Configure 457 */ 458 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 459 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 460 goto attach_fail; 461 } 462 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 463 464 /* 465 * Setup hardware 466 */ 467 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 468 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 469 goto attach_fail; 470 } 471 472 /* 473 * Map in the device registers. 474 */ 475 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 476 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 477 goto attach_fail; 478 } 479 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 480 481 /* 482 * Initialize driver parameters 483 */ 484 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 485 goto attach_fail; 486 } 487 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 488 489 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 490 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 491 goto attach_fail; 492 } 493 494 /* 495 * Initialize interrupts 496 */ 497 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 498 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 499 goto attach_fail; 500 } 501 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 502 503 /* 504 * Initialize mutex's for this device. 505 * Do this before enabling the interrupt handler and 506 * register the softint to avoid the condition where 507 * interrupt handler can try using uninitialized mutex 508 */ 509 e1000g_init_locks(Adapter); 510 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 511 512 /* 513 * Initialize Driver Counters 514 */ 515 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 516 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 517 goto attach_fail; 518 } 519 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 520 521 /* 522 * Initialize chip hardware and software structures 523 */ 524 rw_enter(&Adapter->chip_lock, RW_WRITER); 525 if (e1000g_init(Adapter) != DDI_SUCCESS) { 526 rw_exit(&Adapter->chip_lock); 527 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 528 goto attach_fail; 529 } 530 rw_exit(&Adapter->chip_lock); 531 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 532 533 /* 534 * Register the driver to the MAC 535 */ 536 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 537 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 538 goto attach_fail; 539 } 540 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 541 542 /* 543 * Now that mutex locks are initialized, and the chip is also 544 * initialized, enable interrupts. 545 */ 546 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 547 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 548 goto attach_fail; 549 } 550 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 551 552 /* 553 * If e1000g_force_detach is enabled, in global private dip list, 554 * we will create a new entry, which maintains the priv_dip for DR 555 * supports after driver detached. 556 */ 557 if (e1000g_force_detach) { 558 private_devi_list_t *devi_node; 559 560 Adapter->priv_dip = 561 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 562 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 563 sizeof (struct dev_info)); 564 565 devi_node = 566 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 567 568 mutex_enter(&e1000g_rx_detach_lock); 569 devi_node->priv_dip = Adapter->priv_dip; 570 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 571 devi_node->pending_rx_count = 0; 572 573 Adapter->priv_devi_node = devi_node; 574 575 if (e1000g_private_devi_list == NULL) { 576 devi_node->prev = NULL; 577 devi_node->next = NULL; 578 e1000g_private_devi_list = devi_node; 579 } else { 580 devi_node->prev = NULL; 581 devi_node->next = e1000g_private_devi_list; 582 e1000g_private_devi_list->prev = devi_node; 583 e1000g_private_devi_list = devi_node; 584 } 585 mutex_exit(&e1000g_rx_detach_lock); 586 } 587 588 Adapter->e1000g_state = E1000G_INITIALIZED; 589 return (DDI_SUCCESS); 590 591 attach_fail: 592 e1000g_unattach(devinfo, Adapter); 593 return (DDI_FAILURE); 594 } 595 596 static int 597 e1000g_register_mac(struct e1000g *Adapter) 598 { 599 struct e1000_hw *hw = &Adapter->shared; 600 mac_register_t *mac; 601 int err; 602 603 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 604 return (DDI_FAILURE); 605 606 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 607 mac->m_driver = Adapter; 608 mac->m_dip = Adapter->dip; 609 mac->m_src_addr = hw->mac.addr; 610 mac->m_callbacks = &e1000g_m_callbacks; 611 mac->m_min_sdu = 0; 612 mac->m_max_sdu = Adapter->default_mtu; 613 mac->m_margin = VLAN_TAGSZ; 614 mac->m_priv_props = e1000g_priv_props; 615 mac->m_v12n = MAC_VIRT_LEVEL1; 616 617 err = mac_register(mac, &Adapter->mh); 618 mac_free(mac); 619 620 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 621 } 622 623 static int 624 e1000g_identify_hardware(struct e1000g *Adapter) 625 { 626 struct e1000_hw *hw = &Adapter->shared; 627 struct e1000g_osdep *osdep = &Adapter->osdep; 628 629 /* Get the device id */ 630 hw->vendor_id = 631 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 632 hw->device_id = 633 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 634 hw->revision_id = 635 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 636 hw->subsystem_device_id = 637 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 638 hw->subsystem_vendor_id = 639 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 640 641 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 642 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 643 "MAC type could not be set properly."); 644 return (DDI_FAILURE); 645 } 646 647 return (DDI_SUCCESS); 648 } 649 650 static int 651 e1000g_regs_map(struct e1000g *Adapter) 652 { 653 dev_info_t *devinfo = Adapter->dip; 654 struct e1000_hw *hw = &Adapter->shared; 655 struct e1000g_osdep *osdep = &Adapter->osdep; 656 off_t mem_size; 657 bar_info_t bar_info; 658 int offset, rnumber; 659 660 rnumber = ADAPTER_REG_SET; 661 /* Get size of adapter register memory */ 662 if (ddi_dev_regsize(devinfo, rnumber, &mem_size) != 663 DDI_SUCCESS) { 664 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 665 "ddi_dev_regsize for registers failed"); 666 return (DDI_FAILURE); 667 } 668 669 /* Map adapter register memory */ 670 if ((ddi_regs_map_setup(devinfo, rnumber, 671 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 672 &osdep->reg_handle)) != DDI_SUCCESS) { 673 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 674 "ddi_regs_map_setup for registers failed"); 675 goto regs_map_fail; 676 } 677 678 /* ICH needs to map flash memory */ 679 switch (hw->mac.type) { 680 case e1000_ich8lan: 681 case e1000_ich9lan: 682 case e1000_ich10lan: 683 case e1000_pchlan: 684 case e1000_pch2lan: 685 rnumber = ICH_FLASH_REG_SET; 686 687 /* get flash size */ 688 if (ddi_dev_regsize(devinfo, rnumber, 689 &mem_size) != DDI_SUCCESS) { 690 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 691 "ddi_dev_regsize for ICH flash failed"); 692 goto regs_map_fail; 693 } 694 695 /* map flash in */ 696 if (ddi_regs_map_setup(devinfo, rnumber, 697 (caddr_t *)&hw->flash_address, 0, 698 mem_size, &e1000g_regs_acc_attr, 699 &osdep->ich_flash_handle) != DDI_SUCCESS) { 700 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 701 "ddi_regs_map_setup for ICH flash failed"); 702 goto regs_map_fail; 703 } 704 break; 705 default: 706 break; 707 } 708 709 /* map io space */ 710 switch (hw->mac.type) { 711 case e1000_82544: 712 case e1000_82540: 713 case e1000_82545: 714 case e1000_82546: 715 case e1000_82541: 716 case e1000_82541_rev_2: 717 /* find the IO bar */ 718 rnumber = -1; 719 for (offset = PCI_CONF_BASE1; 720 offset <= PCI_CONF_BASE5; offset += 4) { 721 if (e1000g_get_bar_info(devinfo, offset, &bar_info) 722 != DDI_SUCCESS) 723 continue; 724 if (bar_info.type == E1000G_BAR_IO) { 725 rnumber = bar_info.rnumber; 726 break; 727 } 728 } 729 730 if (rnumber < 0) { 731 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 732 "No io space is found"); 733 goto regs_map_fail; 734 } 735 736 /* get io space size */ 737 if (ddi_dev_regsize(devinfo, rnumber, 738 &mem_size) != DDI_SUCCESS) { 739 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 740 "ddi_dev_regsize for io space failed"); 741 goto regs_map_fail; 742 } 743 744 /* map io space */ 745 if ((ddi_regs_map_setup(devinfo, rnumber, 746 (caddr_t *)&hw->io_base, 0, mem_size, 747 &e1000g_regs_acc_attr, 748 &osdep->io_reg_handle)) != DDI_SUCCESS) { 749 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 750 "ddi_regs_map_setup for io space failed"); 751 goto regs_map_fail; 752 } 753 break; 754 default: 755 hw->io_base = 0; 756 break; 757 } 758 759 return (DDI_SUCCESS); 760 761 regs_map_fail: 762 if (osdep->reg_handle != NULL) 763 ddi_regs_map_free(&osdep->reg_handle); 764 if (osdep->ich_flash_handle != NULL) 765 ddi_regs_map_free(&osdep->ich_flash_handle); 766 return (DDI_FAILURE); 767 } 768 769 static int 770 e1000g_set_driver_params(struct e1000g *Adapter) 771 { 772 struct e1000_hw *hw; 773 774 hw = &Adapter->shared; 775 776 /* Set MAC type and initialize hardware functions */ 777 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 778 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 779 "Could not setup hardware functions"); 780 return (DDI_FAILURE); 781 } 782 783 /* Get bus information */ 784 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 785 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 786 "Could not get bus information"); 787 return (DDI_FAILURE); 788 } 789 790 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 791 792 hw->mac.autoneg_failed = B_TRUE; 793 794 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 795 hw->phy.autoneg_wait_to_complete = B_FALSE; 796 797 /* Adaptive IFS related changes */ 798 hw->mac.adaptive_ifs = B_TRUE; 799 800 /* Enable phy init script for IGP phy of 82541/82547 */ 801 if ((hw->mac.type == e1000_82547) || 802 (hw->mac.type == e1000_82541) || 803 (hw->mac.type == e1000_82547_rev_2) || 804 (hw->mac.type == e1000_82541_rev_2)) 805 e1000_init_script_state_82541(hw, B_TRUE); 806 807 /* Enable the TTL workaround for 82541/82547 */ 808 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 809 810 #ifdef __sparc 811 Adapter->strip_crc = B_TRUE; 812 #else 813 Adapter->strip_crc = B_FALSE; 814 #endif 815 816 /* setup the maximum MTU size of the chip */ 817 e1000g_setup_max_mtu(Adapter); 818 819 /* Get speed/duplex settings in conf file */ 820 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 821 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 822 e1000g_force_speed_duplex(Adapter); 823 824 /* Get Jumbo Frames settings in conf file */ 825 e1000g_get_max_frame_size(Adapter); 826 827 /* Get conf file properties */ 828 e1000g_get_conf(Adapter); 829 830 /* enforce PCH limits */ 831 e1000g_pch_limits(Adapter); 832 833 /* Set Rx/Tx buffer size */ 834 e1000g_set_bufsize(Adapter); 835 836 /* Master Latency Timer */ 837 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 838 839 /* copper options */ 840 if (hw->phy.media_type == e1000_media_type_copper) { 841 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 842 hw->phy.disable_polarity_correction = B_FALSE; 843 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 844 } 845 846 /* The initial link state should be "unknown" */ 847 Adapter->link_state = LINK_STATE_UNKNOWN; 848 849 /* Initialize rx parameters */ 850 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 851 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 852 853 /* Initialize tx parameters */ 854 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 855 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 856 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 857 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 858 859 /* Initialize rx parameters */ 860 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 861 862 return (DDI_SUCCESS); 863 } 864 865 static void 866 e1000g_setup_max_mtu(struct e1000g *Adapter) 867 { 868 struct e1000_mac_info *mac = &Adapter->shared.mac; 869 struct e1000_phy_info *phy = &Adapter->shared.phy; 870 871 switch (mac->type) { 872 /* types that do not support jumbo frames */ 873 case e1000_ich8lan: 874 case e1000_82573: 875 case e1000_82583: 876 Adapter->max_mtu = ETHERMTU; 877 break; 878 /* ich9 supports jumbo frames except on one phy type */ 879 case e1000_ich9lan: 880 if (phy->type == e1000_phy_ife) 881 Adapter->max_mtu = ETHERMTU; 882 else 883 Adapter->max_mtu = MAXIMUM_MTU_9K; 884 break; 885 /* pch can do jumbo frames up to 4K */ 886 case e1000_pchlan: 887 Adapter->max_mtu = MAXIMUM_MTU_4K; 888 break; 889 /* pch2 can do jumbo frames up to 9K */ 890 case e1000_pch2lan: 891 Adapter->max_mtu = MAXIMUM_MTU_9K; 892 break; 893 /* types with a special limit */ 894 case e1000_82571: 895 case e1000_82572: 896 case e1000_82574: 897 case e1000_80003es2lan: 898 case e1000_ich10lan: 899 if (e1000g_jumbo_mtu >= ETHERMTU && 900 e1000g_jumbo_mtu <= MAXIMUM_MTU_9K) { 901 Adapter->max_mtu = e1000g_jumbo_mtu; 902 } else { 903 Adapter->max_mtu = MAXIMUM_MTU_9K; 904 } 905 break; 906 /* default limit is 16K */ 907 default: 908 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 909 sizeof (struct ether_vlan_header) - ETHERFCSL; 910 break; 911 } 912 } 913 914 static void 915 e1000g_set_bufsize(struct e1000g *Adapter) 916 { 917 struct e1000_mac_info *mac = &Adapter->shared.mac; 918 uint64_t rx_size; 919 uint64_t tx_size; 920 921 dev_info_t *devinfo = Adapter->dip; 922 #ifdef __sparc 923 ulong_t iommu_pagesize; 924 #endif 925 /* Get the system page size */ 926 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 927 928 #ifdef __sparc 929 iommu_pagesize = dvma_pagesize(devinfo); 930 if (iommu_pagesize != 0) { 931 if (Adapter->sys_page_sz == iommu_pagesize) { 932 if (iommu_pagesize > 0x4000) 933 Adapter->sys_page_sz = 0x4000; 934 } else { 935 if (Adapter->sys_page_sz > iommu_pagesize) 936 Adapter->sys_page_sz = iommu_pagesize; 937 } 938 } 939 if (Adapter->lso_enable) { 940 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 941 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 942 } else { 943 Adapter->dvma_page_num = Adapter->max_frame_size / 944 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 945 } 946 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 947 #endif 948 949 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 950 951 if (Adapter->mem_workaround_82546 && 952 ((mac->type == e1000_82545) || 953 (mac->type == e1000_82546) || 954 (mac->type == e1000_82546_rev_3))) { 955 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 956 } else { 957 rx_size = Adapter->max_frame_size; 958 if ((rx_size > FRAME_SIZE_UPTO_2K) && 959 (rx_size <= FRAME_SIZE_UPTO_4K)) 960 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 961 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 962 (rx_size <= FRAME_SIZE_UPTO_8K)) 963 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 964 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 965 (rx_size <= FRAME_SIZE_UPTO_16K)) 966 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 967 else 968 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 969 } 970 Adapter->rx_buffer_size += E1000G_IPALIGNROOM; 971 972 tx_size = Adapter->max_frame_size; 973 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 974 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 975 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 976 (tx_size <= FRAME_SIZE_UPTO_8K)) 977 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 978 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 979 (tx_size <= FRAME_SIZE_UPTO_16K)) 980 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 981 else 982 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 983 984 /* 985 * For Wiseman adapters we have an requirement of having receive 986 * buffers aligned at 256 byte boundary. Since Livengood does not 987 * require this and forcing it for all hardwares will have 988 * performance implications, I am making it applicable only for 989 * Wiseman and for Jumbo frames enabled mode as rest of the time, 990 * it is okay to have normal frames...but it does involve a 991 * potential risk where we may loose data if buffer is not 992 * aligned...so all wiseman boards to have 256 byte aligned 993 * buffers 994 */ 995 if (mac->type < e1000_82543) 996 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 997 else 998 Adapter->rx_buf_align = 1; 999 } 1000 1001 /* 1002 * e1000g_detach - driver detach 1003 * 1004 * The detach() function is the complement of the attach routine. 1005 * If cmd is set to DDI_DETACH, detach() is used to remove the 1006 * state associated with a given instance of a device node 1007 * prior to the removal of that instance from the system. 1008 * 1009 * The detach() function will be called once for each instance 1010 * of the device for which there has been a successful attach() 1011 * once there are no longer any opens on the device. 1012 * 1013 * Interrupts routine are disabled, All memory allocated by this 1014 * driver are freed. 1015 */ 1016 static int 1017 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 1018 { 1019 struct e1000g *Adapter; 1020 boolean_t rx_drain; 1021 1022 switch (cmd) { 1023 default: 1024 return (DDI_FAILURE); 1025 1026 case DDI_SUSPEND: 1027 return (e1000g_suspend(devinfo)); 1028 1029 case DDI_DETACH: 1030 break; 1031 } 1032 1033 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1034 if (Adapter == NULL) 1035 return (DDI_FAILURE); 1036 1037 rx_drain = e1000g_rx_drain(Adapter); 1038 if (!rx_drain && !e1000g_force_detach) 1039 return (DDI_FAILURE); 1040 1041 if (mac_unregister(Adapter->mh) != 0) { 1042 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 1043 return (DDI_FAILURE); 1044 } 1045 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 1046 1047 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 1048 1049 if (!e1000g_force_detach && !rx_drain) 1050 return (DDI_FAILURE); 1051 1052 e1000g_unattach(devinfo, Adapter); 1053 1054 return (DDI_SUCCESS); 1055 } 1056 1057 /* 1058 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1059 */ 1060 void 1061 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1062 { 1063 ASSERT(e1000g_private_devi_list != NULL); 1064 ASSERT(devi_node != NULL); 1065 1066 if (devi_node->prev != NULL) 1067 devi_node->prev->next = devi_node->next; 1068 if (devi_node->next != NULL) 1069 devi_node->next->prev = devi_node->prev; 1070 if (devi_node == e1000g_private_devi_list) 1071 e1000g_private_devi_list = devi_node->next; 1072 1073 kmem_free(devi_node->priv_dip, 1074 sizeof (struct dev_info)); 1075 kmem_free(devi_node, 1076 sizeof (private_devi_list_t)); 1077 } 1078 1079 static void 1080 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1081 { 1082 private_devi_list_t *devi_node; 1083 int result; 1084 1085 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1086 (void) e1000g_disable_intrs(Adapter); 1087 } 1088 1089 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1090 (void) mac_unregister(Adapter->mh); 1091 } 1092 1093 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1094 (void) e1000g_rem_intrs(Adapter); 1095 } 1096 1097 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1098 (void) ddi_prop_remove_all(devinfo); 1099 } 1100 1101 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1102 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1103 } 1104 1105 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1106 stop_link_timer(Adapter); 1107 1108 mutex_enter(&e1000g_nvm_lock); 1109 result = e1000_reset_hw(&Adapter->shared); 1110 mutex_exit(&e1000g_nvm_lock); 1111 1112 if (result != E1000_SUCCESS) { 1113 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1114 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1115 } 1116 } 1117 1118 e1000g_release_multicast(Adapter); 1119 1120 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1121 if (Adapter->osdep.reg_handle != NULL) 1122 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1123 if (Adapter->osdep.ich_flash_handle != NULL) 1124 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1125 if (Adapter->osdep.io_reg_handle != NULL) 1126 ddi_regs_map_free(&Adapter->osdep.io_reg_handle); 1127 } 1128 1129 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1130 if (Adapter->osdep.cfg_handle != NULL) 1131 pci_config_teardown(&Adapter->osdep.cfg_handle); 1132 } 1133 1134 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1135 e1000g_destroy_locks(Adapter); 1136 } 1137 1138 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1139 e1000g_fm_fini(Adapter); 1140 } 1141 1142 mutex_enter(&e1000g_rx_detach_lock); 1143 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1144 devi_node = Adapter->priv_devi_node; 1145 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1146 1147 if (devi_node->pending_rx_count == 0) { 1148 e1000g_free_priv_devi_node(devi_node); 1149 } 1150 } 1151 mutex_exit(&e1000g_rx_detach_lock); 1152 1153 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1154 1155 /* 1156 * Another hotplug spec requirement, 1157 * run ddi_set_driver_private(devinfo, null); 1158 */ 1159 ddi_set_driver_private(devinfo, NULL); 1160 } 1161 1162 /* 1163 * Get the BAR type and rnumber for a given PCI BAR offset 1164 */ 1165 static int 1166 e1000g_get_bar_info(dev_info_t *dip, int bar_offset, bar_info_t *bar_info) 1167 { 1168 pci_regspec_t *regs; 1169 uint_t regs_length; 1170 int type, rnumber, rcount; 1171 1172 ASSERT((bar_offset >= PCI_CONF_BASE0) && 1173 (bar_offset <= PCI_CONF_BASE5)); 1174 1175 /* 1176 * Get the DDI "reg" property 1177 */ 1178 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 1179 DDI_PROP_DONTPASS, "reg", (int **)®s, 1180 ®s_length) != DDI_PROP_SUCCESS) { 1181 return (DDI_FAILURE); 1182 } 1183 1184 rcount = regs_length * sizeof (int) / sizeof (pci_regspec_t); 1185 /* 1186 * Check the BAR offset 1187 */ 1188 for (rnumber = 0; rnumber < rcount; ++rnumber) { 1189 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) { 1190 type = regs[rnumber].pci_phys_hi & PCI_ADDR_MASK; 1191 break; 1192 } 1193 } 1194 1195 ddi_prop_free(regs); 1196 1197 if (rnumber >= rcount) 1198 return (DDI_FAILURE); 1199 1200 switch (type) { 1201 case PCI_ADDR_CONFIG: 1202 bar_info->type = E1000G_BAR_CONFIG; 1203 break; 1204 case PCI_ADDR_IO: 1205 bar_info->type = E1000G_BAR_IO; 1206 break; 1207 case PCI_ADDR_MEM32: 1208 bar_info->type = E1000G_BAR_MEM32; 1209 break; 1210 case PCI_ADDR_MEM64: 1211 bar_info->type = E1000G_BAR_MEM64; 1212 break; 1213 default: 1214 return (DDI_FAILURE); 1215 } 1216 bar_info->rnumber = rnumber; 1217 return (DDI_SUCCESS); 1218 } 1219 1220 static void 1221 e1000g_init_locks(struct e1000g *Adapter) 1222 { 1223 e1000g_tx_ring_t *tx_ring; 1224 e1000g_rx_ring_t *rx_ring; 1225 1226 rw_init(&Adapter->chip_lock, NULL, 1227 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1228 mutex_init(&Adapter->link_lock, NULL, 1229 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1230 mutex_init(&Adapter->watchdog_lock, NULL, 1231 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1232 1233 tx_ring = Adapter->tx_ring; 1234 1235 mutex_init(&tx_ring->tx_lock, NULL, 1236 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1237 mutex_init(&tx_ring->usedlist_lock, NULL, 1238 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1239 mutex_init(&tx_ring->freelist_lock, NULL, 1240 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1241 1242 rx_ring = Adapter->rx_ring; 1243 1244 mutex_init(&rx_ring->rx_lock, NULL, 1245 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1246 } 1247 1248 static void 1249 e1000g_destroy_locks(struct e1000g *Adapter) 1250 { 1251 e1000g_tx_ring_t *tx_ring; 1252 e1000g_rx_ring_t *rx_ring; 1253 1254 tx_ring = Adapter->tx_ring; 1255 mutex_destroy(&tx_ring->tx_lock); 1256 mutex_destroy(&tx_ring->usedlist_lock); 1257 mutex_destroy(&tx_ring->freelist_lock); 1258 1259 rx_ring = Adapter->rx_ring; 1260 mutex_destroy(&rx_ring->rx_lock); 1261 1262 mutex_destroy(&Adapter->link_lock); 1263 mutex_destroy(&Adapter->watchdog_lock); 1264 rw_destroy(&Adapter->chip_lock); 1265 1266 /* destory mutex initialized in shared code */ 1267 e1000_destroy_hw_mutex(&Adapter->shared); 1268 } 1269 1270 static int 1271 e1000g_resume(dev_info_t *devinfo) 1272 { 1273 struct e1000g *Adapter; 1274 1275 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1276 if (Adapter == NULL) 1277 e1000g_log(Adapter, CE_PANIC, 1278 "Instance pointer is null\n"); 1279 1280 if (Adapter->dip != devinfo) 1281 e1000g_log(Adapter, CE_PANIC, 1282 "Devinfo is not the same as saved devinfo\n"); 1283 1284 rw_enter(&Adapter->chip_lock, RW_WRITER); 1285 1286 if (Adapter->e1000g_state & E1000G_STARTED) { 1287 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1288 rw_exit(&Adapter->chip_lock); 1289 /* 1290 * We note the failure, but return success, as the 1291 * system is still usable without this controller. 1292 */ 1293 e1000g_log(Adapter, CE_WARN, 1294 "e1000g_resume: failed to restart controller\n"); 1295 return (DDI_SUCCESS); 1296 } 1297 /* Enable and start the watchdog timer */ 1298 enable_watchdog_timer(Adapter); 1299 } 1300 1301 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1302 1303 rw_exit(&Adapter->chip_lock); 1304 1305 return (DDI_SUCCESS); 1306 } 1307 1308 static int 1309 e1000g_suspend(dev_info_t *devinfo) 1310 { 1311 struct e1000g *Adapter; 1312 1313 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1314 if (Adapter == NULL) 1315 return (DDI_FAILURE); 1316 1317 rw_enter(&Adapter->chip_lock, RW_WRITER); 1318 1319 Adapter->e1000g_state |= E1000G_SUSPENDED; 1320 1321 /* if the port isn't plumbed, we can simply return */ 1322 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1323 rw_exit(&Adapter->chip_lock); 1324 return (DDI_SUCCESS); 1325 } 1326 1327 e1000g_stop(Adapter, B_FALSE); 1328 1329 rw_exit(&Adapter->chip_lock); 1330 1331 /* Disable and stop all the timers */ 1332 disable_watchdog_timer(Adapter); 1333 stop_link_timer(Adapter); 1334 stop_82547_timer(Adapter->tx_ring); 1335 1336 return (DDI_SUCCESS); 1337 } 1338 1339 static int 1340 e1000g_init(struct e1000g *Adapter) 1341 { 1342 uint32_t pba; 1343 uint32_t high_water; 1344 struct e1000_hw *hw; 1345 clock_t link_timeout; 1346 int result; 1347 1348 hw = &Adapter->shared; 1349 1350 /* 1351 * reset to put the hardware in a known state 1352 * before we try to do anything with the eeprom 1353 */ 1354 mutex_enter(&e1000g_nvm_lock); 1355 result = e1000_reset_hw(hw); 1356 mutex_exit(&e1000g_nvm_lock); 1357 1358 if (result != E1000_SUCCESS) { 1359 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1360 goto init_fail; 1361 } 1362 1363 mutex_enter(&e1000g_nvm_lock); 1364 result = e1000_validate_nvm_checksum(hw); 1365 if (result < E1000_SUCCESS) { 1366 /* 1367 * Some PCI-E parts fail the first check due to 1368 * the link being in sleep state. Call it again, 1369 * if it fails a second time its a real issue. 1370 */ 1371 result = e1000_validate_nvm_checksum(hw); 1372 } 1373 mutex_exit(&e1000g_nvm_lock); 1374 1375 if (result < E1000_SUCCESS) { 1376 e1000g_log(Adapter, CE_WARN, 1377 "Invalid NVM checksum. Please contact " 1378 "the vendor to update the NVM."); 1379 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1380 goto init_fail; 1381 } 1382 1383 result = 0; 1384 #ifdef __sparc 1385 /* 1386 * First, we try to get the local ethernet address from OBP. If 1387 * failed, then we get it from the EEPROM of NIC card. 1388 */ 1389 result = e1000g_find_mac_address(Adapter); 1390 #endif 1391 /* Get the local ethernet address. */ 1392 if (!result) { 1393 mutex_enter(&e1000g_nvm_lock); 1394 result = e1000_read_mac_addr(hw); 1395 mutex_exit(&e1000g_nvm_lock); 1396 } 1397 1398 if (result < E1000_SUCCESS) { 1399 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1400 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1401 goto init_fail; 1402 } 1403 1404 /* check for valid mac address */ 1405 if (!is_valid_mac_addr(hw->mac.addr)) { 1406 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1407 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1408 goto init_fail; 1409 } 1410 1411 /* Set LAA state for 82571 chipset */ 1412 e1000_set_laa_state_82571(hw, B_TRUE); 1413 1414 /* Master Latency Timer implementation */ 1415 if (Adapter->master_latency_timer) { 1416 pci_config_put8(Adapter->osdep.cfg_handle, 1417 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1418 } 1419 1420 if (hw->mac.type < e1000_82547) { 1421 /* 1422 * Total FIFO is 64K 1423 */ 1424 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1425 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1426 else 1427 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1428 } else if ((hw->mac.type == e1000_82571) || 1429 (hw->mac.type == e1000_82572) || 1430 (hw->mac.type == e1000_80003es2lan)) { 1431 /* 1432 * Total FIFO is 48K 1433 */ 1434 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1435 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1436 else 1437 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1438 } else if (hw->mac.type == e1000_82573) { 1439 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1440 } else if (hw->mac.type == e1000_82574) { 1441 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1442 pba = E1000_READ_REG(hw, E1000_PBA); 1443 } else if (hw->mac.type == e1000_ich8lan) { 1444 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1445 } else if (hw->mac.type == e1000_ich9lan) { 1446 pba = E1000_PBA_10K; 1447 } else if (hw->mac.type == e1000_ich10lan) { 1448 pba = E1000_PBA_10K; 1449 } else if (hw->mac.type == e1000_pchlan) { 1450 pba = E1000_PBA_26K; 1451 } else if (hw->mac.type == e1000_pch2lan) { 1452 pba = E1000_PBA_26K; 1453 } else { 1454 /* 1455 * Total FIFO is 40K 1456 */ 1457 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1458 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1459 else 1460 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1461 } 1462 E1000_WRITE_REG(hw, E1000_PBA, pba); 1463 1464 /* 1465 * These parameters set thresholds for the adapter's generation(Tx) 1466 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1467 * settings. Flow control is enabled or disabled in the configuration 1468 * file. 1469 * High-water mark is set down from the top of the rx fifo (not 1470 * sensitive to max_frame_size) and low-water is set just below 1471 * high-water mark. 1472 * The high water mark must be low enough to fit one full frame above 1473 * it in the rx FIFO. Should be the lower of: 1474 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1475 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1476 * Rx FIFO size minus one full frame. 1477 */ 1478 high_water = min(((pba << 10) * 9 / 10), 1479 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1480 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1481 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1482 ((pba << 10) - Adapter->max_frame_size))); 1483 1484 hw->fc.high_water = high_water & 0xFFF8; 1485 hw->fc.low_water = hw->fc.high_water - 8; 1486 1487 if (hw->mac.type == e1000_80003es2lan) 1488 hw->fc.pause_time = 0xFFFF; 1489 else 1490 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1491 hw->fc.send_xon = B_TRUE; 1492 1493 /* 1494 * Reset the adapter hardware the second time. 1495 */ 1496 mutex_enter(&e1000g_nvm_lock); 1497 result = e1000_reset_hw(hw); 1498 mutex_exit(&e1000g_nvm_lock); 1499 1500 if (result != E1000_SUCCESS) { 1501 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1502 goto init_fail; 1503 } 1504 1505 /* disable wakeup control by default */ 1506 if (hw->mac.type >= e1000_82544) 1507 E1000_WRITE_REG(hw, E1000_WUC, 0); 1508 1509 /* 1510 * MWI should be disabled on 82546. 1511 */ 1512 if (hw->mac.type == e1000_82546) 1513 e1000_pci_clear_mwi(hw); 1514 else 1515 e1000_pci_set_mwi(hw); 1516 1517 /* 1518 * Configure/Initialize hardware 1519 */ 1520 mutex_enter(&e1000g_nvm_lock); 1521 result = e1000_init_hw(hw); 1522 mutex_exit(&e1000g_nvm_lock); 1523 1524 if (result < E1000_SUCCESS) { 1525 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1526 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1527 goto init_fail; 1528 } 1529 1530 /* 1531 * Restore LED settings to the default from EEPROM 1532 * to meet the standard for Sun platforms. 1533 */ 1534 (void) e1000_cleanup_led(hw); 1535 1536 /* Disable Smart Power Down */ 1537 phy_spd_state(hw, B_FALSE); 1538 1539 /* Make sure driver has control */ 1540 e1000g_get_driver_control(hw); 1541 1542 /* 1543 * Initialize unicast addresses. 1544 */ 1545 e1000g_init_unicst(Adapter); 1546 1547 /* 1548 * Setup and initialize the mctable structures. After this routine 1549 * completes Multicast table will be set 1550 */ 1551 e1000_update_mc_addr_list(hw, 1552 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1553 msec_delay(5); 1554 1555 /* 1556 * Implement Adaptive IFS 1557 */ 1558 e1000_reset_adaptive(hw); 1559 1560 /* Setup Interrupt Throttling Register */ 1561 if (hw->mac.type >= e1000_82540) { 1562 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1563 } else 1564 Adapter->intr_adaptive = B_FALSE; 1565 1566 /* Start the timer for link setup */ 1567 if (hw->mac.autoneg) 1568 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1569 else 1570 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1571 1572 mutex_enter(&Adapter->link_lock); 1573 if (hw->phy.autoneg_wait_to_complete) { 1574 Adapter->link_complete = B_TRUE; 1575 } else { 1576 Adapter->link_complete = B_FALSE; 1577 Adapter->link_tid = timeout(e1000g_link_timer, 1578 (void *)Adapter, link_timeout); 1579 } 1580 mutex_exit(&Adapter->link_lock); 1581 1582 /* Save the state of the phy */ 1583 e1000g_get_phy_state(Adapter); 1584 1585 e1000g_param_sync(Adapter); 1586 1587 Adapter->init_count++; 1588 1589 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1590 goto init_fail; 1591 } 1592 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1593 goto init_fail; 1594 } 1595 1596 Adapter->poll_mode = e1000g_poll_mode; 1597 1598 return (DDI_SUCCESS); 1599 1600 init_fail: 1601 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1602 return (DDI_FAILURE); 1603 } 1604 1605 static int 1606 e1000g_alloc_rx_data(struct e1000g *Adapter) 1607 { 1608 e1000g_rx_ring_t *rx_ring; 1609 e1000g_rx_data_t *rx_data; 1610 1611 rx_ring = Adapter->rx_ring; 1612 1613 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1614 1615 if (rx_data == NULL) 1616 return (DDI_FAILURE); 1617 1618 rx_data->priv_devi_node = Adapter->priv_devi_node; 1619 rx_data->rx_ring = rx_ring; 1620 1621 mutex_init(&rx_data->freelist_lock, NULL, 1622 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1623 mutex_init(&rx_data->recycle_lock, NULL, 1624 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1625 1626 rx_ring->rx_data = rx_data; 1627 1628 return (DDI_SUCCESS); 1629 } 1630 1631 void 1632 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1633 { 1634 rx_sw_packet_t *packet, *next_packet; 1635 1636 if (rx_data == NULL) 1637 return; 1638 1639 packet = rx_data->packet_area; 1640 while (packet != NULL) { 1641 next_packet = packet->next; 1642 e1000g_free_rx_sw_packet(packet, B_TRUE); 1643 packet = next_packet; 1644 } 1645 rx_data->packet_area = NULL; 1646 } 1647 1648 void 1649 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1650 { 1651 if (rx_data == NULL) 1652 return; 1653 1654 mutex_destroy(&rx_data->freelist_lock); 1655 mutex_destroy(&rx_data->recycle_lock); 1656 1657 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1658 } 1659 1660 /* 1661 * Check if the link is up 1662 */ 1663 static boolean_t 1664 e1000g_link_up(struct e1000g *Adapter) 1665 { 1666 struct e1000_hw *hw = &Adapter->shared; 1667 boolean_t link_up = B_FALSE; 1668 1669 /* 1670 * get_link_status is set in the interrupt handler on link-status-change 1671 * or rx sequence error interrupt. get_link_status will stay 1672 * false until the e1000_check_for_link establishes link only 1673 * for copper adapters. 1674 */ 1675 switch (hw->phy.media_type) { 1676 case e1000_media_type_copper: 1677 if (hw->mac.get_link_status) { 1678 (void) e1000_check_for_link(hw); 1679 if ((E1000_READ_REG(hw, E1000_STATUS) & 1680 E1000_STATUS_LU)) { 1681 link_up = B_TRUE; 1682 } else { 1683 link_up = !hw->mac.get_link_status; 1684 } 1685 } else { 1686 link_up = B_TRUE; 1687 } 1688 break; 1689 case e1000_media_type_fiber: 1690 (void) e1000_check_for_link(hw); 1691 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1692 E1000_STATUS_LU); 1693 break; 1694 case e1000_media_type_internal_serdes: 1695 (void) e1000_check_for_link(hw); 1696 link_up = hw->mac.serdes_has_link; 1697 break; 1698 } 1699 1700 return (link_up); 1701 } 1702 1703 static void 1704 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1705 { 1706 struct iocblk *iocp; 1707 struct e1000g *e1000gp; 1708 enum ioc_reply status; 1709 1710 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1711 iocp->ioc_error = 0; 1712 e1000gp = (struct e1000g *)arg; 1713 1714 ASSERT(e1000gp); 1715 if (e1000gp == NULL) { 1716 miocnak(q, mp, 0, EINVAL); 1717 return; 1718 } 1719 1720 rw_enter(&e1000gp->chip_lock, RW_READER); 1721 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1722 rw_exit(&e1000gp->chip_lock); 1723 miocnak(q, mp, 0, EINVAL); 1724 return; 1725 } 1726 rw_exit(&e1000gp->chip_lock); 1727 1728 switch (iocp->ioc_cmd) { 1729 1730 case LB_GET_INFO_SIZE: 1731 case LB_GET_INFO: 1732 case LB_GET_MODE: 1733 case LB_SET_MODE: 1734 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1735 break; 1736 1737 1738 #ifdef E1000G_DEBUG 1739 case E1000G_IOC_REG_PEEK: 1740 case E1000G_IOC_REG_POKE: 1741 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1742 break; 1743 case E1000G_IOC_CHIP_RESET: 1744 e1000gp->reset_count++; 1745 if (e1000g_reset_adapter(e1000gp)) 1746 status = IOC_ACK; 1747 else 1748 status = IOC_INVAL; 1749 break; 1750 #endif 1751 default: 1752 status = IOC_INVAL; 1753 break; 1754 } 1755 1756 /* 1757 * Decide how to reply 1758 */ 1759 switch (status) { 1760 default: 1761 case IOC_INVAL: 1762 /* 1763 * Error, reply with a NAK and EINVAL or the specified error 1764 */ 1765 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1766 EINVAL : iocp->ioc_error); 1767 break; 1768 1769 case IOC_DONE: 1770 /* 1771 * OK, reply already sent 1772 */ 1773 break; 1774 1775 case IOC_ACK: 1776 /* 1777 * OK, reply with an ACK 1778 */ 1779 miocack(q, mp, 0, 0); 1780 break; 1781 1782 case IOC_REPLY: 1783 /* 1784 * OK, send prepared reply as ACK or NAK 1785 */ 1786 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1787 M_IOCACK : M_IOCNAK; 1788 qreply(q, mp); 1789 break; 1790 } 1791 } 1792 1793 /* 1794 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1795 * capable of supporting only one interrupt and we shouldn't disable 1796 * the physical interrupt. In this case we let the interrupt come and 1797 * we queue the packets in the rx ring itself in case we are in polling 1798 * mode (better latency but slightly lower performance and a very 1799 * high intrrupt count in mpstat which is harmless). 1800 * 1801 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1802 * which can be disabled in poll mode. This gives better overall 1803 * throughput (compared to the mode above), shows very low interrupt 1804 * count but has slightly higher latency since we pick the packets when 1805 * the poll thread does polling. 1806 * 1807 * Currently, this flag should be enabled only while doing performance 1808 * measurement or when it can be guaranteed that entire NIC going 1809 * in poll mode will not harm any traffic like cluster heartbeat etc. 1810 */ 1811 int e1000g_poll_mode = 0; 1812 1813 /* 1814 * Called from the upper layers when driver is in polling mode to 1815 * pick up any queued packets. Care should be taken to not block 1816 * this thread. 1817 */ 1818 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1819 { 1820 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1821 mblk_t *mp = NULL; 1822 mblk_t *tail; 1823 struct e1000g *adapter; 1824 1825 adapter = rx_ring->adapter; 1826 1827 rw_enter(&adapter->chip_lock, RW_READER); 1828 1829 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1830 rw_exit(&adapter->chip_lock); 1831 return (NULL); 1832 } 1833 1834 mutex_enter(&rx_ring->rx_lock); 1835 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1836 mutex_exit(&rx_ring->rx_lock); 1837 rw_exit(&adapter->chip_lock); 1838 return (mp); 1839 } 1840 1841 static int 1842 e1000g_m_start(void *arg) 1843 { 1844 struct e1000g *Adapter = (struct e1000g *)arg; 1845 1846 rw_enter(&Adapter->chip_lock, RW_WRITER); 1847 1848 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1849 rw_exit(&Adapter->chip_lock); 1850 return (ECANCELED); 1851 } 1852 1853 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1854 rw_exit(&Adapter->chip_lock); 1855 return (ENOTACTIVE); 1856 } 1857 1858 Adapter->e1000g_state |= E1000G_STARTED; 1859 1860 rw_exit(&Adapter->chip_lock); 1861 1862 /* Enable and start the watchdog timer */ 1863 enable_watchdog_timer(Adapter); 1864 1865 return (0); 1866 } 1867 1868 static int 1869 e1000g_start(struct e1000g *Adapter, boolean_t global) 1870 { 1871 e1000g_rx_data_t *rx_data; 1872 1873 if (global) { 1874 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1875 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1876 goto start_fail; 1877 } 1878 1879 /* Allocate dma resources for descriptors and buffers */ 1880 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1881 e1000g_log(Adapter, CE_WARN, 1882 "Alloc DMA resources failed"); 1883 goto start_fail; 1884 } 1885 Adapter->rx_buffer_setup = B_FALSE; 1886 } 1887 1888 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1889 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1890 e1000g_log(Adapter, CE_WARN, 1891 "Adapter initialization failed"); 1892 goto start_fail; 1893 } 1894 } 1895 1896 /* Setup and initialize the transmit structures */ 1897 e1000g_tx_setup(Adapter); 1898 msec_delay(5); 1899 1900 /* Setup and initialize the receive structures */ 1901 e1000g_rx_setup(Adapter); 1902 msec_delay(5); 1903 1904 /* Restore the e1000g promiscuous mode */ 1905 e1000g_restore_promisc(Adapter); 1906 1907 e1000g_mask_interrupt(Adapter); 1908 1909 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1910 1911 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1912 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1913 goto start_fail; 1914 } 1915 1916 return (DDI_SUCCESS); 1917 1918 start_fail: 1919 rx_data = Adapter->rx_ring->rx_data; 1920 1921 if (global) { 1922 e1000g_release_dma_resources(Adapter); 1923 e1000g_free_rx_pending_buffers(rx_data); 1924 e1000g_free_rx_data(rx_data); 1925 } 1926 1927 mutex_enter(&e1000g_nvm_lock); 1928 (void) e1000_reset_hw(&Adapter->shared); 1929 mutex_exit(&e1000g_nvm_lock); 1930 1931 return (DDI_FAILURE); 1932 } 1933 1934 static void 1935 e1000g_m_stop(void *arg) 1936 { 1937 struct e1000g *Adapter = (struct e1000g *)arg; 1938 1939 /* Drain tx sessions */ 1940 (void) e1000g_tx_drain(Adapter); 1941 1942 rw_enter(&Adapter->chip_lock, RW_WRITER); 1943 1944 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1945 rw_exit(&Adapter->chip_lock); 1946 return; 1947 } 1948 Adapter->e1000g_state &= ~E1000G_STARTED; 1949 e1000g_stop(Adapter, B_TRUE); 1950 1951 rw_exit(&Adapter->chip_lock); 1952 1953 /* Disable and stop all the timers */ 1954 disable_watchdog_timer(Adapter); 1955 stop_link_timer(Adapter); 1956 stop_82547_timer(Adapter->tx_ring); 1957 } 1958 1959 static void 1960 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1961 { 1962 private_devi_list_t *devi_node; 1963 e1000g_rx_data_t *rx_data; 1964 int result; 1965 1966 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1967 1968 /* Stop the chip and release pending resources */ 1969 1970 /* Tell firmware driver is no longer in control */ 1971 e1000g_release_driver_control(&Adapter->shared); 1972 1973 e1000g_clear_all_interrupts(Adapter); 1974 1975 mutex_enter(&e1000g_nvm_lock); 1976 result = e1000_reset_hw(&Adapter->shared); 1977 mutex_exit(&e1000g_nvm_lock); 1978 1979 if (result != E1000_SUCCESS) { 1980 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1981 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1982 } 1983 1984 mutex_enter(&Adapter->link_lock); 1985 Adapter->link_complete = B_FALSE; 1986 mutex_exit(&Adapter->link_lock); 1987 1988 /* Release resources still held by the TX descriptors */ 1989 e1000g_tx_clean(Adapter); 1990 1991 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1992 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1993 1994 /* Clean the pending rx jumbo packet fragment */ 1995 e1000g_rx_clean(Adapter); 1996 1997 if (global) { 1998 e1000g_release_dma_resources(Adapter); 1999 2000 mutex_enter(&e1000g_rx_detach_lock); 2001 rx_data = Adapter->rx_ring->rx_data; 2002 rx_data->flag |= E1000G_RX_STOPPED; 2003 2004 if (rx_data->pending_count == 0) { 2005 e1000g_free_rx_pending_buffers(rx_data); 2006 e1000g_free_rx_data(rx_data); 2007 } else { 2008 devi_node = rx_data->priv_devi_node; 2009 if (devi_node != NULL) 2010 atomic_inc_32(&devi_node->pending_rx_count); 2011 else 2012 atomic_inc_32(&Adapter->pending_rx_count); 2013 } 2014 mutex_exit(&e1000g_rx_detach_lock); 2015 } 2016 2017 if (Adapter->link_state != LINK_STATE_UNKNOWN) { 2018 Adapter->link_state = LINK_STATE_UNKNOWN; 2019 if (!Adapter->reset_flag) 2020 mac_link_update(Adapter->mh, Adapter->link_state); 2021 } 2022 } 2023 2024 static void 2025 e1000g_rx_clean(struct e1000g *Adapter) 2026 { 2027 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 2028 2029 if (rx_data == NULL) 2030 return; 2031 2032 if (rx_data->rx_mblk != NULL) { 2033 freemsg(rx_data->rx_mblk); 2034 rx_data->rx_mblk = NULL; 2035 rx_data->rx_mblk_tail = NULL; 2036 rx_data->rx_mblk_len = 0; 2037 } 2038 } 2039 2040 static void 2041 e1000g_tx_clean(struct e1000g *Adapter) 2042 { 2043 e1000g_tx_ring_t *tx_ring; 2044 p_tx_sw_packet_t packet; 2045 mblk_t *mp; 2046 mblk_t *nmp; 2047 uint32_t packet_count; 2048 2049 tx_ring = Adapter->tx_ring; 2050 2051 /* 2052 * Here we don't need to protect the lists using 2053 * the usedlist_lock and freelist_lock, for they 2054 * have been protected by the chip_lock. 2055 */ 2056 mp = NULL; 2057 nmp = NULL; 2058 packet_count = 0; 2059 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 2060 while (packet != NULL) { 2061 if (packet->mp != NULL) { 2062 /* Assemble the message chain */ 2063 if (mp == NULL) { 2064 mp = packet->mp; 2065 nmp = packet->mp; 2066 } else { 2067 nmp->b_next = packet->mp; 2068 nmp = packet->mp; 2069 } 2070 /* Disconnect the message from the sw packet */ 2071 packet->mp = NULL; 2072 } 2073 2074 e1000g_free_tx_swpkt(packet); 2075 packet_count++; 2076 2077 packet = (p_tx_sw_packet_t) 2078 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 2079 } 2080 2081 if (mp != NULL) 2082 freemsgchain(mp); 2083 2084 if (packet_count > 0) { 2085 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 2086 QUEUE_INIT_LIST(&tx_ring->used_list); 2087 2088 /* Setup TX descriptor pointers */ 2089 tx_ring->tbd_next = tx_ring->tbd_first; 2090 tx_ring->tbd_oldest = tx_ring->tbd_first; 2091 2092 /* Setup our HW Tx Head & Tail descriptor pointers */ 2093 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 2094 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 2095 } 2096 } 2097 2098 static boolean_t 2099 e1000g_tx_drain(struct e1000g *Adapter) 2100 { 2101 int i; 2102 boolean_t done; 2103 e1000g_tx_ring_t *tx_ring; 2104 2105 tx_ring = Adapter->tx_ring; 2106 2107 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 2108 for (i = 0; i < TX_DRAIN_TIME; i++) { 2109 mutex_enter(&tx_ring->usedlist_lock); 2110 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 2111 mutex_exit(&tx_ring->usedlist_lock); 2112 2113 if (done) 2114 break; 2115 2116 msec_delay(1); 2117 } 2118 2119 return (done); 2120 } 2121 2122 static boolean_t 2123 e1000g_rx_drain(struct e1000g *Adapter) 2124 { 2125 int i; 2126 boolean_t done; 2127 2128 /* 2129 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2130 */ 2131 for (i = 0; i < RX_DRAIN_TIME; i++) { 2132 done = (Adapter->pending_rx_count == 0); 2133 2134 if (done) 2135 break; 2136 2137 msec_delay(1); 2138 } 2139 2140 return (done); 2141 } 2142 2143 static boolean_t 2144 e1000g_reset_adapter(struct e1000g *Adapter) 2145 { 2146 /* Disable and stop all the timers */ 2147 disable_watchdog_timer(Adapter); 2148 stop_link_timer(Adapter); 2149 stop_82547_timer(Adapter->tx_ring); 2150 2151 rw_enter(&Adapter->chip_lock, RW_WRITER); 2152 2153 if (Adapter->stall_flag) { 2154 Adapter->stall_flag = B_FALSE; 2155 Adapter->reset_flag = B_TRUE; 2156 } 2157 2158 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2159 rw_exit(&Adapter->chip_lock); 2160 return (B_TRUE); 2161 } 2162 2163 e1000g_stop(Adapter, B_FALSE); 2164 2165 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2166 rw_exit(&Adapter->chip_lock); 2167 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2168 return (B_FALSE); 2169 } 2170 2171 rw_exit(&Adapter->chip_lock); 2172 2173 /* Enable and start the watchdog timer */ 2174 enable_watchdog_timer(Adapter); 2175 2176 return (B_TRUE); 2177 } 2178 2179 boolean_t 2180 e1000g_global_reset(struct e1000g *Adapter) 2181 { 2182 /* Disable and stop all the timers */ 2183 disable_watchdog_timer(Adapter); 2184 stop_link_timer(Adapter); 2185 stop_82547_timer(Adapter->tx_ring); 2186 2187 rw_enter(&Adapter->chip_lock, RW_WRITER); 2188 2189 e1000g_stop(Adapter, B_TRUE); 2190 2191 Adapter->init_count = 0; 2192 2193 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2194 rw_exit(&Adapter->chip_lock); 2195 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2196 return (B_FALSE); 2197 } 2198 2199 rw_exit(&Adapter->chip_lock); 2200 2201 /* Enable and start the watchdog timer */ 2202 enable_watchdog_timer(Adapter); 2203 2204 return (B_TRUE); 2205 } 2206 2207 /* 2208 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2209 * 2210 * This interrupt service routine is for PCI-Express adapters. 2211 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2212 * bit is set. 2213 */ 2214 static uint_t 2215 e1000g_intr_pciexpress(caddr_t arg) 2216 { 2217 struct e1000g *Adapter; 2218 uint32_t icr; 2219 2220 Adapter = (struct e1000g *)(uintptr_t)arg; 2221 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2222 2223 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2224 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2225 return (DDI_INTR_CLAIMED); 2226 } 2227 2228 if (icr & E1000_ICR_INT_ASSERTED) { 2229 /* 2230 * E1000_ICR_INT_ASSERTED bit was set: 2231 * Read(Clear) the ICR, claim this interrupt, 2232 * look for work to do. 2233 */ 2234 e1000g_intr_work(Adapter, icr); 2235 return (DDI_INTR_CLAIMED); 2236 } else { 2237 /* 2238 * E1000_ICR_INT_ASSERTED bit was not set: 2239 * Don't claim this interrupt, return immediately. 2240 */ 2241 return (DDI_INTR_UNCLAIMED); 2242 } 2243 } 2244 2245 /* 2246 * e1000g_intr - ISR for PCI/PCI-X chipsets 2247 * 2248 * This interrupt service routine is for PCI/PCI-X adapters. 2249 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2250 * bit is set or not. 2251 */ 2252 static uint_t 2253 e1000g_intr(caddr_t arg) 2254 { 2255 struct e1000g *Adapter; 2256 uint32_t icr; 2257 2258 Adapter = (struct e1000g *)(uintptr_t)arg; 2259 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2260 2261 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2262 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2263 return (DDI_INTR_CLAIMED); 2264 } 2265 2266 if (icr) { 2267 /* 2268 * Any bit was set in ICR: 2269 * Read(Clear) the ICR, claim this interrupt, 2270 * look for work to do. 2271 */ 2272 e1000g_intr_work(Adapter, icr); 2273 return (DDI_INTR_CLAIMED); 2274 } else { 2275 /* 2276 * No bit was set in ICR: 2277 * Don't claim this interrupt, return immediately. 2278 */ 2279 return (DDI_INTR_UNCLAIMED); 2280 } 2281 } 2282 2283 /* 2284 * e1000g_intr_work - actual processing of ISR 2285 * 2286 * Read(clear) the ICR contents and call appropriate interrupt 2287 * processing routines. 2288 */ 2289 static void 2290 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2291 { 2292 struct e1000_hw *hw; 2293 hw = &Adapter->shared; 2294 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2295 2296 Adapter->rx_pkt_cnt = 0; 2297 Adapter->tx_pkt_cnt = 0; 2298 2299 rw_enter(&Adapter->chip_lock, RW_READER); 2300 2301 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2302 rw_exit(&Adapter->chip_lock); 2303 return; 2304 } 2305 /* 2306 * Here we need to check the "e1000g_state" flag within the chip_lock to 2307 * ensure the receive routine will not execute when the adapter is 2308 * being reset. 2309 */ 2310 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2311 rw_exit(&Adapter->chip_lock); 2312 return; 2313 } 2314 2315 if (icr & E1000_ICR_RXT0) { 2316 mblk_t *mp = NULL; 2317 mblk_t *tail = NULL; 2318 e1000g_rx_ring_t *rx_ring; 2319 2320 rx_ring = Adapter->rx_ring; 2321 mutex_enter(&rx_ring->rx_lock); 2322 /* 2323 * Sometimes with legacy interrupts, it possible that 2324 * there is a single interrupt for Rx/Tx. In which 2325 * case, if poll flag is set, we shouldn't really 2326 * be doing Rx processing. 2327 */ 2328 if (!rx_ring->poll_flag) 2329 mp = e1000g_receive(rx_ring, &tail, 2330 E1000G_CHAIN_NO_LIMIT); 2331 mutex_exit(&rx_ring->rx_lock); 2332 rw_exit(&Adapter->chip_lock); 2333 if (mp != NULL) 2334 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2335 mp, rx_ring->ring_gen_num); 2336 } else 2337 rw_exit(&Adapter->chip_lock); 2338 2339 if (icr & E1000_ICR_TXDW) { 2340 if (!Adapter->tx_intr_enable) 2341 e1000g_clear_tx_interrupt(Adapter); 2342 2343 /* Recycle the tx descriptors */ 2344 rw_enter(&Adapter->chip_lock, RW_READER); 2345 (void) e1000g_recycle(tx_ring); 2346 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2347 rw_exit(&Adapter->chip_lock); 2348 2349 if (tx_ring->resched_needed && 2350 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2351 tx_ring->resched_needed = B_FALSE; 2352 mac_tx_update(Adapter->mh); 2353 E1000G_STAT(tx_ring->stat_reschedule); 2354 } 2355 } 2356 2357 /* 2358 * The Receive Sequence errors RXSEQ and the link status change LSC 2359 * are checked to detect that the cable has been pulled out. For 2360 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2361 * are an indication that cable is not connected. 2362 */ 2363 if ((icr & E1000_ICR_RXSEQ) || 2364 (icr & E1000_ICR_LSC) || 2365 (icr & E1000_ICR_GPI_EN1)) { 2366 boolean_t link_changed; 2367 timeout_id_t tid = 0; 2368 2369 stop_watchdog_timer(Adapter); 2370 2371 rw_enter(&Adapter->chip_lock, RW_WRITER); 2372 2373 /* 2374 * Because we got a link-status-change interrupt, force 2375 * e1000_check_for_link() to look at phy 2376 */ 2377 Adapter->shared.mac.get_link_status = B_TRUE; 2378 2379 /* e1000g_link_check takes care of link status change */ 2380 link_changed = e1000g_link_check(Adapter); 2381 2382 /* Get new phy state */ 2383 e1000g_get_phy_state(Adapter); 2384 2385 /* 2386 * If the link timer has not timed out, we'll not notify 2387 * the upper layer with any link state until the link is up. 2388 */ 2389 if (link_changed && !Adapter->link_complete) { 2390 if (Adapter->link_state == LINK_STATE_UP) { 2391 mutex_enter(&Adapter->link_lock); 2392 Adapter->link_complete = B_TRUE; 2393 tid = Adapter->link_tid; 2394 Adapter->link_tid = 0; 2395 mutex_exit(&Adapter->link_lock); 2396 } else { 2397 link_changed = B_FALSE; 2398 } 2399 } 2400 rw_exit(&Adapter->chip_lock); 2401 2402 if (link_changed) { 2403 if (tid != 0) 2404 (void) untimeout(tid); 2405 2406 /* 2407 * Workaround for esb2. Data stuck in fifo on a link 2408 * down event. Stop receiver here and reset in watchdog. 2409 */ 2410 if ((Adapter->link_state == LINK_STATE_DOWN) && 2411 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2412 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2413 E1000_WRITE_REG(hw, E1000_RCTL, 2414 rctl & ~E1000_RCTL_EN); 2415 e1000g_log(Adapter, CE_WARN, 2416 "ESB2 receiver disabled"); 2417 Adapter->esb2_workaround = B_TRUE; 2418 } 2419 if (!Adapter->reset_flag) 2420 mac_link_update(Adapter->mh, 2421 Adapter->link_state); 2422 if (Adapter->link_state == LINK_STATE_UP) 2423 Adapter->reset_flag = B_FALSE; 2424 } 2425 2426 start_watchdog_timer(Adapter); 2427 } 2428 } 2429 2430 static void 2431 e1000g_init_unicst(struct e1000g *Adapter) 2432 { 2433 struct e1000_hw *hw; 2434 int slot; 2435 2436 hw = &Adapter->shared; 2437 2438 if (Adapter->init_count == 0) { 2439 /* Initialize the multiple unicast addresses */ 2440 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2441 2442 /* Workaround for an erratum of 82571 chipst */ 2443 if ((hw->mac.type == e1000_82571) && 2444 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2445 Adapter->unicst_total--; 2446 2447 Adapter->unicst_avail = Adapter->unicst_total; 2448 2449 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2450 /* Clear both the flag and MAC address */ 2451 Adapter->unicst_addr[slot].reg.high = 0; 2452 Adapter->unicst_addr[slot].reg.low = 0; 2453 } 2454 } else { 2455 /* Workaround for an erratum of 82571 chipst */ 2456 if ((hw->mac.type == e1000_82571) && 2457 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2458 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2459 2460 /* Re-configure the RAR registers */ 2461 for (slot = 0; slot < Adapter->unicst_total; slot++) 2462 if (Adapter->unicst_addr[slot].mac.set == 1) 2463 e1000_rar_set(hw, 2464 Adapter->unicst_addr[slot].mac.addr, slot); 2465 } 2466 2467 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2468 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2469 } 2470 2471 static int 2472 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2473 int slot) 2474 { 2475 struct e1000_hw *hw; 2476 2477 hw = &Adapter->shared; 2478 2479 /* 2480 * The first revision of Wiseman silicon (rev 2.0) has an errata 2481 * that requires the receiver to be in reset when any of the 2482 * receive address registers (RAR regs) are accessed. The first 2483 * rev of Wiseman silicon also requires MWI to be disabled when 2484 * a global reset or a receive reset is issued. So before we 2485 * initialize the RARs, we check the rev of the Wiseman controller 2486 * and work around any necessary HW errata. 2487 */ 2488 if ((hw->mac.type == e1000_82542) && 2489 (hw->revision_id == E1000_REVISION_2)) { 2490 e1000_pci_clear_mwi(hw); 2491 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2492 msec_delay(5); 2493 } 2494 if (mac_addr == NULL) { 2495 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2496 E1000_WRITE_FLUSH(hw); 2497 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2498 E1000_WRITE_FLUSH(hw); 2499 /* Clear both the flag and MAC address */ 2500 Adapter->unicst_addr[slot].reg.high = 0; 2501 Adapter->unicst_addr[slot].reg.low = 0; 2502 } else { 2503 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2504 ETHERADDRL); 2505 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2506 Adapter->unicst_addr[slot].mac.set = 1; 2507 } 2508 2509 /* Workaround for an erratum of 82571 chipst */ 2510 if (slot == 0) { 2511 if ((hw->mac.type == e1000_82571) && 2512 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2513 if (mac_addr == NULL) { 2514 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2515 slot << 1, 0); 2516 E1000_WRITE_FLUSH(hw); 2517 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2518 (slot << 1) + 1, 0); 2519 E1000_WRITE_FLUSH(hw); 2520 } else { 2521 e1000_rar_set(hw, (uint8_t *)mac_addr, 2522 LAST_RAR_ENTRY); 2523 } 2524 } 2525 2526 /* 2527 * If we are using Wiseman rev 2.0 silicon, we will have previously 2528 * put the receive in reset, and disabled MWI, to work around some 2529 * HW errata. Now we should take the receiver out of reset, and 2530 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2531 */ 2532 if ((hw->mac.type == e1000_82542) && 2533 (hw->revision_id == E1000_REVISION_2)) { 2534 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2535 msec_delay(1); 2536 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2537 e1000_pci_set_mwi(hw); 2538 e1000g_rx_setup(Adapter); 2539 } 2540 2541 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2542 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2543 return (EIO); 2544 } 2545 2546 return (0); 2547 } 2548 2549 static int 2550 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2551 { 2552 struct e1000_hw *hw = &Adapter->shared; 2553 struct ether_addr *newtable; 2554 size_t new_len; 2555 size_t old_len; 2556 int res = 0; 2557 2558 if ((multiaddr[0] & 01) == 0) { 2559 res = EINVAL; 2560 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2561 goto done; 2562 } 2563 2564 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2565 res = ENOENT; 2566 e1000g_log(Adapter, CE_WARN, 2567 "Adapter requested more than %d mcast addresses", 2568 Adapter->mcast_max_num); 2569 goto done; 2570 } 2571 2572 2573 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2574 old_len = Adapter->mcast_alloc_count * 2575 sizeof (struct ether_addr); 2576 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2577 sizeof (struct ether_addr); 2578 2579 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2580 if (newtable == NULL) { 2581 res = ENOMEM; 2582 e1000g_log(Adapter, CE_WARN, 2583 "Not enough memory to alloc mcast table"); 2584 goto done; 2585 } 2586 2587 if (Adapter->mcast_table != NULL) { 2588 bcopy(Adapter->mcast_table, newtable, old_len); 2589 kmem_free(Adapter->mcast_table, old_len); 2590 } 2591 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2592 Adapter->mcast_table = newtable; 2593 } 2594 2595 bcopy(multiaddr, 2596 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2597 Adapter->mcast_count++; 2598 2599 /* 2600 * Update the MC table in the hardware 2601 */ 2602 e1000g_clear_interrupt(Adapter); 2603 2604 e1000_update_mc_addr_list(hw, 2605 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2606 2607 e1000g_mask_interrupt(Adapter); 2608 2609 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2610 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2611 res = EIO; 2612 } 2613 2614 done: 2615 return (res); 2616 } 2617 2618 static int 2619 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2620 { 2621 struct e1000_hw *hw = &Adapter->shared; 2622 struct ether_addr *newtable; 2623 size_t new_len; 2624 size_t old_len; 2625 unsigned i; 2626 2627 for (i = 0; i < Adapter->mcast_count; i++) { 2628 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2629 ETHERADDRL) == 0) { 2630 for (i++; i < Adapter->mcast_count; i++) { 2631 Adapter->mcast_table[i - 1] = 2632 Adapter->mcast_table[i]; 2633 } 2634 Adapter->mcast_count--; 2635 break; 2636 } 2637 } 2638 2639 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2640 MCAST_ALLOC_SIZE) { 2641 old_len = Adapter->mcast_alloc_count * 2642 sizeof (struct ether_addr); 2643 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2644 sizeof (struct ether_addr); 2645 2646 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2647 if (newtable != NULL) { 2648 bcopy(Adapter->mcast_table, newtable, new_len); 2649 kmem_free(Adapter->mcast_table, old_len); 2650 2651 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2652 Adapter->mcast_table = newtable; 2653 } 2654 } 2655 2656 /* 2657 * Update the MC table in the hardware 2658 */ 2659 e1000g_clear_interrupt(Adapter); 2660 2661 e1000_update_mc_addr_list(hw, 2662 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2663 2664 e1000g_mask_interrupt(Adapter); 2665 2666 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2667 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2668 return (EIO); 2669 } 2670 2671 return (0); 2672 } 2673 2674 static void 2675 e1000g_release_multicast(struct e1000g *Adapter) 2676 { 2677 if (Adapter->mcast_table != NULL) { 2678 kmem_free(Adapter->mcast_table, 2679 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2680 Adapter->mcast_table = NULL; 2681 } 2682 } 2683 2684 int 2685 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2686 { 2687 struct e1000g *Adapter = (struct e1000g *)arg; 2688 int result; 2689 2690 rw_enter(&Adapter->chip_lock, RW_WRITER); 2691 2692 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2693 result = ECANCELED; 2694 goto done; 2695 } 2696 2697 result = (add) ? multicst_add(Adapter, addr) 2698 : multicst_remove(Adapter, addr); 2699 2700 done: 2701 rw_exit(&Adapter->chip_lock); 2702 return (result); 2703 2704 } 2705 2706 int 2707 e1000g_m_promisc(void *arg, boolean_t on) 2708 { 2709 struct e1000g *Adapter = (struct e1000g *)arg; 2710 uint32_t rctl; 2711 2712 rw_enter(&Adapter->chip_lock, RW_WRITER); 2713 2714 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2715 rw_exit(&Adapter->chip_lock); 2716 return (ECANCELED); 2717 } 2718 2719 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2720 2721 if (on) 2722 rctl |= 2723 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2724 else 2725 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2726 2727 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2728 2729 Adapter->e1000g_promisc = on; 2730 2731 rw_exit(&Adapter->chip_lock); 2732 2733 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2734 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2735 return (EIO); 2736 } 2737 2738 return (0); 2739 } 2740 2741 /* 2742 * Entry points to enable and disable interrupts at the granularity of 2743 * a group. 2744 * Turns the poll_mode for the whole adapter on and off to enable or 2745 * override the ring level polling control over the hardware interrupts. 2746 */ 2747 static int 2748 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2749 { 2750 struct e1000g *adapter = (struct e1000g *)arg; 2751 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2752 2753 /* 2754 * Later interrupts at the granularity of the this ring will 2755 * invoke mac_rx() with NULL, indicating the need for another 2756 * software classification. 2757 * We have a single ring usable per adapter now, so we only need to 2758 * reset the rx handle for that one. 2759 * When more RX rings can be used, we should update each one of them. 2760 */ 2761 mutex_enter(&rx_ring->rx_lock); 2762 rx_ring->mrh = NULL; 2763 adapter->poll_mode = B_FALSE; 2764 mutex_exit(&rx_ring->rx_lock); 2765 return (0); 2766 } 2767 2768 static int 2769 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2770 { 2771 struct e1000g *adapter = (struct e1000g *)arg; 2772 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2773 2774 mutex_enter(&rx_ring->rx_lock); 2775 2776 /* 2777 * Later interrupts at the granularity of the this ring will 2778 * invoke mac_rx() with the handle for this ring; 2779 */ 2780 adapter->poll_mode = B_TRUE; 2781 rx_ring->mrh = rx_ring->mrh_init; 2782 mutex_exit(&rx_ring->rx_lock); 2783 return (0); 2784 } 2785 2786 /* 2787 * Entry points to enable and disable interrupts at the granularity of 2788 * a ring. 2789 * adapter poll_mode controls whether we actually proceed with hardware 2790 * interrupt toggling. 2791 */ 2792 static int 2793 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2794 { 2795 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2796 struct e1000g *adapter = rx_ring->adapter; 2797 struct e1000_hw *hw = &adapter->shared; 2798 uint32_t intr_mask; 2799 2800 rw_enter(&adapter->chip_lock, RW_READER); 2801 2802 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2803 rw_exit(&adapter->chip_lock); 2804 return (0); 2805 } 2806 2807 mutex_enter(&rx_ring->rx_lock); 2808 rx_ring->poll_flag = 0; 2809 mutex_exit(&rx_ring->rx_lock); 2810 2811 /* Rx interrupt enabling for MSI and legacy */ 2812 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2813 intr_mask |= E1000_IMS_RXT0; 2814 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2815 E1000_WRITE_FLUSH(hw); 2816 2817 /* Trigger a Rx interrupt to check Rx ring */ 2818 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2819 E1000_WRITE_FLUSH(hw); 2820 2821 rw_exit(&adapter->chip_lock); 2822 return (0); 2823 } 2824 2825 static int 2826 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2827 { 2828 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2829 struct e1000g *adapter = rx_ring->adapter; 2830 struct e1000_hw *hw = &adapter->shared; 2831 2832 rw_enter(&adapter->chip_lock, RW_READER); 2833 2834 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2835 rw_exit(&adapter->chip_lock); 2836 return (0); 2837 } 2838 mutex_enter(&rx_ring->rx_lock); 2839 rx_ring->poll_flag = 1; 2840 mutex_exit(&rx_ring->rx_lock); 2841 2842 /* Rx interrupt disabling for MSI and legacy */ 2843 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2844 E1000_WRITE_FLUSH(hw); 2845 2846 rw_exit(&adapter->chip_lock); 2847 return (0); 2848 } 2849 2850 /* 2851 * e1000g_unicst_find - Find the slot for the specified unicast address 2852 */ 2853 static int 2854 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2855 { 2856 int slot; 2857 2858 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2859 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2860 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2861 mac_addr, ETHERADDRL) == 0)) 2862 return (slot); 2863 } 2864 2865 return (-1); 2866 } 2867 2868 /* 2869 * Entry points to add and remove a MAC address to a ring group. 2870 * The caller takes care of adding and removing the MAC addresses 2871 * to the filter via these two routines. 2872 */ 2873 2874 static int 2875 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2876 { 2877 struct e1000g *Adapter = (struct e1000g *)arg; 2878 int slot, err; 2879 2880 rw_enter(&Adapter->chip_lock, RW_WRITER); 2881 2882 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2883 rw_exit(&Adapter->chip_lock); 2884 return (ECANCELED); 2885 } 2886 2887 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2888 /* The same address is already in slot */ 2889 rw_exit(&Adapter->chip_lock); 2890 return (0); 2891 } 2892 2893 if (Adapter->unicst_avail == 0) { 2894 /* no slots available */ 2895 rw_exit(&Adapter->chip_lock); 2896 return (ENOSPC); 2897 } 2898 2899 /* Search for a free slot */ 2900 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2901 if (Adapter->unicst_addr[slot].mac.set == 0) 2902 break; 2903 } 2904 ASSERT(slot < Adapter->unicst_total); 2905 2906 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2907 if (err == 0) 2908 Adapter->unicst_avail--; 2909 2910 rw_exit(&Adapter->chip_lock); 2911 2912 return (err); 2913 } 2914 2915 static int 2916 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2917 { 2918 struct e1000g *Adapter = (struct e1000g *)arg; 2919 int slot, err; 2920 2921 rw_enter(&Adapter->chip_lock, RW_WRITER); 2922 2923 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2924 rw_exit(&Adapter->chip_lock); 2925 return (ECANCELED); 2926 } 2927 2928 slot = e1000g_unicst_find(Adapter, mac_addr); 2929 if (slot == -1) { 2930 rw_exit(&Adapter->chip_lock); 2931 return (EINVAL); 2932 } 2933 2934 ASSERT(Adapter->unicst_addr[slot].mac.set); 2935 2936 /* Clear this slot */ 2937 err = e1000g_unicst_set(Adapter, NULL, slot); 2938 if (err == 0) 2939 Adapter->unicst_avail++; 2940 2941 rw_exit(&Adapter->chip_lock); 2942 2943 return (err); 2944 } 2945 2946 static int 2947 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2948 { 2949 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2950 2951 mutex_enter(&rx_ring->rx_lock); 2952 rx_ring->ring_gen_num = mr_gen_num; 2953 mutex_exit(&rx_ring->rx_lock); 2954 return (0); 2955 } 2956 2957 /* 2958 * Callback funtion for MAC layer to register all rings. 2959 * 2960 * The hardware supports a single group with currently only one ring 2961 * available. 2962 * Though not offering virtualization ability per se, exposing the 2963 * group/ring still enables the polling and interrupt toggling. 2964 */ 2965 /* ARGSUSED */ 2966 void 2967 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2968 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2969 { 2970 struct e1000g *Adapter = (struct e1000g *)arg; 2971 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2972 mac_intr_t *mintr; 2973 2974 /* 2975 * We advertised only RX group/rings, so the MAC framework shouldn't 2976 * ask for any thing else. 2977 */ 2978 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2979 2980 rx_ring->mrh = rx_ring->mrh_init = rh; 2981 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2982 infop->mri_start = e1000g_ring_start; 2983 infop->mri_stop = NULL; 2984 infop->mri_poll = e1000g_poll_ring; 2985 infop->mri_stat = e1000g_rx_ring_stat; 2986 2987 /* Ring level interrupts */ 2988 mintr = &infop->mri_intr; 2989 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2990 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2991 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2992 if (Adapter->msi_enable) 2993 mintr->mi_ddi_handle = Adapter->htable[0]; 2994 } 2995 2996 /* ARGSUSED */ 2997 static void 2998 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2999 mac_group_info_t *infop, mac_group_handle_t gh) 3000 { 3001 struct e1000g *Adapter = (struct e1000g *)arg; 3002 mac_intr_t *mintr; 3003 3004 /* 3005 * We advertised a single RX ring. Getting a request for anything else 3006 * signifies a bug in the MAC framework. 3007 */ 3008 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 3009 3010 Adapter->rx_group = gh; 3011 3012 infop->mgi_driver = (mac_group_driver_t)Adapter; 3013 infop->mgi_start = NULL; 3014 infop->mgi_stop = NULL; 3015 infop->mgi_addmac = e1000g_addmac; 3016 infop->mgi_remmac = e1000g_remmac; 3017 infop->mgi_count = 1; 3018 3019 /* Group level interrupts */ 3020 mintr = &infop->mgi_intr; 3021 mintr->mi_handle = (mac_intr_handle_t)Adapter; 3022 mintr->mi_enable = e1000g_rx_group_intr_enable; 3023 mintr->mi_disable = e1000g_rx_group_intr_disable; 3024 } 3025 3026 static boolean_t 3027 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 3028 { 3029 struct e1000g *Adapter = (struct e1000g *)arg; 3030 3031 switch (cap) { 3032 case MAC_CAPAB_HCKSUM: { 3033 uint32_t *txflags = cap_data; 3034 3035 if (Adapter->tx_hcksum_enable) 3036 *txflags = HCKSUM_IPHDRCKSUM | 3037 HCKSUM_INET_PARTIAL; 3038 else 3039 return (B_FALSE); 3040 break; 3041 } 3042 3043 case MAC_CAPAB_LSO: { 3044 mac_capab_lso_t *cap_lso = cap_data; 3045 3046 if (Adapter->lso_enable) { 3047 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 3048 cap_lso->lso_basic_tcp_ipv4.lso_max = 3049 E1000_LSO_MAXLEN; 3050 } else 3051 return (B_FALSE); 3052 break; 3053 } 3054 case MAC_CAPAB_RINGS: { 3055 mac_capab_rings_t *cap_rings = cap_data; 3056 3057 /* No TX rings exposed yet */ 3058 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 3059 return (B_FALSE); 3060 3061 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 3062 cap_rings->mr_rnum = 1; 3063 cap_rings->mr_gnum = 1; 3064 cap_rings->mr_rget = e1000g_fill_ring; 3065 cap_rings->mr_gget = e1000g_fill_group; 3066 break; 3067 } 3068 default: 3069 return (B_FALSE); 3070 } 3071 return (B_TRUE); 3072 } 3073 3074 static boolean_t 3075 e1000g_param_locked(mac_prop_id_t pr_num) 3076 { 3077 /* 3078 * All en_* parameters are locked (read-only) while 3079 * the device is in any sort of loopback mode ... 3080 */ 3081 switch (pr_num) { 3082 case MAC_PROP_EN_1000FDX_CAP: 3083 case MAC_PROP_EN_1000HDX_CAP: 3084 case MAC_PROP_EN_100FDX_CAP: 3085 case MAC_PROP_EN_100HDX_CAP: 3086 case MAC_PROP_EN_10FDX_CAP: 3087 case MAC_PROP_EN_10HDX_CAP: 3088 case MAC_PROP_AUTONEG: 3089 case MAC_PROP_FLOWCTRL: 3090 return (B_TRUE); 3091 } 3092 return (B_FALSE); 3093 } 3094 3095 /* 3096 * callback function for set/get of properties 3097 */ 3098 static int 3099 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3100 uint_t pr_valsize, const void *pr_val) 3101 { 3102 struct e1000g *Adapter = arg; 3103 struct e1000_hw *hw = &Adapter->shared; 3104 struct e1000_fc_info *fc = &Adapter->shared.fc; 3105 int err = 0; 3106 link_flowctrl_t flowctrl; 3107 uint32_t cur_mtu, new_mtu; 3108 3109 rw_enter(&Adapter->chip_lock, RW_WRITER); 3110 3111 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3112 rw_exit(&Adapter->chip_lock); 3113 return (ECANCELED); 3114 } 3115 3116 if (Adapter->loopback_mode != E1000G_LB_NONE && 3117 e1000g_param_locked(pr_num)) { 3118 /* 3119 * All en_* parameters are locked (read-only) 3120 * while the device is in any sort of loopback mode. 3121 */ 3122 rw_exit(&Adapter->chip_lock); 3123 return (EBUSY); 3124 } 3125 3126 switch (pr_num) { 3127 case MAC_PROP_EN_1000FDX_CAP: 3128 if (hw->phy.media_type != e1000_media_type_copper) { 3129 err = ENOTSUP; 3130 break; 3131 } 3132 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3133 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3134 goto reset; 3135 case MAC_PROP_EN_100FDX_CAP: 3136 if (hw->phy.media_type != e1000_media_type_copper) { 3137 err = ENOTSUP; 3138 break; 3139 } 3140 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3141 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3142 goto reset; 3143 case MAC_PROP_EN_100HDX_CAP: 3144 if (hw->phy.media_type != e1000_media_type_copper) { 3145 err = ENOTSUP; 3146 break; 3147 } 3148 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3149 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3150 goto reset; 3151 case MAC_PROP_EN_10FDX_CAP: 3152 if (hw->phy.media_type != e1000_media_type_copper) { 3153 err = ENOTSUP; 3154 break; 3155 } 3156 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3157 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3158 goto reset; 3159 case MAC_PROP_EN_10HDX_CAP: 3160 if (hw->phy.media_type != e1000_media_type_copper) { 3161 err = ENOTSUP; 3162 break; 3163 } 3164 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3165 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3166 goto reset; 3167 case MAC_PROP_AUTONEG: 3168 if (hw->phy.media_type != e1000_media_type_copper) { 3169 err = ENOTSUP; 3170 break; 3171 } 3172 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3173 goto reset; 3174 case MAC_PROP_FLOWCTRL: 3175 fc->send_xon = B_TRUE; 3176 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3177 3178 switch (flowctrl) { 3179 default: 3180 err = EINVAL; 3181 break; 3182 case LINK_FLOWCTRL_NONE: 3183 fc->requested_mode = e1000_fc_none; 3184 break; 3185 case LINK_FLOWCTRL_RX: 3186 fc->requested_mode = e1000_fc_rx_pause; 3187 break; 3188 case LINK_FLOWCTRL_TX: 3189 fc->requested_mode = e1000_fc_tx_pause; 3190 break; 3191 case LINK_FLOWCTRL_BI: 3192 fc->requested_mode = e1000_fc_full; 3193 break; 3194 } 3195 reset: 3196 if (err == 0) { 3197 /* check PCH limits & reset the link */ 3198 e1000g_pch_limits(Adapter); 3199 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3200 err = EINVAL; 3201 } 3202 break; 3203 case MAC_PROP_ADV_1000FDX_CAP: 3204 case MAC_PROP_ADV_1000HDX_CAP: 3205 case MAC_PROP_ADV_100FDX_CAP: 3206 case MAC_PROP_ADV_100HDX_CAP: 3207 case MAC_PROP_ADV_10FDX_CAP: 3208 case MAC_PROP_ADV_10HDX_CAP: 3209 case MAC_PROP_EN_1000HDX_CAP: 3210 case MAC_PROP_STATUS: 3211 case MAC_PROP_SPEED: 3212 case MAC_PROP_DUPLEX: 3213 err = ENOTSUP; /* read-only prop. Can't set this. */ 3214 break; 3215 case MAC_PROP_MTU: 3216 /* adapter must be stopped for an MTU change */ 3217 if (Adapter->e1000g_state & E1000G_STARTED) { 3218 err = EBUSY; 3219 break; 3220 } 3221 3222 cur_mtu = Adapter->default_mtu; 3223 3224 /* get new requested MTU */ 3225 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3226 if (new_mtu == cur_mtu) { 3227 err = 0; 3228 break; 3229 } 3230 3231 if ((new_mtu < DEFAULT_MTU) || 3232 (new_mtu > Adapter->max_mtu)) { 3233 err = EINVAL; 3234 break; 3235 } 3236 3237 /* inform MAC framework of new MTU */ 3238 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3239 3240 if (err == 0) { 3241 Adapter->default_mtu = new_mtu; 3242 Adapter->max_frame_size = 3243 e1000g_mtu2maxframe(new_mtu); 3244 3245 /* 3246 * check PCH limits & set buffer sizes to 3247 * match new MTU 3248 */ 3249 e1000g_pch_limits(Adapter); 3250 e1000g_set_bufsize(Adapter); 3251 3252 /* 3253 * decrease the number of descriptors and free 3254 * packets for jumbo frames to reduce tx/rx 3255 * resource consumption 3256 */ 3257 if (Adapter->max_frame_size >= 3258 (FRAME_SIZE_UPTO_4K)) { 3259 if (Adapter->tx_desc_num_flag == 0) 3260 Adapter->tx_desc_num = 3261 DEFAULT_JUMBO_NUM_TX_DESC; 3262 3263 if (Adapter->rx_desc_num_flag == 0) 3264 Adapter->rx_desc_num = 3265 DEFAULT_JUMBO_NUM_RX_DESC; 3266 3267 if (Adapter->tx_buf_num_flag == 0) 3268 Adapter->tx_freelist_num = 3269 DEFAULT_JUMBO_NUM_TX_BUF; 3270 3271 if (Adapter->rx_buf_num_flag == 0) 3272 Adapter->rx_freelist_limit = 3273 DEFAULT_JUMBO_NUM_RX_BUF; 3274 } else { 3275 if (Adapter->tx_desc_num_flag == 0) 3276 Adapter->tx_desc_num = 3277 DEFAULT_NUM_TX_DESCRIPTOR; 3278 3279 if (Adapter->rx_desc_num_flag == 0) 3280 Adapter->rx_desc_num = 3281 DEFAULT_NUM_RX_DESCRIPTOR; 3282 3283 if (Adapter->tx_buf_num_flag == 0) 3284 Adapter->tx_freelist_num = 3285 DEFAULT_NUM_TX_FREELIST; 3286 3287 if (Adapter->rx_buf_num_flag == 0) 3288 Adapter->rx_freelist_limit = 3289 DEFAULT_NUM_RX_FREELIST; 3290 } 3291 } 3292 break; 3293 case MAC_PROP_PRIVATE: 3294 err = e1000g_set_priv_prop(Adapter, pr_name, 3295 pr_valsize, pr_val); 3296 break; 3297 default: 3298 err = ENOTSUP; 3299 break; 3300 } 3301 rw_exit(&Adapter->chip_lock); 3302 return (err); 3303 } 3304 3305 static int 3306 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3307 uint_t pr_valsize, void *pr_val) 3308 { 3309 struct e1000g *Adapter = arg; 3310 struct e1000_fc_info *fc = &Adapter->shared.fc; 3311 int err = 0; 3312 link_flowctrl_t flowctrl; 3313 uint64_t tmp = 0; 3314 3315 switch (pr_num) { 3316 case MAC_PROP_DUPLEX: 3317 ASSERT(pr_valsize >= sizeof (link_duplex_t)); 3318 bcopy(&Adapter->link_duplex, pr_val, 3319 sizeof (link_duplex_t)); 3320 break; 3321 case MAC_PROP_SPEED: 3322 ASSERT(pr_valsize >= sizeof (uint64_t)); 3323 tmp = Adapter->link_speed * 1000000ull; 3324 bcopy(&tmp, pr_val, sizeof (tmp)); 3325 break; 3326 case MAC_PROP_AUTONEG: 3327 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3328 break; 3329 case MAC_PROP_FLOWCTRL: 3330 ASSERT(pr_valsize >= sizeof (link_flowctrl_t)); 3331 switch (fc->current_mode) { 3332 case e1000_fc_none: 3333 flowctrl = LINK_FLOWCTRL_NONE; 3334 break; 3335 case e1000_fc_rx_pause: 3336 flowctrl = LINK_FLOWCTRL_RX; 3337 break; 3338 case e1000_fc_tx_pause: 3339 flowctrl = LINK_FLOWCTRL_TX; 3340 break; 3341 case e1000_fc_full: 3342 flowctrl = LINK_FLOWCTRL_BI; 3343 break; 3344 } 3345 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3346 break; 3347 case MAC_PROP_ADV_1000FDX_CAP: 3348 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3349 break; 3350 case MAC_PROP_EN_1000FDX_CAP: 3351 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3352 break; 3353 case MAC_PROP_ADV_1000HDX_CAP: 3354 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3355 break; 3356 case MAC_PROP_EN_1000HDX_CAP: 3357 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3358 break; 3359 case MAC_PROP_ADV_100FDX_CAP: 3360 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3361 break; 3362 case MAC_PROP_EN_100FDX_CAP: 3363 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3364 break; 3365 case MAC_PROP_ADV_100HDX_CAP: 3366 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3367 break; 3368 case MAC_PROP_EN_100HDX_CAP: 3369 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3370 break; 3371 case MAC_PROP_ADV_10FDX_CAP: 3372 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3373 break; 3374 case MAC_PROP_EN_10FDX_CAP: 3375 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3376 break; 3377 case MAC_PROP_ADV_10HDX_CAP: 3378 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3379 break; 3380 case MAC_PROP_EN_10HDX_CAP: 3381 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3382 break; 3383 case MAC_PROP_ADV_100T4_CAP: 3384 case MAC_PROP_EN_100T4_CAP: 3385 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3386 break; 3387 case MAC_PROP_PRIVATE: 3388 err = e1000g_get_priv_prop(Adapter, pr_name, 3389 pr_valsize, pr_val); 3390 break; 3391 default: 3392 err = ENOTSUP; 3393 break; 3394 } 3395 3396 return (err); 3397 } 3398 3399 static void 3400 e1000g_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3401 mac_prop_info_handle_t prh) 3402 { 3403 struct e1000g *Adapter = arg; 3404 struct e1000_hw *hw = &Adapter->shared; 3405 3406 switch (pr_num) { 3407 case MAC_PROP_DUPLEX: 3408 case MAC_PROP_SPEED: 3409 case MAC_PROP_ADV_1000FDX_CAP: 3410 case MAC_PROP_ADV_1000HDX_CAP: 3411 case MAC_PROP_ADV_100FDX_CAP: 3412 case MAC_PROP_ADV_100HDX_CAP: 3413 case MAC_PROP_ADV_10FDX_CAP: 3414 case MAC_PROP_ADV_10HDX_CAP: 3415 case MAC_PROP_ADV_100T4_CAP: 3416 case MAC_PROP_EN_100T4_CAP: 3417 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3418 break; 3419 3420 case MAC_PROP_EN_1000FDX_CAP: 3421 if (hw->phy.media_type != e1000_media_type_copper) { 3422 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3423 } else { 3424 mac_prop_info_set_default_uint8(prh, 3425 ((Adapter->phy_ext_status & 3426 IEEE_ESR_1000T_FD_CAPS) || 3427 (Adapter->phy_ext_status & 3428 IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0); 3429 } 3430 break; 3431 3432 case MAC_PROP_EN_100FDX_CAP: 3433 if (hw->phy.media_type != e1000_media_type_copper) { 3434 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3435 } else { 3436 mac_prop_info_set_default_uint8(prh, 3437 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3438 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3439 ? 1 : 0); 3440 } 3441 break; 3442 3443 case MAC_PROP_EN_100HDX_CAP: 3444 if (hw->phy.media_type != e1000_media_type_copper) { 3445 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3446 } else { 3447 mac_prop_info_set_default_uint8(prh, 3448 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 3449 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 3450 ? 1 : 0); 3451 } 3452 break; 3453 3454 case MAC_PROP_EN_10FDX_CAP: 3455 if (hw->phy.media_type != e1000_media_type_copper) { 3456 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3457 } else { 3458 mac_prop_info_set_default_uint8(prh, 3459 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0); 3460 } 3461 break; 3462 3463 case MAC_PROP_EN_10HDX_CAP: 3464 if (hw->phy.media_type != e1000_media_type_copper) { 3465 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3466 } else { 3467 mac_prop_info_set_default_uint8(prh, 3468 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0); 3469 } 3470 break; 3471 3472 case MAC_PROP_EN_1000HDX_CAP: 3473 if (hw->phy.media_type != e1000_media_type_copper) 3474 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3475 break; 3476 3477 case MAC_PROP_AUTONEG: 3478 if (hw->phy.media_type != e1000_media_type_copper) { 3479 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3480 } else { 3481 mac_prop_info_set_default_uint8(prh, 3482 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) 3483 ? 1 : 0); 3484 } 3485 break; 3486 3487 case MAC_PROP_FLOWCTRL: 3488 mac_prop_info_set_default_link_flowctrl(prh, LINK_FLOWCTRL_BI); 3489 break; 3490 3491 case MAC_PROP_MTU: { 3492 struct e1000_mac_info *mac = &Adapter->shared.mac; 3493 struct e1000_phy_info *phy = &Adapter->shared.phy; 3494 uint32_t max; 3495 3496 /* some MAC types do not support jumbo frames */ 3497 if ((mac->type == e1000_ich8lan) || 3498 ((mac->type == e1000_ich9lan) && (phy->type == 3499 e1000_phy_ife))) { 3500 max = DEFAULT_MTU; 3501 } else { 3502 max = Adapter->max_mtu; 3503 } 3504 3505 mac_prop_info_set_range_uint32(prh, DEFAULT_MTU, max); 3506 break; 3507 } 3508 case MAC_PROP_PRIVATE: { 3509 char valstr[64]; 3510 int value; 3511 3512 if (strcmp(pr_name, "_adv_pause_cap") == 0 || 3513 strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3514 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3515 return; 3516 } else if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3517 value = DEFAULT_TX_BCOPY_THRESHOLD; 3518 } else if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3519 value = DEFAULT_TX_INTR_ENABLE; 3520 } else if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3521 value = DEFAULT_TX_INTR_DELAY; 3522 } else if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3523 value = DEFAULT_TX_INTR_ABS_DELAY; 3524 } else if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3525 value = DEFAULT_RX_BCOPY_THRESHOLD; 3526 } else if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3527 value = DEFAULT_RX_LIMIT_ON_INTR; 3528 } else if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3529 value = DEFAULT_RX_INTR_DELAY; 3530 } else if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3531 value = DEFAULT_RX_INTR_ABS_DELAY; 3532 } else if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3533 value = DEFAULT_INTR_THROTTLING; 3534 } else if (strcmp(pr_name, "_intr_adaptive") == 0) { 3535 value = 1; 3536 } else { 3537 return; 3538 } 3539 3540 (void) snprintf(valstr, sizeof (valstr), "%d", value); 3541 mac_prop_info_set_default_str(prh, valstr); 3542 break; 3543 } 3544 } 3545 } 3546 3547 /* ARGSUSED2 */ 3548 static int 3549 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3550 uint_t pr_valsize, const void *pr_val) 3551 { 3552 int err = 0; 3553 long result; 3554 struct e1000_hw *hw = &Adapter->shared; 3555 3556 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3557 if (pr_val == NULL) { 3558 err = EINVAL; 3559 return (err); 3560 } 3561 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3562 if (result < MIN_TX_BCOPY_THRESHOLD || 3563 result > MAX_TX_BCOPY_THRESHOLD) 3564 err = EINVAL; 3565 else { 3566 Adapter->tx_bcopy_thresh = (uint32_t)result; 3567 } 3568 return (err); 3569 } 3570 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3571 if (pr_val == NULL) { 3572 err = EINVAL; 3573 return (err); 3574 } 3575 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3576 if (result < 0 || result > 1) 3577 err = EINVAL; 3578 else { 3579 Adapter->tx_intr_enable = (result == 1) ? 3580 B_TRUE: B_FALSE; 3581 if (Adapter->tx_intr_enable) 3582 e1000g_mask_tx_interrupt(Adapter); 3583 else 3584 e1000g_clear_tx_interrupt(Adapter); 3585 if (e1000g_check_acc_handle( 3586 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3587 ddi_fm_service_impact(Adapter->dip, 3588 DDI_SERVICE_DEGRADED); 3589 err = EIO; 3590 } 3591 } 3592 return (err); 3593 } 3594 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3595 if (pr_val == NULL) { 3596 err = EINVAL; 3597 return (err); 3598 } 3599 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3600 if (result < MIN_TX_INTR_DELAY || 3601 result > MAX_TX_INTR_DELAY) 3602 err = EINVAL; 3603 else { 3604 Adapter->tx_intr_delay = (uint32_t)result; 3605 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3606 if (e1000g_check_acc_handle( 3607 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3608 ddi_fm_service_impact(Adapter->dip, 3609 DDI_SERVICE_DEGRADED); 3610 err = EIO; 3611 } 3612 } 3613 return (err); 3614 } 3615 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3616 if (pr_val == NULL) { 3617 err = EINVAL; 3618 return (err); 3619 } 3620 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3621 if (result < MIN_TX_INTR_ABS_DELAY || 3622 result > MAX_TX_INTR_ABS_DELAY) 3623 err = EINVAL; 3624 else { 3625 Adapter->tx_intr_abs_delay = (uint32_t)result; 3626 E1000_WRITE_REG(hw, E1000_TADV, 3627 Adapter->tx_intr_abs_delay); 3628 if (e1000g_check_acc_handle( 3629 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3630 ddi_fm_service_impact(Adapter->dip, 3631 DDI_SERVICE_DEGRADED); 3632 err = EIO; 3633 } 3634 } 3635 return (err); 3636 } 3637 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3638 if (pr_val == NULL) { 3639 err = EINVAL; 3640 return (err); 3641 } 3642 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3643 if (result < MIN_RX_BCOPY_THRESHOLD || 3644 result > MAX_RX_BCOPY_THRESHOLD) 3645 err = EINVAL; 3646 else 3647 Adapter->rx_bcopy_thresh = (uint32_t)result; 3648 return (err); 3649 } 3650 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3651 if (pr_val == NULL) { 3652 err = EINVAL; 3653 return (err); 3654 } 3655 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3656 if (result < MIN_RX_LIMIT_ON_INTR || 3657 result > MAX_RX_LIMIT_ON_INTR) 3658 err = EINVAL; 3659 else 3660 Adapter->rx_limit_onintr = (uint32_t)result; 3661 return (err); 3662 } 3663 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3664 if (pr_val == NULL) { 3665 err = EINVAL; 3666 return (err); 3667 } 3668 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3669 if (result < MIN_RX_INTR_DELAY || 3670 result > MAX_RX_INTR_DELAY) 3671 err = EINVAL; 3672 else { 3673 Adapter->rx_intr_delay = (uint32_t)result; 3674 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3675 if (e1000g_check_acc_handle( 3676 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3677 ddi_fm_service_impact(Adapter->dip, 3678 DDI_SERVICE_DEGRADED); 3679 err = EIO; 3680 } 3681 } 3682 return (err); 3683 } 3684 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3685 if (pr_val == NULL) { 3686 err = EINVAL; 3687 return (err); 3688 } 3689 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3690 if (result < MIN_RX_INTR_ABS_DELAY || 3691 result > MAX_RX_INTR_ABS_DELAY) 3692 err = EINVAL; 3693 else { 3694 Adapter->rx_intr_abs_delay = (uint32_t)result; 3695 E1000_WRITE_REG(hw, E1000_RADV, 3696 Adapter->rx_intr_abs_delay); 3697 if (e1000g_check_acc_handle( 3698 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3699 ddi_fm_service_impact(Adapter->dip, 3700 DDI_SERVICE_DEGRADED); 3701 err = EIO; 3702 } 3703 } 3704 return (err); 3705 } 3706 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3707 if (pr_val == NULL) { 3708 err = EINVAL; 3709 return (err); 3710 } 3711 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3712 if (result < MIN_INTR_THROTTLING || 3713 result > MAX_INTR_THROTTLING) 3714 err = EINVAL; 3715 else { 3716 if (hw->mac.type >= e1000_82540) { 3717 Adapter->intr_throttling_rate = 3718 (uint32_t)result; 3719 E1000_WRITE_REG(hw, E1000_ITR, 3720 Adapter->intr_throttling_rate); 3721 if (e1000g_check_acc_handle( 3722 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3723 ddi_fm_service_impact(Adapter->dip, 3724 DDI_SERVICE_DEGRADED); 3725 err = EIO; 3726 } 3727 } else 3728 err = EINVAL; 3729 } 3730 return (err); 3731 } 3732 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3733 if (pr_val == NULL) { 3734 err = EINVAL; 3735 return (err); 3736 } 3737 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3738 if (result < 0 || result > 1) 3739 err = EINVAL; 3740 else { 3741 if (hw->mac.type >= e1000_82540) { 3742 Adapter->intr_adaptive = (result == 1) ? 3743 B_TRUE : B_FALSE; 3744 } else { 3745 err = EINVAL; 3746 } 3747 } 3748 return (err); 3749 } 3750 return (ENOTSUP); 3751 } 3752 3753 static int 3754 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3755 uint_t pr_valsize, void *pr_val) 3756 { 3757 int err = ENOTSUP; 3758 int value; 3759 3760 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3761 value = Adapter->param_adv_pause; 3762 err = 0; 3763 goto done; 3764 } 3765 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3766 value = Adapter->param_adv_asym_pause; 3767 err = 0; 3768 goto done; 3769 } 3770 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3771 value = Adapter->tx_bcopy_thresh; 3772 err = 0; 3773 goto done; 3774 } 3775 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3776 value = Adapter->tx_intr_enable; 3777 err = 0; 3778 goto done; 3779 } 3780 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3781 value = Adapter->tx_intr_delay; 3782 err = 0; 3783 goto done; 3784 } 3785 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3786 value = Adapter->tx_intr_abs_delay; 3787 err = 0; 3788 goto done; 3789 } 3790 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3791 value = Adapter->rx_bcopy_thresh; 3792 err = 0; 3793 goto done; 3794 } 3795 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3796 value = Adapter->rx_limit_onintr; 3797 err = 0; 3798 goto done; 3799 } 3800 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3801 value = Adapter->rx_intr_delay; 3802 err = 0; 3803 goto done; 3804 } 3805 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3806 value = Adapter->rx_intr_abs_delay; 3807 err = 0; 3808 goto done; 3809 } 3810 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3811 value = Adapter->intr_throttling_rate; 3812 err = 0; 3813 goto done; 3814 } 3815 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3816 value = Adapter->intr_adaptive; 3817 err = 0; 3818 goto done; 3819 } 3820 done: 3821 if (err == 0) { 3822 (void) snprintf(pr_val, pr_valsize, "%d", value); 3823 } 3824 return (err); 3825 } 3826 3827 /* 3828 * e1000g_get_conf - get configurations set in e1000g.conf 3829 * This routine gets user-configured values out of the configuration 3830 * file e1000g.conf. 3831 * 3832 * For each configurable value, there is a minimum, a maximum, and a 3833 * default. 3834 * If user does not configure a value, use the default. 3835 * If user configures below the minimum, use the minumum. 3836 * If user configures above the maximum, use the maxumum. 3837 */ 3838 static void 3839 e1000g_get_conf(struct e1000g *Adapter) 3840 { 3841 struct e1000_hw *hw = &Adapter->shared; 3842 boolean_t tbi_compatibility = B_FALSE; 3843 boolean_t is_jumbo = B_FALSE; 3844 int propval; 3845 /* 3846 * decrease the number of descriptors and free packets 3847 * for jumbo frames to reduce tx/rx resource consumption 3848 */ 3849 if (Adapter->max_frame_size >= FRAME_SIZE_UPTO_4K) { 3850 is_jumbo = B_TRUE; 3851 } 3852 3853 /* 3854 * get each configurable property from e1000g.conf 3855 */ 3856 3857 /* 3858 * NumTxDescriptors 3859 */ 3860 Adapter->tx_desc_num_flag = 3861 e1000g_get_prop(Adapter, "NumTxDescriptors", 3862 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3863 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 3864 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 3865 Adapter->tx_desc_num = propval; 3866 3867 /* 3868 * NumRxDescriptors 3869 */ 3870 Adapter->rx_desc_num_flag = 3871 e1000g_get_prop(Adapter, "NumRxDescriptors", 3872 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3873 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 3874 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 3875 Adapter->rx_desc_num = propval; 3876 3877 /* 3878 * NumRxFreeList 3879 */ 3880 Adapter->rx_buf_num_flag = 3881 e1000g_get_prop(Adapter, "NumRxFreeList", 3882 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3883 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 3884 : DEFAULT_NUM_RX_FREELIST, &propval); 3885 Adapter->rx_freelist_limit = propval; 3886 3887 /* 3888 * NumTxPacketList 3889 */ 3890 Adapter->tx_buf_num_flag = 3891 e1000g_get_prop(Adapter, "NumTxPacketList", 3892 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3893 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 3894 : DEFAULT_NUM_TX_FREELIST, &propval); 3895 Adapter->tx_freelist_num = propval; 3896 3897 /* 3898 * FlowControl 3899 */ 3900 hw->fc.send_xon = B_TRUE; 3901 (void) e1000g_get_prop(Adapter, "FlowControl", 3902 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 3903 hw->fc.requested_mode = propval; 3904 /* 4 is the setting that says "let the eeprom decide" */ 3905 if (hw->fc.requested_mode == 4) 3906 hw->fc.requested_mode = e1000_fc_default; 3907 3908 /* 3909 * Max Num Receive Packets on Interrupt 3910 */ 3911 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3912 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3913 DEFAULT_RX_LIMIT_ON_INTR, &propval); 3914 Adapter->rx_limit_onintr = propval; 3915 3916 /* 3917 * PHY master slave setting 3918 */ 3919 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 3920 e1000_ms_hw_default, e1000_ms_auto, 3921 e1000_ms_hw_default, &propval); 3922 hw->phy.ms_type = propval; 3923 3924 /* 3925 * Parameter which controls TBI mode workaround, which is only 3926 * needed on certain switches such as Cisco 6500/Foundry 3927 */ 3928 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3929 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 3930 tbi_compatibility = (propval == 1); 3931 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3932 3933 /* 3934 * MSI Enable 3935 */ 3936 (void) e1000g_get_prop(Adapter, "MSIEnable", 3937 0, 1, DEFAULT_MSI_ENABLE, &propval); 3938 Adapter->msi_enable = (propval == 1); 3939 3940 /* 3941 * Interrupt Throttling Rate 3942 */ 3943 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 3944 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3945 DEFAULT_INTR_THROTTLING, &propval); 3946 Adapter->intr_throttling_rate = propval; 3947 3948 /* 3949 * Adaptive Interrupt Blanking Enable/Disable 3950 * It is enabled by default 3951 */ 3952 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 3953 &propval); 3954 Adapter->intr_adaptive = (propval == 1); 3955 3956 /* 3957 * Hardware checksum enable/disable parameter 3958 */ 3959 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 3960 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 3961 Adapter->tx_hcksum_enable = (propval == 1); 3962 /* 3963 * Checksum on/off selection via global parameters. 3964 * 3965 * If the chip is flagged as not capable of (correctly) 3966 * handling checksumming, we don't enable it on either 3967 * Rx or Tx side. Otherwise, we take this chip's settings 3968 * from the patchable global defaults. 3969 * 3970 * We advertise our capabilities only if TX offload is 3971 * enabled. On receive, the stack will accept checksummed 3972 * packets anyway, even if we haven't said we can deliver 3973 * them. 3974 */ 3975 switch (hw->mac.type) { 3976 case e1000_82540: 3977 case e1000_82544: 3978 case e1000_82545: 3979 case e1000_82545_rev_3: 3980 case e1000_82546: 3981 case e1000_82546_rev_3: 3982 case e1000_82571: 3983 case e1000_82572: 3984 case e1000_82573: 3985 case e1000_80003es2lan: 3986 break; 3987 /* 3988 * For the following Intel PRO/1000 chipsets, we have not 3989 * tested the hardware checksum offload capability, so we 3990 * disable the capability for them. 3991 * e1000_82542, 3992 * e1000_82543, 3993 * e1000_82541, 3994 * e1000_82541_rev_2, 3995 * e1000_82547, 3996 * e1000_82547_rev_2, 3997 */ 3998 default: 3999 Adapter->tx_hcksum_enable = B_FALSE; 4000 } 4001 4002 /* 4003 * Large Send Offloading(LSO) Enable/Disable 4004 * If the tx hardware checksum is not enabled, LSO should be 4005 * disabled. 4006 */ 4007 (void) e1000g_get_prop(Adapter, "lso_enable", 4008 0, 1, DEFAULT_LSO_ENABLE, &propval); 4009 Adapter->lso_enable = (propval == 1); 4010 4011 switch (hw->mac.type) { 4012 case e1000_82546: 4013 case e1000_82546_rev_3: 4014 if (Adapter->lso_enable) 4015 Adapter->lso_premature_issue = B_TRUE; 4016 /* FALLTHRU */ 4017 case e1000_82571: 4018 case e1000_82572: 4019 case e1000_82573: 4020 case e1000_80003es2lan: 4021 break; 4022 default: 4023 Adapter->lso_enable = B_FALSE; 4024 } 4025 4026 if (!Adapter->tx_hcksum_enable) { 4027 Adapter->lso_premature_issue = B_FALSE; 4028 Adapter->lso_enable = B_FALSE; 4029 } 4030 4031 /* 4032 * If mem_workaround_82546 is enabled, the rx buffer allocated by 4033 * e1000_82545, e1000_82546 and e1000_82546_rev_3 4034 * will not cross 64k boundary. 4035 */ 4036 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 4037 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 4038 Adapter->mem_workaround_82546 = (propval == 1); 4039 4040 /* 4041 * Max number of multicast addresses 4042 */ 4043 (void) e1000g_get_prop(Adapter, "mcast_max_num", 4044 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 4045 &propval); 4046 Adapter->mcast_max_num = propval; 4047 } 4048 4049 /* 4050 * e1000g_get_prop - routine to read properties 4051 * 4052 * Get a user-configure property value out of the configuration 4053 * file e1000g.conf. 4054 * 4055 * Caller provides name of the property, a default value, a minimum 4056 * value, a maximum value and a pointer to the returned property 4057 * value. 4058 * 4059 * Return B_TRUE if the configured value of the property is not a default 4060 * value, otherwise return B_FALSE. 4061 */ 4062 static boolean_t 4063 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 4064 char *propname, /* name of the property */ 4065 int minval, /* minimum acceptable value */ 4066 int maxval, /* maximim acceptable value */ 4067 int defval, /* default value */ 4068 int *propvalue) /* property value return to caller */ 4069 { 4070 int propval; /* value returned for requested property */ 4071 int *props; /* point to array of properties returned */ 4072 uint_t nprops; /* number of property value returned */ 4073 boolean_t ret = B_TRUE; 4074 4075 /* 4076 * get the array of properties from the config file 4077 */ 4078 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 4079 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 4080 /* got some properties, test if we got enough */ 4081 if (Adapter->instance < nprops) { 4082 propval = props[Adapter->instance]; 4083 } else { 4084 /* not enough properties configured */ 4085 propval = defval; 4086 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4087 "Not Enough %s values found in e1000g.conf" 4088 " - set to %d\n", 4089 propname, propval); 4090 ret = B_FALSE; 4091 } 4092 4093 /* free memory allocated for properties */ 4094 ddi_prop_free(props); 4095 4096 } else { 4097 propval = defval; 4098 ret = B_FALSE; 4099 } 4100 4101 /* 4102 * enforce limits 4103 */ 4104 if (propval > maxval) { 4105 propval = maxval; 4106 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4107 "Too High %s value in e1000g.conf - set to %d\n", 4108 propname, propval); 4109 } 4110 4111 if (propval < minval) { 4112 propval = minval; 4113 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4114 "Too Low %s value in e1000g.conf - set to %d\n", 4115 propname, propval); 4116 } 4117 4118 *propvalue = propval; 4119 return (ret); 4120 } 4121 4122 static boolean_t 4123 e1000g_link_check(struct e1000g *Adapter) 4124 { 4125 uint16_t speed, duplex, phydata; 4126 boolean_t link_changed = B_FALSE; 4127 struct e1000_hw *hw; 4128 uint32_t reg_tarc; 4129 4130 hw = &Adapter->shared; 4131 4132 if (e1000g_link_up(Adapter)) { 4133 /* 4134 * The Link is up, check whether it was marked as down earlier 4135 */ 4136 if (Adapter->link_state != LINK_STATE_UP) { 4137 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 4138 Adapter->link_speed = speed; 4139 Adapter->link_duplex = duplex; 4140 Adapter->link_state = LINK_STATE_UP; 4141 link_changed = B_TRUE; 4142 4143 if (Adapter->link_speed == SPEED_1000) 4144 Adapter->stall_threshold = TX_STALL_TIME_2S; 4145 else 4146 Adapter->stall_threshold = TX_STALL_TIME_8S; 4147 4148 Adapter->tx_link_down_timeout = 0; 4149 4150 if ((hw->mac.type == e1000_82571) || 4151 (hw->mac.type == e1000_82572)) { 4152 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 4153 if (speed == SPEED_1000) 4154 reg_tarc |= (1 << 21); 4155 else 4156 reg_tarc &= ~(1 << 21); 4157 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 4158 } 4159 } 4160 Adapter->smartspeed = 0; 4161 } else { 4162 if (Adapter->link_state != LINK_STATE_DOWN) { 4163 Adapter->link_speed = 0; 4164 Adapter->link_duplex = 0; 4165 Adapter->link_state = LINK_STATE_DOWN; 4166 link_changed = B_TRUE; 4167 4168 /* 4169 * SmartSpeed workaround for Tabor/TanaX, When the 4170 * driver loses link disable auto master/slave 4171 * resolution. 4172 */ 4173 if (hw->phy.type == e1000_phy_igp) { 4174 (void) e1000_read_phy_reg(hw, 4175 PHY_1000T_CTRL, &phydata); 4176 phydata |= CR_1000T_MS_ENABLE; 4177 (void) e1000_write_phy_reg(hw, 4178 PHY_1000T_CTRL, phydata); 4179 } 4180 } else { 4181 e1000g_smartspeed(Adapter); 4182 } 4183 4184 if (Adapter->e1000g_state & E1000G_STARTED) { 4185 if (Adapter->tx_link_down_timeout < 4186 MAX_TX_LINK_DOWN_TIMEOUT) { 4187 Adapter->tx_link_down_timeout++; 4188 } else if (Adapter->tx_link_down_timeout == 4189 MAX_TX_LINK_DOWN_TIMEOUT) { 4190 e1000g_tx_clean(Adapter); 4191 Adapter->tx_link_down_timeout++; 4192 } 4193 } 4194 } 4195 4196 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4197 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4198 4199 return (link_changed); 4200 } 4201 4202 /* 4203 * e1000g_reset_link - Using the link properties to setup the link 4204 */ 4205 int 4206 e1000g_reset_link(struct e1000g *Adapter) 4207 { 4208 struct e1000_mac_info *mac; 4209 struct e1000_phy_info *phy; 4210 struct e1000_hw *hw; 4211 boolean_t invalid; 4212 4213 mac = &Adapter->shared.mac; 4214 phy = &Adapter->shared.phy; 4215 hw = &Adapter->shared; 4216 invalid = B_FALSE; 4217 4218 if (hw->phy.media_type != e1000_media_type_copper) 4219 goto out; 4220 4221 if (Adapter->param_adv_autoneg == 1) { 4222 mac->autoneg = B_TRUE; 4223 phy->autoneg_advertised = 0; 4224 4225 /* 4226 * 1000hdx is not supported for autonegotiation 4227 */ 4228 if (Adapter->param_adv_1000fdx == 1) 4229 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4230 4231 if (Adapter->param_adv_100fdx == 1) 4232 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4233 4234 if (Adapter->param_adv_100hdx == 1) 4235 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4236 4237 if (Adapter->param_adv_10fdx == 1) 4238 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4239 4240 if (Adapter->param_adv_10hdx == 1) 4241 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4242 4243 if (phy->autoneg_advertised == 0) 4244 invalid = B_TRUE; 4245 } else { 4246 mac->autoneg = B_FALSE; 4247 4248 /* 4249 * For Intel copper cards, 1000fdx and 1000hdx are not 4250 * supported for forced link 4251 */ 4252 if (Adapter->param_adv_100fdx == 1) 4253 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4254 else if (Adapter->param_adv_100hdx == 1) 4255 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4256 else if (Adapter->param_adv_10fdx == 1) 4257 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4258 else if (Adapter->param_adv_10hdx == 1) 4259 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4260 else 4261 invalid = B_TRUE; 4262 4263 } 4264 4265 if (invalid) { 4266 e1000g_log(Adapter, CE_WARN, 4267 "Invalid link settings. Setup link to " 4268 "support autonegotiation with all link capabilities."); 4269 mac->autoneg = B_TRUE; 4270 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4271 } 4272 4273 out: 4274 return (e1000_setup_link(&Adapter->shared)); 4275 } 4276 4277 static void 4278 e1000g_timer_tx_resched(struct e1000g *Adapter) 4279 { 4280 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4281 4282 rw_enter(&Adapter->chip_lock, RW_READER); 4283 4284 if (tx_ring->resched_needed && 4285 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4286 drv_usectohz(1000000)) && 4287 (Adapter->e1000g_state & E1000G_STARTED) && 4288 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4289 tx_ring->resched_needed = B_FALSE; 4290 mac_tx_update(Adapter->mh); 4291 E1000G_STAT(tx_ring->stat_reschedule); 4292 E1000G_STAT(tx_ring->stat_timer_reschedule); 4293 } 4294 4295 rw_exit(&Adapter->chip_lock); 4296 } 4297 4298 static void 4299 e1000g_local_timer(void *ws) 4300 { 4301 struct e1000g *Adapter = (struct e1000g *)ws; 4302 struct e1000_hw *hw; 4303 e1000g_ether_addr_t ether_addr; 4304 boolean_t link_changed; 4305 4306 hw = &Adapter->shared; 4307 4308 if (Adapter->e1000g_state & E1000G_ERROR) { 4309 rw_enter(&Adapter->chip_lock, RW_WRITER); 4310 Adapter->e1000g_state &= ~E1000G_ERROR; 4311 rw_exit(&Adapter->chip_lock); 4312 4313 Adapter->reset_count++; 4314 if (e1000g_global_reset(Adapter)) { 4315 ddi_fm_service_impact(Adapter->dip, 4316 DDI_SERVICE_RESTORED); 4317 e1000g_timer_tx_resched(Adapter); 4318 } else 4319 ddi_fm_service_impact(Adapter->dip, 4320 DDI_SERVICE_LOST); 4321 return; 4322 } 4323 4324 if (e1000g_stall_check(Adapter)) { 4325 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4326 "Tx stall detected. Activate automatic recovery.\n"); 4327 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4328 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4329 Adapter->reset_count++; 4330 if (e1000g_reset_adapter(Adapter)) { 4331 ddi_fm_service_impact(Adapter->dip, 4332 DDI_SERVICE_RESTORED); 4333 e1000g_timer_tx_resched(Adapter); 4334 } 4335 return; 4336 } 4337 4338 link_changed = B_FALSE; 4339 rw_enter(&Adapter->chip_lock, RW_READER); 4340 if (Adapter->link_complete) 4341 link_changed = e1000g_link_check(Adapter); 4342 rw_exit(&Adapter->chip_lock); 4343 4344 if (link_changed) { 4345 if (!Adapter->reset_flag && 4346 (Adapter->e1000g_state & E1000G_STARTED) && 4347 !(Adapter->e1000g_state & E1000G_SUSPENDED)) 4348 mac_link_update(Adapter->mh, Adapter->link_state); 4349 if (Adapter->link_state == LINK_STATE_UP) 4350 Adapter->reset_flag = B_FALSE; 4351 } 4352 /* 4353 * Workaround for esb2. Data stuck in fifo on a link 4354 * down event. Reset the adapter to recover it. 4355 */ 4356 if (Adapter->esb2_workaround) { 4357 Adapter->esb2_workaround = B_FALSE; 4358 (void) e1000g_reset_adapter(Adapter); 4359 return; 4360 } 4361 4362 /* 4363 * With 82571 controllers, any locally administered address will 4364 * be overwritten when there is a reset on the other port. 4365 * Detect this circumstance and correct it. 4366 */ 4367 if ((hw->mac.type == e1000_82571) && 4368 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4369 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4370 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4371 4372 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4373 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4374 4375 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4376 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4377 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4378 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4379 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4380 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4381 e1000_rar_set(hw, hw->mac.addr, 0); 4382 } 4383 } 4384 4385 /* 4386 * Long TTL workaround for 82541/82547 4387 */ 4388 (void) e1000_igp_ttl_workaround_82547(hw); 4389 4390 /* 4391 * Check for Adaptive IFS settings If there are lots of collisions 4392 * change the value in steps... 4393 * These properties should only be set for 10/100 4394 */ 4395 if ((hw->phy.media_type == e1000_media_type_copper) && 4396 ((Adapter->link_speed == SPEED_100) || 4397 (Adapter->link_speed == SPEED_10))) { 4398 e1000_update_adaptive(hw); 4399 } 4400 /* 4401 * Set Timer Interrupts 4402 */ 4403 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4404 4405 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4406 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4407 else 4408 e1000g_timer_tx_resched(Adapter); 4409 4410 restart_watchdog_timer(Adapter); 4411 } 4412 4413 /* 4414 * The function e1000g_link_timer() is called when the timer for link setup 4415 * is expired, which indicates the completion of the link setup. The link 4416 * state will not be updated until the link setup is completed. And the 4417 * link state will not be sent to the upper layer through mac_link_update() 4418 * in this function. It will be updated in the local timer routine or the 4419 * interrupt service routine after the interface is started (plumbed). 4420 */ 4421 static void 4422 e1000g_link_timer(void *arg) 4423 { 4424 struct e1000g *Adapter = (struct e1000g *)arg; 4425 4426 mutex_enter(&Adapter->link_lock); 4427 Adapter->link_complete = B_TRUE; 4428 Adapter->link_tid = 0; 4429 mutex_exit(&Adapter->link_lock); 4430 } 4431 4432 /* 4433 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4434 * 4435 * This function read the forced speed and duplex for 10/100 Mbps speeds 4436 * and also for 1000 Mbps speeds from the e1000g.conf file 4437 */ 4438 static void 4439 e1000g_force_speed_duplex(struct e1000g *Adapter) 4440 { 4441 int forced; 4442 int propval; 4443 struct e1000_mac_info *mac = &Adapter->shared.mac; 4444 struct e1000_phy_info *phy = &Adapter->shared.phy; 4445 4446 /* 4447 * get value out of config file 4448 */ 4449 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4450 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4451 4452 switch (forced) { 4453 case GDIAG_10_HALF: 4454 /* 4455 * Disable Auto Negotiation 4456 */ 4457 mac->autoneg = B_FALSE; 4458 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4459 break; 4460 case GDIAG_10_FULL: 4461 /* 4462 * Disable Auto Negotiation 4463 */ 4464 mac->autoneg = B_FALSE; 4465 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4466 break; 4467 case GDIAG_100_HALF: 4468 /* 4469 * Disable Auto Negotiation 4470 */ 4471 mac->autoneg = B_FALSE; 4472 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4473 break; 4474 case GDIAG_100_FULL: 4475 /* 4476 * Disable Auto Negotiation 4477 */ 4478 mac->autoneg = B_FALSE; 4479 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4480 break; 4481 case GDIAG_1000_FULL: 4482 /* 4483 * The gigabit spec requires autonegotiation. Therefore, 4484 * when the user wants to force the speed to 1000Mbps, we 4485 * enable AutoNeg, but only allow the harware to advertise 4486 * 1000Mbps. This is different from 10/100 operation, where 4487 * we are allowed to link without any negotiation. 4488 */ 4489 mac->autoneg = B_TRUE; 4490 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4491 break; 4492 default: /* obey the setting of AutoNegAdvertised */ 4493 mac->autoneg = B_TRUE; 4494 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4495 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4496 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4497 phy->autoneg_advertised = (uint16_t)propval; 4498 break; 4499 } /* switch */ 4500 } 4501 4502 /* 4503 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4504 * 4505 * This function reads MaxFrameSize from e1000g.conf 4506 */ 4507 static void 4508 e1000g_get_max_frame_size(struct e1000g *Adapter) 4509 { 4510 int max_frame; 4511 4512 /* 4513 * get value out of config file 4514 */ 4515 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4516 &max_frame); 4517 4518 switch (max_frame) { 4519 case 0: 4520 Adapter->default_mtu = ETHERMTU; 4521 break; 4522 case 1: 4523 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4524 sizeof (struct ether_vlan_header) - ETHERFCSL; 4525 break; 4526 case 2: 4527 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4528 sizeof (struct ether_vlan_header) - ETHERFCSL; 4529 break; 4530 case 3: 4531 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4532 sizeof (struct ether_vlan_header) - ETHERFCSL; 4533 break; 4534 default: 4535 Adapter->default_mtu = ETHERMTU; 4536 break; 4537 } /* switch */ 4538 4539 /* 4540 * If the user configed MTU is larger than the deivce's maximum MTU, 4541 * the MTU is set to the deivce's maximum value. 4542 */ 4543 if (Adapter->default_mtu > Adapter->max_mtu) 4544 Adapter->default_mtu = Adapter->max_mtu; 4545 4546 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4547 } 4548 4549 /* 4550 * e1000g_pch_limits - Apply limits of the PCH silicon type 4551 * 4552 * At any frame size larger than the ethernet default, 4553 * prevent linking at 10/100 speeds. 4554 */ 4555 static void 4556 e1000g_pch_limits(struct e1000g *Adapter) 4557 { 4558 struct e1000_hw *hw = &Adapter->shared; 4559 4560 /* only applies to PCH silicon type */ 4561 if (hw->mac.type != e1000_pchlan && hw->mac.type != e1000_pch2lan) 4562 return; 4563 4564 /* only applies to frames larger than ethernet default */ 4565 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4566 hw->mac.autoneg = B_TRUE; 4567 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4568 4569 Adapter->param_adv_autoneg = 1; 4570 Adapter->param_adv_1000fdx = 1; 4571 4572 Adapter->param_adv_100fdx = 0; 4573 Adapter->param_adv_100hdx = 0; 4574 Adapter->param_adv_10fdx = 0; 4575 Adapter->param_adv_10hdx = 0; 4576 4577 e1000g_param_sync(Adapter); 4578 } 4579 } 4580 4581 /* 4582 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4583 */ 4584 static uint32_t 4585 e1000g_mtu2maxframe(uint32_t mtu) 4586 { 4587 uint32_t maxframe; 4588 4589 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4590 4591 return (maxframe); 4592 } 4593 4594 static void 4595 arm_watchdog_timer(struct e1000g *Adapter) 4596 { 4597 Adapter->watchdog_tid = 4598 timeout(e1000g_local_timer, 4599 (void *)Adapter, 1 * drv_usectohz(1000000)); 4600 } 4601 #pragma inline(arm_watchdog_timer) 4602 4603 static void 4604 enable_watchdog_timer(struct e1000g *Adapter) 4605 { 4606 mutex_enter(&Adapter->watchdog_lock); 4607 4608 if (!Adapter->watchdog_timer_enabled) { 4609 Adapter->watchdog_timer_enabled = B_TRUE; 4610 Adapter->watchdog_timer_started = B_TRUE; 4611 arm_watchdog_timer(Adapter); 4612 } 4613 4614 mutex_exit(&Adapter->watchdog_lock); 4615 } 4616 4617 static void 4618 disable_watchdog_timer(struct e1000g *Adapter) 4619 { 4620 timeout_id_t tid; 4621 4622 mutex_enter(&Adapter->watchdog_lock); 4623 4624 Adapter->watchdog_timer_enabled = B_FALSE; 4625 Adapter->watchdog_timer_started = B_FALSE; 4626 tid = Adapter->watchdog_tid; 4627 Adapter->watchdog_tid = 0; 4628 4629 mutex_exit(&Adapter->watchdog_lock); 4630 4631 if (tid != 0) 4632 (void) untimeout(tid); 4633 } 4634 4635 static void 4636 start_watchdog_timer(struct e1000g *Adapter) 4637 { 4638 mutex_enter(&Adapter->watchdog_lock); 4639 4640 if (Adapter->watchdog_timer_enabled) { 4641 if (!Adapter->watchdog_timer_started) { 4642 Adapter->watchdog_timer_started = B_TRUE; 4643 arm_watchdog_timer(Adapter); 4644 } 4645 } 4646 4647 mutex_exit(&Adapter->watchdog_lock); 4648 } 4649 4650 static void 4651 restart_watchdog_timer(struct e1000g *Adapter) 4652 { 4653 mutex_enter(&Adapter->watchdog_lock); 4654 4655 if (Adapter->watchdog_timer_started) 4656 arm_watchdog_timer(Adapter); 4657 4658 mutex_exit(&Adapter->watchdog_lock); 4659 } 4660 4661 static void 4662 stop_watchdog_timer(struct e1000g *Adapter) 4663 { 4664 timeout_id_t tid; 4665 4666 mutex_enter(&Adapter->watchdog_lock); 4667 4668 Adapter->watchdog_timer_started = B_FALSE; 4669 tid = Adapter->watchdog_tid; 4670 Adapter->watchdog_tid = 0; 4671 4672 mutex_exit(&Adapter->watchdog_lock); 4673 4674 if (tid != 0) 4675 (void) untimeout(tid); 4676 } 4677 4678 static void 4679 stop_link_timer(struct e1000g *Adapter) 4680 { 4681 timeout_id_t tid; 4682 4683 /* Disable the link timer */ 4684 mutex_enter(&Adapter->link_lock); 4685 4686 tid = Adapter->link_tid; 4687 Adapter->link_tid = 0; 4688 4689 mutex_exit(&Adapter->link_lock); 4690 4691 if (tid != 0) 4692 (void) untimeout(tid); 4693 } 4694 4695 static void 4696 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4697 { 4698 timeout_id_t tid; 4699 4700 /* Disable the tx timer for 82547 chipset */ 4701 mutex_enter(&tx_ring->tx_lock); 4702 4703 tx_ring->timer_enable_82547 = B_FALSE; 4704 tid = tx_ring->timer_id_82547; 4705 tx_ring->timer_id_82547 = 0; 4706 4707 mutex_exit(&tx_ring->tx_lock); 4708 4709 if (tid != 0) 4710 (void) untimeout(tid); 4711 } 4712 4713 void 4714 e1000g_clear_interrupt(struct e1000g *Adapter) 4715 { 4716 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4717 0xffffffff & ~E1000_IMS_RXSEQ); 4718 } 4719 4720 void 4721 e1000g_mask_interrupt(struct e1000g *Adapter) 4722 { 4723 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4724 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4725 4726 if (Adapter->tx_intr_enable) 4727 e1000g_mask_tx_interrupt(Adapter); 4728 } 4729 4730 /* 4731 * This routine is called by e1000g_quiesce(), therefore must not block. 4732 */ 4733 void 4734 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4735 { 4736 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4737 } 4738 4739 void 4740 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4741 { 4742 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4743 } 4744 4745 void 4746 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4747 { 4748 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4749 } 4750 4751 static void 4752 e1000g_smartspeed(struct e1000g *Adapter) 4753 { 4754 struct e1000_hw *hw = &Adapter->shared; 4755 uint16_t phy_status; 4756 uint16_t phy_ctrl; 4757 4758 /* 4759 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4760 * advertising 1000Full, we don't even use the workaround 4761 */ 4762 if ((hw->phy.type != e1000_phy_igp) || 4763 !hw->mac.autoneg || 4764 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4765 return; 4766 4767 /* 4768 * True if this is the first call of this function or after every 4769 * 30 seconds of not having link 4770 */ 4771 if (Adapter->smartspeed == 0) { 4772 /* 4773 * If Master/Slave config fault is asserted twice, we 4774 * assume back-to-back 4775 */ 4776 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4777 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4778 return; 4779 4780 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4781 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4782 return; 4783 /* 4784 * We're assuming back-2-back because our status register 4785 * insists! there's a fault in the master/slave 4786 * relationship that was "negotiated" 4787 */ 4788 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4789 /* 4790 * Is the phy configured for manual configuration of 4791 * master/slave? 4792 */ 4793 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4794 /* 4795 * Yes. Then disable manual configuration (enable 4796 * auto configuration) of master/slave 4797 */ 4798 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4799 (void) e1000_write_phy_reg(hw, 4800 PHY_1000T_CTRL, phy_ctrl); 4801 /* 4802 * Effectively starting the clock 4803 */ 4804 Adapter->smartspeed++; 4805 /* 4806 * Restart autonegotiation 4807 */ 4808 if (!e1000_phy_setup_autoneg(hw) && 4809 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4810 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4811 MII_CR_RESTART_AUTO_NEG); 4812 (void) e1000_write_phy_reg(hw, 4813 PHY_CONTROL, phy_ctrl); 4814 } 4815 } 4816 return; 4817 /* 4818 * Has 6 seconds transpired still without link? Remember, 4819 * you should reset the smartspeed counter once you obtain 4820 * link 4821 */ 4822 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4823 /* 4824 * Yes. Remember, we did at the start determine that 4825 * there's a master/slave configuration fault, so we're 4826 * still assuming there's someone on the other end, but we 4827 * just haven't yet been able to talk to it. We then 4828 * re-enable auto configuration of master/slave to see if 4829 * we're running 2/3 pair cables. 4830 */ 4831 /* 4832 * If still no link, perhaps using 2/3 pair cable 4833 */ 4834 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4835 phy_ctrl |= CR_1000T_MS_ENABLE; 4836 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4837 /* 4838 * Restart autoneg with phy enabled for manual 4839 * configuration of master/slave 4840 */ 4841 if (!e1000_phy_setup_autoneg(hw) && 4842 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4843 phy_ctrl |= 4844 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4845 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4846 } 4847 /* 4848 * Hopefully, there are no more faults and we've obtained 4849 * link as a result. 4850 */ 4851 } 4852 /* 4853 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4854 * seconds) 4855 */ 4856 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4857 Adapter->smartspeed = 0; 4858 } 4859 4860 static boolean_t 4861 is_valid_mac_addr(uint8_t *mac_addr) 4862 { 4863 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4864 const uint8_t addr_test2[6] = 4865 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4866 4867 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4868 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4869 return (B_FALSE); 4870 4871 return (B_TRUE); 4872 } 4873 4874 /* 4875 * e1000g_stall_check - check for tx stall 4876 * 4877 * This function checks if the adapter is stalled (in transmit). 4878 * 4879 * It is called each time the watchdog timeout is invoked. 4880 * If the transmit descriptor reclaim continuously fails, 4881 * the watchdog value will increment by 1. If the watchdog 4882 * value exceeds the threshold, the adapter is assumed to 4883 * have stalled and need to be reset. 4884 */ 4885 static boolean_t 4886 e1000g_stall_check(struct e1000g *Adapter) 4887 { 4888 e1000g_tx_ring_t *tx_ring; 4889 4890 tx_ring = Adapter->tx_ring; 4891 4892 if (Adapter->link_state != LINK_STATE_UP) 4893 return (B_FALSE); 4894 4895 (void) e1000g_recycle(tx_ring); 4896 4897 if (Adapter->stall_flag) 4898 return (B_TRUE); 4899 4900 return (B_FALSE); 4901 } 4902 4903 #ifdef E1000G_DEBUG 4904 static enum ioc_reply 4905 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4906 { 4907 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4908 e1000g_peekpoke_t *ppd; 4909 uint64_t mem_va; 4910 uint64_t maxoff; 4911 boolean_t peek; 4912 4913 switch (iocp->ioc_cmd) { 4914 4915 case E1000G_IOC_REG_PEEK: 4916 peek = B_TRUE; 4917 break; 4918 4919 case E1000G_IOC_REG_POKE: 4920 peek = B_FALSE; 4921 break; 4922 4923 deault: 4924 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4925 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4926 iocp->ioc_cmd); 4927 return (IOC_INVAL); 4928 } 4929 4930 /* 4931 * Validate format of ioctl 4932 */ 4933 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4934 return (IOC_INVAL); 4935 if (mp->b_cont == NULL) 4936 return (IOC_INVAL); 4937 4938 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4939 4940 /* 4941 * Validate request parameters 4942 */ 4943 switch (ppd->pp_acc_space) { 4944 4945 default: 4946 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4947 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4948 ppd->pp_acc_space); 4949 return (IOC_INVAL); 4950 4951 case E1000G_PP_SPACE_REG: 4952 /* 4953 * Memory-mapped I/O space 4954 */ 4955 ASSERT(ppd->pp_acc_size == 4); 4956 if (ppd->pp_acc_size != 4) 4957 return (IOC_INVAL); 4958 4959 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4960 return (IOC_INVAL); 4961 4962 mem_va = 0; 4963 maxoff = 0x10000; 4964 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4965 break; 4966 4967 case E1000G_PP_SPACE_E1000G: 4968 /* 4969 * E1000g data structure! 4970 */ 4971 mem_va = (uintptr_t)e1000gp; 4972 maxoff = sizeof (struct e1000g); 4973 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4974 break; 4975 4976 } 4977 4978 if (ppd->pp_acc_offset >= maxoff) 4979 return (IOC_INVAL); 4980 4981 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4982 return (IOC_INVAL); 4983 4984 /* 4985 * All OK - go! 4986 */ 4987 ppd->pp_acc_offset += mem_va; 4988 (*ppfn)(e1000gp, ppd); 4989 return (peek ? IOC_REPLY : IOC_ACK); 4990 } 4991 4992 static void 4993 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4994 { 4995 ddi_acc_handle_t handle; 4996 uint32_t *regaddr; 4997 4998 handle = e1000gp->osdep.reg_handle; 4999 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5000 (uintptr_t)ppd->pp_acc_offset); 5001 5002 ppd->pp_acc_data = ddi_get32(handle, regaddr); 5003 } 5004 5005 static void 5006 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5007 { 5008 ddi_acc_handle_t handle; 5009 uint32_t *regaddr; 5010 uint32_t value; 5011 5012 handle = e1000gp->osdep.reg_handle; 5013 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5014 (uintptr_t)ppd->pp_acc_offset); 5015 value = (uint32_t)ppd->pp_acc_data; 5016 5017 ddi_put32(handle, regaddr, value); 5018 } 5019 5020 static void 5021 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5022 { 5023 uint64_t value; 5024 void *vaddr; 5025 5026 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5027 5028 switch (ppd->pp_acc_size) { 5029 case 1: 5030 value = *(uint8_t *)vaddr; 5031 break; 5032 5033 case 2: 5034 value = *(uint16_t *)vaddr; 5035 break; 5036 5037 case 4: 5038 value = *(uint32_t *)vaddr; 5039 break; 5040 5041 case 8: 5042 value = *(uint64_t *)vaddr; 5043 break; 5044 } 5045 5046 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5047 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 5048 (void *)e1000gp, (void *)ppd, value, vaddr); 5049 5050 ppd->pp_acc_data = value; 5051 } 5052 5053 static void 5054 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5055 { 5056 uint64_t value; 5057 void *vaddr; 5058 5059 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5060 value = ppd->pp_acc_data; 5061 5062 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5063 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 5064 (void *)e1000gp, (void *)ppd, value, vaddr); 5065 5066 switch (ppd->pp_acc_size) { 5067 case 1: 5068 *(uint8_t *)vaddr = (uint8_t)value; 5069 break; 5070 5071 case 2: 5072 *(uint16_t *)vaddr = (uint16_t)value; 5073 break; 5074 5075 case 4: 5076 *(uint32_t *)vaddr = (uint32_t)value; 5077 break; 5078 5079 case 8: 5080 *(uint64_t *)vaddr = (uint64_t)value; 5081 break; 5082 } 5083 } 5084 #endif 5085 5086 /* 5087 * Loopback Support 5088 */ 5089 static lb_property_t lb_normal = 5090 { normal, "normal", E1000G_LB_NONE }; 5091 static lb_property_t lb_external1000 = 5092 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 5093 static lb_property_t lb_external100 = 5094 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 5095 static lb_property_t lb_external10 = 5096 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 5097 static lb_property_t lb_phy = 5098 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 5099 5100 static enum ioc_reply 5101 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 5102 { 5103 lb_info_sz_t *lbsp; 5104 lb_property_t *lbpp; 5105 struct e1000_hw *hw; 5106 uint32_t *lbmp; 5107 uint32_t size; 5108 uint32_t value; 5109 5110 hw = &Adapter->shared; 5111 5112 if (mp->b_cont == NULL) 5113 return (IOC_INVAL); 5114 5115 if (!e1000g_check_loopback_support(hw)) { 5116 e1000g_log(NULL, CE_WARN, 5117 "Loopback is not supported on e1000g%d", Adapter->instance); 5118 return (IOC_INVAL); 5119 } 5120 5121 switch (iocp->ioc_cmd) { 5122 default: 5123 return (IOC_INVAL); 5124 5125 case LB_GET_INFO_SIZE: 5126 size = sizeof (lb_info_sz_t); 5127 if (iocp->ioc_count != size) 5128 return (IOC_INVAL); 5129 5130 rw_enter(&Adapter->chip_lock, RW_WRITER); 5131 e1000g_get_phy_state(Adapter); 5132 5133 /* 5134 * Workaround for hardware faults. In order to get a stable 5135 * state of phy, we will wait for a specific interval and 5136 * try again. The time delay is an experiential value based 5137 * on our testing. 5138 */ 5139 msec_delay(100); 5140 e1000g_get_phy_state(Adapter); 5141 rw_exit(&Adapter->chip_lock); 5142 5143 value = sizeof (lb_normal); 5144 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5145 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5146 (hw->phy.media_type == e1000_media_type_fiber) || 5147 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5148 value += sizeof (lb_phy); 5149 switch (hw->mac.type) { 5150 case e1000_82571: 5151 case e1000_82572: 5152 case e1000_80003es2lan: 5153 value += sizeof (lb_external1000); 5154 break; 5155 } 5156 } 5157 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5158 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5159 value += sizeof (lb_external100); 5160 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5161 value += sizeof (lb_external10); 5162 5163 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 5164 *lbsp = value; 5165 break; 5166 5167 case LB_GET_INFO: 5168 value = sizeof (lb_normal); 5169 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5170 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5171 (hw->phy.media_type == e1000_media_type_fiber) || 5172 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5173 value += sizeof (lb_phy); 5174 switch (hw->mac.type) { 5175 case e1000_82571: 5176 case e1000_82572: 5177 case e1000_80003es2lan: 5178 value += sizeof (lb_external1000); 5179 break; 5180 } 5181 } 5182 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5183 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5184 value += sizeof (lb_external100); 5185 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5186 value += sizeof (lb_external10); 5187 5188 size = value; 5189 if (iocp->ioc_count != size) 5190 return (IOC_INVAL); 5191 5192 value = 0; 5193 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5194 lbpp[value++] = lb_normal; 5195 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5196 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5197 (hw->phy.media_type == e1000_media_type_fiber) || 5198 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5199 lbpp[value++] = lb_phy; 5200 switch (hw->mac.type) { 5201 case e1000_82571: 5202 case e1000_82572: 5203 case e1000_80003es2lan: 5204 lbpp[value++] = lb_external1000; 5205 break; 5206 } 5207 } 5208 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5209 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5210 lbpp[value++] = lb_external100; 5211 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5212 lbpp[value++] = lb_external10; 5213 break; 5214 5215 case LB_GET_MODE: 5216 size = sizeof (uint32_t); 5217 if (iocp->ioc_count != size) 5218 return (IOC_INVAL); 5219 5220 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5221 *lbmp = Adapter->loopback_mode; 5222 break; 5223 5224 case LB_SET_MODE: 5225 size = 0; 5226 if (iocp->ioc_count != sizeof (uint32_t)) 5227 return (IOC_INVAL); 5228 5229 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5230 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5231 return (IOC_INVAL); 5232 break; 5233 } 5234 5235 iocp->ioc_count = size; 5236 iocp->ioc_error = 0; 5237 5238 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5239 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5240 return (IOC_INVAL); 5241 } 5242 5243 return (IOC_REPLY); 5244 } 5245 5246 static boolean_t 5247 e1000g_check_loopback_support(struct e1000_hw *hw) 5248 { 5249 switch (hw->mac.type) { 5250 case e1000_82540: 5251 case e1000_82545: 5252 case e1000_82545_rev_3: 5253 case e1000_82546: 5254 case e1000_82546_rev_3: 5255 case e1000_82541: 5256 case e1000_82541_rev_2: 5257 case e1000_82547: 5258 case e1000_82547_rev_2: 5259 case e1000_82571: 5260 case e1000_82572: 5261 case e1000_82573: 5262 case e1000_82574: 5263 case e1000_80003es2lan: 5264 case e1000_ich9lan: 5265 case e1000_ich10lan: 5266 return (B_TRUE); 5267 } 5268 return (B_FALSE); 5269 } 5270 5271 static boolean_t 5272 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5273 { 5274 struct e1000_hw *hw; 5275 int i, times; 5276 boolean_t link_up; 5277 5278 if (mode == Adapter->loopback_mode) 5279 return (B_TRUE); 5280 5281 hw = &Adapter->shared; 5282 times = 0; 5283 5284 Adapter->loopback_mode = mode; 5285 5286 if (mode == E1000G_LB_NONE) { 5287 /* Reset the chip */ 5288 hw->phy.autoneg_wait_to_complete = B_TRUE; 5289 (void) e1000g_reset_adapter(Adapter); 5290 hw->phy.autoneg_wait_to_complete = B_FALSE; 5291 return (B_TRUE); 5292 } 5293 5294 again: 5295 5296 rw_enter(&Adapter->chip_lock, RW_WRITER); 5297 5298 switch (mode) { 5299 default: 5300 rw_exit(&Adapter->chip_lock); 5301 return (B_FALSE); 5302 5303 case E1000G_LB_EXTERNAL_1000: 5304 e1000g_set_external_loopback_1000(Adapter); 5305 break; 5306 5307 case E1000G_LB_EXTERNAL_100: 5308 e1000g_set_external_loopback_100(Adapter); 5309 break; 5310 5311 case E1000G_LB_EXTERNAL_10: 5312 e1000g_set_external_loopback_10(Adapter); 5313 break; 5314 5315 case E1000G_LB_INTERNAL_PHY: 5316 e1000g_set_internal_loopback(Adapter); 5317 break; 5318 } 5319 5320 times++; 5321 5322 rw_exit(&Adapter->chip_lock); 5323 5324 /* Wait for link up */ 5325 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5326 msec_delay(100); 5327 5328 rw_enter(&Adapter->chip_lock, RW_WRITER); 5329 5330 link_up = e1000g_link_up(Adapter); 5331 5332 rw_exit(&Adapter->chip_lock); 5333 5334 if (!link_up) { 5335 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5336 "Failed to get the link up"); 5337 if (times < 2) { 5338 /* Reset the link */ 5339 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5340 "Reset the link ..."); 5341 (void) e1000g_reset_adapter(Adapter); 5342 goto again; 5343 } 5344 5345 /* 5346 * Reset driver to loopback none when set loopback failed 5347 * for the second time. 5348 */ 5349 Adapter->loopback_mode = E1000G_LB_NONE; 5350 5351 /* Reset the chip */ 5352 hw->phy.autoneg_wait_to_complete = B_TRUE; 5353 (void) e1000g_reset_adapter(Adapter); 5354 hw->phy.autoneg_wait_to_complete = B_FALSE; 5355 5356 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5357 "Set loopback mode failed, reset to loopback none"); 5358 5359 return (B_FALSE); 5360 } 5361 5362 return (B_TRUE); 5363 } 5364 5365 /* 5366 * The following loopback settings are from Intel's technical 5367 * document - "How To Loopback". All the register settings and 5368 * time delay values are directly inherited from the document 5369 * without more explanations available. 5370 */ 5371 static void 5372 e1000g_set_internal_loopback(struct e1000g *Adapter) 5373 { 5374 struct e1000_hw *hw; 5375 uint32_t ctrl; 5376 uint32_t status; 5377 uint16_t phy_ctrl; 5378 uint16_t phy_reg; 5379 uint32_t txcw; 5380 5381 hw = &Adapter->shared; 5382 5383 /* Disable Smart Power Down */ 5384 phy_spd_state(hw, B_FALSE); 5385 5386 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5387 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5388 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5389 5390 switch (hw->mac.type) { 5391 case e1000_82540: 5392 case e1000_82545: 5393 case e1000_82545_rev_3: 5394 case e1000_82546: 5395 case e1000_82546_rev_3: 5396 case e1000_82573: 5397 /* Auto-MDI/MDIX off */ 5398 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5399 /* Reset PHY to update Auto-MDI/MDIX */ 5400 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5401 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5402 /* Reset PHY to auto-neg off and force 1000 */ 5403 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5404 phy_ctrl | MII_CR_RESET); 5405 /* 5406 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5407 * See comments above e1000g_set_internal_loopback() for the 5408 * background. 5409 */ 5410 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5411 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5412 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5413 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5414 break; 5415 case e1000_80003es2lan: 5416 /* Force Link Up */ 5417 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5418 0x1CC); 5419 /* Sets PCS loopback at 1Gbs */ 5420 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5421 0x1046); 5422 break; 5423 } 5424 5425 /* 5426 * The following registers should be set for e1000_phy_bm phy type. 5427 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5428 * For others, we do not need to set these registers. 5429 */ 5430 if (hw->phy.type == e1000_phy_bm) { 5431 /* Set Default MAC Interface speed to 1GB */ 5432 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5433 phy_reg &= ~0x0007; 5434 phy_reg |= 0x006; 5435 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5436 /* Assert SW reset for above settings to take effect */ 5437 (void) e1000_phy_commit(hw); 5438 msec_delay(1); 5439 /* Force Full Duplex */ 5440 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5441 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5442 phy_reg | 0x000C); 5443 /* Set Link Up (in force link) */ 5444 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5445 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5446 phy_reg | 0x0040); 5447 /* Force Link */ 5448 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5449 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5450 phy_reg | 0x0040); 5451 /* Set Early Link Enable */ 5452 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5453 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5454 phy_reg | 0x0400); 5455 } 5456 5457 /* Set loopback */ 5458 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5459 5460 msec_delay(250); 5461 5462 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5463 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5464 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5465 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5466 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5467 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5468 E1000_CTRL_FD); /* Force Duplex to FULL */ 5469 5470 switch (hw->mac.type) { 5471 case e1000_82540: 5472 case e1000_82545: 5473 case e1000_82545_rev_3: 5474 case e1000_82546: 5475 case e1000_82546_rev_3: 5476 /* 5477 * For some serdes we'll need to commit the writes now 5478 * so that the status is updated on link 5479 */ 5480 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5481 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5482 msec_delay(100); 5483 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5484 } 5485 5486 if (hw->phy.media_type == e1000_media_type_copper) { 5487 /* Invert Loss of Signal */ 5488 ctrl |= E1000_CTRL_ILOS; 5489 } else { 5490 /* Set ILOS on fiber nic if half duplex is detected */ 5491 status = E1000_READ_REG(hw, E1000_STATUS); 5492 if ((status & E1000_STATUS_FD) == 0) 5493 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5494 } 5495 break; 5496 5497 case e1000_82571: 5498 case e1000_82572: 5499 /* 5500 * The fiber/SerDes versions of this adapter do not contain an 5501 * accessible PHY. Therefore, loopback beyond MAC must be done 5502 * using SerDes analog loopback. 5503 */ 5504 if (hw->phy.media_type != e1000_media_type_copper) { 5505 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5506 txcw = E1000_READ_REG(hw, E1000_TXCW); 5507 txcw &= ~((uint32_t)1 << 31); 5508 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5509 5510 /* 5511 * Write 0x410 to Serdes Control register 5512 * to enable Serdes analog loopback 5513 */ 5514 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5515 msec_delay(10); 5516 } 5517 5518 status = E1000_READ_REG(hw, E1000_STATUS); 5519 /* Set ILOS on fiber nic if half duplex is detected */ 5520 if ((hw->phy.media_type == e1000_media_type_fiber) && 5521 ((status & E1000_STATUS_FD) == 0 || 5522 (status & E1000_STATUS_LU) == 0)) 5523 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5524 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5525 ctrl |= E1000_CTRL_SLU; 5526 break; 5527 5528 case e1000_82573: 5529 ctrl |= E1000_CTRL_ILOS; 5530 break; 5531 case e1000_ich9lan: 5532 case e1000_ich10lan: 5533 ctrl |= E1000_CTRL_SLU; 5534 break; 5535 } 5536 if (hw->phy.type == e1000_phy_bm) 5537 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5538 5539 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5540 } 5541 5542 static void 5543 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5544 { 5545 struct e1000_hw *hw; 5546 uint32_t rctl; 5547 uint32_t ctrl_ext; 5548 uint32_t ctrl; 5549 uint32_t status; 5550 uint32_t txcw; 5551 uint16_t phydata; 5552 5553 hw = &Adapter->shared; 5554 5555 /* Disable Smart Power Down */ 5556 phy_spd_state(hw, B_FALSE); 5557 5558 switch (hw->mac.type) { 5559 case e1000_82571: 5560 case e1000_82572: 5561 switch (hw->phy.media_type) { 5562 case e1000_media_type_copper: 5563 /* Force link up (Must be done before the PHY writes) */ 5564 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5565 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5566 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5567 5568 rctl = E1000_READ_REG(hw, E1000_RCTL); 5569 rctl |= (E1000_RCTL_EN | 5570 E1000_RCTL_SBP | 5571 E1000_RCTL_UPE | 5572 E1000_RCTL_MPE | 5573 E1000_RCTL_LPE | 5574 E1000_RCTL_BAM); /* 0x803E */ 5575 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5576 5577 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5578 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5579 E1000_CTRL_EXT_SDP6_DATA | 5580 E1000_CTRL_EXT_SDP3_DATA | 5581 E1000_CTRL_EXT_SDP4_DIR | 5582 E1000_CTRL_EXT_SDP6_DIR | 5583 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5584 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5585 5586 /* 5587 * This sequence tunes the PHY's SDP and no customer 5588 * settable values. For background, see comments above 5589 * e1000g_set_internal_loopback(). 5590 */ 5591 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5592 msec_delay(10); 5593 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5594 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5595 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5596 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5597 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5598 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5599 5600 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5601 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5602 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5603 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5604 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5605 5606 msec_delay(50); 5607 break; 5608 case e1000_media_type_fiber: 5609 case e1000_media_type_internal_serdes: 5610 status = E1000_READ_REG(hw, E1000_STATUS); 5611 if (((status & E1000_STATUS_LU) == 0) || 5612 (hw->phy.media_type == 5613 e1000_media_type_internal_serdes)) { 5614 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5615 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5616 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5617 } 5618 5619 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5620 txcw = E1000_READ_REG(hw, E1000_TXCW); 5621 txcw &= ~((uint32_t)1 << 31); 5622 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5623 5624 /* 5625 * Write 0x410 to Serdes Control register 5626 * to enable Serdes analog loopback 5627 */ 5628 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5629 msec_delay(10); 5630 break; 5631 default: 5632 break; 5633 } 5634 break; 5635 case e1000_82574: 5636 case e1000_80003es2lan: 5637 case e1000_ich9lan: 5638 case e1000_ich10lan: 5639 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5640 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5641 phydata | (1 << 5)); 5642 Adapter->param_adv_autoneg = 1; 5643 Adapter->param_adv_1000fdx = 1; 5644 (void) e1000g_reset_link(Adapter); 5645 break; 5646 } 5647 } 5648 5649 static void 5650 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5651 { 5652 struct e1000_hw *hw; 5653 uint32_t ctrl; 5654 uint16_t phy_ctrl; 5655 5656 hw = &Adapter->shared; 5657 5658 /* Disable Smart Power Down */ 5659 phy_spd_state(hw, B_FALSE); 5660 5661 phy_ctrl = (MII_CR_FULL_DUPLEX | 5662 MII_CR_SPEED_100); 5663 5664 /* Force 100/FD, reset PHY */ 5665 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5666 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5667 msec_delay(10); 5668 5669 /* Force 100/FD */ 5670 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5671 phy_ctrl); /* 0x2100 */ 5672 msec_delay(10); 5673 5674 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5675 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5676 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5677 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5678 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5679 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5680 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5681 E1000_CTRL_FD); /* Force Duplex to FULL */ 5682 5683 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5684 } 5685 5686 static void 5687 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5688 { 5689 struct e1000_hw *hw; 5690 uint32_t ctrl; 5691 uint16_t phy_ctrl; 5692 5693 hw = &Adapter->shared; 5694 5695 /* Disable Smart Power Down */ 5696 phy_spd_state(hw, B_FALSE); 5697 5698 phy_ctrl = (MII_CR_FULL_DUPLEX | 5699 MII_CR_SPEED_10); 5700 5701 /* Force 10/FD, reset PHY */ 5702 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5703 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5704 msec_delay(10); 5705 5706 /* Force 10/FD */ 5707 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5708 phy_ctrl); /* 0x0100 */ 5709 msec_delay(10); 5710 5711 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5712 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5713 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5714 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5715 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5716 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5717 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5718 E1000_CTRL_FD); /* Force Duplex to FULL */ 5719 5720 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5721 } 5722 5723 #ifdef __sparc 5724 static boolean_t 5725 e1000g_find_mac_address(struct e1000g *Adapter) 5726 { 5727 struct e1000_hw *hw = &Adapter->shared; 5728 uchar_t *bytes; 5729 struct ether_addr sysaddr; 5730 uint_t nelts; 5731 int err; 5732 boolean_t found = B_FALSE; 5733 5734 /* 5735 * The "vendor's factory-set address" may already have 5736 * been extracted from the chip, but if the property 5737 * "local-mac-address" is set we use that instead. 5738 * 5739 * We check whether it looks like an array of 6 5740 * bytes (which it should, if OBP set it). If we can't 5741 * make sense of it this way, we'll ignore it. 5742 */ 5743 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5744 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5745 if (err == DDI_PROP_SUCCESS) { 5746 if (nelts == ETHERADDRL) { 5747 while (nelts--) 5748 hw->mac.addr[nelts] = bytes[nelts]; 5749 found = B_TRUE; 5750 } 5751 ddi_prop_free(bytes); 5752 } 5753 5754 /* 5755 * Look up the OBP property "local-mac-address?". If the user has set 5756 * 'local-mac-address? = false', use "the system address" instead. 5757 */ 5758 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5759 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5760 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5761 if (localetheraddr(NULL, &sysaddr) != 0) { 5762 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5763 found = B_TRUE; 5764 } 5765 } 5766 ddi_prop_free(bytes); 5767 } 5768 5769 /* 5770 * Finally(!), if there's a valid "mac-address" property (created 5771 * if we netbooted from this interface), we must use this instead 5772 * of any of the above to ensure that the NFS/install server doesn't 5773 * get confused by the address changing as Solaris takes over! 5774 */ 5775 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5776 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5777 if (err == DDI_PROP_SUCCESS) { 5778 if (nelts == ETHERADDRL) { 5779 while (nelts--) 5780 hw->mac.addr[nelts] = bytes[nelts]; 5781 found = B_TRUE; 5782 } 5783 ddi_prop_free(bytes); 5784 } 5785 5786 if (found) { 5787 bcopy(hw->mac.addr, hw->mac.perm_addr, 5788 ETHERADDRL); 5789 } 5790 5791 return (found); 5792 } 5793 #endif 5794 5795 static int 5796 e1000g_add_intrs(struct e1000g *Adapter) 5797 { 5798 dev_info_t *devinfo; 5799 int intr_types; 5800 int rc; 5801 5802 devinfo = Adapter->dip; 5803 5804 /* Get supported interrupt types */ 5805 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5806 5807 if (rc != DDI_SUCCESS) { 5808 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5809 "Get supported interrupt types failed: %d\n", rc); 5810 return (DDI_FAILURE); 5811 } 5812 5813 /* 5814 * Based on Intel Technical Advisory document (TA-160), there are some 5815 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5816 * that it supports MSI, but in fact has problems. 5817 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5818 * PCI/PCI-X NICs. 5819 */ 5820 if (Adapter->shared.mac.type < e1000_82571) 5821 Adapter->msi_enable = B_FALSE; 5822 5823 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5824 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5825 5826 if (rc != DDI_SUCCESS) { 5827 /* EMPTY */ 5828 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5829 "Add MSI failed, trying Legacy interrupts\n"); 5830 } else { 5831 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5832 } 5833 } 5834 5835 if ((Adapter->intr_type == 0) && 5836 (intr_types & DDI_INTR_TYPE_FIXED)) { 5837 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5838 5839 if (rc != DDI_SUCCESS) { 5840 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5841 "Add Legacy interrupts failed\n"); 5842 return (DDI_FAILURE); 5843 } 5844 5845 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5846 } 5847 5848 if (Adapter->intr_type == 0) { 5849 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5850 "No interrupts registered\n"); 5851 return (DDI_FAILURE); 5852 } 5853 5854 return (DDI_SUCCESS); 5855 } 5856 5857 /* 5858 * e1000g_intr_add() handles MSI/Legacy interrupts 5859 */ 5860 static int 5861 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5862 { 5863 dev_info_t *devinfo; 5864 int count, avail, actual; 5865 int x, y, rc, inum = 0; 5866 int flag; 5867 ddi_intr_handler_t *intr_handler; 5868 5869 devinfo = Adapter->dip; 5870 5871 /* get number of interrupts */ 5872 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5873 if ((rc != DDI_SUCCESS) || (count == 0)) { 5874 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5875 "Get interrupt number failed. Return: %d, count: %d\n", 5876 rc, count); 5877 return (DDI_FAILURE); 5878 } 5879 5880 /* get number of available interrupts */ 5881 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5882 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5883 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5884 "Get interrupt available number failed. " 5885 "Return: %d, available: %d\n", rc, avail); 5886 return (DDI_FAILURE); 5887 } 5888 5889 if (avail < count) { 5890 /* EMPTY */ 5891 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5892 "Interrupts count: %d, available: %d\n", 5893 count, avail); 5894 } 5895 5896 /* Allocate an array of interrupt handles */ 5897 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5898 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5899 5900 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5901 flag = DDI_INTR_ALLOC_NORMAL; 5902 5903 /* call ddi_intr_alloc() */ 5904 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5905 count, &actual, flag); 5906 5907 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5908 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5909 "Allocate interrupts failed: %d\n", rc); 5910 5911 kmem_free(Adapter->htable, Adapter->intr_size); 5912 return (DDI_FAILURE); 5913 } 5914 5915 if (actual < count) { 5916 /* EMPTY */ 5917 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5918 "Interrupts requested: %d, received: %d\n", 5919 count, actual); 5920 } 5921 5922 Adapter->intr_cnt = actual; 5923 5924 /* Get priority for first msi, assume remaining are all the same */ 5925 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5926 5927 if (rc != DDI_SUCCESS) { 5928 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5929 "Get interrupt priority failed: %d\n", rc); 5930 5931 /* Free already allocated intr */ 5932 for (y = 0; y < actual; y++) 5933 (void) ddi_intr_free(Adapter->htable[y]); 5934 5935 kmem_free(Adapter->htable, Adapter->intr_size); 5936 return (DDI_FAILURE); 5937 } 5938 5939 /* 5940 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5941 * use the interrupt service routine e1000g_intr_pciexpress() 5942 * to avoid interrupt stealing when sharing interrupt with other 5943 * devices. 5944 */ 5945 if (Adapter->shared.mac.type < e1000_82571) 5946 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5947 else 5948 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5949 5950 /* Call ddi_intr_add_handler() */ 5951 for (x = 0; x < actual; x++) { 5952 rc = ddi_intr_add_handler(Adapter->htable[x], 5953 intr_handler, (caddr_t)Adapter, NULL); 5954 5955 if (rc != DDI_SUCCESS) { 5956 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5957 "Add interrupt handler failed: %d\n", rc); 5958 5959 /* Remove already added handler */ 5960 for (y = 0; y < x; y++) 5961 (void) ddi_intr_remove_handler( 5962 Adapter->htable[y]); 5963 5964 /* Free already allocated intr */ 5965 for (y = 0; y < actual; y++) 5966 (void) ddi_intr_free(Adapter->htable[y]); 5967 5968 kmem_free(Adapter->htable, Adapter->intr_size); 5969 return (DDI_FAILURE); 5970 } 5971 } 5972 5973 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5974 5975 if (rc != DDI_SUCCESS) { 5976 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5977 "Get interrupt cap failed: %d\n", rc); 5978 5979 /* Free already allocated intr */ 5980 for (y = 0; y < actual; y++) { 5981 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5982 (void) ddi_intr_free(Adapter->htable[y]); 5983 } 5984 5985 kmem_free(Adapter->htable, Adapter->intr_size); 5986 return (DDI_FAILURE); 5987 } 5988 5989 return (DDI_SUCCESS); 5990 } 5991 5992 static int 5993 e1000g_rem_intrs(struct e1000g *Adapter) 5994 { 5995 int x; 5996 int rc; 5997 5998 for (x = 0; x < Adapter->intr_cnt; x++) { 5999 rc = ddi_intr_remove_handler(Adapter->htable[x]); 6000 if (rc != DDI_SUCCESS) { 6001 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6002 "Remove intr handler failed: %d\n", rc); 6003 return (DDI_FAILURE); 6004 } 6005 6006 rc = ddi_intr_free(Adapter->htable[x]); 6007 if (rc != DDI_SUCCESS) { 6008 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6009 "Free intr failed: %d\n", rc); 6010 return (DDI_FAILURE); 6011 } 6012 } 6013 6014 kmem_free(Adapter->htable, Adapter->intr_size); 6015 6016 return (DDI_SUCCESS); 6017 } 6018 6019 static int 6020 e1000g_enable_intrs(struct e1000g *Adapter) 6021 { 6022 int x; 6023 int rc; 6024 6025 /* Enable interrupts */ 6026 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6027 /* Call ddi_intr_block_enable() for MSI */ 6028 rc = ddi_intr_block_enable(Adapter->htable, 6029 Adapter->intr_cnt); 6030 if (rc != DDI_SUCCESS) { 6031 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6032 "Enable block intr failed: %d\n", rc); 6033 return (DDI_FAILURE); 6034 } 6035 } else { 6036 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 6037 for (x = 0; x < Adapter->intr_cnt; x++) { 6038 rc = ddi_intr_enable(Adapter->htable[x]); 6039 if (rc != DDI_SUCCESS) { 6040 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6041 "Enable intr failed: %d\n", rc); 6042 return (DDI_FAILURE); 6043 } 6044 } 6045 } 6046 6047 return (DDI_SUCCESS); 6048 } 6049 6050 static int 6051 e1000g_disable_intrs(struct e1000g *Adapter) 6052 { 6053 int x; 6054 int rc; 6055 6056 /* Disable all interrupts */ 6057 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6058 rc = ddi_intr_block_disable(Adapter->htable, 6059 Adapter->intr_cnt); 6060 if (rc != DDI_SUCCESS) { 6061 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6062 "Disable block intr failed: %d\n", rc); 6063 return (DDI_FAILURE); 6064 } 6065 } else { 6066 for (x = 0; x < Adapter->intr_cnt; x++) { 6067 rc = ddi_intr_disable(Adapter->htable[x]); 6068 if (rc != DDI_SUCCESS) { 6069 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6070 "Disable intr failed: %d\n", rc); 6071 return (DDI_FAILURE); 6072 } 6073 } 6074 } 6075 6076 return (DDI_SUCCESS); 6077 } 6078 6079 /* 6080 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 6081 */ 6082 static void 6083 e1000g_get_phy_state(struct e1000g *Adapter) 6084 { 6085 struct e1000_hw *hw = &Adapter->shared; 6086 6087 if (hw->phy.media_type == e1000_media_type_copper) { 6088 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 6089 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 6090 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 6091 &Adapter->phy_an_adv); 6092 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 6093 &Adapter->phy_an_exp); 6094 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 6095 &Adapter->phy_ext_status); 6096 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 6097 &Adapter->phy_1000t_ctrl); 6098 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 6099 &Adapter->phy_1000t_status); 6100 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 6101 &Adapter->phy_lp_able); 6102 6103 Adapter->param_autoneg_cap = 6104 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 6105 Adapter->param_pause_cap = 6106 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6107 Adapter->param_asym_pause_cap = 6108 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6109 Adapter->param_1000fdx_cap = 6110 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 6111 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 6112 Adapter->param_1000hdx_cap = 6113 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 6114 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 6115 Adapter->param_100t4_cap = 6116 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 6117 Adapter->param_100fdx_cap = 6118 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6119 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 6120 Adapter->param_100hdx_cap = 6121 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6122 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6123 Adapter->param_10fdx_cap = 6124 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6125 Adapter->param_10hdx_cap = 6126 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6127 6128 Adapter->param_adv_autoneg = hw->mac.autoneg; 6129 Adapter->param_adv_pause = 6130 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6131 Adapter->param_adv_asym_pause = 6132 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6133 Adapter->param_adv_1000hdx = 6134 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 6135 Adapter->param_adv_100t4 = 6136 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 6137 if (Adapter->param_adv_autoneg == 1) { 6138 Adapter->param_adv_1000fdx = 6139 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 6140 ? 1 : 0; 6141 Adapter->param_adv_100fdx = 6142 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 6143 ? 1 : 0; 6144 Adapter->param_adv_100hdx = 6145 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 6146 ? 1 : 0; 6147 Adapter->param_adv_10fdx = 6148 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 6149 Adapter->param_adv_10hdx = 6150 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 6151 } 6152 6153 Adapter->param_lp_autoneg = 6154 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 6155 Adapter->param_lp_pause = 6156 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 6157 Adapter->param_lp_asym_pause = 6158 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 6159 Adapter->param_lp_1000fdx = 6160 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 6161 Adapter->param_lp_1000hdx = 6162 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 6163 Adapter->param_lp_100t4 = 6164 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 6165 Adapter->param_lp_100fdx = 6166 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 6167 Adapter->param_lp_100hdx = 6168 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 6169 Adapter->param_lp_10fdx = 6170 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 6171 Adapter->param_lp_10hdx = 6172 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 6173 } else { 6174 /* 6175 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 6176 * it can only work with 1Gig Full Duplex Link Partner. 6177 */ 6178 Adapter->param_autoneg_cap = 0; 6179 Adapter->param_pause_cap = 1; 6180 Adapter->param_asym_pause_cap = 1; 6181 Adapter->param_1000fdx_cap = 1; 6182 Adapter->param_1000hdx_cap = 0; 6183 Adapter->param_100t4_cap = 0; 6184 Adapter->param_100fdx_cap = 0; 6185 Adapter->param_100hdx_cap = 0; 6186 Adapter->param_10fdx_cap = 0; 6187 Adapter->param_10hdx_cap = 0; 6188 6189 Adapter->param_adv_autoneg = 0; 6190 Adapter->param_adv_pause = 1; 6191 Adapter->param_adv_asym_pause = 1; 6192 Adapter->param_adv_1000fdx = 1; 6193 Adapter->param_adv_1000hdx = 0; 6194 Adapter->param_adv_100t4 = 0; 6195 Adapter->param_adv_100fdx = 0; 6196 Adapter->param_adv_100hdx = 0; 6197 Adapter->param_adv_10fdx = 0; 6198 Adapter->param_adv_10hdx = 0; 6199 6200 Adapter->param_lp_autoneg = 0; 6201 Adapter->param_lp_pause = 0; 6202 Adapter->param_lp_asym_pause = 0; 6203 Adapter->param_lp_1000fdx = 0; 6204 Adapter->param_lp_1000hdx = 0; 6205 Adapter->param_lp_100t4 = 0; 6206 Adapter->param_lp_100fdx = 0; 6207 Adapter->param_lp_100hdx = 0; 6208 Adapter->param_lp_10fdx = 0; 6209 Adapter->param_lp_10hdx = 0; 6210 } 6211 } 6212 6213 /* 6214 * FMA support 6215 */ 6216 6217 int 6218 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6219 { 6220 ddi_fm_error_t de; 6221 6222 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6223 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6224 return (de.fme_status); 6225 } 6226 6227 int 6228 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6229 { 6230 ddi_fm_error_t de; 6231 6232 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6233 return (de.fme_status); 6234 } 6235 6236 /* 6237 * The IO fault service error handling callback function 6238 */ 6239 /* ARGSUSED2 */ 6240 static int 6241 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6242 { 6243 /* 6244 * as the driver can always deal with an error in any dma or 6245 * access handle, we can just return the fme_status value. 6246 */ 6247 pci_ereport_post(dip, err, NULL); 6248 return (err->fme_status); 6249 } 6250 6251 static void 6252 e1000g_fm_init(struct e1000g *Adapter) 6253 { 6254 ddi_iblock_cookie_t iblk; 6255 int fma_dma_flag; 6256 6257 /* Only register with IO Fault Services if we have some capability */ 6258 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6259 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6260 } else { 6261 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6262 } 6263 6264 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6265 fma_dma_flag = 1; 6266 } else { 6267 fma_dma_flag = 0; 6268 } 6269 6270 (void) e1000g_set_fma_flags(fma_dma_flag); 6271 6272 if (Adapter->fm_capabilities) { 6273 6274 /* Register capabilities with IO Fault Services */ 6275 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6276 6277 /* 6278 * Initialize pci ereport capabilities if ereport capable 6279 */ 6280 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6281 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6282 pci_ereport_setup(Adapter->dip); 6283 6284 /* 6285 * Register error callback if error callback capable 6286 */ 6287 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6288 ddi_fm_handler_register(Adapter->dip, 6289 e1000g_fm_error_cb, (void*) Adapter); 6290 } 6291 } 6292 6293 static void 6294 e1000g_fm_fini(struct e1000g *Adapter) 6295 { 6296 /* Only unregister FMA capabilities if we registered some */ 6297 if (Adapter->fm_capabilities) { 6298 6299 /* 6300 * Release any resources allocated by pci_ereport_setup() 6301 */ 6302 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6303 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6304 pci_ereport_teardown(Adapter->dip); 6305 6306 /* 6307 * Un-register error callback if error callback capable 6308 */ 6309 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6310 ddi_fm_handler_unregister(Adapter->dip); 6311 6312 /* Unregister from IO Fault Services */ 6313 mutex_enter(&e1000g_rx_detach_lock); 6314 ddi_fm_fini(Adapter->dip); 6315 if (Adapter->priv_dip != NULL) { 6316 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6317 } 6318 mutex_exit(&e1000g_rx_detach_lock); 6319 } 6320 } 6321 6322 void 6323 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6324 { 6325 uint64_t ena; 6326 char buf[FM_MAX_CLASS]; 6327 6328 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6329 ena = fm_ena_generate(0, FM_ENA_FMT1); 6330 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6331 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6332 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6333 } 6334 } 6335 6336 /* 6337 * quiesce(9E) entry point. 6338 * 6339 * This function is called when the system is single-threaded at high 6340 * PIL with preemption disabled. Therefore, this function must not be 6341 * blocked. 6342 * 6343 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6344 * DDI_FAILURE indicates an error condition and should almost never happen. 6345 */ 6346 static int 6347 e1000g_quiesce(dev_info_t *devinfo) 6348 { 6349 struct e1000g *Adapter; 6350 6351 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6352 6353 if (Adapter == NULL) 6354 return (DDI_FAILURE); 6355 6356 e1000g_clear_all_interrupts(Adapter); 6357 6358 (void) e1000_reset_hw(&Adapter->shared); 6359 6360 /* Setup our HW Tx Head & Tail descriptor pointers */ 6361 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6362 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6363 6364 /* Setup our HW Rx Head & Tail descriptor pointers */ 6365 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6366 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6367 6368 return (DDI_SUCCESS); 6369 } 6370 6371 /* 6372 * synchronize the adv* and en* parameters. 6373 * 6374 * See comments in <sys/dld.h> for details of the *_en_* 6375 * parameters. The usage of ndd for setting adv parameters will 6376 * synchronize all the en parameters with the e1000g parameters, 6377 * implicitly disabling any settings made via dladm. 6378 */ 6379 static void 6380 e1000g_param_sync(struct e1000g *Adapter) 6381 { 6382 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6383 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6384 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6385 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6386 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6387 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6388 } 6389 6390 /* 6391 * e1000g_get_driver_control - tell manageability firmware that the driver 6392 * has control. 6393 */ 6394 static void 6395 e1000g_get_driver_control(struct e1000_hw *hw) 6396 { 6397 uint32_t ctrl_ext; 6398 uint32_t swsm; 6399 6400 /* tell manageability firmware the driver has taken over */ 6401 switch (hw->mac.type) { 6402 case e1000_82573: 6403 swsm = E1000_READ_REG(hw, E1000_SWSM); 6404 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6405 break; 6406 case e1000_82571: 6407 case e1000_82572: 6408 case e1000_82574: 6409 case e1000_80003es2lan: 6410 case e1000_ich8lan: 6411 case e1000_ich9lan: 6412 case e1000_ich10lan: 6413 case e1000_pchlan: 6414 case e1000_pch2lan: 6415 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6416 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6417 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6418 break; 6419 default: 6420 /* no manageability firmware: do nothing */ 6421 break; 6422 } 6423 } 6424 6425 /* 6426 * e1000g_release_driver_control - tell manageability firmware that the driver 6427 * has released control. 6428 */ 6429 static void 6430 e1000g_release_driver_control(struct e1000_hw *hw) 6431 { 6432 uint32_t ctrl_ext; 6433 uint32_t swsm; 6434 6435 /* tell manageability firmware the driver has released control */ 6436 switch (hw->mac.type) { 6437 case e1000_82573: 6438 swsm = E1000_READ_REG(hw, E1000_SWSM); 6439 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6440 break; 6441 case e1000_82571: 6442 case e1000_82572: 6443 case e1000_82574: 6444 case e1000_80003es2lan: 6445 case e1000_ich8lan: 6446 case e1000_ich9lan: 6447 case e1000_ich10lan: 6448 case e1000_pchlan: 6449 case e1000_pch2lan: 6450 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6451 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6452 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6453 break; 6454 default: 6455 /* no manageability firmware: do nothing */ 6456 break; 6457 } 6458 } 6459 6460 /* 6461 * Restore e1000g promiscuous mode. 6462 */ 6463 static void 6464 e1000g_restore_promisc(struct e1000g *Adapter) 6465 { 6466 if (Adapter->e1000g_promisc) { 6467 uint32_t rctl; 6468 6469 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6470 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6471 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6472 } 6473 } 6474