1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include "e1000g_sw.h" 47 #include "e1000g_debug.h" 48 49 static char ident[] = "Intel PRO/1000 Ethernet 5.2.4"; 50 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 51 static char e1000g_version[] = "Driver Ver. 5.2.4"; 52 53 /* 54 * Proto types for DDI entry points 55 */ 56 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 57 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 58 59 /* 60 * init and intr routines prototype 61 */ 62 static int e1000g_resume(dev_info_t *); 63 static int e1000g_suspend(dev_info_t *); 64 static uint_t e1000g_intr_pciexpress(caddr_t); 65 static uint_t e1000g_intr(caddr_t); 66 static void e1000g_intr_work(struct e1000g *, uint32_t); 67 #pragma inline(e1000g_intr_work) 68 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 69 #pragma inline(e1000g_get_itr) 70 static int e1000g_init(struct e1000g *); 71 static int e1000g_start(struct e1000g *, boolean_t); 72 static void e1000g_stop(struct e1000g *, boolean_t); 73 static int e1000g_m_start(void *); 74 static void e1000g_m_stop(void *); 75 static int e1000g_m_promisc(void *, boolean_t); 76 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 77 static int e1000g_m_unicst(void *, const uint8_t *); 78 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 79 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 80 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 81 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 82 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 83 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static int e1000g_register_mac(struct e1000g *); 90 static boolean_t e1000g_rx_drain(struct e1000g *); 91 static boolean_t e1000g_tx_drain(struct e1000g *); 92 static void e1000g_init_unicst(struct e1000g *); 93 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 94 95 /* 96 * Local routines 97 */ 98 static void e1000g_tx_clean(struct e1000g *); 99 static void e1000g_rx_clean(struct e1000g *); 100 static void e1000g_link_timer(void *); 101 static void e1000g_local_timer(void *); 102 static boolean_t e1000g_link_check(struct e1000g *); 103 static boolean_t e1000g_stall_check(struct e1000g *); 104 static void e1000g_smartspeed(struct e1000g *); 105 static void e1000g_get_conf(struct e1000g *); 106 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 107 static void enable_watchdog_timer(struct e1000g *); 108 static void disable_watchdog_timer(struct e1000g *); 109 static void start_watchdog_timer(struct e1000g *); 110 static void restart_watchdog_timer(struct e1000g *); 111 static void stop_watchdog_timer(struct e1000g *); 112 static void stop_link_timer(struct e1000g *); 113 static void stop_82547_timer(e1000g_tx_ring_t *); 114 static void e1000g_force_speed_duplex(struct e1000g *); 115 static void e1000g_get_max_frame_size(struct e1000g *); 116 static boolean_t is_valid_mac_addr(uint8_t *); 117 static void e1000g_unattach(dev_info_t *, struct e1000g *); 118 #ifdef E1000G_DEBUG 119 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 120 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 121 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 122 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 123 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 124 struct iocblk *, mblk_t *); 125 #endif 126 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 127 struct iocblk *, mblk_t *); 128 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 129 static void e1000g_set_internal_loopback(struct e1000g *); 130 static void e1000g_set_external_loopback_1000(struct e1000g *); 131 static void e1000g_set_external_loopback_100(struct e1000g *); 132 static void e1000g_set_external_loopback_10(struct e1000g *); 133 static int e1000g_add_intrs(struct e1000g *); 134 static int e1000g_intr_add(struct e1000g *, int); 135 static int e1000g_rem_intrs(struct e1000g *); 136 static int e1000g_enable_intrs(struct e1000g *); 137 static int e1000g_disable_intrs(struct e1000g *); 138 static boolean_t e1000g_link_up(struct e1000g *); 139 #ifdef __sparc 140 static boolean_t e1000g_find_mac_address(struct e1000g *); 141 #endif 142 static void e1000g_get_phy_state(struct e1000g *); 143 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 144 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 145 const void *impl_data); 146 static void e1000g_fm_init(struct e1000g *Adapter); 147 static void e1000g_fm_fini(struct e1000g *Adapter); 148 149 static struct cb_ops cb_ws_ops = { 150 nulldev, /* cb_open */ 151 nulldev, /* cb_close */ 152 nodev, /* cb_strategy */ 153 nodev, /* cb_print */ 154 nodev, /* cb_dump */ 155 nodev, /* cb_read */ 156 nodev, /* cb_write */ 157 nodev, /* cb_ioctl */ 158 nodev, /* cb_devmap */ 159 nodev, /* cb_mmap */ 160 nodev, /* cb_segmap */ 161 nochpoll, /* cb_chpoll */ 162 ddi_prop_op, /* cb_prop_op */ 163 NULL, /* cb_stream */ 164 D_MP | D_HOTPLUG, /* cb_flag */ 165 CB_REV, /* cb_rev */ 166 nodev, /* cb_aread */ 167 nodev /* cb_awrite */ 168 }; 169 170 static struct dev_ops ws_ops = { 171 DEVO_REV, /* devo_rev */ 172 0, /* devo_refcnt */ 173 NULL, /* devo_getinfo */ 174 nulldev, /* devo_identify */ 175 nulldev, /* devo_probe */ 176 e1000g_attach, /* devo_attach */ 177 e1000g_detach, /* devo_detach */ 178 nodev, /* devo_reset */ 179 &cb_ws_ops, /* devo_cb_ops */ 180 NULL, /* devo_bus_ops */ 181 ddi_power /* devo_power */ 182 }; 183 184 static struct modldrv modldrv = { 185 &mod_driverops, /* Type of module. This one is a driver */ 186 ident, /* Discription string */ 187 &ws_ops, /* driver ops */ 188 }; 189 190 static struct modlinkage modlinkage = { 191 MODREV_1, &modldrv, NULL 192 }; 193 194 /* Access attributes for register mapping */ 195 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 196 DDI_DEVICE_ATTR_V0, 197 DDI_STRUCTURE_LE_ACC, 198 DDI_STRICTORDER_ACC, 199 DDI_FLAGERR_ACC 200 }; 201 202 #define E1000G_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 203 204 static mac_callbacks_t e1000g_m_callbacks = { 205 E1000G_M_CALLBACK_FLAGS, 206 e1000g_m_stat, 207 e1000g_m_start, 208 e1000g_m_stop, 209 e1000g_m_promisc, 210 e1000g_m_multicst, 211 e1000g_m_unicst, 212 e1000g_m_tx, 213 NULL, 214 e1000g_m_ioctl, 215 e1000g_m_getcapab 216 }; 217 218 /* 219 * Global variables 220 */ 221 uint32_t e1000g_mblks_pending = 0; 222 /* 223 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 224 * Here we maintain a private dev_info list if e1000g_force_detach is 225 * enabled. If we force the driver to detach while there are still some 226 * rx buffers retained in the upper layer, we have to keep a copy of the 227 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 228 * structure will be freed after the driver is detached. However when we 229 * finally free those rx buffers released by the upper layer, we need to 230 * refer to the dev_info to free the dma buffers. So we save a copy of 231 * the dev_info for this purpose. On x86 platform, we assume this copy 232 * of dev_info is always valid, but on SPARC platform, it could be invalid 233 * after the system board level DR operation. For this reason, the global 234 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 235 */ 236 #ifdef __sparc 237 boolean_t e1000g_force_detach = B_FALSE; 238 #else 239 boolean_t e1000g_force_detach = B_TRUE; 240 #endif 241 private_devi_list_t *e1000g_private_devi_list = NULL; 242 243 /* 244 * The rwlock is defined to protect the whole processing of rx recycling 245 * and the rx packets release in detach processing to make them mutually 246 * exclusive. 247 * The rx recycling processes different rx packets in different threads, 248 * so it will be protected with RW_READER and it won't block any other rx 249 * recycling threads. 250 * While the detach processing will be protected with RW_WRITER to make 251 * it mutually exclusive with the rx recycling. 252 */ 253 krwlock_t e1000g_rx_detach_lock; 254 /* 255 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 256 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 257 * If there are many e1000g instances, the system may run out of DVMA 258 * resources during the initialization of the instances, then the flag will 259 * be changed to "USE_DMA". Because different e1000g instances are initialized 260 * in parallel, we need to use this lock to protect the flag. 261 */ 262 krwlock_t e1000g_dma_type_lock; 263 264 265 /* 266 * Loadable module configuration entry points for the driver 267 */ 268 269 /* 270 * _init - module initialization 271 */ 272 int 273 _init(void) 274 { 275 int status; 276 277 mac_init_ops(&ws_ops, WSNAME); 278 status = mod_install(&modlinkage); 279 if (status != DDI_SUCCESS) 280 mac_fini_ops(&ws_ops); 281 else { 282 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 283 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 284 } 285 286 return (status); 287 } 288 289 /* 290 * _fini - module finalization 291 */ 292 int 293 _fini(void) 294 { 295 int status; 296 297 rw_enter(&e1000g_rx_detach_lock, RW_READER); 298 if (e1000g_mblks_pending != 0) { 299 rw_exit(&e1000g_rx_detach_lock); 300 return (EBUSY); 301 } 302 rw_exit(&e1000g_rx_detach_lock); 303 304 status = mod_remove(&modlinkage); 305 if (status == DDI_SUCCESS) { 306 mac_fini_ops(&ws_ops); 307 308 if (e1000g_force_detach) { 309 private_devi_list_t *devi_node; 310 311 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 312 while (e1000g_private_devi_list != NULL) { 313 devi_node = e1000g_private_devi_list; 314 e1000g_private_devi_list = 315 e1000g_private_devi_list->next; 316 317 kmem_free(devi_node->priv_dip, 318 sizeof (struct dev_info)); 319 kmem_free(devi_node, 320 sizeof (private_devi_list_t)); 321 } 322 rw_exit(&e1000g_rx_detach_lock); 323 } 324 325 rw_destroy(&e1000g_rx_detach_lock); 326 rw_destroy(&e1000g_dma_type_lock); 327 } 328 329 return (status); 330 } 331 332 /* 333 * _info - module information 334 */ 335 int 336 _info(struct modinfo *modinfop) 337 { 338 return (mod_info(&modlinkage, modinfop)); 339 } 340 341 /* 342 * e1000g_attach - driver attach 343 * 344 * This function is the device-specific initialization entry 345 * point. This entry point is required and must be written. 346 * The DDI_ATTACH command must be provided in the attach entry 347 * point. When attach() is called with cmd set to DDI_ATTACH, 348 * all normal kernel services (such as kmem_alloc(9F)) are 349 * available for use by the driver. 350 * 351 * The attach() function will be called once for each instance 352 * of the device on the system with cmd set to DDI_ATTACH. 353 * Until attach() succeeds, the only driver entry points which 354 * may be called are open(9E) and getinfo(9E). 355 */ 356 static int 357 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 358 { 359 struct e1000g *Adapter; 360 struct e1000_hw *hw; 361 struct e1000g_osdep *osdep; 362 int instance; 363 364 switch (cmd) { 365 default: 366 e1000g_log(NULL, CE_WARN, 367 "Unsupported command send to e1000g_attach... "); 368 return (DDI_FAILURE); 369 370 case DDI_RESUME: 371 return (e1000g_resume(devinfo)); 372 373 case DDI_ATTACH: 374 break; 375 } 376 377 /* 378 * get device instance number 379 */ 380 instance = ddi_get_instance(devinfo); 381 382 /* 383 * Allocate soft data structure 384 */ 385 Adapter = 386 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 387 388 Adapter->dip = devinfo; 389 Adapter->instance = instance; 390 Adapter->tx_ring->adapter = Adapter; 391 Adapter->rx_ring->adapter = Adapter; 392 393 hw = &Adapter->shared; 394 osdep = &Adapter->osdep; 395 hw->back = osdep; 396 osdep->adapter = Adapter; 397 398 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 399 400 /* 401 * Initialize for fma support 402 */ 403 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 404 0, 0x0f, 405 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 406 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 407 e1000g_fm_init(Adapter); 408 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 409 410 /* 411 * PCI Configure 412 */ 413 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 414 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 415 goto attach_fail; 416 } 417 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 418 419 /* 420 * Setup hardware 421 */ 422 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 423 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 424 goto attach_fail; 425 } 426 427 /* 428 * Map in the device registers. 429 */ 430 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 431 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 432 goto attach_fail; 433 } 434 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 435 436 /* 437 * Initialize driver parameters 438 */ 439 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 440 goto attach_fail; 441 } 442 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 443 444 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 445 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 446 goto attach_fail; 447 } 448 449 /* 450 * Initialize interrupts 451 */ 452 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 453 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 454 goto attach_fail; 455 } 456 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 457 458 /* 459 * Initialize mutex's for this device. 460 * Do this before enabling the interrupt handler and 461 * register the softint to avoid the condition where 462 * interrupt handler can try using uninitialized mutex 463 */ 464 e1000g_init_locks(Adapter); 465 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 466 467 /* 468 * Initialize Driver Counters 469 */ 470 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 471 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 472 goto attach_fail; 473 } 474 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 475 476 /* 477 * Initialize chip hardware and software structures 478 */ 479 if (e1000g_init(Adapter) != DDI_SUCCESS) { 480 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 481 goto attach_fail; 482 } 483 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 484 485 /* 486 * Initialize NDD parameters 487 */ 488 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 489 e1000g_log(Adapter, CE_WARN, "Init ndd failed"); 490 goto attach_fail; 491 } 492 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 493 494 /* 495 * Register the driver to the MAC 496 */ 497 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 498 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 499 goto attach_fail; 500 } 501 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 502 503 /* 504 * Now that mutex locks are initialized, and the chip is also 505 * initialized, enable interrupts. 506 */ 507 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 508 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 509 goto attach_fail; 510 } 511 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 512 513 /* 514 * If e1000g_force_detach is enabled, in global private dip list, 515 * we will create a new entry, which maintains the priv_dip for DR 516 * supports after driver detached. 517 */ 518 if (e1000g_force_detach) { 519 private_devi_list_t *devi_node; 520 521 Adapter->priv_dip = 522 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 523 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 524 sizeof (struct dev_info)); 525 526 devi_node = 527 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 528 529 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 530 devi_node->priv_dip = Adapter->priv_dip; 531 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 532 devi_node->next = e1000g_private_devi_list; 533 e1000g_private_devi_list = devi_node; 534 rw_exit(&e1000g_rx_detach_lock); 535 } 536 537 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 538 539 return (DDI_SUCCESS); 540 541 attach_fail: 542 e1000g_unattach(devinfo, Adapter); 543 return (DDI_FAILURE); 544 } 545 546 static int 547 e1000g_register_mac(struct e1000g *Adapter) 548 { 549 struct e1000_hw *hw = &Adapter->shared; 550 mac_register_t *mac; 551 int err; 552 553 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 554 return (DDI_FAILURE); 555 556 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 557 mac->m_driver = Adapter; 558 mac->m_dip = Adapter->dip; 559 mac->m_src_addr = hw->mac.addr; 560 mac->m_callbacks = &e1000g_m_callbacks; 561 mac->m_min_sdu = 0; 562 mac->m_max_sdu = 563 (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) ? 564 hw->mac.max_frame_size - 256 : 565 (hw->mac.max_frame_size != ETHERMAX) ? 566 hw->mac.max_frame_size - 24 : ETHERMTU; 567 568 err = mac_register(mac, &Adapter->mh); 569 mac_free(mac); 570 571 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 572 } 573 574 static int 575 e1000g_identify_hardware(struct e1000g *Adapter) 576 { 577 struct e1000_hw *hw = &Adapter->shared; 578 struct e1000g_osdep *osdep = &Adapter->osdep; 579 580 /* Get the device id */ 581 hw->vendor_id = 582 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 583 hw->device_id = 584 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 585 hw->revision_id = 586 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 587 hw->subsystem_device_id = 588 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 589 hw->subsystem_vendor_id = 590 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 591 592 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 593 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 594 "MAC type could not be set properly."); 595 return (DDI_FAILURE); 596 } 597 598 return (DDI_SUCCESS); 599 } 600 601 static int 602 e1000g_regs_map(struct e1000g *Adapter) 603 { 604 dev_info_t *devinfo = Adapter->dip; 605 struct e1000_hw *hw = &Adapter->shared; 606 struct e1000g_osdep *osdep = &Adapter->osdep; 607 off_t mem_size; 608 609 /* 610 * first get the size of device register to be mapped. The 611 * second parameter is the register we are interested. I our 612 * wiseman 0 is for config registers and 1 is for memory mapped 613 * registers Mem size should have memory mapped region size 614 */ 615 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 616 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 617 "ddi_dev_regsize for registers failed"); 618 return (DDI_FAILURE); 619 } 620 621 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 622 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 623 &osdep->reg_handle)) != DDI_SUCCESS) { 624 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 625 "ddi_regs_map_setup for registers failed"); 626 goto regs_map_fail; 627 } 628 629 /* ICH needs to map flash memory */ 630 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 631 /* get flash size */ 632 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 633 &mem_size) != DDI_SUCCESS) { 634 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 635 "ddi_dev_regsize for ICH flash failed"); 636 goto regs_map_fail; 637 } 638 639 /* map flash in */ 640 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 641 (caddr_t *)&hw->flash_address, 0, 642 mem_size, &e1000g_regs_acc_attr, 643 &osdep->ich_flash_handle) != DDI_SUCCESS) { 644 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 645 "ddi_regs_map_setup for ICH flash failed"); 646 goto regs_map_fail; 647 } 648 } 649 650 return (DDI_SUCCESS); 651 652 regs_map_fail: 653 if (osdep->reg_handle != NULL) 654 ddi_regs_map_free(&osdep->reg_handle); 655 656 return (DDI_FAILURE); 657 } 658 659 static int 660 e1000g_set_driver_params(struct e1000g *Adapter) 661 { 662 struct e1000_hw *hw; 663 e1000g_tx_ring_t *tx_ring; 664 uint32_t mem_bar, io_bar, bar64; 665 #ifdef __sparc 666 dev_info_t *devinfo = Adapter->dip; 667 ulong_t iommu_pagesize; 668 #endif 669 670 hw = &Adapter->shared; 671 672 /* Set MAC type and initialize hardware functions */ 673 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 674 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 675 "Could not setup hardware functions"); 676 return (DDI_FAILURE); 677 } 678 679 /* Get bus information */ 680 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 681 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 682 "Could not get bus information"); 683 return (DDI_FAILURE); 684 } 685 686 /* get mem_base addr */ 687 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 688 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 689 690 /* get io_base addr */ 691 if (hw->mac.type >= e1000_82544) { 692 if (bar64) { 693 /* IO BAR is different for 64 bit BAR mode */ 694 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 695 PCI_CONF_BASE4); 696 } else { 697 /* normal 32-bit BAR mode */ 698 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 699 PCI_CONF_BASE2); 700 } 701 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 702 } else { 703 /* no I/O access for adapters prior to 82544 */ 704 hw->io_base = 0x0; 705 } 706 707 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 708 709 hw->mac.autoneg_failed = B_TRUE; 710 711 /* Set the wait_for_link flag to B_FALSE */ 712 hw->phy.wait_for_link = B_FALSE; 713 714 /* Adaptive IFS related changes */ 715 hw->mac.adaptive_ifs = B_TRUE; 716 717 /* Enable phy init script for IGP phy of 82541/82547 */ 718 if ((hw->mac.type == e1000_82547) || 719 (hw->mac.type == e1000_82541) || 720 (hw->mac.type == e1000_82547_rev_2) || 721 (hw->mac.type == e1000_82541_rev_2)) 722 e1000_init_script_state_82541(hw, B_TRUE); 723 724 /* Enable the TTL workaround for 82541/82547 */ 725 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 726 727 #ifdef __sparc 728 Adapter->strip_crc = B_TRUE; 729 #else 730 Adapter->strip_crc = B_FALSE; 731 #endif 732 733 /* Get conf file properties */ 734 e1000g_get_conf(Adapter); 735 736 /* Get speed/duplex settings in conf file */ 737 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 738 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 739 e1000g_force_speed_duplex(Adapter); 740 741 /* Get Jumbo Frames settings in conf file */ 742 e1000g_get_max_frame_size(Adapter); 743 hw->mac.min_frame_size = 744 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 745 746 #ifdef __sparc 747 /* Get the system page size */ 748 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 749 iommu_pagesize = dvma_pagesize(devinfo); 750 if (iommu_pagesize != 0) { 751 if (Adapter->sys_page_sz == iommu_pagesize) { 752 if (iommu_pagesize > 0x4000) 753 Adapter->sys_page_sz = 0x4000; 754 } else { 755 if (Adapter->sys_page_sz > iommu_pagesize) 756 Adapter->sys_page_sz = iommu_pagesize; 757 } 758 } 759 Adapter->dvma_page_num = hw->mac.max_frame_size / 760 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 761 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 762 #endif 763 764 /* Set Rx/Tx buffer size */ 765 switch (hw->mac.max_frame_size) { 766 case ETHERMAX: 767 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 768 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 769 break; 770 case FRAME_SIZE_UPTO_4K: 771 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 772 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 773 break; 774 case FRAME_SIZE_UPTO_8K: 775 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 776 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 777 break; 778 case FRAME_SIZE_UPTO_9K: 779 case FRAME_SIZE_UPTO_16K: 780 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 781 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 782 break; 783 default: 784 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 785 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 786 break; 787 } 788 Adapter->rx_buffer_size += E1000G_IPALIGNPRESERVEROOM; 789 790 #ifndef NO_82542_SUPPORT 791 /* 792 * For Wiseman adapters we have an requirement of having receive 793 * buffers aligned at 256 byte boundary. Since Livengood does not 794 * require this and forcing it for all hardwares will have 795 * performance implications, I am making it applicable only for 796 * Wiseman and for Jumbo frames enabled mode as rest of the time, 797 * it is okay to have normal frames...but it does involve a 798 * potential risk where we may loose data if buffer is not 799 * aligned...so all wiseman boards to have 256 byte aligned 800 * buffers 801 */ 802 if (hw->mac.type < e1000_82543) 803 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 804 else 805 Adapter->rx_buf_align = 1; 806 #endif 807 808 /* Master Latency Timer */ 809 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 810 811 /* copper options */ 812 if (hw->media_type == e1000_media_type_copper) { 813 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 814 hw->phy.disable_polarity_correction = B_FALSE; 815 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 816 } 817 818 /* The initial link state should be "unknown" */ 819 Adapter->link_state = LINK_STATE_UNKNOWN; 820 821 /* Initialize rx parameters */ 822 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 823 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 824 825 /* Initialize tx parameters */ 826 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 827 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 828 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 829 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 830 831 tx_ring = Adapter->tx_ring; 832 tx_ring->frags_limit = 833 (hw->mac.max_frame_size / Adapter->tx_bcopy_thresh) + 2; 834 if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) 835 tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); 836 837 /* Initialize rx parameters */ 838 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 839 840 return (DDI_SUCCESS); 841 } 842 843 /* 844 * e1000g_detach - driver detach 845 * 846 * The detach() function is the complement of the attach routine. 847 * If cmd is set to DDI_DETACH, detach() is used to remove the 848 * state associated with a given instance of a device node 849 * prior to the removal of that instance from the system. 850 * 851 * The detach() function will be called once for each instance 852 * of the device for which there has been a successful attach() 853 * once there are no longer any opens on the device. 854 * 855 * Interrupts routine are disabled, All memory allocated by this 856 * driver are freed. 857 */ 858 static int 859 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 860 { 861 struct e1000g *Adapter; 862 boolean_t rx_drain; 863 864 switch (cmd) { 865 default: 866 return (DDI_FAILURE); 867 868 case DDI_SUSPEND: 869 return (e1000g_suspend(devinfo)); 870 871 case DDI_DETACH: 872 break; 873 } 874 875 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 876 if (Adapter == NULL) 877 return (DDI_FAILURE); 878 879 if (mac_unregister(Adapter->mh) != 0) { 880 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 881 return (DDI_FAILURE); 882 } 883 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 884 885 886 if (Adapter->chip_state != E1000G_STOP) 887 e1000g_stop(Adapter, B_TRUE); 888 889 rx_drain = e1000g_rx_drain(Adapter); 890 891 /* 892 * If e1000g_force_detach is enabled, driver detach is safe. 893 * We will let e1000g_free_priv_devi_node routine determine 894 * whether we need to free the priv_dip entry for current 895 * driver instance. 896 */ 897 if (e1000g_force_detach) { 898 e1000g_free_priv_devi_node(Adapter, rx_drain); 899 } else { 900 if (!rx_drain) 901 return (DDI_FAILURE); 902 } 903 904 e1000g_unattach(devinfo, Adapter); 905 906 return (DDI_SUCCESS); 907 } 908 909 /* 910 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 911 * 912 * If free_flag is true, that indicates the upper layer is not holding 913 * the rx buffers, we could free the priv_dip entry safely. 914 * 915 * Otherwise, we have to keep this entry even after driver detached, 916 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 917 * so that driver could free it while all of rx buffers are returned 918 * by upper layer later. 919 */ 920 static void 921 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 922 { 923 private_devi_list_t *devi_node, *devi_del; 924 925 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 926 ASSERT(e1000g_private_devi_list != NULL); 927 ASSERT(Adapter->priv_dip != NULL); 928 929 devi_node = e1000g_private_devi_list; 930 if (devi_node->priv_dip == Adapter->priv_dip) { 931 if (free_flag) { 932 e1000g_private_devi_list = 933 devi_node->next; 934 kmem_free(devi_node->priv_dip, 935 sizeof (struct dev_info)); 936 kmem_free(devi_node, 937 sizeof (private_devi_list_t)); 938 } else { 939 ASSERT(e1000g_mblks_pending != 0); 940 devi_node->flag = 941 E1000G_PRIV_DEVI_DETACH; 942 } 943 rw_exit(&e1000g_rx_detach_lock); 944 return; 945 } 946 947 devi_node = e1000g_private_devi_list; 948 while (devi_node->next != NULL) { 949 if (devi_node->next->priv_dip == Adapter->priv_dip) { 950 if (free_flag) { 951 devi_del = devi_node->next; 952 devi_node->next = devi_del->next; 953 kmem_free(devi_del->priv_dip, 954 sizeof (struct dev_info)); 955 kmem_free(devi_del, 956 sizeof (private_devi_list_t)); 957 } else { 958 ASSERT(e1000g_mblks_pending != 0); 959 devi_node->next->flag = 960 E1000G_PRIV_DEVI_DETACH; 961 } 962 break; 963 } 964 devi_node = devi_node->next; 965 } 966 rw_exit(&e1000g_rx_detach_lock); 967 } 968 969 static void 970 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 971 { 972 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 973 (void) e1000g_disable_intrs(Adapter); 974 } 975 976 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 977 (void) mac_unregister(Adapter->mh); 978 } 979 980 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 981 e1000g_nd_cleanup(Adapter); 982 } 983 984 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 985 (void) e1000g_rem_intrs(Adapter); 986 } 987 988 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 989 (void) ddi_prop_remove_all(devinfo); 990 } 991 992 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 993 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 994 } 995 996 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 997 stop_link_timer(Adapter); 998 if (e1000_reset_hw(&Adapter->shared) != 0) { 999 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1000 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1001 } 1002 } 1003 1004 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1005 if (Adapter->osdep.reg_handle != NULL) 1006 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1007 if (Adapter->osdep.ich_flash_handle != NULL) 1008 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1009 } 1010 1011 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1012 if (Adapter->osdep.cfg_handle != NULL) 1013 pci_config_teardown(&Adapter->osdep.cfg_handle); 1014 } 1015 1016 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1017 e1000g_destroy_locks(Adapter); 1018 } 1019 1020 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1021 e1000g_fm_fini(Adapter); 1022 } 1023 1024 e1000_remove_device(&Adapter->shared); 1025 1026 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1027 1028 /* 1029 * Another hotplug spec requirement, 1030 * run ddi_set_driver_private(devinfo, null); 1031 */ 1032 ddi_set_driver_private(devinfo, NULL); 1033 } 1034 1035 static void 1036 e1000g_init_locks(struct e1000g *Adapter) 1037 { 1038 e1000g_tx_ring_t *tx_ring; 1039 e1000g_rx_ring_t *rx_ring; 1040 1041 rw_init(&Adapter->chip_lock, NULL, 1042 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1043 mutex_init(&Adapter->link_lock, NULL, 1044 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1045 mutex_init(&Adapter->watchdog_lock, NULL, 1046 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1047 1048 tx_ring = Adapter->tx_ring; 1049 1050 mutex_init(&tx_ring->tx_lock, NULL, 1051 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1052 mutex_init(&tx_ring->usedlist_lock, NULL, 1053 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1054 mutex_init(&tx_ring->freelist_lock, NULL, 1055 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1056 1057 rx_ring = Adapter->rx_ring; 1058 1059 mutex_init(&rx_ring->freelist_lock, NULL, 1060 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1061 } 1062 1063 static void 1064 e1000g_destroy_locks(struct e1000g *Adapter) 1065 { 1066 e1000g_tx_ring_t *tx_ring; 1067 e1000g_rx_ring_t *rx_ring; 1068 1069 tx_ring = Adapter->tx_ring; 1070 mutex_destroy(&tx_ring->tx_lock); 1071 mutex_destroy(&tx_ring->usedlist_lock); 1072 mutex_destroy(&tx_ring->freelist_lock); 1073 1074 rx_ring = Adapter->rx_ring; 1075 mutex_destroy(&rx_ring->freelist_lock); 1076 1077 mutex_destroy(&Adapter->link_lock); 1078 mutex_destroy(&Adapter->watchdog_lock); 1079 rw_destroy(&Adapter->chip_lock); 1080 } 1081 1082 static int 1083 e1000g_resume(dev_info_t *devinfo) 1084 { 1085 struct e1000g *Adapter; 1086 1087 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1088 if (Adapter == NULL) 1089 return (DDI_FAILURE); 1090 1091 if (e1000g_start(Adapter, B_TRUE)) 1092 return (DDI_FAILURE); 1093 1094 return (DDI_SUCCESS); 1095 } 1096 1097 static int 1098 e1000g_suspend(dev_info_t *devinfo) 1099 { 1100 struct e1000g *Adapter; 1101 1102 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1103 if (Adapter == NULL) 1104 return (DDI_FAILURE); 1105 1106 e1000g_stop(Adapter, B_TRUE); 1107 1108 return (DDI_SUCCESS); 1109 } 1110 1111 static int 1112 e1000g_init(struct e1000g *Adapter) 1113 { 1114 uint32_t pba; 1115 uint32_t high_water; 1116 struct e1000_hw *hw; 1117 clock_t link_timeout; 1118 1119 hw = &Adapter->shared; 1120 1121 rw_enter(&Adapter->chip_lock, RW_WRITER); 1122 1123 /* 1124 * reset to put the hardware in a known state 1125 * before we try to do anything with the eeprom 1126 */ 1127 if (e1000_reset_hw(hw) != 0) { 1128 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1129 goto init_fail; 1130 } 1131 1132 if (e1000_validate_nvm_checksum(hw) < 0) { 1133 /* 1134 * Some PCI-E parts fail the first check due to 1135 * the link being in sleep state. Call it again, 1136 * if it fails a second time its a real issue. 1137 */ 1138 if (e1000_validate_nvm_checksum(hw) < 0) { 1139 e1000g_log(Adapter, CE_WARN, 1140 "Invalid NVM checksum. Please contact " 1141 "the vendor to update the NVM."); 1142 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1143 goto init_fail; 1144 } 1145 } 1146 1147 #ifdef __sparc 1148 /* 1149 * Firstly, we try to get the local ethernet address from OBP. If 1150 * fail, we get from EEPROM of NIC card. 1151 */ 1152 if (!e1000g_find_mac_address(Adapter)) { 1153 if (e1000_read_mac_addr(hw) < 0) { 1154 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1155 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1156 goto init_fail; 1157 } 1158 } 1159 #else 1160 /* Get the local ethernet address. */ 1161 if (e1000_read_mac_addr(hw) < 0) { 1162 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1163 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1164 goto init_fail; 1165 } 1166 #endif 1167 1168 /* check for valid mac address */ 1169 if (!is_valid_mac_addr(hw->mac.addr)) { 1170 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1171 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1172 goto init_fail; 1173 } 1174 1175 /* Set LAA state for 82571 chipset */ 1176 e1000_set_laa_state_82571(hw, B_TRUE); 1177 1178 /* Master Latency Timer implementation */ 1179 if (Adapter->master_latency_timer) { 1180 pci_config_put8(Adapter->osdep.cfg_handle, 1181 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1182 } 1183 1184 if (hw->mac.type < e1000_82547) { 1185 /* 1186 * Total FIFO is 64K 1187 */ 1188 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1189 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1190 else 1191 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1192 } else if (hw->mac.type >= e1000_82571 && 1193 hw->mac.type <= e1000_82572) { 1194 /* 1195 * Total FIFO is 48K 1196 */ 1197 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1198 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1199 else 1200 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1201 } else if (hw->mac.type == e1000_ich8lan) { 1202 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1203 } else if (hw->mac.type == e1000_ich9lan) { 1204 pba = E1000_PBA_12K; 1205 } else { 1206 /* 1207 * Total FIFO is 40K 1208 */ 1209 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1210 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1211 else 1212 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1213 } 1214 E1000_WRITE_REG(hw, E1000_PBA, pba); 1215 1216 /* 1217 * These parameters set thresholds for the adapter's generation(Tx) 1218 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1219 * settings. Flow control is enabled or disabled in the configuration 1220 * file. 1221 * High-water mark is set down from the top of the rx fifo (not 1222 * sensitive to max_frame_size) and low-water is set just below 1223 * high-water mark. 1224 * The high water mark must be low enough to fit one full frame above 1225 * it in the rx FIFO. Should be the lower of: 1226 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1227 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1228 * Rx FIFO size minus one full frame. 1229 */ 1230 high_water = min(((pba << 10) * 9 / 10), 1231 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1232 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1233 ((pba << 10) - hw->mac.max_frame_size))); 1234 1235 hw->mac.fc_high_water = high_water & 0xFFF8; 1236 hw->mac.fc_low_water = hw->mac.fc_high_water - 8; 1237 1238 if (hw->mac.type == e1000_80003es2lan) 1239 hw->mac.fc_pause_time = 0xFFFF; 1240 else 1241 hw->mac.fc_pause_time = E1000_FC_PAUSE_TIME; 1242 hw->mac.fc_send_xon = B_TRUE; 1243 hw->mac.fc = hw->mac.original_fc; 1244 1245 /* 1246 * Reset the adapter hardware the second time. 1247 */ 1248 if (e1000_reset_hw(hw) != 0) { 1249 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1250 goto init_fail; 1251 } 1252 1253 /* disable wakeup control by default */ 1254 if (hw->mac.type >= e1000_82544) 1255 E1000_WRITE_REG(hw, E1000_WUC, 0); 1256 1257 /* MWI setup */ 1258 e1000_pci_set_mwi(hw); 1259 1260 /* 1261 * Configure/Initialize hardware 1262 */ 1263 if (e1000_init_hw(hw) < 0) { 1264 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1265 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1266 goto init_fail; 1267 } 1268 1269 /* Disable Smart Power Down */ 1270 phy_spd_state(hw, B_FALSE); 1271 1272 /* Make sure driver has control */ 1273 e1000g_get_driver_control(hw); 1274 1275 /* 1276 * Initialize unicast addresses. 1277 */ 1278 e1000g_init_unicst(Adapter); 1279 1280 /* 1281 * Setup and initialize the mctable structures. After this routine 1282 * completes Multicast table will be set 1283 */ 1284 e1000g_setup_multicast(Adapter); 1285 msec_delay(5); 1286 1287 /* 1288 * Implement Adaptive IFS 1289 */ 1290 e1000_reset_adaptive(hw); 1291 1292 /* Setup Interrupt Throttling Register */ 1293 if (hw->mac.type >= e1000_82540) { 1294 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1295 } else 1296 Adapter->intr_adaptive = B_FALSE; 1297 1298 /* Start the timer for link setup */ 1299 if (hw->mac.autoneg) 1300 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1301 else 1302 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1303 1304 mutex_enter(&Adapter->link_lock); 1305 if (hw->phy.wait_for_link) { 1306 Adapter->link_complete = B_TRUE; 1307 } else { 1308 Adapter->link_complete = B_FALSE; 1309 Adapter->link_tid = timeout(e1000g_link_timer, 1310 (void *)Adapter, link_timeout); 1311 } 1312 mutex_exit(&Adapter->link_lock); 1313 1314 /* Enable PCI-Ex master */ 1315 if (hw->bus.type == e1000_bus_type_pci_express) { 1316 e1000_enable_pciex_master(hw); 1317 } 1318 1319 /* Save the state of the phy */ 1320 e1000g_get_phy_state(Adapter); 1321 1322 Adapter->init_count++; 1323 1324 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1325 goto init_fail; 1326 } 1327 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1328 goto init_fail; 1329 } 1330 1331 rw_exit(&Adapter->chip_lock); 1332 1333 return (DDI_SUCCESS); 1334 1335 init_fail: 1336 rw_exit(&Adapter->chip_lock); 1337 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1338 return (DDI_FAILURE); 1339 } 1340 1341 /* 1342 * Check if the link is up 1343 */ 1344 static boolean_t 1345 e1000g_link_up(struct e1000g *Adapter) 1346 { 1347 struct e1000_hw *hw; 1348 boolean_t link_up; 1349 1350 hw = &Adapter->shared; 1351 1352 e1000_check_for_link(hw); 1353 1354 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1355 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1356 ((hw->media_type == e1000_media_type_internal_serdes) && 1357 (hw->mac.serdes_has_link))) { 1358 link_up = B_TRUE; 1359 } else { 1360 link_up = B_FALSE; 1361 } 1362 1363 return (link_up); 1364 } 1365 1366 static void 1367 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1368 { 1369 struct iocblk *iocp; 1370 struct e1000g *e1000gp; 1371 enum ioc_reply status; 1372 int err; 1373 1374 iocp = (struct iocblk *)mp->b_rptr; 1375 iocp->ioc_error = 0; 1376 e1000gp = (struct e1000g *)arg; 1377 1378 ASSERT(e1000gp); 1379 if (e1000gp == NULL) { 1380 miocnak(q, mp, 0, EINVAL); 1381 return; 1382 } 1383 1384 switch (iocp->ioc_cmd) { 1385 1386 case LB_GET_INFO_SIZE: 1387 case LB_GET_INFO: 1388 case LB_GET_MODE: 1389 case LB_SET_MODE: 1390 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1391 break; 1392 1393 case ND_GET: 1394 case ND_SET: 1395 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1396 break; 1397 1398 #ifdef E1000G_DEBUG 1399 case E1000G_IOC_REG_PEEK: 1400 case E1000G_IOC_REG_POKE: 1401 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1402 break; 1403 case E1000G_IOC_CHIP_RESET: 1404 e1000gp->reset_count++; 1405 if (e1000g_reset(e1000gp)) 1406 status = IOC_ACK; 1407 else 1408 status = IOC_INVAL; 1409 break; 1410 #endif 1411 default: 1412 status = IOC_INVAL; 1413 break; 1414 } 1415 1416 /* 1417 * Decide how to reply 1418 */ 1419 switch (status) { 1420 default: 1421 case IOC_INVAL: 1422 /* 1423 * Error, reply with a NAK and EINVAL or the specified error 1424 */ 1425 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1426 EINVAL : iocp->ioc_error); 1427 break; 1428 1429 case IOC_DONE: 1430 /* 1431 * OK, reply already sent 1432 */ 1433 break; 1434 1435 case IOC_ACK: 1436 /* 1437 * OK, reply with an ACK 1438 */ 1439 miocack(q, mp, 0, 0); 1440 break; 1441 1442 case IOC_REPLY: 1443 /* 1444 * OK, send prepared reply as ACK or NAK 1445 */ 1446 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1447 M_IOCACK : M_IOCNAK; 1448 qreply(q, mp); 1449 break; 1450 } 1451 } 1452 1453 static int 1454 e1000g_m_start(void *arg) 1455 { 1456 struct e1000g *Adapter = (struct e1000g *)arg; 1457 1458 return (e1000g_start(Adapter, B_TRUE)); 1459 } 1460 1461 static int 1462 e1000g_start(struct e1000g *Adapter, boolean_t global) 1463 { 1464 if (global) { 1465 /* Allocate dma resources for descriptors and buffers */ 1466 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1467 e1000g_log(Adapter, CE_WARN, 1468 "Alloc DMA resources failed"); 1469 return (ENOTACTIVE); 1470 } 1471 Adapter->rx_buffer_setup = B_FALSE; 1472 } 1473 1474 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1475 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1476 e1000g_log(Adapter, CE_WARN, 1477 "Adapter initialization failed"); 1478 if (global) 1479 e1000g_release_dma_resources(Adapter); 1480 return (ENOTACTIVE); 1481 } 1482 } 1483 1484 rw_enter(&Adapter->chip_lock, RW_WRITER); 1485 1486 /* Setup and initialize the transmit structures */ 1487 e1000g_tx_setup(Adapter); 1488 msec_delay(5); 1489 1490 /* Setup and initialize the receive structures */ 1491 e1000g_rx_setup(Adapter); 1492 msec_delay(5); 1493 1494 e1000g_mask_interrupt(Adapter); 1495 1496 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1497 rw_exit(&Adapter->chip_lock); 1498 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1499 return (ENOTACTIVE); 1500 } 1501 1502 Adapter->chip_state = E1000G_START; 1503 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1504 1505 rw_exit(&Adapter->chip_lock); 1506 1507 /* Enable and start the watchdog timer */ 1508 enable_watchdog_timer(Adapter); 1509 1510 return (0); 1511 } 1512 1513 static void 1514 e1000g_m_stop(void *arg) 1515 { 1516 struct e1000g *Adapter = (struct e1000g *)arg; 1517 1518 e1000g_stop(Adapter, B_TRUE); 1519 } 1520 1521 static void 1522 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1523 { 1524 /* Set stop flags */ 1525 rw_enter(&Adapter->chip_lock, RW_WRITER); 1526 1527 Adapter->chip_state = E1000G_STOP; 1528 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1529 1530 rw_exit(&Adapter->chip_lock); 1531 1532 /* Drain tx sessions */ 1533 (void) e1000g_tx_drain(Adapter); 1534 1535 /* Disable and stop all the timers */ 1536 disable_watchdog_timer(Adapter); 1537 stop_link_timer(Adapter); 1538 stop_82547_timer(Adapter->tx_ring); 1539 1540 /* Stop the chip and release pending resources */ 1541 rw_enter(&Adapter->chip_lock, RW_WRITER); 1542 1543 e1000g_clear_all_interrupts(Adapter); 1544 if (e1000_reset_hw(&Adapter->shared) != 0) { 1545 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1546 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1547 } 1548 1549 /* Release resources still held by the TX descriptors */ 1550 e1000g_tx_clean(Adapter); 1551 1552 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1553 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1554 1555 /* Clean the pending rx jumbo packet fragment */ 1556 e1000g_rx_clean(Adapter); 1557 1558 rw_exit(&Adapter->chip_lock); 1559 1560 if (global) 1561 e1000g_release_dma_resources(Adapter); 1562 } 1563 1564 static void 1565 e1000g_rx_clean(struct e1000g *Adapter) 1566 { 1567 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1568 1569 if (rx_ring->rx_mblk != NULL) { 1570 freemsg(rx_ring->rx_mblk); 1571 rx_ring->rx_mblk = NULL; 1572 rx_ring->rx_mblk_tail = NULL; 1573 rx_ring->rx_mblk_len = 0; 1574 } 1575 } 1576 1577 static void 1578 e1000g_tx_clean(struct e1000g *Adapter) 1579 { 1580 e1000g_tx_ring_t *tx_ring; 1581 p_tx_sw_packet_t packet; 1582 mblk_t *mp; 1583 mblk_t *nmp; 1584 uint32_t packet_count; 1585 1586 tx_ring = Adapter->tx_ring; 1587 1588 /* 1589 * Here we don't need to protect the lists using 1590 * the usedlist_lock and freelist_lock, for they 1591 * have been protected by the chip_lock. 1592 */ 1593 mp = NULL; 1594 nmp = NULL; 1595 packet_count = 0; 1596 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1597 while (packet != NULL) { 1598 if (packet->mp != NULL) { 1599 /* Assemble the message chain */ 1600 if (mp == NULL) { 1601 mp = packet->mp; 1602 nmp = packet->mp; 1603 } else { 1604 nmp->b_next = packet->mp; 1605 nmp = packet->mp; 1606 } 1607 /* Disconnect the message from the sw packet */ 1608 packet->mp = NULL; 1609 } 1610 1611 e1000g_free_tx_swpkt(packet); 1612 packet_count++; 1613 1614 packet = (p_tx_sw_packet_t) 1615 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1616 } 1617 1618 if (mp != NULL) 1619 freemsgchain(mp); 1620 1621 if (packet_count > 0) { 1622 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1623 QUEUE_INIT_LIST(&tx_ring->used_list); 1624 1625 /* Setup TX descriptor pointers */ 1626 tx_ring->tbd_next = tx_ring->tbd_first; 1627 tx_ring->tbd_oldest = tx_ring->tbd_first; 1628 1629 /* Setup our HW Tx Head & Tail descriptor pointers */ 1630 E1000_WRITE_REG(&Adapter->shared, E1000_TDH, 0); 1631 E1000_WRITE_REG(&Adapter->shared, E1000_TDT, 0); 1632 } 1633 } 1634 1635 static boolean_t 1636 e1000g_tx_drain(struct e1000g *Adapter) 1637 { 1638 int i; 1639 boolean_t done; 1640 e1000g_tx_ring_t *tx_ring; 1641 1642 tx_ring = Adapter->tx_ring; 1643 1644 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1645 for (i = 0; i < TX_DRAIN_TIME; i++) { 1646 mutex_enter(&tx_ring->usedlist_lock); 1647 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1648 mutex_exit(&tx_ring->usedlist_lock); 1649 1650 if (done) 1651 break; 1652 1653 msec_delay(1); 1654 } 1655 1656 return (done); 1657 } 1658 1659 static boolean_t 1660 e1000g_rx_drain(struct e1000g *Adapter) 1661 { 1662 e1000g_rx_ring_t *rx_ring; 1663 p_rx_sw_packet_t packet; 1664 boolean_t done; 1665 1666 rx_ring = Adapter->rx_ring; 1667 done = B_TRUE; 1668 1669 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1670 1671 while (rx_ring->pending_list != NULL) { 1672 packet = rx_ring->pending_list; 1673 rx_ring->pending_list = 1674 rx_ring->pending_list->next; 1675 1676 if (packet->flag == E1000G_RX_SW_STOP) { 1677 packet->flag = E1000G_RX_SW_DETACH; 1678 done = B_FALSE; 1679 } else { 1680 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1681 ASSERT(packet->mp == NULL); 1682 e1000g_free_rx_sw_packet(packet); 1683 } 1684 } 1685 1686 rw_exit(&e1000g_rx_detach_lock); 1687 1688 return (done); 1689 } 1690 1691 boolean_t 1692 e1000g_reset(struct e1000g *Adapter) 1693 { 1694 e1000g_stop(Adapter, B_FALSE); 1695 1696 if (e1000g_start(Adapter, B_FALSE)) { 1697 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1698 return (B_FALSE); 1699 } 1700 1701 return (B_TRUE); 1702 } 1703 1704 boolean_t 1705 e1000g_global_reset(struct e1000g *Adapter) 1706 { 1707 e1000g_stop(Adapter, B_TRUE); 1708 1709 Adapter->init_count = 0; 1710 1711 if (e1000g_start(Adapter, B_TRUE)) { 1712 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1713 return (B_FALSE); 1714 } 1715 1716 return (B_TRUE); 1717 } 1718 1719 /* 1720 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1721 * 1722 * This interrupt service routine is for PCI-Express adapters. 1723 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1724 * bit is set. 1725 */ 1726 static uint_t 1727 e1000g_intr_pciexpress(caddr_t arg) 1728 { 1729 struct e1000g *Adapter; 1730 uint32_t icr; 1731 1732 Adapter = (struct e1000g *)arg; 1733 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1734 1735 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1736 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1737 1738 if (icr & E1000_ICR_INT_ASSERTED) { 1739 /* 1740 * E1000_ICR_INT_ASSERTED bit was set: 1741 * Read(Clear) the ICR, claim this interrupt, 1742 * look for work to do. 1743 */ 1744 e1000g_intr_work(Adapter, icr); 1745 return (DDI_INTR_CLAIMED); 1746 } else { 1747 /* 1748 * E1000_ICR_INT_ASSERTED bit was not set: 1749 * Don't claim this interrupt, return immediately. 1750 */ 1751 return (DDI_INTR_UNCLAIMED); 1752 } 1753 } 1754 1755 /* 1756 * e1000g_intr - ISR for PCI/PCI-X chipsets 1757 * 1758 * This interrupt service routine is for PCI/PCI-X adapters. 1759 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1760 * bit is set or not. 1761 */ 1762 static uint_t 1763 e1000g_intr(caddr_t arg) 1764 { 1765 struct e1000g *Adapter; 1766 uint32_t icr; 1767 1768 Adapter = (struct e1000g *)arg; 1769 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1770 1771 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1772 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1773 1774 if (icr) { 1775 /* 1776 * Any bit was set in ICR: 1777 * Read(Clear) the ICR, claim this interrupt, 1778 * look for work to do. 1779 */ 1780 e1000g_intr_work(Adapter, icr); 1781 return (DDI_INTR_CLAIMED); 1782 } else { 1783 /* 1784 * No bit was set in ICR: 1785 * Don't claim this interrupt, return immediately. 1786 */ 1787 return (DDI_INTR_UNCLAIMED); 1788 } 1789 } 1790 1791 /* 1792 * e1000g_intr_work - actual processing of ISR 1793 * 1794 * Read(clear) the ICR contents and call appropriate interrupt 1795 * processing routines. 1796 */ 1797 static void 1798 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1799 { 1800 struct e1000_hw *hw; 1801 hw = &Adapter->shared; 1802 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1803 uint32_t itr; 1804 1805 Adapter->rx_pkt_cnt = 0; 1806 Adapter->tx_pkt_cnt = 0; 1807 1808 rw_enter(&Adapter->chip_lock, RW_READER); 1809 /* 1810 * Here we need to check the "chip_state" flag within the chip_lock to 1811 * ensure the receive routine will not execute when the adapter is 1812 * being reset. 1813 */ 1814 if (Adapter->chip_state != E1000G_START) { 1815 rw_exit(&Adapter->chip_lock); 1816 return; 1817 } 1818 1819 if (icr & E1000_ICR_RXT0) { 1820 mblk_t *mp; 1821 1822 mp = e1000g_receive(Adapter); 1823 1824 rw_exit(&Adapter->chip_lock); 1825 1826 if (mp != NULL) 1827 mac_rx(Adapter->mh, Adapter->mrh, mp); 1828 } else 1829 rw_exit(&Adapter->chip_lock); 1830 1831 if (icr & E1000_ICR_TXDW) { 1832 if (!Adapter->tx_intr_enable) 1833 e1000g_clear_tx_interrupt(Adapter); 1834 1835 /* Recycle the tx descriptors */ 1836 rw_enter(&Adapter->chip_lock, RW_READER); 1837 e1000g_recycle(tx_ring); 1838 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1839 rw_exit(&Adapter->chip_lock); 1840 1841 /* Schedule the re-transmit */ 1842 if (tx_ring->resched_needed && 1843 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1844 tx_ring->resched_needed = B_FALSE; 1845 mac_tx_update(Adapter->mh); 1846 E1000G_STAT(tx_ring->stat_reschedule); 1847 } 1848 } 1849 1850 if (Adapter->intr_adaptive) { 1851 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1852 Adapter->intr_throttling_rate); 1853 if (itr) { 1854 E1000_WRITE_REG(hw, E1000_ITR, itr); 1855 Adapter->intr_throttling_rate = itr; 1856 } 1857 } 1858 1859 /* 1860 * The Receive Sequence errors RXSEQ and the link status change LSC 1861 * are checked to detect that the cable has been pulled out. For 1862 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1863 * are an indication that cable is not connected. 1864 */ 1865 if ((icr & E1000_ICR_RXSEQ) || 1866 (icr & E1000_ICR_LSC) || 1867 (icr & E1000_ICR_GPI_EN1)) { 1868 boolean_t link_changed; 1869 timeout_id_t tid = 0; 1870 1871 stop_watchdog_timer(Adapter); 1872 1873 rw_enter(&Adapter->chip_lock, RW_WRITER); 1874 1875 /* 1876 * Because we got a link-status-change interrupt, force 1877 * e1000_check_for_link() to look at phy 1878 */ 1879 Adapter->shared.mac.get_link_status = B_TRUE; 1880 1881 /* e1000g_link_check takes care of link status change */ 1882 link_changed = e1000g_link_check(Adapter); 1883 1884 /* Get new phy state */ 1885 e1000g_get_phy_state(Adapter); 1886 1887 /* 1888 * If the link timer has not timed out, we'll not notify 1889 * the upper layer with any link state until the link is up. 1890 */ 1891 if (link_changed && !Adapter->link_complete) { 1892 if (Adapter->link_state == LINK_STATE_UP) { 1893 mutex_enter(&Adapter->link_lock); 1894 Adapter->link_complete = B_TRUE; 1895 tid = Adapter->link_tid; 1896 Adapter->link_tid = 0; 1897 mutex_exit(&Adapter->link_lock); 1898 } else { 1899 link_changed = B_FALSE; 1900 } 1901 } 1902 rw_exit(&Adapter->chip_lock); 1903 1904 if (link_changed) { 1905 if (tid != 0) 1906 (void) untimeout(tid); 1907 1908 /* 1909 * Workaround for esb2. Data stuck in fifo on a link 1910 * down event. Reset the adapter to recover it. 1911 */ 1912 if ((Adapter->link_state == LINK_STATE_DOWN) && 1913 (Adapter->shared.mac.type == e1000_80003es2lan)) 1914 (void) e1000g_reset(Adapter); 1915 1916 mac_link_update(Adapter->mh, Adapter->link_state); 1917 } 1918 1919 start_watchdog_timer(Adapter); 1920 } 1921 } 1922 1923 static uint32_t 1924 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 1925 { 1926 uint32_t new_itr; 1927 1928 /* 1929 * Determine a propper itr according to rx/tx packet count 1930 * per interrupt, the value of itr are based on document 1931 * and testing. 1932 */ 1933 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 1934 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 1935 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1936 goto itr_done; 1937 } 1938 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 1939 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 1940 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1941 goto itr_done; 1942 } 1943 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 1944 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 1945 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 1946 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1947 } else 1948 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1949 1950 itr_done: 1951 if (cur_itr == new_itr) 1952 return (0); 1953 else 1954 return (new_itr); 1955 } 1956 1957 static void 1958 e1000g_init_unicst(struct e1000g *Adapter) 1959 { 1960 struct e1000_hw *hw; 1961 int slot; 1962 1963 hw = &Adapter->shared; 1964 1965 if (!Adapter->unicst_init) { 1966 /* Initialize the multiple unicast addresses */ 1967 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1968 1969 if ((hw->mac.type == e1000_82571) && 1970 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1971 Adapter->unicst_total--; 1972 1973 Adapter->unicst_avail = Adapter->unicst_total - 1; 1974 1975 /* Store the default mac address */ 1976 e1000_rar_set(hw, hw->mac.addr, 0); 1977 if ((hw->mac.type == e1000_82571) && 1978 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1979 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 1980 1981 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 1982 ETHERADDRL); 1983 Adapter->unicst_addr[0].mac.set = 1; 1984 1985 for (slot = 1; slot < Adapter->unicst_total; slot++) 1986 Adapter->unicst_addr[slot].mac.set = 0; 1987 1988 Adapter->unicst_init = B_TRUE; 1989 } else { 1990 /* Recover the default mac address */ 1991 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 1992 ETHERADDRL); 1993 1994 /* Store the default mac address */ 1995 e1000_rar_set(hw, hw->mac.addr, 0); 1996 if ((hw->mac.type == e1000_82571) && 1997 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1998 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 1999 2000 /* Re-configure the RAR registers */ 2001 for (slot = 1; slot < Adapter->unicst_total; slot++) 2002 e1000_rar_set(hw, 2003 Adapter->unicst_addr[slot].mac.addr, slot); 2004 } 2005 2006 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2007 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2008 } 2009 2010 static int 2011 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2012 { 2013 struct e1000g *Adapter; 2014 2015 Adapter = (struct e1000g *)arg; 2016 2017 /* Store the default MAC address */ 2018 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2019 2020 /* Set MAC address in address slot 0, which is the default address */ 2021 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2022 } 2023 2024 static int 2025 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2026 mac_addr_slot_t slot) 2027 { 2028 struct e1000_hw *hw; 2029 2030 hw = &Adapter->shared; 2031 2032 rw_enter(&Adapter->chip_lock, RW_WRITER); 2033 2034 #ifndef NO_82542_SUPPORT 2035 /* 2036 * The first revision of Wiseman silicon (rev 2.0) has an errata 2037 * that requires the receiver to be in reset when any of the 2038 * receive address registers (RAR regs) are accessed. The first 2039 * rev of Wiseman silicon also requires MWI to be disabled when 2040 * a global reset or a receive reset is issued. So before we 2041 * initialize the RARs, we check the rev of the Wiseman controller 2042 * and work around any necessary HW errata. 2043 */ 2044 if ((hw->mac.type == e1000_82542) && 2045 (hw->revision_id == E1000_REVISION_2)) { 2046 e1000_pci_clear_mwi(hw); 2047 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2048 msec_delay(5); 2049 } 2050 #endif 2051 2052 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2053 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2054 2055 if (slot == 0) { 2056 if ((hw->mac.type == e1000_82571) && 2057 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2058 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2059 } 2060 2061 #ifndef NO_82542_SUPPORT 2062 /* 2063 * If we are using Wiseman rev 2.0 silicon, we will have previously 2064 * put the receive in reset, and disabled MWI, to work around some 2065 * HW errata. Now we should take the receiver out of reset, and 2066 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2067 */ 2068 if ((hw->mac.type == e1000_82542) && 2069 (hw->revision_id == E1000_REVISION_2)) { 2070 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2071 msec_delay(1); 2072 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2073 e1000_pci_set_mwi(hw); 2074 e1000g_rx_setup(Adapter); 2075 } 2076 #endif 2077 2078 rw_exit(&Adapter->chip_lock); 2079 2080 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2081 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2082 return (EIO); 2083 } 2084 2085 return (0); 2086 } 2087 2088 /* 2089 * e1000g_m_unicst_add() - will find an unused address slot, set the 2090 * address value to the one specified, reserve that slot and enable 2091 * the NIC to start filtering on the new MAC address. 2092 * Returns 0 on success. 2093 */ 2094 static int 2095 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2096 { 2097 struct e1000g *Adapter = (struct e1000g *)arg; 2098 mac_addr_slot_t slot; 2099 int err; 2100 2101 if (mac_unicst_verify(Adapter->mh, 2102 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2103 return (EINVAL); 2104 2105 rw_enter(&Adapter->chip_lock, RW_WRITER); 2106 if (Adapter->unicst_avail == 0) { 2107 /* no slots available */ 2108 rw_exit(&Adapter->chip_lock); 2109 return (ENOSPC); 2110 } 2111 2112 /* 2113 * Primary/default address is in slot 0. The next addresses 2114 * are the multiple MAC addresses. So multiple MAC address 0 2115 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2116 * MAC address resides in slot 1. 2117 */ 2118 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2119 if (Adapter->unicst_addr[slot].mac.set == 0) { 2120 Adapter->unicst_addr[slot].mac.set = 1; 2121 break; 2122 } 2123 } 2124 2125 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2126 2127 Adapter->unicst_avail--; 2128 rw_exit(&Adapter->chip_lock); 2129 2130 maddr->mma_slot = slot; 2131 2132 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2133 rw_enter(&Adapter->chip_lock, RW_WRITER); 2134 Adapter->unicst_addr[slot].mac.set = 0; 2135 Adapter->unicst_avail++; 2136 rw_exit(&Adapter->chip_lock); 2137 } 2138 2139 return (err); 2140 } 2141 2142 /* 2143 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2144 * call to e1000g_m_unicst_add(). The slot number that was returned in 2145 * e1000g_m_unicst_add() is passed in the call to remove the address. 2146 * Returns 0 on success. 2147 */ 2148 static int 2149 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2150 { 2151 struct e1000g *Adapter = (struct e1000g *)arg; 2152 int err; 2153 2154 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2155 return (EINVAL); 2156 2157 rw_enter(&Adapter->chip_lock, RW_WRITER); 2158 if (Adapter->unicst_addr[slot].mac.set == 1) { 2159 Adapter->unicst_addr[slot].mac.set = 0; 2160 Adapter->unicst_avail++; 2161 rw_exit(&Adapter->chip_lock); 2162 2163 /* Copy the default address to the passed slot */ 2164 if (err = e1000g_unicst_set(Adapter, 2165 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2166 rw_enter(&Adapter->chip_lock, RW_WRITER); 2167 Adapter->unicst_addr[slot].mac.set = 1; 2168 Adapter->unicst_avail--; 2169 rw_exit(&Adapter->chip_lock); 2170 } 2171 return (err); 2172 } 2173 rw_exit(&Adapter->chip_lock); 2174 2175 return (EINVAL); 2176 } 2177 2178 /* 2179 * e1000g_m_unicst_modify() - modifies the value of an address that 2180 * has been added by e1000g_m_unicst_add(). The new address, address 2181 * length and the slot number that was returned in the call to add 2182 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2183 * set to 0. Returns 0 on success. 2184 */ 2185 static int 2186 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2187 { 2188 struct e1000g *Adapter = (struct e1000g *)arg; 2189 mac_addr_slot_t slot; 2190 2191 if (mac_unicst_verify(Adapter->mh, 2192 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2193 return (EINVAL); 2194 2195 slot = maddr->mma_slot; 2196 2197 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2198 return (EINVAL); 2199 2200 rw_enter(&Adapter->chip_lock, RW_WRITER); 2201 if (Adapter->unicst_addr[slot].mac.set == 1) { 2202 rw_exit(&Adapter->chip_lock); 2203 2204 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2205 } 2206 rw_exit(&Adapter->chip_lock); 2207 2208 return (EINVAL); 2209 } 2210 2211 /* 2212 * e1000g_m_unicst_get() - will get the MAC address and all other 2213 * information related to the address slot passed in mac_multi_addr_t. 2214 * mma_flags should be set to 0 in the call. 2215 * On return, mma_flags can take the following values: 2216 * 1) MMAC_SLOT_UNUSED 2217 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2218 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2219 * 4) MMAC_SLOT_USED 2220 */ 2221 static int 2222 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2223 { 2224 struct e1000g *Adapter = (struct e1000g *)arg; 2225 mac_addr_slot_t slot; 2226 2227 slot = maddr->mma_slot; 2228 2229 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2230 return (EINVAL); 2231 2232 rw_enter(&Adapter->chip_lock, RW_WRITER); 2233 if (Adapter->unicst_addr[slot].mac.set == 1) { 2234 bcopy(Adapter->unicst_addr[slot].mac.addr, 2235 maddr->mma_addr, ETHERADDRL); 2236 maddr->mma_flags = MMAC_SLOT_USED; 2237 } else { 2238 maddr->mma_flags = MMAC_SLOT_UNUSED; 2239 } 2240 rw_exit(&Adapter->chip_lock); 2241 2242 return (0); 2243 } 2244 2245 static int 2246 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2247 { 2248 struct e1000_hw *hw = &Adapter->shared; 2249 unsigned i; 2250 int res = 0; 2251 2252 rw_enter(&Adapter->chip_lock, RW_WRITER); 2253 2254 if ((multiaddr[0] & 01) == 0) { 2255 res = EINVAL; 2256 goto done; 2257 } 2258 2259 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2260 res = ENOENT; 2261 goto done; 2262 } 2263 2264 bcopy(multiaddr, 2265 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2266 Adapter->mcast_count++; 2267 2268 /* 2269 * Update the MC table in the hardware 2270 */ 2271 e1000g_clear_interrupt(Adapter); 2272 2273 e1000g_setup_multicast(Adapter); 2274 2275 #ifndef NO_82542_SUPPORT 2276 if ((hw->mac.type == e1000_82542) && 2277 (hw->revision_id == E1000_REVISION_2)) 2278 e1000g_rx_setup(Adapter); 2279 #endif 2280 2281 e1000g_mask_interrupt(Adapter); 2282 2283 done: 2284 rw_exit(&Adapter->chip_lock); 2285 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2286 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2287 res = EIO; 2288 } 2289 2290 return (res); 2291 } 2292 2293 static int 2294 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2295 { 2296 struct e1000_hw *hw = &Adapter->shared; 2297 unsigned i; 2298 2299 rw_enter(&Adapter->chip_lock, RW_WRITER); 2300 2301 for (i = 0; i < Adapter->mcast_count; i++) { 2302 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2303 ETHERADDRL) == 0) { 2304 for (i++; i < Adapter->mcast_count; i++) { 2305 Adapter->mcast_table[i - 1] = 2306 Adapter->mcast_table[i]; 2307 } 2308 Adapter->mcast_count--; 2309 break; 2310 } 2311 } 2312 2313 /* 2314 * Update the MC table in the hardware 2315 */ 2316 e1000g_clear_interrupt(Adapter); 2317 2318 e1000g_setup_multicast(Adapter); 2319 2320 #ifndef NO_82542_SUPPORT 2321 if ((hw->mac.type == e1000_82542) && 2322 (hw->revision_id == E1000_REVISION_2)) 2323 e1000g_rx_setup(Adapter); 2324 #endif 2325 2326 e1000g_mask_interrupt(Adapter); 2327 2328 done: 2329 rw_exit(&Adapter->chip_lock); 2330 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2331 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2332 return (EIO); 2333 } 2334 2335 return (0); 2336 } 2337 2338 /* 2339 * e1000g_setup_multicast - setup multicast data structures 2340 * 2341 * This routine initializes all of the multicast related structures. 2342 */ 2343 void 2344 e1000g_setup_multicast(struct e1000g *Adapter) 2345 { 2346 uint8_t *mc_addr_list; 2347 uint32_t mc_addr_count; 2348 uint32_t rctl; 2349 struct e1000_hw *hw; 2350 2351 hw = &Adapter->shared; 2352 2353 /* 2354 * The e1000g has the ability to do perfect filtering of 16 2355 * addresses. The driver uses one of the e1000g's 16 receive 2356 * address registers for its node/network/mac/individual address. 2357 * So, we have room for up to 15 multicast addresses in the CAM, 2358 * additional MC addresses are handled by the MTA (Multicast Table 2359 * Array) 2360 */ 2361 2362 rctl = E1000_READ_REG(hw, E1000_RCTL); 2363 2364 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2365 2366 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2367 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2368 "Adapter requested more than %d MC Addresses.\n", 2369 MAX_NUM_MULTICAST_ADDRESSES); 2370 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2371 } else { 2372 /* 2373 * Set the number of MC addresses that we are being 2374 * requested to use 2375 */ 2376 mc_addr_count = Adapter->mcast_count; 2377 } 2378 #ifndef NO_82542_SUPPORT 2379 /* 2380 * The Wiseman 2.0 silicon has an errata by which the receiver will 2381 * hang while writing to the receive address registers if the receiver 2382 * is not in reset before writing to the registers. Updating the RAR 2383 * is done during the setting up of the multicast table, hence the 2384 * receiver has to be put in reset before updating the multicast table 2385 * and then taken out of reset at the end 2386 */ 2387 /* 2388 * if WMI was enabled then dis able it before issueing the global 2389 * reset to the hardware. 2390 */ 2391 /* 2392 * Only required for WISEMAN_2_0 2393 */ 2394 if ((hw->mac.type == e1000_82542) && 2395 (hw->revision_id == E1000_REVISION_2)) { 2396 e1000_pci_clear_mwi(hw); 2397 /* 2398 * The e1000g must be in reset before changing any RA 2399 * registers. Reset receive unit. The chip will remain in 2400 * the reset state until software explicitly restarts it. 2401 */ 2402 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2403 /* Allow receiver time to go in to reset */ 2404 msec_delay(5); 2405 } 2406 #endif 2407 2408 e1000_mc_addr_list_update(hw, mc_addr_list, mc_addr_count, 2409 Adapter->unicst_total, hw->mac.rar_entry_count); 2410 2411 #ifndef NO_82542_SUPPORT 2412 /* 2413 * Only for Wiseman_2_0 2414 * If MWI was enabled then re-enable it after issueing (as we 2415 * disabled it up there) the receive reset command. 2416 * Wainwright does not have a receive reset command and only thing 2417 * close to it is global reset which will require tx setup also 2418 */ 2419 if ((hw->mac.type == e1000_82542) && 2420 (hw->revision_id == E1000_REVISION_2)) { 2421 /* 2422 * if WMI was enabled then reenable it after issueing the 2423 * global or receive reset to the hardware. 2424 */ 2425 2426 /* 2427 * Take receiver out of reset 2428 * clear E1000_RCTL_RST bit (and all others) 2429 */ 2430 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2431 msec_delay(5); 2432 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2433 e1000_pci_set_mwi(hw); 2434 } 2435 #endif 2436 2437 /* 2438 * Restore original value 2439 */ 2440 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2441 } 2442 2443 int 2444 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2445 { 2446 struct e1000g *Adapter = (struct e1000g *)arg; 2447 2448 return ((add) ? multicst_add(Adapter, addr) 2449 : multicst_remove(Adapter, addr)); 2450 } 2451 2452 int 2453 e1000g_m_promisc(void *arg, boolean_t on) 2454 { 2455 struct e1000g *Adapter = (struct e1000g *)arg; 2456 uint32_t rctl; 2457 2458 rw_enter(&Adapter->chip_lock, RW_WRITER); 2459 2460 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2461 2462 if (on) 2463 rctl |= 2464 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2465 else 2466 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2467 2468 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2469 2470 Adapter->e1000g_promisc = on; 2471 2472 rw_exit(&Adapter->chip_lock); 2473 2474 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2475 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2476 return (EIO); 2477 } 2478 2479 return (0); 2480 } 2481 2482 static boolean_t 2483 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2484 { 2485 struct e1000g *Adapter = (struct e1000g *)arg; 2486 struct e1000_hw *hw = &Adapter->shared; 2487 2488 switch (cap) { 2489 case MAC_CAPAB_HCKSUM: { 2490 uint32_t *txflags = cap_data; 2491 /* 2492 * Checksum on/off selection via global parameters. 2493 * 2494 * If the chip is flagged as not capable of (correctly) 2495 * handling checksumming, we don't enable it on either 2496 * Rx or Tx side. Otherwise, we take this chip's settings 2497 * from the patchable global defaults. 2498 * 2499 * We advertise our capabilities only if TX offload is 2500 * enabled. On receive, the stack will accept checksummed 2501 * packets anyway, even if we haven't said we can deliver 2502 * them. 2503 */ 2504 switch (hw->mac.type) { 2505 case e1000_82540: 2506 case e1000_82544: 2507 case e1000_82545: 2508 case e1000_82545_rev_3: 2509 case e1000_82546: 2510 case e1000_82546_rev_3: 2511 case e1000_82571: 2512 case e1000_82572: 2513 case e1000_82573: 2514 case e1000_80003es2lan: 2515 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2516 break; 2517 2518 /* 2519 * For the following Intel PRO/1000 chipsets, we have not 2520 * tested the hardware checksum offload capability, so we 2521 * disable the capability for them. 2522 * e1000_82542, 2523 * e1000_82543, 2524 * e1000_82541, 2525 * e1000_82541_rev_2, 2526 * e1000_82547, 2527 * e1000_82547_rev_2, 2528 */ 2529 default: 2530 return (B_FALSE); 2531 } 2532 2533 break; 2534 } 2535 case MAC_CAPAB_POLL: 2536 /* 2537 * There's nothing for us to fill in, simply returning 2538 * B_TRUE stating that we support polling is sufficient. 2539 */ 2540 break; 2541 2542 case MAC_CAPAB_MULTIADDRESS: { 2543 multiaddress_capab_t *mmacp = cap_data; 2544 2545 /* 2546 * The number of MAC addresses made available by 2547 * this capability is one less than the total as 2548 * the primary address in slot 0 is counted in 2549 * the total. 2550 */ 2551 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2552 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2553 /* No multiple factory addresses, set mma_flag to 0 */ 2554 mmacp->maddr_flag = 0; 2555 mmacp->maddr_handle = Adapter; 2556 mmacp->maddr_add = e1000g_m_unicst_add; 2557 mmacp->maddr_remove = e1000g_m_unicst_remove; 2558 mmacp->maddr_modify = e1000g_m_unicst_modify; 2559 mmacp->maddr_get = e1000g_m_unicst_get; 2560 mmacp->maddr_reserve = NULL; 2561 break; 2562 } 2563 default: 2564 return (B_FALSE); 2565 } 2566 return (B_TRUE); 2567 } 2568 2569 /* 2570 * e1000g_get_conf - get configurations set in e1000g.conf 2571 * 2572 * This routine gets user-configured values out of the configuration 2573 * file e1000g.conf. 2574 * 2575 * For each configurable value, there is a minimum, a maximum, and a 2576 * default. 2577 * If user does not configure a value, use the default. 2578 * If user configures below the minimum, use the minumum. 2579 * If user configures above the maximum, use the maxumum. 2580 */ 2581 static void 2582 e1000g_get_conf(struct e1000g *Adapter) 2583 { 2584 struct e1000_hw *hw = &Adapter->shared; 2585 boolean_t tbi_compatibility = B_FALSE; 2586 2587 /* 2588 * get each configurable property from e1000g.conf 2589 */ 2590 2591 /* 2592 * NumTxDescriptors 2593 */ 2594 Adapter->tx_desc_num = 2595 e1000g_get_prop(Adapter, "NumTxDescriptors", 2596 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 2597 DEFAULT_NUM_TX_DESCRIPTOR); 2598 2599 /* 2600 * NumRxDescriptors 2601 */ 2602 Adapter->rx_desc_num = 2603 e1000g_get_prop(Adapter, "NumRxDescriptors", 2604 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 2605 DEFAULT_NUM_RX_DESCRIPTOR); 2606 2607 /* 2608 * NumRxFreeList 2609 */ 2610 Adapter->rx_freelist_num = 2611 e1000g_get_prop(Adapter, "NumRxFreeList", 2612 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 2613 DEFAULT_NUM_RX_FREELIST); 2614 2615 /* 2616 * NumTxPacketList 2617 */ 2618 Adapter->tx_freelist_num = 2619 e1000g_get_prop(Adapter, "NumTxPacketList", 2620 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 2621 DEFAULT_NUM_TX_FREELIST); 2622 2623 /* 2624 * FlowControl 2625 */ 2626 hw->mac.fc_send_xon = B_TRUE; 2627 hw->mac.fc = 2628 e1000g_get_prop(Adapter, "FlowControl", 2629 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 2630 /* 4 is the setting that says "let the eeprom decide" */ 2631 if (hw->mac.fc == 4) 2632 hw->mac.fc = e1000_fc_default; 2633 2634 /* 2635 * Max Num Receive Packets on Interrupt 2636 */ 2637 Adapter->rx_limit_onintr = 2638 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 2639 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 2640 DEFAULT_RX_LIMIT_ON_INTR); 2641 2642 /* 2643 * PHY master slave setting 2644 */ 2645 hw->phy.ms_type = 2646 e1000g_get_prop(Adapter, "SetMasterSlave", 2647 e1000_ms_hw_default, e1000_ms_auto, 2648 e1000_ms_hw_default); 2649 2650 /* 2651 * Parameter which controls TBI mode workaround, which is only 2652 * needed on certain switches such as Cisco 6500/Foundry 2653 */ 2654 tbi_compatibility = 2655 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 2656 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 2657 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 2658 2659 /* 2660 * MSI Enable 2661 */ 2662 Adapter->msi_enabled = 2663 e1000g_get_prop(Adapter, "MSIEnable", 2664 0, 1, DEFAULT_MSI_ENABLE); 2665 2666 /* 2667 * Interrupt Throttling Rate 2668 */ 2669 Adapter->intr_throttling_rate = 2670 e1000g_get_prop(Adapter, "intr_throttling_rate", 2671 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2672 DEFAULT_INTR_THROTTLING); 2673 2674 /* 2675 * Adaptive Interrupt Blanking Enable/Disable 2676 * It is enabled by default 2677 */ 2678 Adapter->intr_adaptive = 2679 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2680 B_TRUE : B_FALSE; 2681 2682 /* 2683 * Tx recycle threshold 2684 */ 2685 Adapter->tx_recycle_thresh = 2686 e1000g_get_prop(Adapter, "tx_recycle_thresh", 2687 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2688 DEFAULT_TX_RECYCLE_THRESHOLD); 2689 2690 /* 2691 * Tx recycle descriptor number 2692 */ 2693 Adapter->tx_recycle_num = 2694 e1000g_get_prop(Adapter, "tx_recycle_num", 2695 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 2696 DEFAULT_TX_RECYCLE_NUM); 2697 } 2698 2699 /* 2700 * e1000g_get_prop - routine to read properties 2701 * 2702 * Get a user-configure property value out of the configuration 2703 * file e1000g.conf. 2704 * 2705 * Caller provides name of the property, a default value, a minimum 2706 * value, and a maximum value. 2707 * 2708 * Return configured value of the property, with default, minimum and 2709 * maximum properly applied. 2710 */ 2711 static int 2712 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 2713 char *propname, /* name of the property */ 2714 int minval, /* minimum acceptable value */ 2715 int maxval, /* maximim acceptable value */ 2716 int defval) /* default value */ 2717 { 2718 int propval; /* value returned for requested property */ 2719 int *props; /* point to array of properties returned */ 2720 uint_t nprops; /* number of property value returned */ 2721 2722 /* 2723 * get the array of properties from the config file 2724 */ 2725 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2726 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2727 /* got some properties, test if we got enough */ 2728 if (Adapter->instance < nprops) { 2729 propval = props[Adapter->instance]; 2730 } else { 2731 /* not enough properties configured */ 2732 propval = defval; 2733 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2734 "Not Enough %s values found in e1000g.conf" 2735 " - set to %d\n", 2736 propname, propval); 2737 } 2738 2739 /* free memory allocated for properties */ 2740 ddi_prop_free(props); 2741 2742 } else { 2743 propval = defval; 2744 } 2745 2746 /* 2747 * enforce limits 2748 */ 2749 if (propval > maxval) { 2750 propval = maxval; 2751 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2752 "Too High %s value in e1000g.conf - set to %d\n", 2753 propname, propval); 2754 } 2755 2756 if (propval < minval) { 2757 propval = minval; 2758 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2759 "Too Low %s value in e1000g.conf - set to %d\n", 2760 propname, propval); 2761 } 2762 2763 return (propval); 2764 } 2765 2766 static boolean_t 2767 e1000g_link_check(struct e1000g *Adapter) 2768 { 2769 uint16_t speed, duplex, phydata; 2770 boolean_t link_changed = B_FALSE; 2771 struct e1000_hw *hw; 2772 uint32_t reg_tarc; 2773 2774 hw = &Adapter->shared; 2775 2776 if (e1000g_link_up(Adapter)) { 2777 /* 2778 * The Link is up, check whether it was marked as down earlier 2779 */ 2780 if (Adapter->link_state != LINK_STATE_UP) { 2781 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2782 Adapter->link_speed = speed; 2783 Adapter->link_duplex = duplex; 2784 Adapter->link_state = LINK_STATE_UP; 2785 link_changed = B_TRUE; 2786 2787 Adapter->tx_link_down_timeout = 0; 2788 2789 if ((hw->mac.type == e1000_82571) || 2790 (hw->mac.type == e1000_82572)) { 2791 reg_tarc = E1000_READ_REG(hw, E1000_TARC0); 2792 if (speed == SPEED_1000) 2793 reg_tarc |= (1 << 21); 2794 else 2795 reg_tarc &= ~(1 << 21); 2796 E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); 2797 } 2798 } 2799 Adapter->smartspeed = 0; 2800 } else { 2801 if (Adapter->link_state != LINK_STATE_DOWN) { 2802 Adapter->link_speed = 0; 2803 Adapter->link_duplex = 0; 2804 Adapter->link_state = LINK_STATE_DOWN; 2805 link_changed = B_TRUE; 2806 2807 /* 2808 * SmartSpeed workaround for Tabor/TanaX, When the 2809 * driver loses link disable auto master/slave 2810 * resolution. 2811 */ 2812 if (hw->phy.type == e1000_phy_igp) { 2813 e1000_read_phy_reg(hw, 2814 PHY_1000T_CTRL, &phydata); 2815 phydata |= CR_1000T_MS_ENABLE; 2816 e1000_write_phy_reg(hw, 2817 PHY_1000T_CTRL, phydata); 2818 } 2819 } else { 2820 e1000g_smartspeed(Adapter); 2821 } 2822 2823 if (Adapter->chip_state == E1000G_START) { 2824 if (Adapter->tx_link_down_timeout < 2825 MAX_TX_LINK_DOWN_TIMEOUT) { 2826 Adapter->tx_link_down_timeout++; 2827 } else if (Adapter->tx_link_down_timeout == 2828 MAX_TX_LINK_DOWN_TIMEOUT) { 2829 e1000g_tx_clean(Adapter); 2830 Adapter->tx_link_down_timeout++; 2831 } 2832 } 2833 } 2834 2835 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2836 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2837 2838 return (link_changed); 2839 } 2840 2841 static void 2842 e1000g_local_timer(void *ws) 2843 { 2844 struct e1000g *Adapter = (struct e1000g *)ws; 2845 struct e1000_hw *hw; 2846 e1000g_ether_addr_t ether_addr; 2847 boolean_t link_changed; 2848 2849 hw = &Adapter->shared; 2850 2851 if (Adapter->chip_state == E1000G_ERROR) { 2852 Adapter->reset_count++; 2853 if (e1000g_global_reset(Adapter)) 2854 ddi_fm_service_impact(Adapter->dip, 2855 DDI_SERVICE_RESTORED); 2856 else 2857 ddi_fm_service_impact(Adapter->dip, 2858 DDI_SERVICE_LOST); 2859 return; 2860 } 2861 2862 if (e1000g_stall_check(Adapter)) { 2863 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 2864 "Tx stall detected. Activate automatic recovery.\n"); 2865 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 2866 Adapter->reset_count++; 2867 if (e1000g_reset(Adapter)) 2868 ddi_fm_service_impact(Adapter->dip, 2869 DDI_SERVICE_RESTORED); 2870 else 2871 ddi_fm_service_impact(Adapter->dip, 2872 DDI_SERVICE_LOST); 2873 return; 2874 } 2875 2876 link_changed = B_FALSE; 2877 rw_enter(&Adapter->chip_lock, RW_READER); 2878 if (Adapter->link_complete) 2879 link_changed = e1000g_link_check(Adapter); 2880 rw_exit(&Adapter->chip_lock); 2881 2882 if (link_changed) { 2883 /* 2884 * Workaround for esb2. Data stuck in fifo on a link 2885 * down event. Reset the adapter to recover it. 2886 */ 2887 if ((Adapter->link_state == LINK_STATE_DOWN) && 2888 (hw->mac.type == e1000_80003es2lan)) 2889 (void) e1000g_reset(Adapter); 2890 2891 mac_link_update(Adapter->mh, Adapter->link_state); 2892 } 2893 2894 /* 2895 * With 82571 controllers, any locally administered address will 2896 * be overwritten when there is a reset on the other port. 2897 * Detect this circumstance and correct it. 2898 */ 2899 if ((hw->mac.type == e1000_82571) && 2900 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 2901 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 2902 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 2903 2904 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2905 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2906 2907 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 2908 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 2909 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 2910 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 2911 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 2912 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 2913 e1000_rar_set(hw, hw->mac.addr, 0); 2914 } 2915 } 2916 2917 /* 2918 * Long TTL workaround for 82541/82547 2919 */ 2920 e1000_igp_ttl_workaround_82547(hw); 2921 2922 /* 2923 * Check for Adaptive IFS settings If there are lots of collisions 2924 * change the value in steps... 2925 * These properties should only be set for 10/100 2926 */ 2927 if ((hw->media_type == e1000_media_type_copper) && 2928 ((Adapter->link_speed == SPEED_100) || 2929 (Adapter->link_speed == SPEED_10))) { 2930 e1000_update_adaptive(hw); 2931 } 2932 /* 2933 * Set Timer Interrupts 2934 */ 2935 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2936 2937 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2938 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2939 2940 restart_watchdog_timer(Adapter); 2941 } 2942 2943 /* 2944 * The function e1000g_link_timer() is called when the timer for link setup 2945 * is expired, which indicates the completion of the link setup. The link 2946 * state will not be updated until the link setup is completed. And the 2947 * link state will not be sent to the upper layer through mac_link_update() 2948 * in this function. It will be updated in the local timer routine or the 2949 * interrupt service routine after the interface is started (plumbed). 2950 */ 2951 static void 2952 e1000g_link_timer(void *arg) 2953 { 2954 struct e1000g *Adapter = (struct e1000g *)arg; 2955 2956 mutex_enter(&Adapter->link_lock); 2957 Adapter->link_complete = B_TRUE; 2958 Adapter->link_tid = 0; 2959 mutex_exit(&Adapter->link_lock); 2960 } 2961 2962 /* 2963 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 2964 * 2965 * This function read the forced speed and duplex for 10/100 Mbps speeds 2966 * and also for 1000 Mbps speeds from the e1000g.conf file 2967 */ 2968 static void 2969 e1000g_force_speed_duplex(struct e1000g *Adapter) 2970 { 2971 int forced; 2972 struct e1000_mac_info *mac = &Adapter->shared.mac; 2973 struct e1000_phy_info *phy = &Adapter->shared.phy; 2974 2975 /* 2976 * get value out of config file 2977 */ 2978 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 2979 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2980 2981 switch (forced) { 2982 case GDIAG_10_HALF: 2983 /* 2984 * Disable Auto Negotiation 2985 */ 2986 mac->autoneg = B_FALSE; 2987 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2988 break; 2989 case GDIAG_10_FULL: 2990 /* 2991 * Disable Auto Negotiation 2992 */ 2993 mac->autoneg = B_FALSE; 2994 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2995 break; 2996 case GDIAG_100_HALF: 2997 /* 2998 * Disable Auto Negotiation 2999 */ 3000 mac->autoneg = B_FALSE; 3001 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3002 break; 3003 case GDIAG_100_FULL: 3004 /* 3005 * Disable Auto Negotiation 3006 */ 3007 mac->autoneg = B_FALSE; 3008 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3009 break; 3010 case GDIAG_1000_FULL: 3011 /* 3012 * The gigabit spec requires autonegotiation. Therefore, 3013 * when the user wants to force the speed to 1000Mbps, we 3014 * enable AutoNeg, but only allow the harware to advertise 3015 * 1000Mbps. This is different from 10/100 operation, where 3016 * we are allowed to link without any negotiation. 3017 */ 3018 mac->autoneg = B_TRUE; 3019 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3020 break; 3021 default: /* obey the setting of AutoNegAdvertised */ 3022 mac->autoneg = B_TRUE; 3023 phy->autoneg_advertised = 3024 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3025 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3026 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3027 break; 3028 } /* switch */ 3029 } 3030 3031 /* 3032 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3033 * 3034 * This function reads MaxFrameSize from e1000g.conf 3035 */ 3036 static void 3037 e1000g_get_max_frame_size(struct e1000g *Adapter) 3038 { 3039 int max_frame; 3040 struct e1000_mac_info *mac = &Adapter->shared.mac; 3041 struct e1000_phy_info *phy = &Adapter->shared.phy; 3042 3043 /* 3044 * get value out of config file 3045 */ 3046 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3047 3048 switch (max_frame) { 3049 case 0: 3050 mac->max_frame_size = ETHERMAX; 3051 break; 3052 case 1: 3053 mac->max_frame_size = FRAME_SIZE_UPTO_4K; 3054 break; 3055 case 2: 3056 mac->max_frame_size = FRAME_SIZE_UPTO_8K; 3057 break; 3058 case 3: 3059 if (mac->type < e1000_82571) 3060 mac->max_frame_size = FRAME_SIZE_UPTO_16K; 3061 else 3062 mac->max_frame_size = FRAME_SIZE_UPTO_9K; 3063 break; 3064 default: 3065 mac->max_frame_size = ETHERMAX; 3066 break; 3067 } /* switch */ 3068 3069 /* ich8 does not do jumbo frames */ 3070 if (mac->type == e1000_ich8lan) { 3071 mac->max_frame_size = ETHERMAX; 3072 } 3073 3074 /* ich9 does not do jumbo frames on one phy type */ 3075 if ((mac->type == e1000_ich9lan) && 3076 (phy->type == e1000_phy_ife)) { 3077 mac->max_frame_size = ETHERMAX; 3078 } 3079 } 3080 3081 static void 3082 arm_watchdog_timer(struct e1000g *Adapter) 3083 { 3084 Adapter->watchdog_tid = 3085 timeout(e1000g_local_timer, 3086 (void *)Adapter, 1 * drv_usectohz(1000000)); 3087 } 3088 #pragma inline(arm_watchdog_timer) 3089 3090 static void 3091 enable_watchdog_timer(struct e1000g *Adapter) 3092 { 3093 mutex_enter(&Adapter->watchdog_lock); 3094 3095 if (!Adapter->watchdog_timer_enabled) { 3096 Adapter->watchdog_timer_enabled = B_TRUE; 3097 Adapter->watchdog_timer_started = B_TRUE; 3098 arm_watchdog_timer(Adapter); 3099 } 3100 3101 mutex_exit(&Adapter->watchdog_lock); 3102 } 3103 3104 static void 3105 disable_watchdog_timer(struct e1000g *Adapter) 3106 { 3107 timeout_id_t tid; 3108 3109 mutex_enter(&Adapter->watchdog_lock); 3110 3111 Adapter->watchdog_timer_enabled = B_FALSE; 3112 Adapter->watchdog_timer_started = B_FALSE; 3113 tid = Adapter->watchdog_tid; 3114 Adapter->watchdog_tid = 0; 3115 3116 mutex_exit(&Adapter->watchdog_lock); 3117 3118 if (tid != 0) 3119 (void) untimeout(tid); 3120 } 3121 3122 static void 3123 start_watchdog_timer(struct e1000g *Adapter) 3124 { 3125 mutex_enter(&Adapter->watchdog_lock); 3126 3127 if (Adapter->watchdog_timer_enabled) { 3128 if (!Adapter->watchdog_timer_started) { 3129 Adapter->watchdog_timer_started = B_TRUE; 3130 arm_watchdog_timer(Adapter); 3131 } 3132 } 3133 3134 mutex_exit(&Adapter->watchdog_lock); 3135 } 3136 3137 static void 3138 restart_watchdog_timer(struct e1000g *Adapter) 3139 { 3140 mutex_enter(&Adapter->watchdog_lock); 3141 3142 if (Adapter->watchdog_timer_started) 3143 arm_watchdog_timer(Adapter); 3144 3145 mutex_exit(&Adapter->watchdog_lock); 3146 } 3147 3148 static void 3149 stop_watchdog_timer(struct e1000g *Adapter) 3150 { 3151 timeout_id_t tid; 3152 3153 mutex_enter(&Adapter->watchdog_lock); 3154 3155 Adapter->watchdog_timer_started = B_FALSE; 3156 tid = Adapter->watchdog_tid; 3157 Adapter->watchdog_tid = 0; 3158 3159 mutex_exit(&Adapter->watchdog_lock); 3160 3161 if (tid != 0) 3162 (void) untimeout(tid); 3163 } 3164 3165 static void 3166 stop_link_timer(struct e1000g *Adapter) 3167 { 3168 timeout_id_t tid; 3169 3170 /* Disable the link timer */ 3171 mutex_enter(&Adapter->link_lock); 3172 3173 tid = Adapter->link_tid; 3174 Adapter->link_tid = 0; 3175 3176 mutex_exit(&Adapter->link_lock); 3177 3178 if (tid != 0) 3179 (void) untimeout(tid); 3180 } 3181 3182 static void 3183 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3184 { 3185 timeout_id_t tid; 3186 3187 /* Disable the tx timer for 82547 chipset */ 3188 mutex_enter(&tx_ring->tx_lock); 3189 3190 tx_ring->timer_enable_82547 = B_FALSE; 3191 tid = tx_ring->timer_id_82547; 3192 tx_ring->timer_id_82547 = 0; 3193 3194 mutex_exit(&tx_ring->tx_lock); 3195 3196 if (tid != 0) 3197 (void) untimeout(tid); 3198 } 3199 3200 void 3201 e1000g_clear_interrupt(struct e1000g *Adapter) 3202 { 3203 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 3204 0xffffffff & ~E1000_IMS_RXSEQ); 3205 } 3206 3207 void 3208 e1000g_mask_interrupt(struct e1000g *Adapter) 3209 { 3210 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 3211 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 3212 3213 if (Adapter->tx_intr_enable) 3214 e1000g_mask_tx_interrupt(Adapter); 3215 } 3216 3217 void 3218 e1000g_clear_all_interrupts(struct e1000g *Adapter) 3219 { 3220 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 3221 } 3222 3223 void 3224 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 3225 { 3226 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 3227 } 3228 3229 void 3230 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 3231 { 3232 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 3233 } 3234 3235 static void 3236 e1000g_smartspeed(struct e1000g *Adapter) 3237 { 3238 struct e1000_hw *hw = &Adapter->shared; 3239 uint16_t phy_status; 3240 uint16_t phy_ctrl; 3241 3242 /* 3243 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3244 * advertising 1000Full, we don't even use the workaround 3245 */ 3246 if ((hw->phy.type != e1000_phy_igp) || 3247 !hw->mac.autoneg || 3248 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 3249 return; 3250 3251 /* 3252 * True if this is the first call of this function or after every 3253 * 30 seconds of not having link 3254 */ 3255 if (Adapter->smartspeed == 0) { 3256 /* 3257 * If Master/Slave config fault is asserted twice, we 3258 * assume back-to-back 3259 */ 3260 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3261 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3262 return; 3263 3264 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3265 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3266 return; 3267 /* 3268 * We're assuming back-2-back because our status register 3269 * insists! there's a fault in the master/slave 3270 * relationship that was "negotiated" 3271 */ 3272 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3273 /* 3274 * Is the phy configured for manual configuration of 3275 * master/slave? 3276 */ 3277 if (phy_ctrl & CR_1000T_MS_ENABLE) { 3278 /* 3279 * Yes. Then disable manual configuration (enable 3280 * auto configuration) of master/slave 3281 */ 3282 phy_ctrl &= ~CR_1000T_MS_ENABLE; 3283 e1000_write_phy_reg(hw, 3284 PHY_1000T_CTRL, phy_ctrl); 3285 /* 3286 * Effectively starting the clock 3287 */ 3288 Adapter->smartspeed++; 3289 /* 3290 * Restart autonegotiation 3291 */ 3292 if (!e1000_phy_setup_autoneg(hw) && 3293 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 3294 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 3295 MII_CR_RESTART_AUTO_NEG); 3296 e1000_write_phy_reg(hw, 3297 PHY_CONTROL, phy_ctrl); 3298 } 3299 } 3300 return; 3301 /* 3302 * Has 6 seconds transpired still without link? Remember, 3303 * you should reset the smartspeed counter once you obtain 3304 * link 3305 */ 3306 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 3307 /* 3308 * Yes. Remember, we did at the start determine that 3309 * there's a master/slave configuration fault, so we're 3310 * still assuming there's someone on the other end, but we 3311 * just haven't yet been able to talk to it. We then 3312 * re-enable auto configuration of master/slave to see if 3313 * we're running 2/3 pair cables. 3314 */ 3315 /* 3316 * If still no link, perhaps using 2/3 pair cable 3317 */ 3318 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3319 phy_ctrl |= CR_1000T_MS_ENABLE; 3320 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 3321 /* 3322 * Restart autoneg with phy enabled for manual 3323 * configuration of master/slave 3324 */ 3325 if (!e1000_phy_setup_autoneg(hw) && 3326 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 3327 phy_ctrl |= 3328 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3329 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3330 } 3331 /* 3332 * Hopefully, there are no more faults and we've obtained 3333 * link as a result. 3334 */ 3335 } 3336 /* 3337 * Restart process after E1000_SMARTSPEED_MAX iterations (30 3338 * seconds) 3339 */ 3340 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 3341 Adapter->smartspeed = 0; 3342 } 3343 3344 static boolean_t 3345 is_valid_mac_addr(uint8_t *mac_addr) 3346 { 3347 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3348 const uint8_t addr_test2[6] = 3349 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3350 3351 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3352 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3353 return (B_FALSE); 3354 3355 return (B_TRUE); 3356 } 3357 3358 /* 3359 * e1000g_stall_check - check for tx stall 3360 * 3361 * This function checks if the adapter is stalled (in transmit). 3362 * 3363 * It is called each time the watchdog timeout is invoked. 3364 * If the transmit descriptor reclaim continuously fails, 3365 * the watchdog value will increment by 1. If the watchdog 3366 * value exceeds the threshold, the adapter is assumed to 3367 * have stalled and need to be reset. 3368 */ 3369 static boolean_t 3370 e1000g_stall_check(struct e1000g *Adapter) 3371 { 3372 e1000g_tx_ring_t *tx_ring; 3373 3374 tx_ring = Adapter->tx_ring; 3375 3376 if (Adapter->link_state != LINK_STATE_UP) 3377 return (B_FALSE); 3378 3379 if (tx_ring->recycle_fail > 0) 3380 tx_ring->stall_watchdog++; 3381 else 3382 tx_ring->stall_watchdog = 0; 3383 3384 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 3385 return (B_FALSE); 3386 3387 tx_ring->stall_watchdog = 0; 3388 tx_ring->recycle_fail = 0; 3389 3390 return (B_TRUE); 3391 } 3392 3393 #ifdef E1000G_DEBUG 3394 static enum ioc_reply 3395 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3396 { 3397 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3398 e1000g_peekpoke_t *ppd; 3399 uint64_t mem_va; 3400 uint64_t maxoff; 3401 boolean_t peek; 3402 3403 switch (iocp->ioc_cmd) { 3404 3405 case E1000G_IOC_REG_PEEK: 3406 peek = B_TRUE; 3407 break; 3408 3409 case E1000G_IOC_REG_POKE: 3410 peek = B_FALSE; 3411 break; 3412 3413 deault: 3414 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 3415 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3416 iocp->ioc_cmd); 3417 return (IOC_INVAL); 3418 } 3419 3420 /* 3421 * Validate format of ioctl 3422 */ 3423 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3424 return (IOC_INVAL); 3425 if (mp->b_cont == NULL) 3426 return (IOC_INVAL); 3427 3428 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3429 3430 /* 3431 * Validate request parameters 3432 */ 3433 switch (ppd->pp_acc_space) { 3434 3435 default: 3436 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 3437 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3438 ppd->pp_acc_space); 3439 return (IOC_INVAL); 3440 3441 case E1000G_PP_SPACE_REG: 3442 /* 3443 * Memory-mapped I/O space 3444 */ 3445 ASSERT(ppd->pp_acc_size == 4); 3446 if (ppd->pp_acc_size != 4) 3447 return (IOC_INVAL); 3448 3449 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3450 return (IOC_INVAL); 3451 3452 mem_va = 0; 3453 maxoff = 0x10000; 3454 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3455 break; 3456 3457 case E1000G_PP_SPACE_E1000G: 3458 /* 3459 * E1000g data structure! 3460 */ 3461 mem_va = (uintptr_t)e1000gp; 3462 maxoff = sizeof (struct e1000g); 3463 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3464 break; 3465 3466 } 3467 3468 if (ppd->pp_acc_offset >= maxoff) 3469 return (IOC_INVAL); 3470 3471 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3472 return (IOC_INVAL); 3473 3474 /* 3475 * All OK - go! 3476 */ 3477 ppd->pp_acc_offset += mem_va; 3478 (*ppfn)(e1000gp, ppd); 3479 return (peek ? IOC_REPLY : IOC_ACK); 3480 } 3481 3482 static void 3483 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3484 { 3485 ddi_acc_handle_t handle; 3486 uint32_t *regaddr; 3487 3488 handle = e1000gp->osdep.reg_handle; 3489 regaddr = 3490 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 3491 3492 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3493 } 3494 3495 static void 3496 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3497 { 3498 ddi_acc_handle_t handle; 3499 uint32_t *regaddr; 3500 uint32_t value; 3501 3502 handle = e1000gp->osdep.reg_handle; 3503 regaddr = 3504 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 3505 value = (uint32_t)ppd->pp_acc_data; 3506 3507 ddi_put32(handle, regaddr, value); 3508 } 3509 3510 static void 3511 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3512 { 3513 uint64_t value; 3514 void *vaddr; 3515 3516 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3517 3518 switch (ppd->pp_acc_size) { 3519 case 1: 3520 value = *(uint8_t *)vaddr; 3521 break; 3522 3523 case 2: 3524 value = *(uint16_t *)vaddr; 3525 break; 3526 3527 case 4: 3528 value = *(uint32_t *)vaddr; 3529 break; 3530 3531 case 8: 3532 value = *(uint64_t *)vaddr; 3533 break; 3534 } 3535 3536 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 3537 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3538 (void *)e1000gp, (void *)ppd, value, vaddr); 3539 3540 ppd->pp_acc_data = value; 3541 } 3542 3543 static void 3544 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3545 { 3546 uint64_t value; 3547 void *vaddr; 3548 3549 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3550 value = ppd->pp_acc_data; 3551 3552 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 3553 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3554 (void *)e1000gp, (void *)ppd, value, vaddr); 3555 3556 switch (ppd->pp_acc_size) { 3557 case 1: 3558 *(uint8_t *)vaddr = (uint8_t)value; 3559 break; 3560 3561 case 2: 3562 *(uint16_t *)vaddr = (uint16_t)value; 3563 break; 3564 3565 case 4: 3566 *(uint32_t *)vaddr = (uint32_t)value; 3567 break; 3568 3569 case 8: 3570 *(uint64_t *)vaddr = (uint64_t)value; 3571 break; 3572 } 3573 } 3574 #endif 3575 3576 /* 3577 * Loopback Support 3578 */ 3579 static lb_property_t lb_normal = 3580 { normal, "normal", E1000G_LB_NONE }; 3581 static lb_property_t lb_external1000 = 3582 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3583 static lb_property_t lb_external100 = 3584 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3585 static lb_property_t lb_external10 = 3586 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3587 static lb_property_t lb_phy = 3588 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3589 3590 static enum ioc_reply 3591 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3592 { 3593 lb_info_sz_t *lbsp; 3594 lb_property_t *lbpp; 3595 struct e1000_hw *hw; 3596 uint32_t *lbmp; 3597 uint32_t size; 3598 uint32_t value; 3599 3600 hw = &Adapter->shared; 3601 3602 if (mp->b_cont == NULL) 3603 return (IOC_INVAL); 3604 3605 switch (iocp->ioc_cmd) { 3606 default: 3607 return (IOC_INVAL); 3608 3609 case LB_GET_INFO_SIZE: 3610 size = sizeof (lb_info_sz_t); 3611 if (iocp->ioc_count != size) 3612 return (IOC_INVAL); 3613 3614 rw_enter(&Adapter->chip_lock, RW_WRITER); 3615 e1000g_get_phy_state(Adapter); 3616 3617 /* 3618 * Workaround for hardware faults. In order to get a stable 3619 * state of phy, we will wait for a specific interval and 3620 * try again. The time delay is an experiential value based 3621 * on our testing. 3622 */ 3623 msec_delay(100); 3624 e1000g_get_phy_state(Adapter); 3625 rw_exit(&Adapter->chip_lock); 3626 3627 value = sizeof (lb_normal); 3628 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3629 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3630 (hw->media_type == e1000_media_type_fiber) || 3631 (hw->media_type == e1000_media_type_internal_serdes)) { 3632 value += sizeof (lb_phy); 3633 switch (hw->mac.type) { 3634 case e1000_82571: 3635 case e1000_82572: 3636 value += sizeof (lb_external1000); 3637 break; 3638 } 3639 } 3640 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3641 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3642 value += sizeof (lb_external100); 3643 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3644 value += sizeof (lb_external10); 3645 3646 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3647 *lbsp = value; 3648 break; 3649 3650 case LB_GET_INFO: 3651 value = sizeof (lb_normal); 3652 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3653 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3654 (hw->media_type == e1000_media_type_fiber) || 3655 (hw->media_type == e1000_media_type_internal_serdes)) { 3656 value += sizeof (lb_phy); 3657 switch (hw->mac.type) { 3658 case e1000_82571: 3659 case e1000_82572: 3660 value += sizeof (lb_external1000); 3661 break; 3662 } 3663 } 3664 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3665 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3666 value += sizeof (lb_external100); 3667 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3668 value += sizeof (lb_external10); 3669 3670 size = value; 3671 if (iocp->ioc_count != size) 3672 return (IOC_INVAL); 3673 3674 value = 0; 3675 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3676 lbpp[value++] = lb_normal; 3677 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3678 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3679 (hw->media_type == e1000_media_type_fiber) || 3680 (hw->media_type == e1000_media_type_internal_serdes)) { 3681 lbpp[value++] = lb_phy; 3682 switch (hw->mac.type) { 3683 case e1000_82571: 3684 case e1000_82572: 3685 lbpp[value++] = lb_external1000; 3686 break; 3687 } 3688 } 3689 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3690 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3691 lbpp[value++] = lb_external100; 3692 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 3693 lbpp[value++] = lb_external10; 3694 break; 3695 3696 case LB_GET_MODE: 3697 size = sizeof (uint32_t); 3698 if (iocp->ioc_count != size) 3699 return (IOC_INVAL); 3700 3701 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3702 *lbmp = Adapter->loopback_mode; 3703 break; 3704 3705 case LB_SET_MODE: 3706 size = 0; 3707 if (iocp->ioc_count != sizeof (uint32_t)) 3708 return (IOC_INVAL); 3709 3710 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3711 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3712 return (IOC_INVAL); 3713 break; 3714 } 3715 3716 iocp->ioc_count = size; 3717 iocp->ioc_error = 0; 3718 3719 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 3720 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3721 return (IOC_INVAL); 3722 } 3723 3724 return (IOC_REPLY); 3725 } 3726 3727 static boolean_t 3728 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3729 { 3730 struct e1000_hw *hw; 3731 int i, times; 3732 boolean_t link_up; 3733 3734 if (mode == Adapter->loopback_mode) 3735 return (B_TRUE); 3736 3737 hw = &Adapter->shared; 3738 times = 0; 3739 3740 Adapter->loopback_mode = mode; 3741 3742 if (mode == E1000G_LB_NONE) { 3743 /* Reset the chip */ 3744 hw->phy.wait_for_link = B_TRUE; 3745 (void) e1000g_reset(Adapter); 3746 hw->phy.wait_for_link = B_FALSE; 3747 return (B_TRUE); 3748 } 3749 3750 again: 3751 3752 rw_enter(&Adapter->chip_lock, RW_WRITER); 3753 3754 switch (mode) { 3755 default: 3756 rw_exit(&Adapter->chip_lock); 3757 return (B_FALSE); 3758 3759 case E1000G_LB_EXTERNAL_1000: 3760 e1000g_set_external_loopback_1000(Adapter); 3761 break; 3762 3763 case E1000G_LB_EXTERNAL_100: 3764 e1000g_set_external_loopback_100(Adapter); 3765 break; 3766 3767 case E1000G_LB_EXTERNAL_10: 3768 e1000g_set_external_loopback_10(Adapter); 3769 break; 3770 3771 case E1000G_LB_INTERNAL_PHY: 3772 e1000g_set_internal_loopback(Adapter); 3773 break; 3774 } 3775 3776 times++; 3777 3778 rw_exit(&Adapter->chip_lock); 3779 3780 /* Wait for link up */ 3781 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 3782 msec_delay(100); 3783 3784 rw_enter(&Adapter->chip_lock, RW_WRITER); 3785 3786 link_up = e1000g_link_up(Adapter); 3787 3788 rw_exit(&Adapter->chip_lock); 3789 3790 if (!link_up) { 3791 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3792 "Failed to get the link up"); 3793 if (times < 2) { 3794 /* Reset the link */ 3795 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3796 "Reset the link ..."); 3797 (void) e1000g_reset(Adapter); 3798 goto again; 3799 } 3800 } 3801 3802 return (B_TRUE); 3803 } 3804 3805 /* 3806 * The following loopback settings are from Intel's technical 3807 * document - "How To Loopback". All the register settings and 3808 * time delay values are directly inherited from the document 3809 * without more explanations available. 3810 */ 3811 static void 3812 e1000g_set_internal_loopback(struct e1000g *Adapter) 3813 { 3814 struct e1000_hw *hw; 3815 uint32_t ctrl; 3816 uint32_t status; 3817 uint16_t phy_ctrl; 3818 uint32_t txcw; 3819 3820 hw = &Adapter->shared; 3821 3822 /* Disable Smart Power Down */ 3823 phy_spd_state(hw, B_FALSE); 3824 3825 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3826 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3827 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3828 3829 switch (hw->mac.type) { 3830 case e1000_82540: 3831 case e1000_82545: 3832 case e1000_82545_rev_3: 3833 case e1000_82546: 3834 case e1000_82546_rev_3: 3835 case e1000_82573: 3836 /* Auto-MDI/MDIX off */ 3837 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3838 /* Reset PHY to update Auto-MDI/MDIX */ 3839 e1000_write_phy_reg(hw, PHY_CONTROL, 3840 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3841 /* Reset PHY to auto-neg off and force 1000 */ 3842 e1000_write_phy_reg(hw, PHY_CONTROL, 3843 phy_ctrl | MII_CR_RESET); 3844 /* 3845 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3846 * See comments above e1000g_set_internal_loopback() for the 3847 * background. 3848 */ 3849 e1000_write_phy_reg(hw, 29, 0x001F); 3850 e1000_write_phy_reg(hw, 30, 0x8FFC); 3851 e1000_write_phy_reg(hw, 29, 0x001A); 3852 e1000_write_phy_reg(hw, 30, 0x8FF0); 3853 break; 3854 } 3855 3856 /* Set loopback */ 3857 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 3858 3859 msec_delay(250); 3860 3861 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3862 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3863 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3864 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3865 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3866 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3867 E1000_CTRL_FD); /* Force Duplex to FULL */ 3868 3869 switch (hw->mac.type) { 3870 case e1000_82540: 3871 case e1000_82545: 3872 case e1000_82545_rev_3: 3873 case e1000_82546: 3874 case e1000_82546_rev_3: 3875 /* 3876 * For some serdes we'll need to commit the writes now 3877 * so that the status is updated on link 3878 */ 3879 if (hw->media_type == e1000_media_type_internal_serdes) { 3880 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3881 msec_delay(100); 3882 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3883 } 3884 3885 if (hw->media_type == e1000_media_type_copper) { 3886 /* Invert Loss of Signal */ 3887 ctrl |= E1000_CTRL_ILOS; 3888 } else { 3889 /* Set ILOS on fiber nic if half duplex is detected */ 3890 status = E1000_READ_REG(hw, E1000_STATUS); 3891 if ((status & E1000_STATUS_FD) == 0) 3892 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3893 } 3894 break; 3895 3896 case e1000_82571: 3897 case e1000_82572: 3898 /* 3899 * The fiber/SerDes versions of this adapter do not contain an 3900 * accessible PHY. Therefore, loopback beyond MAC must be done 3901 * using SerDes analog loopback. 3902 */ 3903 if (hw->media_type != e1000_media_type_copper) { 3904 status = E1000_READ_REG(hw, E1000_STATUS); 3905 /* Set ILOS on fiber nic if half duplex is detected */ 3906 if (((status & E1000_STATUS_LU) == 0) || 3907 ((status & E1000_STATUS_FD) == 0) || 3908 (hw->media_type == 3909 e1000_media_type_internal_serdes)) 3910 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3911 3912 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3913 txcw = E1000_READ_REG(hw, E1000_TXCW); 3914 txcw &= ~((uint32_t)1 << 31); 3915 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 3916 3917 /* 3918 * Write 0x410 to Serdes Control register 3919 * to enable Serdes analog loopback 3920 */ 3921 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 3922 msec_delay(10); 3923 } 3924 break; 3925 3926 case e1000_82573: 3927 ctrl |= E1000_CTRL_ILOS; 3928 break; 3929 } 3930 3931 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3932 3933 } 3934 3935 static void 3936 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3937 { 3938 struct e1000_hw *hw; 3939 uint32_t rctl; 3940 uint32_t ctrl_ext; 3941 uint32_t ctrl; 3942 uint32_t status; 3943 uint32_t txcw; 3944 3945 hw = &Adapter->shared; 3946 3947 /* Disable Smart Power Down */ 3948 phy_spd_state(hw, B_FALSE); 3949 3950 switch (hw->media_type) { 3951 case e1000_media_type_copper: 3952 /* Force link up (Must be done before the PHY writes) */ 3953 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3954 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3955 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3956 3957 rctl = E1000_READ_REG(hw, E1000_RCTL); 3958 rctl |= (E1000_RCTL_EN | 3959 E1000_RCTL_SBP | 3960 E1000_RCTL_UPE | 3961 E1000_RCTL_MPE | 3962 E1000_RCTL_LPE | 3963 E1000_RCTL_BAM); /* 0x803E */ 3964 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3965 3966 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3967 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3968 E1000_CTRL_EXT_SDP6_DATA | 3969 E1000_CTRL_EXT_SDP7_DATA | 3970 E1000_CTRL_EXT_SDP4_DIR | 3971 E1000_CTRL_EXT_SDP6_DIR | 3972 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3973 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3974 3975 /* 3976 * This sequence tunes the PHY's SDP and no customer 3977 * settable values. For background, see comments above 3978 * e1000g_set_internal_loopback(). 3979 */ 3980 e1000_write_phy_reg(hw, 0x0, 0x140); 3981 msec_delay(10); 3982 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3983 e1000_write_phy_reg(hw, 0x12, 0xC10); 3984 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3985 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3986 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3987 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3988 3989 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3990 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3991 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3992 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3993 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3994 3995 msec_delay(50); 3996 break; 3997 case e1000_media_type_fiber: 3998 case e1000_media_type_internal_serdes: 3999 status = E1000_READ_REG(hw, E1000_STATUS); 4000 if (((status & E1000_STATUS_LU) == 0) || 4001 (hw->media_type == e1000_media_type_internal_serdes)) { 4002 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4003 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4004 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4005 } 4006 4007 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4008 txcw = E1000_READ_REG(hw, E1000_TXCW); 4009 txcw &= ~((uint32_t)1 << 31); 4010 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4011 4012 /* 4013 * Write 0x410 to Serdes Control register 4014 * to enable Serdes analog loopback 4015 */ 4016 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4017 msec_delay(10); 4018 break; 4019 default: 4020 break; 4021 } 4022 } 4023 4024 static void 4025 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4026 { 4027 struct e1000_hw *hw; 4028 uint32_t ctrl; 4029 uint16_t phy_ctrl; 4030 4031 hw = &Adapter->shared; 4032 4033 /* Disable Smart Power Down */ 4034 phy_spd_state(hw, B_FALSE); 4035 4036 phy_ctrl = (MII_CR_FULL_DUPLEX | 4037 MII_CR_SPEED_100); 4038 4039 /* Force 100/FD, reset PHY */ 4040 e1000_write_phy_reg(hw, PHY_CONTROL, 4041 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4042 msec_delay(10); 4043 4044 /* Force 100/FD */ 4045 e1000_write_phy_reg(hw, PHY_CONTROL, 4046 phy_ctrl); /* 0x2100 */ 4047 msec_delay(10); 4048 4049 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4050 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4051 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4052 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4053 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4054 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4055 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4056 E1000_CTRL_FD); /* Force Duplex to FULL */ 4057 4058 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4059 } 4060 4061 static void 4062 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4063 { 4064 struct e1000_hw *hw; 4065 uint32_t ctrl; 4066 uint16_t phy_ctrl; 4067 4068 hw = &Adapter->shared; 4069 4070 /* Disable Smart Power Down */ 4071 phy_spd_state(hw, B_FALSE); 4072 4073 phy_ctrl = (MII_CR_FULL_DUPLEX | 4074 MII_CR_SPEED_10); 4075 4076 /* Force 10/FD, reset PHY */ 4077 e1000_write_phy_reg(hw, PHY_CONTROL, 4078 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4079 msec_delay(10); 4080 4081 /* Force 10/FD */ 4082 e1000_write_phy_reg(hw, PHY_CONTROL, 4083 phy_ctrl); /* 0x0100 */ 4084 msec_delay(10); 4085 4086 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4087 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4088 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4089 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4090 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4091 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4092 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4093 E1000_CTRL_FD); /* Force Duplex to FULL */ 4094 4095 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4096 } 4097 4098 #ifdef __sparc 4099 static boolean_t 4100 e1000g_find_mac_address(struct e1000g *Adapter) 4101 { 4102 struct e1000_hw *hw = &Adapter->shared; 4103 uchar_t *bytes; 4104 struct ether_addr sysaddr; 4105 uint_t nelts; 4106 int err; 4107 boolean_t found = B_FALSE; 4108 4109 /* 4110 * The "vendor's factory-set address" may already have 4111 * been extracted from the chip, but if the property 4112 * "local-mac-address" is set we use that instead. 4113 * 4114 * We check whether it looks like an array of 6 4115 * bytes (which it should, if OBP set it). If we can't 4116 * make sense of it this way, we'll ignore it. 4117 */ 4118 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4119 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4120 if (err == DDI_PROP_SUCCESS) { 4121 if (nelts == ETHERADDRL) { 4122 while (nelts--) 4123 hw->mac.addr[nelts] = bytes[nelts]; 4124 found = B_TRUE; 4125 } 4126 ddi_prop_free(bytes); 4127 } 4128 4129 /* 4130 * Look up the OBP property "local-mac-address?". If the user has set 4131 * 'local-mac-address? = false', use "the system address" instead. 4132 */ 4133 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4134 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4135 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4136 if (localetheraddr(NULL, &sysaddr) != 0) { 4137 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4138 found = B_TRUE; 4139 } 4140 } 4141 ddi_prop_free(bytes); 4142 } 4143 4144 /* 4145 * Finally(!), if there's a valid "mac-address" property (created 4146 * if we netbooted from this interface), we must use this instead 4147 * of any of the above to ensure that the NFS/install server doesn't 4148 * get confused by the address changing as Solaris takes over! 4149 */ 4150 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4151 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 4152 if (err == DDI_PROP_SUCCESS) { 4153 if (nelts == ETHERADDRL) { 4154 while (nelts--) 4155 hw->mac.addr[nelts] = bytes[nelts]; 4156 found = B_TRUE; 4157 } 4158 ddi_prop_free(bytes); 4159 } 4160 4161 if (found) { 4162 bcopy(hw->mac.addr, hw->mac.perm_addr, 4163 ETHERADDRL); 4164 } 4165 4166 return (found); 4167 } 4168 #endif 4169 4170 static int 4171 e1000g_add_intrs(struct e1000g *Adapter) 4172 { 4173 dev_info_t *devinfo; 4174 int intr_types; 4175 int rc; 4176 4177 devinfo = Adapter->dip; 4178 4179 /* Get supported interrupt types */ 4180 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4181 4182 if (rc != DDI_SUCCESS) { 4183 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4184 "Get supported interrupt types failed: %d\n", rc); 4185 return (DDI_FAILURE); 4186 } 4187 4188 /* 4189 * Based on Intel Technical Advisory document (TA-160), there are some 4190 * cases where some older Intel PCI-X NICs may "advertise" to the OS 4191 * that it supports MSI, but in fact has problems. 4192 * So we should only enable MSI for PCI-E NICs and disable MSI for old 4193 * PCI/PCI-X NICs. 4194 */ 4195 if (Adapter->shared.mac.type < e1000_82571) 4196 Adapter->msi_enabled = B_FALSE; 4197 4198 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 4199 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 4200 4201 if (rc != DDI_SUCCESS) { 4202 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4203 "Add MSI failed, trying Legacy interrupts\n"); 4204 } else { 4205 Adapter->intr_type = DDI_INTR_TYPE_MSI; 4206 } 4207 } 4208 4209 if ((Adapter->intr_type == 0) && 4210 (intr_types & DDI_INTR_TYPE_FIXED)) { 4211 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 4212 4213 if (rc != DDI_SUCCESS) { 4214 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4215 "Add Legacy interrupts failed\n"); 4216 return (DDI_FAILURE); 4217 } 4218 4219 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4220 } 4221 4222 if (Adapter->intr_type == 0) { 4223 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4224 "No interrupts registered\n"); 4225 return (DDI_FAILURE); 4226 } 4227 4228 return (DDI_SUCCESS); 4229 } 4230 4231 /* 4232 * e1000g_intr_add() handles MSI/Legacy interrupts 4233 */ 4234 static int 4235 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4236 { 4237 dev_info_t *devinfo; 4238 int count, avail, actual; 4239 int x, y, rc, inum = 0; 4240 int flag; 4241 ddi_intr_handler_t *intr_handler; 4242 4243 devinfo = Adapter->dip; 4244 4245 /* get number of interrupts */ 4246 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4247 if ((rc != DDI_SUCCESS) || (count == 0)) { 4248 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4249 "Get interrupt number failed. Return: %d, count: %d\n", 4250 rc, count); 4251 return (DDI_FAILURE); 4252 } 4253 4254 /* get number of available interrupts */ 4255 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4256 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4257 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4258 "Get interrupt available number failed. " 4259 "Return: %d, available: %d\n", rc, avail); 4260 return (DDI_FAILURE); 4261 } 4262 4263 if (avail < count) { 4264 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4265 "Interrupts count: %d, available: %d\n", 4266 count, avail); 4267 } 4268 4269 /* Allocate an array of interrupt handles */ 4270 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4271 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4272 4273 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4274 flag = DDI_INTR_ALLOC_NORMAL; 4275 4276 /* call ddi_intr_alloc() */ 4277 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 4278 count, &actual, flag); 4279 4280 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4281 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4282 "Allocate interrupts failed: %d\n", rc); 4283 4284 kmem_free(Adapter->htable, Adapter->intr_size); 4285 return (DDI_FAILURE); 4286 } 4287 4288 if (actual < count) { 4289 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4290 "Interrupts requested: %d, received: %d\n", 4291 count, actual); 4292 } 4293 4294 Adapter->intr_cnt = actual; 4295 4296 /* Get priority for first msi, assume remaining are all the same */ 4297 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 4298 4299 if (rc != DDI_SUCCESS) { 4300 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4301 "Get interrupt priority failed: %d\n", rc); 4302 4303 /* Free already allocated intr */ 4304 for (y = 0; y < actual; y++) 4305 (void) ddi_intr_free(Adapter->htable[y]); 4306 4307 kmem_free(Adapter->htable, Adapter->intr_size); 4308 return (DDI_FAILURE); 4309 } 4310 4311 /* 4312 * In Legacy Interrupt mode, for PCI-Express adapters, we should 4313 * use the interrupt service routine e1000g_intr_pciexpress() 4314 * to avoid interrupt stealing when sharing interrupt with other 4315 * devices. 4316 */ 4317 if (Adapter->shared.mac.type < e1000_82571) 4318 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 4319 else 4320 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 4321 4322 /* Call ddi_intr_add_handler() */ 4323 for (x = 0; x < actual; x++) { 4324 rc = ddi_intr_add_handler(Adapter->htable[x], 4325 intr_handler, (caddr_t)Adapter, NULL); 4326 4327 if (rc != DDI_SUCCESS) { 4328 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4329 "Add interrupt handler failed: %d\n", rc); 4330 4331 /* Remove already added handler */ 4332 for (y = 0; y < x; y++) 4333 (void) ddi_intr_remove_handler( 4334 Adapter->htable[y]); 4335 4336 /* Free already allocated intr */ 4337 for (y = 0; y < actual; y++) 4338 (void) ddi_intr_free(Adapter->htable[y]); 4339 4340 kmem_free(Adapter->htable, Adapter->intr_size); 4341 return (DDI_FAILURE); 4342 } 4343 } 4344 4345 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 4346 4347 if (rc != DDI_SUCCESS) { 4348 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4349 "Get interrupt cap failed: %d\n", rc); 4350 4351 /* Free already allocated intr */ 4352 for (y = 0; y < actual; y++) { 4353 (void) ddi_intr_remove_handler(Adapter->htable[y]); 4354 (void) ddi_intr_free(Adapter->htable[y]); 4355 } 4356 4357 kmem_free(Adapter->htable, Adapter->intr_size); 4358 return (DDI_FAILURE); 4359 } 4360 4361 return (DDI_SUCCESS); 4362 } 4363 4364 static int 4365 e1000g_rem_intrs(struct e1000g *Adapter) 4366 { 4367 int x; 4368 int rc; 4369 4370 for (x = 0; x < Adapter->intr_cnt; x++) { 4371 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4372 if (rc != DDI_SUCCESS) { 4373 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4374 "Remove intr handler failed: %d\n", rc); 4375 return (DDI_FAILURE); 4376 } 4377 4378 rc = ddi_intr_free(Adapter->htable[x]); 4379 if (rc != DDI_SUCCESS) { 4380 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4381 "Free intr failed: %d\n", rc); 4382 return (DDI_FAILURE); 4383 } 4384 } 4385 4386 kmem_free(Adapter->htable, Adapter->intr_size); 4387 4388 return (DDI_SUCCESS); 4389 } 4390 4391 static int 4392 e1000g_enable_intrs(struct e1000g *Adapter) 4393 { 4394 int x; 4395 int rc; 4396 4397 /* Enable interrupts */ 4398 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4399 /* Call ddi_intr_block_enable() for MSI */ 4400 rc = ddi_intr_block_enable(Adapter->htable, 4401 Adapter->intr_cnt); 4402 if (rc != DDI_SUCCESS) { 4403 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4404 "Enable block intr failed: %d\n", rc); 4405 return (DDI_FAILURE); 4406 } 4407 } else { 4408 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4409 for (x = 0; x < Adapter->intr_cnt; x++) { 4410 rc = ddi_intr_enable(Adapter->htable[x]); 4411 if (rc != DDI_SUCCESS) { 4412 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4413 "Enable intr failed: %d\n", rc); 4414 return (DDI_FAILURE); 4415 } 4416 } 4417 } 4418 4419 return (DDI_SUCCESS); 4420 } 4421 4422 static int 4423 e1000g_disable_intrs(struct e1000g *Adapter) 4424 { 4425 int x; 4426 int rc; 4427 4428 /* Disable all interrupts */ 4429 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4430 rc = ddi_intr_block_disable(Adapter->htable, 4431 Adapter->intr_cnt); 4432 if (rc != DDI_SUCCESS) { 4433 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4434 "Disable block intr failed: %d\n", rc); 4435 return (DDI_FAILURE); 4436 } 4437 } else { 4438 for (x = 0; x < Adapter->intr_cnt; x++) { 4439 rc = ddi_intr_disable(Adapter->htable[x]); 4440 if (rc != DDI_SUCCESS) { 4441 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4442 "Disable intr failed: %d\n", rc); 4443 return (DDI_FAILURE); 4444 } 4445 } 4446 } 4447 4448 return (DDI_SUCCESS); 4449 } 4450 4451 /* 4452 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 4453 */ 4454 static void 4455 e1000g_get_phy_state(struct e1000g *Adapter) 4456 { 4457 struct e1000_hw *hw = &Adapter->shared; 4458 4459 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 4460 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 4461 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 4462 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 4463 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 4464 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 4465 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 4466 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 4467 } 4468 4469 /* 4470 * FMA support 4471 */ 4472 4473 int 4474 e1000g_check_acc_handle(ddi_acc_handle_t handle) 4475 { 4476 ddi_fm_error_t de; 4477 4478 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4479 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4480 return (de.fme_status); 4481 } 4482 4483 int 4484 e1000g_check_dma_handle(ddi_dma_handle_t handle) 4485 { 4486 ddi_fm_error_t de; 4487 4488 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4489 return (de.fme_status); 4490 } 4491 4492 /* 4493 * The IO fault service error handling callback function 4494 */ 4495 static int 4496 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4497 { 4498 /* 4499 * as the driver can always deal with an error in any dma or 4500 * access handle, we can just return the fme_status value. 4501 */ 4502 pci_ereport_post(dip, err, NULL); 4503 return (err->fme_status); 4504 } 4505 4506 static void 4507 e1000g_fm_init(struct e1000g *Adapter) 4508 { 4509 ddi_iblock_cookie_t iblk; 4510 int fma_acc_flag, fma_dma_flag; 4511 4512 /* Only register with IO Fault Services if we have some capability */ 4513 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4514 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4515 fma_acc_flag = 1; 4516 } else { 4517 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4518 fma_acc_flag = 0; 4519 } 4520 4521 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4522 fma_dma_flag = 1; 4523 } else { 4524 fma_dma_flag = 0; 4525 } 4526 4527 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 4528 4529 if (Adapter->fm_capabilities) { 4530 4531 /* Register capabilities with IO Fault Services */ 4532 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 4533 4534 /* 4535 * Initialize pci ereport capabilities if ereport capable 4536 */ 4537 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 4538 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4539 pci_ereport_setup(Adapter->dip); 4540 4541 /* 4542 * Register error callback if error callback capable 4543 */ 4544 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4545 ddi_fm_handler_register(Adapter->dip, 4546 e1000g_fm_error_cb, (void*) Adapter); 4547 } 4548 } 4549 4550 static void 4551 e1000g_fm_fini(struct e1000g *Adapter) 4552 { 4553 /* Only unregister FMA capabilities if we registered some */ 4554 if (Adapter->fm_capabilities) { 4555 4556 /* 4557 * Release any resources allocated by pci_ereport_setup() 4558 */ 4559 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 4560 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4561 pci_ereport_teardown(Adapter->dip); 4562 4563 /* 4564 * Un-register error callback if error callback capable 4565 */ 4566 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 4567 ddi_fm_handler_unregister(Adapter->dip); 4568 4569 /* Unregister from IO Fault Services */ 4570 ddi_fm_fini(Adapter->dip); 4571 } 4572 } 4573 4574 void 4575 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 4576 { 4577 uint64_t ena; 4578 char buf[FM_MAX_CLASS]; 4579 4580 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4581 ena = fm_ena_generate(0, FM_ENA_FMT1); 4582 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 4583 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 4584 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4585 } 4586 } 4587