1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.17"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 static void e1000g_pch_limits(struct e1000g *); 98 static uint32_t e1000g_mtu2maxframe(uint32_t); 99 100 /* 101 * Local routines 102 */ 103 static boolean_t e1000g_reset_adapter(struct e1000g *); 104 static void e1000g_tx_clean(struct e1000g *); 105 static void e1000g_rx_clean(struct e1000g *); 106 static void e1000g_link_timer(void *); 107 static void e1000g_local_timer(void *); 108 static boolean_t e1000g_link_check(struct e1000g *); 109 static boolean_t e1000g_stall_check(struct e1000g *); 110 static void e1000g_smartspeed(struct e1000g *); 111 static void e1000g_get_conf(struct e1000g *); 112 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 113 static void enable_watchdog_timer(struct e1000g *); 114 static void disable_watchdog_timer(struct e1000g *); 115 static void start_watchdog_timer(struct e1000g *); 116 static void restart_watchdog_timer(struct e1000g *); 117 static void stop_watchdog_timer(struct e1000g *); 118 static void stop_link_timer(struct e1000g *); 119 static void stop_82547_timer(e1000g_tx_ring_t *); 120 static void e1000g_force_speed_duplex(struct e1000g *); 121 static void e1000g_setup_max_mtu(struct e1000g *); 122 static void e1000g_get_max_frame_size(struct e1000g *); 123 static boolean_t is_valid_mac_addr(uint8_t *); 124 static void e1000g_unattach(dev_info_t *, struct e1000g *); 125 #ifdef E1000G_DEBUG 126 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 127 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 128 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 130 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 131 struct iocblk *, mblk_t *); 132 #endif 133 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 134 struct iocblk *, mblk_t *); 135 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 136 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 137 static void e1000g_set_internal_loopback(struct e1000g *); 138 static void e1000g_set_external_loopback_1000(struct e1000g *); 139 static void e1000g_set_external_loopback_100(struct e1000g *); 140 static void e1000g_set_external_loopback_10(struct e1000g *); 141 static int e1000g_add_intrs(struct e1000g *); 142 static int e1000g_intr_add(struct e1000g *, int); 143 static int e1000g_rem_intrs(struct e1000g *); 144 static int e1000g_enable_intrs(struct e1000g *); 145 static int e1000g_disable_intrs(struct e1000g *); 146 static boolean_t e1000g_link_up(struct e1000g *); 147 #ifdef __sparc 148 static boolean_t e1000g_find_mac_address(struct e1000g *); 149 #endif 150 static void e1000g_get_phy_state(struct e1000g *); 151 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 152 const void *impl_data); 153 static void e1000g_fm_init(struct e1000g *Adapter); 154 static void e1000g_fm_fini(struct e1000g *Adapter); 155 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 156 static void e1000g_param_sync(struct e1000g *); 157 static void e1000g_get_driver_control(struct e1000_hw *); 158 static void e1000g_release_driver_control(struct e1000_hw *); 159 static void e1000g_restore_promisc(struct e1000g *Adapter); 160 161 mac_priv_prop_t e1000g_priv_props[] = { 162 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 164 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 167 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 168 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 169 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 170 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 171 {"_intr_adaptive", MAC_PROP_PERM_RW}, 172 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 173 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 174 }; 175 #define E1000G_MAX_PRIV_PROPS \ 176 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 177 178 179 static struct cb_ops cb_ws_ops = { 180 nulldev, /* cb_open */ 181 nulldev, /* cb_close */ 182 nodev, /* cb_strategy */ 183 nodev, /* cb_print */ 184 nodev, /* cb_dump */ 185 nodev, /* cb_read */ 186 nodev, /* cb_write */ 187 nodev, /* cb_ioctl */ 188 nodev, /* cb_devmap */ 189 nodev, /* cb_mmap */ 190 nodev, /* cb_segmap */ 191 nochpoll, /* cb_chpoll */ 192 ddi_prop_op, /* cb_prop_op */ 193 NULL, /* cb_stream */ 194 D_MP | D_HOTPLUG, /* cb_flag */ 195 CB_REV, /* cb_rev */ 196 nodev, /* cb_aread */ 197 nodev /* cb_awrite */ 198 }; 199 200 static struct dev_ops ws_ops = { 201 DEVO_REV, /* devo_rev */ 202 0, /* devo_refcnt */ 203 NULL, /* devo_getinfo */ 204 nulldev, /* devo_identify */ 205 nulldev, /* devo_probe */ 206 e1000g_attach, /* devo_attach */ 207 e1000g_detach, /* devo_detach */ 208 nodev, /* devo_reset */ 209 &cb_ws_ops, /* devo_cb_ops */ 210 NULL, /* devo_bus_ops */ 211 ddi_power, /* devo_power */ 212 e1000g_quiesce /* devo_quiesce */ 213 }; 214 215 static struct modldrv modldrv = { 216 &mod_driverops, /* Type of module. This one is a driver */ 217 ident, /* Discription string */ 218 &ws_ops, /* driver ops */ 219 }; 220 221 static struct modlinkage modlinkage = { 222 MODREV_1, &modldrv, NULL 223 }; 224 225 /* Access attributes for register mapping */ 226 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 227 DDI_DEVICE_ATTR_V0, 228 DDI_STRUCTURE_LE_ACC, 229 DDI_STRICTORDER_ACC, 230 DDI_FLAGERR_ACC 231 }; 232 233 #define E1000G_M_CALLBACK_FLAGS \ 234 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 235 236 static mac_callbacks_t e1000g_m_callbacks = { 237 E1000G_M_CALLBACK_FLAGS, 238 e1000g_m_stat, 239 e1000g_m_start, 240 e1000g_m_stop, 241 e1000g_m_promisc, 242 e1000g_m_multicst, 243 NULL, 244 e1000g_m_tx, 245 e1000g_m_ioctl, 246 e1000g_m_getcapab, 247 NULL, 248 NULL, 249 e1000g_m_setprop, 250 e1000g_m_getprop 251 }; 252 253 /* 254 * Global variables 255 */ 256 uint32_t e1000g_mblks_pending = 0; 257 /* 258 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 259 * Here we maintain a private dev_info list if e1000g_force_detach is 260 * enabled. If we force the driver to detach while there are still some 261 * rx buffers retained in the upper layer, we have to keep a copy of the 262 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 263 * structure will be freed after the driver is detached. However when we 264 * finally free those rx buffers released by the upper layer, we need to 265 * refer to the dev_info to free the dma buffers. So we save a copy of 266 * the dev_info for this purpose. On x86 platform, we assume this copy 267 * of dev_info is always valid, but on SPARC platform, it could be invalid 268 * after the system board level DR operation. For this reason, the global 269 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 270 */ 271 #ifdef __sparc 272 boolean_t e1000g_force_detach = B_FALSE; 273 #else 274 boolean_t e1000g_force_detach = B_TRUE; 275 #endif 276 private_devi_list_t *e1000g_private_devi_list = NULL; 277 278 /* 279 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 280 * the private dev_info list, and to serialize the processing of rx buffer 281 * freeing and rx buffer recycling. 282 */ 283 kmutex_t e1000g_rx_detach_lock; 284 /* 285 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 286 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 287 * If there are many e1000g instances, the system may run out of DVMA 288 * resources during the initialization of the instances, then the flag will 289 * be changed to "USE_DMA". Because different e1000g instances are initialized 290 * in parallel, we need to use this lock to protect the flag. 291 */ 292 krwlock_t e1000g_dma_type_lock; 293 294 /* 295 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 296 * Based on the information from Intel, the 82546 chipset has some hardware 297 * problem. When one port is being reset and the other port is trying to 298 * access the eeprom, it could cause system hang or panic. To workaround this 299 * hardware problem, we use a global mutex to prevent such operations from 300 * happening simultaneously on different instances. This workaround is applied 301 * to all the devices supported by this driver. 302 */ 303 kmutex_t e1000g_nvm_lock; 304 305 /* 306 * Loadable module configuration entry points for the driver 307 */ 308 309 /* 310 * _init - module initialization 311 */ 312 int 313 _init(void) 314 { 315 int status; 316 317 mac_init_ops(&ws_ops, WSNAME); 318 status = mod_install(&modlinkage); 319 if (status != DDI_SUCCESS) 320 mac_fini_ops(&ws_ops); 321 else { 322 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 323 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 324 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 325 } 326 327 return (status); 328 } 329 330 /* 331 * _fini - module finalization 332 */ 333 int 334 _fini(void) 335 { 336 int status; 337 338 if (e1000g_mblks_pending != 0) 339 return (EBUSY); 340 341 status = mod_remove(&modlinkage); 342 if (status == DDI_SUCCESS) { 343 mac_fini_ops(&ws_ops); 344 345 if (e1000g_force_detach) { 346 private_devi_list_t *devi_node; 347 348 mutex_enter(&e1000g_rx_detach_lock); 349 while (e1000g_private_devi_list != NULL) { 350 devi_node = e1000g_private_devi_list; 351 e1000g_private_devi_list = 352 e1000g_private_devi_list->next; 353 354 kmem_free(devi_node->priv_dip, 355 sizeof (struct dev_info)); 356 kmem_free(devi_node, 357 sizeof (private_devi_list_t)); 358 } 359 mutex_exit(&e1000g_rx_detach_lock); 360 } 361 362 mutex_destroy(&e1000g_rx_detach_lock); 363 rw_destroy(&e1000g_dma_type_lock); 364 mutex_destroy(&e1000g_nvm_lock); 365 } 366 367 return (status); 368 } 369 370 /* 371 * _info - module information 372 */ 373 int 374 _info(struct modinfo *modinfop) 375 { 376 return (mod_info(&modlinkage, modinfop)); 377 } 378 379 /* 380 * e1000g_attach - driver attach 381 * 382 * This function is the device-specific initialization entry 383 * point. This entry point is required and must be written. 384 * The DDI_ATTACH command must be provided in the attach entry 385 * point. When attach() is called with cmd set to DDI_ATTACH, 386 * all normal kernel services (such as kmem_alloc(9F)) are 387 * available for use by the driver. 388 * 389 * The attach() function will be called once for each instance 390 * of the device on the system with cmd set to DDI_ATTACH. 391 * Until attach() succeeds, the only driver entry points which 392 * may be called are open(9E) and getinfo(9E). 393 */ 394 static int 395 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 396 { 397 struct e1000g *Adapter; 398 struct e1000_hw *hw; 399 struct e1000g_osdep *osdep; 400 int instance; 401 402 switch (cmd) { 403 default: 404 e1000g_log(NULL, CE_WARN, 405 "Unsupported command send to e1000g_attach... "); 406 return (DDI_FAILURE); 407 408 case DDI_RESUME: 409 return (e1000g_resume(devinfo)); 410 411 case DDI_ATTACH: 412 break; 413 } 414 415 /* 416 * get device instance number 417 */ 418 instance = ddi_get_instance(devinfo); 419 420 /* 421 * Allocate soft data structure 422 */ 423 Adapter = 424 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 425 426 Adapter->dip = devinfo; 427 Adapter->instance = instance; 428 Adapter->tx_ring->adapter = Adapter; 429 Adapter->rx_ring->adapter = Adapter; 430 431 hw = &Adapter->shared; 432 osdep = &Adapter->osdep; 433 hw->back = osdep; 434 osdep->adapter = Adapter; 435 436 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 437 438 /* 439 * Initialize for fma support 440 */ 441 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 442 0, 0x0f, 443 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 444 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 445 e1000g_fm_init(Adapter); 446 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 447 448 /* 449 * PCI Configure 450 */ 451 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 452 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 453 goto attach_fail; 454 } 455 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 456 457 /* 458 * Setup hardware 459 */ 460 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 461 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 462 goto attach_fail; 463 } 464 465 /* 466 * Map in the device registers. 467 */ 468 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 469 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 470 goto attach_fail; 471 } 472 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 473 474 /* 475 * Initialize driver parameters 476 */ 477 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 478 goto attach_fail; 479 } 480 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 481 482 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 483 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 484 goto attach_fail; 485 } 486 487 /* 488 * Initialize interrupts 489 */ 490 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 491 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 492 goto attach_fail; 493 } 494 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 495 496 /* 497 * Initialize mutex's for this device. 498 * Do this before enabling the interrupt handler and 499 * register the softint to avoid the condition where 500 * interrupt handler can try using uninitialized mutex 501 */ 502 e1000g_init_locks(Adapter); 503 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 504 505 /* 506 * Initialize Driver Counters 507 */ 508 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 509 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 510 goto attach_fail; 511 } 512 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 513 514 /* 515 * Initialize chip hardware and software structures 516 */ 517 rw_enter(&Adapter->chip_lock, RW_WRITER); 518 if (e1000g_init(Adapter) != DDI_SUCCESS) { 519 rw_exit(&Adapter->chip_lock); 520 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 521 goto attach_fail; 522 } 523 rw_exit(&Adapter->chip_lock); 524 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 525 526 /* 527 * Register the driver to the MAC 528 */ 529 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 530 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 531 goto attach_fail; 532 } 533 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 534 535 /* 536 * Now that mutex locks are initialized, and the chip is also 537 * initialized, enable interrupts. 538 */ 539 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 540 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 541 goto attach_fail; 542 } 543 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 544 545 /* 546 * If e1000g_force_detach is enabled, in global private dip list, 547 * we will create a new entry, which maintains the priv_dip for DR 548 * supports after driver detached. 549 */ 550 if (e1000g_force_detach) { 551 private_devi_list_t *devi_node; 552 553 Adapter->priv_dip = 554 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 555 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 556 sizeof (struct dev_info)); 557 558 devi_node = 559 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 560 561 mutex_enter(&e1000g_rx_detach_lock); 562 devi_node->priv_dip = Adapter->priv_dip; 563 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 564 devi_node->pending_rx_count = 0; 565 566 Adapter->priv_devi_node = devi_node; 567 568 if (e1000g_private_devi_list == NULL) { 569 devi_node->prev = NULL; 570 devi_node->next = NULL; 571 e1000g_private_devi_list = devi_node; 572 } else { 573 devi_node->prev = NULL; 574 devi_node->next = e1000g_private_devi_list; 575 e1000g_private_devi_list->prev = devi_node; 576 e1000g_private_devi_list = devi_node; 577 } 578 mutex_exit(&e1000g_rx_detach_lock); 579 } 580 581 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 582 Adapter->e1000g_state = E1000G_INITIALIZED; 583 584 return (DDI_SUCCESS); 585 586 attach_fail: 587 e1000g_unattach(devinfo, Adapter); 588 return (DDI_FAILURE); 589 } 590 591 static int 592 e1000g_register_mac(struct e1000g *Adapter) 593 { 594 struct e1000_hw *hw = &Adapter->shared; 595 mac_register_t *mac; 596 int err; 597 598 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 599 return (DDI_FAILURE); 600 601 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 602 mac->m_driver = Adapter; 603 mac->m_dip = Adapter->dip; 604 mac->m_src_addr = hw->mac.addr; 605 mac->m_callbacks = &e1000g_m_callbacks; 606 mac->m_min_sdu = 0; 607 mac->m_max_sdu = Adapter->default_mtu; 608 mac->m_margin = VLAN_TAGSZ; 609 mac->m_priv_props = e1000g_priv_props; 610 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 611 mac->m_v12n = MAC_VIRT_LEVEL1; 612 613 err = mac_register(mac, &Adapter->mh); 614 mac_free(mac); 615 616 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 617 } 618 619 static int 620 e1000g_identify_hardware(struct e1000g *Adapter) 621 { 622 struct e1000_hw *hw = &Adapter->shared; 623 struct e1000g_osdep *osdep = &Adapter->osdep; 624 625 /* Get the device id */ 626 hw->vendor_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 628 hw->device_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 630 hw->revision_id = 631 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 632 hw->subsystem_device_id = 633 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 634 hw->subsystem_vendor_id = 635 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 636 637 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 638 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 639 "MAC type could not be set properly."); 640 return (DDI_FAILURE); 641 } 642 643 return (DDI_SUCCESS); 644 } 645 646 static int 647 e1000g_regs_map(struct e1000g *Adapter) 648 { 649 dev_info_t *devinfo = Adapter->dip; 650 struct e1000_hw *hw = &Adapter->shared; 651 struct e1000g_osdep *osdep = &Adapter->osdep; 652 off_t mem_size; 653 654 /* Get size of adapter register memory */ 655 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 656 DDI_SUCCESS) { 657 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 658 "ddi_dev_regsize for registers failed"); 659 return (DDI_FAILURE); 660 } 661 662 /* Map adapter register memory */ 663 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 664 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 665 &osdep->reg_handle)) != DDI_SUCCESS) { 666 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 667 "ddi_regs_map_setup for registers failed"); 668 goto regs_map_fail; 669 } 670 671 /* ICH needs to map flash memory */ 672 if (hw->mac.type == e1000_ich8lan || 673 hw->mac.type == e1000_ich9lan || 674 hw->mac.type == e1000_ich10lan || 675 hw->mac.type == e1000_pchlan) { 676 /* get flash size */ 677 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 678 &mem_size) != DDI_SUCCESS) { 679 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 680 "ddi_dev_regsize for ICH flash failed"); 681 goto regs_map_fail; 682 } 683 684 /* map flash in */ 685 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 686 (caddr_t *)&hw->flash_address, 0, 687 mem_size, &e1000g_regs_acc_attr, 688 &osdep->ich_flash_handle) != DDI_SUCCESS) { 689 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 690 "ddi_regs_map_setup for ICH flash failed"); 691 goto regs_map_fail; 692 } 693 } 694 695 return (DDI_SUCCESS); 696 697 regs_map_fail: 698 if (osdep->reg_handle != NULL) 699 ddi_regs_map_free(&osdep->reg_handle); 700 701 return (DDI_FAILURE); 702 } 703 704 static int 705 e1000g_set_driver_params(struct e1000g *Adapter) 706 { 707 struct e1000_hw *hw; 708 uint32_t mem_bar, io_bar, bar64; 709 710 hw = &Adapter->shared; 711 712 /* Set MAC type and initialize hardware functions */ 713 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 714 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 715 "Could not setup hardware functions"); 716 return (DDI_FAILURE); 717 } 718 719 /* Get bus information */ 720 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 721 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 722 "Could not get bus information"); 723 return (DDI_FAILURE); 724 } 725 726 /* get mem_base addr */ 727 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 728 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 729 730 /* get io_base addr */ 731 if (hw->mac.type >= e1000_82544) { 732 if (bar64) { 733 /* IO BAR is different for 64 bit BAR mode */ 734 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 735 PCI_CONF_BASE4); 736 } else { 737 /* normal 32-bit BAR mode */ 738 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 739 PCI_CONF_BASE2); 740 } 741 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 742 } else { 743 /* no I/O access for adapters prior to 82544 */ 744 hw->io_base = 0x0; 745 } 746 747 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 748 749 hw->mac.autoneg_failed = B_TRUE; 750 751 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 752 hw->phy.autoneg_wait_to_complete = B_FALSE; 753 754 /* Adaptive IFS related changes */ 755 hw->mac.adaptive_ifs = B_TRUE; 756 757 /* Enable phy init script for IGP phy of 82541/82547 */ 758 if ((hw->mac.type == e1000_82547) || 759 (hw->mac.type == e1000_82541) || 760 (hw->mac.type == e1000_82547_rev_2) || 761 (hw->mac.type == e1000_82541_rev_2)) 762 e1000_init_script_state_82541(hw, B_TRUE); 763 764 /* Enable the TTL workaround for 82541/82547 */ 765 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 766 767 #ifdef __sparc 768 Adapter->strip_crc = B_TRUE; 769 #else 770 Adapter->strip_crc = B_FALSE; 771 #endif 772 773 /* setup the maximum MTU size of the chip */ 774 e1000g_setup_max_mtu(Adapter); 775 776 /* Get conf file properties */ 777 e1000g_get_conf(Adapter); 778 779 /* Get speed/duplex settings in conf file */ 780 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 781 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 782 e1000g_force_speed_duplex(Adapter); 783 784 /* Get Jumbo Frames settings in conf file */ 785 e1000g_get_max_frame_size(Adapter); 786 787 /* enforce PCH limits */ 788 e1000g_pch_limits(Adapter); 789 790 /* Set Rx/Tx buffer size */ 791 e1000g_set_bufsize(Adapter); 792 793 /* Master Latency Timer */ 794 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 795 796 /* copper options */ 797 if (hw->phy.media_type == e1000_media_type_copper) { 798 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 799 hw->phy.disable_polarity_correction = B_FALSE; 800 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 801 } 802 803 /* The initial link state should be "unknown" */ 804 Adapter->link_state = LINK_STATE_UNKNOWN; 805 806 /* Initialize rx parameters */ 807 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 808 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 809 810 /* Initialize tx parameters */ 811 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 812 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 813 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 814 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 815 816 /* Initialize rx parameters */ 817 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 818 819 return (DDI_SUCCESS); 820 } 821 822 static void 823 e1000g_setup_max_mtu(struct e1000g *Adapter) 824 { 825 struct e1000_mac_info *mac = &Adapter->shared.mac; 826 struct e1000_phy_info *phy = &Adapter->shared.phy; 827 828 switch (mac->type) { 829 /* types that do not support jumbo frames */ 830 case e1000_ich8lan: 831 case e1000_82573: 832 case e1000_82583: 833 Adapter->max_mtu = ETHERMTU; 834 break; 835 /* ich9 supports jumbo frames except on one phy type */ 836 case e1000_ich9lan: 837 if (phy->type == e1000_phy_ife) 838 Adapter->max_mtu = ETHERMTU; 839 else 840 Adapter->max_mtu = MAXIMUM_MTU_9K; 841 break; 842 /* pch can do jumbo frames up to 4K */ 843 case e1000_pchlan: 844 Adapter->max_mtu = MAXIMUM_MTU_4K; 845 break; 846 /* types with a special limit */ 847 case e1000_82571: 848 case e1000_82572: 849 case e1000_82574: 850 case e1000_80003es2lan: 851 case e1000_ich10lan: 852 Adapter->max_mtu = MAXIMUM_MTU_9K; 853 break; 854 /* default limit is 16K */ 855 default: 856 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 857 sizeof (struct ether_vlan_header) - ETHERFCSL - 858 E1000G_IPALIGNPRESERVEROOM; 859 break; 860 } 861 } 862 863 static void 864 e1000g_set_bufsize(struct e1000g *Adapter) 865 { 866 struct e1000_mac_info *mac = &Adapter->shared.mac; 867 uint64_t rx_size; 868 uint64_t tx_size; 869 870 dev_info_t *devinfo = Adapter->dip; 871 #ifdef __sparc 872 ulong_t iommu_pagesize; 873 #endif 874 /* Get the system page size */ 875 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 876 877 #ifdef __sparc 878 iommu_pagesize = dvma_pagesize(devinfo); 879 if (iommu_pagesize != 0) { 880 if (Adapter->sys_page_sz == iommu_pagesize) { 881 if (iommu_pagesize > 0x4000) 882 Adapter->sys_page_sz = 0x4000; 883 } else { 884 if (Adapter->sys_page_sz > iommu_pagesize) 885 Adapter->sys_page_sz = iommu_pagesize; 886 } 887 } 888 if (Adapter->lso_enable) { 889 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 890 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 891 } else { 892 Adapter->dvma_page_num = Adapter->max_frame_size / 893 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 894 } 895 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 896 #endif 897 898 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 899 900 if (Adapter->mem_workaround_82546 && 901 ((mac->type == e1000_82545) || 902 (mac->type == e1000_82546) || 903 (mac->type == e1000_82546_rev_3))) { 904 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 905 } else { 906 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 907 if ((rx_size > FRAME_SIZE_UPTO_2K) && 908 (rx_size <= FRAME_SIZE_UPTO_4K)) 909 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 910 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 911 (rx_size <= FRAME_SIZE_UPTO_8K)) 912 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 913 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 914 (rx_size <= FRAME_SIZE_UPTO_16K)) 915 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 916 else 917 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 918 } 919 920 tx_size = Adapter->max_frame_size; 921 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 922 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 923 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 924 (tx_size <= FRAME_SIZE_UPTO_8K)) 925 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 926 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 927 (tx_size <= FRAME_SIZE_UPTO_16K)) 928 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 929 else 930 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 931 932 /* 933 * For Wiseman adapters we have an requirement of having receive 934 * buffers aligned at 256 byte boundary. Since Livengood does not 935 * require this and forcing it for all hardwares will have 936 * performance implications, I am making it applicable only for 937 * Wiseman and for Jumbo frames enabled mode as rest of the time, 938 * it is okay to have normal frames...but it does involve a 939 * potential risk where we may loose data if buffer is not 940 * aligned...so all wiseman boards to have 256 byte aligned 941 * buffers 942 */ 943 if (mac->type < e1000_82543) 944 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 945 else 946 Adapter->rx_buf_align = 1; 947 } 948 949 /* 950 * e1000g_detach - driver detach 951 * 952 * The detach() function is the complement of the attach routine. 953 * If cmd is set to DDI_DETACH, detach() is used to remove the 954 * state associated with a given instance of a device node 955 * prior to the removal of that instance from the system. 956 * 957 * The detach() function will be called once for each instance 958 * of the device for which there has been a successful attach() 959 * once there are no longer any opens on the device. 960 * 961 * Interrupts routine are disabled, All memory allocated by this 962 * driver are freed. 963 */ 964 static int 965 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 966 { 967 struct e1000g *Adapter; 968 boolean_t rx_drain; 969 970 switch (cmd) { 971 default: 972 return (DDI_FAILURE); 973 974 case DDI_SUSPEND: 975 return (e1000g_suspend(devinfo)); 976 977 case DDI_DETACH: 978 break; 979 } 980 981 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 982 if (Adapter == NULL) 983 return (DDI_FAILURE); 984 985 rx_drain = e1000g_rx_drain(Adapter); 986 if (!rx_drain && !e1000g_force_detach) 987 return (DDI_FAILURE); 988 989 if (mac_unregister(Adapter->mh) != 0) { 990 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 991 return (DDI_FAILURE); 992 } 993 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 994 995 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 996 997 if (!e1000g_force_detach && !rx_drain) 998 return (DDI_FAILURE); 999 1000 e1000g_unattach(devinfo, Adapter); 1001 1002 return (DDI_SUCCESS); 1003 } 1004 1005 /* 1006 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1007 */ 1008 void 1009 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1010 { 1011 ASSERT(e1000g_private_devi_list != NULL); 1012 ASSERT(devi_node != NULL); 1013 1014 if (devi_node->prev != NULL) 1015 devi_node->prev->next = devi_node->next; 1016 if (devi_node->next != NULL) 1017 devi_node->next->prev = devi_node->prev; 1018 if (devi_node == e1000g_private_devi_list) 1019 e1000g_private_devi_list = devi_node->next; 1020 1021 kmem_free(devi_node->priv_dip, 1022 sizeof (struct dev_info)); 1023 kmem_free(devi_node, 1024 sizeof (private_devi_list_t)); 1025 } 1026 1027 static void 1028 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1029 { 1030 private_devi_list_t *devi_node; 1031 int result; 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1034 (void) e1000g_disable_intrs(Adapter); 1035 } 1036 1037 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1038 (void) mac_unregister(Adapter->mh); 1039 } 1040 1041 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1042 (void) e1000g_rem_intrs(Adapter); 1043 } 1044 1045 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1046 (void) ddi_prop_remove_all(devinfo); 1047 } 1048 1049 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1050 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1051 } 1052 1053 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1054 stop_link_timer(Adapter); 1055 1056 mutex_enter(&e1000g_nvm_lock); 1057 result = e1000_reset_hw(&Adapter->shared); 1058 mutex_exit(&e1000g_nvm_lock); 1059 1060 if (result != E1000_SUCCESS) { 1061 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1062 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1063 } 1064 } 1065 1066 e1000g_release_multicast(Adapter); 1067 1068 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1069 if (Adapter->osdep.reg_handle != NULL) 1070 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1071 if (Adapter->osdep.ich_flash_handle != NULL) 1072 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1073 } 1074 1075 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1076 if (Adapter->osdep.cfg_handle != NULL) 1077 pci_config_teardown(&Adapter->osdep.cfg_handle); 1078 } 1079 1080 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1081 e1000g_destroy_locks(Adapter); 1082 } 1083 1084 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1085 e1000g_fm_fini(Adapter); 1086 } 1087 1088 mutex_enter(&e1000g_rx_detach_lock); 1089 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1090 devi_node = Adapter->priv_devi_node; 1091 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1092 1093 if (devi_node->pending_rx_count == 0) { 1094 e1000g_free_priv_devi_node(devi_node); 1095 } 1096 } 1097 mutex_exit(&e1000g_rx_detach_lock); 1098 1099 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1100 1101 /* 1102 * Another hotplug spec requirement, 1103 * run ddi_set_driver_private(devinfo, null); 1104 */ 1105 ddi_set_driver_private(devinfo, NULL); 1106 } 1107 1108 static void 1109 e1000g_init_locks(struct e1000g *Adapter) 1110 { 1111 e1000g_tx_ring_t *tx_ring; 1112 e1000g_rx_ring_t *rx_ring; 1113 1114 rw_init(&Adapter->chip_lock, NULL, 1115 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1116 mutex_init(&Adapter->link_lock, NULL, 1117 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1118 mutex_init(&Adapter->watchdog_lock, NULL, 1119 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1120 1121 tx_ring = Adapter->tx_ring; 1122 1123 mutex_init(&tx_ring->tx_lock, NULL, 1124 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1125 mutex_init(&tx_ring->usedlist_lock, NULL, 1126 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1127 mutex_init(&tx_ring->freelist_lock, NULL, 1128 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1129 1130 rx_ring = Adapter->rx_ring; 1131 1132 mutex_init(&rx_ring->rx_lock, NULL, 1133 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1134 } 1135 1136 static void 1137 e1000g_destroy_locks(struct e1000g *Adapter) 1138 { 1139 e1000g_tx_ring_t *tx_ring; 1140 e1000g_rx_ring_t *rx_ring; 1141 1142 tx_ring = Adapter->tx_ring; 1143 mutex_destroy(&tx_ring->tx_lock); 1144 mutex_destroy(&tx_ring->usedlist_lock); 1145 mutex_destroy(&tx_ring->freelist_lock); 1146 1147 rx_ring = Adapter->rx_ring; 1148 mutex_destroy(&rx_ring->rx_lock); 1149 1150 mutex_destroy(&Adapter->link_lock); 1151 mutex_destroy(&Adapter->watchdog_lock); 1152 rw_destroy(&Adapter->chip_lock); 1153 1154 /* destory mutex initialized in shared code */ 1155 e1000_destroy_hw_mutex(&Adapter->shared); 1156 } 1157 1158 static int 1159 e1000g_resume(dev_info_t *devinfo) 1160 { 1161 struct e1000g *Adapter; 1162 1163 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1164 if (Adapter == NULL) 1165 e1000g_log(Adapter, CE_PANIC, 1166 "Instance pointer is null\n"); 1167 1168 if (Adapter->dip != devinfo) 1169 e1000g_log(Adapter, CE_PANIC, 1170 "Devinfo is not the same as saved devinfo\n"); 1171 1172 rw_enter(&Adapter->chip_lock, RW_WRITER); 1173 1174 if (Adapter->e1000g_state & E1000G_STARTED) { 1175 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1176 rw_exit(&Adapter->chip_lock); 1177 /* 1178 * We note the failure, but return success, as the 1179 * system is still usable without this controller. 1180 */ 1181 e1000g_log(Adapter, CE_WARN, 1182 "e1000g_resume: failed to restart controller\n"); 1183 return (DDI_SUCCESS); 1184 } 1185 /* Enable and start the watchdog timer */ 1186 enable_watchdog_timer(Adapter); 1187 } 1188 1189 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1190 1191 rw_exit(&Adapter->chip_lock); 1192 1193 return (DDI_SUCCESS); 1194 } 1195 1196 static int 1197 e1000g_suspend(dev_info_t *devinfo) 1198 { 1199 struct e1000g *Adapter; 1200 1201 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1202 if (Adapter == NULL) 1203 return (DDI_FAILURE); 1204 1205 rw_enter(&Adapter->chip_lock, RW_WRITER); 1206 1207 Adapter->e1000g_state |= E1000G_SUSPENDED; 1208 1209 /* if the port isn't plumbed, we can simply return */ 1210 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1211 rw_exit(&Adapter->chip_lock); 1212 return (DDI_SUCCESS); 1213 } 1214 1215 e1000g_stop(Adapter, B_FALSE); 1216 1217 rw_exit(&Adapter->chip_lock); 1218 1219 /* Disable and stop all the timers */ 1220 disable_watchdog_timer(Adapter); 1221 stop_link_timer(Adapter); 1222 stop_82547_timer(Adapter->tx_ring); 1223 1224 return (DDI_SUCCESS); 1225 } 1226 1227 static int 1228 e1000g_init(struct e1000g *Adapter) 1229 { 1230 uint32_t pba; 1231 uint32_t high_water; 1232 struct e1000_hw *hw; 1233 clock_t link_timeout; 1234 int result; 1235 1236 hw = &Adapter->shared; 1237 1238 /* 1239 * reset to put the hardware in a known state 1240 * before we try to do anything with the eeprom 1241 */ 1242 mutex_enter(&e1000g_nvm_lock); 1243 result = e1000_reset_hw(hw); 1244 mutex_exit(&e1000g_nvm_lock); 1245 1246 if (result != E1000_SUCCESS) { 1247 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1248 goto init_fail; 1249 } 1250 1251 mutex_enter(&e1000g_nvm_lock); 1252 result = e1000_validate_nvm_checksum(hw); 1253 if (result < E1000_SUCCESS) { 1254 /* 1255 * Some PCI-E parts fail the first check due to 1256 * the link being in sleep state. Call it again, 1257 * if it fails a second time its a real issue. 1258 */ 1259 result = e1000_validate_nvm_checksum(hw); 1260 } 1261 mutex_exit(&e1000g_nvm_lock); 1262 1263 if (result < E1000_SUCCESS) { 1264 e1000g_log(Adapter, CE_WARN, 1265 "Invalid NVM checksum. Please contact " 1266 "the vendor to update the NVM."); 1267 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1268 goto init_fail; 1269 } 1270 1271 result = 0; 1272 #ifdef __sparc 1273 /* 1274 * First, we try to get the local ethernet address from OBP. If 1275 * failed, then we get it from the EEPROM of NIC card. 1276 */ 1277 result = e1000g_find_mac_address(Adapter); 1278 #endif 1279 /* Get the local ethernet address. */ 1280 if (!result) { 1281 mutex_enter(&e1000g_nvm_lock); 1282 result = e1000_read_mac_addr(hw); 1283 mutex_exit(&e1000g_nvm_lock); 1284 } 1285 1286 if (result < E1000_SUCCESS) { 1287 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1288 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1289 goto init_fail; 1290 } 1291 1292 /* check for valid mac address */ 1293 if (!is_valid_mac_addr(hw->mac.addr)) { 1294 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1295 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1296 goto init_fail; 1297 } 1298 1299 /* Set LAA state for 82571 chipset */ 1300 e1000_set_laa_state_82571(hw, B_TRUE); 1301 1302 /* Master Latency Timer implementation */ 1303 if (Adapter->master_latency_timer) { 1304 pci_config_put8(Adapter->osdep.cfg_handle, 1305 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1306 } 1307 1308 if (hw->mac.type < e1000_82547) { 1309 /* 1310 * Total FIFO is 64K 1311 */ 1312 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1313 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1314 else 1315 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1316 } else if ((hw->mac.type == e1000_82571) || 1317 (hw->mac.type == e1000_82572) || 1318 (hw->mac.type == e1000_80003es2lan)) { 1319 /* 1320 * Total FIFO is 48K 1321 */ 1322 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1323 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1324 else 1325 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1326 } else if (hw->mac.type == e1000_82573) { 1327 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1328 } else if (hw->mac.type == e1000_82574) { 1329 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1330 pba = E1000_READ_REG(hw, E1000_PBA); 1331 } else if (hw->mac.type == e1000_ich8lan) { 1332 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1333 } else if (hw->mac.type == e1000_ich9lan) { 1334 pba = E1000_PBA_10K; 1335 } else if (hw->mac.type == e1000_ich10lan) { 1336 pba = E1000_PBA_10K; 1337 } else if (hw->mac.type == e1000_pchlan) { 1338 pba = E1000_PBA_26K; 1339 } else { 1340 /* 1341 * Total FIFO is 40K 1342 */ 1343 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1344 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1345 else 1346 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1347 } 1348 E1000_WRITE_REG(hw, E1000_PBA, pba); 1349 1350 /* 1351 * These parameters set thresholds for the adapter's generation(Tx) 1352 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1353 * settings. Flow control is enabled or disabled in the configuration 1354 * file. 1355 * High-water mark is set down from the top of the rx fifo (not 1356 * sensitive to max_frame_size) and low-water is set just below 1357 * high-water mark. 1358 * The high water mark must be low enough to fit one full frame above 1359 * it in the rx FIFO. Should be the lower of: 1360 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1361 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1362 * Rx FIFO size minus one full frame. 1363 */ 1364 high_water = min(((pba << 10) * 9 / 10), 1365 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1366 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1367 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1368 ((pba << 10) - Adapter->max_frame_size))); 1369 1370 hw->fc.high_water = high_water & 0xFFF8; 1371 hw->fc.low_water = hw->fc.high_water - 8; 1372 1373 if (hw->mac.type == e1000_80003es2lan) 1374 hw->fc.pause_time = 0xFFFF; 1375 else 1376 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1377 hw->fc.send_xon = B_TRUE; 1378 1379 /* 1380 * Reset the adapter hardware the second time. 1381 */ 1382 mutex_enter(&e1000g_nvm_lock); 1383 result = e1000_reset_hw(hw); 1384 mutex_exit(&e1000g_nvm_lock); 1385 1386 if (result != E1000_SUCCESS) { 1387 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1388 goto init_fail; 1389 } 1390 1391 /* disable wakeup control by default */ 1392 if (hw->mac.type >= e1000_82544) 1393 E1000_WRITE_REG(hw, E1000_WUC, 0); 1394 1395 /* 1396 * MWI should be disabled on 82546. 1397 */ 1398 if (hw->mac.type == e1000_82546) 1399 e1000_pci_clear_mwi(hw); 1400 else 1401 e1000_pci_set_mwi(hw); 1402 1403 /* 1404 * Configure/Initialize hardware 1405 */ 1406 mutex_enter(&e1000g_nvm_lock); 1407 result = e1000_init_hw(hw); 1408 mutex_exit(&e1000g_nvm_lock); 1409 1410 if (result < E1000_SUCCESS) { 1411 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1412 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1413 goto init_fail; 1414 } 1415 1416 /* 1417 * Restore LED settings to the default from EEPROM 1418 * to meet the standard for Sun platforms. 1419 */ 1420 (void) e1000_cleanup_led(hw); 1421 1422 /* Disable Smart Power Down */ 1423 phy_spd_state(hw, B_FALSE); 1424 1425 /* Make sure driver has control */ 1426 e1000g_get_driver_control(hw); 1427 1428 /* 1429 * Initialize unicast addresses. 1430 */ 1431 e1000g_init_unicst(Adapter); 1432 1433 /* 1434 * Setup and initialize the mctable structures. After this routine 1435 * completes Multicast table will be set 1436 */ 1437 e1000_update_mc_addr_list(hw, 1438 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1439 msec_delay(5); 1440 1441 /* 1442 * Implement Adaptive IFS 1443 */ 1444 e1000_reset_adaptive(hw); 1445 1446 /* Setup Interrupt Throttling Register */ 1447 if (hw->mac.type >= e1000_82540) { 1448 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1449 } else 1450 Adapter->intr_adaptive = B_FALSE; 1451 1452 /* Start the timer for link setup */ 1453 if (hw->mac.autoneg) 1454 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1455 else 1456 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1457 1458 mutex_enter(&Adapter->link_lock); 1459 if (hw->phy.autoneg_wait_to_complete) { 1460 Adapter->link_complete = B_TRUE; 1461 } else { 1462 Adapter->link_complete = B_FALSE; 1463 Adapter->link_tid = timeout(e1000g_link_timer, 1464 (void *)Adapter, link_timeout); 1465 } 1466 mutex_exit(&Adapter->link_lock); 1467 1468 /* Save the state of the phy */ 1469 e1000g_get_phy_state(Adapter); 1470 1471 e1000g_param_sync(Adapter); 1472 1473 Adapter->init_count++; 1474 1475 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1476 goto init_fail; 1477 } 1478 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1479 goto init_fail; 1480 } 1481 1482 Adapter->poll_mode = e1000g_poll_mode; 1483 1484 return (DDI_SUCCESS); 1485 1486 init_fail: 1487 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1488 return (DDI_FAILURE); 1489 } 1490 1491 static int 1492 e1000g_alloc_rx_data(struct e1000g *Adapter) 1493 { 1494 e1000g_rx_ring_t *rx_ring; 1495 e1000g_rx_data_t *rx_data; 1496 1497 rx_ring = Adapter->rx_ring; 1498 1499 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1500 1501 if (rx_data == NULL) 1502 return (DDI_FAILURE); 1503 1504 rx_data->priv_devi_node = Adapter->priv_devi_node; 1505 rx_data->rx_ring = rx_ring; 1506 1507 mutex_init(&rx_data->freelist_lock, NULL, 1508 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1509 mutex_init(&rx_data->recycle_lock, NULL, 1510 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1511 1512 rx_ring->rx_data = rx_data; 1513 1514 return (DDI_SUCCESS); 1515 } 1516 1517 void 1518 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1519 { 1520 rx_sw_packet_t *packet, *next_packet; 1521 1522 if (rx_data == NULL) 1523 return; 1524 1525 packet = rx_data->packet_area; 1526 while (packet != NULL) { 1527 next_packet = packet->next; 1528 e1000g_free_rx_sw_packet(packet, B_TRUE); 1529 packet = next_packet; 1530 } 1531 rx_data->packet_area = NULL; 1532 } 1533 1534 void 1535 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1536 { 1537 if (rx_data == NULL) 1538 return; 1539 1540 mutex_destroy(&rx_data->freelist_lock); 1541 mutex_destroy(&rx_data->recycle_lock); 1542 1543 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1544 } 1545 1546 /* 1547 * Check if the link is up 1548 */ 1549 static boolean_t 1550 e1000g_link_up(struct e1000g *Adapter) 1551 { 1552 struct e1000_hw *hw = &Adapter->shared; 1553 boolean_t link_up = B_FALSE; 1554 1555 /* 1556 * get_link_status is set in the interrupt handler on link-status-change 1557 * or rx sequence error interrupt. get_link_status will stay 1558 * false until the e1000_check_for_link establishes link only 1559 * for copper adapters. 1560 */ 1561 switch (hw->phy.media_type) { 1562 case e1000_media_type_copper: 1563 if (hw->mac.get_link_status) { 1564 (void) e1000_check_for_link(hw); 1565 link_up = !hw->mac.get_link_status; 1566 } else { 1567 link_up = B_TRUE; 1568 } 1569 break; 1570 case e1000_media_type_fiber: 1571 (void) e1000_check_for_link(hw); 1572 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1573 E1000_STATUS_LU); 1574 break; 1575 case e1000_media_type_internal_serdes: 1576 (void) e1000_check_for_link(hw); 1577 link_up = hw->mac.serdes_has_link; 1578 break; 1579 } 1580 1581 return (link_up); 1582 } 1583 1584 static void 1585 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1586 { 1587 struct iocblk *iocp; 1588 struct e1000g *e1000gp; 1589 enum ioc_reply status; 1590 1591 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1592 iocp->ioc_error = 0; 1593 e1000gp = (struct e1000g *)arg; 1594 1595 ASSERT(e1000gp); 1596 if (e1000gp == NULL) { 1597 miocnak(q, mp, 0, EINVAL); 1598 return; 1599 } 1600 1601 rw_enter(&e1000gp->chip_lock, RW_READER); 1602 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1603 rw_exit(&e1000gp->chip_lock); 1604 miocnak(q, mp, 0, EINVAL); 1605 return; 1606 } 1607 rw_exit(&e1000gp->chip_lock); 1608 1609 switch (iocp->ioc_cmd) { 1610 1611 case LB_GET_INFO_SIZE: 1612 case LB_GET_INFO: 1613 case LB_GET_MODE: 1614 case LB_SET_MODE: 1615 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1616 break; 1617 1618 1619 #ifdef E1000G_DEBUG 1620 case E1000G_IOC_REG_PEEK: 1621 case E1000G_IOC_REG_POKE: 1622 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1623 break; 1624 case E1000G_IOC_CHIP_RESET: 1625 e1000gp->reset_count++; 1626 if (e1000g_reset_adapter(e1000gp)) 1627 status = IOC_ACK; 1628 else 1629 status = IOC_INVAL; 1630 break; 1631 #endif 1632 default: 1633 status = IOC_INVAL; 1634 break; 1635 } 1636 1637 /* 1638 * Decide how to reply 1639 */ 1640 switch (status) { 1641 default: 1642 case IOC_INVAL: 1643 /* 1644 * Error, reply with a NAK and EINVAL or the specified error 1645 */ 1646 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1647 EINVAL : iocp->ioc_error); 1648 break; 1649 1650 case IOC_DONE: 1651 /* 1652 * OK, reply already sent 1653 */ 1654 break; 1655 1656 case IOC_ACK: 1657 /* 1658 * OK, reply with an ACK 1659 */ 1660 miocack(q, mp, 0, 0); 1661 break; 1662 1663 case IOC_REPLY: 1664 /* 1665 * OK, send prepared reply as ACK or NAK 1666 */ 1667 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1668 M_IOCACK : M_IOCNAK; 1669 qreply(q, mp); 1670 break; 1671 } 1672 } 1673 1674 /* 1675 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1676 * capable of supporting only one interrupt and we shouldn't disable 1677 * the physical interrupt. In this case we let the interrupt come and 1678 * we queue the packets in the rx ring itself in case we are in polling 1679 * mode (better latency but slightly lower performance and a very 1680 * high intrrupt count in mpstat which is harmless). 1681 * 1682 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1683 * which can be disabled in poll mode. This gives better overall 1684 * throughput (compared to the mode above), shows very low interrupt 1685 * count but has slightly higher latency since we pick the packets when 1686 * the poll thread does polling. 1687 * 1688 * Currently, this flag should be enabled only while doing performance 1689 * measurement or when it can be guaranteed that entire NIC going 1690 * in poll mode will not harm any traffic like cluster heartbeat etc. 1691 */ 1692 int e1000g_poll_mode = 0; 1693 1694 /* 1695 * Called from the upper layers when driver is in polling mode to 1696 * pick up any queued packets. Care should be taken to not block 1697 * this thread. 1698 */ 1699 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1700 { 1701 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1702 mblk_t *mp = NULL; 1703 mblk_t *tail; 1704 struct e1000g *adapter; 1705 1706 adapter = rx_ring->adapter; 1707 1708 rw_enter(&adapter->chip_lock, RW_READER); 1709 1710 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1711 rw_exit(&adapter->chip_lock); 1712 return (NULL); 1713 } 1714 1715 mutex_enter(&rx_ring->rx_lock); 1716 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1717 mutex_exit(&rx_ring->rx_lock); 1718 rw_exit(&adapter->chip_lock); 1719 return (mp); 1720 } 1721 1722 static int 1723 e1000g_m_start(void *arg) 1724 { 1725 struct e1000g *Adapter = (struct e1000g *)arg; 1726 1727 rw_enter(&Adapter->chip_lock, RW_WRITER); 1728 1729 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1730 rw_exit(&Adapter->chip_lock); 1731 return (ECANCELED); 1732 } 1733 1734 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1735 rw_exit(&Adapter->chip_lock); 1736 return (ENOTACTIVE); 1737 } 1738 1739 Adapter->e1000g_state |= E1000G_STARTED; 1740 1741 rw_exit(&Adapter->chip_lock); 1742 1743 /* Enable and start the watchdog timer */ 1744 enable_watchdog_timer(Adapter); 1745 1746 return (0); 1747 } 1748 1749 static int 1750 e1000g_start(struct e1000g *Adapter, boolean_t global) 1751 { 1752 e1000g_rx_data_t *rx_data; 1753 1754 if (global) { 1755 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1756 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1757 goto start_fail; 1758 } 1759 1760 /* Allocate dma resources for descriptors and buffers */ 1761 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1762 e1000g_log(Adapter, CE_WARN, 1763 "Alloc DMA resources failed"); 1764 goto start_fail; 1765 } 1766 Adapter->rx_buffer_setup = B_FALSE; 1767 } 1768 1769 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1770 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1771 e1000g_log(Adapter, CE_WARN, 1772 "Adapter initialization failed"); 1773 goto start_fail; 1774 } 1775 } 1776 1777 /* Setup and initialize the transmit structures */ 1778 e1000g_tx_setup(Adapter); 1779 msec_delay(5); 1780 1781 /* Setup and initialize the receive structures */ 1782 e1000g_rx_setup(Adapter); 1783 msec_delay(5); 1784 1785 /* Restore the e1000g promiscuous mode */ 1786 e1000g_restore_promisc(Adapter); 1787 1788 e1000g_mask_interrupt(Adapter); 1789 1790 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1791 1792 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1793 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1794 goto start_fail; 1795 } 1796 1797 return (DDI_SUCCESS); 1798 1799 start_fail: 1800 rx_data = Adapter->rx_ring->rx_data; 1801 1802 if (global) { 1803 e1000g_release_dma_resources(Adapter); 1804 e1000g_free_rx_pending_buffers(rx_data); 1805 e1000g_free_rx_data(rx_data); 1806 } 1807 1808 mutex_enter(&e1000g_nvm_lock); 1809 (void) e1000_reset_hw(&Adapter->shared); 1810 mutex_exit(&e1000g_nvm_lock); 1811 1812 return (DDI_FAILURE); 1813 } 1814 1815 static void 1816 e1000g_m_stop(void *arg) 1817 { 1818 struct e1000g *Adapter = (struct e1000g *)arg; 1819 1820 /* Drain tx sessions */ 1821 (void) e1000g_tx_drain(Adapter); 1822 1823 rw_enter(&Adapter->chip_lock, RW_WRITER); 1824 1825 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1826 rw_exit(&Adapter->chip_lock); 1827 return; 1828 } 1829 Adapter->e1000g_state &= ~E1000G_STARTED; 1830 e1000g_stop(Adapter, B_TRUE); 1831 1832 rw_exit(&Adapter->chip_lock); 1833 1834 /* Disable and stop all the timers */ 1835 disable_watchdog_timer(Adapter); 1836 stop_link_timer(Adapter); 1837 stop_82547_timer(Adapter->tx_ring); 1838 } 1839 1840 static void 1841 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1842 { 1843 private_devi_list_t *devi_node; 1844 e1000g_rx_data_t *rx_data; 1845 int result; 1846 1847 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1848 1849 /* Stop the chip and release pending resources */ 1850 1851 /* Tell firmware driver is no longer in control */ 1852 e1000g_release_driver_control(&Adapter->shared); 1853 1854 e1000g_clear_all_interrupts(Adapter); 1855 1856 mutex_enter(&e1000g_nvm_lock); 1857 result = e1000_reset_hw(&Adapter->shared); 1858 mutex_exit(&e1000g_nvm_lock); 1859 1860 if (result != E1000_SUCCESS) { 1861 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1862 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1863 } 1864 1865 /* Release resources still held by the TX descriptors */ 1866 e1000g_tx_clean(Adapter); 1867 1868 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1869 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1870 1871 /* Clean the pending rx jumbo packet fragment */ 1872 e1000g_rx_clean(Adapter); 1873 1874 if (global) { 1875 e1000g_release_dma_resources(Adapter); 1876 1877 mutex_enter(&e1000g_rx_detach_lock); 1878 rx_data = Adapter->rx_ring->rx_data; 1879 rx_data->flag |= E1000G_RX_STOPPED; 1880 1881 if (rx_data->pending_count == 0) { 1882 e1000g_free_rx_pending_buffers(rx_data); 1883 e1000g_free_rx_data(rx_data); 1884 } else { 1885 devi_node = rx_data->priv_devi_node; 1886 if (devi_node != NULL) 1887 atomic_inc_32(&devi_node->pending_rx_count); 1888 else 1889 atomic_inc_32(&Adapter->pending_rx_count); 1890 } 1891 mutex_exit(&e1000g_rx_detach_lock); 1892 } 1893 1894 if (Adapter->link_state == LINK_STATE_UP) { 1895 Adapter->link_state = LINK_STATE_UNKNOWN; 1896 mac_link_update(Adapter->mh, Adapter->link_state); 1897 } 1898 } 1899 1900 static void 1901 e1000g_rx_clean(struct e1000g *Adapter) 1902 { 1903 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 1904 1905 if (rx_data == NULL) 1906 return; 1907 1908 if (rx_data->rx_mblk != NULL) { 1909 freemsg(rx_data->rx_mblk); 1910 rx_data->rx_mblk = NULL; 1911 rx_data->rx_mblk_tail = NULL; 1912 rx_data->rx_mblk_len = 0; 1913 } 1914 } 1915 1916 static void 1917 e1000g_tx_clean(struct e1000g *Adapter) 1918 { 1919 e1000g_tx_ring_t *tx_ring; 1920 p_tx_sw_packet_t packet; 1921 mblk_t *mp; 1922 mblk_t *nmp; 1923 uint32_t packet_count; 1924 1925 tx_ring = Adapter->tx_ring; 1926 1927 /* 1928 * Here we don't need to protect the lists using 1929 * the usedlist_lock and freelist_lock, for they 1930 * have been protected by the chip_lock. 1931 */ 1932 mp = NULL; 1933 nmp = NULL; 1934 packet_count = 0; 1935 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1936 while (packet != NULL) { 1937 if (packet->mp != NULL) { 1938 /* Assemble the message chain */ 1939 if (mp == NULL) { 1940 mp = packet->mp; 1941 nmp = packet->mp; 1942 } else { 1943 nmp->b_next = packet->mp; 1944 nmp = packet->mp; 1945 } 1946 /* Disconnect the message from the sw packet */ 1947 packet->mp = NULL; 1948 } 1949 1950 e1000g_free_tx_swpkt(packet); 1951 packet_count++; 1952 1953 packet = (p_tx_sw_packet_t) 1954 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1955 } 1956 1957 if (mp != NULL) 1958 freemsgchain(mp); 1959 1960 if (packet_count > 0) { 1961 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1962 QUEUE_INIT_LIST(&tx_ring->used_list); 1963 1964 /* Setup TX descriptor pointers */ 1965 tx_ring->tbd_next = tx_ring->tbd_first; 1966 tx_ring->tbd_oldest = tx_ring->tbd_first; 1967 1968 /* Setup our HW Tx Head & Tail descriptor pointers */ 1969 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1970 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1971 } 1972 } 1973 1974 static boolean_t 1975 e1000g_tx_drain(struct e1000g *Adapter) 1976 { 1977 int i; 1978 boolean_t done; 1979 e1000g_tx_ring_t *tx_ring; 1980 1981 tx_ring = Adapter->tx_ring; 1982 1983 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1984 for (i = 0; i < TX_DRAIN_TIME; i++) { 1985 mutex_enter(&tx_ring->usedlist_lock); 1986 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1987 mutex_exit(&tx_ring->usedlist_lock); 1988 1989 if (done) 1990 break; 1991 1992 msec_delay(1); 1993 } 1994 1995 return (done); 1996 } 1997 1998 static boolean_t 1999 e1000g_rx_drain(struct e1000g *Adapter) 2000 { 2001 int i; 2002 boolean_t done; 2003 2004 /* 2005 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2006 */ 2007 for (i = 0; i < RX_DRAIN_TIME; i++) { 2008 done = (Adapter->pending_rx_count == 0); 2009 2010 if (done) 2011 break; 2012 2013 msec_delay(1); 2014 } 2015 2016 return (done); 2017 } 2018 2019 static boolean_t 2020 e1000g_reset_adapter(struct e1000g *Adapter) 2021 { 2022 /* Disable and stop all the timers */ 2023 disable_watchdog_timer(Adapter); 2024 stop_link_timer(Adapter); 2025 stop_82547_timer(Adapter->tx_ring); 2026 2027 rw_enter(&Adapter->chip_lock, RW_WRITER); 2028 2029 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2030 rw_exit(&Adapter->chip_lock); 2031 return (B_TRUE); 2032 } 2033 2034 e1000g_stop(Adapter, B_FALSE); 2035 2036 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2037 rw_exit(&Adapter->chip_lock); 2038 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2039 return (B_FALSE); 2040 } 2041 2042 rw_exit(&Adapter->chip_lock); 2043 2044 /* Enable and start the watchdog timer */ 2045 enable_watchdog_timer(Adapter); 2046 2047 return (B_TRUE); 2048 } 2049 2050 boolean_t 2051 e1000g_global_reset(struct e1000g *Adapter) 2052 { 2053 /* Disable and stop all the timers */ 2054 disable_watchdog_timer(Adapter); 2055 stop_link_timer(Adapter); 2056 stop_82547_timer(Adapter->tx_ring); 2057 2058 rw_enter(&Adapter->chip_lock, RW_WRITER); 2059 2060 e1000g_stop(Adapter, B_TRUE); 2061 2062 Adapter->init_count = 0; 2063 2064 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2065 rw_exit(&Adapter->chip_lock); 2066 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2067 return (B_FALSE); 2068 } 2069 2070 rw_exit(&Adapter->chip_lock); 2071 2072 /* Enable and start the watchdog timer */ 2073 enable_watchdog_timer(Adapter); 2074 2075 return (B_TRUE); 2076 } 2077 2078 /* 2079 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2080 * 2081 * This interrupt service routine is for PCI-Express adapters. 2082 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2083 * bit is set. 2084 */ 2085 static uint_t 2086 e1000g_intr_pciexpress(caddr_t arg) 2087 { 2088 struct e1000g *Adapter; 2089 uint32_t icr; 2090 2091 Adapter = (struct e1000g *)(uintptr_t)arg; 2092 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2093 2094 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2095 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2096 return (DDI_INTR_CLAIMED); 2097 } 2098 2099 if (icr & E1000_ICR_INT_ASSERTED) { 2100 /* 2101 * E1000_ICR_INT_ASSERTED bit was set: 2102 * Read(Clear) the ICR, claim this interrupt, 2103 * look for work to do. 2104 */ 2105 e1000g_intr_work(Adapter, icr); 2106 return (DDI_INTR_CLAIMED); 2107 } else { 2108 /* 2109 * E1000_ICR_INT_ASSERTED bit was not set: 2110 * Don't claim this interrupt, return immediately. 2111 */ 2112 return (DDI_INTR_UNCLAIMED); 2113 } 2114 } 2115 2116 /* 2117 * e1000g_intr - ISR for PCI/PCI-X chipsets 2118 * 2119 * This interrupt service routine is for PCI/PCI-X adapters. 2120 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2121 * bit is set or not. 2122 */ 2123 static uint_t 2124 e1000g_intr(caddr_t arg) 2125 { 2126 struct e1000g *Adapter; 2127 uint32_t icr; 2128 2129 Adapter = (struct e1000g *)(uintptr_t)arg; 2130 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2131 2132 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2133 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2134 return (DDI_INTR_CLAIMED); 2135 } 2136 2137 if (icr) { 2138 /* 2139 * Any bit was set in ICR: 2140 * Read(Clear) the ICR, claim this interrupt, 2141 * look for work to do. 2142 */ 2143 e1000g_intr_work(Adapter, icr); 2144 return (DDI_INTR_CLAIMED); 2145 } else { 2146 /* 2147 * No bit was set in ICR: 2148 * Don't claim this interrupt, return immediately. 2149 */ 2150 return (DDI_INTR_UNCLAIMED); 2151 } 2152 } 2153 2154 /* 2155 * e1000g_intr_work - actual processing of ISR 2156 * 2157 * Read(clear) the ICR contents and call appropriate interrupt 2158 * processing routines. 2159 */ 2160 static void 2161 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2162 { 2163 struct e1000_hw *hw; 2164 hw = &Adapter->shared; 2165 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2166 2167 Adapter->rx_pkt_cnt = 0; 2168 Adapter->tx_pkt_cnt = 0; 2169 2170 rw_enter(&Adapter->chip_lock, RW_READER); 2171 2172 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2173 rw_exit(&Adapter->chip_lock); 2174 return; 2175 } 2176 /* 2177 * Here we need to check the "e1000g_state" flag within the chip_lock to 2178 * ensure the receive routine will not execute when the adapter is 2179 * being reset. 2180 */ 2181 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2182 rw_exit(&Adapter->chip_lock); 2183 return; 2184 } 2185 2186 if (icr & E1000_ICR_RXT0) { 2187 mblk_t *mp = NULL; 2188 mblk_t *tail = NULL; 2189 e1000g_rx_ring_t *rx_ring; 2190 2191 rx_ring = Adapter->rx_ring; 2192 mutex_enter(&rx_ring->rx_lock); 2193 /* 2194 * Sometimes with legacy interrupts, it possible that 2195 * there is a single interrupt for Rx/Tx. In which 2196 * case, if poll flag is set, we shouldn't really 2197 * be doing Rx processing. 2198 */ 2199 if (!rx_ring->poll_flag) 2200 mp = e1000g_receive(rx_ring, &tail, 2201 E1000G_CHAIN_NO_LIMIT); 2202 mutex_exit(&rx_ring->rx_lock); 2203 rw_exit(&Adapter->chip_lock); 2204 if (mp != NULL) 2205 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2206 mp, rx_ring->ring_gen_num); 2207 } else 2208 rw_exit(&Adapter->chip_lock); 2209 2210 if (icr & E1000_ICR_TXDW) { 2211 if (!Adapter->tx_intr_enable) 2212 e1000g_clear_tx_interrupt(Adapter); 2213 2214 /* Recycle the tx descriptors */ 2215 rw_enter(&Adapter->chip_lock, RW_READER); 2216 (void) e1000g_recycle(tx_ring); 2217 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2218 rw_exit(&Adapter->chip_lock); 2219 2220 if (tx_ring->resched_needed && 2221 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2222 tx_ring->resched_needed = B_FALSE; 2223 mac_tx_update(Adapter->mh); 2224 E1000G_STAT(tx_ring->stat_reschedule); 2225 } 2226 } 2227 2228 /* 2229 * The Receive Sequence errors RXSEQ and the link status change LSC 2230 * are checked to detect that the cable has been pulled out. For 2231 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2232 * are an indication that cable is not connected. 2233 */ 2234 if ((icr & E1000_ICR_RXSEQ) || 2235 (icr & E1000_ICR_LSC) || 2236 (icr & E1000_ICR_GPI_EN1)) { 2237 boolean_t link_changed; 2238 timeout_id_t tid = 0; 2239 2240 stop_watchdog_timer(Adapter); 2241 2242 rw_enter(&Adapter->chip_lock, RW_WRITER); 2243 2244 /* 2245 * Because we got a link-status-change interrupt, force 2246 * e1000_check_for_link() to look at phy 2247 */ 2248 Adapter->shared.mac.get_link_status = B_TRUE; 2249 2250 /* e1000g_link_check takes care of link status change */ 2251 link_changed = e1000g_link_check(Adapter); 2252 2253 /* Get new phy state */ 2254 e1000g_get_phy_state(Adapter); 2255 2256 /* 2257 * If the link timer has not timed out, we'll not notify 2258 * the upper layer with any link state until the link is up. 2259 */ 2260 if (link_changed && !Adapter->link_complete) { 2261 if (Adapter->link_state == LINK_STATE_UP) { 2262 mutex_enter(&Adapter->link_lock); 2263 Adapter->link_complete = B_TRUE; 2264 tid = Adapter->link_tid; 2265 Adapter->link_tid = 0; 2266 mutex_exit(&Adapter->link_lock); 2267 } else { 2268 link_changed = B_FALSE; 2269 } 2270 } 2271 rw_exit(&Adapter->chip_lock); 2272 2273 if (link_changed) { 2274 if (tid != 0) 2275 (void) untimeout(tid); 2276 2277 /* 2278 * Workaround for esb2. Data stuck in fifo on a link 2279 * down event. Stop receiver here and reset in watchdog. 2280 */ 2281 if ((Adapter->link_state == LINK_STATE_DOWN) && 2282 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2283 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2284 E1000_WRITE_REG(hw, E1000_RCTL, 2285 rctl & ~E1000_RCTL_EN); 2286 e1000g_log(Adapter, CE_WARN, 2287 "ESB2 receiver disabled"); 2288 Adapter->esb2_workaround = B_TRUE; 2289 } 2290 if (!Adapter->reset_flag) 2291 mac_link_update(Adapter->mh, 2292 Adapter->link_state); 2293 if (Adapter->link_state == LINK_STATE_UP) 2294 Adapter->reset_flag = B_FALSE; 2295 } 2296 2297 start_watchdog_timer(Adapter); 2298 } 2299 } 2300 2301 static void 2302 e1000g_init_unicst(struct e1000g *Adapter) 2303 { 2304 struct e1000_hw *hw; 2305 int slot; 2306 2307 hw = &Adapter->shared; 2308 2309 if (Adapter->init_count == 0) { 2310 /* Initialize the multiple unicast addresses */ 2311 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2312 2313 /* Workaround for an erratum of 82571 chipst */ 2314 if ((hw->mac.type == e1000_82571) && 2315 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2316 Adapter->unicst_total--; 2317 2318 Adapter->unicst_avail = Adapter->unicst_total; 2319 2320 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2321 /* Clear both the flag and MAC address */ 2322 Adapter->unicst_addr[slot].reg.high = 0; 2323 Adapter->unicst_addr[slot].reg.low = 0; 2324 } 2325 } else { 2326 /* Workaround for an erratum of 82571 chipst */ 2327 if ((hw->mac.type == e1000_82571) && 2328 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2329 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2330 2331 /* Re-configure the RAR registers */ 2332 for (slot = 0; slot < Adapter->unicst_total; slot++) 2333 if (Adapter->unicst_addr[slot].mac.set == 1) 2334 e1000_rar_set(hw, 2335 Adapter->unicst_addr[slot].mac.addr, slot); 2336 } 2337 2338 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2339 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2340 } 2341 2342 static int 2343 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2344 int slot) 2345 { 2346 struct e1000_hw *hw; 2347 2348 hw = &Adapter->shared; 2349 2350 /* 2351 * The first revision of Wiseman silicon (rev 2.0) has an errata 2352 * that requires the receiver to be in reset when any of the 2353 * receive address registers (RAR regs) are accessed. The first 2354 * rev of Wiseman silicon also requires MWI to be disabled when 2355 * a global reset or a receive reset is issued. So before we 2356 * initialize the RARs, we check the rev of the Wiseman controller 2357 * and work around any necessary HW errata. 2358 */ 2359 if ((hw->mac.type == e1000_82542) && 2360 (hw->revision_id == E1000_REVISION_2)) { 2361 e1000_pci_clear_mwi(hw); 2362 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2363 msec_delay(5); 2364 } 2365 if (mac_addr == NULL) { 2366 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2367 E1000_WRITE_FLUSH(hw); 2368 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2369 E1000_WRITE_FLUSH(hw); 2370 /* Clear both the flag and MAC address */ 2371 Adapter->unicst_addr[slot].reg.high = 0; 2372 Adapter->unicst_addr[slot].reg.low = 0; 2373 } else { 2374 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2375 ETHERADDRL); 2376 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2377 Adapter->unicst_addr[slot].mac.set = 1; 2378 } 2379 2380 /* Workaround for an erratum of 82571 chipst */ 2381 if (slot == 0) { 2382 if ((hw->mac.type == e1000_82571) && 2383 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2384 if (mac_addr == NULL) { 2385 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2386 slot << 1, 0); 2387 E1000_WRITE_FLUSH(hw); 2388 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2389 (slot << 1) + 1, 0); 2390 E1000_WRITE_FLUSH(hw); 2391 } else { 2392 e1000_rar_set(hw, (uint8_t *)mac_addr, 2393 LAST_RAR_ENTRY); 2394 } 2395 } 2396 2397 /* 2398 * If we are using Wiseman rev 2.0 silicon, we will have previously 2399 * put the receive in reset, and disabled MWI, to work around some 2400 * HW errata. Now we should take the receiver out of reset, and 2401 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2402 */ 2403 if ((hw->mac.type == e1000_82542) && 2404 (hw->revision_id == E1000_REVISION_2)) { 2405 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2406 msec_delay(1); 2407 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2408 e1000_pci_set_mwi(hw); 2409 e1000g_rx_setup(Adapter); 2410 } 2411 2412 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2413 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2414 return (EIO); 2415 } 2416 2417 return (0); 2418 } 2419 2420 static int 2421 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2422 { 2423 struct e1000_hw *hw = &Adapter->shared; 2424 struct ether_addr *newtable; 2425 size_t new_len; 2426 size_t old_len; 2427 int res = 0; 2428 2429 if ((multiaddr[0] & 01) == 0) { 2430 res = EINVAL; 2431 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2432 goto done; 2433 } 2434 2435 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2436 res = ENOENT; 2437 e1000g_log(Adapter, CE_WARN, 2438 "Adapter requested more than %d mcast addresses", 2439 Adapter->mcast_max_num); 2440 goto done; 2441 } 2442 2443 2444 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2445 old_len = Adapter->mcast_alloc_count * 2446 sizeof (struct ether_addr); 2447 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2448 sizeof (struct ether_addr); 2449 2450 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2451 if (newtable == NULL) { 2452 res = ENOMEM; 2453 e1000g_log(Adapter, CE_WARN, 2454 "Not enough memory to alloc mcast table"); 2455 goto done; 2456 } 2457 2458 if (Adapter->mcast_table != NULL) { 2459 bcopy(Adapter->mcast_table, newtable, old_len); 2460 kmem_free(Adapter->mcast_table, old_len); 2461 } 2462 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2463 Adapter->mcast_table = newtable; 2464 } 2465 2466 bcopy(multiaddr, 2467 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2468 Adapter->mcast_count++; 2469 2470 /* 2471 * Update the MC table in the hardware 2472 */ 2473 e1000g_clear_interrupt(Adapter); 2474 2475 e1000_update_mc_addr_list(hw, 2476 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2477 2478 e1000g_mask_interrupt(Adapter); 2479 2480 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2481 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2482 res = EIO; 2483 } 2484 2485 done: 2486 return (res); 2487 } 2488 2489 static int 2490 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2491 { 2492 struct e1000_hw *hw = &Adapter->shared; 2493 struct ether_addr *newtable; 2494 size_t new_len; 2495 size_t old_len; 2496 unsigned i; 2497 2498 for (i = 0; i < Adapter->mcast_count; i++) { 2499 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2500 ETHERADDRL) == 0) { 2501 for (i++; i < Adapter->mcast_count; i++) { 2502 Adapter->mcast_table[i - 1] = 2503 Adapter->mcast_table[i]; 2504 } 2505 Adapter->mcast_count--; 2506 break; 2507 } 2508 } 2509 2510 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2511 MCAST_ALLOC_SIZE) { 2512 old_len = Adapter->mcast_alloc_count * 2513 sizeof (struct ether_addr); 2514 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2515 sizeof (struct ether_addr); 2516 2517 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2518 if (newtable != NULL) { 2519 bcopy(Adapter->mcast_table, newtable, new_len); 2520 kmem_free(Adapter->mcast_table, old_len); 2521 2522 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2523 Adapter->mcast_table = newtable; 2524 } 2525 } 2526 2527 /* 2528 * Update the MC table in the hardware 2529 */ 2530 e1000g_clear_interrupt(Adapter); 2531 2532 e1000_update_mc_addr_list(hw, 2533 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2534 2535 e1000g_mask_interrupt(Adapter); 2536 2537 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2538 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2539 return (EIO); 2540 } 2541 2542 return (0); 2543 } 2544 2545 static void 2546 e1000g_release_multicast(struct e1000g *Adapter) 2547 { 2548 if (Adapter->mcast_table != NULL) { 2549 kmem_free(Adapter->mcast_table, 2550 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2551 Adapter->mcast_table = NULL; 2552 } 2553 } 2554 2555 int 2556 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2557 { 2558 struct e1000g *Adapter = (struct e1000g *)arg; 2559 int result; 2560 2561 rw_enter(&Adapter->chip_lock, RW_WRITER); 2562 2563 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2564 result = ECANCELED; 2565 goto done; 2566 } 2567 2568 result = (add) ? multicst_add(Adapter, addr) 2569 : multicst_remove(Adapter, addr); 2570 2571 done: 2572 rw_exit(&Adapter->chip_lock); 2573 return (result); 2574 2575 } 2576 2577 int 2578 e1000g_m_promisc(void *arg, boolean_t on) 2579 { 2580 struct e1000g *Adapter = (struct e1000g *)arg; 2581 uint32_t rctl; 2582 2583 rw_enter(&Adapter->chip_lock, RW_WRITER); 2584 2585 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2586 rw_exit(&Adapter->chip_lock); 2587 return (ECANCELED); 2588 } 2589 2590 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2591 2592 if (on) 2593 rctl |= 2594 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2595 else 2596 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2597 2598 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2599 2600 Adapter->e1000g_promisc = on; 2601 2602 rw_exit(&Adapter->chip_lock); 2603 2604 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2605 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2606 return (EIO); 2607 } 2608 2609 return (0); 2610 } 2611 2612 /* 2613 * Entry points to enable and disable interrupts at the granularity of 2614 * a group. 2615 * Turns the poll_mode for the whole adapter on and off to enable or 2616 * override the ring level polling control over the hardware interrupts. 2617 */ 2618 static int 2619 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2620 { 2621 struct e1000g *adapter = (struct e1000g *)arg; 2622 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2623 2624 /* 2625 * Later interrupts at the granularity of the this ring will 2626 * invoke mac_rx() with NULL, indicating the need for another 2627 * software classification. 2628 * We have a single ring usable per adapter now, so we only need to 2629 * reset the rx handle for that one. 2630 * When more RX rings can be used, we should update each one of them. 2631 */ 2632 mutex_enter(&rx_ring->rx_lock); 2633 rx_ring->mrh = NULL; 2634 adapter->poll_mode = B_FALSE; 2635 mutex_exit(&rx_ring->rx_lock); 2636 return (0); 2637 } 2638 2639 static int 2640 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2641 { 2642 struct e1000g *adapter = (struct e1000g *)arg; 2643 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2644 2645 mutex_enter(&rx_ring->rx_lock); 2646 2647 /* 2648 * Later interrupts at the granularity of the this ring will 2649 * invoke mac_rx() with the handle for this ring; 2650 */ 2651 adapter->poll_mode = B_TRUE; 2652 rx_ring->mrh = rx_ring->mrh_init; 2653 mutex_exit(&rx_ring->rx_lock); 2654 return (0); 2655 } 2656 2657 /* 2658 * Entry points to enable and disable interrupts at the granularity of 2659 * a ring. 2660 * adapter poll_mode controls whether we actually proceed with hardware 2661 * interrupt toggling. 2662 */ 2663 static int 2664 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2665 { 2666 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2667 struct e1000g *adapter = rx_ring->adapter; 2668 struct e1000_hw *hw = &adapter->shared; 2669 uint32_t intr_mask; 2670 2671 rw_enter(&adapter->chip_lock, RW_READER); 2672 2673 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2674 rw_exit(&adapter->chip_lock); 2675 return (0); 2676 } 2677 2678 mutex_enter(&rx_ring->rx_lock); 2679 rx_ring->poll_flag = 0; 2680 mutex_exit(&rx_ring->rx_lock); 2681 2682 /* Rx interrupt enabling for MSI and legacy */ 2683 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2684 intr_mask |= E1000_IMS_RXT0; 2685 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2686 E1000_WRITE_FLUSH(hw); 2687 2688 /* Trigger a Rx interrupt to check Rx ring */ 2689 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2690 E1000_WRITE_FLUSH(hw); 2691 2692 rw_exit(&adapter->chip_lock); 2693 return (0); 2694 } 2695 2696 static int 2697 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2698 { 2699 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2700 struct e1000g *adapter = rx_ring->adapter; 2701 struct e1000_hw *hw = &adapter->shared; 2702 2703 rw_enter(&adapter->chip_lock, RW_READER); 2704 2705 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2706 rw_exit(&adapter->chip_lock); 2707 return (0); 2708 } 2709 mutex_enter(&rx_ring->rx_lock); 2710 rx_ring->poll_flag = 1; 2711 mutex_exit(&rx_ring->rx_lock); 2712 2713 /* Rx interrupt disabling for MSI and legacy */ 2714 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2715 E1000_WRITE_FLUSH(hw); 2716 2717 rw_exit(&adapter->chip_lock); 2718 return (0); 2719 } 2720 2721 /* 2722 * e1000g_unicst_find - Find the slot for the specified unicast address 2723 */ 2724 static int 2725 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2726 { 2727 int slot; 2728 2729 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2730 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2731 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2732 mac_addr, ETHERADDRL) == 0)) 2733 return (slot); 2734 } 2735 2736 return (-1); 2737 } 2738 2739 /* 2740 * Entry points to add and remove a MAC address to a ring group. 2741 * The caller takes care of adding and removing the MAC addresses 2742 * to the filter via these two routines. 2743 */ 2744 2745 static int 2746 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2747 { 2748 struct e1000g *Adapter = (struct e1000g *)arg; 2749 int slot, err; 2750 2751 rw_enter(&Adapter->chip_lock, RW_WRITER); 2752 2753 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2754 rw_exit(&Adapter->chip_lock); 2755 return (ECANCELED); 2756 } 2757 2758 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2759 /* The same address is already in slot */ 2760 rw_exit(&Adapter->chip_lock); 2761 return (0); 2762 } 2763 2764 if (Adapter->unicst_avail == 0) { 2765 /* no slots available */ 2766 rw_exit(&Adapter->chip_lock); 2767 return (ENOSPC); 2768 } 2769 2770 /* Search for a free slot */ 2771 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2772 if (Adapter->unicst_addr[slot].mac.set == 0) 2773 break; 2774 } 2775 ASSERT(slot < Adapter->unicst_total); 2776 2777 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2778 if (err == 0) 2779 Adapter->unicst_avail--; 2780 2781 rw_exit(&Adapter->chip_lock); 2782 2783 return (err); 2784 } 2785 2786 static int 2787 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2788 { 2789 struct e1000g *Adapter = (struct e1000g *)arg; 2790 int slot, err; 2791 2792 rw_enter(&Adapter->chip_lock, RW_WRITER); 2793 2794 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2795 rw_exit(&Adapter->chip_lock); 2796 return (ECANCELED); 2797 } 2798 2799 slot = e1000g_unicst_find(Adapter, mac_addr); 2800 if (slot == -1) { 2801 rw_exit(&Adapter->chip_lock); 2802 return (EINVAL); 2803 } 2804 2805 ASSERT(Adapter->unicst_addr[slot].mac.set); 2806 2807 /* Clear this slot */ 2808 err = e1000g_unicst_set(Adapter, NULL, slot); 2809 if (err == 0) 2810 Adapter->unicst_avail++; 2811 2812 rw_exit(&Adapter->chip_lock); 2813 2814 return (err); 2815 } 2816 2817 static int 2818 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2819 { 2820 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2821 2822 mutex_enter(&rx_ring->rx_lock); 2823 rx_ring->ring_gen_num = mr_gen_num; 2824 mutex_exit(&rx_ring->rx_lock); 2825 return (0); 2826 } 2827 2828 /* 2829 * Callback funtion for MAC layer to register all rings. 2830 * 2831 * The hardware supports a single group with currently only one ring 2832 * available. 2833 * Though not offering virtualization ability per se, exposing the 2834 * group/ring still enables the polling and interrupt toggling. 2835 */ 2836 void 2837 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2838 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2839 { 2840 struct e1000g *Adapter = (struct e1000g *)arg; 2841 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2842 mac_intr_t *mintr; 2843 2844 /* 2845 * We advertised only RX group/rings, so the MAC framework shouldn't 2846 * ask for any thing else. 2847 */ 2848 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2849 2850 rx_ring->mrh = rx_ring->mrh_init = rh; 2851 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2852 infop->mri_start = e1000g_ring_start; 2853 infop->mri_stop = NULL; 2854 infop->mri_poll = e1000g_poll_ring; 2855 2856 /* Ring level interrupts */ 2857 mintr = &infop->mri_intr; 2858 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2859 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2860 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2861 } 2862 2863 static void 2864 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2865 mac_group_info_t *infop, mac_group_handle_t gh) 2866 { 2867 struct e1000g *Adapter = (struct e1000g *)arg; 2868 mac_intr_t *mintr; 2869 2870 /* 2871 * We advertised a single RX ring. Getting a request for anything else 2872 * signifies a bug in the MAC framework. 2873 */ 2874 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2875 2876 Adapter->rx_group = gh; 2877 2878 infop->mgi_driver = (mac_group_driver_t)Adapter; 2879 infop->mgi_start = NULL; 2880 infop->mgi_stop = NULL; 2881 infop->mgi_addmac = e1000g_addmac; 2882 infop->mgi_remmac = e1000g_remmac; 2883 infop->mgi_count = 1; 2884 2885 /* Group level interrupts */ 2886 mintr = &infop->mgi_intr; 2887 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2888 mintr->mi_enable = e1000g_rx_group_intr_enable; 2889 mintr->mi_disable = e1000g_rx_group_intr_disable; 2890 } 2891 2892 static boolean_t 2893 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2894 { 2895 struct e1000g *Adapter = (struct e1000g *)arg; 2896 2897 switch (cap) { 2898 case MAC_CAPAB_HCKSUM: { 2899 uint32_t *txflags = cap_data; 2900 2901 if (Adapter->tx_hcksum_enable) 2902 *txflags = HCKSUM_IPHDRCKSUM | 2903 HCKSUM_INET_PARTIAL; 2904 else 2905 return (B_FALSE); 2906 break; 2907 } 2908 2909 case MAC_CAPAB_LSO: { 2910 mac_capab_lso_t *cap_lso = cap_data; 2911 2912 if (Adapter->lso_enable) { 2913 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2914 cap_lso->lso_basic_tcp_ipv4.lso_max = 2915 E1000_LSO_MAXLEN; 2916 } else 2917 return (B_FALSE); 2918 break; 2919 } 2920 case MAC_CAPAB_RINGS: { 2921 mac_capab_rings_t *cap_rings = cap_data; 2922 2923 /* No TX rings exposed yet */ 2924 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2925 return (B_FALSE); 2926 2927 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2928 cap_rings->mr_rnum = 1; 2929 cap_rings->mr_gnum = 1; 2930 cap_rings->mr_rget = e1000g_fill_ring; 2931 cap_rings->mr_gget = e1000g_fill_group; 2932 break; 2933 } 2934 default: 2935 return (B_FALSE); 2936 } 2937 return (B_TRUE); 2938 } 2939 2940 static boolean_t 2941 e1000g_param_locked(mac_prop_id_t pr_num) 2942 { 2943 /* 2944 * All en_* parameters are locked (read-only) while 2945 * the device is in any sort of loopback mode ... 2946 */ 2947 switch (pr_num) { 2948 case MAC_PROP_EN_1000FDX_CAP: 2949 case MAC_PROP_EN_1000HDX_CAP: 2950 case MAC_PROP_EN_100FDX_CAP: 2951 case MAC_PROP_EN_100HDX_CAP: 2952 case MAC_PROP_EN_10FDX_CAP: 2953 case MAC_PROP_EN_10HDX_CAP: 2954 case MAC_PROP_AUTONEG: 2955 case MAC_PROP_FLOWCTRL: 2956 return (B_TRUE); 2957 } 2958 return (B_FALSE); 2959 } 2960 2961 /* 2962 * callback function for set/get of properties 2963 */ 2964 static int 2965 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2966 uint_t pr_valsize, const void *pr_val) 2967 { 2968 struct e1000g *Adapter = arg; 2969 struct e1000_hw *hw = &Adapter->shared; 2970 struct e1000_fc_info *fc = &Adapter->shared.fc; 2971 int err = 0; 2972 link_flowctrl_t flowctrl; 2973 uint32_t cur_mtu, new_mtu; 2974 2975 rw_enter(&Adapter->chip_lock, RW_WRITER); 2976 2977 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2978 rw_exit(&Adapter->chip_lock); 2979 return (ECANCELED); 2980 } 2981 2982 if (Adapter->loopback_mode != E1000G_LB_NONE && 2983 e1000g_param_locked(pr_num)) { 2984 /* 2985 * All en_* parameters are locked (read-only) 2986 * while the device is in any sort of loopback mode. 2987 */ 2988 rw_exit(&Adapter->chip_lock); 2989 return (EBUSY); 2990 } 2991 2992 switch (pr_num) { 2993 case MAC_PROP_EN_1000FDX_CAP: 2994 if (hw->phy.media_type != e1000_media_type_copper) { 2995 err = ENOTSUP; 2996 break; 2997 } 2998 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2999 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3000 goto reset; 3001 case MAC_PROP_EN_100FDX_CAP: 3002 if (hw->phy.media_type != e1000_media_type_copper) { 3003 err = ENOTSUP; 3004 break; 3005 } 3006 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3007 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3008 goto reset; 3009 case MAC_PROP_EN_100HDX_CAP: 3010 if (hw->phy.media_type != e1000_media_type_copper) { 3011 err = ENOTSUP; 3012 break; 3013 } 3014 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3015 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3016 goto reset; 3017 case MAC_PROP_EN_10FDX_CAP: 3018 if (hw->phy.media_type != e1000_media_type_copper) { 3019 err = ENOTSUP; 3020 break; 3021 } 3022 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3023 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3024 goto reset; 3025 case MAC_PROP_EN_10HDX_CAP: 3026 if (hw->phy.media_type != e1000_media_type_copper) { 3027 err = ENOTSUP; 3028 break; 3029 } 3030 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3031 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3032 goto reset; 3033 case MAC_PROP_AUTONEG: 3034 if (hw->phy.media_type != e1000_media_type_copper) { 3035 err = ENOTSUP; 3036 break; 3037 } 3038 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3039 goto reset; 3040 case MAC_PROP_FLOWCTRL: 3041 fc->send_xon = B_TRUE; 3042 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3043 3044 switch (flowctrl) { 3045 default: 3046 err = EINVAL; 3047 break; 3048 case LINK_FLOWCTRL_NONE: 3049 fc->requested_mode = e1000_fc_none; 3050 break; 3051 case LINK_FLOWCTRL_RX: 3052 fc->requested_mode = e1000_fc_rx_pause; 3053 break; 3054 case LINK_FLOWCTRL_TX: 3055 fc->requested_mode = e1000_fc_tx_pause; 3056 break; 3057 case LINK_FLOWCTRL_BI: 3058 fc->requested_mode = e1000_fc_full; 3059 break; 3060 } 3061 reset: 3062 if (err == 0) { 3063 /* check PCH limits & reset the link */ 3064 e1000g_pch_limits(Adapter); 3065 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3066 err = EINVAL; 3067 } 3068 break; 3069 case MAC_PROP_ADV_1000FDX_CAP: 3070 case MAC_PROP_ADV_1000HDX_CAP: 3071 case MAC_PROP_ADV_100FDX_CAP: 3072 case MAC_PROP_ADV_100HDX_CAP: 3073 case MAC_PROP_ADV_10FDX_CAP: 3074 case MAC_PROP_ADV_10HDX_CAP: 3075 case MAC_PROP_EN_1000HDX_CAP: 3076 case MAC_PROP_STATUS: 3077 case MAC_PROP_SPEED: 3078 case MAC_PROP_DUPLEX: 3079 err = ENOTSUP; /* read-only prop. Can't set this. */ 3080 break; 3081 case MAC_PROP_MTU: 3082 /* adapter must be stopped for an MTU change */ 3083 if (Adapter->e1000g_state & E1000G_STARTED) { 3084 err = EBUSY; 3085 break; 3086 } 3087 3088 cur_mtu = Adapter->default_mtu; 3089 3090 /* get new requested MTU */ 3091 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3092 if (new_mtu == cur_mtu) { 3093 err = 0; 3094 break; 3095 } 3096 3097 if ((new_mtu < DEFAULT_MTU) || 3098 (new_mtu > Adapter->max_mtu)) { 3099 err = EINVAL; 3100 break; 3101 } 3102 3103 /* inform MAC framework of new MTU */ 3104 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3105 3106 if (err == 0) { 3107 Adapter->default_mtu = new_mtu; 3108 Adapter->max_frame_size = 3109 e1000g_mtu2maxframe(new_mtu); 3110 3111 /* 3112 * check PCH limits & set buffer sizes to 3113 * match new MTU 3114 */ 3115 e1000g_pch_limits(Adapter); 3116 e1000g_set_bufsize(Adapter); 3117 } 3118 break; 3119 case MAC_PROP_PRIVATE: 3120 err = e1000g_set_priv_prop(Adapter, pr_name, 3121 pr_valsize, pr_val); 3122 break; 3123 default: 3124 err = ENOTSUP; 3125 break; 3126 } 3127 rw_exit(&Adapter->chip_lock); 3128 return (err); 3129 } 3130 3131 static int 3132 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3133 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3134 { 3135 struct e1000g *Adapter = arg; 3136 struct e1000_fc_info *fc = &Adapter->shared.fc; 3137 struct e1000_hw *hw = &Adapter->shared; 3138 int err = 0; 3139 link_flowctrl_t flowctrl; 3140 uint64_t tmp = 0; 3141 3142 if (pr_valsize == 0) 3143 return (EINVAL); 3144 3145 *perm = MAC_PROP_PERM_RW; 3146 3147 bzero(pr_val, pr_valsize); 3148 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3149 return (e1000g_get_def_val(Adapter, pr_num, 3150 pr_valsize, pr_val)); 3151 } 3152 3153 switch (pr_num) { 3154 case MAC_PROP_DUPLEX: 3155 *perm = MAC_PROP_PERM_READ; 3156 if (pr_valsize >= sizeof (link_duplex_t)) { 3157 bcopy(&Adapter->link_duplex, pr_val, 3158 sizeof (link_duplex_t)); 3159 } else 3160 err = EINVAL; 3161 break; 3162 case MAC_PROP_SPEED: 3163 *perm = MAC_PROP_PERM_READ; 3164 if (pr_valsize >= sizeof (uint64_t)) { 3165 tmp = Adapter->link_speed * 1000000ull; 3166 bcopy(&tmp, pr_val, sizeof (tmp)); 3167 } else 3168 err = EINVAL; 3169 break; 3170 case MAC_PROP_AUTONEG: 3171 if (hw->phy.media_type != e1000_media_type_copper) 3172 *perm = MAC_PROP_PERM_READ; 3173 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3174 break; 3175 case MAC_PROP_FLOWCTRL: 3176 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3177 switch (fc->current_mode) { 3178 case e1000_fc_none: 3179 flowctrl = LINK_FLOWCTRL_NONE; 3180 break; 3181 case e1000_fc_rx_pause: 3182 flowctrl = LINK_FLOWCTRL_RX; 3183 break; 3184 case e1000_fc_tx_pause: 3185 flowctrl = LINK_FLOWCTRL_TX; 3186 break; 3187 case e1000_fc_full: 3188 flowctrl = LINK_FLOWCTRL_BI; 3189 break; 3190 } 3191 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3192 } else 3193 err = EINVAL; 3194 break; 3195 case MAC_PROP_ADV_1000FDX_CAP: 3196 *perm = MAC_PROP_PERM_READ; 3197 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3198 break; 3199 case MAC_PROP_EN_1000FDX_CAP: 3200 if (hw->phy.media_type != e1000_media_type_copper) 3201 *perm = MAC_PROP_PERM_READ; 3202 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3203 break; 3204 case MAC_PROP_ADV_1000HDX_CAP: 3205 *perm = MAC_PROP_PERM_READ; 3206 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3207 break; 3208 case MAC_PROP_EN_1000HDX_CAP: 3209 *perm = MAC_PROP_PERM_READ; 3210 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3211 break; 3212 case MAC_PROP_ADV_100FDX_CAP: 3213 *perm = MAC_PROP_PERM_READ; 3214 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3215 break; 3216 case MAC_PROP_EN_100FDX_CAP: 3217 if (hw->phy.media_type != e1000_media_type_copper) 3218 *perm = MAC_PROP_PERM_READ; 3219 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3220 break; 3221 case MAC_PROP_ADV_100HDX_CAP: 3222 *perm = MAC_PROP_PERM_READ; 3223 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3224 break; 3225 case MAC_PROP_EN_100HDX_CAP: 3226 if (hw->phy.media_type != e1000_media_type_copper) 3227 *perm = MAC_PROP_PERM_READ; 3228 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3229 break; 3230 case MAC_PROP_ADV_10FDX_CAP: 3231 *perm = MAC_PROP_PERM_READ; 3232 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3233 break; 3234 case MAC_PROP_EN_10FDX_CAP: 3235 if (hw->phy.media_type != e1000_media_type_copper) 3236 *perm = MAC_PROP_PERM_READ; 3237 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3238 break; 3239 case MAC_PROP_ADV_10HDX_CAP: 3240 *perm = MAC_PROP_PERM_READ; 3241 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3242 break; 3243 case MAC_PROP_EN_10HDX_CAP: 3244 if (hw->phy.media_type != e1000_media_type_copper) 3245 *perm = MAC_PROP_PERM_READ; 3246 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3247 break; 3248 case MAC_PROP_ADV_100T4_CAP: 3249 case MAC_PROP_EN_100T4_CAP: 3250 *perm = MAC_PROP_PERM_READ; 3251 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3252 break; 3253 case MAC_PROP_PRIVATE: 3254 err = e1000g_get_priv_prop(Adapter, pr_name, 3255 pr_flags, pr_valsize, pr_val, perm); 3256 break; 3257 case MAC_PROP_MTU: { 3258 struct e1000_mac_info *mac = &Adapter->shared.mac; 3259 struct e1000_phy_info *phy = &Adapter->shared.phy; 3260 mac_propval_range_t range; 3261 3262 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3263 return (ENOTSUP); 3264 if (pr_valsize < sizeof (mac_propval_range_t)) 3265 return (EINVAL); 3266 range.mpr_count = 1; 3267 range.mpr_type = MAC_PROPVAL_UINT32; 3268 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3269 range.range_uint32[0].mpur_max = Adapter->max_mtu; 3270 /* following MAC type do not support jumbo frames */ 3271 if ((mac->type == e1000_ich8lan) || 3272 ((mac->type == e1000_ich9lan) && (phy->type == 3273 e1000_phy_ife))) { 3274 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3275 } 3276 bcopy(&range, pr_val, sizeof (range)); 3277 break; 3278 } 3279 default: 3280 err = ENOTSUP; 3281 break; 3282 } 3283 return (err); 3284 } 3285 3286 /* ARGSUSED2 */ 3287 static int 3288 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3289 uint_t pr_valsize, const void *pr_val) 3290 { 3291 int err = 0; 3292 long result; 3293 struct e1000_hw *hw = &Adapter->shared; 3294 3295 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3296 if (pr_val == NULL) { 3297 err = EINVAL; 3298 return (err); 3299 } 3300 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3301 if (result < MIN_TX_BCOPY_THRESHOLD || 3302 result > MAX_TX_BCOPY_THRESHOLD) 3303 err = EINVAL; 3304 else { 3305 Adapter->tx_bcopy_thresh = (uint32_t)result; 3306 } 3307 return (err); 3308 } 3309 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3310 if (pr_val == NULL) { 3311 err = EINVAL; 3312 return (err); 3313 } 3314 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3315 if (result < 0 || result > 1) 3316 err = EINVAL; 3317 else { 3318 Adapter->tx_intr_enable = (result == 1) ? 3319 B_TRUE: B_FALSE; 3320 if (Adapter->tx_intr_enable) 3321 e1000g_mask_tx_interrupt(Adapter); 3322 else 3323 e1000g_clear_tx_interrupt(Adapter); 3324 if (e1000g_check_acc_handle( 3325 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3326 ddi_fm_service_impact(Adapter->dip, 3327 DDI_SERVICE_DEGRADED); 3328 err = EIO; 3329 } 3330 } 3331 return (err); 3332 } 3333 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3334 if (pr_val == NULL) { 3335 err = EINVAL; 3336 return (err); 3337 } 3338 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3339 if (result < MIN_TX_INTR_DELAY || 3340 result > MAX_TX_INTR_DELAY) 3341 err = EINVAL; 3342 else { 3343 Adapter->tx_intr_delay = (uint32_t)result; 3344 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3345 if (e1000g_check_acc_handle( 3346 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3347 ddi_fm_service_impact(Adapter->dip, 3348 DDI_SERVICE_DEGRADED); 3349 err = EIO; 3350 } 3351 } 3352 return (err); 3353 } 3354 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3355 if (pr_val == NULL) { 3356 err = EINVAL; 3357 return (err); 3358 } 3359 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3360 if (result < MIN_TX_INTR_ABS_DELAY || 3361 result > MAX_TX_INTR_ABS_DELAY) 3362 err = EINVAL; 3363 else { 3364 Adapter->tx_intr_abs_delay = (uint32_t)result; 3365 E1000_WRITE_REG(hw, E1000_TADV, 3366 Adapter->tx_intr_abs_delay); 3367 if (e1000g_check_acc_handle( 3368 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3369 ddi_fm_service_impact(Adapter->dip, 3370 DDI_SERVICE_DEGRADED); 3371 err = EIO; 3372 } 3373 } 3374 return (err); 3375 } 3376 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3377 if (pr_val == NULL) { 3378 err = EINVAL; 3379 return (err); 3380 } 3381 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3382 if (result < MIN_RX_BCOPY_THRESHOLD || 3383 result > MAX_RX_BCOPY_THRESHOLD) 3384 err = EINVAL; 3385 else 3386 Adapter->rx_bcopy_thresh = (uint32_t)result; 3387 return (err); 3388 } 3389 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3390 if (pr_val == NULL) { 3391 err = EINVAL; 3392 return (err); 3393 } 3394 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3395 if (result < MIN_RX_LIMIT_ON_INTR || 3396 result > MAX_RX_LIMIT_ON_INTR) 3397 err = EINVAL; 3398 else 3399 Adapter->rx_limit_onintr = (uint32_t)result; 3400 return (err); 3401 } 3402 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3403 if (pr_val == NULL) { 3404 err = EINVAL; 3405 return (err); 3406 } 3407 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3408 if (result < MIN_RX_INTR_DELAY || 3409 result > MAX_RX_INTR_DELAY) 3410 err = EINVAL; 3411 else { 3412 Adapter->rx_intr_delay = (uint32_t)result; 3413 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3414 if (e1000g_check_acc_handle( 3415 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3416 ddi_fm_service_impact(Adapter->dip, 3417 DDI_SERVICE_DEGRADED); 3418 err = EIO; 3419 } 3420 } 3421 return (err); 3422 } 3423 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3424 if (pr_val == NULL) { 3425 err = EINVAL; 3426 return (err); 3427 } 3428 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3429 if (result < MIN_RX_INTR_ABS_DELAY || 3430 result > MAX_RX_INTR_ABS_DELAY) 3431 err = EINVAL; 3432 else { 3433 Adapter->rx_intr_abs_delay = (uint32_t)result; 3434 E1000_WRITE_REG(hw, E1000_RADV, 3435 Adapter->rx_intr_abs_delay); 3436 if (e1000g_check_acc_handle( 3437 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3438 ddi_fm_service_impact(Adapter->dip, 3439 DDI_SERVICE_DEGRADED); 3440 err = EIO; 3441 } 3442 } 3443 return (err); 3444 } 3445 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3446 if (pr_val == NULL) { 3447 err = EINVAL; 3448 return (err); 3449 } 3450 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3451 if (result < MIN_INTR_THROTTLING || 3452 result > MAX_INTR_THROTTLING) 3453 err = EINVAL; 3454 else { 3455 if (hw->mac.type >= e1000_82540) { 3456 Adapter->intr_throttling_rate = 3457 (uint32_t)result; 3458 E1000_WRITE_REG(hw, E1000_ITR, 3459 Adapter->intr_throttling_rate); 3460 if (e1000g_check_acc_handle( 3461 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3462 ddi_fm_service_impact(Adapter->dip, 3463 DDI_SERVICE_DEGRADED); 3464 err = EIO; 3465 } 3466 } else 3467 err = EINVAL; 3468 } 3469 return (err); 3470 } 3471 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3472 if (pr_val == NULL) { 3473 err = EINVAL; 3474 return (err); 3475 } 3476 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3477 if (result < 0 || result > 1) 3478 err = EINVAL; 3479 else { 3480 if (hw->mac.type >= e1000_82540) { 3481 Adapter->intr_adaptive = (result == 1) ? 3482 B_TRUE : B_FALSE; 3483 } else { 3484 err = EINVAL; 3485 } 3486 } 3487 return (err); 3488 } 3489 return (ENOTSUP); 3490 } 3491 3492 static int 3493 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3494 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3495 { 3496 int err = ENOTSUP; 3497 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3498 int value; 3499 3500 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3501 *perm = MAC_PROP_PERM_READ; 3502 if (is_default) 3503 goto done; 3504 value = Adapter->param_adv_pause; 3505 err = 0; 3506 goto done; 3507 } 3508 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3509 *perm = MAC_PROP_PERM_READ; 3510 if (is_default) 3511 goto done; 3512 value = Adapter->param_adv_asym_pause; 3513 err = 0; 3514 goto done; 3515 } 3516 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3517 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3518 Adapter->tx_bcopy_thresh); 3519 err = 0; 3520 goto done; 3521 } 3522 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3523 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3524 Adapter->tx_intr_enable); 3525 err = 0; 3526 goto done; 3527 } 3528 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3529 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3530 Adapter->tx_intr_delay); 3531 err = 0; 3532 goto done; 3533 } 3534 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3535 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3536 Adapter->tx_intr_abs_delay); 3537 err = 0; 3538 goto done; 3539 } 3540 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3541 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3542 Adapter->rx_bcopy_thresh); 3543 err = 0; 3544 goto done; 3545 } 3546 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3547 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3548 Adapter->rx_limit_onintr); 3549 err = 0; 3550 goto done; 3551 } 3552 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3553 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3554 Adapter->rx_intr_delay); 3555 err = 0; 3556 goto done; 3557 } 3558 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3559 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3560 Adapter->rx_intr_abs_delay); 3561 err = 0; 3562 goto done; 3563 } 3564 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3565 value = (is_default ? DEFAULT_INTR_THROTTLING : 3566 Adapter->intr_throttling_rate); 3567 err = 0; 3568 goto done; 3569 } 3570 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3571 value = (is_default ? 1 : Adapter->intr_adaptive); 3572 err = 0; 3573 goto done; 3574 } 3575 done: 3576 if (err == 0) { 3577 (void) snprintf(pr_val, pr_valsize, "%d", value); 3578 } 3579 return (err); 3580 } 3581 3582 /* 3583 * e1000g_get_conf - get configurations set in e1000g.conf 3584 * This routine gets user-configured values out of the configuration 3585 * file e1000g.conf. 3586 * 3587 * For each configurable value, there is a minimum, a maximum, and a 3588 * default. 3589 * If user does not configure a value, use the default. 3590 * If user configures below the minimum, use the minumum. 3591 * If user configures above the maximum, use the maxumum. 3592 */ 3593 static void 3594 e1000g_get_conf(struct e1000g *Adapter) 3595 { 3596 struct e1000_hw *hw = &Adapter->shared; 3597 boolean_t tbi_compatibility = B_FALSE; 3598 3599 /* 3600 * get each configurable property from e1000g.conf 3601 */ 3602 3603 /* 3604 * NumTxDescriptors 3605 */ 3606 Adapter->tx_desc_num = 3607 e1000g_get_prop(Adapter, "NumTxDescriptors", 3608 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3609 DEFAULT_NUM_TX_DESCRIPTOR); 3610 3611 /* 3612 * NumRxDescriptors 3613 */ 3614 Adapter->rx_desc_num = 3615 e1000g_get_prop(Adapter, "NumRxDescriptors", 3616 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3617 DEFAULT_NUM_RX_DESCRIPTOR); 3618 3619 /* 3620 * NumRxFreeList 3621 */ 3622 Adapter->rx_freelist_num = 3623 e1000g_get_prop(Adapter, "NumRxFreeList", 3624 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3625 DEFAULT_NUM_RX_FREELIST); 3626 3627 /* 3628 * NumTxPacketList 3629 */ 3630 Adapter->tx_freelist_num = 3631 e1000g_get_prop(Adapter, "NumTxPacketList", 3632 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3633 DEFAULT_NUM_TX_FREELIST); 3634 3635 /* 3636 * FlowControl 3637 */ 3638 hw->fc.send_xon = B_TRUE; 3639 hw->fc.requested_mode = 3640 e1000g_get_prop(Adapter, "FlowControl", 3641 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3642 /* 4 is the setting that says "let the eeprom decide" */ 3643 if (hw->fc.requested_mode == 4) 3644 hw->fc.requested_mode = e1000_fc_default; 3645 3646 /* 3647 * Max Num Receive Packets on Interrupt 3648 */ 3649 Adapter->rx_limit_onintr = 3650 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3651 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3652 DEFAULT_RX_LIMIT_ON_INTR); 3653 3654 /* 3655 * PHY master slave setting 3656 */ 3657 hw->phy.ms_type = 3658 e1000g_get_prop(Adapter, "SetMasterSlave", 3659 e1000_ms_hw_default, e1000_ms_auto, 3660 e1000_ms_hw_default); 3661 3662 /* 3663 * Parameter which controls TBI mode workaround, which is only 3664 * needed on certain switches such as Cisco 6500/Foundry 3665 */ 3666 tbi_compatibility = 3667 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3668 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3669 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3670 3671 /* 3672 * MSI Enable 3673 */ 3674 Adapter->msi_enable = 3675 e1000g_get_prop(Adapter, "MSIEnable", 3676 0, 1, DEFAULT_MSI_ENABLE); 3677 3678 /* 3679 * Interrupt Throttling Rate 3680 */ 3681 Adapter->intr_throttling_rate = 3682 e1000g_get_prop(Adapter, "intr_throttling_rate", 3683 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3684 DEFAULT_INTR_THROTTLING); 3685 3686 /* 3687 * Adaptive Interrupt Blanking Enable/Disable 3688 * It is enabled by default 3689 */ 3690 Adapter->intr_adaptive = 3691 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3692 B_TRUE : B_FALSE; 3693 3694 /* 3695 * Hardware checksum enable/disable parameter 3696 */ 3697 Adapter->tx_hcksum_enable = 3698 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3699 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3700 /* 3701 * Checksum on/off selection via global parameters. 3702 * 3703 * If the chip is flagged as not capable of (correctly) 3704 * handling checksumming, we don't enable it on either 3705 * Rx or Tx side. Otherwise, we take this chip's settings 3706 * from the patchable global defaults. 3707 * 3708 * We advertise our capabilities only if TX offload is 3709 * enabled. On receive, the stack will accept checksummed 3710 * packets anyway, even if we haven't said we can deliver 3711 * them. 3712 */ 3713 switch (hw->mac.type) { 3714 case e1000_82540: 3715 case e1000_82544: 3716 case e1000_82545: 3717 case e1000_82545_rev_3: 3718 case e1000_82546: 3719 case e1000_82546_rev_3: 3720 case e1000_82571: 3721 case e1000_82572: 3722 case e1000_82573: 3723 case e1000_80003es2lan: 3724 break; 3725 /* 3726 * For the following Intel PRO/1000 chipsets, we have not 3727 * tested the hardware checksum offload capability, so we 3728 * disable the capability for them. 3729 * e1000_82542, 3730 * e1000_82543, 3731 * e1000_82541, 3732 * e1000_82541_rev_2, 3733 * e1000_82547, 3734 * e1000_82547_rev_2, 3735 */ 3736 default: 3737 Adapter->tx_hcksum_enable = B_FALSE; 3738 } 3739 3740 /* 3741 * Large Send Offloading(LSO) Enable/Disable 3742 * If the tx hardware checksum is not enabled, LSO should be 3743 * disabled. 3744 */ 3745 Adapter->lso_enable = 3746 e1000g_get_prop(Adapter, "lso_enable", 3747 0, 1, DEFAULT_LSO_ENABLE); 3748 3749 switch (hw->mac.type) { 3750 case e1000_82546: 3751 case e1000_82546_rev_3: 3752 if (Adapter->lso_enable) 3753 Adapter->lso_premature_issue = B_TRUE; 3754 /* FALLTHRU */ 3755 case e1000_82571: 3756 case e1000_82572: 3757 case e1000_82573: 3758 case e1000_80003es2lan: 3759 break; 3760 default: 3761 Adapter->lso_enable = B_FALSE; 3762 } 3763 3764 if (!Adapter->tx_hcksum_enable) { 3765 Adapter->lso_premature_issue = B_FALSE; 3766 Adapter->lso_enable = B_FALSE; 3767 } 3768 3769 /* 3770 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3771 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3772 * will not cross 64k boundary. 3773 */ 3774 Adapter->mem_workaround_82546 = 3775 e1000g_get_prop(Adapter, "mem_workaround_82546", 3776 0, 1, DEFAULT_MEM_WORKAROUND_82546); 3777 3778 /* 3779 * Max number of multicast addresses 3780 */ 3781 Adapter->mcast_max_num = 3782 e1000g_get_prop(Adapter, "mcast_max_num", 3783 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32); 3784 } 3785 3786 /* 3787 * e1000g_get_prop - routine to read properties 3788 * 3789 * Get a user-configure property value out of the configuration 3790 * file e1000g.conf. 3791 * 3792 * Caller provides name of the property, a default value, a minimum 3793 * value, and a maximum value. 3794 * 3795 * Return configured value of the property, with default, minimum and 3796 * maximum properly applied. 3797 */ 3798 static int 3799 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3800 char *propname, /* name of the property */ 3801 int minval, /* minimum acceptable value */ 3802 int maxval, /* maximim acceptable value */ 3803 int defval) /* default value */ 3804 { 3805 int propval; /* value returned for requested property */ 3806 int *props; /* point to array of properties returned */ 3807 uint_t nprops; /* number of property value returned */ 3808 3809 /* 3810 * get the array of properties from the config file 3811 */ 3812 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3813 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3814 /* got some properties, test if we got enough */ 3815 if (Adapter->instance < nprops) { 3816 propval = props[Adapter->instance]; 3817 } else { 3818 /* not enough properties configured */ 3819 propval = defval; 3820 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3821 "Not Enough %s values found in e1000g.conf" 3822 " - set to %d\n", 3823 propname, propval); 3824 } 3825 3826 /* free memory allocated for properties */ 3827 ddi_prop_free(props); 3828 3829 } else { 3830 propval = defval; 3831 } 3832 3833 /* 3834 * enforce limits 3835 */ 3836 if (propval > maxval) { 3837 propval = maxval; 3838 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3839 "Too High %s value in e1000g.conf - set to %d\n", 3840 propname, propval); 3841 } 3842 3843 if (propval < minval) { 3844 propval = minval; 3845 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3846 "Too Low %s value in e1000g.conf - set to %d\n", 3847 propname, propval); 3848 } 3849 3850 return (propval); 3851 } 3852 3853 static boolean_t 3854 e1000g_link_check(struct e1000g *Adapter) 3855 { 3856 uint16_t speed, duplex, phydata; 3857 boolean_t link_changed = B_FALSE; 3858 struct e1000_hw *hw; 3859 uint32_t reg_tarc; 3860 3861 hw = &Adapter->shared; 3862 3863 if (e1000g_link_up(Adapter)) { 3864 /* 3865 * The Link is up, check whether it was marked as down earlier 3866 */ 3867 if (Adapter->link_state != LINK_STATE_UP) { 3868 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3869 Adapter->link_speed = speed; 3870 Adapter->link_duplex = duplex; 3871 Adapter->link_state = LINK_STATE_UP; 3872 link_changed = B_TRUE; 3873 3874 if (Adapter->link_speed == SPEED_1000) 3875 Adapter->stall_threshold = TX_STALL_TIME_2S; 3876 else 3877 Adapter->stall_threshold = TX_STALL_TIME_8S; 3878 3879 Adapter->tx_link_down_timeout = 0; 3880 3881 if ((hw->mac.type == e1000_82571) || 3882 (hw->mac.type == e1000_82572)) { 3883 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3884 if (speed == SPEED_1000) 3885 reg_tarc |= (1 << 21); 3886 else 3887 reg_tarc &= ~(1 << 21); 3888 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3889 } 3890 } 3891 Adapter->smartspeed = 0; 3892 } else { 3893 if (Adapter->link_state != LINK_STATE_DOWN) { 3894 Adapter->link_speed = 0; 3895 Adapter->link_duplex = 0; 3896 Adapter->link_state = LINK_STATE_DOWN; 3897 link_changed = B_TRUE; 3898 3899 /* 3900 * SmartSpeed workaround for Tabor/TanaX, When the 3901 * driver loses link disable auto master/slave 3902 * resolution. 3903 */ 3904 if (hw->phy.type == e1000_phy_igp) { 3905 (void) e1000_read_phy_reg(hw, 3906 PHY_1000T_CTRL, &phydata); 3907 phydata |= CR_1000T_MS_ENABLE; 3908 (void) e1000_write_phy_reg(hw, 3909 PHY_1000T_CTRL, phydata); 3910 } 3911 } else { 3912 e1000g_smartspeed(Adapter); 3913 } 3914 3915 if (Adapter->e1000g_state & E1000G_STARTED) { 3916 if (Adapter->tx_link_down_timeout < 3917 MAX_TX_LINK_DOWN_TIMEOUT) { 3918 Adapter->tx_link_down_timeout++; 3919 } else if (Adapter->tx_link_down_timeout == 3920 MAX_TX_LINK_DOWN_TIMEOUT) { 3921 e1000g_tx_clean(Adapter); 3922 Adapter->tx_link_down_timeout++; 3923 } 3924 } 3925 } 3926 3927 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3928 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3929 3930 return (link_changed); 3931 } 3932 3933 /* 3934 * e1000g_reset_link - Using the link properties to setup the link 3935 */ 3936 int 3937 e1000g_reset_link(struct e1000g *Adapter) 3938 { 3939 struct e1000_mac_info *mac; 3940 struct e1000_phy_info *phy; 3941 struct e1000_hw *hw; 3942 boolean_t invalid; 3943 3944 mac = &Adapter->shared.mac; 3945 phy = &Adapter->shared.phy; 3946 hw = &Adapter->shared; 3947 invalid = B_FALSE; 3948 3949 if (hw->phy.media_type != e1000_media_type_copper) 3950 goto out; 3951 3952 if (Adapter->param_adv_autoneg == 1) { 3953 mac->autoneg = B_TRUE; 3954 phy->autoneg_advertised = 0; 3955 3956 /* 3957 * 1000hdx is not supported for autonegotiation 3958 */ 3959 if (Adapter->param_adv_1000fdx == 1) 3960 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3961 3962 if (Adapter->param_adv_100fdx == 1) 3963 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3964 3965 if (Adapter->param_adv_100hdx == 1) 3966 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3967 3968 if (Adapter->param_adv_10fdx == 1) 3969 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3970 3971 if (Adapter->param_adv_10hdx == 1) 3972 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3973 3974 if (phy->autoneg_advertised == 0) 3975 invalid = B_TRUE; 3976 } else { 3977 mac->autoneg = B_FALSE; 3978 3979 /* 3980 * For Intel copper cards, 1000fdx and 1000hdx are not 3981 * supported for forced link 3982 */ 3983 if (Adapter->param_adv_100fdx == 1) 3984 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3985 else if (Adapter->param_adv_100hdx == 1) 3986 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3987 else if (Adapter->param_adv_10fdx == 1) 3988 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3989 else if (Adapter->param_adv_10hdx == 1) 3990 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3991 else 3992 invalid = B_TRUE; 3993 3994 } 3995 3996 if (invalid) { 3997 e1000g_log(Adapter, CE_WARN, 3998 "Invalid link settings. Setup link to " 3999 "support autonegotiation with all link capabilities."); 4000 mac->autoneg = B_TRUE; 4001 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4002 } 4003 4004 out: 4005 return (e1000_setup_link(&Adapter->shared)); 4006 } 4007 4008 static void 4009 e1000g_timer_tx_resched(struct e1000g *Adapter) 4010 { 4011 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4012 4013 rw_enter(&Adapter->chip_lock, RW_READER); 4014 4015 if (tx_ring->resched_needed && 4016 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4017 drv_usectohz(1000000)) && 4018 (Adapter->e1000g_state & E1000G_STARTED) && 4019 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4020 tx_ring->resched_needed = B_FALSE; 4021 mac_tx_update(Adapter->mh); 4022 E1000G_STAT(tx_ring->stat_reschedule); 4023 E1000G_STAT(tx_ring->stat_timer_reschedule); 4024 } 4025 4026 rw_exit(&Adapter->chip_lock); 4027 } 4028 4029 static void 4030 e1000g_local_timer(void *ws) 4031 { 4032 struct e1000g *Adapter = (struct e1000g *)ws; 4033 struct e1000_hw *hw; 4034 e1000g_ether_addr_t ether_addr; 4035 boolean_t link_changed; 4036 4037 hw = &Adapter->shared; 4038 4039 if (Adapter->e1000g_state & E1000G_ERROR) { 4040 rw_enter(&Adapter->chip_lock, RW_WRITER); 4041 Adapter->e1000g_state &= ~E1000G_ERROR; 4042 rw_exit(&Adapter->chip_lock); 4043 4044 Adapter->reset_count++; 4045 if (e1000g_global_reset(Adapter)) { 4046 ddi_fm_service_impact(Adapter->dip, 4047 DDI_SERVICE_RESTORED); 4048 e1000g_timer_tx_resched(Adapter); 4049 } else 4050 ddi_fm_service_impact(Adapter->dip, 4051 DDI_SERVICE_LOST); 4052 return; 4053 } 4054 4055 if (e1000g_stall_check(Adapter)) { 4056 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4057 "Tx stall detected. Activate automatic recovery.\n"); 4058 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4059 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4060 Adapter->reset_count++; 4061 if (e1000g_reset_adapter(Adapter)) { 4062 ddi_fm_service_impact(Adapter->dip, 4063 DDI_SERVICE_RESTORED); 4064 e1000g_timer_tx_resched(Adapter); 4065 } 4066 return; 4067 } 4068 4069 link_changed = B_FALSE; 4070 rw_enter(&Adapter->chip_lock, RW_READER); 4071 if (Adapter->link_complete) 4072 link_changed = e1000g_link_check(Adapter); 4073 rw_exit(&Adapter->chip_lock); 4074 4075 if (link_changed) { 4076 if (!Adapter->reset_flag) 4077 mac_link_update(Adapter->mh, Adapter->link_state); 4078 if (Adapter->link_state == LINK_STATE_UP) 4079 Adapter->reset_flag = B_FALSE; 4080 } 4081 /* 4082 * Workaround for esb2. Data stuck in fifo on a link 4083 * down event. Reset the adapter to recover it. 4084 */ 4085 if (Adapter->esb2_workaround) { 4086 Adapter->esb2_workaround = B_FALSE; 4087 (void) e1000g_reset_adapter(Adapter); 4088 return; 4089 } 4090 4091 /* 4092 * With 82571 controllers, any locally administered address will 4093 * be overwritten when there is a reset on the other port. 4094 * Detect this circumstance and correct it. 4095 */ 4096 if ((hw->mac.type == e1000_82571) && 4097 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4098 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4099 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4100 4101 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4102 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4103 4104 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4105 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4106 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4107 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4108 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4109 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4110 e1000_rar_set(hw, hw->mac.addr, 0); 4111 } 4112 } 4113 4114 /* 4115 * Long TTL workaround for 82541/82547 4116 */ 4117 (void) e1000_igp_ttl_workaround_82547(hw); 4118 4119 /* 4120 * Check for Adaptive IFS settings If there are lots of collisions 4121 * change the value in steps... 4122 * These properties should only be set for 10/100 4123 */ 4124 if ((hw->phy.media_type == e1000_media_type_copper) && 4125 ((Adapter->link_speed == SPEED_100) || 4126 (Adapter->link_speed == SPEED_10))) { 4127 e1000_update_adaptive(hw); 4128 } 4129 /* 4130 * Set Timer Interrupts 4131 */ 4132 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4133 4134 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4135 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4136 else 4137 e1000g_timer_tx_resched(Adapter); 4138 4139 restart_watchdog_timer(Adapter); 4140 } 4141 4142 /* 4143 * The function e1000g_link_timer() is called when the timer for link setup 4144 * is expired, which indicates the completion of the link setup. The link 4145 * state will not be updated until the link setup is completed. And the 4146 * link state will not be sent to the upper layer through mac_link_update() 4147 * in this function. It will be updated in the local timer routine or the 4148 * interrupt service routine after the interface is started (plumbed). 4149 */ 4150 static void 4151 e1000g_link_timer(void *arg) 4152 { 4153 struct e1000g *Adapter = (struct e1000g *)arg; 4154 4155 mutex_enter(&Adapter->link_lock); 4156 Adapter->link_complete = B_TRUE; 4157 Adapter->link_tid = 0; 4158 mutex_exit(&Adapter->link_lock); 4159 } 4160 4161 /* 4162 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4163 * 4164 * This function read the forced speed and duplex for 10/100 Mbps speeds 4165 * and also for 1000 Mbps speeds from the e1000g.conf file 4166 */ 4167 static void 4168 e1000g_force_speed_duplex(struct e1000g *Adapter) 4169 { 4170 int forced; 4171 struct e1000_mac_info *mac = &Adapter->shared.mac; 4172 struct e1000_phy_info *phy = &Adapter->shared.phy; 4173 4174 /* 4175 * get value out of config file 4176 */ 4177 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4178 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 4179 4180 switch (forced) { 4181 case GDIAG_10_HALF: 4182 /* 4183 * Disable Auto Negotiation 4184 */ 4185 mac->autoneg = B_FALSE; 4186 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4187 break; 4188 case GDIAG_10_FULL: 4189 /* 4190 * Disable Auto Negotiation 4191 */ 4192 mac->autoneg = B_FALSE; 4193 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4194 break; 4195 case GDIAG_100_HALF: 4196 /* 4197 * Disable Auto Negotiation 4198 */ 4199 mac->autoneg = B_FALSE; 4200 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4201 break; 4202 case GDIAG_100_FULL: 4203 /* 4204 * Disable Auto Negotiation 4205 */ 4206 mac->autoneg = B_FALSE; 4207 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4208 break; 4209 case GDIAG_1000_FULL: 4210 /* 4211 * The gigabit spec requires autonegotiation. Therefore, 4212 * when the user wants to force the speed to 1000Mbps, we 4213 * enable AutoNeg, but only allow the harware to advertise 4214 * 1000Mbps. This is different from 10/100 operation, where 4215 * we are allowed to link without any negotiation. 4216 */ 4217 mac->autoneg = B_TRUE; 4218 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4219 break; 4220 default: /* obey the setting of AutoNegAdvertised */ 4221 mac->autoneg = B_TRUE; 4222 phy->autoneg_advertised = 4223 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 4224 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4225 AUTONEG_ADVERTISE_SPEED_DEFAULT); 4226 break; 4227 } /* switch */ 4228 } 4229 4230 /* 4231 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4232 * 4233 * This function reads MaxFrameSize from e1000g.conf 4234 */ 4235 static void 4236 e1000g_get_max_frame_size(struct e1000g *Adapter) 4237 { 4238 int max_frame; 4239 4240 /* 4241 * get value out of config file 4242 */ 4243 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 4244 4245 switch (max_frame) { 4246 case 0: 4247 Adapter->default_mtu = ETHERMTU; 4248 break; 4249 /* 4250 * To avoid excessive memory allocation for rx buffers, 4251 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4252 */ 4253 case 1: 4254 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4255 sizeof (struct ether_vlan_header) - ETHERFCSL - 4256 E1000G_IPALIGNPRESERVEROOM; 4257 break; 4258 case 2: 4259 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4260 sizeof (struct ether_vlan_header) - ETHERFCSL - 4261 E1000G_IPALIGNPRESERVEROOM; 4262 break; 4263 case 3: 4264 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4265 sizeof (struct ether_vlan_header) - ETHERFCSL - 4266 E1000G_IPALIGNPRESERVEROOM; 4267 break; 4268 default: 4269 Adapter->default_mtu = ETHERMTU; 4270 break; 4271 } /* switch */ 4272 4273 /* 4274 * If the user configed MTU is larger than the deivce's maximum MTU, 4275 * the MTU is set to the deivce's maximum value. 4276 */ 4277 if (Adapter->default_mtu > Adapter->max_mtu) 4278 Adapter->default_mtu = Adapter->max_mtu; 4279 4280 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4281 } 4282 4283 /* 4284 * e1000g_pch_limits - Apply limits of the PCH silicon type 4285 * 4286 * At any frame size larger than the ethernet default, 4287 * prevent linking at 10/100 speeds. 4288 */ 4289 static void 4290 e1000g_pch_limits(struct e1000g *Adapter) 4291 { 4292 struct e1000_hw *hw = &Adapter->shared; 4293 4294 /* only applies to PCH silicon type */ 4295 if (hw->mac.type != e1000_pchlan) 4296 return; 4297 4298 /* only applies to frames larger than ethernet default */ 4299 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4300 hw->mac.autoneg = B_TRUE; 4301 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4302 4303 Adapter->param_adv_autoneg = 1; 4304 Adapter->param_adv_1000fdx = 1; 4305 4306 Adapter->param_adv_100fdx = 0; 4307 Adapter->param_adv_100hdx = 0; 4308 Adapter->param_adv_10fdx = 0; 4309 Adapter->param_adv_10hdx = 0; 4310 4311 e1000g_param_sync(Adapter); 4312 } 4313 } 4314 4315 /* 4316 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4317 */ 4318 static uint32_t 4319 e1000g_mtu2maxframe(uint32_t mtu) 4320 { 4321 uint32_t maxframe; 4322 4323 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4324 4325 return (maxframe); 4326 } 4327 4328 static void 4329 arm_watchdog_timer(struct e1000g *Adapter) 4330 { 4331 Adapter->watchdog_tid = 4332 timeout(e1000g_local_timer, 4333 (void *)Adapter, 1 * drv_usectohz(1000000)); 4334 } 4335 #pragma inline(arm_watchdog_timer) 4336 4337 static void 4338 enable_watchdog_timer(struct e1000g *Adapter) 4339 { 4340 mutex_enter(&Adapter->watchdog_lock); 4341 4342 if (!Adapter->watchdog_timer_enabled) { 4343 Adapter->watchdog_timer_enabled = B_TRUE; 4344 Adapter->watchdog_timer_started = B_TRUE; 4345 arm_watchdog_timer(Adapter); 4346 } 4347 4348 mutex_exit(&Adapter->watchdog_lock); 4349 } 4350 4351 static void 4352 disable_watchdog_timer(struct e1000g *Adapter) 4353 { 4354 timeout_id_t tid; 4355 4356 mutex_enter(&Adapter->watchdog_lock); 4357 4358 Adapter->watchdog_timer_enabled = B_FALSE; 4359 Adapter->watchdog_timer_started = B_FALSE; 4360 tid = Adapter->watchdog_tid; 4361 Adapter->watchdog_tid = 0; 4362 4363 mutex_exit(&Adapter->watchdog_lock); 4364 4365 if (tid != 0) 4366 (void) untimeout(tid); 4367 } 4368 4369 static void 4370 start_watchdog_timer(struct e1000g *Adapter) 4371 { 4372 mutex_enter(&Adapter->watchdog_lock); 4373 4374 if (Adapter->watchdog_timer_enabled) { 4375 if (!Adapter->watchdog_timer_started) { 4376 Adapter->watchdog_timer_started = B_TRUE; 4377 arm_watchdog_timer(Adapter); 4378 } 4379 } 4380 4381 mutex_exit(&Adapter->watchdog_lock); 4382 } 4383 4384 static void 4385 restart_watchdog_timer(struct e1000g *Adapter) 4386 { 4387 mutex_enter(&Adapter->watchdog_lock); 4388 4389 if (Adapter->watchdog_timer_started) 4390 arm_watchdog_timer(Adapter); 4391 4392 mutex_exit(&Adapter->watchdog_lock); 4393 } 4394 4395 static void 4396 stop_watchdog_timer(struct e1000g *Adapter) 4397 { 4398 timeout_id_t tid; 4399 4400 mutex_enter(&Adapter->watchdog_lock); 4401 4402 Adapter->watchdog_timer_started = B_FALSE; 4403 tid = Adapter->watchdog_tid; 4404 Adapter->watchdog_tid = 0; 4405 4406 mutex_exit(&Adapter->watchdog_lock); 4407 4408 if (tid != 0) 4409 (void) untimeout(tid); 4410 } 4411 4412 static void 4413 stop_link_timer(struct e1000g *Adapter) 4414 { 4415 timeout_id_t tid; 4416 4417 /* Disable the link timer */ 4418 mutex_enter(&Adapter->link_lock); 4419 4420 tid = Adapter->link_tid; 4421 Adapter->link_tid = 0; 4422 4423 mutex_exit(&Adapter->link_lock); 4424 4425 if (tid != 0) 4426 (void) untimeout(tid); 4427 } 4428 4429 static void 4430 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4431 { 4432 timeout_id_t tid; 4433 4434 /* Disable the tx timer for 82547 chipset */ 4435 mutex_enter(&tx_ring->tx_lock); 4436 4437 tx_ring->timer_enable_82547 = B_FALSE; 4438 tid = tx_ring->timer_id_82547; 4439 tx_ring->timer_id_82547 = 0; 4440 4441 mutex_exit(&tx_ring->tx_lock); 4442 4443 if (tid != 0) 4444 (void) untimeout(tid); 4445 } 4446 4447 void 4448 e1000g_clear_interrupt(struct e1000g *Adapter) 4449 { 4450 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4451 0xffffffff & ~E1000_IMS_RXSEQ); 4452 } 4453 4454 void 4455 e1000g_mask_interrupt(struct e1000g *Adapter) 4456 { 4457 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4458 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4459 4460 if (Adapter->tx_intr_enable) 4461 e1000g_mask_tx_interrupt(Adapter); 4462 } 4463 4464 /* 4465 * This routine is called by e1000g_quiesce(), therefore must not block. 4466 */ 4467 void 4468 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4469 { 4470 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4471 } 4472 4473 void 4474 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4475 { 4476 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4477 } 4478 4479 void 4480 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4481 { 4482 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4483 } 4484 4485 static void 4486 e1000g_smartspeed(struct e1000g *Adapter) 4487 { 4488 struct e1000_hw *hw = &Adapter->shared; 4489 uint16_t phy_status; 4490 uint16_t phy_ctrl; 4491 4492 /* 4493 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4494 * advertising 1000Full, we don't even use the workaround 4495 */ 4496 if ((hw->phy.type != e1000_phy_igp) || 4497 !hw->mac.autoneg || 4498 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4499 return; 4500 4501 /* 4502 * True if this is the first call of this function or after every 4503 * 30 seconds of not having link 4504 */ 4505 if (Adapter->smartspeed == 0) { 4506 /* 4507 * If Master/Slave config fault is asserted twice, we 4508 * assume back-to-back 4509 */ 4510 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4511 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4512 return; 4513 4514 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4515 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4516 return; 4517 /* 4518 * We're assuming back-2-back because our status register 4519 * insists! there's a fault in the master/slave 4520 * relationship that was "negotiated" 4521 */ 4522 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4523 /* 4524 * Is the phy configured for manual configuration of 4525 * master/slave? 4526 */ 4527 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4528 /* 4529 * Yes. Then disable manual configuration (enable 4530 * auto configuration) of master/slave 4531 */ 4532 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4533 (void) e1000_write_phy_reg(hw, 4534 PHY_1000T_CTRL, phy_ctrl); 4535 /* 4536 * Effectively starting the clock 4537 */ 4538 Adapter->smartspeed++; 4539 /* 4540 * Restart autonegotiation 4541 */ 4542 if (!e1000_phy_setup_autoneg(hw) && 4543 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4544 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4545 MII_CR_RESTART_AUTO_NEG); 4546 (void) e1000_write_phy_reg(hw, 4547 PHY_CONTROL, phy_ctrl); 4548 } 4549 } 4550 return; 4551 /* 4552 * Has 6 seconds transpired still without link? Remember, 4553 * you should reset the smartspeed counter once you obtain 4554 * link 4555 */ 4556 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4557 /* 4558 * Yes. Remember, we did at the start determine that 4559 * there's a master/slave configuration fault, so we're 4560 * still assuming there's someone on the other end, but we 4561 * just haven't yet been able to talk to it. We then 4562 * re-enable auto configuration of master/slave to see if 4563 * we're running 2/3 pair cables. 4564 */ 4565 /* 4566 * If still no link, perhaps using 2/3 pair cable 4567 */ 4568 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4569 phy_ctrl |= CR_1000T_MS_ENABLE; 4570 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4571 /* 4572 * Restart autoneg with phy enabled for manual 4573 * configuration of master/slave 4574 */ 4575 if (!e1000_phy_setup_autoneg(hw) && 4576 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4577 phy_ctrl |= 4578 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4579 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4580 } 4581 /* 4582 * Hopefully, there are no more faults and we've obtained 4583 * link as a result. 4584 */ 4585 } 4586 /* 4587 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4588 * seconds) 4589 */ 4590 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4591 Adapter->smartspeed = 0; 4592 } 4593 4594 static boolean_t 4595 is_valid_mac_addr(uint8_t *mac_addr) 4596 { 4597 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4598 const uint8_t addr_test2[6] = 4599 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4600 4601 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4602 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4603 return (B_FALSE); 4604 4605 return (B_TRUE); 4606 } 4607 4608 /* 4609 * e1000g_stall_check - check for tx stall 4610 * 4611 * This function checks if the adapter is stalled (in transmit). 4612 * 4613 * It is called each time the watchdog timeout is invoked. 4614 * If the transmit descriptor reclaim continuously fails, 4615 * the watchdog value will increment by 1. If the watchdog 4616 * value exceeds the threshold, the adapter is assumed to 4617 * have stalled and need to be reset. 4618 */ 4619 static boolean_t 4620 e1000g_stall_check(struct e1000g *Adapter) 4621 { 4622 e1000g_tx_ring_t *tx_ring; 4623 4624 tx_ring = Adapter->tx_ring; 4625 4626 if (Adapter->link_state != LINK_STATE_UP) 4627 return (B_FALSE); 4628 4629 (void) e1000g_recycle(tx_ring); 4630 4631 if (Adapter->stall_flag) { 4632 Adapter->stall_flag = B_FALSE; 4633 Adapter->reset_flag = B_TRUE; 4634 return (B_TRUE); 4635 } 4636 4637 return (B_FALSE); 4638 } 4639 4640 #ifdef E1000G_DEBUG 4641 static enum ioc_reply 4642 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4643 { 4644 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4645 e1000g_peekpoke_t *ppd; 4646 uint64_t mem_va; 4647 uint64_t maxoff; 4648 boolean_t peek; 4649 4650 switch (iocp->ioc_cmd) { 4651 4652 case E1000G_IOC_REG_PEEK: 4653 peek = B_TRUE; 4654 break; 4655 4656 case E1000G_IOC_REG_POKE: 4657 peek = B_FALSE; 4658 break; 4659 4660 deault: 4661 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4662 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4663 iocp->ioc_cmd); 4664 return (IOC_INVAL); 4665 } 4666 4667 /* 4668 * Validate format of ioctl 4669 */ 4670 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4671 return (IOC_INVAL); 4672 if (mp->b_cont == NULL) 4673 return (IOC_INVAL); 4674 4675 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4676 4677 /* 4678 * Validate request parameters 4679 */ 4680 switch (ppd->pp_acc_space) { 4681 4682 default: 4683 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4684 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4685 ppd->pp_acc_space); 4686 return (IOC_INVAL); 4687 4688 case E1000G_PP_SPACE_REG: 4689 /* 4690 * Memory-mapped I/O space 4691 */ 4692 ASSERT(ppd->pp_acc_size == 4); 4693 if (ppd->pp_acc_size != 4) 4694 return (IOC_INVAL); 4695 4696 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4697 return (IOC_INVAL); 4698 4699 mem_va = 0; 4700 maxoff = 0x10000; 4701 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4702 break; 4703 4704 case E1000G_PP_SPACE_E1000G: 4705 /* 4706 * E1000g data structure! 4707 */ 4708 mem_va = (uintptr_t)e1000gp; 4709 maxoff = sizeof (struct e1000g); 4710 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4711 break; 4712 4713 } 4714 4715 if (ppd->pp_acc_offset >= maxoff) 4716 return (IOC_INVAL); 4717 4718 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4719 return (IOC_INVAL); 4720 4721 /* 4722 * All OK - go! 4723 */ 4724 ppd->pp_acc_offset += mem_va; 4725 (*ppfn)(e1000gp, ppd); 4726 return (peek ? IOC_REPLY : IOC_ACK); 4727 } 4728 4729 static void 4730 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4731 { 4732 ddi_acc_handle_t handle; 4733 uint32_t *regaddr; 4734 4735 handle = e1000gp->osdep.reg_handle; 4736 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4737 (uintptr_t)ppd->pp_acc_offset); 4738 4739 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4740 } 4741 4742 static void 4743 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4744 { 4745 ddi_acc_handle_t handle; 4746 uint32_t *regaddr; 4747 uint32_t value; 4748 4749 handle = e1000gp->osdep.reg_handle; 4750 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4751 (uintptr_t)ppd->pp_acc_offset); 4752 value = (uint32_t)ppd->pp_acc_data; 4753 4754 ddi_put32(handle, regaddr, value); 4755 } 4756 4757 static void 4758 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4759 { 4760 uint64_t value; 4761 void *vaddr; 4762 4763 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4764 4765 switch (ppd->pp_acc_size) { 4766 case 1: 4767 value = *(uint8_t *)vaddr; 4768 break; 4769 4770 case 2: 4771 value = *(uint16_t *)vaddr; 4772 break; 4773 4774 case 4: 4775 value = *(uint32_t *)vaddr; 4776 break; 4777 4778 case 8: 4779 value = *(uint64_t *)vaddr; 4780 break; 4781 } 4782 4783 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4784 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4785 (void *)e1000gp, (void *)ppd, value, vaddr); 4786 4787 ppd->pp_acc_data = value; 4788 } 4789 4790 static void 4791 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4792 { 4793 uint64_t value; 4794 void *vaddr; 4795 4796 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4797 value = ppd->pp_acc_data; 4798 4799 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4800 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4801 (void *)e1000gp, (void *)ppd, value, vaddr); 4802 4803 switch (ppd->pp_acc_size) { 4804 case 1: 4805 *(uint8_t *)vaddr = (uint8_t)value; 4806 break; 4807 4808 case 2: 4809 *(uint16_t *)vaddr = (uint16_t)value; 4810 break; 4811 4812 case 4: 4813 *(uint32_t *)vaddr = (uint32_t)value; 4814 break; 4815 4816 case 8: 4817 *(uint64_t *)vaddr = (uint64_t)value; 4818 break; 4819 } 4820 } 4821 #endif 4822 4823 /* 4824 * Loopback Support 4825 */ 4826 static lb_property_t lb_normal = 4827 { normal, "normal", E1000G_LB_NONE }; 4828 static lb_property_t lb_external1000 = 4829 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4830 static lb_property_t lb_external100 = 4831 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4832 static lb_property_t lb_external10 = 4833 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4834 static lb_property_t lb_phy = 4835 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4836 4837 static enum ioc_reply 4838 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4839 { 4840 lb_info_sz_t *lbsp; 4841 lb_property_t *lbpp; 4842 struct e1000_hw *hw; 4843 uint32_t *lbmp; 4844 uint32_t size; 4845 uint32_t value; 4846 4847 hw = &Adapter->shared; 4848 4849 if (mp->b_cont == NULL) 4850 return (IOC_INVAL); 4851 4852 if (!e1000g_check_loopback_support(hw)) { 4853 e1000g_log(NULL, CE_WARN, 4854 "Loopback is not supported on e1000g%d", Adapter->instance); 4855 return (IOC_INVAL); 4856 } 4857 4858 switch (iocp->ioc_cmd) { 4859 default: 4860 return (IOC_INVAL); 4861 4862 case LB_GET_INFO_SIZE: 4863 size = sizeof (lb_info_sz_t); 4864 if (iocp->ioc_count != size) 4865 return (IOC_INVAL); 4866 4867 rw_enter(&Adapter->chip_lock, RW_WRITER); 4868 e1000g_get_phy_state(Adapter); 4869 4870 /* 4871 * Workaround for hardware faults. In order to get a stable 4872 * state of phy, we will wait for a specific interval and 4873 * try again. The time delay is an experiential value based 4874 * on our testing. 4875 */ 4876 msec_delay(100); 4877 e1000g_get_phy_state(Adapter); 4878 rw_exit(&Adapter->chip_lock); 4879 4880 value = sizeof (lb_normal); 4881 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4882 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4883 (hw->phy.media_type == e1000_media_type_fiber) || 4884 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4885 value += sizeof (lb_phy); 4886 switch (hw->mac.type) { 4887 case e1000_82571: 4888 case e1000_82572: 4889 case e1000_80003es2lan: 4890 value += sizeof (lb_external1000); 4891 break; 4892 } 4893 } 4894 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4895 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4896 value += sizeof (lb_external100); 4897 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4898 value += sizeof (lb_external10); 4899 4900 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4901 *lbsp = value; 4902 break; 4903 4904 case LB_GET_INFO: 4905 value = sizeof (lb_normal); 4906 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4907 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4908 (hw->phy.media_type == e1000_media_type_fiber) || 4909 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4910 value += sizeof (lb_phy); 4911 switch (hw->mac.type) { 4912 case e1000_82571: 4913 case e1000_82572: 4914 case e1000_80003es2lan: 4915 value += sizeof (lb_external1000); 4916 break; 4917 } 4918 } 4919 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4920 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4921 value += sizeof (lb_external100); 4922 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4923 value += sizeof (lb_external10); 4924 4925 size = value; 4926 if (iocp->ioc_count != size) 4927 return (IOC_INVAL); 4928 4929 value = 0; 4930 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4931 lbpp[value++] = lb_normal; 4932 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4933 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4934 (hw->phy.media_type == e1000_media_type_fiber) || 4935 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4936 lbpp[value++] = lb_phy; 4937 switch (hw->mac.type) { 4938 case e1000_82571: 4939 case e1000_82572: 4940 case e1000_80003es2lan: 4941 lbpp[value++] = lb_external1000; 4942 break; 4943 } 4944 } 4945 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4946 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4947 lbpp[value++] = lb_external100; 4948 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4949 lbpp[value++] = lb_external10; 4950 break; 4951 4952 case LB_GET_MODE: 4953 size = sizeof (uint32_t); 4954 if (iocp->ioc_count != size) 4955 return (IOC_INVAL); 4956 4957 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4958 *lbmp = Adapter->loopback_mode; 4959 break; 4960 4961 case LB_SET_MODE: 4962 size = 0; 4963 if (iocp->ioc_count != sizeof (uint32_t)) 4964 return (IOC_INVAL); 4965 4966 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4967 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4968 return (IOC_INVAL); 4969 break; 4970 } 4971 4972 iocp->ioc_count = size; 4973 iocp->ioc_error = 0; 4974 4975 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4976 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4977 return (IOC_INVAL); 4978 } 4979 4980 return (IOC_REPLY); 4981 } 4982 4983 static boolean_t 4984 e1000g_check_loopback_support(struct e1000_hw *hw) 4985 { 4986 switch (hw->mac.type) { 4987 case e1000_82540: 4988 case e1000_82545: 4989 case e1000_82545_rev_3: 4990 case e1000_82546: 4991 case e1000_82546_rev_3: 4992 case e1000_82541: 4993 case e1000_82541_rev_2: 4994 case e1000_82547: 4995 case e1000_82547_rev_2: 4996 case e1000_82571: 4997 case e1000_82572: 4998 case e1000_82573: 4999 case e1000_82574: 5000 case e1000_80003es2lan: 5001 case e1000_ich9lan: 5002 case e1000_ich10lan: 5003 return (B_TRUE); 5004 } 5005 return (B_FALSE); 5006 } 5007 5008 static boolean_t 5009 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5010 { 5011 struct e1000_hw *hw; 5012 int i, times; 5013 boolean_t link_up; 5014 5015 if (mode == Adapter->loopback_mode) 5016 return (B_TRUE); 5017 5018 hw = &Adapter->shared; 5019 times = 0; 5020 5021 Adapter->loopback_mode = mode; 5022 5023 if (mode == E1000G_LB_NONE) { 5024 /* Reset the chip */ 5025 hw->phy.autoneg_wait_to_complete = B_TRUE; 5026 (void) e1000g_reset_adapter(Adapter); 5027 hw->phy.autoneg_wait_to_complete = B_FALSE; 5028 return (B_TRUE); 5029 } 5030 5031 again: 5032 5033 rw_enter(&Adapter->chip_lock, RW_WRITER); 5034 5035 switch (mode) { 5036 default: 5037 rw_exit(&Adapter->chip_lock); 5038 return (B_FALSE); 5039 5040 case E1000G_LB_EXTERNAL_1000: 5041 e1000g_set_external_loopback_1000(Adapter); 5042 break; 5043 5044 case E1000G_LB_EXTERNAL_100: 5045 e1000g_set_external_loopback_100(Adapter); 5046 break; 5047 5048 case E1000G_LB_EXTERNAL_10: 5049 e1000g_set_external_loopback_10(Adapter); 5050 break; 5051 5052 case E1000G_LB_INTERNAL_PHY: 5053 e1000g_set_internal_loopback(Adapter); 5054 break; 5055 } 5056 5057 times++; 5058 5059 rw_exit(&Adapter->chip_lock); 5060 5061 /* Wait for link up */ 5062 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5063 msec_delay(100); 5064 5065 rw_enter(&Adapter->chip_lock, RW_WRITER); 5066 5067 link_up = e1000g_link_up(Adapter); 5068 5069 rw_exit(&Adapter->chip_lock); 5070 5071 if (!link_up) { 5072 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5073 "Failed to get the link up"); 5074 if (times < 2) { 5075 /* Reset the link */ 5076 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5077 "Reset the link ..."); 5078 (void) e1000g_reset_adapter(Adapter); 5079 goto again; 5080 } 5081 } 5082 5083 return (B_TRUE); 5084 } 5085 5086 /* 5087 * The following loopback settings are from Intel's technical 5088 * document - "How To Loopback". All the register settings and 5089 * time delay values are directly inherited from the document 5090 * without more explanations available. 5091 */ 5092 static void 5093 e1000g_set_internal_loopback(struct e1000g *Adapter) 5094 { 5095 struct e1000_hw *hw; 5096 uint32_t ctrl; 5097 uint32_t status; 5098 uint16_t phy_ctrl; 5099 uint16_t phy_reg; 5100 uint32_t txcw; 5101 5102 hw = &Adapter->shared; 5103 5104 /* Disable Smart Power Down */ 5105 phy_spd_state(hw, B_FALSE); 5106 5107 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5108 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5109 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5110 5111 switch (hw->mac.type) { 5112 case e1000_82540: 5113 case e1000_82545: 5114 case e1000_82545_rev_3: 5115 case e1000_82546: 5116 case e1000_82546_rev_3: 5117 case e1000_82573: 5118 /* Auto-MDI/MDIX off */ 5119 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5120 /* Reset PHY to update Auto-MDI/MDIX */ 5121 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5122 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5123 /* Reset PHY to auto-neg off and force 1000 */ 5124 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5125 phy_ctrl | MII_CR_RESET); 5126 /* 5127 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5128 * See comments above e1000g_set_internal_loopback() for the 5129 * background. 5130 */ 5131 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5132 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5133 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5134 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5135 break; 5136 case e1000_80003es2lan: 5137 /* Force Link Up */ 5138 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5139 0x1CC); 5140 /* Sets PCS loopback at 1Gbs */ 5141 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5142 0x1046); 5143 break; 5144 } 5145 5146 /* 5147 * The following registers should be set for e1000_phy_bm phy type. 5148 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5149 * For others, we do not need to set these registers. 5150 */ 5151 if (hw->phy.type == e1000_phy_bm) { 5152 /* Set Default MAC Interface speed to 1GB */ 5153 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5154 phy_reg &= ~0x0007; 5155 phy_reg |= 0x006; 5156 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5157 /* Assert SW reset for above settings to take effect */ 5158 (void) e1000_phy_commit(hw); 5159 msec_delay(1); 5160 /* Force Full Duplex */ 5161 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5162 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5163 phy_reg | 0x000C); 5164 /* Set Link Up (in force link) */ 5165 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5166 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5167 phy_reg | 0x0040); 5168 /* Force Link */ 5169 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5170 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5171 phy_reg | 0x0040); 5172 /* Set Early Link Enable */ 5173 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5174 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5175 phy_reg | 0x0400); 5176 } 5177 5178 /* Set loopback */ 5179 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5180 5181 msec_delay(250); 5182 5183 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5184 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5185 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5186 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5187 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5188 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5189 E1000_CTRL_FD); /* Force Duplex to FULL */ 5190 5191 switch (hw->mac.type) { 5192 case e1000_82540: 5193 case e1000_82545: 5194 case e1000_82545_rev_3: 5195 case e1000_82546: 5196 case e1000_82546_rev_3: 5197 /* 5198 * For some serdes we'll need to commit the writes now 5199 * so that the status is updated on link 5200 */ 5201 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5202 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5203 msec_delay(100); 5204 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5205 } 5206 5207 if (hw->phy.media_type == e1000_media_type_copper) { 5208 /* Invert Loss of Signal */ 5209 ctrl |= E1000_CTRL_ILOS; 5210 } else { 5211 /* Set ILOS on fiber nic if half duplex is detected */ 5212 status = E1000_READ_REG(hw, E1000_STATUS); 5213 if ((status & E1000_STATUS_FD) == 0) 5214 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5215 } 5216 break; 5217 5218 case e1000_82571: 5219 case e1000_82572: 5220 /* 5221 * The fiber/SerDes versions of this adapter do not contain an 5222 * accessible PHY. Therefore, loopback beyond MAC must be done 5223 * using SerDes analog loopback. 5224 */ 5225 if (hw->phy.media_type != e1000_media_type_copper) { 5226 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5227 txcw = E1000_READ_REG(hw, E1000_TXCW); 5228 txcw &= ~((uint32_t)1 << 31); 5229 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5230 5231 /* 5232 * Write 0x410 to Serdes Control register 5233 * to enable Serdes analog loopback 5234 */ 5235 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5236 msec_delay(10); 5237 } 5238 5239 status = E1000_READ_REG(hw, E1000_STATUS); 5240 /* Set ILOS on fiber nic if half duplex is detected */ 5241 if ((hw->phy.media_type == e1000_media_type_fiber) && 5242 ((status & E1000_STATUS_FD) == 0 || 5243 (status & E1000_STATUS_LU) == 0)) 5244 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5245 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5246 ctrl |= E1000_CTRL_SLU; 5247 break; 5248 5249 case e1000_82573: 5250 ctrl |= E1000_CTRL_ILOS; 5251 break; 5252 case e1000_ich9lan: 5253 case e1000_ich10lan: 5254 ctrl |= E1000_CTRL_SLU; 5255 break; 5256 } 5257 if (hw->phy.type == e1000_phy_bm) 5258 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5259 5260 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5261 } 5262 5263 static void 5264 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5265 { 5266 struct e1000_hw *hw; 5267 uint32_t rctl; 5268 uint32_t ctrl_ext; 5269 uint32_t ctrl; 5270 uint32_t status; 5271 uint32_t txcw; 5272 uint16_t phydata; 5273 5274 hw = &Adapter->shared; 5275 5276 /* Disable Smart Power Down */ 5277 phy_spd_state(hw, B_FALSE); 5278 5279 switch (hw->mac.type) { 5280 case e1000_82571: 5281 case e1000_82572: 5282 switch (hw->phy.media_type) { 5283 case e1000_media_type_copper: 5284 /* Force link up (Must be done before the PHY writes) */ 5285 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5286 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5287 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5288 5289 rctl = E1000_READ_REG(hw, E1000_RCTL); 5290 rctl |= (E1000_RCTL_EN | 5291 E1000_RCTL_SBP | 5292 E1000_RCTL_UPE | 5293 E1000_RCTL_MPE | 5294 E1000_RCTL_LPE | 5295 E1000_RCTL_BAM); /* 0x803E */ 5296 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5297 5298 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5299 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5300 E1000_CTRL_EXT_SDP6_DATA | 5301 E1000_CTRL_EXT_SDP3_DATA | 5302 E1000_CTRL_EXT_SDP4_DIR | 5303 E1000_CTRL_EXT_SDP6_DIR | 5304 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5305 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5306 5307 /* 5308 * This sequence tunes the PHY's SDP and no customer 5309 * settable values. For background, see comments above 5310 * e1000g_set_internal_loopback(). 5311 */ 5312 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5313 msec_delay(10); 5314 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5315 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5316 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5317 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5318 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5319 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5320 5321 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5322 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5323 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5324 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5325 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5326 5327 msec_delay(50); 5328 break; 5329 case e1000_media_type_fiber: 5330 case e1000_media_type_internal_serdes: 5331 status = E1000_READ_REG(hw, E1000_STATUS); 5332 if (((status & E1000_STATUS_LU) == 0) || 5333 (hw->phy.media_type == 5334 e1000_media_type_internal_serdes)) { 5335 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5336 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5337 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5338 } 5339 5340 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5341 txcw = E1000_READ_REG(hw, E1000_TXCW); 5342 txcw &= ~((uint32_t)1 << 31); 5343 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5344 5345 /* 5346 * Write 0x410 to Serdes Control register 5347 * to enable Serdes analog loopback 5348 */ 5349 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5350 msec_delay(10); 5351 break; 5352 default: 5353 break; 5354 } 5355 break; 5356 case e1000_82574: 5357 case e1000_80003es2lan: 5358 case e1000_ich9lan: 5359 case e1000_ich10lan: 5360 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5361 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5362 phydata | (1 << 5)); 5363 Adapter->param_adv_autoneg = 1; 5364 Adapter->param_adv_1000fdx = 1; 5365 (void) e1000g_reset_link(Adapter); 5366 break; 5367 } 5368 } 5369 5370 static void 5371 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5372 { 5373 struct e1000_hw *hw; 5374 uint32_t ctrl; 5375 uint16_t phy_ctrl; 5376 5377 hw = &Adapter->shared; 5378 5379 /* Disable Smart Power Down */ 5380 phy_spd_state(hw, B_FALSE); 5381 5382 phy_ctrl = (MII_CR_FULL_DUPLEX | 5383 MII_CR_SPEED_100); 5384 5385 /* Force 100/FD, reset PHY */ 5386 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5387 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5388 msec_delay(10); 5389 5390 /* Force 100/FD */ 5391 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5392 phy_ctrl); /* 0x2100 */ 5393 msec_delay(10); 5394 5395 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5396 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5397 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5398 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5399 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5400 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5401 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5402 E1000_CTRL_FD); /* Force Duplex to FULL */ 5403 5404 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5405 } 5406 5407 static void 5408 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5409 { 5410 struct e1000_hw *hw; 5411 uint32_t ctrl; 5412 uint16_t phy_ctrl; 5413 5414 hw = &Adapter->shared; 5415 5416 /* Disable Smart Power Down */ 5417 phy_spd_state(hw, B_FALSE); 5418 5419 phy_ctrl = (MII_CR_FULL_DUPLEX | 5420 MII_CR_SPEED_10); 5421 5422 /* Force 10/FD, reset PHY */ 5423 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5424 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5425 msec_delay(10); 5426 5427 /* Force 10/FD */ 5428 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5429 phy_ctrl); /* 0x0100 */ 5430 msec_delay(10); 5431 5432 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5433 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5434 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5435 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5436 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5437 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5438 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5439 E1000_CTRL_FD); /* Force Duplex to FULL */ 5440 5441 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5442 } 5443 5444 #ifdef __sparc 5445 static boolean_t 5446 e1000g_find_mac_address(struct e1000g *Adapter) 5447 { 5448 struct e1000_hw *hw = &Adapter->shared; 5449 uchar_t *bytes; 5450 struct ether_addr sysaddr; 5451 uint_t nelts; 5452 int err; 5453 boolean_t found = B_FALSE; 5454 5455 /* 5456 * The "vendor's factory-set address" may already have 5457 * been extracted from the chip, but if the property 5458 * "local-mac-address" is set we use that instead. 5459 * 5460 * We check whether it looks like an array of 6 5461 * bytes (which it should, if OBP set it). If we can't 5462 * make sense of it this way, we'll ignore it. 5463 */ 5464 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5465 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5466 if (err == DDI_PROP_SUCCESS) { 5467 if (nelts == ETHERADDRL) { 5468 while (nelts--) 5469 hw->mac.addr[nelts] = bytes[nelts]; 5470 found = B_TRUE; 5471 } 5472 ddi_prop_free(bytes); 5473 } 5474 5475 /* 5476 * Look up the OBP property "local-mac-address?". If the user has set 5477 * 'local-mac-address? = false', use "the system address" instead. 5478 */ 5479 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5480 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5481 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5482 if (localetheraddr(NULL, &sysaddr) != 0) { 5483 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5484 found = B_TRUE; 5485 } 5486 } 5487 ddi_prop_free(bytes); 5488 } 5489 5490 /* 5491 * Finally(!), if there's a valid "mac-address" property (created 5492 * if we netbooted from this interface), we must use this instead 5493 * of any of the above to ensure that the NFS/install server doesn't 5494 * get confused by the address changing as Solaris takes over! 5495 */ 5496 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5497 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5498 if (err == DDI_PROP_SUCCESS) { 5499 if (nelts == ETHERADDRL) { 5500 while (nelts--) 5501 hw->mac.addr[nelts] = bytes[nelts]; 5502 found = B_TRUE; 5503 } 5504 ddi_prop_free(bytes); 5505 } 5506 5507 if (found) { 5508 bcopy(hw->mac.addr, hw->mac.perm_addr, 5509 ETHERADDRL); 5510 } 5511 5512 return (found); 5513 } 5514 #endif 5515 5516 static int 5517 e1000g_add_intrs(struct e1000g *Adapter) 5518 { 5519 dev_info_t *devinfo; 5520 int intr_types; 5521 int rc; 5522 5523 devinfo = Adapter->dip; 5524 5525 /* Get supported interrupt types */ 5526 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5527 5528 if (rc != DDI_SUCCESS) { 5529 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5530 "Get supported interrupt types failed: %d\n", rc); 5531 return (DDI_FAILURE); 5532 } 5533 5534 /* 5535 * Based on Intel Technical Advisory document (TA-160), there are some 5536 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5537 * that it supports MSI, but in fact has problems. 5538 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5539 * PCI/PCI-X NICs. 5540 */ 5541 if (Adapter->shared.mac.type < e1000_82571) 5542 Adapter->msi_enable = B_FALSE; 5543 5544 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5545 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5546 5547 if (rc != DDI_SUCCESS) { 5548 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5549 "Add MSI failed, trying Legacy interrupts\n"); 5550 } else { 5551 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5552 } 5553 } 5554 5555 if ((Adapter->intr_type == 0) && 5556 (intr_types & DDI_INTR_TYPE_FIXED)) { 5557 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5558 5559 if (rc != DDI_SUCCESS) { 5560 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5561 "Add Legacy interrupts failed\n"); 5562 return (DDI_FAILURE); 5563 } 5564 5565 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5566 } 5567 5568 if (Adapter->intr_type == 0) { 5569 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5570 "No interrupts registered\n"); 5571 return (DDI_FAILURE); 5572 } 5573 5574 return (DDI_SUCCESS); 5575 } 5576 5577 /* 5578 * e1000g_intr_add() handles MSI/Legacy interrupts 5579 */ 5580 static int 5581 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5582 { 5583 dev_info_t *devinfo; 5584 int count, avail, actual; 5585 int x, y, rc, inum = 0; 5586 int flag; 5587 ddi_intr_handler_t *intr_handler; 5588 5589 devinfo = Adapter->dip; 5590 5591 /* get number of interrupts */ 5592 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5593 if ((rc != DDI_SUCCESS) || (count == 0)) { 5594 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5595 "Get interrupt number failed. Return: %d, count: %d\n", 5596 rc, count); 5597 return (DDI_FAILURE); 5598 } 5599 5600 /* get number of available interrupts */ 5601 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5602 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5603 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5604 "Get interrupt available number failed. " 5605 "Return: %d, available: %d\n", rc, avail); 5606 return (DDI_FAILURE); 5607 } 5608 5609 if (avail < count) { 5610 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5611 "Interrupts count: %d, available: %d\n", 5612 count, avail); 5613 } 5614 5615 /* Allocate an array of interrupt handles */ 5616 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5617 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5618 5619 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5620 flag = DDI_INTR_ALLOC_NORMAL; 5621 5622 /* call ddi_intr_alloc() */ 5623 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5624 count, &actual, flag); 5625 5626 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5627 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5628 "Allocate interrupts failed: %d\n", rc); 5629 5630 kmem_free(Adapter->htable, Adapter->intr_size); 5631 return (DDI_FAILURE); 5632 } 5633 5634 if (actual < count) { 5635 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5636 "Interrupts requested: %d, received: %d\n", 5637 count, actual); 5638 } 5639 5640 Adapter->intr_cnt = actual; 5641 5642 /* Get priority for first msi, assume remaining are all the same */ 5643 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5644 5645 if (rc != DDI_SUCCESS) { 5646 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5647 "Get interrupt priority failed: %d\n", rc); 5648 5649 /* Free already allocated intr */ 5650 for (y = 0; y < actual; y++) 5651 (void) ddi_intr_free(Adapter->htable[y]); 5652 5653 kmem_free(Adapter->htable, Adapter->intr_size); 5654 return (DDI_FAILURE); 5655 } 5656 5657 /* 5658 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5659 * use the interrupt service routine e1000g_intr_pciexpress() 5660 * to avoid interrupt stealing when sharing interrupt with other 5661 * devices. 5662 */ 5663 if (Adapter->shared.mac.type < e1000_82571) 5664 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5665 else 5666 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5667 5668 /* Call ddi_intr_add_handler() */ 5669 for (x = 0; x < actual; x++) { 5670 rc = ddi_intr_add_handler(Adapter->htable[x], 5671 intr_handler, (caddr_t)Adapter, NULL); 5672 5673 if (rc != DDI_SUCCESS) { 5674 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5675 "Add interrupt handler failed: %d\n", rc); 5676 5677 /* Remove already added handler */ 5678 for (y = 0; y < x; y++) 5679 (void) ddi_intr_remove_handler( 5680 Adapter->htable[y]); 5681 5682 /* Free already allocated intr */ 5683 for (y = 0; y < actual; y++) 5684 (void) ddi_intr_free(Adapter->htable[y]); 5685 5686 kmem_free(Adapter->htable, Adapter->intr_size); 5687 return (DDI_FAILURE); 5688 } 5689 } 5690 5691 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5692 5693 if (rc != DDI_SUCCESS) { 5694 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5695 "Get interrupt cap failed: %d\n", rc); 5696 5697 /* Free already allocated intr */ 5698 for (y = 0; y < actual; y++) { 5699 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5700 (void) ddi_intr_free(Adapter->htable[y]); 5701 } 5702 5703 kmem_free(Adapter->htable, Adapter->intr_size); 5704 return (DDI_FAILURE); 5705 } 5706 5707 return (DDI_SUCCESS); 5708 } 5709 5710 static int 5711 e1000g_rem_intrs(struct e1000g *Adapter) 5712 { 5713 int x; 5714 int rc; 5715 5716 for (x = 0; x < Adapter->intr_cnt; x++) { 5717 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5718 if (rc != DDI_SUCCESS) { 5719 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5720 "Remove intr handler failed: %d\n", rc); 5721 return (DDI_FAILURE); 5722 } 5723 5724 rc = ddi_intr_free(Adapter->htable[x]); 5725 if (rc != DDI_SUCCESS) { 5726 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5727 "Free intr failed: %d\n", rc); 5728 return (DDI_FAILURE); 5729 } 5730 } 5731 5732 kmem_free(Adapter->htable, Adapter->intr_size); 5733 5734 return (DDI_SUCCESS); 5735 } 5736 5737 static int 5738 e1000g_enable_intrs(struct e1000g *Adapter) 5739 { 5740 int x; 5741 int rc; 5742 5743 /* Enable interrupts */ 5744 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5745 /* Call ddi_intr_block_enable() for MSI */ 5746 rc = ddi_intr_block_enable(Adapter->htable, 5747 Adapter->intr_cnt); 5748 if (rc != DDI_SUCCESS) { 5749 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5750 "Enable block intr failed: %d\n", rc); 5751 return (DDI_FAILURE); 5752 } 5753 } else { 5754 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5755 for (x = 0; x < Adapter->intr_cnt; x++) { 5756 rc = ddi_intr_enable(Adapter->htable[x]); 5757 if (rc != DDI_SUCCESS) { 5758 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5759 "Enable intr failed: %d\n", rc); 5760 return (DDI_FAILURE); 5761 } 5762 } 5763 } 5764 5765 return (DDI_SUCCESS); 5766 } 5767 5768 static int 5769 e1000g_disable_intrs(struct e1000g *Adapter) 5770 { 5771 int x; 5772 int rc; 5773 5774 /* Disable all interrupts */ 5775 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5776 rc = ddi_intr_block_disable(Adapter->htable, 5777 Adapter->intr_cnt); 5778 if (rc != DDI_SUCCESS) { 5779 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5780 "Disable block intr failed: %d\n", rc); 5781 return (DDI_FAILURE); 5782 } 5783 } else { 5784 for (x = 0; x < Adapter->intr_cnt; x++) { 5785 rc = ddi_intr_disable(Adapter->htable[x]); 5786 if (rc != DDI_SUCCESS) { 5787 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5788 "Disable intr failed: %d\n", rc); 5789 return (DDI_FAILURE); 5790 } 5791 } 5792 } 5793 5794 return (DDI_SUCCESS); 5795 } 5796 5797 /* 5798 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5799 */ 5800 static void 5801 e1000g_get_phy_state(struct e1000g *Adapter) 5802 { 5803 struct e1000_hw *hw = &Adapter->shared; 5804 5805 if (hw->phy.media_type == e1000_media_type_copper) { 5806 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5807 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5808 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 5809 &Adapter->phy_an_adv); 5810 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 5811 &Adapter->phy_an_exp); 5812 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 5813 &Adapter->phy_ext_status); 5814 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 5815 &Adapter->phy_1000t_ctrl); 5816 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5817 &Adapter->phy_1000t_status); 5818 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 5819 &Adapter->phy_lp_able); 5820 5821 Adapter->param_autoneg_cap = 5822 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5823 Adapter->param_pause_cap = 5824 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5825 Adapter->param_asym_pause_cap = 5826 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5827 Adapter->param_1000fdx_cap = 5828 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5829 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5830 Adapter->param_1000hdx_cap = 5831 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5832 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5833 Adapter->param_100t4_cap = 5834 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5835 Adapter->param_100fdx_cap = 5836 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5837 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5838 Adapter->param_100hdx_cap = 5839 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5840 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5841 Adapter->param_10fdx_cap = 5842 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5843 Adapter->param_10hdx_cap = 5844 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5845 5846 Adapter->param_adv_autoneg = hw->mac.autoneg; 5847 Adapter->param_adv_pause = 5848 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5849 Adapter->param_adv_asym_pause = 5850 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5851 Adapter->param_adv_1000hdx = 5852 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5853 Adapter->param_adv_100t4 = 5854 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5855 if (Adapter->param_adv_autoneg == 1) { 5856 Adapter->param_adv_1000fdx = 5857 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 5858 ? 1 : 0; 5859 Adapter->param_adv_100fdx = 5860 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 5861 ? 1 : 0; 5862 Adapter->param_adv_100hdx = 5863 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 5864 ? 1 : 0; 5865 Adapter->param_adv_10fdx = 5866 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5867 Adapter->param_adv_10hdx = 5868 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5869 } 5870 5871 Adapter->param_lp_autoneg = 5872 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5873 Adapter->param_lp_pause = 5874 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5875 Adapter->param_lp_asym_pause = 5876 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5877 Adapter->param_lp_1000fdx = 5878 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5879 Adapter->param_lp_1000hdx = 5880 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5881 Adapter->param_lp_100t4 = 5882 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5883 Adapter->param_lp_100fdx = 5884 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5885 Adapter->param_lp_100hdx = 5886 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5887 Adapter->param_lp_10fdx = 5888 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5889 Adapter->param_lp_10hdx = 5890 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5891 } else { 5892 /* 5893 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 5894 * it can only work with 1Gig Full Duplex Link Partner. 5895 */ 5896 Adapter->param_autoneg_cap = 0; 5897 Adapter->param_pause_cap = 1; 5898 Adapter->param_asym_pause_cap = 1; 5899 Adapter->param_1000fdx_cap = 1; 5900 Adapter->param_1000hdx_cap = 0; 5901 Adapter->param_100t4_cap = 0; 5902 Adapter->param_100fdx_cap = 0; 5903 Adapter->param_100hdx_cap = 0; 5904 Adapter->param_10fdx_cap = 0; 5905 Adapter->param_10hdx_cap = 0; 5906 5907 Adapter->param_adv_autoneg = 0; 5908 Adapter->param_adv_pause = 1; 5909 Adapter->param_adv_asym_pause = 1; 5910 Adapter->param_adv_1000fdx = 1; 5911 Adapter->param_adv_1000hdx = 0; 5912 Adapter->param_adv_100t4 = 0; 5913 Adapter->param_adv_100fdx = 0; 5914 Adapter->param_adv_100hdx = 0; 5915 Adapter->param_adv_10fdx = 0; 5916 Adapter->param_adv_10hdx = 0; 5917 5918 Adapter->param_lp_autoneg = 0; 5919 Adapter->param_lp_pause = 0; 5920 Adapter->param_lp_asym_pause = 0; 5921 Adapter->param_lp_1000fdx = 0; 5922 Adapter->param_lp_1000hdx = 0; 5923 Adapter->param_lp_100t4 = 0; 5924 Adapter->param_lp_100fdx = 0; 5925 Adapter->param_lp_100hdx = 0; 5926 Adapter->param_lp_10fdx = 0; 5927 Adapter->param_lp_10hdx = 0; 5928 } 5929 } 5930 5931 /* 5932 * FMA support 5933 */ 5934 5935 int 5936 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5937 { 5938 ddi_fm_error_t de; 5939 5940 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5941 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5942 return (de.fme_status); 5943 } 5944 5945 int 5946 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5947 { 5948 ddi_fm_error_t de; 5949 5950 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5951 return (de.fme_status); 5952 } 5953 5954 /* 5955 * The IO fault service error handling callback function 5956 */ 5957 /* ARGSUSED2 */ 5958 static int 5959 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5960 { 5961 /* 5962 * as the driver can always deal with an error in any dma or 5963 * access handle, we can just return the fme_status value. 5964 */ 5965 pci_ereport_post(dip, err, NULL); 5966 return (err->fme_status); 5967 } 5968 5969 static void 5970 e1000g_fm_init(struct e1000g *Adapter) 5971 { 5972 ddi_iblock_cookie_t iblk; 5973 int fma_acc_flag, fma_dma_flag; 5974 5975 /* Only register with IO Fault Services if we have some capability */ 5976 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5977 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5978 fma_acc_flag = 1; 5979 } else { 5980 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5981 fma_acc_flag = 0; 5982 } 5983 5984 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5985 fma_dma_flag = 1; 5986 } else { 5987 fma_dma_flag = 0; 5988 } 5989 5990 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5991 5992 if (Adapter->fm_capabilities) { 5993 5994 /* Register capabilities with IO Fault Services */ 5995 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5996 5997 /* 5998 * Initialize pci ereport capabilities if ereport capable 5999 */ 6000 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6001 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6002 pci_ereport_setup(Adapter->dip); 6003 6004 /* 6005 * Register error callback if error callback capable 6006 */ 6007 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6008 ddi_fm_handler_register(Adapter->dip, 6009 e1000g_fm_error_cb, (void*) Adapter); 6010 } 6011 } 6012 6013 static void 6014 e1000g_fm_fini(struct e1000g *Adapter) 6015 { 6016 /* Only unregister FMA capabilities if we registered some */ 6017 if (Adapter->fm_capabilities) { 6018 6019 /* 6020 * Release any resources allocated by pci_ereport_setup() 6021 */ 6022 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6023 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6024 pci_ereport_teardown(Adapter->dip); 6025 6026 /* 6027 * Un-register error callback if error callback capable 6028 */ 6029 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6030 ddi_fm_handler_unregister(Adapter->dip); 6031 6032 /* Unregister from IO Fault Services */ 6033 mutex_enter(&e1000g_rx_detach_lock); 6034 ddi_fm_fini(Adapter->dip); 6035 if (Adapter->priv_dip != NULL) { 6036 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6037 } 6038 mutex_exit(&e1000g_rx_detach_lock); 6039 } 6040 } 6041 6042 void 6043 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6044 { 6045 uint64_t ena; 6046 char buf[FM_MAX_CLASS]; 6047 6048 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6049 ena = fm_ena_generate(0, FM_ENA_FMT1); 6050 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6051 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6052 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6053 } 6054 } 6055 6056 /* 6057 * quiesce(9E) entry point. 6058 * 6059 * This function is called when the system is single-threaded at high 6060 * PIL with preemption disabled. Therefore, this function must not be 6061 * blocked. 6062 * 6063 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6064 * DDI_FAILURE indicates an error condition and should almost never happen. 6065 */ 6066 static int 6067 e1000g_quiesce(dev_info_t *devinfo) 6068 { 6069 struct e1000g *Adapter; 6070 6071 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6072 6073 if (Adapter == NULL) 6074 return (DDI_FAILURE); 6075 6076 e1000g_clear_all_interrupts(Adapter); 6077 6078 (void) e1000_reset_hw(&Adapter->shared); 6079 6080 /* Setup our HW Tx Head & Tail descriptor pointers */ 6081 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6082 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6083 6084 /* Setup our HW Rx Head & Tail descriptor pointers */ 6085 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6086 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6087 6088 return (DDI_SUCCESS); 6089 } 6090 6091 static int 6092 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 6093 uint_t pr_valsize, void *pr_val) 6094 { 6095 link_flowctrl_t fl; 6096 struct e1000_hw *hw = &Adapter->shared; 6097 int err = 0; 6098 6099 ASSERT(pr_valsize > 0); 6100 switch (pr_num) { 6101 case MAC_PROP_AUTONEG: 6102 if (hw->phy.media_type != e1000_media_type_copper) 6103 *(uint8_t *)pr_val = 0; 6104 else 6105 *(uint8_t *)pr_val = 6106 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) 6107 ? 1 : 0); 6108 break; 6109 case MAC_PROP_FLOWCTRL: 6110 if (pr_valsize < sizeof (link_flowctrl_t)) 6111 return (EINVAL); 6112 fl = LINK_FLOWCTRL_BI; 6113 bcopy(&fl, pr_val, sizeof (fl)); 6114 break; 6115 case MAC_PROP_ADV_1000FDX_CAP: 6116 case MAC_PROP_EN_1000FDX_CAP: 6117 if (hw->phy.media_type != e1000_media_type_copper) 6118 *(uint8_t *)pr_val = 1; 6119 else 6120 *(uint8_t *)pr_val = 6121 ((Adapter->phy_ext_status & 6122 IEEE_ESR_1000T_FD_CAPS) || 6123 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) 6124 ? 1 : 0; 6125 break; 6126 case MAC_PROP_ADV_1000HDX_CAP: 6127 case MAC_PROP_EN_1000HDX_CAP: 6128 *(uint8_t *)pr_val = 0; 6129 break; 6130 case MAC_PROP_ADV_100FDX_CAP: 6131 case MAC_PROP_EN_100FDX_CAP: 6132 if (hw->phy.media_type != e1000_media_type_copper) 6133 *(uint8_t *)pr_val = 0; 6134 else 6135 *(uint8_t *)pr_val = 6136 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6137 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 6138 ? 1 : 0; 6139 break; 6140 case MAC_PROP_ADV_100HDX_CAP: 6141 case MAC_PROP_EN_100HDX_CAP: 6142 if (hw->phy.media_type != e1000_media_type_copper) 6143 *(uint8_t *)pr_val = 0; 6144 else 6145 *(uint8_t *)pr_val = 6146 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6147 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 6148 ? 1 : 0; 6149 break; 6150 case MAC_PROP_ADV_10FDX_CAP: 6151 case MAC_PROP_EN_10FDX_CAP: 6152 if (hw->phy.media_type != e1000_media_type_copper) 6153 *(uint8_t *)pr_val = 0; 6154 else 6155 *(uint8_t *)pr_val = 6156 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6157 break; 6158 case MAC_PROP_ADV_10HDX_CAP: 6159 case MAC_PROP_EN_10HDX_CAP: 6160 if (hw->phy.media_type != e1000_media_type_copper) 6161 *(uint8_t *)pr_val = 0; 6162 else 6163 *(uint8_t *)pr_val = 6164 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6165 break; 6166 default: 6167 err = ENOTSUP; 6168 break; 6169 } 6170 return (err); 6171 } 6172 6173 /* 6174 * synchronize the adv* and en* parameters. 6175 * 6176 * See comments in <sys/dld.h> for details of the *_en_* 6177 * parameters. The usage of ndd for setting adv parameters will 6178 * synchronize all the en parameters with the e1000g parameters, 6179 * implicitly disabling any settings made via dladm. 6180 */ 6181 static void 6182 e1000g_param_sync(struct e1000g *Adapter) 6183 { 6184 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6185 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6186 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6187 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6188 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6189 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6190 } 6191 6192 /* 6193 * e1000g_get_driver_control - tell manageability firmware that the driver 6194 * has control. 6195 */ 6196 static void 6197 e1000g_get_driver_control(struct e1000_hw *hw) 6198 { 6199 uint32_t ctrl_ext; 6200 uint32_t swsm; 6201 6202 /* tell manageability firmware the driver has taken over */ 6203 switch (hw->mac.type) { 6204 case e1000_82573: 6205 swsm = E1000_READ_REG(hw, E1000_SWSM); 6206 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6207 break; 6208 case e1000_82571: 6209 case e1000_82572: 6210 case e1000_82574: 6211 case e1000_80003es2lan: 6212 case e1000_ich8lan: 6213 case e1000_ich9lan: 6214 case e1000_ich10lan: 6215 case e1000_pchlan: 6216 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6217 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6218 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6219 break; 6220 default: 6221 /* no manageability firmware: do nothing */ 6222 break; 6223 } 6224 } 6225 6226 /* 6227 * e1000g_release_driver_control - tell manageability firmware that the driver 6228 * has released control. 6229 */ 6230 static void 6231 e1000g_release_driver_control(struct e1000_hw *hw) 6232 { 6233 uint32_t ctrl_ext; 6234 uint32_t swsm; 6235 6236 /* tell manageability firmware the driver has released control */ 6237 switch (hw->mac.type) { 6238 case e1000_82573: 6239 swsm = E1000_READ_REG(hw, E1000_SWSM); 6240 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6241 break; 6242 case e1000_82571: 6243 case e1000_82572: 6244 case e1000_82574: 6245 case e1000_80003es2lan: 6246 case e1000_ich8lan: 6247 case e1000_ich9lan: 6248 case e1000_ich10lan: 6249 case e1000_pchlan: 6250 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6251 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6252 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6253 break; 6254 default: 6255 /* no manageability firmware: do nothing */ 6256 break; 6257 } 6258 } 6259 6260 /* 6261 * Restore e1000g promiscuous mode. 6262 */ 6263 static void 6264 e1000g_restore_promisc(struct e1000g *Adapter) 6265 { 6266 if (Adapter->e1000g_promisc) { 6267 uint32_t rctl; 6268 6269 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6270 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6271 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6272 } 6273 } 6274