1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routine for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point * 37 * routines. * 38 * This file also contains routines that takes care of initialization * 39 * uninit routine and interrupt routine * 40 * * 41 * * 42 * Environment: * 43 * Kernel Mode - * 44 * * 45 * ********************************************************************** 46 */ 47 48 #include <sys/dlpi.h> 49 #include <sys/mac.h> 50 #include "e1000g_sw.h" 51 #include "e1000g_debug.h" 52 53 #define E1000_RX_INTPT_TIME 128 54 #define E1000_RX_PKT_CNT 8 55 56 static char ident[] = "Intel PRO/1000 Ethernet 5.1.11"; 57 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 58 static char e1000g_version[] = "Driver Ver. 5.1.11"; 59 60 /* 61 * Proto types for DDI entry points 62 */ 63 static int e1000gattach(dev_info_t *, ddi_attach_cmd_t); 64 static int e1000gdetach(dev_info_t *, ddi_detach_cmd_t); 65 66 /* 67 * init and intr routines prototype 68 */ 69 static int e1000g_resume(dev_info_t *devinfo); 70 static int e1000g_suspend(dev_info_t *devinfo); 71 static uint_t e1000g_intr_pciexpress(caddr_t); 72 static uint_t e1000g_intr(caddr_t); 73 static void e1000g_intr_work(struct e1000g *, uint32_t); 74 #pragma inline(e1000g_intr_work) 75 static int e1000g_init(struct e1000g *); 76 static int e1000g_start(struct e1000g *); 77 static void e1000g_stop(struct e1000g *); 78 static int e1000g_m_start(void *); 79 static void e1000g_m_stop(void *); 80 static int e1000g_m_promisc(void *, boolean_t); 81 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 82 static int e1000g_m_unicst(void *, const uint8_t *); 83 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 84 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 85 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 86 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 87 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 88 static void e1000g_m_blank(void *, time_t, uint32_t); 89 static void e1000g_m_resources(void *); 90 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 91 static void e1000g_init_locks(struct e1000g *Adapter); 92 static void e1000g_destroy_locks(struct e1000g *Adapter); 93 static int e1000g_set_driver_params(struct e1000g *Adapter); 94 static int e1000g_register_mac(struct e1000g *Adapter); 95 static boolean_t e1000g_rx_drain(struct e1000g *Adapter); 96 static boolean_t e1000g_tx_drain(struct e1000g *Adapter); 97 static void e1000g_init_unicst(struct e1000g *Adapter); 98 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 99 100 /* 101 * Local routines 102 */ 103 static void e1000g_tx_drop(struct e1000g *Adapter); 104 static void e1000g_link_timer(void *); 105 static void e1000g_LocalTimer(void *); 106 static boolean_t e1000g_link_check(struct e1000g *); 107 static boolean_t e1000g_stall_check(struct e1000g *); 108 static void e1000g_smartspeed(struct e1000g *); 109 static void e1000g_getparam(struct e1000g *Adapter); 110 static int e1000g_getprop(struct e1000g *, char *, int, int, int); 111 static void e1000g_error(dev_info_t *dip, char *fmt, char *a1, 112 char *a2, char *a3, char *a4, char *a5, char *a6); 113 static void enable_timeout(struct e1000g *Adapter); 114 static void disable_timeout(struct e1000g *Adapter); 115 static void start_timeout(struct e1000g *Adapter); 116 static void restart_timeout(struct e1000g *Adapter); 117 static void stop_timeout(struct e1000g *Adapter); 118 static void e1000g_force_speed_duplex(struct e1000g *Adapter); 119 static void e1000g_get_max_frame_size(struct e1000g *Adapter); 120 static boolean_t is_valid_mac_addr(uint8_t *mac_addr); 121 static void e1000g_unattach(dev_info_t *, struct e1000g *); 122 static void e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 123 static void e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 124 static void e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 125 static void e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 126 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *e1000gp, 127 struct iocblk *iocp, mblk_t *mp); 128 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *Adapter, 129 struct iocblk *iocp, mblk_t *mp); 130 static boolean_t e1000g_set_loopback_mode(struct e1000g *Adapter, 131 uint32_t mode); 132 static void e1000g_set_internal_loopback(struct e1000g *Adapter); 133 static void e1000g_set_external_loopback_1000(struct e1000g *Adapter); 134 static void e1000g_set_external_loopback_100(struct e1000g *Adapter); 135 static void e1000g_set_external_loopback_10(struct e1000g *Adapter); 136 static int e1000g_add_intrs(struct e1000g *Adapter); 137 static int e1000g_intr_add(struct e1000g *Adapter, int intr_type); 138 static int e1000g_rem_intrs(struct e1000g *Adapter); 139 static int e1000g_enable_intrs(struct e1000g *Adapter); 140 static int e1000g_disable_intrs(struct e1000g *Adapter); 141 static boolean_t e1000g_link_up(struct e1000g *Adapter); 142 #ifdef __sparc 143 static boolean_t e1000g_find_mac_address(struct e1000g *Adapter); 144 #endif 145 146 static struct cb_ops cb_ws_ops = { 147 nulldev, /* cb_open */ 148 nulldev, /* cb_close */ 149 nodev, /* cb_strategy */ 150 nodev, /* cb_print */ 151 nodev, /* cb_dump */ 152 nodev, /* cb_read */ 153 nodev, /* cb_write */ 154 nodev, /* cb_ioctl */ 155 nodev, /* cb_devmap */ 156 nodev, /* cb_mmap */ 157 nodev, /* cb_segmap */ 158 nochpoll, /* cb_chpoll */ 159 ddi_prop_op, /* cb_prop_op */ 160 NULL, /* cb_stream */ 161 D_MP | D_HOTPLUG, /* cb_flag */ 162 CB_REV, /* cb_rev */ 163 nodev, /* cb_aread */ 164 nodev /* cb_awrite */ 165 }; 166 167 static struct dev_ops ws_ops = { 168 DEVO_REV, /* devo_rev */ 169 0, /* devo_refcnt */ 170 NULL, /* devo_getinfo */ 171 nulldev, /* devo_identify */ 172 nulldev, /* devo_probe */ 173 e1000gattach, /* devo_attach */ 174 e1000gdetach, /* devo_detach */ 175 nodev, /* devo_reset */ 176 &cb_ws_ops, /* devo_cb_ops */ 177 NULL, /* devo_bus_ops */ 178 ddi_power /* devo_power */ 179 }; 180 181 static struct modldrv modldrv = { 182 &mod_driverops, /* Type of module. This one is a driver */ 183 ident, /* Discription string */ 184 &ws_ops, /* driver ops */ 185 }; 186 187 static struct modlinkage modlinkage = { 188 MODREV_1, &modldrv, NULL 189 }; 190 191 /* 192 * DMA access attributes <Little Endian Card> 193 */ 194 static ddi_device_acc_attr_t accattr1 = { 195 DDI_DEVICE_ATTR_V0, 196 DDI_STRUCTURE_LE_ACC, 197 DDI_STRICTORDER_ACC, 198 }; 199 200 #define E1000G_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 201 202 static mac_callbacks_t e1000g_m_callbacks = { 203 E1000G_M_CALLBACK_FLAGS, 204 e1000g_m_stat, 205 e1000g_m_start, 206 e1000g_m_stop, 207 e1000g_m_promisc, 208 e1000g_m_multicst, 209 e1000g_m_unicst, 210 e1000g_m_tx, 211 e1000g_m_resources, 212 e1000g_m_ioctl, 213 e1000g_m_getcapab 214 }; 215 216 /* 217 * Global variables 218 */ 219 uint32_t e1000g_mblks_pending = 0; 220 /* 221 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 222 * Here we maintain a private dev_info list if e1000g_force_detach is 223 * enabled. If we force the driver to detach while there are still some 224 * rx buffers retained in the upper layer, we have to keep a copy of the 225 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 226 * structure will be freed after the driver is detached. However when we 227 * finally free those rx buffers released by the upper layer, we need to 228 * refer to the dev_info to free the dma buffers. So we save a copy of 229 * the dev_info for this purpose. On x86 platform, we assume this copy 230 * of dev_info is always valid, but on SPARC platform, it could be invalid 231 * after the system board level DR operation. For this reason, the global 232 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 233 */ 234 #ifdef __sparc 235 boolean_t e1000g_force_detach = B_FALSE; 236 #else 237 boolean_t e1000g_force_detach = B_TRUE; 238 #endif 239 private_devi_list_t *e1000g_private_devi_list = NULL; 240 241 /* 242 * The rwlock is defined to protect the whole processing of rx recycling 243 * and the rx packets release in detach processing to make them mutually 244 * exclusive. 245 * The rx recycling processes different rx packets in different threads, 246 * so it will be protected with RW_READER and it won't block any other rx 247 * recycling threads. 248 * While the detach processing will be protected with RW_WRITER to make 249 * it mutually exclusive with the rx recycling. 250 */ 251 krwlock_t e1000g_rx_detach_lock; 252 /* 253 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 254 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 255 * If there are many e1000g instances, the system may run out of DVMA 256 * resources during the initialization of the instances, then the flag will 257 * be changed to "USE_DMA". Because different e1000g instances are initialized 258 * in parallel, we need to use this lock to protect the flag. 259 */ 260 krwlock_t e1000g_dma_type_lock; 261 262 263 /* 264 * Loadable module configuration entry points for the driver 265 */ 266 267 /* 268 * ********************************************************************** 269 * Name: _init * 270 * * 271 * Description: * 272 * Initializes a loadable module. It is called before * 273 * any other routine in a loadable module. * 274 * All global locks are intialised here and it returns the retun * 275 * value from mod_install() * 276 * This is mandotary function for the driver * 277 * Parameter Passed: * 278 * None * 279 * Return Value: * 280 * 0 on success * 281 * Functions called * 282 * mod_install() (system call) * 283 * * 284 * ********************************************************************** 285 */ 286 int 287 _init(void) 288 { 289 int status; 290 291 mac_init_ops(&ws_ops, WSNAME); 292 status = mod_install(&modlinkage); 293 if (status != DDI_SUCCESS) 294 mac_fini_ops(&ws_ops); 295 else { 296 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 297 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 298 } 299 300 return (status); 301 } 302 303 /* 304 * ********************************************************************** 305 * Name: _fini * 306 * * 307 * Description: * 308 * Prepares a loadable module for unloading. It is * 309 * called when the system wants to unload a module. * 310 * This is mandotary function for the driver * 311 * Parameter Passed: * 312 * None * 313 * Return Value: * 314 * 0 on success * 315 * Functions called * 316 * mod_remove() (system call) * 317 * * 318 * * 319 * * 320 * ********************************************************************** 321 */ 322 int 323 _fini(void) 324 { 325 int status; 326 327 rw_enter(&e1000g_rx_detach_lock, RW_READER); 328 if (e1000g_mblks_pending != 0) { 329 rw_exit(&e1000g_rx_detach_lock); 330 return (EBUSY); 331 } 332 rw_exit(&e1000g_rx_detach_lock); 333 334 status = mod_remove(&modlinkage); 335 if (status == DDI_SUCCESS) { 336 mac_fini_ops(&ws_ops); 337 338 if (e1000g_force_detach) { 339 private_devi_list_t *devi_node; 340 341 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 342 while (e1000g_private_devi_list != NULL) { 343 devi_node = e1000g_private_devi_list; 344 e1000g_private_devi_list = 345 e1000g_private_devi_list->next; 346 347 kmem_free(devi_node->priv_dip, 348 sizeof (struct dev_info)); 349 kmem_free(devi_node, 350 sizeof (private_devi_list_t)); 351 } 352 rw_exit(&e1000g_rx_detach_lock); 353 } 354 355 rw_destroy(&e1000g_rx_detach_lock); 356 rw_destroy(&e1000g_dma_type_lock); 357 } 358 359 return (status); 360 } 361 362 /* 363 * ********************************************************************** 364 * Name: _info * 365 * * 366 * Description: * 367 * Returns information about a loadable module. * 368 * This is mandotary function for the driver * 369 * Parameter Passed: * 370 * module info structure * 371 * Return Value: * 372 * 0 on success * 373 * Functions called * 374 * mod_info() (system call) * 375 * * 376 * * 377 * ********************************************************************** 378 */ 379 int 380 _info(struct modinfo *modinfop) 381 { 382 return (mod_info(&modlinkage, modinfop)); 383 } 384 385 /* 386 * Interface exists: make available by filling in network interface 387 * record. System will initialize the interface when it is ready 388 * to accept packets. 389 */ 390 391 /* 392 * ********************************************************************** 393 * Name: e1000gattach * 394 * * 395 * Description: * 396 * This function is the device-specific initialization * 397 * entry point. This entry point is required and must be writ- * 398 * ten. The DDI_ATTACH command must be provided in the attach * 399 * entry point. When attach() is called with cmd set to DDI_ATTACH, * 400 * all normal kernel services (such as kmem_alloc(9F)) are * 401 * available for use by the driver. Device interrupts are not * 402 * blocked when attaching a device to the system. * 403 * * 404 * The attach() function will be called once for each instance * 405 * of the device on the system with cmd set to DDI_ATTACH. * 406 * Until attach() succeeds, the only driver entry points which * 407 * may be called are open(9E) and getinfo(9E). * 408 * * 409 * * 410 * * 411 * Parameter Passed: * 412 * * 413 * Return Value: * 414 * * 415 * Functions called * 416 * * 417 * * 418 * ********************************************************************** 419 */ 420 static int 421 e1000gattach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 422 { 423 struct e1000g *Adapter; 424 struct e1000_hw *hw; 425 ddi_acc_handle_t handle; 426 off_t mem_size; 427 int instance; 428 429 switch (cmd) { 430 default: 431 e1000g_log(NULL, CE_WARN, 432 "Unsupported command send to e1000gattach... "); 433 return (DDI_FAILURE); 434 435 case DDI_RESUME: 436 return (e1000g_resume(devinfo)); 437 438 case DDI_ATTACH: 439 break; 440 } 441 442 /* 443 * get device instance number 444 */ 445 instance = ddi_get_instance(devinfo); 446 447 /* 448 * Allocate soft data structure 449 */ 450 Adapter = 451 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 452 453 Adapter->dip = devinfo; 454 Adapter->AdapterInstance = instance; 455 Adapter->tx_ring->adapter = Adapter; 456 Adapter->rx_ring->adapter = Adapter; 457 458 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 459 460 if (e1000g_force_detach) { 461 private_devi_list_t *devi_node; 462 463 Adapter->priv_dip = 464 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 465 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 466 sizeof (struct dev_info)); 467 468 devi_node = 469 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 470 471 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 472 devi_node->dip = devinfo; 473 devi_node->priv_dip = Adapter->priv_dip; 474 devi_node->next = e1000g_private_devi_list; 475 e1000g_private_devi_list = devi_node; 476 rw_exit(&e1000g_rx_detach_lock); 477 } 478 479 hw = &Adapter->Shared; 480 481 /* 482 * Map in the device registers. 483 * 484 * first get the size of device register to be mapped. The 485 * second parameter is the register we are interested. I our 486 * wiseman 0 is for config registers and 1 is for memory mapped 487 * registers Mem size should have memory mapped region size 488 */ 489 ddi_dev_regsize(devinfo, 1, /* register of interest */ 490 (off_t *)&mem_size); 491 492 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 493 (caddr_t *)&hw->hw_addr, 494 0, mem_size, &accattr1, &Adapter->E1000_handle)) 495 != DDI_SUCCESS) { 496 e1000g_log(Adapter, CE_WARN, "ddi_regs_map_setup failed"); 497 goto attach_fail; 498 } 499 Adapter->attach_progress |= ATTACH_PROGRESS_REGSMAPPED; 500 501 Adapter->osdep.E1000_handle = Adapter->E1000_handle; 502 hw->back = &Adapter->osdep; 503 504 /* 505 * PCI Configure 506 */ 507 if (pci_config_setup(devinfo, &handle) != DDI_SUCCESS) { 508 e1000g_log(Adapter, CE_WARN, 509 "PCI configuration could not be read."); 510 goto attach_fail; 511 } 512 513 Adapter->handle = handle; 514 Adapter->osdep.handle = handle; 515 516 hw->vendor_id = 517 pci_config_get16(handle, PCI_CONF_VENID); 518 hw->device_id = 519 pci_config_get16(handle, PCI_CONF_DEVID); 520 hw->revision_id = 521 pci_config_get8(handle, PCI_CONF_REVID); 522 hw->subsystem_id = 523 pci_config_get16(handle, PCI_CONF_SUBSYSID); 524 hw->subsystem_vendor_id = 525 pci_config_get16(handle, PCI_CONF_SUBVENID); 526 527 Adapter->attach_progress |= ATTACH_PROGRESS_PCICONFIG; 528 529 /* 530 * Initialize driver parameters 531 */ 532 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 533 goto attach_fail; 534 } 535 Adapter->attach_progress |= ATTACH_PROGRESS_PROP; 536 537 /* 538 * Initialize interrupts 539 */ 540 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 541 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 542 goto attach_fail; 543 } 544 Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; 545 Adapter->attach_progress |= ATTACH_PROGRESS_INTRADDED; 546 547 /* 548 * Initialize mutex's for this device. 549 * Do this before enabling the interrupt handler and 550 * register the softint to avoid the condition where 551 * interrupt handler can try using uninitialized mutex 552 */ 553 e1000g_init_locks(Adapter); 554 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 555 556 if (ddi_intr_add_softint(devinfo, 557 &Adapter->tx_softint_handle, Adapter->tx_softint_pri, 558 e1000g_tx_freemsg, (caddr_t)Adapter) != DDI_SUCCESS) { 559 e1000g_log(Adapter, CE_WARN, "Add soft intr failed"); 560 goto attach_fail; 561 } 562 Adapter->attach_progress |= ATTACH_PROGRESS_SOFTINTR; 563 564 /* 565 * Initialize Driver Counters 566 */ 567 if (InitStatsCounters(Adapter) != DDI_SUCCESS) { 568 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 569 goto attach_fail; 570 } 571 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 572 573 /* 574 * Allocate dma resources for descriptors and buffers 575 */ 576 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 577 e1000g_log(Adapter, CE_WARN, "Alloc dma resources failed"); 578 goto attach_fail; 579 } 580 Adapter->attach_progress |= ATTACH_PROGRESS_ALLOC; 581 582 /* 583 * Initialize chip hardware and software structures 584 */ 585 if (e1000g_init(Adapter) != DDI_SUCCESS) { 586 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 587 goto attach_fail; 588 } 589 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 590 591 /* 592 * Initialize NDD parameters 593 */ 594 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 595 e1000g_log(Adapter, CE_WARN, "Init NDD failed"); 596 goto attach_fail; 597 } 598 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 599 600 /* 601 * Register the driver to the MAC 602 */ 603 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 604 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 605 goto attach_fail; 606 } 607 Adapter->attach_progress |= ATTACH_PROGRESS_MACREGISTERED; 608 609 /* 610 * Now that mutex locks are initialized, and the chip is also 611 * initialized, enable interrupts. 612 */ 613 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 614 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 615 goto attach_fail; 616 } 617 Adapter->attach_progress |= ATTACH_PROGRESS_INTRENABLED; 618 619 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 620 621 return (DDI_SUCCESS); 622 623 attach_fail: 624 e1000g_unattach(devinfo, Adapter); 625 return (DDI_FAILURE); 626 } 627 628 static int 629 e1000g_register_mac(struct e1000g *Adapter) 630 { 631 struct e1000_hw *hw = &Adapter->Shared; 632 mac_register_t *mac; 633 int err; 634 635 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 636 return (DDI_FAILURE); 637 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 638 mac->m_driver = Adapter; 639 mac->m_dip = Adapter->dip; 640 mac->m_src_addr = hw->mac_addr; 641 mac->m_callbacks = &e1000g_m_callbacks; 642 mac->m_min_sdu = 0; 643 mac->m_max_sdu = 644 (hw->max_frame_size > FRAME_SIZE_UPTO_8K) ? 645 hw->max_frame_size - 256 : 646 (hw->max_frame_size != ETHERMAX) ? 647 hw->max_frame_size - 24 : ETHERMTU; 648 err = mac_register(mac, &Adapter->mh); 649 mac_free(mac); 650 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 651 } 652 653 static int 654 e1000g_set_driver_params(struct e1000g *Adapter) 655 { 656 dev_info_t *devinfo; 657 ddi_acc_handle_t handle; 658 struct e1000_hw *hw; 659 uint32_t mem_bar, io_bar; 660 #ifdef __sparc 661 ulong_t iommu_pagesize; 662 #endif 663 664 devinfo = Adapter->dip; 665 handle = Adapter->handle; 666 hw = &Adapter->Shared; 667 668 /* Set Mac Type */ 669 if (e1000_set_mac_type(hw) != 0) { 670 e1000g_log(Adapter, CE_WARN, 671 "Could not identify hardware"); 672 return (DDI_FAILURE); 673 } 674 675 /* ich8 needs to map flash memory */ 676 if (hw->mac_type == e1000_ich8lan) { 677 /* get flash size */ 678 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 679 &Adapter->osdep.ich_flash_size) != DDI_SUCCESS) { 680 e1000g_log(Adapter, CE_WARN, 681 "ddi_dev_regsize for ich8 flash failed"); 682 return (DDI_FAILURE); 683 } 684 685 /* map flash in */ 686 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 687 &Adapter->osdep.ich_flash_base, 0, 688 Adapter->osdep.ich_flash_size, 689 &accattr1, 690 &Adapter->osdep.ich_flash_handle) != DDI_SUCCESS) { 691 e1000g_log(Adapter, CE_WARN, 692 "ddi_regs_map_setup for for ich8 flash failed"); 693 return (DDI_FAILURE); 694 } 695 } 696 697 /* get mem_base addr */ 698 mem_bar = pci_config_get32(handle, PCI_CONF_BASE0); 699 Adapter->bar64 = mem_bar & PCI_BASE_TYPE_ALL; 700 701 /* get io_base addr */ 702 if (hw->mac_type >= e1000_82544) { 703 if (Adapter->bar64) { 704 /* IO BAR is different for 64 bit BAR mode */ 705 io_bar = pci_config_get32(handle, PCI_CONF_BASE4); 706 } else { 707 /* normal 32-bit BAR mode */ 708 io_bar = pci_config_get32(handle, PCI_CONF_BASE2); 709 } 710 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 711 } else { 712 /* no I/O access for adapters prior to 82544 */ 713 hw->io_base = 0x0; 714 } 715 716 e1000_read_pci_cfg(hw, 717 PCI_COMMAND_REGISTER, &(hw->pci_cmd_word)); 718 719 /* Set the wait_autoneg_complete flag to B_FALSE */ 720 hw->wait_autoneg_complete = B_FALSE; 721 722 /* Adaptive IFS related changes */ 723 hw->adaptive_ifs = B_TRUE; 724 725 /* set phy init script revision */ 726 if ((hw->mac_type == e1000_82547) || 727 (hw->mac_type == e1000_82541) || 728 (hw->mac_type == e1000_82547_rev_2) || 729 (hw->mac_type == e1000_82541_rev_2)) 730 hw->phy_init_script = 1; 731 732 /* Enable the TTL workaround for TnT: DCR 49 */ 733 hw->ttl_wa_activation = 1; 734 735 if (hw->mac_type == e1000_82571) 736 hw->laa_is_present = B_TRUE; 737 738 #ifdef __sparc 739 Adapter->strip_crc = B_TRUE; 740 #else 741 Adapter->strip_crc = B_FALSE; 742 #endif 743 744 /* Get conf file properties */ 745 e1000g_getparam(Adapter); 746 747 hw->forced_speed_duplex = e1000_100_full; 748 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 749 e1000g_force_speed_duplex(Adapter); 750 751 e1000g_get_max_frame_size(Adapter); 752 hw->min_frame_size = 753 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 754 755 #ifdef __sparc 756 /* Get the system page size */ 757 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 758 iommu_pagesize = dvma_pagesize(devinfo); 759 if (iommu_pagesize != 0) { 760 if (Adapter->sys_page_sz == iommu_pagesize) { 761 if (iommu_pagesize > 0x4000) 762 Adapter->sys_page_sz = 0x4000; 763 } else { 764 if (Adapter->sys_page_sz > iommu_pagesize) 765 Adapter->sys_page_sz = iommu_pagesize; 766 } 767 } 768 Adapter->dvma_page_num = hw->max_frame_size / 769 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 770 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 771 #endif 772 773 /* Set Rx/Tx buffer size */ 774 switch (hw->max_frame_size) { 775 case ETHERMAX: 776 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 777 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 778 break; 779 case FRAME_SIZE_UPTO_4K: 780 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_4K; 781 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_4K; 782 break; 783 case FRAME_SIZE_UPTO_8K: 784 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_8K; 785 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_8K; 786 break; 787 case FRAME_SIZE_UPTO_10K: 788 case FRAME_SIZE_UPTO_16K: 789 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_16K; 790 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_16K; 791 break; 792 default: 793 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 794 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 795 break; 796 } 797 Adapter->RxBufferSize += E1000G_IPALIGNPRESERVEROOM; 798 799 /* 800 * For Wiseman adapters we have an requirement of having receive 801 * buffers aligned at 256 byte boundary. Since Livengood does not 802 * require this and forcing it for all hardwares will have 803 * performance implications, I am making it applicable only for 804 * Wiseman and for Jumbo frames enabled mode as rest of the time, 805 * it is okay to have normal frames...but it does involve a 806 * potential risk where we may loose data if buffer is not 807 * aligned...so all wiseman boards to have 256 byte aligned 808 * buffers 809 */ 810 if (hw->mac_type < e1000_82543) 811 Adapter->RcvBufferAlignment = RECEIVE_BUFFER_ALIGN_SIZE; 812 else 813 /* 814 * For livengood, there is no such Rcv buf alignment 815 * requirement 816 */ 817 Adapter->RcvBufferAlignment = 1; 818 819 /* DmaFairness */ 820 if (hw->mac_type <= e1000_82543) 821 hw->dma_fairness = DEFAULTRXPCIPRIORITYVAL; 822 else 823 hw->dma_fairness = 0; 824 825 /* MasterLatencyTimer */ 826 Adapter->MasterLatencyTimer = DEFAULTMASTERLATENCYTIMERVAL; 827 828 /* MWIEnable */ 829 Adapter->MWIEnable = DEFAULTMWIENABLEVAL; 830 831 /* profile jumbo traffic */ 832 Adapter->ProfileJumboTraffic = DEFAULTPROFILEJUMBOTRAFFIC; 833 834 e1000_set_media_type(hw); 835 /* copper options */ 836 if (hw->media_type == e1000_media_type_copper) { 837 hw->mdix = 0; /* AUTO_ALL_MODES */ 838 hw->disable_polarity_correction = B_FALSE; 839 hw->master_slave = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 840 } 841 842 Adapter->link_state = LINK_STATE_UNKNOWN; 843 844 return (DDI_SUCCESS); 845 } 846 847 /* 848 * ********************************************************************** 849 * Name: e1000gdettach * 850 * * 851 * Description: * 852 * The detach() function is the complement of the attach routine. * 853 * If cmd is set to DDI_DETACH, detach() is used to remove the * 854 * state associated with a given instance of a device node * 855 * prior to the removal of that instance from the system. * 856 * * 857 * The detach() function will be called once for each instance * 858 * of the device for which there has been a successful attach() * 859 * once there are no longer any opens on the device. * 860 * * 861 * Interrupts routine are disabled, All memory allocated by this * 862 * driver are freed. * 863 * * 864 * Parameter Passed: * 865 * devinfo structure, cmd * 866 * * 867 * Return Value: * 868 * DDI_SUCCESS on success * 869 * * 870 * Functions called * 871 * * 872 * * 873 * ********************************************************************** 874 */ 875 static int 876 e1000gdetach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 877 { 878 struct e1000g *Adapter; 879 880 switch (cmd) { 881 default: 882 return (DDI_FAILURE); 883 884 case DDI_SUSPEND: 885 return (e1000g_suspend(devinfo)); 886 887 case DDI_DETACH: 888 break; 889 } 890 891 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 892 if (Adapter == NULL) 893 return (DDI_FAILURE); 894 895 if (Adapter->started) 896 e1000g_stop(Adapter); 897 898 if (!e1000g_rx_drain(Adapter)) { 899 if (!e1000g_force_detach) 900 return (DDI_FAILURE); 901 } 902 903 if (e1000g_disable_intrs(Adapter) != DDI_SUCCESS) { 904 e1000g_log(Adapter, CE_WARN, 905 "Disable DDI interrupts failed"); 906 return (DDI_FAILURE); 907 } 908 Adapter->attach_progress &= ~ATTACH_PROGRESS_INTRENABLED; 909 910 if (mac_unregister(Adapter->mh) != 0) { 911 e1000g_log(Adapter, CE_WARN, 912 "Unregister MAC failed"); 913 return (DDI_FAILURE); 914 } 915 Adapter->attach_progress &= ~ATTACH_PROGRESS_MACREGISTERED; 916 917 e1000g_unattach(devinfo, Adapter); 918 919 return (DDI_SUCCESS); 920 } 921 922 static void 923 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 924 { 925 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRENABLED) { 926 (void) e1000g_disable_intrs(Adapter); 927 } 928 929 if (Adapter->attach_progress & ATTACH_PROGRESS_MACREGISTERED) { 930 (void) mac_unregister(Adapter->mh); 931 } 932 933 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 934 e1000g_nd_cleanup(Adapter); 935 } 936 937 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRADDED) { 938 (void) e1000g_rem_intrs(Adapter); 939 } 940 941 if (Adapter->attach_progress & ATTACH_PROGRESS_SOFTINTR) { 942 (void) ddi_intr_remove_softint(Adapter->tx_softint_handle); 943 } 944 945 if (Adapter->attach_progress & ATTACH_PROGRESS_PROP) { 946 (void) ddi_prop_remove_all(devinfo); 947 } 948 949 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 950 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 951 } 952 953 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 954 timeout_id_t tid = 0; 955 956 /* Disable the link timer */ 957 mutex_enter(&Adapter->e1000g_linklock); 958 tid = Adapter->link_tid; 959 Adapter->link_tid = 0; 960 mutex_exit(&Adapter->e1000g_linklock); 961 962 if (tid != 0) 963 (void) untimeout(tid); 964 965 e1000_reset_hw(&Adapter->Shared); 966 } 967 968 if (Adapter->attach_progress & ATTACH_PROGRESS_REGSMAPPED) { 969 ddi_regs_map_free(&Adapter->E1000_handle); 970 } 971 972 if (Adapter->attach_progress & ATTACH_PROGRESS_PCICONFIG) { 973 pci_config_teardown(&Adapter->handle); 974 } 975 976 if (Adapter->attach_progress & ATTACH_PROGRESS_ALLOC) { 977 e1000g_release_dma_resources(Adapter); 978 } 979 980 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 981 e1000g_destroy_locks(Adapter); 982 } 983 984 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 985 986 /* 987 * Another hotplug spec requirement, 988 * run ddi_set_driver_private(devinfo, null); 989 */ 990 ddi_set_driver_private(devinfo, NULL); 991 } 992 993 static void 994 e1000g_init_locks(struct e1000g *Adapter) 995 { 996 e1000g_tx_ring_t *tx_ring; 997 e1000g_rx_ring_t *rx_ring; 998 999 rw_init(&Adapter->chip_lock, NULL, 1000 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1001 mutex_init(&Adapter->e1000g_linklock, NULL, 1002 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1003 mutex_init(&Adapter->e1000g_timeout_lock, NULL, 1004 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1005 mutex_init(&Adapter->TbiCntrMutex, NULL, 1006 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1007 1008 mutex_init(&Adapter->tx_msg_chain->lock, NULL, 1009 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->tx_softint_pri)); 1010 1011 tx_ring = Adapter->tx_ring; 1012 1013 mutex_init(&tx_ring->tx_lock, NULL, 1014 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1015 mutex_init(&tx_ring->usedlist_lock, NULL, 1016 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1017 mutex_init(&tx_ring->freelist_lock, NULL, 1018 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1019 1020 rx_ring = Adapter->rx_ring; 1021 1022 mutex_init(&rx_ring->rx_lock, NULL, 1023 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1024 mutex_init(&rx_ring->freelist_lock, NULL, 1025 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1026 } 1027 1028 static void 1029 e1000g_destroy_locks(struct e1000g *Adapter) 1030 { 1031 e1000g_tx_ring_t *tx_ring; 1032 e1000g_rx_ring_t *rx_ring; 1033 1034 tx_ring = Adapter->tx_ring; 1035 mutex_destroy(&tx_ring->tx_lock); 1036 mutex_destroy(&tx_ring->usedlist_lock); 1037 mutex_destroy(&tx_ring->freelist_lock); 1038 1039 rx_ring = Adapter->rx_ring; 1040 mutex_destroy(&rx_ring->rx_lock); 1041 mutex_destroy(&rx_ring->freelist_lock); 1042 1043 mutex_destroy(&Adapter->tx_msg_chain->lock); 1044 mutex_destroy(&Adapter->e1000g_linklock); 1045 mutex_destroy(&Adapter->TbiCntrMutex); 1046 mutex_destroy(&Adapter->e1000g_timeout_lock); 1047 rw_destroy(&Adapter->chip_lock); 1048 } 1049 1050 static int 1051 e1000g_resume(dev_info_t *devinfo) 1052 { 1053 struct e1000g *Adapter; 1054 1055 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1056 if (Adapter == NULL) 1057 return (DDI_FAILURE); 1058 1059 if (e1000g_start(Adapter)) 1060 return (DDI_FAILURE); 1061 1062 return (DDI_SUCCESS); 1063 } 1064 1065 static int 1066 e1000g_suspend(dev_info_t *devinfo) 1067 { 1068 struct e1000g *Adapter; 1069 1070 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1071 if (Adapter == NULL) 1072 return (DDI_FAILURE); 1073 1074 e1000g_stop(Adapter); 1075 1076 return (DDI_SUCCESS); 1077 } 1078 1079 static int 1080 e1000g_init(struct e1000g *Adapter) 1081 { 1082 uint32_t pba; 1083 uint32_t ctrl; 1084 struct e1000_hw *hw; 1085 clock_t link_timeout; 1086 1087 hw = &Adapter->Shared; 1088 1089 rw_enter(&Adapter->chip_lock, RW_WRITER); 1090 1091 /* Preserve manageability features */ 1092 e1000_check_phy_reset_block(hw); 1093 1094 /* 1095 * reset to put the hardware in a known state 1096 * before we try to do anything with the eeprom 1097 */ 1098 (void) e1000_reset_hw(hw); 1099 1100 (void) e1000_init_eeprom_params(hw); 1101 1102 if (e1000_validate_eeprom_checksum(hw) < 0) { 1103 /* 1104 * Some PCI-E parts fail the first check due to 1105 * the link being in sleep state. Call it again, 1106 * if it fails a second time its a real issue. 1107 */ 1108 if (e1000_validate_eeprom_checksum(hw) < 0) { 1109 e1000g_log(Adapter, CE_WARN, 1110 "Invalid EEPROM checksum. Please contact " 1111 "the vendor to update the EEPROM."); 1112 goto init_fail; 1113 } 1114 } 1115 1116 #ifdef __sparc 1117 /* 1118 * Firstly, we try to get the local ethernet address from OBP. If 1119 * fail, we get from EEPROM of NIC card. 1120 */ 1121 if (!e1000g_find_mac_address(Adapter)) { 1122 if (e1000_read_mac_addr(hw) < 0) { 1123 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1124 goto init_fail; 1125 } 1126 } 1127 #else 1128 /* Get the local ethernet address. */ 1129 if (e1000_read_mac_addr(hw) < 0) { 1130 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1131 goto init_fail; 1132 } 1133 #endif 1134 1135 /* check for valid mac address */ 1136 if (!is_valid_mac_addr(hw->mac_addr)) { 1137 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1138 goto init_fail; 1139 } 1140 1141 e1000_get_bus_info(hw); 1142 1143 /* Master Latency Timer implementation */ 1144 if (Adapter->MasterLatencyTimer) { 1145 pci_config_put8(Adapter->handle, PCI_CONF_LATENCY_TIMER, 1146 Adapter->MasterLatencyTimer); 1147 } 1148 1149 if (hw->mac_type < e1000_82547) { 1150 /* 1151 * Total FIFO is 64K 1152 */ 1153 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1154 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1155 else 1156 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1157 } else if (hw->mac_type >= e1000_82571 && 1158 hw->mac_type <= e1000_82572) { 1159 /* 1160 * Total FIFO is 48K 1161 */ 1162 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1163 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1164 else 1165 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1166 } else if (hw->mac_type == e1000_ich8lan) { 1167 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1168 } else { 1169 /* 1170 * Total FIFO is 40K 1171 */ 1172 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1173 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1174 else 1175 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1176 } 1177 E1000_WRITE_REG(hw, PBA, pba); 1178 1179 /* 1180 * These parameters set thresholds for the adapter's generation(Tx) 1181 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1182 * settings. Flow control is enabled or disabled in the configuration 1183 * file. 1184 * High-water mark is set down from the top of the rx fifo (not 1185 * sensitive to max_frame_size) and low-water is set just below 1186 * high-water mark. 1187 */ 1188 hw->fc_high_water = 1189 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1190 E1000_FC_HIGH_DIFF; 1191 hw->fc_low_water = 1192 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1193 E1000_FC_LOW_DIFF; 1194 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 1195 hw->fc_send_xon = B_TRUE; 1196 1197 /* 1198 * Reset the adapter hardware the second time. 1199 */ 1200 (void) e1000_reset_hw(hw); 1201 1202 /* disable wakeup control by default */ 1203 if (hw->mac_type >= e1000_82544) 1204 E1000_WRITE_REG(hw, WUC, 0); 1205 1206 /* MWI setup */ 1207 if (Adapter->MWIEnable) { 1208 hw->pci_cmd_word |= CMD_MEM_WRT_INVALIDATE; 1209 e1000_pci_set_mwi(hw); 1210 } else 1211 e1000_pci_clear_mwi(hw); 1212 1213 /* 1214 * Configure/Initialize hardware 1215 */ 1216 if (e1000_init_hw(hw) < 0) { 1217 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1218 goto init_fail; 1219 } 1220 1221 /* Disable Smart Power Down */ 1222 phy_spd_state(hw, B_FALSE); 1223 1224 /* 1225 * Initialize unicast addresses. 1226 */ 1227 e1000g_init_unicst(Adapter); 1228 1229 /* 1230 * Setup and initialize the transmit structures. 1231 */ 1232 SetupTransmitStructures(Adapter); 1233 DelayInMilliseconds(5); 1234 1235 /* 1236 * Setup and initialize the mctable structures. After this routine 1237 * completes Multicast table will be set 1238 */ 1239 SetupMulticastTable(Adapter); 1240 DelayInMilliseconds(5); 1241 1242 /* 1243 * Setup and initialize the receive structures. After this routine 1244 * completes we can receive packets off of the wire. 1245 */ 1246 SetupReceiveStructures(Adapter); 1247 DelayInMilliseconds(5); 1248 1249 /* 1250 * Implement Adaptive IFS 1251 */ 1252 e1000_reset_adaptive(hw); 1253 1254 /* Setup Interrupt Throttling Register */ 1255 E1000_WRITE_REG(hw, ITR, Adapter->intr_throttling_rate); 1256 1257 /* Start the timer for link setup */ 1258 if (hw->autoneg) 1259 link_timeout = PHY_AUTO_NEG_TIME * drv_usectohz(100000); 1260 else 1261 link_timeout = PHY_FORCE_TIME * drv_usectohz(100000); 1262 1263 mutex_enter(&Adapter->e1000g_linklock); 1264 if (hw->wait_autoneg_complete) { 1265 Adapter->link_complete = B_TRUE; 1266 } else { 1267 Adapter->link_complete = B_FALSE; 1268 Adapter->link_tid = timeout(e1000g_link_timer, 1269 (void *)Adapter, link_timeout); 1270 } 1271 mutex_exit(&Adapter->e1000g_linklock); 1272 1273 /* Enable PCI-Ex master */ 1274 if (hw->bus_type == e1000_bus_type_pci_express) { 1275 e1000_enable_pciex_master(hw); 1276 } 1277 1278 Adapter->init_count++; 1279 1280 rw_exit(&Adapter->chip_lock); 1281 1282 return (DDI_SUCCESS); 1283 1284 init_fail: 1285 rw_exit(&Adapter->chip_lock); 1286 return (DDI_FAILURE); 1287 } 1288 1289 /* 1290 * Check if the link is up 1291 */ 1292 static boolean_t 1293 e1000g_link_up(struct e1000g *Adapter) 1294 { 1295 struct e1000_hw *hw; 1296 boolean_t link_up; 1297 1298 hw = &Adapter->Shared; 1299 1300 /* Ensure this is set to get accurate copper link status */ 1301 hw->get_link_status = B_TRUE; 1302 1303 e1000_check_for_link(hw); 1304 1305 if ((E1000_READ_REG(hw, STATUS) & E1000_STATUS_LU) || 1306 ((!hw->get_link_status) && (hw->mac_type == e1000_82543)) || 1307 ((hw->media_type == e1000_media_type_internal_serdes) && 1308 (!hw->serdes_link_down))) { 1309 link_up = B_TRUE; 1310 } else { 1311 link_up = B_FALSE; 1312 } 1313 1314 return (link_up); 1315 } 1316 1317 static void 1318 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1319 { 1320 struct iocblk *iocp; 1321 struct e1000g *e1000gp; 1322 enum ioc_reply status; 1323 int err; 1324 1325 iocp = (struct iocblk *)mp->b_rptr; 1326 iocp->ioc_error = 0; 1327 e1000gp = (struct e1000g *)arg; 1328 1329 ASSERT(e1000gp); 1330 if (e1000gp == NULL) { 1331 miocnak(q, mp, 0, EINVAL); 1332 return; 1333 } 1334 1335 switch (iocp->ioc_cmd) { 1336 1337 case LB_GET_INFO_SIZE: 1338 case LB_GET_INFO: 1339 case LB_GET_MODE: 1340 case LB_SET_MODE: 1341 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1342 break; 1343 1344 case ND_GET: 1345 case ND_SET: 1346 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1347 break; 1348 1349 case E1000G_IOC_REG_PEEK: 1350 case E1000G_IOC_REG_POKE: 1351 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1352 break; 1353 case E1000G_IOC_CHIP_RESET: 1354 e1000gp->reset_count++; 1355 if (e1000g_reset(e1000gp)) 1356 status = IOC_ACK; 1357 else 1358 status = IOC_INVAL; 1359 break; 1360 default: 1361 status = IOC_INVAL; 1362 break; 1363 } 1364 1365 /* 1366 * Decide how to reply 1367 */ 1368 switch (status) { 1369 default: 1370 case IOC_INVAL: 1371 /* 1372 * Error, reply with a NAK and EINVAL or the specified error 1373 */ 1374 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1375 EINVAL : iocp->ioc_error); 1376 break; 1377 1378 case IOC_DONE: 1379 /* 1380 * OK, reply already sent 1381 */ 1382 break; 1383 1384 case IOC_ACK: 1385 /* 1386 * OK, reply with an ACK 1387 */ 1388 miocack(q, mp, 0, 0); 1389 break; 1390 1391 case IOC_REPLY: 1392 /* 1393 * OK, send prepared reply as ACK or NAK 1394 */ 1395 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1396 M_IOCACK : M_IOCNAK; 1397 qreply(q, mp); 1398 break; 1399 } 1400 } 1401 1402 static void e1000g_m_blank(void *arg, time_t ticks, uint32_t count) 1403 { 1404 struct e1000g *Adapter; 1405 1406 Adapter = (struct e1000g *)arg; 1407 1408 /* 1409 * Adjust ITR (Interrupt Throttling Register) to coalesce 1410 * interrupts. This formula and its coefficient come from 1411 * our experiments. 1412 */ 1413 if (Adapter->intr_adaptive) { 1414 Adapter->intr_throttling_rate = count << 5; 1415 E1000_WRITE_REG(&Adapter->Shared, ITR, 1416 Adapter->intr_throttling_rate); 1417 } 1418 } 1419 1420 static void 1421 e1000g_m_resources(void *arg) 1422 { 1423 struct e1000g *adapter = (struct e1000g *)arg; 1424 mac_rx_fifo_t mrf; 1425 1426 mrf.mrf_type = MAC_RX_FIFO; 1427 mrf.mrf_blank = e1000g_m_blank; 1428 mrf.mrf_arg = (void *)adapter; 1429 mrf.mrf_normal_blank_time = E1000_RX_INTPT_TIME; 1430 mrf.mrf_normal_pkt_count = E1000_RX_PKT_CNT; 1431 1432 adapter->mrh = mac_resource_add(adapter->mh, (mac_resource_t *)&mrf); 1433 } 1434 1435 static int 1436 e1000g_m_start(void *arg) 1437 { 1438 struct e1000g *Adapter = (struct e1000g *)arg; 1439 1440 return (e1000g_start(Adapter)); 1441 } 1442 1443 static int 1444 e1000g_start(struct e1000g *Adapter) 1445 { 1446 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1447 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1448 e1000g_log(Adapter, CE_WARN, 1449 "Adapter initialization failed"); 1450 return (ENOTACTIVE); 1451 } 1452 } 1453 1454 enable_timeout(Adapter); 1455 1456 rw_enter(&Adapter->chip_lock, RW_WRITER); 1457 1458 e1000g_EnableInterrupt(Adapter); 1459 if (Adapter->tx_intr_enable) 1460 e1000g_EnableTxInterrupt(Adapter); 1461 1462 Adapter->started = B_TRUE; 1463 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1464 1465 rw_exit(&Adapter->chip_lock); 1466 1467 return (0); 1468 } 1469 1470 static void 1471 e1000g_m_stop(void *arg) 1472 { 1473 struct e1000g *Adapter = (struct e1000g *)arg; 1474 1475 e1000g_stop(Adapter); 1476 } 1477 1478 static void 1479 e1000g_stop(struct e1000g *Adapter) 1480 { 1481 timeout_id_t tid; 1482 e1000g_tx_ring_t *tx_ring; 1483 boolean_t link_changed; 1484 1485 tx_ring = Adapter->tx_ring; 1486 1487 /* Set stop flags */ 1488 rw_enter(&Adapter->chip_lock, RW_WRITER); 1489 1490 Adapter->started = B_FALSE; 1491 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1492 1493 rw_exit(&Adapter->chip_lock); 1494 1495 /* Drain tx sessions */ 1496 (void) e1000g_tx_drain(Adapter); 1497 1498 /* Disable timers */ 1499 disable_timeout(Adapter); 1500 1501 /* Disable the tx timer for 82547 chipset */ 1502 mutex_enter(&tx_ring->tx_lock); 1503 tx_ring->timer_enable_82547 = B_FALSE; 1504 tid = tx_ring->timer_id_82547; 1505 tx_ring->timer_id_82547 = 0; 1506 mutex_exit(&tx_ring->tx_lock); 1507 1508 if (tid != 0) 1509 (void) untimeout(tid); 1510 1511 /* Disable the link timer */ 1512 mutex_enter(&Adapter->e1000g_linklock); 1513 tid = Adapter->link_tid; 1514 Adapter->link_tid = 0; 1515 mutex_exit(&Adapter->e1000g_linklock); 1516 1517 if (tid != 0) 1518 (void) untimeout(tid); 1519 1520 /* Stop the chip and release pending resources */ 1521 rw_enter(&Adapter->chip_lock, RW_WRITER); 1522 1523 e1000g_DisableAllInterrupts(Adapter); 1524 1525 e1000_reset_hw(&Adapter->Shared); 1526 1527 /* Release resources still held by the TX descriptors */ 1528 e1000g_tx_drop(Adapter); 1529 1530 /* Clean the pending rx jumbo packet fragment */ 1531 if (Adapter->rx_mblk != NULL) { 1532 freemsg(Adapter->rx_mblk); 1533 Adapter->rx_mblk = NULL; 1534 Adapter->rx_mblk_tail = NULL; 1535 Adapter->rx_packet_len = 0; 1536 } 1537 1538 rw_exit(&Adapter->chip_lock); 1539 } 1540 1541 static void 1542 e1000g_tx_drop(struct e1000g *Adapter) 1543 { 1544 e1000g_tx_ring_t *tx_ring; 1545 e1000g_msg_chain_t *msg_chain; 1546 PTX_SW_PACKET packet; 1547 mblk_t *mp; 1548 mblk_t *nmp; 1549 uint32_t packet_count; 1550 1551 tx_ring = Adapter->tx_ring; 1552 1553 /* 1554 * Here we don't need to protect the lists using 1555 * the usedlist_lock and freelist_lock, for they 1556 * have been protected by the chip_lock. 1557 */ 1558 mp = NULL; 1559 nmp = NULL; 1560 packet_count = 0; 1561 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list); 1562 while (packet != NULL) { 1563 if (packet->mp != NULL) { 1564 /* Assemble the message chain */ 1565 if (mp == NULL) { 1566 mp = packet->mp; 1567 nmp = packet->mp; 1568 } else { 1569 nmp->b_next = packet->mp; 1570 nmp = packet->mp; 1571 } 1572 /* Disconnect the message from the sw packet */ 1573 packet->mp = NULL; 1574 } 1575 1576 FreeTxSwPacket(packet); 1577 packet_count++; 1578 1579 packet = (PTX_SW_PACKET) 1580 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1581 } 1582 1583 if (mp != NULL) { 1584 msg_chain = Adapter->tx_msg_chain; 1585 mutex_enter(&msg_chain->lock); 1586 if (msg_chain->head == NULL) { 1587 msg_chain->head = mp; 1588 msg_chain->tail = nmp; 1589 } else { 1590 msg_chain->tail->b_next = mp; 1591 msg_chain->tail = nmp; 1592 } 1593 mutex_exit(&msg_chain->lock); 1594 } 1595 1596 ddi_intr_trigger_softint(Adapter->tx_softint_handle, NULL); 1597 1598 if (packet_count > 0) { 1599 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1600 QUEUE_INIT_LIST(&tx_ring->used_list); 1601 1602 /* Setup TX descriptor pointers */ 1603 tx_ring->tbd_next = tx_ring->tbd_first; 1604 tx_ring->tbd_oldest = tx_ring->tbd_first; 1605 1606 /* Setup our HW Tx Head & Tail descriptor pointers */ 1607 E1000_WRITE_REG(&Adapter->Shared, TDH, 0); 1608 E1000_WRITE_REG(&Adapter->Shared, TDT, 0); 1609 } 1610 } 1611 1612 static boolean_t 1613 e1000g_tx_drain(struct e1000g *Adapter) 1614 { 1615 int i; 1616 boolean_t done; 1617 e1000g_tx_ring_t *tx_ring; 1618 1619 tx_ring = Adapter->tx_ring; 1620 1621 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1622 for (i = 0; i < WSDRAINTIME; i++) { 1623 mutex_enter(&tx_ring->usedlist_lock); 1624 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1625 mutex_exit(&tx_ring->usedlist_lock); 1626 1627 if (done) 1628 break; 1629 1630 msec_delay(1); 1631 } 1632 1633 return (done); 1634 } 1635 1636 static boolean_t 1637 e1000g_rx_drain(struct e1000g *Adapter) 1638 { 1639 boolean_t done; 1640 1641 mutex_enter(&Adapter->rx_ring->freelist_lock); 1642 done = (Adapter->rx_avail_freepkt == Adapter->NumRxFreeList); 1643 mutex_exit(&Adapter->rx_ring->freelist_lock); 1644 1645 return (done); 1646 } 1647 1648 boolean_t 1649 e1000g_reset(struct e1000g *Adapter) 1650 { 1651 e1000g_stop(Adapter); 1652 1653 if (e1000g_start(Adapter)) { 1654 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1655 return (B_FALSE); 1656 } 1657 1658 return (B_TRUE); 1659 } 1660 1661 /* 1662 * ********************************************************************** 1663 * Name: e1000g_intr_pciexpress * 1664 * * 1665 * Description: * 1666 * This interrupt service routine is for PCI-Express adapters. * 1667 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED * 1668 * bit is set. * 1669 * * 1670 * Parameter Passed: * 1671 * * 1672 * Return Value: * 1673 * * 1674 * Functions called: * 1675 * e1000g_intr_work * 1676 * * 1677 * ********************************************************************** 1678 */ 1679 static uint_t 1680 e1000g_intr_pciexpress(caddr_t arg) 1681 { 1682 struct e1000g *Adapter; 1683 uint32_t ICRContents; 1684 1685 Adapter = (struct e1000g *)arg; 1686 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1687 1688 if (ICRContents & E1000_ICR_INT_ASSERTED) { 1689 /* 1690 * E1000_ICR_INT_ASSERTED bit was set: 1691 * Read(Clear) the ICR, claim this interrupt, 1692 * look for work to do. 1693 */ 1694 e1000g_intr_work(Adapter, ICRContents); 1695 return (DDI_INTR_CLAIMED); 1696 } else { 1697 /* 1698 * E1000_ICR_INT_ASSERTED bit was not set: 1699 * Don't claim this interrupt, return immediately. 1700 */ 1701 return (DDI_INTR_UNCLAIMED); 1702 } 1703 } 1704 1705 /* 1706 * ********************************************************************** 1707 * Name: e1000g_intr * 1708 * * 1709 * Description: * 1710 * This interrupt service routine is for PCI/PCI-X adapters. * 1711 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED * 1712 * bit is set or not. * 1713 * * 1714 * Parameter Passed: * 1715 * * 1716 * Return Value: * 1717 * * 1718 * Functions called: * 1719 * e1000g_intr_work * 1720 * * 1721 * ********************************************************************** 1722 */ 1723 static uint_t 1724 e1000g_intr(caddr_t arg) 1725 { 1726 struct e1000g *Adapter; 1727 uint32_t ICRContents; 1728 1729 Adapter = (struct e1000g *)arg; 1730 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1731 1732 if (ICRContents) { 1733 /* 1734 * Any bit was set in ICR: 1735 * Read(Clear) the ICR, claim this interrupt, 1736 * look for work to do. 1737 */ 1738 e1000g_intr_work(Adapter, ICRContents); 1739 return (DDI_INTR_CLAIMED); 1740 } else { 1741 /* 1742 * No bit was set in ICR: 1743 * Don't claim this interrupt, return immediately. 1744 */ 1745 return (DDI_INTR_UNCLAIMED); 1746 } 1747 } 1748 1749 /* 1750 * ********************************************************************** 1751 * Name: e1000g_intr_work * 1752 * * 1753 * Description: * 1754 * Called from interrupt service routines. * 1755 * Read(clear) the ICR contents and call appropriate interrupt * 1756 * processing routines. * 1757 * * 1758 * Parameter Passed: * 1759 * * 1760 * Return Value: * 1761 * * 1762 * Functions called: * 1763 * e1000g_receive * 1764 * e1000g_link_check * 1765 * e1000g_recycle * 1766 * * 1767 * ********************************************************************** 1768 */ 1769 static void 1770 e1000g_intr_work(struct e1000g *Adapter, uint32_t ICRContents) 1771 { 1772 if (ICRContents & E1000_ICR_RXT0) { 1773 mblk_t *mp; 1774 1775 rw_enter(&Adapter->chip_lock, RW_READER); 1776 /* 1777 * Here we need to check the "started" flag to ensure the 1778 * receive routine will not execute when the adapter is 1779 * stopped or being reset. 1780 */ 1781 if (Adapter->started) { 1782 mutex_enter(&Adapter->rx_ring->rx_lock); 1783 mp = e1000g_receive(Adapter); 1784 mutex_exit(&Adapter->rx_ring->rx_lock); 1785 1786 rw_exit(&Adapter->chip_lock); 1787 1788 if (mp != NULL) 1789 mac_rx(Adapter->mh, Adapter->mrh, mp); 1790 } else { 1791 rw_exit(&Adapter->chip_lock); 1792 } 1793 } 1794 1795 /* 1796 * The Receive Sequence errors RXSEQ and the link status change LSC 1797 * are checked to detect that the cable has been pulled out. For 1798 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1799 * are an indication that cable is not connected. 1800 */ 1801 if ((ICRContents & E1000_ICR_RXSEQ) || 1802 (ICRContents & E1000_ICR_LSC) || 1803 (ICRContents & E1000_ICR_GPI_EN1)) { 1804 boolean_t link_changed; 1805 timeout_id_t tid = 0; 1806 1807 /* 1808 * Encountered RX Sequence Error!!! Link maybe forced and 1809 * the cable may have just been disconnected so we will 1810 * read the LOS to see. 1811 */ 1812 if (ICRContents & E1000_ICR_RXSEQ) 1813 Adapter->rx_seq_intr++; 1814 1815 stop_timeout(Adapter); 1816 1817 mutex_enter(&Adapter->e1000g_linklock); 1818 /* e1000g_link_check takes care of link status change */ 1819 link_changed = e1000g_link_check(Adapter); 1820 /* 1821 * If the link timer has not timed out, we'll not notify 1822 * the upper layer with any link state until the link 1823 * is up. 1824 */ 1825 if (link_changed && !Adapter->link_complete) { 1826 if (Adapter->link_state == LINK_STATE_UP) { 1827 Adapter->link_complete = B_TRUE; 1828 tid = Adapter->link_tid; 1829 Adapter->link_tid = 0; 1830 } else { 1831 link_changed = B_FALSE; 1832 } 1833 } 1834 mutex_exit(&Adapter->e1000g_linklock); 1835 1836 if (link_changed) { 1837 if (tid != 0) 1838 (void) untimeout(tid); 1839 1840 /* 1841 * Workaround for esb2. Data stuck in fifo on a link 1842 * down event. Reset the adapter to recover it. 1843 */ 1844 if ((Adapter->link_state == LINK_STATE_DOWN) && 1845 (Adapter->Shared.mac_type == e1000_80003es2lan)) 1846 (void) e1000g_reset(Adapter); 1847 1848 mac_link_update(Adapter->mh, Adapter->link_state); 1849 } 1850 1851 start_timeout(Adapter); 1852 } 1853 1854 if (ICRContents & E1000G_ICR_TX_INTR) { 1855 if (!Adapter->tx_intr_enable) 1856 e1000g_DisableTxInterrupt(Adapter); 1857 /* Schedule the re-transmit */ 1858 if (Adapter->resched_needed) { 1859 Adapter->tx_reschedule++; 1860 Adapter->resched_needed = B_FALSE; 1861 mac_tx_update(Adapter->mh); 1862 } 1863 if (Adapter->tx_intr_enable) { 1864 /* Recycle the tx descriptors */ 1865 rw_enter(&Adapter->chip_lock, RW_READER); 1866 Adapter->tx_recycle_intr++; 1867 e1000g_recycle(Adapter->tx_ring); 1868 rw_exit(&Adapter->chip_lock); 1869 /* Free the recycled messages */ 1870 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 1871 NULL); 1872 } 1873 } 1874 } 1875 1876 static void 1877 e1000g_init_unicst(struct e1000g *Adapter) 1878 { 1879 struct e1000_hw *hw; 1880 int slot; 1881 1882 hw = &Adapter->Shared; 1883 1884 if (Adapter->init_count == 0) { 1885 /* Initialize the multiple unicast addresses */ 1886 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1887 1888 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1889 Adapter->unicst_total--; 1890 1891 Adapter->unicst_avail = Adapter->unicst_total - 1; 1892 1893 /* Store the default mac address */ 1894 e1000_rar_set(hw, hw->mac_addr, 0); 1895 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1896 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1897 1898 bcopy(hw->mac_addr, Adapter->unicst_addr[0].mac.addr, 1899 ETHERADDRL); 1900 Adapter->unicst_addr[0].mac.set = 1; 1901 1902 for (slot = 1; slot < Adapter->unicst_total; slot++) 1903 Adapter->unicst_addr[slot].mac.set = 0; 1904 } else { 1905 /* Recover the default mac address */ 1906 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac_addr, 1907 ETHERADDRL); 1908 1909 /* Store the default mac address */ 1910 e1000_rar_set(hw, hw->mac_addr, 0); 1911 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1912 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1913 1914 /* Re-configure the RAR registers */ 1915 for (slot = 1; slot < Adapter->unicst_total; slot++) 1916 e1000_rar_set(hw, 1917 Adapter->unicst_addr[slot].mac.addr, slot); 1918 } 1919 } 1920 1921 static int 1922 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 1923 { 1924 struct e1000g *Adapter; 1925 1926 Adapter = (struct e1000g *)arg; 1927 1928 /* Store the default MAC address */ 1929 bcopy(mac_addr, Adapter->Shared.mac_addr, ETHERADDRL); 1930 1931 /* Set MAC address in address slot 0, which is the default address */ 1932 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 1933 } 1934 1935 static int 1936 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 1937 mac_addr_slot_t slot) 1938 { 1939 struct e1000_hw *hw; 1940 1941 hw = &Adapter->Shared; 1942 1943 /* 1944 * Error if the address specified is a multicast or broadcast 1945 * address. 1946 */ 1947 if (((mac_addr[0] & 01) == 1) || 1948 (bcmp(mac_addr, ðerbroadcastaddr, ETHERADDRL) == 0)) 1949 return (EINVAL); 1950 1951 rw_enter(&Adapter->chip_lock, RW_WRITER); 1952 1953 /* 1954 * The first revision of Wiseman silicon (rev 2.0) has an errata 1955 * that requires the receiver to be in reset when any of the 1956 * receive address registers (RAR regs) are accessed. The first 1957 * rev of Wiseman silicon also requires MWI to be disabled when 1958 * a global reset or a receive reset is issued. So before we 1959 * initialize the RARs, we check the rev of the Wiseman controller 1960 * and work around any necessary HW errata. 1961 */ 1962 if (hw->mac_type == e1000_82542_rev2_0) { 1963 e1000_pci_clear_mwi(hw); 1964 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1965 DelayInMilliseconds(5); 1966 } 1967 1968 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 1969 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 1970 1971 if (slot == 0) { 1972 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1973 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1974 } 1975 1976 /* 1977 * If we are using Wiseman rev 2.0 silicon, we will have previously 1978 * put the receive in reset, and disabled MWI, to work around some 1979 * HW errata. Now we should take the receiver out of reset, and 1980 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 1981 */ 1982 if (hw->mac_type == e1000_82542_rev2_0) { 1983 E1000_WRITE_REG(hw, RCTL, 0); 1984 DelayInMilliseconds(1); 1985 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1986 e1000_pci_set_mwi(hw); 1987 SetupReceiveStructures(Adapter); 1988 } 1989 1990 rw_exit(&Adapter->chip_lock); 1991 1992 return (0); 1993 } 1994 1995 /* 1996 * e1000g_m_unicst_add() - will find an unused address slot, set the 1997 * address value to the one specified, reserve that slot and enable 1998 * the NIC to start filtering on the new MAC address. 1999 * Returns 0 on success. 2000 */ 2001 static int 2002 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2003 { 2004 struct e1000g *Adapter = (struct e1000g *)arg; 2005 mac_addr_slot_t slot; 2006 int err; 2007 2008 if (mac_unicst_verify(Adapter->mh, 2009 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2010 return (EINVAL); 2011 2012 rw_enter(&Adapter->chip_lock, RW_WRITER); 2013 if (Adapter->unicst_avail == 0) { 2014 /* no slots available */ 2015 rw_exit(&Adapter->chip_lock); 2016 return (ENOSPC); 2017 } 2018 2019 /* 2020 * Primary/default address is in slot 0. The next addresses 2021 * are the multiple MAC addresses. So multiple MAC address 0 2022 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2023 * MAC address resides in slot 1. 2024 */ 2025 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2026 if (Adapter->unicst_addr[slot].mac.set == 0) { 2027 Adapter->unicst_addr[slot].mac.set = 1; 2028 break; 2029 } 2030 } 2031 2032 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2033 2034 Adapter->unicst_avail--; 2035 rw_exit(&Adapter->chip_lock); 2036 2037 maddr->mma_slot = slot; 2038 2039 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2040 rw_enter(&Adapter->chip_lock, RW_WRITER); 2041 Adapter->unicst_addr[slot].mac.set = 0; 2042 Adapter->unicst_avail++; 2043 rw_exit(&Adapter->chip_lock); 2044 } 2045 2046 return (err); 2047 } 2048 2049 /* 2050 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2051 * call to e1000g_m_unicst_add(). The slot number that was returned in 2052 * e1000g_m_unicst_add() is passed in the call to remove the address. 2053 * Returns 0 on success. 2054 */ 2055 static int 2056 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2057 { 2058 struct e1000g *Adapter = (struct e1000g *)arg; 2059 int err; 2060 2061 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2062 return (EINVAL); 2063 2064 rw_enter(&Adapter->chip_lock, RW_WRITER); 2065 if (Adapter->unicst_addr[slot].mac.set == 1) { 2066 Adapter->unicst_addr[slot].mac.set = 0; 2067 Adapter->unicst_avail++; 2068 rw_exit(&Adapter->chip_lock); 2069 2070 /* Copy the default address to the passed slot */ 2071 if (err = e1000g_unicst_set(Adapter, 2072 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2073 rw_enter(&Adapter->chip_lock, RW_WRITER); 2074 Adapter->unicst_addr[slot].mac.set = 1; 2075 Adapter->unicst_avail--; 2076 rw_exit(&Adapter->chip_lock); 2077 } 2078 return (err); 2079 } 2080 rw_exit(&Adapter->chip_lock); 2081 2082 return (EINVAL); 2083 } 2084 2085 /* 2086 * e1000g_m_unicst_modify() - modifies the value of an address that 2087 * has been added by e1000g_m_unicst_add(). The new address, address 2088 * length and the slot number that was returned in the call to add 2089 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2090 * set to 0. Returns 0 on success. 2091 */ 2092 static int 2093 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2094 { 2095 struct e1000g *Adapter = (struct e1000g *)arg; 2096 mac_addr_slot_t slot; 2097 2098 if (mac_unicst_verify(Adapter->mh, 2099 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2100 return (EINVAL); 2101 2102 slot = maddr->mma_slot; 2103 2104 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2105 return (EINVAL); 2106 2107 rw_enter(&Adapter->chip_lock, RW_WRITER); 2108 if (Adapter->unicst_addr[slot].mac.set == 1) { 2109 rw_exit(&Adapter->chip_lock); 2110 2111 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2112 } 2113 rw_exit(&Adapter->chip_lock); 2114 2115 return (EINVAL); 2116 } 2117 2118 /* 2119 * e1000g_m_unicst_get() - will get the MAC address and all other 2120 * information related to the address slot passed in mac_multi_addr_t. 2121 * mma_flags should be set to 0 in the call. 2122 * On return, mma_flags can take the following values: 2123 * 1) MMAC_SLOT_UNUSED 2124 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2125 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2126 * 4) MMAC_SLOT_USED 2127 */ 2128 static int 2129 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2130 { 2131 struct e1000g *Adapter = (struct e1000g *)arg; 2132 mac_addr_slot_t slot; 2133 2134 slot = maddr->mma_slot; 2135 2136 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2137 return (EINVAL); 2138 2139 rw_enter(&Adapter->chip_lock, RW_WRITER); 2140 if (Adapter->unicst_addr[slot].mac.set == 1) { 2141 bcopy(Adapter->unicst_addr[slot].mac.addr, 2142 maddr->mma_addr, ETHERADDRL); 2143 maddr->mma_flags = MMAC_SLOT_USED; 2144 } else { 2145 maddr->mma_flags = MMAC_SLOT_UNUSED; 2146 } 2147 rw_exit(&Adapter->chip_lock); 2148 2149 return (0); 2150 } 2151 2152 static int 2153 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2154 { 2155 unsigned i; 2156 int res = 0; 2157 2158 rw_enter(&Adapter->chip_lock, RW_WRITER); 2159 2160 if ((multiaddr[0] & 01) == 0) { 2161 res = EINVAL; 2162 goto done; 2163 } 2164 2165 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2166 res = ENOENT; 2167 goto done; 2168 } 2169 2170 bcopy(multiaddr, 2171 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2172 Adapter->mcast_count++; 2173 2174 /* 2175 * Update the MC table in the hardware 2176 */ 2177 e1000g_DisableInterrupt(Adapter); 2178 2179 SetupMulticastTable(Adapter); 2180 2181 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2182 SetupReceiveStructures(Adapter); 2183 2184 e1000g_EnableInterrupt(Adapter); 2185 2186 done: 2187 rw_exit(&Adapter->chip_lock); 2188 return (res); 2189 } 2190 2191 static int 2192 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2193 { 2194 unsigned i; 2195 2196 rw_enter(&Adapter->chip_lock, RW_WRITER); 2197 2198 for (i = 0; i < Adapter->mcast_count; i++) { 2199 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2200 ETHERADDRL) == 0) { 2201 for (i++; i < Adapter->mcast_count; i++) { 2202 Adapter->mcast_table[i - 1] = 2203 Adapter->mcast_table[i]; 2204 } 2205 Adapter->mcast_count--; 2206 break; 2207 } 2208 } 2209 2210 /* 2211 * Update the MC table in the hardware 2212 */ 2213 e1000g_DisableInterrupt(Adapter); 2214 2215 SetupMulticastTable(Adapter); 2216 2217 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2218 SetupReceiveStructures(Adapter); 2219 2220 e1000g_EnableInterrupt(Adapter); 2221 2222 done: 2223 rw_exit(&Adapter->chip_lock); 2224 return (0); 2225 } 2226 2227 int 2228 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2229 { 2230 struct e1000g *Adapter = (struct e1000g *)arg; 2231 2232 return ((add) ? multicst_add(Adapter, addr) 2233 : multicst_remove(Adapter, addr)); 2234 } 2235 2236 int 2237 e1000g_m_promisc(void *arg, boolean_t on) 2238 { 2239 struct e1000g *Adapter = (struct e1000g *)arg; 2240 ULONG RctlRegValue; 2241 2242 rw_enter(&Adapter->chip_lock, RW_WRITER); 2243 2244 RctlRegValue = E1000_READ_REG(&Adapter->Shared, RCTL); 2245 2246 if (on) 2247 RctlRegValue |= 2248 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2249 else 2250 RctlRegValue &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2251 2252 E1000_WRITE_REG(&Adapter->Shared, RCTL, RctlRegValue); 2253 2254 Adapter->e1000g_promisc = on; 2255 2256 rw_exit(&Adapter->chip_lock); 2257 2258 return (0); 2259 } 2260 2261 static boolean_t 2262 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2263 { 2264 struct e1000g *Adapter = (struct e1000g *)arg; 2265 2266 switch (cap) { 2267 case MAC_CAPAB_HCKSUM: { 2268 uint32_t *txflags = cap_data; 2269 2270 /* 2271 * In Jumbo mode, enabling hardware checksum will cause 2272 * port hang. 2273 */ 2274 if (Adapter->Shared.max_frame_size > ETHERMAX) 2275 return (B_FALSE); 2276 2277 /* 2278 * Checksum on/off selection via global parameters. 2279 * 2280 * If the chip is flagged as not capable of (correctly) 2281 * handling FULL checksumming, we don't enable it on either 2282 * Rx or Tx side. Otherwise, we take this chip's settings 2283 * from the patchable global defaults. 2284 * 2285 * We advertise our capabilities only if TX offload is 2286 * enabled. On receive, the stack will accept checksummed 2287 * packets anyway, even if we haven't said we can deliver 2288 * them. 2289 */ 2290 switch (Adapter->Shared.mac_type) { 2291 /* 2292 * Switch on hardware checksum offload of 2293 * chip 82540, 82545, 82546 2294 */ 2295 case e1000_82540: 2296 case e1000_82544: /* pci8086,1008 */ 2297 case e1000_82545: 2298 case e1000_82545_rev_3: /* pci8086,1026 */ 2299 case e1000_82571: 2300 case e1000_82572: 2301 case e1000_82573: 2302 case e1000_80003es2lan: 2303 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2304 break; 2305 2306 case e1000_82546: /* 82546EB. devID: 1010, 101d */ 2307 case e1000_82546_rev_3: /* 82546GB. devID: 1079, 107a */ 2308 #if !defined(__sparc) && !defined(__amd64) 2309 /* Workaround for Galaxy on 32bit */ 2310 return (B_FALSE); 2311 #else 2312 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2313 break; 2314 #endif 2315 2316 /* 2317 * We don't have the following PRO 1000 chip types at 2318 * hand and haven't tested their hardware checksum 2319 * offload capability. We had better switch them off. 2320 * e1000_undefined = 0, 2321 * e1000_82542_rev2_0, 2322 * e1000_82542_rev2_1, 2323 * e1000_82543, 2324 * e1000_82541, 2325 * e1000_82541_rev_2, 2326 * e1000_82547, 2327 * e1000_82547_rev_2, 2328 * e1000_num_macs 2329 */ 2330 default: 2331 return (B_FALSE); 2332 } 2333 2334 break; 2335 } 2336 case MAC_CAPAB_POLL: 2337 /* 2338 * There's nothing for us to fill in, simply returning 2339 * B_TRUE stating that we support polling is sufficient. 2340 */ 2341 break; 2342 2343 case MAC_CAPAB_MULTIADDRESS: { 2344 multiaddress_capab_t *mmacp = cap_data; 2345 2346 /* 2347 * The number of MAC addresses made available by 2348 * this capability is one less than the total as 2349 * the primary address in slot 0 is counted in 2350 * the total. 2351 */ 2352 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2353 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2354 /* No multiple factory addresses, set mma_flag to 0 */ 2355 mmacp->maddr_flag = 0; 2356 mmacp->maddr_handle = Adapter; 2357 mmacp->maddr_add = e1000g_m_unicst_add; 2358 mmacp->maddr_remove = e1000g_m_unicst_remove; 2359 mmacp->maddr_modify = e1000g_m_unicst_modify; 2360 mmacp->maddr_get = e1000g_m_unicst_get; 2361 mmacp->maddr_reserve = NULL; 2362 break; 2363 } 2364 default: 2365 return (B_FALSE); 2366 } 2367 return (B_TRUE); 2368 } 2369 2370 /* 2371 * ********************************************************************** 2372 * Name: e1000g_getparam * 2373 * * 2374 * Description: This routine gets user-configured values out of the * 2375 * configuration file e1000g.conf. * 2376 * For each configurable value, there is a minimum, a maximum, and a * 2377 * default. * 2378 * If user does not configure a value, use the default. * 2379 * If user configures below the minimum, use the minumum. * 2380 * If user configures above the maximum, use the maxumum. * 2381 * * 2382 * Arguments: * 2383 * Adapter - A pointer to our adapter structure * 2384 * * 2385 * Returns: None * 2386 * ********************************************************************** 2387 */ 2388 static void 2389 e1000g_getparam(struct e1000g *Adapter) 2390 { 2391 /* 2392 * get each configurable property from e1000g.conf 2393 */ 2394 2395 /* 2396 * NumTxDescriptors 2397 */ 2398 Adapter->NumTxDescriptors = 2399 e1000g_getprop(Adapter, "NumTxDescriptors", 2400 MINNUMTXDESCRIPTOR, MAXNUMTXDESCRIPTOR, 2401 DEFAULTNUMTXDESCRIPTOR); 2402 2403 /* 2404 * NumRxDescriptors 2405 */ 2406 Adapter->NumRxDescriptors = 2407 e1000g_getprop(Adapter, "NumRxDescriptors", 2408 MINNUMRXDESCRIPTOR, MAXNUMRXDESCRIPTOR, 2409 DEFAULTNUMRXDESCRIPTOR); 2410 2411 /* 2412 * NumRxFreeList 2413 */ 2414 Adapter->NumRxFreeList = 2415 e1000g_getprop(Adapter, "NumRxFreeList", 2416 MINNUMRXFREELIST, MAXNUMRXFREELIST, 2417 DEFAULTNUMRXFREELIST); 2418 2419 /* 2420 * NumTxPacketList 2421 */ 2422 Adapter->NumTxSwPacket = 2423 e1000g_getprop(Adapter, "NumTxPacketList", 2424 MINNUMTXSWPACKET, MAXNUMTXSWPACKET, 2425 DEFAULTNUMTXSWPACKET); 2426 2427 /* 2428 * FlowControl 2429 */ 2430 Adapter->Shared.fc_send_xon = B_TRUE; 2431 Adapter->Shared.fc = 2432 e1000g_getprop(Adapter, "FlowControl", 2433 E1000_FC_NONE, 4, DEFAULTFLOWCONTROLVAL); 2434 /* 4 is the setting that says "let the eeprom decide" */ 2435 if (Adapter->Shared.fc == 4) 2436 Adapter->Shared.fc = E1000_FC_DEFAULT; 2437 2438 /* 2439 * MaxNumReceivePackets 2440 */ 2441 Adapter->MaxNumReceivePackets = 2442 e1000g_getprop(Adapter, "MaxNumReceivePackets", 2443 MINNUMRCVPKTONINTR, MAXNUMRCVPKTONINTR, 2444 DEFAULTMAXNUMRCVPKTONINTR); 2445 2446 /* 2447 * TxInterruptDelay 2448 */ 2449 Adapter->TxInterruptDelay = 2450 e1000g_getprop(Adapter, "TxInterruptDelay", 2451 MINTXINTERRUPTDELAYVAL, MAXTXINTERRUPTDELAYVAL, 2452 DEFAULTTXINTERRUPTDELAYVAL); 2453 2454 /* 2455 * PHY master slave setting 2456 */ 2457 Adapter->Shared.master_slave = 2458 e1000g_getprop(Adapter, "SetMasterSlave", 2459 e1000_ms_hw_default, e1000_ms_auto, 2460 e1000_ms_hw_default); 2461 2462 /* 2463 * Parameter which controls TBI mode workaround, which is only 2464 * needed on certain switches such as Cisco 6500/Foundry 2465 */ 2466 Adapter->Shared.tbi_compatibility_en = 2467 e1000g_getprop(Adapter, "TbiCompatibilityEnable", 2468 0, 1, DEFAULTTBICOMPATIBILITYENABLE); 2469 2470 /* 2471 * MSI Enable 2472 */ 2473 Adapter->msi_enabled = 2474 e1000g_getprop(Adapter, "MSIEnable", 2475 0, 1, DEFAULTMSIENABLE); 2476 2477 /* 2478 * Interrupt Throttling Rate 2479 */ 2480 Adapter->intr_throttling_rate = 2481 e1000g_getprop(Adapter, "intr_throttling_rate", 2482 MININTERRUPTTHROTTLINGVAL, MAXINTERRUPTTHROTTLINGVAL, 2483 DEFAULTINTERRUPTTHROTTLINGVAL); 2484 2485 /* 2486 * Adaptive Interrupt Blanking Enable/Disable 2487 * It is enabled by default 2488 */ 2489 Adapter->intr_adaptive = 2490 (e1000g_getprop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2491 B_TRUE : B_FALSE; 2492 } 2493 2494 /* 2495 * ********************************************************************** 2496 * Name: e1000g_getprop * 2497 * * 2498 * Description: get a user-configure property value out of the * 2499 * configuration file e1000g.conf. * 2500 * Caller provides name of the property, a default value, a * 2501 * minimum value, and a maximum value. * 2502 * * 2503 * Returns: configured value of the property, with default, minimum and * 2504 * maximum properly applied. * 2505 * ********************************************************************** 2506 */ 2507 static int 2508 e1000g_getprop(struct e1000g *Adapter, /* point to per-adapter structure */ 2509 char *propname, /* name of the property */ 2510 int minval, /* minimum acceptable value */ 2511 int maxval, /* maximim acceptable value */ 2512 int defval) /* default value */ 2513 { 2514 int propval; /* value returned for requested property */ 2515 int *props; /* point to array of properties returned */ 2516 uint_t nprops; /* number of property value returned */ 2517 2518 /* 2519 * get the array of properties from the config file 2520 */ 2521 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2522 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2523 /* got some properties, test if we got enough */ 2524 if (Adapter->AdapterInstance < nprops) { 2525 propval = props[Adapter->AdapterInstance]; 2526 } else { 2527 /* not enough properties configured */ 2528 propval = defval; 2529 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2530 "Not Enough %s values found in e1000g.conf" 2531 " - set to %d\n", 2532 propname, propval); 2533 } 2534 2535 /* free memory allocated for properties */ 2536 ddi_prop_free(props); 2537 2538 } else { 2539 propval = defval; 2540 } 2541 2542 /* 2543 * enforce limits 2544 */ 2545 if (propval > maxval) { 2546 propval = maxval; 2547 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2548 "Too High %s value in e1000g.conf - set to %d\n", 2549 propname, propval); 2550 } 2551 2552 if (propval < minval) { 2553 propval = minval; 2554 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2555 "Too Low %s value in e1000g.conf - set to %d\n", 2556 propname, propval); 2557 } 2558 2559 return (propval); 2560 } 2561 2562 static boolean_t 2563 e1000g_link_check(struct e1000g *Adapter) 2564 { 2565 uint16_t speed, duplex, phydata; 2566 boolean_t link_changed = B_FALSE; 2567 struct e1000_hw *hw; 2568 uint32_t reg_tarc; 2569 2570 hw = &Adapter->Shared; 2571 2572 if (e1000g_link_up(Adapter)) { 2573 /* 2574 * The Link is up, check whether it was marked as down earlier 2575 */ 2576 if (Adapter->link_state != LINK_STATE_UP) { 2577 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2578 Adapter->link_speed = speed; 2579 Adapter->link_duplex = duplex; 2580 Adapter->link_state = LINK_STATE_UP; 2581 link_changed = B_TRUE; 2582 2583 Adapter->tx_link_down_timeout = 0; 2584 2585 if ((hw->mac_type == e1000_82571) || 2586 (hw->mac_type == e1000_82572)) { 2587 reg_tarc = E1000_READ_REG(hw, TARC0); 2588 if (speed == SPEED_1000) 2589 reg_tarc |= (1 << 21); 2590 else 2591 reg_tarc &= ~(1 << 21); 2592 E1000_WRITE_REG(hw, TARC0, reg_tarc); 2593 } 2594 } 2595 Adapter->smartspeed = 0; 2596 } else { 2597 if (Adapter->link_state != LINK_STATE_DOWN) { 2598 Adapter->link_speed = 0; 2599 Adapter->link_duplex = 0; 2600 Adapter->link_state = LINK_STATE_DOWN; 2601 link_changed = B_TRUE; 2602 2603 /* 2604 * SmartSpeed workaround for Tabor/TanaX, When the 2605 * driver loses link disable auto master/slave 2606 * resolution. 2607 */ 2608 if (hw->phy_type == e1000_phy_igp) { 2609 e1000_read_phy_reg(hw, 2610 PHY_1000T_CTRL, &phydata); 2611 phydata |= CR_1000T_MS_ENABLE; 2612 e1000_write_phy_reg(hw, 2613 PHY_1000T_CTRL, phydata); 2614 } 2615 } else { 2616 e1000g_smartspeed(Adapter); 2617 } 2618 2619 if (Adapter->started) { 2620 if (Adapter->tx_link_down_timeout < 2621 MAX_TX_LINK_DOWN_TIMEOUT) { 2622 Adapter->tx_link_down_timeout++; 2623 } else if (Adapter->tx_link_down_timeout == 2624 MAX_TX_LINK_DOWN_TIMEOUT) { 2625 rw_enter(&Adapter->chip_lock, RW_WRITER); 2626 e1000g_tx_drop(Adapter); 2627 rw_exit(&Adapter->chip_lock); 2628 Adapter->tx_link_down_timeout++; 2629 } 2630 } 2631 } 2632 2633 return (link_changed); 2634 } 2635 2636 static void 2637 e1000g_LocalTimer(void *ws) 2638 { 2639 struct e1000g *Adapter = (struct e1000g *)ws; 2640 struct e1000_hw *hw; 2641 e1000g_ether_addr_t ether_addr; 2642 boolean_t link_changed; 2643 2644 hw = &Adapter->Shared; 2645 2646 (void) e1000g_tx_freemsg((caddr_t)Adapter, NULL); 2647 2648 if (e1000g_stall_check(Adapter)) { 2649 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 2650 "Tx stall detected. Activate automatic recovery.\n"); 2651 Adapter->StallWatchdog = 0; 2652 Adapter->tx_recycle_fail = 0; 2653 Adapter->reset_count++; 2654 (void) e1000g_reset(Adapter); 2655 } 2656 2657 link_changed = B_FALSE; 2658 mutex_enter(&Adapter->e1000g_linklock); 2659 if (Adapter->link_complete) 2660 link_changed = e1000g_link_check(Adapter); 2661 mutex_exit(&Adapter->e1000g_linklock); 2662 2663 if (link_changed) { 2664 /* 2665 * Workaround for esb2. Data stuck in fifo on a link 2666 * down event. Reset the adapter to recover it. 2667 */ 2668 if ((Adapter->link_state == LINK_STATE_DOWN) && 2669 (hw->mac_type == e1000_80003es2lan)) 2670 (void) e1000g_reset(Adapter); 2671 2672 mac_link_update(Adapter->mh, Adapter->link_state); 2673 } 2674 2675 /* 2676 * With 82571 controllers, any locally administered address will 2677 * be overwritten when there is a reset on the other port. 2678 * Detect this circumstance and correct it. 2679 */ 2680 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) { 2681 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, RA, 0); 2682 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, RA, 1); 2683 2684 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2685 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2686 2687 if ((ether_addr.mac.addr[5] != hw->mac_addr[0]) || 2688 (ether_addr.mac.addr[4] != hw->mac_addr[1]) || 2689 (ether_addr.mac.addr[3] != hw->mac_addr[2]) || 2690 (ether_addr.mac.addr[2] != hw->mac_addr[3]) || 2691 (ether_addr.mac.addr[1] != hw->mac_addr[4]) || 2692 (ether_addr.mac.addr[0] != hw->mac_addr[5])) { 2693 e1000_rar_set(hw, hw->mac_addr, 0); 2694 } 2695 } 2696 2697 /* 2698 * RP: ttl_workaround : DCR 49 2699 */ 2700 e1000_igp_ttl_workaround(hw); 2701 2702 /* 2703 * Check for Adaptive IFS settings If there are lots of collisions 2704 * change the value in steps... 2705 * These properties should only be set for 10/100 2706 */ 2707 if ((hw->media_type == e1000_media_type_copper) && 2708 ((Adapter->link_speed == SPEED_100) || 2709 (Adapter->link_speed == SPEED_10))) { 2710 e1000_update_adaptive(hw); 2711 } 2712 /* 2713 * Set Timer Interrupts 2714 */ 2715 E1000_WRITE_REG(hw, ICS, E1000_IMS_RXT0); 2716 2717 restart_timeout(Adapter); 2718 } 2719 2720 /* 2721 * The function e1000g_link_timer() is called when the timer for link setup 2722 * is expired, which indicates the completion of the link setup. The link 2723 * state will not be updated until the link setup is completed. And the 2724 * link state will not be sent to the upper layer through mac_link_update() 2725 * in this function. It will be updated in the local timer routine or the 2726 * interrupt service routine after the interface is started (plumbed). 2727 */ 2728 static void 2729 e1000g_link_timer(void *arg) 2730 { 2731 struct e1000g *Adapter = (struct e1000g *)arg; 2732 2733 mutex_enter(&Adapter->e1000g_linklock); 2734 Adapter->link_complete = B_TRUE; 2735 Adapter->link_tid = 0; 2736 mutex_exit(&Adapter->e1000g_linklock); 2737 } 2738 2739 /* 2740 * ********************************************************************** 2741 * Name: e1000g_force_speed_duplex * 2742 * * 2743 * Description: * 2744 * This function forces speed and duplex for 10/100 Mbps speeds * 2745 * and also for 1000 Mbps speeds, it advertises half or full duplex * 2746 * * 2747 * Parameter Passed: * 2748 * struct e1000g* (information of adpater) * 2749 * * 2750 * Return Value: * 2751 * * 2752 * Functions called: * 2753 * ********************************************************************** 2754 */ 2755 static void 2756 e1000g_force_speed_duplex(struct e1000g *Adapter) 2757 { 2758 int forced; 2759 2760 /* 2761 * get value out of config file 2762 */ 2763 forced = e1000g_getprop(Adapter, "ForceSpeedDuplex", 2764 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2765 2766 switch (forced) { 2767 case GDIAG_10_HALF: 2768 /* 2769 * Disable Auto Negotiation 2770 */ 2771 Adapter->Shared.autoneg = B_FALSE; 2772 Adapter->Shared.forced_speed_duplex = e1000_10_half; 2773 break; 2774 case GDIAG_10_FULL: 2775 /* 2776 * Disable Auto Negotiation 2777 */ 2778 Adapter->Shared.autoneg = B_FALSE; 2779 Adapter->Shared.forced_speed_duplex = e1000_10_full; 2780 break; 2781 case GDIAG_100_HALF: 2782 /* 2783 * Disable Auto Negotiation 2784 */ 2785 Adapter->Shared.autoneg = B_FALSE; 2786 Adapter->Shared.forced_speed_duplex = e1000_100_half; 2787 break; 2788 case GDIAG_100_FULL: 2789 /* 2790 * Disable Auto Negotiation 2791 */ 2792 Adapter->Shared.autoneg = B_FALSE; 2793 Adapter->Shared.forced_speed_duplex = e1000_100_full; 2794 break; 2795 case GDIAG_1000_FULL: 2796 /* 2797 * The gigabit spec requires autonegotiation. Therefore, 2798 * when the user wants to force the speed to 1000Mbps, we 2799 * enable AutoNeg, but only allow the harware to advertise 2800 * 1000Mbps. This is different from 10/100 operation, where 2801 * we are allowed to link without any negotiation. 2802 */ 2803 Adapter->Shared.autoneg = B_TRUE; 2804 Adapter->Shared.autoneg_advertised = ADVERTISE_1000_FULL; 2805 break; 2806 default: /* obey the setting of AutoNegAdvertised */ 2807 Adapter->Shared.autoneg = B_TRUE; 2808 Adapter->Shared.autoneg_advertised = 2809 (uint16_t)e1000g_getprop(Adapter, "AutoNegAdvertised", 2810 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 2811 AUTONEG_ADVERTISE_SPEED_DEFAULT); 2812 break; 2813 } /* switch */ 2814 } 2815 2816 /* 2817 * ********************************************************************** 2818 * Name: e1000g_get_max_frame_size * 2819 * * 2820 * Description: * 2821 * This function reads MaxFrameSize from e1000g.conf and sets it for * 2822 * adapter. * 2823 * * 2824 * Parameter Passed: * 2825 * struct e1000g* (information of adpater) * 2826 * * 2827 * Return Value: * 2828 * * 2829 * Functions called: * 2830 * ********************************************************************** 2831 */ 2832 static void 2833 e1000g_get_max_frame_size(struct e1000g *Adapter) 2834 { 2835 int max_frame; 2836 2837 /* 2838 * get value out of config file 2839 */ 2840 max_frame = e1000g_getprop(Adapter, "MaxFrameSize", 0, 3, 0); 2841 2842 switch (max_frame) { 2843 case 0: 2844 Adapter->Shared.max_frame_size = ETHERMAX; 2845 break; 2846 case 1: 2847 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_4K; 2848 break; 2849 case 2: 2850 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_8K; 2851 break; 2852 case 3: 2853 if (Adapter->Shared.mac_type < e1000_82571) 2854 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_16K; 2855 else 2856 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_10K; 2857 break; 2858 default: 2859 Adapter->Shared.max_frame_size = ETHERMAX; 2860 break; 2861 } /* switch */ 2862 2863 /* ich8 does not do jumbo frames */ 2864 if (Adapter->Shared.mac_type == e1000_ich8lan) { 2865 Adapter->Shared.max_frame_size = ETHERMAX; 2866 } 2867 } 2868 2869 static void 2870 arm_timer(struct e1000g *Adapter) 2871 { 2872 Adapter->WatchDogTimer_id = 2873 timeout(e1000g_LocalTimer, 2874 (void *)Adapter, 1 * drv_usectohz(1000000)); 2875 } 2876 2877 static void 2878 enable_timeout(struct e1000g *Adapter) 2879 { 2880 mutex_enter(&Adapter->e1000g_timeout_lock); 2881 2882 if (!Adapter->timeout_enabled) { 2883 Adapter->timeout_enabled = B_TRUE; 2884 Adapter->timeout_started = B_TRUE; 2885 2886 arm_timer(Adapter); 2887 } 2888 2889 mutex_exit(&Adapter->e1000g_timeout_lock); 2890 } 2891 2892 static void 2893 disable_timeout(struct e1000g *Adapter) 2894 { 2895 timeout_id_t tid; 2896 2897 mutex_enter(&Adapter->e1000g_timeout_lock); 2898 2899 Adapter->timeout_enabled = B_FALSE; 2900 Adapter->timeout_started = B_FALSE; 2901 2902 tid = Adapter->WatchDogTimer_id; 2903 Adapter->WatchDogTimer_id = 0; 2904 2905 mutex_exit(&Adapter->e1000g_timeout_lock); 2906 2907 if (tid != 0) 2908 (void) untimeout(tid); 2909 } 2910 2911 static void 2912 start_timeout(struct e1000g *Adapter) 2913 { 2914 mutex_enter(&Adapter->e1000g_timeout_lock); 2915 2916 if (Adapter->timeout_enabled) { 2917 if (!Adapter->timeout_started) { 2918 Adapter->timeout_started = B_TRUE; 2919 arm_timer(Adapter); 2920 } 2921 } 2922 2923 mutex_exit(&Adapter->e1000g_timeout_lock); 2924 } 2925 2926 static void 2927 restart_timeout(struct e1000g *Adapter) 2928 { 2929 mutex_enter(&Adapter->e1000g_timeout_lock); 2930 2931 if (Adapter->timeout_started) 2932 arm_timer(Adapter); 2933 2934 mutex_exit(&Adapter->e1000g_timeout_lock); 2935 } 2936 2937 static void 2938 stop_timeout(struct e1000g *Adapter) 2939 { 2940 timeout_id_t tid; 2941 2942 mutex_enter(&Adapter->e1000g_timeout_lock); 2943 2944 Adapter->timeout_started = B_FALSE; 2945 2946 tid = Adapter->WatchDogTimer_id; 2947 Adapter->WatchDogTimer_id = 0; 2948 2949 mutex_exit(&Adapter->e1000g_timeout_lock); 2950 2951 if (tid != 0) 2952 (void) untimeout(tid); 2953 } 2954 2955 void 2956 e1000g_DisableInterrupt(struct e1000g *Adapter) 2957 { 2958 E1000_WRITE_REG(&Adapter->Shared, IMC, 2959 0xffffffff & ~E1000_IMC_RXSEQ); 2960 } 2961 2962 void 2963 e1000g_EnableInterrupt(struct e1000g *Adapter) 2964 { 2965 E1000_WRITE_REG(&Adapter->Shared, IMS, 2966 IMS_ENABLE_MASK & ~E1000_IMS_TXDW & ~E1000_IMS_TXQE); 2967 } 2968 2969 void 2970 e1000g_DisableAllInterrupts(struct e1000g *Adapter) 2971 { 2972 E1000_WRITE_REG(&Adapter->Shared, IMC, 0xffffffff) 2973 } 2974 2975 void 2976 e1000g_EnableTxInterrupt(struct e1000g *Adapter) 2977 { 2978 E1000_WRITE_REG(&Adapter->Shared, IMS, E1000G_IMS_TX_INTR); 2979 } 2980 2981 void 2982 e1000g_DisableTxInterrupt(struct e1000g *Adapter) 2983 { 2984 E1000_WRITE_REG(&Adapter->Shared, IMC, E1000G_IMC_TX_INTR); 2985 } 2986 2987 void 2988 e1000_pci_set_mwi(struct e1000_hw *hw) 2989 { 2990 uint16_t val = hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE; 2991 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2992 } 2993 2994 void 2995 e1000_pci_clear_mwi(struct e1000_hw *hw) 2996 { 2997 uint16_t val = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; 2998 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2999 } 3000 3001 void 3002 e1000_write_pci_cfg(struct e1000_hw *adapter, 3003 uint32_t reg, uint16_t *value) 3004 { 3005 pci_config_put16(((struct e1000g_osdep *)(adapter->back))->handle, 3006 reg, *value); 3007 } 3008 3009 void 3010 e1000_read_pci_cfg(struct e1000_hw *adapter, 3011 uint32_t reg, uint16_t *value) 3012 { 3013 *value = 3014 pci_config_get16(((struct e1000g_osdep *)(adapter->back))-> 3015 handle, reg); 3016 } 3017 3018 #ifndef __sparc 3019 void 3020 e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 3021 { 3022 outl(port, value); 3023 } 3024 3025 uint32_t 3026 e1000_io_read(struct e1000_hw *hw, unsigned long port) 3027 { 3028 return (inl(port)); 3029 } 3030 #endif 3031 3032 static void 3033 e1000g_smartspeed(struct e1000g *adapter) 3034 { 3035 uint16_t phy_status; 3036 uint16_t phy_ctrl; 3037 3038 /* 3039 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3040 * advertising 1000Full, we don't even use the workaround 3041 */ 3042 if ((adapter->Shared.phy_type != e1000_phy_igp) || 3043 !adapter->Shared.autoneg || 3044 !(adapter->Shared.autoneg_advertised & ADVERTISE_1000_FULL)) 3045 return; 3046 3047 /* 3048 * True if this is the first call of this function or after every 3049 * 30 seconds of not having link 3050 */ 3051 if (adapter->smartspeed == 0) { 3052 /* 3053 * If Master/Slave config fault is asserted twice, we 3054 * assume back-to-back 3055 */ 3056 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 3057 &phy_status); 3058 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3059 return; 3060 3061 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 3062 &phy_status); 3063 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3064 return; 3065 /* 3066 * We're assuming back-2-back because our status register 3067 * insists! there's a fault in the master/slave 3068 * relationship that was "negotiated" 3069 */ 3070 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3071 &phy_ctrl); 3072 /* 3073 * Is the phy configured for manual configuration of 3074 * master/slave? 3075 */ 3076 if (phy_ctrl & CR_1000T_MS_ENABLE) { 3077 /* 3078 * Yes. Then disable manual configuration (enable 3079 * auto configuration) of master/slave 3080 */ 3081 phy_ctrl &= ~CR_1000T_MS_ENABLE; 3082 e1000_write_phy_reg(&adapter->Shared, 3083 PHY_1000T_CTRL, phy_ctrl); 3084 /* 3085 * Effectively starting the clock 3086 */ 3087 adapter->smartspeed++; 3088 /* 3089 * Restart autonegotiation 3090 */ 3091 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 3092 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 3093 &phy_ctrl)) { 3094 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 3095 MII_CR_RESTART_AUTO_NEG); 3096 e1000_write_phy_reg(&adapter->Shared, 3097 PHY_CTRL, phy_ctrl); 3098 } 3099 } 3100 return; 3101 /* 3102 * Has 6 seconds transpired still without link? Remember, 3103 * you should reset the smartspeed counter once you obtain 3104 * link 3105 */ 3106 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 3107 /* 3108 * Yes. Remember, we did at the start determine that 3109 * there's a master/slave configuration fault, so we're 3110 * still assuming there's someone on the other end, but we 3111 * just haven't yet been able to talk to it. We then 3112 * re-enable auto configuration of master/slave to see if 3113 * we're running 2/3 pair cables. 3114 */ 3115 /* 3116 * If still no link, perhaps using 2/3 pair cable 3117 */ 3118 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3119 &phy_ctrl); 3120 phy_ctrl |= CR_1000T_MS_ENABLE; 3121 e1000_write_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3122 phy_ctrl); 3123 /* 3124 * Restart autoneg with phy enabled for manual 3125 * configuration of master/slave 3126 */ 3127 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 3128 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 3129 &phy_ctrl)) { 3130 phy_ctrl |= 3131 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3132 e1000_write_phy_reg(&adapter->Shared, PHY_CTRL, 3133 phy_ctrl); 3134 } 3135 /* 3136 * Hopefully, there are no more faults and we've obtained 3137 * link as a result. 3138 */ 3139 } 3140 /* 3141 * Restart process after E1000_SMARTSPEED_MAX iterations (30 3142 * seconds) 3143 */ 3144 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 3145 adapter->smartspeed = 0; 3146 } 3147 3148 static boolean_t 3149 is_valid_mac_addr(uint8_t *mac_addr) 3150 { 3151 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3152 const uint8_t addr_test2[6] = 3153 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3154 3155 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3156 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3157 return (B_FALSE); 3158 3159 return (B_TRUE); 3160 } 3161 3162 /* 3163 * ********************************************************************** 3164 * Name: * 3165 * e1000g_stall_check * 3166 * * 3167 * Description: * 3168 * This function checks if the adapter is stalled. (In transmit) * 3169 * * 3170 * It is called each time the timeout is invoked. * 3171 * If the transmit descriptor reclaim continuously fails, * 3172 * the watchdog value will increment by 1. If the watchdog * 3173 * value exceeds the threshold, the adapter is assumed to * 3174 * have stalled and need to be reset. * 3175 * * 3176 * Arguments: * 3177 * Adapter - A pointer to our context sensitive "Adapter" * 3178 * structure. * 3179 * * 3180 * Returns: * 3181 * B_TRUE - The dapter is assumed to have stalled. * 3182 * B_FALSE * 3183 * * 3184 * ********************************************************************** 3185 */ 3186 static boolean_t 3187 e1000g_stall_check(struct e1000g *Adapter) 3188 { 3189 if (Adapter->link_state != LINK_STATE_UP) 3190 return (B_FALSE); 3191 3192 if (Adapter->tx_recycle_fail > 0) 3193 Adapter->StallWatchdog++; 3194 else 3195 Adapter->StallWatchdog = 0; 3196 3197 if (Adapter->StallWatchdog < E1000G_STALL_WATCHDOG_COUNT) 3198 return (B_FALSE); 3199 3200 return (B_TRUE); 3201 } 3202 3203 3204 static enum ioc_reply 3205 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3206 { 3207 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3208 e1000g_peekpoke_t *ppd; 3209 uint64_t mem_va; 3210 uint64_t maxoff; 3211 boolean_t peek; 3212 3213 switch (iocp->ioc_cmd) { 3214 3215 case E1000G_IOC_REG_PEEK: 3216 peek = B_TRUE; 3217 break; 3218 3219 case E1000G_IOC_REG_POKE: 3220 peek = B_FALSE; 3221 break; 3222 3223 deault: 3224 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3225 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3226 iocp->ioc_cmd); 3227 return (IOC_INVAL); 3228 } 3229 3230 /* 3231 * Validate format of ioctl 3232 */ 3233 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3234 return (IOC_INVAL); 3235 if (mp->b_cont == NULL) 3236 return (IOC_INVAL); 3237 3238 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3239 3240 /* 3241 * Validate request parameters 3242 */ 3243 switch (ppd->pp_acc_space) { 3244 3245 default: 3246 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3247 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3248 ppd->pp_acc_space); 3249 return (IOC_INVAL); 3250 3251 case E1000G_PP_SPACE_REG: 3252 /* 3253 * Memory-mapped I/O space 3254 */ 3255 ASSERT(ppd->pp_acc_size == 4); 3256 if (ppd->pp_acc_size != 4) 3257 return (IOC_INVAL); 3258 3259 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3260 return (IOC_INVAL); 3261 3262 mem_va = 0; 3263 maxoff = 0x10000; 3264 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3265 break; 3266 3267 case E1000G_PP_SPACE_E1000G: 3268 /* 3269 * E1000g data structure! 3270 */ 3271 mem_va = (uintptr_t)e1000gp; 3272 maxoff = sizeof (struct e1000g); 3273 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3274 break; 3275 3276 } 3277 3278 if (ppd->pp_acc_offset >= maxoff) 3279 return (IOC_INVAL); 3280 3281 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3282 return (IOC_INVAL); 3283 3284 /* 3285 * All OK - go! 3286 */ 3287 ppd->pp_acc_offset += mem_va; 3288 (*ppfn)(e1000gp, ppd); 3289 return (peek ? IOC_REPLY : IOC_ACK); 3290 } 3291 3292 static void 3293 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3294 { 3295 ddi_acc_handle_t handle; 3296 uint32_t *regaddr; 3297 3298 handle = 3299 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle; 3300 regaddr = 3301 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3302 3303 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3304 } 3305 3306 static void 3307 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3308 { 3309 ddi_acc_handle_t handle; 3310 uint32_t *regaddr; 3311 uint32_t value; 3312 3313 handle = 3314 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle; 3315 regaddr = 3316 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3317 value = (uint32_t)ppd->pp_acc_data; 3318 3319 ddi_put32(handle, regaddr, value); 3320 } 3321 3322 static void 3323 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3324 { 3325 uint64_t value; 3326 void *vaddr; 3327 3328 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3329 3330 switch (ppd->pp_acc_size) { 3331 case 1: 3332 value = *(uint8_t *)vaddr; 3333 break; 3334 3335 case 2: 3336 value = *(uint16_t *)vaddr; 3337 break; 3338 3339 case 4: 3340 value = *(uint32_t *)vaddr; 3341 break; 3342 3343 case 8: 3344 value = *(uint64_t *)vaddr; 3345 break; 3346 } 3347 3348 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3349 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3350 (void *)e1000gp, (void *)ppd, value, vaddr); 3351 3352 ppd->pp_acc_data = value; 3353 } 3354 3355 static void 3356 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3357 { 3358 uint64_t value; 3359 void *vaddr; 3360 3361 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3362 value = ppd->pp_acc_data; 3363 3364 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3365 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3366 (void *)e1000gp, (void *)ppd, value, vaddr); 3367 3368 switch (ppd->pp_acc_size) { 3369 case 1: 3370 *(uint8_t *)vaddr = (uint8_t)value; 3371 break; 3372 3373 case 2: 3374 *(uint16_t *)vaddr = (uint16_t)value; 3375 break; 3376 3377 case 4: 3378 *(uint32_t *)vaddr = (uint32_t)value; 3379 break; 3380 3381 case 8: 3382 *(uint64_t *)vaddr = (uint64_t)value; 3383 break; 3384 } 3385 } 3386 3387 /* 3388 * Loopback Support 3389 */ 3390 static lb_property_t lb_normal = 3391 { normal, "normal", E1000G_LB_NONE }; 3392 static lb_property_t lb_external1000 = 3393 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3394 static lb_property_t lb_external100 = 3395 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3396 static lb_property_t lb_external10 = 3397 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3398 static lb_property_t lb_phy = 3399 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3400 3401 static enum ioc_reply 3402 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3403 { 3404 lb_info_sz_t *lbsp; 3405 lb_property_t *lbpp; 3406 struct e1000_hw *hw; 3407 uint32_t *lbmp; 3408 uint32_t size; 3409 uint32_t value; 3410 uint16_t phy_status; 3411 uint16_t phy_ext_status; 3412 3413 hw = &Adapter->Shared; 3414 3415 if (mp->b_cont == NULL) 3416 return (IOC_INVAL); 3417 3418 switch (iocp->ioc_cmd) { 3419 default: 3420 return (IOC_INVAL); 3421 3422 case LB_GET_INFO_SIZE: 3423 size = sizeof (lb_info_sz_t); 3424 if (iocp->ioc_count != size) 3425 return (IOC_INVAL); 3426 3427 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3428 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3429 3430 value = sizeof (lb_normal); 3431 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3432 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3433 (hw->media_type == e1000_media_type_fiber) || 3434 (hw->media_type == e1000_media_type_internal_serdes)) { 3435 value += sizeof (lb_phy); 3436 switch (hw->mac_type) { 3437 case e1000_82571: 3438 case e1000_82572: 3439 value += sizeof (lb_external1000); 3440 break; 3441 } 3442 } 3443 if ((phy_status & MII_SR_100X_FD_CAPS) || 3444 (phy_status & MII_SR_100T2_FD_CAPS)) 3445 value += sizeof (lb_external100); 3446 if (phy_status & MII_SR_10T_FD_CAPS) 3447 value += sizeof (lb_external10); 3448 3449 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3450 *lbsp = value; 3451 break; 3452 3453 case LB_GET_INFO: 3454 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3455 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3456 3457 value = sizeof (lb_normal); 3458 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3459 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3460 (hw->media_type == e1000_media_type_fiber) || 3461 (hw->media_type == e1000_media_type_internal_serdes)) { 3462 value += sizeof (lb_phy); 3463 switch (hw->mac_type) { 3464 case e1000_82571: 3465 case e1000_82572: 3466 value += sizeof (lb_external1000); 3467 break; 3468 } 3469 } 3470 if ((phy_status & MII_SR_100X_FD_CAPS) || 3471 (phy_status & MII_SR_100T2_FD_CAPS)) 3472 value += sizeof (lb_external100); 3473 if (phy_status & MII_SR_10T_FD_CAPS) 3474 value += sizeof (lb_external10); 3475 3476 size = value; 3477 if (iocp->ioc_count != size) 3478 return (IOC_INVAL); 3479 3480 value = 0; 3481 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3482 lbpp[value++] = lb_normal; 3483 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3484 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3485 (hw->media_type == e1000_media_type_fiber) || 3486 (hw->media_type == e1000_media_type_internal_serdes)) { 3487 lbpp[value++] = lb_phy; 3488 switch (hw->mac_type) { 3489 case e1000_82571: 3490 case e1000_82572: 3491 lbpp[value++] = lb_external1000; 3492 break; 3493 } 3494 } 3495 if ((phy_status & MII_SR_100X_FD_CAPS) || 3496 (phy_status & MII_SR_100T2_FD_CAPS)) 3497 lbpp[value++] = lb_external100; 3498 if (phy_status & MII_SR_10T_FD_CAPS) 3499 lbpp[value++] = lb_external10; 3500 break; 3501 3502 case LB_GET_MODE: 3503 size = sizeof (uint32_t); 3504 if (iocp->ioc_count != size) 3505 return (IOC_INVAL); 3506 3507 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3508 *lbmp = Adapter->loopback_mode; 3509 break; 3510 3511 case LB_SET_MODE: 3512 size = 0; 3513 if (iocp->ioc_count != sizeof (uint32_t)) 3514 return (IOC_INVAL); 3515 3516 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3517 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3518 return (IOC_INVAL); 3519 break; 3520 } 3521 3522 iocp->ioc_count = size; 3523 iocp->ioc_error = 0; 3524 3525 return (IOC_REPLY); 3526 } 3527 3528 static boolean_t 3529 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3530 { 3531 struct e1000_hw *hw; 3532 #ifndef __sparc 3533 uint32_t reg_rctl; 3534 #endif 3535 int i, times; 3536 3537 if (mode == Adapter->loopback_mode) 3538 return (B_TRUE); 3539 3540 hw = &Adapter->Shared; 3541 times = 0; 3542 3543 again: 3544 switch (mode) { 3545 default: 3546 return (B_FALSE); 3547 3548 case E1000G_LB_NONE: 3549 /* Get original speed and duplex settings */ 3550 e1000g_force_speed_duplex(Adapter); 3551 /* Reset the chip */ 3552 hw->wait_autoneg_complete = B_TRUE; 3553 (void) e1000g_reset(Adapter); 3554 hw->wait_autoneg_complete = B_FALSE; 3555 break; 3556 3557 case E1000G_LB_EXTERNAL_1000: 3558 e1000g_set_external_loopback_1000(Adapter); 3559 break; 3560 3561 case E1000G_LB_EXTERNAL_100: 3562 e1000g_set_external_loopback_100(Adapter); 3563 break; 3564 3565 case E1000G_LB_EXTERNAL_10: 3566 e1000g_set_external_loopback_10(Adapter); 3567 break; 3568 3569 case E1000G_LB_INTERNAL_PHY: 3570 e1000g_set_internal_loopback(Adapter); 3571 break; 3572 } 3573 3574 times++; 3575 3576 switch (mode) { 3577 case E1000G_LB_EXTERNAL_1000: 3578 case E1000G_LB_EXTERNAL_100: 3579 case E1000G_LB_EXTERNAL_10: 3580 case E1000G_LB_INTERNAL_PHY: 3581 /* Wait for link up */ 3582 for (i = (PHY_FORCE_TIME * 2); i > 0; i--) 3583 msec_delay(100); 3584 3585 if (!e1000g_link_up(Adapter)) { 3586 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3587 "Failed to get the link up"); 3588 if (times < 2) { 3589 /* Reset the link */ 3590 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3591 "Reset the link ..."); 3592 (void) e1000g_reset(Adapter); 3593 goto again; 3594 } 3595 } 3596 break; 3597 } 3598 3599 Adapter->loopback_mode = mode; 3600 3601 return (B_TRUE); 3602 } 3603 3604 /* 3605 * The following loopback settings are from Intel's technical 3606 * document - "How To Loopback". All the register settings and 3607 * time delay values are directly inherited from the document 3608 * without more explanations available. 3609 */ 3610 static void 3611 e1000g_set_internal_loopback(struct e1000g *Adapter) 3612 { 3613 struct e1000_hw *hw; 3614 uint32_t ctrl; 3615 uint32_t status; 3616 uint16_t phy_ctrl; 3617 3618 hw = &Adapter->Shared; 3619 3620 /* Disable Smart Power Down */ 3621 phy_spd_state(hw, B_FALSE); 3622 3623 e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl); 3624 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3625 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3626 3627 switch (hw->mac_type) { 3628 case e1000_82540: 3629 case e1000_82545: 3630 case e1000_82545_rev_3: 3631 case e1000_82546: 3632 case e1000_82546_rev_3: 3633 case e1000_82573: 3634 /* Auto-MDI/MDIX off */ 3635 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3636 /* Reset PHY to update Auto-MDI/MDIX */ 3637 e1000_write_phy_reg(hw, PHY_CTRL, 3638 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3639 /* Reset PHY to auto-neg off and force 1000 */ 3640 e1000_write_phy_reg(hw, PHY_CTRL, 3641 phy_ctrl | MII_CR_RESET); 3642 break; 3643 } 3644 3645 /* Set loopback */ 3646 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl | MII_CR_LOOPBACK); 3647 3648 msec_delay(250); 3649 3650 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3651 ctrl = E1000_READ_REG(hw, CTRL); 3652 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3653 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3654 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3655 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3656 E1000_CTRL_FD); /* Force Duplex to FULL */ 3657 3658 switch (hw->mac_type) { 3659 case e1000_82540: 3660 case e1000_82545: 3661 case e1000_82545_rev_3: 3662 case e1000_82546: 3663 case e1000_82546_rev_3: 3664 /* 3665 * For some serdes we'll need to commit the writes now 3666 * so that the status is updated on link 3667 */ 3668 if (hw->media_type == e1000_media_type_internal_serdes) { 3669 E1000_WRITE_REG(hw, CTRL, ctrl); 3670 msec_delay(100); 3671 ctrl = E1000_READ_REG(hw, CTRL); 3672 } 3673 3674 if (hw->media_type == e1000_media_type_copper) { 3675 /* Invert Loss of Signal */ 3676 ctrl |= E1000_CTRL_ILOS; 3677 } else { 3678 /* Set ILOS on fiber nic if half duplex is detected */ 3679 status = E1000_READ_REG(hw, STATUS); 3680 if ((status & E1000_STATUS_FD) == 0) 3681 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3682 } 3683 break; 3684 3685 case e1000_82571: 3686 case e1000_82572: 3687 if (hw->media_type != e1000_media_type_copper) { 3688 /* Set ILOS on fiber nic if half duplex is detected */ 3689 status = E1000_READ_REG(hw, STATUS); 3690 if ((status & E1000_STATUS_FD) == 0) 3691 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3692 } 3693 break; 3694 3695 case e1000_82573: 3696 ctrl |= E1000_CTRL_ILOS; 3697 break; 3698 } 3699 3700 E1000_WRITE_REG(hw, CTRL, ctrl); 3701 3702 /* 3703 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3704 * For background, see comments above e1000g_set_internal_loopback(). 3705 */ 3706 switch (hw->mac_type) { 3707 case e1000_82540: 3708 case e1000_82545: 3709 case e1000_82545_rev_3: 3710 case e1000_82546: 3711 case e1000_82546_rev_3: 3712 case e1000_82573: 3713 e1000_write_phy_reg(hw, 29, 0x001F); 3714 e1000_write_phy_reg(hw, 30, 0x8FFC); 3715 e1000_write_phy_reg(hw, 29, 0x001A); 3716 e1000_write_phy_reg(hw, 30, 0x8FF0); 3717 break; 3718 } 3719 } 3720 3721 static void 3722 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3723 { 3724 struct e1000_hw *hw; 3725 uint32_t rctl; 3726 uint32_t ctrl_ext; 3727 uint32_t ctrl; 3728 uint32_t status; 3729 uint32_t txcw; 3730 3731 hw = &Adapter->Shared; 3732 3733 /* Disable Smart Power Down */ 3734 phy_spd_state(hw, B_FALSE); 3735 3736 switch (hw->media_type) { 3737 case e1000_media_type_copper: 3738 /* Force link up (Must be done before the PHY writes) */ 3739 ctrl = E1000_READ_REG(hw, CTRL); 3740 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3741 E1000_WRITE_REG(hw, CTRL, ctrl); 3742 3743 rctl = E1000_READ_REG(hw, RCTL); 3744 rctl |= (E1000_RCTL_EN | 3745 E1000_RCTL_SBP | 3746 E1000_RCTL_UPE | 3747 E1000_RCTL_MPE | 3748 E1000_RCTL_LPE | 3749 E1000_RCTL_BAM); /* 0x803E */ 3750 E1000_WRITE_REG(hw, RCTL, rctl); 3751 3752 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3753 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3754 E1000_CTRL_EXT_SDP6_DATA | 3755 E1000_CTRL_EXT_SDP7_DATA | 3756 E1000_CTRL_EXT_SDP4_DIR | 3757 E1000_CTRL_EXT_SDP6_DIR | 3758 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3759 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3760 3761 /* 3762 * This sequence tunes the PHY's SDP and no customer 3763 * settable values. For background, see comments above 3764 * e1000g_set_internal_loopback(). 3765 */ 3766 e1000_write_phy_reg(hw, 0x0, 0x140); 3767 msec_delay(10); 3768 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3769 e1000_write_phy_reg(hw, 0x12, 0xC10); 3770 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3771 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3772 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3773 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3774 3775 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3776 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3777 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3778 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3779 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3780 3781 msec_delay(50); 3782 break; 3783 case e1000_media_type_fiber: 3784 case e1000_media_type_internal_serdes: 3785 status = E1000_READ_REG(hw, STATUS); 3786 if (((status & E1000_STATUS_LU) == 0) || 3787 (hw->media_type == e1000_media_type_internal_serdes)) { 3788 ctrl = E1000_READ_REG(hw, CTRL); 3789 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3790 E1000_WRITE_REG(hw, CTRL, ctrl); 3791 } 3792 3793 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3794 txcw = E1000_READ_REG(hw, TXCW); 3795 txcw &= ~((uint32_t)1 << 31); 3796 E1000_WRITE_REG(hw, TXCW, txcw); 3797 3798 /* 3799 * Write 0x410 to Serdes Control register 3800 * to enable Serdes analog loopback 3801 */ 3802 E1000_WRITE_REG(hw, SCTL, 0x0410); 3803 msec_delay(10); 3804 break; 3805 default: 3806 break; 3807 } 3808 } 3809 3810 static void 3811 e1000g_set_external_loopback_100(struct e1000g *Adapter) 3812 { 3813 struct e1000_hw *hw; 3814 uint32_t ctrl; 3815 uint16_t phy_ctrl; 3816 3817 hw = &Adapter->Shared; 3818 3819 /* Disable Smart Power Down */ 3820 phy_spd_state(hw, B_FALSE); 3821 3822 phy_ctrl = (MII_CR_FULL_DUPLEX | 3823 MII_CR_SPEED_100); 3824 3825 /* Force 100/FD, reset PHY */ 3826 e1000_write_phy_reg(hw, PHY_CTRL, 3827 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 3828 msec_delay(10); 3829 3830 /* Force 100/FD */ 3831 e1000_write_phy_reg(hw, PHY_CTRL, 3832 phy_ctrl); /* 0x2100 */ 3833 msec_delay(10); 3834 3835 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3836 ctrl = E1000_READ_REG(hw, CTRL); 3837 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3838 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3839 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3840 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3841 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 3842 E1000_CTRL_FD); /* Force Duplex to FULL */ 3843 3844 E1000_WRITE_REG(hw, CTRL, ctrl); 3845 } 3846 3847 static void 3848 e1000g_set_external_loopback_10(struct e1000g *Adapter) 3849 { 3850 struct e1000_hw *hw; 3851 uint32_t ctrl; 3852 uint16_t phy_ctrl; 3853 3854 hw = &Adapter->Shared; 3855 3856 /* Disable Smart Power Down */ 3857 phy_spd_state(hw, B_FALSE); 3858 3859 phy_ctrl = (MII_CR_FULL_DUPLEX | 3860 MII_CR_SPEED_10); 3861 3862 /* Force 10/FD, reset PHY */ 3863 e1000_write_phy_reg(hw, PHY_CTRL, 3864 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 3865 msec_delay(10); 3866 3867 /* Force 10/FD */ 3868 e1000_write_phy_reg(hw, PHY_CTRL, 3869 phy_ctrl); /* 0x0100 */ 3870 msec_delay(10); 3871 3872 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3873 ctrl = E1000_READ_REG(hw, CTRL); 3874 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3875 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3876 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3877 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3878 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 3879 E1000_CTRL_FD); /* Force Duplex to FULL */ 3880 3881 E1000_WRITE_REG(hw, CTRL, ctrl); 3882 } 3883 3884 #ifdef __sparc 3885 static boolean_t 3886 e1000g_find_mac_address(struct e1000g *Adapter) 3887 { 3888 uchar_t *bytes; 3889 struct ether_addr sysaddr; 3890 uint_t nelts; 3891 int err; 3892 boolean_t found = B_FALSE; 3893 3894 /* 3895 * The "vendor's factory-set address" may already have 3896 * been extracted from the chip, but if the property 3897 * "local-mac-address" is set we use that instead. 3898 * 3899 * We check whether it looks like an array of 6 3900 * bytes (which it should, if OBP set it). If we can't 3901 * make sense of it this way, we'll ignore it. 3902 */ 3903 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3904 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3905 if (err == DDI_PROP_SUCCESS) { 3906 if (nelts == ETHERADDRL) { 3907 while (nelts--) 3908 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3909 found = B_TRUE; 3910 } 3911 ddi_prop_free(bytes); 3912 } 3913 3914 /* 3915 * Look up the OBP property "local-mac-address?". If the user has set 3916 * 'local-mac-address? = false', use "the system address" instead. 3917 */ 3918 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 3919 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3920 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3921 if (localetheraddr(NULL, &sysaddr) != 0) { 3922 bcopy(&sysaddr, Adapter->Shared.mac_addr, 3923 ETHERADDRL); 3924 found = B_TRUE; 3925 } 3926 } 3927 ddi_prop_free(bytes); 3928 } 3929 3930 /* 3931 * Finally(!), if there's a valid "mac-address" property (created 3932 * if we netbooted from this interface), we must use this instead 3933 * of any of the above to ensure that the NFS/install server doesn't 3934 * get confused by the address changing as Solaris takes over! 3935 */ 3936 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3937 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3938 if (err == DDI_PROP_SUCCESS) { 3939 if (nelts == ETHERADDRL) { 3940 while (nelts--) 3941 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3942 found = B_TRUE; 3943 } 3944 ddi_prop_free(bytes); 3945 } 3946 3947 if (found) { 3948 bcopy(Adapter->Shared.mac_addr, Adapter->Shared.perm_mac_addr, 3949 ETHERADDRL); 3950 } 3951 3952 return (found); 3953 } 3954 #endif 3955 3956 static int 3957 e1000g_add_intrs(struct e1000g *Adapter) 3958 { 3959 dev_info_t *devinfo; 3960 int intr_types; 3961 int rc; 3962 3963 devinfo = Adapter->dip; 3964 3965 /* Get supported interrupt types */ 3966 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3967 3968 if (rc != DDI_SUCCESS) { 3969 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3970 "Get supported interrupt types failed: %d\n", rc); 3971 return (DDI_FAILURE); 3972 } 3973 3974 /* 3975 * Based on Intel Technical Advisory document (TA-160), there are some 3976 * cases where some older Intel PCI-X NICs may "advertise" to the OS 3977 * that it supports MSI, but in fact has problems. 3978 * So we should only enable MSI for PCI-E NICs and disable MSI for old 3979 * PCI/PCI-X NICs. 3980 */ 3981 if (Adapter->Shared.mac_type < e1000_82571) 3982 Adapter->msi_enabled = B_FALSE; 3983 3984 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 3985 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 3986 3987 if (rc != DDI_SUCCESS) { 3988 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3989 "Add MSI failed, trying Legacy interrupts\n"); 3990 } else { 3991 Adapter->intr_type = DDI_INTR_TYPE_MSI; 3992 } 3993 } 3994 3995 if ((Adapter->intr_type == 0) && 3996 (intr_types & DDI_INTR_TYPE_FIXED)) { 3997 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 3998 3999 if (rc != DDI_SUCCESS) { 4000 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 4001 "Add Legacy interrupts failed\n"); 4002 return (DDI_FAILURE); 4003 } 4004 4005 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4006 } 4007 4008 if (Adapter->intr_type == 0) { 4009 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 4010 "No interrupts registered\n"); 4011 return (DDI_FAILURE); 4012 } 4013 4014 return (DDI_SUCCESS); 4015 } 4016 4017 /* 4018 * e1000g_intr_add() handles MSI/Legacy interrupts 4019 */ 4020 static int 4021 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4022 { 4023 dev_info_t *devinfo; 4024 int count, avail, actual; 4025 int x, y, rc, inum = 0; 4026 int flag; 4027 ddi_intr_handler_t *intr_handler; 4028 4029 devinfo = Adapter->dip; 4030 4031 /* get number of interrupts */ 4032 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4033 if ((rc != DDI_SUCCESS) || (count == 0)) { 4034 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4035 "Get interrupt number failed. Return: %d, count: %d\n", 4036 rc, count); 4037 return (DDI_FAILURE); 4038 } 4039 4040 /* get number of available interrupts */ 4041 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4042 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4043 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4044 "Get interrupt available number failed. " 4045 "Return: %d, available: %d\n", rc, avail); 4046 return (DDI_FAILURE); 4047 } 4048 4049 if (avail < count) { 4050 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4051 "Interrupts count: %d, available: %d\n", 4052 count, avail); 4053 } 4054 4055 /* Allocate an array of interrupt handles */ 4056 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4057 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4058 4059 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4060 flag = DDI_INTR_ALLOC_NORMAL; 4061 4062 /* call ddi_intr_alloc() */ 4063 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 4064 count, &actual, flag); 4065 4066 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4067 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4068 "Allocate interrupts failed: %d\n", rc); 4069 4070 kmem_free(Adapter->htable, Adapter->intr_size); 4071 return (DDI_FAILURE); 4072 } 4073 4074 if (actual < count) { 4075 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4076 "Interrupts requested: %d, received: %d\n", 4077 count, actual); 4078 } 4079 4080 Adapter->intr_cnt = actual; 4081 4082 /* Get priority for first msi, assume remaining are all the same */ 4083 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 4084 4085 if (rc != DDI_SUCCESS) { 4086 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4087 "Get interrupt priority failed: %d\n", rc); 4088 4089 /* Free already allocated intr */ 4090 for (y = 0; y < actual; y++) 4091 (void) ddi_intr_free(Adapter->htable[y]); 4092 4093 kmem_free(Adapter->htable, Adapter->intr_size); 4094 return (DDI_FAILURE); 4095 } 4096 4097 /* 4098 * In Legacy Interrupt mode, for PCI-Express adapters, we should 4099 * use the interrupt service routine e1000g_intr_pciexpress() 4100 * to avoid interrupt stealing when sharing interrupt with other 4101 * devices. 4102 */ 4103 if (Adapter->Shared.mac_type < e1000_82571) 4104 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 4105 else 4106 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 4107 4108 /* Call ddi_intr_add_handler() */ 4109 for (x = 0; x < actual; x++) { 4110 rc = ddi_intr_add_handler(Adapter->htable[x], 4111 intr_handler, (caddr_t)Adapter, NULL); 4112 4113 if (rc != DDI_SUCCESS) { 4114 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4115 "Add interrupt handler failed: %d\n", rc); 4116 4117 /* Remove already added handler */ 4118 for (y = 0; y < x; y++) 4119 (void) ddi_intr_remove_handler( 4120 Adapter->htable[y]); 4121 4122 /* Free already allocated intr */ 4123 for (y = 0; y < actual; y++) 4124 (void) ddi_intr_free(Adapter->htable[y]); 4125 4126 kmem_free(Adapter->htable, Adapter->intr_size); 4127 return (DDI_FAILURE); 4128 } 4129 } 4130 4131 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 4132 4133 if (rc != DDI_SUCCESS) { 4134 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4135 "Get interrupt cap failed: %d\n", rc); 4136 4137 /* Free already allocated intr */ 4138 for (y = 0; y < actual; y++) { 4139 (void) ddi_intr_remove_handler(Adapter->htable[y]); 4140 (void) ddi_intr_free(Adapter->htable[y]); 4141 } 4142 4143 kmem_free(Adapter->htable, Adapter->intr_size); 4144 return (DDI_FAILURE); 4145 } 4146 4147 return (DDI_SUCCESS); 4148 } 4149 4150 static int 4151 e1000g_rem_intrs(struct e1000g *Adapter) 4152 { 4153 int x; 4154 int rc; 4155 4156 for (x = 0; x < Adapter->intr_cnt; x++) { 4157 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4158 if (rc != DDI_SUCCESS) { 4159 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4160 "Remove intr handler failed: %d\n", rc); 4161 return (DDI_FAILURE); 4162 } 4163 4164 rc = ddi_intr_free(Adapter->htable[x]); 4165 if (rc != DDI_SUCCESS) { 4166 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4167 "Free intr failed: %d\n", rc); 4168 return (DDI_FAILURE); 4169 } 4170 } 4171 4172 kmem_free(Adapter->htable, Adapter->intr_size); 4173 4174 return (DDI_SUCCESS); 4175 } 4176 4177 static int 4178 e1000g_enable_intrs(struct e1000g *Adapter) 4179 { 4180 int x; 4181 int rc; 4182 4183 /* Enable interrupts */ 4184 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4185 /* Call ddi_intr_block_enable() for MSI */ 4186 rc = ddi_intr_block_enable(Adapter->htable, 4187 Adapter->intr_cnt); 4188 if (rc != DDI_SUCCESS) { 4189 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4190 "Enable block intr failed: %d\n", rc); 4191 return (DDI_FAILURE); 4192 } 4193 } else { 4194 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4195 for (x = 0; x < Adapter->intr_cnt; x++) { 4196 rc = ddi_intr_enable(Adapter->htable[x]); 4197 if (rc != DDI_SUCCESS) { 4198 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4199 "Enable intr failed: %d\n", rc); 4200 return (DDI_FAILURE); 4201 } 4202 } 4203 } 4204 4205 return (DDI_SUCCESS); 4206 } 4207 4208 static int 4209 e1000g_disable_intrs(struct e1000g *Adapter) 4210 { 4211 int x; 4212 int rc; 4213 4214 /* Disable all interrupts */ 4215 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4216 rc = ddi_intr_block_disable(Adapter->htable, 4217 Adapter->intr_cnt); 4218 if (rc != DDI_SUCCESS) { 4219 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4220 "Disable block intr failed: %d\n", rc); 4221 return (DDI_FAILURE); 4222 } 4223 } else { 4224 for (x = 0; x < Adapter->intr_cnt; x++) { 4225 rc = ddi_intr_disable(Adapter->htable[x]); 4226 if (rc != DDI_SUCCESS) { 4227 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4228 "Disable intr failed: %d\n", rc); 4229 return (DDI_FAILURE); 4230 } 4231 } 4232 } 4233 4234 return (DDI_SUCCESS); 4235 } 4236 4237 /* 4238 * phy_spd_state - set smart-power-down (SPD) state 4239 * 4240 * This only acts on the 82541/47 family and the 82571/72 family. 4241 * For any others, return without doing anything. 4242 */ 4243 void 4244 phy_spd_state(struct e1000_hw *hw, boolean_t enable) 4245 { 4246 int32_t offset; /* offset to register */ 4247 uint16_t spd_bit; /* bit to be set */ 4248 uint16_t reg; /* register contents */ 4249 4250 switch (hw->mac_type) { 4251 case e1000_82541: 4252 case e1000_82547: 4253 case e1000_82541_rev_2: 4254 case e1000_82547_rev_2: 4255 offset = IGP01E1000_GMII_FIFO; 4256 spd_bit = IGP01E1000_GMII_SPD; 4257 break; 4258 case e1000_82571: 4259 case e1000_82572: 4260 offset = IGP02E1000_PHY_POWER_MGMT; 4261 spd_bit = IGP02E1000_PM_SPD; 4262 break; 4263 default: 4264 return; /* no action */ 4265 } 4266 4267 e1000_read_phy_reg(hw, offset, ®); 4268 4269 if (enable) 4270 reg |= spd_bit; /* enable: set the spd bit */ 4271 else 4272 reg &= ~spd_bit; /* disable: clear the spd bit */ 4273 4274 e1000_write_phy_reg(hw, offset, reg); 4275 } 4276 4277 /* 4278 * The real intent of this routine is to return the value from pci-e 4279 * config space at offset reg into the capability space. 4280 * ICH devices are "PCI Express"-ish. They have a configuration space, 4281 * but do not contain PCI Express Capability registers, so this returns 4282 * the equivalent of "not supported" 4283 */ 4284 int32_t 4285 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4286 { 4287 *value = pci_config_get16(((struct e1000g_osdep *)hw->back)->handle, 4288 PCI_EX_CONF_CAP + reg); 4289 4290 return (0); 4291 } 4292 4293 /* 4294 * Enables PCI-Express master access. 4295 * 4296 * hw: Struct containing variables accessed by shared code 4297 * 4298 * returns: - none. 4299 */ 4300 void 4301 e1000_enable_pciex_master(struct e1000_hw *hw) 4302 { 4303 uint32_t ctrl; 4304 4305 if (hw->bus_type != e1000_bus_type_pci_express) 4306 return; 4307 4308 ctrl = E1000_READ_REG(hw, CTRL); 4309 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 4310 E1000_WRITE_REG(hw, CTRL, ctrl); 4311 } 4312