1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.2.14"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 68 #pragma inline(e1000g_get_itr) 69 static int e1000g_init(struct e1000g *); 70 static int e1000g_start(struct e1000g *, boolean_t); 71 static void e1000g_stop(struct e1000g *, boolean_t); 72 static int e1000g_m_start(void *); 73 static void e1000g_m_stop(void *); 74 static int e1000g_m_promisc(void *, boolean_t); 75 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 76 static int e1000g_m_unicst(void *, const uint8_t *); 77 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 78 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 79 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 80 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 81 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 82 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 83 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 84 uint_t, const void *); 85 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 86 uint_t, uint_t, void *, uint_t *); 87 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 88 const void *); 89 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 90 uint_t, void *, uint_t *); 91 static void e1000g_init_locks(struct e1000g *); 92 static void e1000g_destroy_locks(struct e1000g *); 93 static int e1000g_identify_hardware(struct e1000g *); 94 static int e1000g_regs_map(struct e1000g *); 95 static int e1000g_set_driver_params(struct e1000g *); 96 static void e1000g_set_bufsize(struct e1000g *); 97 static int e1000g_register_mac(struct e1000g *); 98 static boolean_t e1000g_rx_drain(struct e1000g *); 99 static boolean_t e1000g_tx_drain(struct e1000g *); 100 static void e1000g_init_unicst(struct e1000g *); 101 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 102 103 /* 104 * Local routines 105 */ 106 static boolean_t e1000g_reset_adapter(struct e1000g *); 107 static void e1000g_tx_clean(struct e1000g *); 108 static void e1000g_rx_clean(struct e1000g *); 109 static void e1000g_link_timer(void *); 110 static void e1000g_local_timer(void *); 111 static boolean_t e1000g_link_check(struct e1000g *); 112 static boolean_t e1000g_stall_check(struct e1000g *); 113 static void e1000g_smartspeed(struct e1000g *); 114 static void e1000g_get_conf(struct e1000g *); 115 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 116 static void enable_watchdog_timer(struct e1000g *); 117 static void disable_watchdog_timer(struct e1000g *); 118 static void start_watchdog_timer(struct e1000g *); 119 static void restart_watchdog_timer(struct e1000g *); 120 static void stop_watchdog_timer(struct e1000g *); 121 static void stop_link_timer(struct e1000g *); 122 static void stop_82547_timer(e1000g_tx_ring_t *); 123 static void e1000g_force_speed_duplex(struct e1000g *); 124 static void e1000g_get_max_frame_size(struct e1000g *); 125 static boolean_t is_valid_mac_addr(uint8_t *); 126 static void e1000g_unattach(dev_info_t *, struct e1000g *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 154 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 155 const void *impl_data); 156 static void e1000g_fm_init(struct e1000g *Adapter); 157 static void e1000g_fm_fini(struct e1000g *Adapter); 158 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 159 static void e1000g_param_sync(struct e1000g *); 160 static void e1000g_get_driver_control(struct e1000_hw *); 161 static void e1000g_release_driver_control(struct e1000_hw *); 162 static void e1000g_restore_promisc(struct e1000g *Adapter); 163 164 mac_priv_prop_t e1000g_priv_props[] = { 165 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 166 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 167 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 168 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 169 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 170 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 171 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 172 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 173 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 174 {"_intr_adaptive", MAC_PROP_PERM_RW}, 175 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 176 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 177 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 178 {"_tx_recycle_num", MAC_PROP_PERM_RW} 179 }; 180 #define E1000G_MAX_PRIV_PROPS \ 181 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 182 183 184 static struct cb_ops cb_ws_ops = { 185 nulldev, /* cb_open */ 186 nulldev, /* cb_close */ 187 nodev, /* cb_strategy */ 188 nodev, /* cb_print */ 189 nodev, /* cb_dump */ 190 nodev, /* cb_read */ 191 nodev, /* cb_write */ 192 nodev, /* cb_ioctl */ 193 nodev, /* cb_devmap */ 194 nodev, /* cb_mmap */ 195 nodev, /* cb_segmap */ 196 nochpoll, /* cb_chpoll */ 197 ddi_prop_op, /* cb_prop_op */ 198 NULL, /* cb_stream */ 199 D_MP | D_HOTPLUG, /* cb_flag */ 200 CB_REV, /* cb_rev */ 201 nodev, /* cb_aread */ 202 nodev /* cb_awrite */ 203 }; 204 205 static struct dev_ops ws_ops = { 206 DEVO_REV, /* devo_rev */ 207 0, /* devo_refcnt */ 208 NULL, /* devo_getinfo */ 209 nulldev, /* devo_identify */ 210 nulldev, /* devo_probe */ 211 e1000g_attach, /* devo_attach */ 212 e1000g_detach, /* devo_detach */ 213 nodev, /* devo_reset */ 214 &cb_ws_ops, /* devo_cb_ops */ 215 NULL, /* devo_bus_ops */ 216 ddi_power, /* devo_power */ 217 e1000g_quiesce /* devo_quiesce */ 218 }; 219 220 static struct modldrv modldrv = { 221 &mod_driverops, /* Type of module. This one is a driver */ 222 ident, /* Discription string */ 223 &ws_ops, /* driver ops */ 224 }; 225 226 static struct modlinkage modlinkage = { 227 MODREV_1, &modldrv, NULL 228 }; 229 230 /* Access attributes for register mapping */ 231 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 232 DDI_DEVICE_ATTR_V0, 233 DDI_STRUCTURE_LE_ACC, 234 DDI_STRICTORDER_ACC, 235 DDI_FLAGERR_ACC 236 }; 237 238 #define E1000G_M_CALLBACK_FLAGS \ 239 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 240 241 static mac_callbacks_t e1000g_m_callbacks = { 242 E1000G_M_CALLBACK_FLAGS, 243 e1000g_m_stat, 244 e1000g_m_start, 245 e1000g_m_stop, 246 e1000g_m_promisc, 247 e1000g_m_multicst, 248 e1000g_m_unicst, 249 e1000g_m_tx, 250 NULL, 251 e1000g_m_ioctl, 252 e1000g_m_getcapab, 253 NULL, 254 NULL, 255 e1000g_m_setprop, 256 e1000g_m_getprop 257 }; 258 259 /* 260 * Global variables 261 */ 262 uint32_t e1000g_mblks_pending = 0; 263 /* 264 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 265 * Here we maintain a private dev_info list if e1000g_force_detach is 266 * enabled. If we force the driver to detach while there are still some 267 * rx buffers retained in the upper layer, we have to keep a copy of the 268 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 269 * structure will be freed after the driver is detached. However when we 270 * finally free those rx buffers released by the upper layer, we need to 271 * refer to the dev_info to free the dma buffers. So we save a copy of 272 * the dev_info for this purpose. On x86 platform, we assume this copy 273 * of dev_info is always valid, but on SPARC platform, it could be invalid 274 * after the system board level DR operation. For this reason, the global 275 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 276 */ 277 #ifdef __sparc 278 boolean_t e1000g_force_detach = B_FALSE; 279 #else 280 boolean_t e1000g_force_detach = B_TRUE; 281 #endif 282 private_devi_list_t *e1000g_private_devi_list = NULL; 283 284 /* 285 * The rwlock is defined to protect the whole processing of rx recycling 286 * and the rx packets release in detach processing to make them mutually 287 * exclusive. 288 * The rx recycling processes different rx packets in different threads, 289 * so it will be protected with RW_READER and it won't block any other rx 290 * recycling threads. 291 * While the detach processing will be protected with RW_WRITER to make 292 * it mutually exclusive with the rx recycling. 293 */ 294 krwlock_t e1000g_rx_detach_lock; 295 /* 296 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 297 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 298 * If there are many e1000g instances, the system may run out of DVMA 299 * resources during the initialization of the instances, then the flag will 300 * be changed to "USE_DMA". Because different e1000g instances are initialized 301 * in parallel, we need to use this lock to protect the flag. 302 */ 303 krwlock_t e1000g_dma_type_lock; 304 305 /* 306 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 307 * Based on the information from Intel, the 82546 chipset has some hardware 308 * problem. When one port is being reset and the other port is trying to 309 * access the eeprom, it could cause system hang or panic. To workaround this 310 * hardware problem, we use a global mutex to prevent such operations from 311 * happening simultaneously on different instances. This workaround is applied 312 * to all the devices supported by this driver. 313 */ 314 kmutex_t e1000g_nvm_lock; 315 316 /* 317 * Loadable module configuration entry points for the driver 318 */ 319 320 /* 321 * _init - module initialization 322 */ 323 int 324 _init(void) 325 { 326 int status; 327 328 mac_init_ops(&ws_ops, WSNAME); 329 status = mod_install(&modlinkage); 330 if (status != DDI_SUCCESS) 331 mac_fini_ops(&ws_ops); 332 else { 333 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 334 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 335 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 336 } 337 338 return (status); 339 } 340 341 /* 342 * _fini - module finalization 343 */ 344 int 345 _fini(void) 346 { 347 int status; 348 349 rw_enter(&e1000g_rx_detach_lock, RW_READER); 350 if (e1000g_mblks_pending != 0) { 351 rw_exit(&e1000g_rx_detach_lock); 352 return (EBUSY); 353 } 354 rw_exit(&e1000g_rx_detach_lock); 355 356 status = mod_remove(&modlinkage); 357 if (status == DDI_SUCCESS) { 358 mac_fini_ops(&ws_ops); 359 360 if (e1000g_force_detach) { 361 private_devi_list_t *devi_node; 362 363 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 364 while (e1000g_private_devi_list != NULL) { 365 devi_node = e1000g_private_devi_list; 366 e1000g_private_devi_list = 367 e1000g_private_devi_list->next; 368 369 kmem_free(devi_node->priv_dip, 370 sizeof (struct dev_info)); 371 kmem_free(devi_node, 372 sizeof (private_devi_list_t)); 373 } 374 rw_exit(&e1000g_rx_detach_lock); 375 } 376 377 rw_destroy(&e1000g_rx_detach_lock); 378 rw_destroy(&e1000g_dma_type_lock); 379 mutex_destroy(&e1000g_nvm_lock); 380 } 381 382 return (status); 383 } 384 385 /* 386 * _info - module information 387 */ 388 int 389 _info(struct modinfo *modinfop) 390 { 391 return (mod_info(&modlinkage, modinfop)); 392 } 393 394 /* 395 * e1000g_attach - driver attach 396 * 397 * This function is the device-specific initialization entry 398 * point. This entry point is required and must be written. 399 * The DDI_ATTACH command must be provided in the attach entry 400 * point. When attach() is called with cmd set to DDI_ATTACH, 401 * all normal kernel services (such as kmem_alloc(9F)) are 402 * available for use by the driver. 403 * 404 * The attach() function will be called once for each instance 405 * of the device on the system with cmd set to DDI_ATTACH. 406 * Until attach() succeeds, the only driver entry points which 407 * may be called are open(9E) and getinfo(9E). 408 */ 409 static int 410 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 411 { 412 struct e1000g *Adapter; 413 struct e1000_hw *hw; 414 struct e1000g_osdep *osdep; 415 int instance; 416 417 switch (cmd) { 418 default: 419 e1000g_log(NULL, CE_WARN, 420 "Unsupported command send to e1000g_attach... "); 421 return (DDI_FAILURE); 422 423 case DDI_RESUME: 424 return (e1000g_resume(devinfo)); 425 426 case DDI_ATTACH: 427 break; 428 } 429 430 /* 431 * get device instance number 432 */ 433 instance = ddi_get_instance(devinfo); 434 435 /* 436 * Allocate soft data structure 437 */ 438 Adapter = 439 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 440 441 Adapter->dip = devinfo; 442 Adapter->instance = instance; 443 Adapter->tx_ring->adapter = Adapter; 444 Adapter->rx_ring->adapter = Adapter; 445 446 hw = &Adapter->shared; 447 osdep = &Adapter->osdep; 448 hw->back = osdep; 449 osdep->adapter = Adapter; 450 451 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 452 453 /* 454 * Initialize for fma support 455 */ 456 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 457 0, 0x0f, 458 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 459 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 460 e1000g_fm_init(Adapter); 461 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 462 463 /* 464 * PCI Configure 465 */ 466 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 467 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 468 goto attach_fail; 469 } 470 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 471 472 /* 473 * Setup hardware 474 */ 475 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 476 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 477 goto attach_fail; 478 } 479 480 /* 481 * Map in the device registers. 482 */ 483 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 484 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 485 goto attach_fail; 486 } 487 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 488 489 /* 490 * Initialize driver parameters 491 */ 492 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 493 goto attach_fail; 494 } 495 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 496 497 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 498 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 499 goto attach_fail; 500 } 501 502 /* 503 * Initialize interrupts 504 */ 505 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 506 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 507 goto attach_fail; 508 } 509 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 510 511 /* 512 * Initialize mutex's for this device. 513 * Do this before enabling the interrupt handler and 514 * register the softint to avoid the condition where 515 * interrupt handler can try using uninitialized mutex 516 */ 517 e1000g_init_locks(Adapter); 518 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 519 520 /* 521 * Initialize Driver Counters 522 */ 523 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 524 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 525 goto attach_fail; 526 } 527 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 528 529 /* 530 * Initialize chip hardware and software structures 531 */ 532 if (e1000g_init(Adapter) != DDI_SUCCESS) { 533 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 534 goto attach_fail; 535 } 536 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 537 538 /* 539 * Register the driver to the MAC 540 */ 541 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 542 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 543 goto attach_fail; 544 } 545 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 546 547 /* 548 * Now that mutex locks are initialized, and the chip is also 549 * initialized, enable interrupts. 550 */ 551 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 552 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 553 goto attach_fail; 554 } 555 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 556 557 /* 558 * If e1000g_force_detach is enabled, in global private dip list, 559 * we will create a new entry, which maintains the priv_dip for DR 560 * supports after driver detached. 561 */ 562 if (e1000g_force_detach) { 563 private_devi_list_t *devi_node; 564 565 Adapter->priv_dip = 566 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 567 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 568 sizeof (struct dev_info)); 569 570 devi_node = 571 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 572 573 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 574 devi_node->priv_dip = Adapter->priv_dip; 575 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 576 devi_node->next = e1000g_private_devi_list; 577 e1000g_private_devi_list = devi_node; 578 rw_exit(&e1000g_rx_detach_lock); 579 } 580 581 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 582 583 return (DDI_SUCCESS); 584 585 attach_fail: 586 e1000g_unattach(devinfo, Adapter); 587 return (DDI_FAILURE); 588 } 589 590 static int 591 e1000g_register_mac(struct e1000g *Adapter) 592 { 593 struct e1000_hw *hw = &Adapter->shared; 594 mac_register_t *mac; 595 int err; 596 597 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 598 return (DDI_FAILURE); 599 600 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 601 mac->m_driver = Adapter; 602 mac->m_dip = Adapter->dip; 603 mac->m_src_addr = hw->mac.addr; 604 mac->m_callbacks = &e1000g_m_callbacks; 605 mac->m_min_sdu = 0; 606 mac->m_max_sdu = Adapter->default_mtu; 607 mac->m_margin = VLAN_TAGSZ; 608 mac->m_priv_props = e1000g_priv_props; 609 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 610 611 err = mac_register(mac, &Adapter->mh); 612 mac_free(mac); 613 614 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 615 } 616 617 static int 618 e1000g_identify_hardware(struct e1000g *Adapter) 619 { 620 struct e1000_hw *hw = &Adapter->shared; 621 struct e1000g_osdep *osdep = &Adapter->osdep; 622 623 /* Get the device id */ 624 hw->vendor_id = 625 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 626 hw->device_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 628 hw->revision_id = 629 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 630 hw->subsystem_device_id = 631 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 632 hw->subsystem_vendor_id = 633 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 634 635 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 636 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 637 "MAC type could not be set properly."); 638 return (DDI_FAILURE); 639 } 640 641 return (DDI_SUCCESS); 642 } 643 644 static int 645 e1000g_regs_map(struct e1000g *Adapter) 646 { 647 dev_info_t *devinfo = Adapter->dip; 648 struct e1000_hw *hw = &Adapter->shared; 649 struct e1000g_osdep *osdep = &Adapter->osdep; 650 off_t mem_size; 651 652 /* Get size of adapter register memory */ 653 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 654 DDI_SUCCESS) { 655 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 656 "ddi_dev_regsize for registers failed"); 657 return (DDI_FAILURE); 658 } 659 660 /* Map adapter register memory */ 661 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 662 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 663 &osdep->reg_handle)) != DDI_SUCCESS) { 664 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 665 "ddi_regs_map_setup for registers failed"); 666 goto regs_map_fail; 667 } 668 669 /* ICH needs to map flash memory */ 670 if (hw->mac.type == e1000_ich8lan || 671 hw->mac.type == e1000_ich9lan || 672 hw->mac.type == e1000_ich10lan) { 673 /* get flash size */ 674 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 675 &mem_size) != DDI_SUCCESS) { 676 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 677 "ddi_dev_regsize for ICH flash failed"); 678 goto regs_map_fail; 679 } 680 681 /* map flash in */ 682 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 683 (caddr_t *)&hw->flash_address, 0, 684 mem_size, &e1000g_regs_acc_attr, 685 &osdep->ich_flash_handle) != DDI_SUCCESS) { 686 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 687 "ddi_regs_map_setup for ICH flash failed"); 688 goto regs_map_fail; 689 } 690 } 691 692 return (DDI_SUCCESS); 693 694 regs_map_fail: 695 if (osdep->reg_handle != NULL) 696 ddi_regs_map_free(&osdep->reg_handle); 697 698 return (DDI_FAILURE); 699 } 700 701 static int 702 e1000g_set_driver_params(struct e1000g *Adapter) 703 { 704 struct e1000_hw *hw; 705 uint32_t mem_bar, io_bar, bar64; 706 707 hw = &Adapter->shared; 708 709 /* Set MAC type and initialize hardware functions */ 710 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 711 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 712 "Could not setup hardware functions"); 713 return (DDI_FAILURE); 714 } 715 716 /* Get bus information */ 717 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 718 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 719 "Could not get bus information"); 720 return (DDI_FAILURE); 721 } 722 723 /* get mem_base addr */ 724 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 725 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 726 727 /* get io_base addr */ 728 if (hw->mac.type >= e1000_82544) { 729 if (bar64) { 730 /* IO BAR is different for 64 bit BAR mode */ 731 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 732 PCI_CONF_BASE4); 733 } else { 734 /* normal 32-bit BAR mode */ 735 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 736 PCI_CONF_BASE2); 737 } 738 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 739 } else { 740 /* no I/O access for adapters prior to 82544 */ 741 hw->io_base = 0x0; 742 } 743 744 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 745 746 hw->mac.autoneg_failed = B_TRUE; 747 748 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 749 hw->phy.autoneg_wait_to_complete = B_FALSE; 750 751 /* Adaptive IFS related changes */ 752 hw->mac.adaptive_ifs = B_TRUE; 753 754 /* Enable phy init script for IGP phy of 82541/82547 */ 755 if ((hw->mac.type == e1000_82547) || 756 (hw->mac.type == e1000_82541) || 757 (hw->mac.type == e1000_82547_rev_2) || 758 (hw->mac.type == e1000_82541_rev_2)) 759 e1000_init_script_state_82541(hw, B_TRUE); 760 761 /* Enable the TTL workaround for 82541/82547 */ 762 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 763 764 #ifdef __sparc 765 Adapter->strip_crc = B_TRUE; 766 #else 767 Adapter->strip_crc = B_FALSE; 768 #endif 769 770 /* Get conf file properties */ 771 e1000g_get_conf(Adapter); 772 773 /* Get speed/duplex settings in conf file */ 774 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 775 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 776 e1000g_force_speed_duplex(Adapter); 777 778 /* Get Jumbo Frames settings in conf file */ 779 e1000g_get_max_frame_size(Adapter); 780 781 /* Set Rx/Tx buffer size */ 782 e1000g_set_bufsize(Adapter); 783 784 /* Master Latency Timer */ 785 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 786 787 /* copper options */ 788 if (hw->phy.media_type == e1000_media_type_copper) { 789 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 790 hw->phy.disable_polarity_correction = B_FALSE; 791 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 792 } 793 794 /* The initial link state should be "unknown" */ 795 Adapter->link_state = LINK_STATE_UNKNOWN; 796 797 /* Initialize rx parameters */ 798 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 799 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 800 801 /* Initialize tx parameters */ 802 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 803 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 804 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 805 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 806 807 /* Initialize rx parameters */ 808 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 809 810 return (DDI_SUCCESS); 811 } 812 813 static void 814 e1000g_set_bufsize(struct e1000g *Adapter) 815 { 816 struct e1000_mac_info *mac = &Adapter->shared.mac; 817 uint64_t rx_size; 818 uint64_t tx_size; 819 820 dev_info_t *devinfo = Adapter->dip; 821 #ifdef __sparc 822 ulong_t iommu_pagesize; 823 #endif 824 /* Get the system page size */ 825 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 826 827 #ifdef __sparc 828 iommu_pagesize = dvma_pagesize(devinfo); 829 if (iommu_pagesize != 0) { 830 if (Adapter->sys_page_sz == iommu_pagesize) { 831 if (iommu_pagesize > 0x4000) 832 Adapter->sys_page_sz = 0x4000; 833 } else { 834 if (Adapter->sys_page_sz > iommu_pagesize) 835 Adapter->sys_page_sz = iommu_pagesize; 836 } 837 } 838 if (Adapter->lso_enable) { 839 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 840 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 841 } else { 842 Adapter->dvma_page_num = Adapter->max_frame_size / 843 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 844 } 845 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 846 #endif 847 848 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 849 850 if ((mac->type == e1000_82545) || 851 (mac->type == e1000_82546) || 852 (mac->type == e1000_82546_rev_3)) { 853 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 854 } else { 855 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 856 if ((rx_size > FRAME_SIZE_UPTO_2K) && 857 (rx_size <= FRAME_SIZE_UPTO_4K)) 858 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 859 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 860 (rx_size <= FRAME_SIZE_UPTO_8K)) 861 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 862 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 863 (rx_size <= FRAME_SIZE_UPTO_16K)) 864 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 865 else 866 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 867 } 868 869 tx_size = Adapter->max_frame_size; 870 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 871 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 872 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 873 (tx_size <= FRAME_SIZE_UPTO_8K)) 874 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 875 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 876 (tx_size <= FRAME_SIZE_UPTO_16K)) 877 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 878 else 879 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 880 881 /* 882 * For Wiseman adapters we have an requirement of having receive 883 * buffers aligned at 256 byte boundary. Since Livengood does not 884 * require this and forcing it for all hardwares will have 885 * performance implications, I am making it applicable only for 886 * Wiseman and for Jumbo frames enabled mode as rest of the time, 887 * it is okay to have normal frames...but it does involve a 888 * potential risk where we may loose data if buffer is not 889 * aligned...so all wiseman boards to have 256 byte aligned 890 * buffers 891 */ 892 if (mac->type < e1000_82543) 893 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 894 else if ((mac->type == e1000_82545) || 895 (mac->type == e1000_82546) || 896 (mac->type == e1000_82546_rev_3)) 897 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE_82546; 898 else 899 Adapter->rx_buf_align = 1; 900 } 901 902 /* 903 * e1000g_detach - driver detach 904 * 905 * The detach() function is the complement of the attach routine. 906 * If cmd is set to DDI_DETACH, detach() is used to remove the 907 * state associated with a given instance of a device node 908 * prior to the removal of that instance from the system. 909 * 910 * The detach() function will be called once for each instance 911 * of the device for which there has been a successful attach() 912 * once there are no longer any opens on the device. 913 * 914 * Interrupts routine are disabled, All memory allocated by this 915 * driver are freed. 916 */ 917 static int 918 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 919 { 920 struct e1000g *Adapter; 921 boolean_t rx_drain; 922 923 switch (cmd) { 924 default: 925 return (DDI_FAILURE); 926 927 case DDI_SUSPEND: 928 return (e1000g_suspend(devinfo)); 929 930 case DDI_DETACH: 931 break; 932 } 933 934 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 935 if (Adapter == NULL) 936 return (DDI_FAILURE); 937 938 if (mac_unregister(Adapter->mh) != 0) { 939 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 940 return (DDI_FAILURE); 941 } 942 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 943 944 945 if (Adapter->chip_state != E1000G_STOP) 946 e1000g_stop(Adapter, B_TRUE); 947 948 rx_drain = e1000g_rx_drain(Adapter); 949 950 /* 951 * If e1000g_force_detach is enabled, driver detach is safe. 952 * We will let e1000g_free_priv_devi_node routine determine 953 * whether we need to free the priv_dip entry for current 954 * driver instance. 955 */ 956 if (e1000g_force_detach) { 957 e1000g_free_priv_devi_node(Adapter, rx_drain); 958 } else { 959 if (!rx_drain) 960 return (DDI_FAILURE); 961 } 962 963 e1000g_unattach(devinfo, Adapter); 964 965 return (DDI_SUCCESS); 966 } 967 968 /* 969 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 970 * 971 * If free_flag is true, that indicates the upper layer is not holding 972 * the rx buffers, we could free the priv_dip entry safely. 973 * 974 * Otherwise, we have to keep this entry even after driver detached, 975 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 976 * so that driver could free it while all of rx buffers are returned 977 * by upper layer later. 978 */ 979 static void 980 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 981 { 982 private_devi_list_t *devi_node, *devi_del; 983 984 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 985 ASSERT(e1000g_private_devi_list != NULL); 986 ASSERT(Adapter->priv_dip != NULL); 987 988 devi_node = e1000g_private_devi_list; 989 if (devi_node->priv_dip == Adapter->priv_dip) { 990 if (free_flag) { 991 e1000g_private_devi_list = 992 devi_node->next; 993 kmem_free(devi_node->priv_dip, 994 sizeof (struct dev_info)); 995 kmem_free(devi_node, 996 sizeof (private_devi_list_t)); 997 } else { 998 ASSERT(e1000g_mblks_pending != 0); 999 devi_node->flag = 1000 E1000G_PRIV_DEVI_DETACH; 1001 } 1002 rw_exit(&e1000g_rx_detach_lock); 1003 return; 1004 } 1005 1006 devi_node = e1000g_private_devi_list; 1007 while (devi_node->next != NULL) { 1008 if (devi_node->next->priv_dip == Adapter->priv_dip) { 1009 if (free_flag) { 1010 devi_del = devi_node->next; 1011 devi_node->next = devi_del->next; 1012 kmem_free(devi_del->priv_dip, 1013 sizeof (struct dev_info)); 1014 kmem_free(devi_del, 1015 sizeof (private_devi_list_t)); 1016 } else { 1017 ASSERT(e1000g_mblks_pending != 0); 1018 devi_node->next->flag = 1019 E1000G_PRIV_DEVI_DETACH; 1020 } 1021 break; 1022 } 1023 devi_node = devi_node->next; 1024 } 1025 rw_exit(&e1000g_rx_detach_lock); 1026 } 1027 1028 static void 1029 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1030 { 1031 int result; 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1034 (void) e1000g_disable_intrs(Adapter); 1035 } 1036 1037 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1038 (void) mac_unregister(Adapter->mh); 1039 } 1040 1041 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1042 (void) e1000g_rem_intrs(Adapter); 1043 } 1044 1045 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1046 (void) ddi_prop_remove_all(devinfo); 1047 } 1048 1049 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1050 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1051 } 1052 1053 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1054 stop_link_timer(Adapter); 1055 1056 mutex_enter(&e1000g_nvm_lock); 1057 result = e1000_reset_hw(&Adapter->shared); 1058 mutex_exit(&e1000g_nvm_lock); 1059 1060 if (result != E1000_SUCCESS) { 1061 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1062 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1063 } 1064 } 1065 1066 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1067 if (Adapter->osdep.reg_handle != NULL) 1068 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1069 if (Adapter->osdep.ich_flash_handle != NULL) 1070 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1071 } 1072 1073 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1074 if (Adapter->osdep.cfg_handle != NULL) 1075 pci_config_teardown(&Adapter->osdep.cfg_handle); 1076 } 1077 1078 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1079 e1000g_destroy_locks(Adapter); 1080 } 1081 1082 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1083 e1000g_fm_fini(Adapter); 1084 } 1085 1086 e1000_remove_device(&Adapter->shared); 1087 1088 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1089 1090 /* 1091 * Another hotplug spec requirement, 1092 * run ddi_set_driver_private(devinfo, null); 1093 */ 1094 ddi_set_driver_private(devinfo, NULL); 1095 } 1096 1097 static void 1098 e1000g_init_locks(struct e1000g *Adapter) 1099 { 1100 e1000g_tx_ring_t *tx_ring; 1101 e1000g_rx_ring_t *rx_ring; 1102 1103 rw_init(&Adapter->chip_lock, NULL, 1104 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1105 mutex_init(&Adapter->link_lock, NULL, 1106 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1107 mutex_init(&Adapter->watchdog_lock, NULL, 1108 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1109 1110 tx_ring = Adapter->tx_ring; 1111 1112 mutex_init(&tx_ring->tx_lock, NULL, 1113 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1114 mutex_init(&tx_ring->usedlist_lock, NULL, 1115 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1116 mutex_init(&tx_ring->freelist_lock, NULL, 1117 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1118 1119 rx_ring = Adapter->rx_ring; 1120 1121 mutex_init(&rx_ring->rx_lock, NULL, 1122 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1123 mutex_init(&rx_ring->freelist_lock, NULL, 1124 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1125 } 1126 1127 static void 1128 e1000g_destroy_locks(struct e1000g *Adapter) 1129 { 1130 e1000g_tx_ring_t *tx_ring; 1131 e1000g_rx_ring_t *rx_ring; 1132 1133 tx_ring = Adapter->tx_ring; 1134 mutex_destroy(&tx_ring->tx_lock); 1135 mutex_destroy(&tx_ring->usedlist_lock); 1136 mutex_destroy(&tx_ring->freelist_lock); 1137 1138 rx_ring = Adapter->rx_ring; 1139 mutex_destroy(&rx_ring->rx_lock); 1140 mutex_destroy(&rx_ring->freelist_lock); 1141 1142 mutex_destroy(&Adapter->link_lock); 1143 mutex_destroy(&Adapter->watchdog_lock); 1144 rw_destroy(&Adapter->chip_lock); 1145 } 1146 1147 static int 1148 e1000g_resume(dev_info_t *devinfo) 1149 { 1150 struct e1000g *Adapter; 1151 1152 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1153 if (Adapter == NULL) 1154 return (DDI_FAILURE); 1155 1156 if (e1000g_start(Adapter, B_TRUE)) 1157 return (DDI_FAILURE); 1158 1159 return (DDI_SUCCESS); 1160 } 1161 1162 static int 1163 e1000g_suspend(dev_info_t *devinfo) 1164 { 1165 struct e1000g *Adapter; 1166 1167 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1168 if (Adapter == NULL) 1169 return (DDI_FAILURE); 1170 1171 e1000g_stop(Adapter, B_TRUE); 1172 1173 return (DDI_SUCCESS); 1174 } 1175 1176 static int 1177 e1000g_init(struct e1000g *Adapter) 1178 { 1179 uint32_t pba; 1180 uint32_t high_water; 1181 struct e1000_hw *hw; 1182 clock_t link_timeout; 1183 int result; 1184 1185 hw = &Adapter->shared; 1186 1187 rw_enter(&Adapter->chip_lock, RW_WRITER); 1188 1189 /* 1190 * reset to put the hardware in a known state 1191 * before we try to do anything with the eeprom 1192 */ 1193 mutex_enter(&e1000g_nvm_lock); 1194 result = e1000_reset_hw(hw); 1195 mutex_exit(&e1000g_nvm_lock); 1196 1197 if (result != E1000_SUCCESS) { 1198 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1199 goto init_fail; 1200 } 1201 1202 mutex_enter(&e1000g_nvm_lock); 1203 result = e1000_validate_nvm_checksum(hw); 1204 if (result < E1000_SUCCESS) { 1205 /* 1206 * Some PCI-E parts fail the first check due to 1207 * the link being in sleep state. Call it again, 1208 * if it fails a second time its a real issue. 1209 */ 1210 result = e1000_validate_nvm_checksum(hw); 1211 } 1212 mutex_exit(&e1000g_nvm_lock); 1213 1214 if (result < E1000_SUCCESS) { 1215 e1000g_log(Adapter, CE_WARN, 1216 "Invalid NVM checksum. Please contact " 1217 "the vendor to update the NVM."); 1218 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1219 goto init_fail; 1220 } 1221 1222 result = 0; 1223 #ifdef __sparc 1224 /* 1225 * First, we try to get the local ethernet address from OBP. If 1226 * failed, then we get it from the EEPROM of NIC card. 1227 */ 1228 result = e1000g_find_mac_address(Adapter); 1229 #endif 1230 /* Get the local ethernet address. */ 1231 if (!result) { 1232 mutex_enter(&e1000g_nvm_lock); 1233 result = e1000_read_mac_addr(hw); 1234 mutex_exit(&e1000g_nvm_lock); 1235 } 1236 1237 if (result < E1000_SUCCESS) { 1238 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1239 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1240 goto init_fail; 1241 } 1242 1243 /* check for valid mac address */ 1244 if (!is_valid_mac_addr(hw->mac.addr)) { 1245 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1246 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1247 goto init_fail; 1248 } 1249 1250 /* Set LAA state for 82571 chipset */ 1251 e1000_set_laa_state_82571(hw, B_TRUE); 1252 1253 /* Master Latency Timer implementation */ 1254 if (Adapter->master_latency_timer) { 1255 pci_config_put8(Adapter->osdep.cfg_handle, 1256 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1257 } 1258 1259 if (hw->mac.type < e1000_82547) { 1260 /* 1261 * Total FIFO is 64K 1262 */ 1263 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1264 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1265 else 1266 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1267 } else if ((hw->mac.type == e1000_82571) || 1268 (hw->mac.type == e1000_82572) || 1269 (hw->mac.type == e1000_80003es2lan)) { 1270 /* 1271 * Total FIFO is 48K 1272 */ 1273 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1274 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1275 else 1276 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1277 } else if (hw->mac.type == e1000_82573) { 1278 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1279 } else if (hw->mac.type == e1000_82574) { 1280 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1281 pba = E1000_READ_REG(hw, E1000_PBA); 1282 } else if (hw->mac.type == e1000_ich8lan) { 1283 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1284 } else if (hw->mac.type == e1000_ich9lan) { 1285 pba = E1000_PBA_10K; 1286 } else if (hw->mac.type == e1000_ich10lan) { 1287 pba = E1000_PBA_10K; 1288 } else { 1289 /* 1290 * Total FIFO is 40K 1291 */ 1292 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1293 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1294 else 1295 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1296 } 1297 E1000_WRITE_REG(hw, E1000_PBA, pba); 1298 1299 /* 1300 * These parameters set thresholds for the adapter's generation(Tx) 1301 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1302 * settings. Flow control is enabled or disabled in the configuration 1303 * file. 1304 * High-water mark is set down from the top of the rx fifo (not 1305 * sensitive to max_frame_size) and low-water is set just below 1306 * high-water mark. 1307 * The high water mark must be low enough to fit one full frame above 1308 * it in the rx FIFO. Should be the lower of: 1309 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1310 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1311 * Rx FIFO size minus one full frame. 1312 */ 1313 high_water = min(((pba << 10) * 9 / 10), 1314 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan || 1315 hw->mac.type == e1000_ich10lan) ? 1316 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1317 ((pba << 10) - Adapter->max_frame_size))); 1318 1319 hw->fc.high_water = high_water & 0xFFF8; 1320 hw->fc.low_water = hw->fc.high_water - 8; 1321 1322 if (hw->mac.type == e1000_80003es2lan) 1323 hw->fc.pause_time = 0xFFFF; 1324 else 1325 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1326 hw->fc.send_xon = B_TRUE; 1327 1328 /* 1329 * Reset the adapter hardware the second time. 1330 */ 1331 mutex_enter(&e1000g_nvm_lock); 1332 result = e1000_reset_hw(hw); 1333 mutex_exit(&e1000g_nvm_lock); 1334 1335 if (result != E1000_SUCCESS) { 1336 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1337 goto init_fail; 1338 } 1339 1340 /* disable wakeup control by default */ 1341 if (hw->mac.type >= e1000_82544) 1342 E1000_WRITE_REG(hw, E1000_WUC, 0); 1343 1344 /* 1345 * MWI should be disabled on 82546. 1346 */ 1347 if (hw->mac.type == e1000_82546) 1348 e1000_pci_clear_mwi(hw); 1349 else 1350 e1000_pci_set_mwi(hw); 1351 1352 /* 1353 * Configure/Initialize hardware 1354 */ 1355 mutex_enter(&e1000g_nvm_lock); 1356 result = e1000_init_hw(hw); 1357 mutex_exit(&e1000g_nvm_lock); 1358 1359 if (result < E1000_SUCCESS) { 1360 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1361 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1362 goto init_fail; 1363 } 1364 1365 /* 1366 * Restore LED settings to the default from EEPROM 1367 * to meet the standard for Sun platforms. 1368 */ 1369 (void) e1000_cleanup_led(hw); 1370 1371 /* Disable Smart Power Down */ 1372 phy_spd_state(hw, B_FALSE); 1373 1374 /* Make sure driver has control */ 1375 e1000g_get_driver_control(hw); 1376 1377 /* 1378 * Initialize unicast addresses. 1379 */ 1380 e1000g_init_unicst(Adapter); 1381 1382 /* 1383 * Setup and initialize the mctable structures. After this routine 1384 * completes Multicast table will be set 1385 */ 1386 e1000g_setup_multicast(Adapter); 1387 msec_delay(5); 1388 1389 /* 1390 * Implement Adaptive IFS 1391 */ 1392 e1000_reset_adaptive(hw); 1393 1394 /* Setup Interrupt Throttling Register */ 1395 if (hw->mac.type >= e1000_82540) { 1396 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1397 } else 1398 Adapter->intr_adaptive = B_FALSE; 1399 1400 /* Start the timer for link setup */ 1401 if (hw->mac.autoneg) 1402 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1403 else 1404 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1405 1406 mutex_enter(&Adapter->link_lock); 1407 if (hw->phy.autoneg_wait_to_complete) { 1408 Adapter->link_complete = B_TRUE; 1409 } else { 1410 Adapter->link_complete = B_FALSE; 1411 Adapter->link_tid = timeout(e1000g_link_timer, 1412 (void *)Adapter, link_timeout); 1413 } 1414 mutex_exit(&Adapter->link_lock); 1415 1416 /* Enable PCI-Ex master */ 1417 if (hw->bus.type == e1000_bus_type_pci_express) { 1418 e1000_enable_pciex_master(hw); 1419 } 1420 1421 /* Save the state of the phy */ 1422 e1000g_get_phy_state(Adapter); 1423 1424 e1000g_param_sync(Adapter); 1425 1426 Adapter->init_count++; 1427 1428 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1429 goto init_fail; 1430 } 1431 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1432 goto init_fail; 1433 } 1434 1435 rw_exit(&Adapter->chip_lock); 1436 1437 return (DDI_SUCCESS); 1438 1439 init_fail: 1440 rw_exit(&Adapter->chip_lock); 1441 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1442 return (DDI_FAILURE); 1443 } 1444 1445 /* 1446 * Check if the link is up 1447 */ 1448 static boolean_t 1449 e1000g_link_up(struct e1000g *Adapter) 1450 { 1451 struct e1000_hw *hw; 1452 boolean_t link_up; 1453 1454 hw = &Adapter->shared; 1455 1456 (void) e1000_check_for_link(hw); 1457 1458 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1459 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1460 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1461 (hw->mac.serdes_has_link))) { 1462 link_up = B_TRUE; 1463 } else { 1464 link_up = B_FALSE; 1465 } 1466 1467 return (link_up); 1468 } 1469 1470 static void 1471 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1472 { 1473 struct iocblk *iocp; 1474 struct e1000g *e1000gp; 1475 enum ioc_reply status; 1476 1477 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1478 iocp->ioc_error = 0; 1479 e1000gp = (struct e1000g *)arg; 1480 1481 ASSERT(e1000gp); 1482 if (e1000gp == NULL) { 1483 miocnak(q, mp, 0, EINVAL); 1484 return; 1485 } 1486 1487 switch (iocp->ioc_cmd) { 1488 1489 case LB_GET_INFO_SIZE: 1490 case LB_GET_INFO: 1491 case LB_GET_MODE: 1492 case LB_SET_MODE: 1493 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1494 break; 1495 1496 1497 #ifdef E1000G_DEBUG 1498 case E1000G_IOC_REG_PEEK: 1499 case E1000G_IOC_REG_POKE: 1500 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1501 break; 1502 case E1000G_IOC_CHIP_RESET: 1503 e1000gp->reset_count++; 1504 if (e1000g_reset_adapter(e1000gp)) 1505 status = IOC_ACK; 1506 else 1507 status = IOC_INVAL; 1508 break; 1509 #endif 1510 default: 1511 status = IOC_INVAL; 1512 break; 1513 } 1514 1515 /* 1516 * Decide how to reply 1517 */ 1518 switch (status) { 1519 default: 1520 case IOC_INVAL: 1521 /* 1522 * Error, reply with a NAK and EINVAL or the specified error 1523 */ 1524 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1525 EINVAL : iocp->ioc_error); 1526 break; 1527 1528 case IOC_DONE: 1529 /* 1530 * OK, reply already sent 1531 */ 1532 break; 1533 1534 case IOC_ACK: 1535 /* 1536 * OK, reply with an ACK 1537 */ 1538 miocack(q, mp, 0, 0); 1539 break; 1540 1541 case IOC_REPLY: 1542 /* 1543 * OK, send prepared reply as ACK or NAK 1544 */ 1545 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1546 M_IOCACK : M_IOCNAK; 1547 qreply(q, mp); 1548 break; 1549 } 1550 } 1551 1552 static int 1553 e1000g_m_start(void *arg) 1554 { 1555 struct e1000g *Adapter = (struct e1000g *)arg; 1556 1557 return (e1000g_start(Adapter, B_TRUE)); 1558 } 1559 1560 static int 1561 e1000g_start(struct e1000g *Adapter, boolean_t global) 1562 { 1563 if (global) { 1564 /* Allocate dma resources for descriptors and buffers */ 1565 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1566 e1000g_log(Adapter, CE_WARN, 1567 "Alloc DMA resources failed"); 1568 return (ENOTACTIVE); 1569 } 1570 Adapter->rx_buffer_setup = B_FALSE; 1571 } 1572 1573 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1574 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1575 e1000g_log(Adapter, CE_WARN, 1576 "Adapter initialization failed"); 1577 if (global) 1578 e1000g_release_dma_resources(Adapter); 1579 return (ENOTACTIVE); 1580 } 1581 } 1582 1583 rw_enter(&Adapter->chip_lock, RW_WRITER); 1584 1585 /* Setup and initialize the transmit structures */ 1586 e1000g_tx_setup(Adapter); 1587 msec_delay(5); 1588 1589 /* Setup and initialize the receive structures */ 1590 e1000g_rx_setup(Adapter); 1591 msec_delay(5); 1592 1593 /* Restore the e1000g promiscuous mode */ 1594 e1000g_restore_promisc(Adapter); 1595 1596 e1000g_mask_interrupt(Adapter); 1597 1598 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1599 rw_exit(&Adapter->chip_lock); 1600 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1601 return (ENOTACTIVE); 1602 } 1603 1604 Adapter->chip_state = E1000G_START; 1605 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1606 1607 rw_exit(&Adapter->chip_lock); 1608 1609 /* Enable and start the watchdog timer */ 1610 enable_watchdog_timer(Adapter); 1611 1612 return (0); 1613 } 1614 1615 static void 1616 e1000g_m_stop(void *arg) 1617 { 1618 struct e1000g *Adapter = (struct e1000g *)arg; 1619 1620 e1000g_stop(Adapter, B_TRUE); 1621 } 1622 1623 static void 1624 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1625 { 1626 int result; 1627 1628 /* Set stop flags */ 1629 rw_enter(&Adapter->chip_lock, RW_WRITER); 1630 1631 Adapter->chip_state = E1000G_STOP; 1632 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1633 1634 rw_exit(&Adapter->chip_lock); 1635 1636 /* Drain tx sessions */ 1637 (void) e1000g_tx_drain(Adapter); 1638 1639 /* Disable and stop all the timers */ 1640 disable_watchdog_timer(Adapter); 1641 stop_link_timer(Adapter); 1642 stop_82547_timer(Adapter->tx_ring); 1643 1644 /* Stop the chip and release pending resources */ 1645 rw_enter(&Adapter->chip_lock, RW_WRITER); 1646 1647 /* Tell firmware driver is no longer in control */ 1648 e1000g_release_driver_control(&Adapter->shared); 1649 1650 e1000g_clear_all_interrupts(Adapter); 1651 1652 mutex_enter(&e1000g_nvm_lock); 1653 result = e1000_reset_hw(&Adapter->shared); 1654 mutex_exit(&e1000g_nvm_lock); 1655 1656 if (result != E1000_SUCCESS) { 1657 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1658 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1659 } 1660 1661 /* Release resources still held by the TX descriptors */ 1662 e1000g_tx_clean(Adapter); 1663 1664 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1665 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1666 1667 /* Clean the pending rx jumbo packet fragment */ 1668 e1000g_rx_clean(Adapter); 1669 1670 rw_exit(&Adapter->chip_lock); 1671 1672 if (global) 1673 e1000g_release_dma_resources(Adapter); 1674 } 1675 1676 static void 1677 e1000g_rx_clean(struct e1000g *Adapter) 1678 { 1679 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1680 1681 if (rx_ring->rx_mblk != NULL) { 1682 freemsg(rx_ring->rx_mblk); 1683 rx_ring->rx_mblk = NULL; 1684 rx_ring->rx_mblk_tail = NULL; 1685 rx_ring->rx_mblk_len = 0; 1686 } 1687 } 1688 1689 static void 1690 e1000g_tx_clean(struct e1000g *Adapter) 1691 { 1692 e1000g_tx_ring_t *tx_ring; 1693 p_tx_sw_packet_t packet; 1694 mblk_t *mp; 1695 mblk_t *nmp; 1696 uint32_t packet_count; 1697 1698 tx_ring = Adapter->tx_ring; 1699 1700 /* 1701 * Here we don't need to protect the lists using 1702 * the usedlist_lock and freelist_lock, for they 1703 * have been protected by the chip_lock. 1704 */ 1705 mp = NULL; 1706 nmp = NULL; 1707 packet_count = 0; 1708 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1709 while (packet != NULL) { 1710 if (packet->mp != NULL) { 1711 /* Assemble the message chain */ 1712 if (mp == NULL) { 1713 mp = packet->mp; 1714 nmp = packet->mp; 1715 } else { 1716 nmp->b_next = packet->mp; 1717 nmp = packet->mp; 1718 } 1719 /* Disconnect the message from the sw packet */ 1720 packet->mp = NULL; 1721 } 1722 1723 e1000g_free_tx_swpkt(packet); 1724 packet_count++; 1725 1726 packet = (p_tx_sw_packet_t) 1727 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1728 } 1729 1730 if (mp != NULL) 1731 freemsgchain(mp); 1732 1733 if (packet_count > 0) { 1734 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1735 QUEUE_INIT_LIST(&tx_ring->used_list); 1736 1737 /* Setup TX descriptor pointers */ 1738 tx_ring->tbd_next = tx_ring->tbd_first; 1739 tx_ring->tbd_oldest = tx_ring->tbd_first; 1740 1741 /* Setup our HW Tx Head & Tail descriptor pointers */ 1742 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1743 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1744 } 1745 } 1746 1747 static boolean_t 1748 e1000g_tx_drain(struct e1000g *Adapter) 1749 { 1750 int i; 1751 boolean_t done; 1752 e1000g_tx_ring_t *tx_ring; 1753 1754 tx_ring = Adapter->tx_ring; 1755 1756 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1757 for (i = 0; i < TX_DRAIN_TIME; i++) { 1758 mutex_enter(&tx_ring->usedlist_lock); 1759 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1760 mutex_exit(&tx_ring->usedlist_lock); 1761 1762 if (done) 1763 break; 1764 1765 msec_delay(1); 1766 } 1767 1768 return (done); 1769 } 1770 1771 static boolean_t 1772 e1000g_rx_drain(struct e1000g *Adapter) 1773 { 1774 e1000g_rx_ring_t *rx_ring; 1775 p_rx_sw_packet_t packet; 1776 boolean_t done; 1777 1778 rx_ring = Adapter->rx_ring; 1779 done = B_TRUE; 1780 1781 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1782 1783 while (rx_ring->pending_list != NULL) { 1784 packet = rx_ring->pending_list; 1785 rx_ring->pending_list = 1786 rx_ring->pending_list->next; 1787 1788 if (packet->flag == E1000G_RX_SW_STOP) { 1789 packet->flag = E1000G_RX_SW_DETACH; 1790 done = B_FALSE; 1791 } else { 1792 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1793 ASSERT(packet->mp == NULL); 1794 e1000g_free_rx_sw_packet(packet); 1795 } 1796 } 1797 1798 rw_exit(&e1000g_rx_detach_lock); 1799 1800 return (done); 1801 } 1802 1803 static boolean_t 1804 e1000g_reset_adapter(struct e1000g *Adapter) 1805 { 1806 e1000g_stop(Adapter, B_FALSE); 1807 1808 if (e1000g_start(Adapter, B_FALSE)) { 1809 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1810 return (B_FALSE); 1811 } 1812 1813 return (B_TRUE); 1814 } 1815 1816 boolean_t 1817 e1000g_global_reset(struct e1000g *Adapter) 1818 { 1819 e1000g_stop(Adapter, B_TRUE); 1820 1821 Adapter->init_count = 0; 1822 1823 if (e1000g_start(Adapter, B_TRUE)) { 1824 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1825 return (B_FALSE); 1826 } 1827 1828 return (B_TRUE); 1829 } 1830 1831 /* 1832 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1833 * 1834 * This interrupt service routine is for PCI-Express adapters. 1835 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1836 * bit is set. 1837 */ 1838 static uint_t 1839 e1000g_intr_pciexpress(caddr_t arg) 1840 { 1841 struct e1000g *Adapter; 1842 uint32_t icr; 1843 1844 Adapter = (struct e1000g *)(uintptr_t)arg; 1845 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1846 1847 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1848 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1849 1850 if (icr & E1000_ICR_INT_ASSERTED) { 1851 /* 1852 * E1000_ICR_INT_ASSERTED bit was set: 1853 * Read(Clear) the ICR, claim this interrupt, 1854 * look for work to do. 1855 */ 1856 e1000g_intr_work(Adapter, icr); 1857 return (DDI_INTR_CLAIMED); 1858 } else { 1859 /* 1860 * E1000_ICR_INT_ASSERTED bit was not set: 1861 * Don't claim this interrupt, return immediately. 1862 */ 1863 return (DDI_INTR_UNCLAIMED); 1864 } 1865 } 1866 1867 /* 1868 * e1000g_intr - ISR for PCI/PCI-X chipsets 1869 * 1870 * This interrupt service routine is for PCI/PCI-X adapters. 1871 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1872 * bit is set or not. 1873 */ 1874 static uint_t 1875 e1000g_intr(caddr_t arg) 1876 { 1877 struct e1000g *Adapter; 1878 uint32_t icr; 1879 1880 Adapter = (struct e1000g *)(uintptr_t)arg; 1881 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1882 1883 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1884 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1885 1886 if (icr) { 1887 /* 1888 * Any bit was set in ICR: 1889 * Read(Clear) the ICR, claim this interrupt, 1890 * look for work to do. 1891 */ 1892 e1000g_intr_work(Adapter, icr); 1893 return (DDI_INTR_CLAIMED); 1894 } else { 1895 /* 1896 * No bit was set in ICR: 1897 * Don't claim this interrupt, return immediately. 1898 */ 1899 return (DDI_INTR_UNCLAIMED); 1900 } 1901 } 1902 1903 /* 1904 * e1000g_intr_work - actual processing of ISR 1905 * 1906 * Read(clear) the ICR contents and call appropriate interrupt 1907 * processing routines. 1908 */ 1909 static void 1910 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1911 { 1912 struct e1000_hw *hw; 1913 hw = &Adapter->shared; 1914 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1915 uint32_t itr; 1916 1917 Adapter->rx_pkt_cnt = 0; 1918 Adapter->tx_pkt_cnt = 0; 1919 1920 rw_enter(&Adapter->chip_lock, RW_READER); 1921 /* 1922 * Here we need to check the "chip_state" flag within the chip_lock to 1923 * ensure the receive routine will not execute when the adapter is 1924 * being reset. 1925 */ 1926 if (Adapter->chip_state != E1000G_START) { 1927 rw_exit(&Adapter->chip_lock); 1928 return; 1929 } 1930 1931 if (icr & E1000_ICR_RXT0) { 1932 mblk_t *mp; 1933 1934 mutex_enter(&Adapter->rx_ring->rx_lock); 1935 mp = e1000g_receive(Adapter); 1936 mutex_exit(&Adapter->rx_ring->rx_lock); 1937 1938 rw_exit(&Adapter->chip_lock); 1939 1940 if (mp != NULL) 1941 mac_rx(Adapter->mh, Adapter->mrh, mp); 1942 } else 1943 rw_exit(&Adapter->chip_lock); 1944 1945 if (icr & E1000_ICR_TXDW) { 1946 if (!Adapter->tx_intr_enable) 1947 e1000g_clear_tx_interrupt(Adapter); 1948 1949 /* Recycle the tx descriptors */ 1950 rw_enter(&Adapter->chip_lock, RW_READER); 1951 (void) e1000g_recycle(tx_ring); 1952 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1953 rw_exit(&Adapter->chip_lock); 1954 1955 /* Schedule the re-transmit */ 1956 if (tx_ring->resched_needed && 1957 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1958 tx_ring->resched_needed = B_FALSE; 1959 mac_tx_update(Adapter->mh); 1960 E1000G_STAT(tx_ring->stat_reschedule); 1961 } 1962 } 1963 1964 if (Adapter->intr_adaptive) { 1965 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1966 Adapter->intr_throttling_rate); 1967 if (itr) { 1968 E1000_WRITE_REG(hw, E1000_ITR, itr); 1969 Adapter->intr_throttling_rate = itr; 1970 } 1971 } 1972 1973 /* 1974 * The Receive Sequence errors RXSEQ and the link status change LSC 1975 * are checked to detect that the cable has been pulled out. For 1976 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1977 * are an indication that cable is not connected. 1978 */ 1979 if ((icr & E1000_ICR_RXSEQ) || 1980 (icr & E1000_ICR_LSC) || 1981 (icr & E1000_ICR_GPI_EN1)) { 1982 boolean_t link_changed; 1983 timeout_id_t tid = 0; 1984 1985 stop_watchdog_timer(Adapter); 1986 1987 rw_enter(&Adapter->chip_lock, RW_WRITER); 1988 1989 /* 1990 * Because we got a link-status-change interrupt, force 1991 * e1000_check_for_link() to look at phy 1992 */ 1993 Adapter->shared.mac.get_link_status = B_TRUE; 1994 1995 /* e1000g_link_check takes care of link status change */ 1996 link_changed = e1000g_link_check(Adapter); 1997 1998 /* Get new phy state */ 1999 e1000g_get_phy_state(Adapter); 2000 2001 /* 2002 * If the link timer has not timed out, we'll not notify 2003 * the upper layer with any link state until the link is up. 2004 */ 2005 if (link_changed && !Adapter->link_complete) { 2006 if (Adapter->link_state == LINK_STATE_UP) { 2007 mutex_enter(&Adapter->link_lock); 2008 Adapter->link_complete = B_TRUE; 2009 tid = Adapter->link_tid; 2010 Adapter->link_tid = 0; 2011 mutex_exit(&Adapter->link_lock); 2012 } else { 2013 link_changed = B_FALSE; 2014 } 2015 } 2016 rw_exit(&Adapter->chip_lock); 2017 2018 if (link_changed) { 2019 if (tid != 0) 2020 (void) untimeout(tid); 2021 2022 /* 2023 * Workaround for esb2. Data stuck in fifo on a link 2024 * down event. Stop receiver here and reset in watchdog. 2025 */ 2026 if ((Adapter->link_state == LINK_STATE_DOWN) && 2027 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2028 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2029 E1000_WRITE_REG(hw, E1000_RCTL, 2030 rctl & ~E1000_RCTL_EN); 2031 e1000g_log(Adapter, CE_WARN, 2032 "ESB2 receiver disabled"); 2033 Adapter->esb2_workaround = B_TRUE; 2034 } 2035 2036 mac_link_update(Adapter->mh, Adapter->link_state); 2037 } 2038 2039 start_watchdog_timer(Adapter); 2040 } 2041 } 2042 2043 static uint32_t 2044 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 2045 { 2046 uint32_t new_itr; 2047 2048 /* 2049 * Determine a propper itr according to rx/tx packet count 2050 * per interrupt, the value of itr are based on document 2051 * and testing. 2052 */ 2053 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 2054 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 2055 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2056 goto itr_done; 2057 } 2058 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 2059 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 2060 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2061 goto itr_done; 2062 } 2063 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 2064 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 2065 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 2066 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2067 } else 2068 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2069 2070 itr_done: 2071 if (cur_itr == new_itr) 2072 return (0); 2073 else 2074 return (new_itr); 2075 } 2076 2077 static void 2078 e1000g_init_unicst(struct e1000g *Adapter) 2079 { 2080 struct e1000_hw *hw; 2081 int slot; 2082 2083 hw = &Adapter->shared; 2084 2085 if (!Adapter->unicst_init) { 2086 /* Initialize the multiple unicast addresses */ 2087 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2088 2089 if ((hw->mac.type == e1000_82571) && 2090 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2091 Adapter->unicst_total--; 2092 2093 Adapter->unicst_avail = Adapter->unicst_total - 1; 2094 2095 /* Store the default mac address */ 2096 e1000_rar_set(hw, hw->mac.addr, 0); 2097 if ((hw->mac.type == e1000_82571) && 2098 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2099 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2100 2101 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2102 ETHERADDRL); 2103 Adapter->unicst_addr[0].mac.set = 1; 2104 2105 for (slot = 1; slot < Adapter->unicst_total; slot++) 2106 Adapter->unicst_addr[slot].mac.set = 0; 2107 2108 Adapter->unicst_init = B_TRUE; 2109 } else { 2110 /* Recover the default mac address */ 2111 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2112 ETHERADDRL); 2113 2114 /* Store the default mac address */ 2115 e1000_rar_set(hw, hw->mac.addr, 0); 2116 if ((hw->mac.type == e1000_82571) && 2117 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2118 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2119 2120 /* Re-configure the RAR registers */ 2121 for (slot = 1; slot < Adapter->unicst_total; slot++) 2122 e1000_rar_set(hw, 2123 Adapter->unicst_addr[slot].mac.addr, slot); 2124 } 2125 2126 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2127 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2128 } 2129 2130 static int 2131 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2132 { 2133 struct e1000g *Adapter; 2134 2135 Adapter = (struct e1000g *)arg; 2136 2137 /* Store the default MAC address */ 2138 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2139 2140 /* Set MAC address in address slot 0, which is the default address */ 2141 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2142 } 2143 2144 static int 2145 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2146 mac_addr_slot_t slot) 2147 { 2148 struct e1000_hw *hw; 2149 2150 hw = &Adapter->shared; 2151 2152 rw_enter(&Adapter->chip_lock, RW_WRITER); 2153 2154 /* 2155 * The first revision of Wiseman silicon (rev 2.0) has an errata 2156 * that requires the receiver to be in reset when any of the 2157 * receive address registers (RAR regs) are accessed. The first 2158 * rev of Wiseman silicon also requires MWI to be disabled when 2159 * a global reset or a receive reset is issued. So before we 2160 * initialize the RARs, we check the rev of the Wiseman controller 2161 * and work around any necessary HW errata. 2162 */ 2163 if ((hw->mac.type == e1000_82542) && 2164 (hw->revision_id == E1000_REVISION_2)) { 2165 e1000_pci_clear_mwi(hw); 2166 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2167 msec_delay(5); 2168 } 2169 2170 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2171 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2172 2173 if (slot == 0) { 2174 if ((hw->mac.type == e1000_82571) && 2175 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2176 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2177 } 2178 2179 /* 2180 * If we are using Wiseman rev 2.0 silicon, we will have previously 2181 * put the receive in reset, and disabled MWI, to work around some 2182 * HW errata. Now we should take the receiver out of reset, and 2183 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2184 */ 2185 if ((hw->mac.type == e1000_82542) && 2186 (hw->revision_id == E1000_REVISION_2)) { 2187 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2188 msec_delay(1); 2189 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2190 e1000_pci_set_mwi(hw); 2191 e1000g_rx_setup(Adapter); 2192 } 2193 2194 rw_exit(&Adapter->chip_lock); 2195 2196 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2197 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2198 return (EIO); 2199 } 2200 2201 return (0); 2202 } 2203 2204 /* 2205 * e1000g_m_unicst_add() - will find an unused address slot, set the 2206 * address value to the one specified, reserve that slot and enable 2207 * the NIC to start filtering on the new MAC address. 2208 * Returns 0 on success. 2209 */ 2210 static int 2211 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2212 { 2213 struct e1000g *Adapter = (struct e1000g *)arg; 2214 mac_addr_slot_t slot; 2215 int err; 2216 2217 if (mac_unicst_verify(Adapter->mh, 2218 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2219 return (EINVAL); 2220 2221 rw_enter(&Adapter->chip_lock, RW_WRITER); 2222 if (Adapter->unicst_avail == 0) { 2223 /* no slots available */ 2224 rw_exit(&Adapter->chip_lock); 2225 return (ENOSPC); 2226 } 2227 2228 /* 2229 * Primary/default address is in slot 0. The next addresses 2230 * are the multiple MAC addresses. So multiple MAC address 0 2231 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2232 * MAC address resides in slot 1. 2233 */ 2234 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2235 if (Adapter->unicst_addr[slot].mac.set == 0) { 2236 Adapter->unicst_addr[slot].mac.set = 1; 2237 break; 2238 } 2239 } 2240 2241 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2242 2243 Adapter->unicst_avail--; 2244 rw_exit(&Adapter->chip_lock); 2245 2246 maddr->mma_slot = slot; 2247 2248 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2249 rw_enter(&Adapter->chip_lock, RW_WRITER); 2250 Adapter->unicst_addr[slot].mac.set = 0; 2251 Adapter->unicst_avail++; 2252 rw_exit(&Adapter->chip_lock); 2253 } 2254 2255 return (err); 2256 } 2257 2258 /* 2259 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2260 * call to e1000g_m_unicst_add(). The slot number that was returned in 2261 * e1000g_m_unicst_add() is passed in the call to remove the address. 2262 * Returns 0 on success. 2263 */ 2264 static int 2265 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2266 { 2267 struct e1000g *Adapter = (struct e1000g *)arg; 2268 int err; 2269 2270 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2271 return (EINVAL); 2272 2273 rw_enter(&Adapter->chip_lock, RW_WRITER); 2274 if (Adapter->unicst_addr[slot].mac.set == 1) { 2275 Adapter->unicst_addr[slot].mac.set = 0; 2276 Adapter->unicst_avail++; 2277 rw_exit(&Adapter->chip_lock); 2278 2279 /* Copy the default address to the passed slot */ 2280 if ((err = e1000g_unicst_set(Adapter, 2281 Adapter->unicst_addr[0].mac.addr, slot)) != 0) { 2282 rw_enter(&Adapter->chip_lock, RW_WRITER); 2283 Adapter->unicst_addr[slot].mac.set = 1; 2284 Adapter->unicst_avail--; 2285 rw_exit(&Adapter->chip_lock); 2286 } 2287 return (err); 2288 } 2289 rw_exit(&Adapter->chip_lock); 2290 2291 return (EINVAL); 2292 } 2293 2294 /* 2295 * e1000g_m_unicst_modify() - modifies the value of an address that 2296 * has been added by e1000g_m_unicst_add(). The new address, address 2297 * length and the slot number that was returned in the call to add 2298 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2299 * set to 0. Returns 0 on success. 2300 */ 2301 static int 2302 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2303 { 2304 struct e1000g *Adapter = (struct e1000g *)arg; 2305 mac_addr_slot_t slot; 2306 2307 if (mac_unicst_verify(Adapter->mh, 2308 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2309 return (EINVAL); 2310 2311 slot = maddr->mma_slot; 2312 2313 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2314 return (EINVAL); 2315 2316 rw_enter(&Adapter->chip_lock, RW_WRITER); 2317 if (Adapter->unicst_addr[slot].mac.set == 1) { 2318 rw_exit(&Adapter->chip_lock); 2319 2320 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2321 } 2322 rw_exit(&Adapter->chip_lock); 2323 2324 return (EINVAL); 2325 } 2326 2327 /* 2328 * e1000g_m_unicst_get() - will get the MAC address and all other 2329 * information related to the address slot passed in mac_multi_addr_t. 2330 * mma_flags should be set to 0 in the call. 2331 * On return, mma_flags can take the following values: 2332 * 1) MMAC_SLOT_UNUSED 2333 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2334 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2335 * 4) MMAC_SLOT_USED 2336 */ 2337 static int 2338 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2339 { 2340 struct e1000g *Adapter = (struct e1000g *)arg; 2341 mac_addr_slot_t slot; 2342 2343 slot = maddr->mma_slot; 2344 2345 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2346 return (EINVAL); 2347 2348 rw_enter(&Adapter->chip_lock, RW_WRITER); 2349 if (Adapter->unicst_addr[slot].mac.set == 1) { 2350 bcopy(Adapter->unicst_addr[slot].mac.addr, 2351 maddr->mma_addr, ETHERADDRL); 2352 maddr->mma_flags = MMAC_SLOT_USED; 2353 } else { 2354 maddr->mma_flags = MMAC_SLOT_UNUSED; 2355 } 2356 rw_exit(&Adapter->chip_lock); 2357 2358 return (0); 2359 } 2360 2361 static int 2362 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2363 { 2364 struct e1000_hw *hw = &Adapter->shared; 2365 int res = 0; 2366 2367 rw_enter(&Adapter->chip_lock, RW_WRITER); 2368 2369 if ((multiaddr[0] & 01) == 0) { 2370 res = EINVAL; 2371 goto done; 2372 } 2373 2374 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2375 res = ENOENT; 2376 goto done; 2377 } 2378 2379 bcopy(multiaddr, 2380 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2381 Adapter->mcast_count++; 2382 2383 /* 2384 * Update the MC table in the hardware 2385 */ 2386 e1000g_clear_interrupt(Adapter); 2387 2388 e1000g_setup_multicast(Adapter); 2389 2390 if ((hw->mac.type == e1000_82542) && 2391 (hw->revision_id == E1000_REVISION_2)) 2392 e1000g_rx_setup(Adapter); 2393 2394 e1000g_mask_interrupt(Adapter); 2395 2396 done: 2397 rw_exit(&Adapter->chip_lock); 2398 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2399 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2400 res = EIO; 2401 } 2402 2403 return (res); 2404 } 2405 2406 static int 2407 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2408 { 2409 struct e1000_hw *hw = &Adapter->shared; 2410 unsigned i; 2411 2412 rw_enter(&Adapter->chip_lock, RW_WRITER); 2413 2414 for (i = 0; i < Adapter->mcast_count; i++) { 2415 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2416 ETHERADDRL) == 0) { 2417 for (i++; i < Adapter->mcast_count; i++) { 2418 Adapter->mcast_table[i - 1] = 2419 Adapter->mcast_table[i]; 2420 } 2421 Adapter->mcast_count--; 2422 break; 2423 } 2424 } 2425 2426 /* 2427 * Update the MC table in the hardware 2428 */ 2429 e1000g_clear_interrupt(Adapter); 2430 2431 e1000g_setup_multicast(Adapter); 2432 2433 if ((hw->mac.type == e1000_82542) && 2434 (hw->revision_id == E1000_REVISION_2)) 2435 e1000g_rx_setup(Adapter); 2436 2437 e1000g_mask_interrupt(Adapter); 2438 2439 done: 2440 rw_exit(&Adapter->chip_lock); 2441 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2442 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2443 return (EIO); 2444 } 2445 2446 return (0); 2447 } 2448 2449 /* 2450 * e1000g_setup_multicast - setup multicast data structures 2451 * 2452 * This routine initializes all of the multicast related structures. 2453 */ 2454 void 2455 e1000g_setup_multicast(struct e1000g *Adapter) 2456 { 2457 uint8_t *mc_addr_list; 2458 uint32_t mc_addr_count; 2459 uint32_t rctl; 2460 struct e1000_hw *hw; 2461 2462 hw = &Adapter->shared; 2463 2464 /* 2465 * The e1000g has the ability to do perfect filtering of 16 2466 * addresses. The driver uses one of the e1000g's 16 receive 2467 * address registers for its node/network/mac/individual address. 2468 * So, we have room for up to 15 multicast addresses in the CAM, 2469 * additional MC addresses are handled by the MTA (Multicast Table 2470 * Array) 2471 */ 2472 2473 rctl = E1000_READ_REG(hw, E1000_RCTL); 2474 2475 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2476 2477 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2478 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2479 "Adapter requested more than %d MC Addresses.\n", 2480 MAX_NUM_MULTICAST_ADDRESSES); 2481 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2482 } else { 2483 /* 2484 * Set the number of MC addresses that we are being 2485 * requested to use 2486 */ 2487 mc_addr_count = Adapter->mcast_count; 2488 } 2489 /* 2490 * The Wiseman 2.0 silicon has an errata by which the receiver will 2491 * hang while writing to the receive address registers if the receiver 2492 * is not in reset before writing to the registers. Updating the RAR 2493 * is done during the setting up of the multicast table, hence the 2494 * receiver has to be put in reset before updating the multicast table 2495 * and then taken out of reset at the end 2496 */ 2497 /* 2498 * if WMI was enabled then dis able it before issueing the global 2499 * reset to the hardware. 2500 */ 2501 /* 2502 * Only required for WISEMAN_2_0 2503 */ 2504 if ((hw->mac.type == e1000_82542) && 2505 (hw->revision_id == E1000_REVISION_2)) { 2506 e1000_pci_clear_mwi(hw); 2507 /* 2508 * The e1000g must be in reset before changing any RA 2509 * registers. Reset receive unit. The chip will remain in 2510 * the reset state until software explicitly restarts it. 2511 */ 2512 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2513 /* Allow receiver time to go in to reset */ 2514 msec_delay(5); 2515 } 2516 2517 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2518 Adapter->unicst_total, hw->mac.rar_entry_count); 2519 2520 /* 2521 * Only for Wiseman_2_0 2522 * If MWI was enabled then re-enable it after issueing (as we 2523 * disabled it up there) the receive reset command. 2524 * Wainwright does not have a receive reset command and only thing 2525 * close to it is global reset which will require tx setup also 2526 */ 2527 if ((hw->mac.type == e1000_82542) && 2528 (hw->revision_id == E1000_REVISION_2)) { 2529 /* 2530 * if WMI was enabled then reenable it after issueing the 2531 * global or receive reset to the hardware. 2532 */ 2533 2534 /* 2535 * Take receiver out of reset 2536 * clear E1000_RCTL_RST bit (and all others) 2537 */ 2538 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2539 msec_delay(5); 2540 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2541 e1000_pci_set_mwi(hw); 2542 } 2543 2544 /* 2545 * Restore original value 2546 */ 2547 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2548 } 2549 2550 int 2551 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2552 { 2553 struct e1000g *Adapter = (struct e1000g *)arg; 2554 2555 return ((add) ? multicst_add(Adapter, addr) 2556 : multicst_remove(Adapter, addr)); 2557 } 2558 2559 int 2560 e1000g_m_promisc(void *arg, boolean_t on) 2561 { 2562 struct e1000g *Adapter = (struct e1000g *)arg; 2563 uint32_t rctl; 2564 2565 rw_enter(&Adapter->chip_lock, RW_WRITER); 2566 2567 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2568 2569 if (on) 2570 rctl |= 2571 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2572 else 2573 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2574 2575 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2576 2577 Adapter->e1000g_promisc = on; 2578 2579 rw_exit(&Adapter->chip_lock); 2580 2581 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2582 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2583 return (EIO); 2584 } 2585 2586 return (0); 2587 } 2588 2589 static boolean_t 2590 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2591 { 2592 struct e1000g *Adapter = (struct e1000g *)arg; 2593 2594 switch (cap) { 2595 case MAC_CAPAB_HCKSUM: { 2596 uint32_t *txflags = cap_data; 2597 2598 if (Adapter->tx_hcksum_enable) 2599 *txflags = HCKSUM_IPHDRCKSUM | 2600 HCKSUM_INET_PARTIAL; 2601 else 2602 return (B_FALSE); 2603 break; 2604 } 2605 case MAC_CAPAB_POLL: 2606 /* 2607 * There's nothing for us to fill in, simply returning 2608 * B_TRUE stating that we support polling is sufficient. 2609 */ 2610 break; 2611 2612 case MAC_CAPAB_MULTIADDRESS: { 2613 multiaddress_capab_t *mmacp = cap_data; 2614 2615 /* 2616 * The number of MAC addresses made available by 2617 * this capability is one less than the total as 2618 * the primary address in slot 0 is counted in 2619 * the total. 2620 */ 2621 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2622 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2623 /* No multiple factory addresses, set mma_flag to 0 */ 2624 mmacp->maddr_flag = 0; 2625 mmacp->maddr_handle = Adapter; 2626 mmacp->maddr_add = e1000g_m_unicst_add; 2627 mmacp->maddr_remove = e1000g_m_unicst_remove; 2628 mmacp->maddr_modify = e1000g_m_unicst_modify; 2629 mmacp->maddr_get = e1000g_m_unicst_get; 2630 mmacp->maddr_reserve = NULL; 2631 break; 2632 } 2633 2634 case MAC_CAPAB_LSO: { 2635 mac_capab_lso_t *cap_lso = cap_data; 2636 2637 if (Adapter->lso_enable) { 2638 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2639 cap_lso->lso_basic_tcp_ipv4.lso_max = 2640 E1000_LSO_MAXLEN; 2641 } else 2642 return (B_FALSE); 2643 break; 2644 } 2645 2646 default: 2647 return (B_FALSE); 2648 } 2649 return (B_TRUE); 2650 } 2651 2652 static boolean_t 2653 e1000g_param_locked(mac_prop_id_t pr_num) 2654 { 2655 /* 2656 * All en_* parameters are locked (read-only) while 2657 * the device is in any sort of loopback mode ... 2658 */ 2659 switch (pr_num) { 2660 case MAC_PROP_EN_1000FDX_CAP: 2661 case MAC_PROP_EN_1000HDX_CAP: 2662 case MAC_PROP_EN_100FDX_CAP: 2663 case MAC_PROP_EN_100HDX_CAP: 2664 case MAC_PROP_EN_10FDX_CAP: 2665 case MAC_PROP_EN_10HDX_CAP: 2666 case MAC_PROP_AUTONEG: 2667 case MAC_PROP_FLOWCTRL: 2668 return (B_TRUE); 2669 } 2670 return (B_FALSE); 2671 } 2672 2673 /* 2674 * callback function for set/get of properties 2675 */ 2676 static int 2677 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2678 uint_t pr_valsize, const void *pr_val) 2679 { 2680 struct e1000g *Adapter = arg; 2681 struct e1000_mac_info *mac = &Adapter->shared.mac; 2682 struct e1000_phy_info *phy = &Adapter->shared.phy; 2683 struct e1000_fc_info *fc = &Adapter->shared.fc; 2684 int err = 0; 2685 link_flowctrl_t flowctrl; 2686 uint32_t cur_mtu, new_mtu; 2687 uint64_t tmp = 0; 2688 2689 rw_enter(&Adapter->chip_lock, RW_WRITER); 2690 if (Adapter->loopback_mode != E1000G_LB_NONE && 2691 e1000g_param_locked(pr_num)) { 2692 /* 2693 * All en_* parameters are locked (read-only) 2694 * while the device is in any sort of loopback mode. 2695 */ 2696 rw_exit(&Adapter->chip_lock); 2697 return (EBUSY); 2698 } 2699 2700 switch (pr_num) { 2701 case MAC_PROP_EN_1000FDX_CAP: 2702 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2703 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2704 goto reset; 2705 case MAC_PROP_EN_100FDX_CAP: 2706 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2707 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2708 goto reset; 2709 case MAC_PROP_EN_100HDX_CAP: 2710 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2711 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2712 goto reset; 2713 case MAC_PROP_EN_10FDX_CAP: 2714 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2715 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2716 goto reset; 2717 case MAC_PROP_EN_10HDX_CAP: 2718 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2719 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2720 goto reset; 2721 case MAC_PROP_AUTONEG: 2722 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2723 goto reset; 2724 case MAC_PROP_FLOWCTRL: 2725 fc->send_xon = B_TRUE; 2726 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2727 2728 switch (flowctrl) { 2729 default: 2730 err = EINVAL; 2731 break; 2732 case LINK_FLOWCTRL_NONE: 2733 fc->type = e1000_fc_none; 2734 break; 2735 case LINK_FLOWCTRL_RX: 2736 fc->type = e1000_fc_rx_pause; 2737 break; 2738 case LINK_FLOWCTRL_TX: 2739 fc->type = e1000_fc_tx_pause; 2740 break; 2741 case LINK_FLOWCTRL_BI: 2742 fc->type = e1000_fc_full; 2743 break; 2744 } 2745 reset: 2746 if (err == 0) { 2747 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2748 err = EINVAL; 2749 } 2750 break; 2751 case MAC_PROP_ADV_1000FDX_CAP: 2752 case MAC_PROP_ADV_1000HDX_CAP: 2753 case MAC_PROP_ADV_100FDX_CAP: 2754 case MAC_PROP_ADV_100HDX_CAP: 2755 case MAC_PROP_ADV_10FDX_CAP: 2756 case MAC_PROP_ADV_10HDX_CAP: 2757 case MAC_PROP_EN_1000HDX_CAP: 2758 case MAC_PROP_STATUS: 2759 case MAC_PROP_SPEED: 2760 case MAC_PROP_DUPLEX: 2761 err = ENOTSUP; /* read-only prop. Can't set this. */ 2762 break; 2763 case MAC_PROP_MTU: 2764 cur_mtu = Adapter->default_mtu; 2765 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2766 if (new_mtu == cur_mtu) { 2767 err = 0; 2768 break; 2769 } 2770 2771 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2772 ETHERFCSL; 2773 if ((tmp < DEFAULT_FRAME_SIZE) || 2774 (tmp > MAXIMUM_FRAME_SIZE)) { 2775 err = EINVAL; 2776 break; 2777 } 2778 2779 /* ich8 does not support jumbo frames */ 2780 if ((mac->type == e1000_ich8lan) && 2781 (tmp > DEFAULT_FRAME_SIZE)) { 2782 err = EINVAL; 2783 break; 2784 } 2785 /* ich9 does not do jumbo frames on one phy type */ 2786 if ((mac->type == e1000_ich9lan) && 2787 (phy->type == e1000_phy_ife) && 2788 (tmp > DEFAULT_FRAME_SIZE)) { 2789 err = EINVAL; 2790 break; 2791 } 2792 if (Adapter->chip_state != E1000G_STOP) { 2793 err = EBUSY; 2794 break; 2795 } 2796 2797 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2798 if (err == 0) { 2799 Adapter->max_frame_size = (uint32_t)tmp; 2800 Adapter->default_mtu = new_mtu; 2801 e1000g_set_bufsize(Adapter); 2802 } 2803 break; 2804 case MAC_PROP_PRIVATE: 2805 err = e1000g_set_priv_prop(Adapter, pr_name, 2806 pr_valsize, pr_val); 2807 break; 2808 default: 2809 err = ENOTSUP; 2810 break; 2811 } 2812 rw_exit(&Adapter->chip_lock); 2813 return (err); 2814 } 2815 2816 static int 2817 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2818 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 2819 { 2820 struct e1000g *Adapter = arg; 2821 struct e1000_fc_info *fc = &Adapter->shared.fc; 2822 int err = 0; 2823 link_flowctrl_t flowctrl; 2824 uint64_t tmp = 0; 2825 2826 if (pr_valsize == 0) 2827 return (EINVAL); 2828 2829 *perm = MAC_PROP_PERM_RW; 2830 2831 bzero(pr_val, pr_valsize); 2832 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2833 return (e1000g_get_def_val(Adapter, pr_num, 2834 pr_valsize, pr_val)); 2835 } 2836 2837 switch (pr_num) { 2838 case MAC_PROP_DUPLEX: 2839 *perm = MAC_PROP_PERM_READ; 2840 if (pr_valsize >= sizeof (link_duplex_t)) { 2841 bcopy(&Adapter->link_duplex, pr_val, 2842 sizeof (link_duplex_t)); 2843 } else 2844 err = EINVAL; 2845 break; 2846 case MAC_PROP_SPEED: 2847 *perm = MAC_PROP_PERM_READ; 2848 if (pr_valsize >= sizeof (uint64_t)) { 2849 tmp = Adapter->link_speed * 1000000ull; 2850 bcopy(&tmp, pr_val, sizeof (tmp)); 2851 } else 2852 err = EINVAL; 2853 break; 2854 case MAC_PROP_AUTONEG: 2855 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2856 break; 2857 case MAC_PROP_FLOWCTRL: 2858 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2859 switch (fc->type) { 2860 case e1000_fc_none: 2861 flowctrl = LINK_FLOWCTRL_NONE; 2862 break; 2863 case e1000_fc_rx_pause: 2864 flowctrl = LINK_FLOWCTRL_RX; 2865 break; 2866 case e1000_fc_tx_pause: 2867 flowctrl = LINK_FLOWCTRL_TX; 2868 break; 2869 case e1000_fc_full: 2870 flowctrl = LINK_FLOWCTRL_BI; 2871 break; 2872 } 2873 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2874 } else 2875 err = EINVAL; 2876 break; 2877 case MAC_PROP_ADV_1000FDX_CAP: 2878 *perm = MAC_PROP_PERM_READ; 2879 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2880 break; 2881 case MAC_PROP_EN_1000FDX_CAP: 2882 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2883 break; 2884 case MAC_PROP_ADV_1000HDX_CAP: 2885 *perm = MAC_PROP_PERM_READ; 2886 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2887 break; 2888 case MAC_PROP_EN_1000HDX_CAP: 2889 *perm = MAC_PROP_PERM_READ; 2890 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2891 break; 2892 case MAC_PROP_ADV_100FDX_CAP: 2893 *perm = MAC_PROP_PERM_READ; 2894 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2895 break; 2896 case MAC_PROP_EN_100FDX_CAP: 2897 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2898 break; 2899 case MAC_PROP_ADV_100HDX_CAP: 2900 *perm = MAC_PROP_PERM_READ; 2901 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2902 break; 2903 case MAC_PROP_EN_100HDX_CAP: 2904 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2905 break; 2906 case MAC_PROP_ADV_10FDX_CAP: 2907 *perm = MAC_PROP_PERM_READ; 2908 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2909 break; 2910 case MAC_PROP_EN_10FDX_CAP: 2911 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2912 break; 2913 case MAC_PROP_ADV_10HDX_CAP: 2914 *perm = MAC_PROP_PERM_READ; 2915 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2916 break; 2917 case MAC_PROP_EN_10HDX_CAP: 2918 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2919 break; 2920 case MAC_PROP_ADV_100T4_CAP: 2921 case MAC_PROP_EN_100T4_CAP: 2922 *perm = MAC_PROP_PERM_READ; 2923 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2924 break; 2925 case MAC_PROP_PRIVATE: 2926 err = e1000g_get_priv_prop(Adapter, pr_name, 2927 pr_flags, pr_valsize, pr_val, perm); 2928 break; 2929 default: 2930 err = ENOTSUP; 2931 break; 2932 } 2933 return (err); 2934 } 2935 2936 /* ARGSUSED2 */ 2937 static int 2938 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2939 uint_t pr_valsize, const void *pr_val) 2940 { 2941 int err = 0; 2942 long result; 2943 struct e1000_hw *hw = &Adapter->shared; 2944 2945 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2946 if (pr_val == NULL) { 2947 err = EINVAL; 2948 return (err); 2949 } 2950 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2951 if (result < MIN_TX_BCOPY_THRESHOLD || 2952 result > MAX_TX_BCOPY_THRESHOLD) 2953 err = EINVAL; 2954 else { 2955 Adapter->tx_bcopy_thresh = (uint32_t)result; 2956 } 2957 return (err); 2958 } 2959 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2960 if (pr_val == NULL) { 2961 err = EINVAL; 2962 return (err); 2963 } 2964 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2965 if (result < 0 || result > 1) 2966 err = EINVAL; 2967 else { 2968 Adapter->tx_intr_enable = (result == 1) ? 2969 B_TRUE: B_FALSE; 2970 if (Adapter->tx_intr_enable) 2971 e1000g_mask_tx_interrupt(Adapter); 2972 else 2973 e1000g_clear_tx_interrupt(Adapter); 2974 if (e1000g_check_acc_handle( 2975 Adapter->osdep.reg_handle) != DDI_FM_OK) 2976 ddi_fm_service_impact(Adapter->dip, 2977 DDI_SERVICE_DEGRADED); 2978 } 2979 return (err); 2980 } 2981 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2982 if (pr_val == NULL) { 2983 err = EINVAL; 2984 return (err); 2985 } 2986 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2987 if (result < MIN_TX_INTR_DELAY || 2988 result > MAX_TX_INTR_DELAY) 2989 err = EINVAL; 2990 else { 2991 Adapter->tx_intr_delay = (uint32_t)result; 2992 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2993 if (e1000g_check_acc_handle( 2994 Adapter->osdep.reg_handle) != DDI_FM_OK) 2995 ddi_fm_service_impact(Adapter->dip, 2996 DDI_SERVICE_DEGRADED); 2997 } 2998 return (err); 2999 } 3000 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3001 if (pr_val == NULL) { 3002 err = EINVAL; 3003 return (err); 3004 } 3005 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3006 if (result < MIN_TX_INTR_ABS_DELAY || 3007 result > MAX_TX_INTR_ABS_DELAY) 3008 err = EINVAL; 3009 else { 3010 Adapter->tx_intr_abs_delay = (uint32_t)result; 3011 E1000_WRITE_REG(hw, E1000_TADV, 3012 Adapter->tx_intr_abs_delay); 3013 if (e1000g_check_acc_handle( 3014 Adapter->osdep.reg_handle) != DDI_FM_OK) 3015 ddi_fm_service_impact(Adapter->dip, 3016 DDI_SERVICE_DEGRADED); 3017 } 3018 return (err); 3019 } 3020 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3021 if (pr_val == NULL) { 3022 err = EINVAL; 3023 return (err); 3024 } 3025 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3026 if (result < MIN_RX_BCOPY_THRESHOLD || 3027 result > MAX_RX_BCOPY_THRESHOLD) 3028 err = EINVAL; 3029 else 3030 Adapter->rx_bcopy_thresh = (uint32_t)result; 3031 return (err); 3032 } 3033 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3034 if (pr_val == NULL) { 3035 err = EINVAL; 3036 return (err); 3037 } 3038 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3039 if (result < MIN_RX_LIMIT_ON_INTR || 3040 result > MAX_RX_LIMIT_ON_INTR) 3041 err = EINVAL; 3042 else 3043 Adapter->rx_limit_onintr = (uint32_t)result; 3044 return (err); 3045 } 3046 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3047 if (pr_val == NULL) { 3048 err = EINVAL; 3049 return (err); 3050 } 3051 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3052 if (result < MIN_RX_INTR_DELAY || 3053 result > MAX_RX_INTR_DELAY) 3054 err = EINVAL; 3055 else { 3056 Adapter->rx_intr_delay = (uint32_t)result; 3057 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3058 if (e1000g_check_acc_handle( 3059 Adapter->osdep.reg_handle) != DDI_FM_OK) 3060 ddi_fm_service_impact(Adapter->dip, 3061 DDI_SERVICE_DEGRADED); 3062 } 3063 return (err); 3064 } 3065 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3066 if (pr_val == NULL) { 3067 err = EINVAL; 3068 return (err); 3069 } 3070 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3071 if (result < MIN_RX_INTR_ABS_DELAY || 3072 result > MAX_RX_INTR_ABS_DELAY) 3073 err = EINVAL; 3074 else { 3075 Adapter->rx_intr_abs_delay = (uint32_t)result; 3076 E1000_WRITE_REG(hw, E1000_RADV, 3077 Adapter->rx_intr_abs_delay); 3078 if (e1000g_check_acc_handle( 3079 Adapter->osdep.reg_handle) != DDI_FM_OK) 3080 ddi_fm_service_impact(Adapter->dip, 3081 DDI_SERVICE_DEGRADED); 3082 } 3083 return (err); 3084 } 3085 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3086 if (pr_val == NULL) { 3087 err = EINVAL; 3088 return (err); 3089 } 3090 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3091 if (result < MIN_INTR_THROTTLING || 3092 result > MAX_INTR_THROTTLING) 3093 err = EINVAL; 3094 else { 3095 if (hw->mac.type >= e1000_82540) { 3096 Adapter->intr_throttling_rate = 3097 (uint32_t)result; 3098 E1000_WRITE_REG(hw, E1000_ITR, 3099 Adapter->intr_throttling_rate); 3100 if (e1000g_check_acc_handle( 3101 Adapter->osdep.reg_handle) != DDI_FM_OK) 3102 ddi_fm_service_impact(Adapter->dip, 3103 DDI_SERVICE_DEGRADED); 3104 } else 3105 err = EINVAL; 3106 } 3107 return (err); 3108 } 3109 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3110 if (pr_val == NULL) { 3111 err = EINVAL; 3112 return (err); 3113 } 3114 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3115 if (result < 0 || result > 1) 3116 err = EINVAL; 3117 else { 3118 if (hw->mac.type >= e1000_82540) { 3119 Adapter->intr_adaptive = (result == 1) ? 3120 B_TRUE : B_FALSE; 3121 } else { 3122 err = EINVAL; 3123 } 3124 } 3125 return (err); 3126 } 3127 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3128 if (pr_val == NULL) { 3129 err = EINVAL; 3130 return (err); 3131 } 3132 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3133 if (result < MIN_TX_RECYCLE_THRESHOLD || 3134 result > MAX_TX_RECYCLE_THRESHOLD) 3135 err = EINVAL; 3136 else 3137 Adapter->tx_recycle_thresh = (uint32_t)result; 3138 return (err); 3139 } 3140 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3141 if (pr_val == NULL) { 3142 err = EINVAL; 3143 return (err); 3144 } 3145 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3146 if (result < MIN_TX_RECYCLE_NUM || 3147 result > MAX_TX_RECYCLE_NUM) 3148 err = EINVAL; 3149 else 3150 Adapter->tx_recycle_num = (uint32_t)result; 3151 return (err); 3152 } 3153 return (ENOTSUP); 3154 } 3155 3156 static int 3157 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3158 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3159 { 3160 int err = ENOTSUP; 3161 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3162 int value; 3163 3164 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3165 *perm = MAC_PROP_PERM_READ; 3166 if (is_default) 3167 goto done; 3168 value = Adapter->param_adv_pause; 3169 err = 0; 3170 goto done; 3171 } 3172 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3173 *perm = MAC_PROP_PERM_READ; 3174 if (is_default) 3175 goto done; 3176 value = Adapter->param_adv_asym_pause; 3177 err = 0; 3178 goto done; 3179 } 3180 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3181 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3182 Adapter->tx_bcopy_thresh); 3183 err = 0; 3184 goto done; 3185 } 3186 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3187 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3188 Adapter->tx_intr_enable); 3189 err = 0; 3190 goto done; 3191 } 3192 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3193 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3194 Adapter->tx_intr_delay); 3195 err = 0; 3196 goto done; 3197 } 3198 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3199 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3200 Adapter->tx_intr_abs_delay); 3201 err = 0; 3202 goto done; 3203 } 3204 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3205 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3206 Adapter->rx_bcopy_thresh); 3207 err = 0; 3208 goto done; 3209 } 3210 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3211 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3212 Adapter->rx_limit_onintr); 3213 err = 0; 3214 goto done; 3215 } 3216 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3217 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3218 Adapter->rx_intr_delay); 3219 err = 0; 3220 goto done; 3221 } 3222 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3223 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3224 Adapter->rx_intr_abs_delay); 3225 err = 0; 3226 goto done; 3227 } 3228 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3229 value = (is_default ? DEFAULT_INTR_THROTTLING : 3230 Adapter->intr_throttling_rate); 3231 err = 0; 3232 goto done; 3233 } 3234 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3235 value = (is_default ? 1 : Adapter->intr_adaptive); 3236 err = 0; 3237 goto done; 3238 } 3239 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3240 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3241 Adapter->tx_recycle_thresh); 3242 err = 0; 3243 goto done; 3244 } 3245 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3246 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3247 Adapter->tx_recycle_num); 3248 err = 0; 3249 goto done; 3250 } 3251 done: 3252 if (err == 0) { 3253 (void) snprintf(pr_val, pr_valsize, "%d", value); 3254 } 3255 return (err); 3256 } 3257 3258 /* 3259 * e1000g_get_conf - get configurations set in e1000g.conf 3260 * This routine gets user-configured values out of the configuration 3261 * file e1000g.conf. 3262 * 3263 * For each configurable value, there is a minimum, a maximum, and a 3264 * default. 3265 * If user does not configure a value, use the default. 3266 * If user configures below the minimum, use the minumum. 3267 * If user configures above the maximum, use the maxumum. 3268 */ 3269 static void 3270 e1000g_get_conf(struct e1000g *Adapter) 3271 { 3272 struct e1000_hw *hw = &Adapter->shared; 3273 boolean_t tbi_compatibility = B_FALSE; 3274 3275 /* 3276 * get each configurable property from e1000g.conf 3277 */ 3278 3279 /* 3280 * NumTxDescriptors 3281 */ 3282 Adapter->tx_desc_num = 3283 e1000g_get_prop(Adapter, "NumTxDescriptors", 3284 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3285 DEFAULT_NUM_TX_DESCRIPTOR); 3286 3287 /* 3288 * NumRxDescriptors 3289 */ 3290 Adapter->rx_desc_num = 3291 e1000g_get_prop(Adapter, "NumRxDescriptors", 3292 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3293 DEFAULT_NUM_RX_DESCRIPTOR); 3294 3295 /* 3296 * NumRxFreeList 3297 */ 3298 Adapter->rx_freelist_num = 3299 e1000g_get_prop(Adapter, "NumRxFreeList", 3300 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3301 DEFAULT_NUM_RX_FREELIST); 3302 3303 /* 3304 * NumTxPacketList 3305 */ 3306 Adapter->tx_freelist_num = 3307 e1000g_get_prop(Adapter, "NumTxPacketList", 3308 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3309 DEFAULT_NUM_TX_FREELIST); 3310 3311 /* 3312 * FlowControl 3313 */ 3314 hw->fc.send_xon = B_TRUE; 3315 hw->fc.type = 3316 e1000g_get_prop(Adapter, "FlowControl", 3317 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3318 /* 4 is the setting that says "let the eeprom decide" */ 3319 if (hw->fc.type == 4) 3320 hw->fc.type = e1000_fc_default; 3321 3322 /* 3323 * Max Num Receive Packets on Interrupt 3324 */ 3325 Adapter->rx_limit_onintr = 3326 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3327 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3328 DEFAULT_RX_LIMIT_ON_INTR); 3329 3330 /* 3331 * PHY master slave setting 3332 */ 3333 hw->phy.ms_type = 3334 e1000g_get_prop(Adapter, "SetMasterSlave", 3335 e1000_ms_hw_default, e1000_ms_auto, 3336 e1000_ms_hw_default); 3337 3338 /* 3339 * Parameter which controls TBI mode workaround, which is only 3340 * needed on certain switches such as Cisco 6500/Foundry 3341 */ 3342 tbi_compatibility = 3343 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3344 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3345 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3346 3347 /* 3348 * MSI Enable 3349 */ 3350 Adapter->msi_enable = 3351 e1000g_get_prop(Adapter, "MSIEnable", 3352 0, 1, DEFAULT_MSI_ENABLE); 3353 3354 /* 3355 * Interrupt Throttling Rate 3356 */ 3357 Adapter->intr_throttling_rate = 3358 e1000g_get_prop(Adapter, "intr_throttling_rate", 3359 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3360 DEFAULT_INTR_THROTTLING); 3361 3362 /* 3363 * Adaptive Interrupt Blanking Enable/Disable 3364 * It is enabled by default 3365 */ 3366 Adapter->intr_adaptive = 3367 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3368 B_TRUE : B_FALSE; 3369 3370 /* 3371 * Tx recycle threshold 3372 */ 3373 Adapter->tx_recycle_thresh = 3374 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3375 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3376 DEFAULT_TX_RECYCLE_THRESHOLD); 3377 3378 /* 3379 * Tx recycle descriptor number 3380 */ 3381 Adapter->tx_recycle_num = 3382 e1000g_get_prop(Adapter, "tx_recycle_num", 3383 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3384 DEFAULT_TX_RECYCLE_NUM); 3385 3386 /* 3387 * Hardware checksum enable/disable parameter 3388 */ 3389 Adapter->tx_hcksum_enable = 3390 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3391 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3392 /* 3393 * Checksum on/off selection via global parameters. 3394 * 3395 * If the chip is flagged as not capable of (correctly) 3396 * handling checksumming, we don't enable it on either 3397 * Rx or Tx side. Otherwise, we take this chip's settings 3398 * from the patchable global defaults. 3399 * 3400 * We advertise our capabilities only if TX offload is 3401 * enabled. On receive, the stack will accept checksummed 3402 * packets anyway, even if we haven't said we can deliver 3403 * them. 3404 */ 3405 switch (hw->mac.type) { 3406 case e1000_82540: 3407 case e1000_82544: 3408 case e1000_82545: 3409 case e1000_82545_rev_3: 3410 case e1000_82546: 3411 case e1000_82546_rev_3: 3412 case e1000_82571: 3413 case e1000_82572: 3414 case e1000_82573: 3415 case e1000_80003es2lan: 3416 break; 3417 /* 3418 * For the following Intel PRO/1000 chipsets, we have not 3419 * tested the hardware checksum offload capability, so we 3420 * disable the capability for them. 3421 * e1000_82542, 3422 * e1000_82543, 3423 * e1000_82541, 3424 * e1000_82541_rev_2, 3425 * e1000_82547, 3426 * e1000_82547_rev_2, 3427 */ 3428 default: 3429 Adapter->tx_hcksum_enable = B_FALSE; 3430 } 3431 3432 /* 3433 * Large Send Offloading(LSO) Enable/Disable 3434 * If the tx hardware checksum is not enabled, LSO should be 3435 * disabled. 3436 */ 3437 Adapter->lso_enable = 3438 e1000g_get_prop(Adapter, "lso_enable", 3439 0, 1, DEFAULT_LSO_ENABLE); 3440 3441 switch (hw->mac.type) { 3442 case e1000_82546: 3443 case e1000_82546_rev_3: 3444 if (Adapter->lso_enable) 3445 Adapter->lso_premature_issue = B_TRUE; 3446 /* FALLTHRU */ 3447 case e1000_82571: 3448 case e1000_82572: 3449 case e1000_82573: 3450 case e1000_80003es2lan: 3451 break; 3452 default: 3453 Adapter->lso_enable = B_FALSE; 3454 } 3455 3456 if (!Adapter->tx_hcksum_enable) { 3457 Adapter->lso_premature_issue = B_FALSE; 3458 Adapter->lso_enable = B_FALSE; 3459 } 3460 } 3461 3462 /* 3463 * e1000g_get_prop - routine to read properties 3464 * 3465 * Get a user-configure property value out of the configuration 3466 * file e1000g.conf. 3467 * 3468 * Caller provides name of the property, a default value, a minimum 3469 * value, and a maximum value. 3470 * 3471 * Return configured value of the property, with default, minimum and 3472 * maximum properly applied. 3473 */ 3474 static int 3475 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3476 char *propname, /* name of the property */ 3477 int minval, /* minimum acceptable value */ 3478 int maxval, /* maximim acceptable value */ 3479 int defval) /* default value */ 3480 { 3481 int propval; /* value returned for requested property */ 3482 int *props; /* point to array of properties returned */ 3483 uint_t nprops; /* number of property value returned */ 3484 3485 /* 3486 * get the array of properties from the config file 3487 */ 3488 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3489 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3490 /* got some properties, test if we got enough */ 3491 if (Adapter->instance < nprops) { 3492 propval = props[Adapter->instance]; 3493 } else { 3494 /* not enough properties configured */ 3495 propval = defval; 3496 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3497 "Not Enough %s values found in e1000g.conf" 3498 " - set to %d\n", 3499 propname, propval); 3500 } 3501 3502 /* free memory allocated for properties */ 3503 ddi_prop_free(props); 3504 3505 } else { 3506 propval = defval; 3507 } 3508 3509 /* 3510 * enforce limits 3511 */ 3512 if (propval > maxval) { 3513 propval = maxval; 3514 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3515 "Too High %s value in e1000g.conf - set to %d\n", 3516 propname, propval); 3517 } 3518 3519 if (propval < minval) { 3520 propval = minval; 3521 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3522 "Too Low %s value in e1000g.conf - set to %d\n", 3523 propname, propval); 3524 } 3525 3526 return (propval); 3527 } 3528 3529 static boolean_t 3530 e1000g_link_check(struct e1000g *Adapter) 3531 { 3532 uint16_t speed, duplex, phydata; 3533 boolean_t link_changed = B_FALSE; 3534 struct e1000_hw *hw; 3535 uint32_t reg_tarc; 3536 3537 hw = &Adapter->shared; 3538 3539 if (e1000g_link_up(Adapter)) { 3540 /* 3541 * The Link is up, check whether it was marked as down earlier 3542 */ 3543 if (Adapter->link_state != LINK_STATE_UP) { 3544 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3545 Adapter->link_speed = speed; 3546 Adapter->link_duplex = duplex; 3547 Adapter->link_state = LINK_STATE_UP; 3548 link_changed = B_TRUE; 3549 3550 Adapter->tx_link_down_timeout = 0; 3551 3552 if ((hw->mac.type == e1000_82571) || 3553 (hw->mac.type == e1000_82572)) { 3554 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3555 if (speed == SPEED_1000) 3556 reg_tarc |= (1 << 21); 3557 else 3558 reg_tarc &= ~(1 << 21); 3559 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3560 } 3561 } 3562 Adapter->smartspeed = 0; 3563 } else { 3564 if (Adapter->link_state != LINK_STATE_DOWN) { 3565 Adapter->link_speed = 0; 3566 Adapter->link_duplex = 0; 3567 Adapter->link_state = LINK_STATE_DOWN; 3568 link_changed = B_TRUE; 3569 3570 /* 3571 * SmartSpeed workaround for Tabor/TanaX, When the 3572 * driver loses link disable auto master/slave 3573 * resolution. 3574 */ 3575 if (hw->phy.type == e1000_phy_igp) { 3576 (void) e1000_read_phy_reg(hw, 3577 PHY_1000T_CTRL, &phydata); 3578 phydata |= CR_1000T_MS_ENABLE; 3579 (void) e1000_write_phy_reg(hw, 3580 PHY_1000T_CTRL, phydata); 3581 } 3582 } else { 3583 e1000g_smartspeed(Adapter); 3584 } 3585 3586 if (Adapter->chip_state == E1000G_START) { 3587 if (Adapter->tx_link_down_timeout < 3588 MAX_TX_LINK_DOWN_TIMEOUT) { 3589 Adapter->tx_link_down_timeout++; 3590 } else if (Adapter->tx_link_down_timeout == 3591 MAX_TX_LINK_DOWN_TIMEOUT) { 3592 e1000g_tx_clean(Adapter); 3593 Adapter->tx_link_down_timeout++; 3594 } 3595 } 3596 } 3597 3598 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3599 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3600 3601 return (link_changed); 3602 } 3603 3604 /* 3605 * e1000g_reset_link - Using the link properties to setup the link 3606 */ 3607 int 3608 e1000g_reset_link(struct e1000g *Adapter) 3609 { 3610 struct e1000_mac_info *mac; 3611 struct e1000_phy_info *phy; 3612 boolean_t invalid; 3613 3614 mac = &Adapter->shared.mac; 3615 phy = &Adapter->shared.phy; 3616 invalid = B_FALSE; 3617 3618 if (Adapter->param_adv_autoneg == 1) { 3619 mac->autoneg = B_TRUE; 3620 phy->autoneg_advertised = 0; 3621 3622 /* 3623 * 1000hdx is not supported for autonegotiation 3624 */ 3625 if (Adapter->param_adv_1000fdx == 1) 3626 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3627 3628 if (Adapter->param_adv_100fdx == 1) 3629 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3630 3631 if (Adapter->param_adv_100hdx == 1) 3632 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3633 3634 if (Adapter->param_adv_10fdx == 1) 3635 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3636 3637 if (Adapter->param_adv_10hdx == 1) 3638 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3639 3640 if (phy->autoneg_advertised == 0) 3641 invalid = B_TRUE; 3642 } else { 3643 mac->autoneg = B_FALSE; 3644 3645 /* 3646 * 1000fdx and 1000hdx are not supported for forced link 3647 */ 3648 if (Adapter->param_adv_100fdx == 1) 3649 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3650 else if (Adapter->param_adv_100hdx == 1) 3651 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3652 else if (Adapter->param_adv_10fdx == 1) 3653 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3654 else if (Adapter->param_adv_10hdx == 1) 3655 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3656 else 3657 invalid = B_TRUE; 3658 3659 } 3660 3661 if (invalid) { 3662 e1000g_log(Adapter, CE_WARN, 3663 "Invalid link sets. Setup link to" 3664 "support autonegotiation with all link capabilities."); 3665 mac->autoneg = B_TRUE; 3666 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3667 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3668 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3669 } 3670 3671 return (e1000_setup_link(&Adapter->shared)); 3672 } 3673 3674 static void 3675 e1000g_local_timer(void *ws) 3676 { 3677 struct e1000g *Adapter = (struct e1000g *)ws; 3678 struct e1000_hw *hw; 3679 e1000g_ether_addr_t ether_addr; 3680 boolean_t link_changed; 3681 3682 hw = &Adapter->shared; 3683 3684 if (Adapter->chip_state == E1000G_ERROR) { 3685 Adapter->reset_count++; 3686 if (e1000g_global_reset(Adapter)) 3687 ddi_fm_service_impact(Adapter->dip, 3688 DDI_SERVICE_RESTORED); 3689 else 3690 ddi_fm_service_impact(Adapter->dip, 3691 DDI_SERVICE_LOST); 3692 return; 3693 } 3694 3695 if (e1000g_stall_check(Adapter)) { 3696 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3697 "Tx stall detected. Activate automatic recovery.\n"); 3698 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3699 Adapter->reset_count++; 3700 if (e1000g_reset_adapter(Adapter)) 3701 ddi_fm_service_impact(Adapter->dip, 3702 DDI_SERVICE_RESTORED); 3703 else 3704 ddi_fm_service_impact(Adapter->dip, 3705 DDI_SERVICE_LOST); 3706 return; 3707 } 3708 3709 link_changed = B_FALSE; 3710 rw_enter(&Adapter->chip_lock, RW_READER); 3711 if (Adapter->link_complete) 3712 link_changed = e1000g_link_check(Adapter); 3713 rw_exit(&Adapter->chip_lock); 3714 3715 if (link_changed) 3716 mac_link_update(Adapter->mh, Adapter->link_state); 3717 3718 /* 3719 * Workaround for esb2. Data stuck in fifo on a link 3720 * down event. Reset the adapter to recover it. 3721 */ 3722 if (Adapter->esb2_workaround) { 3723 Adapter->esb2_workaround = B_FALSE; 3724 (void) e1000g_reset_adapter(Adapter); 3725 } 3726 3727 /* 3728 * With 82571 controllers, any locally administered address will 3729 * be overwritten when there is a reset on the other port. 3730 * Detect this circumstance and correct it. 3731 */ 3732 if ((hw->mac.type == e1000_82571) && 3733 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3734 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3735 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3736 3737 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3738 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3739 3740 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3741 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3742 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3743 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3744 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3745 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3746 e1000_rar_set(hw, hw->mac.addr, 0); 3747 } 3748 } 3749 3750 /* 3751 * Long TTL workaround for 82541/82547 3752 */ 3753 (void) e1000_igp_ttl_workaround_82547(hw); 3754 3755 /* 3756 * Check for Adaptive IFS settings If there are lots of collisions 3757 * change the value in steps... 3758 * These properties should only be set for 10/100 3759 */ 3760 if ((hw->phy.media_type == e1000_media_type_copper) && 3761 ((Adapter->link_speed == SPEED_100) || 3762 (Adapter->link_speed == SPEED_10))) { 3763 e1000_update_adaptive(hw); 3764 } 3765 /* 3766 * Set Timer Interrupts 3767 */ 3768 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3769 3770 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3771 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3772 3773 restart_watchdog_timer(Adapter); 3774 } 3775 3776 /* 3777 * The function e1000g_link_timer() is called when the timer for link setup 3778 * is expired, which indicates the completion of the link setup. The link 3779 * state will not be updated until the link setup is completed. And the 3780 * link state will not be sent to the upper layer through mac_link_update() 3781 * in this function. It will be updated in the local timer routine or the 3782 * interrupt service routine after the interface is started (plumbed). 3783 */ 3784 static void 3785 e1000g_link_timer(void *arg) 3786 { 3787 struct e1000g *Adapter = (struct e1000g *)arg; 3788 3789 mutex_enter(&Adapter->link_lock); 3790 Adapter->link_complete = B_TRUE; 3791 Adapter->link_tid = 0; 3792 mutex_exit(&Adapter->link_lock); 3793 } 3794 3795 /* 3796 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3797 * 3798 * This function read the forced speed and duplex for 10/100 Mbps speeds 3799 * and also for 1000 Mbps speeds from the e1000g.conf file 3800 */ 3801 static void 3802 e1000g_force_speed_duplex(struct e1000g *Adapter) 3803 { 3804 int forced; 3805 struct e1000_mac_info *mac = &Adapter->shared.mac; 3806 struct e1000_phy_info *phy = &Adapter->shared.phy; 3807 3808 /* 3809 * get value out of config file 3810 */ 3811 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3812 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3813 3814 switch (forced) { 3815 case GDIAG_10_HALF: 3816 /* 3817 * Disable Auto Negotiation 3818 */ 3819 mac->autoneg = B_FALSE; 3820 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3821 break; 3822 case GDIAG_10_FULL: 3823 /* 3824 * Disable Auto Negotiation 3825 */ 3826 mac->autoneg = B_FALSE; 3827 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3828 break; 3829 case GDIAG_100_HALF: 3830 /* 3831 * Disable Auto Negotiation 3832 */ 3833 mac->autoneg = B_FALSE; 3834 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3835 break; 3836 case GDIAG_100_FULL: 3837 /* 3838 * Disable Auto Negotiation 3839 */ 3840 mac->autoneg = B_FALSE; 3841 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3842 break; 3843 case GDIAG_1000_FULL: 3844 /* 3845 * The gigabit spec requires autonegotiation. Therefore, 3846 * when the user wants to force the speed to 1000Mbps, we 3847 * enable AutoNeg, but only allow the harware to advertise 3848 * 1000Mbps. This is different from 10/100 operation, where 3849 * we are allowed to link without any negotiation. 3850 */ 3851 mac->autoneg = B_TRUE; 3852 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3853 break; 3854 default: /* obey the setting of AutoNegAdvertised */ 3855 mac->autoneg = B_TRUE; 3856 phy->autoneg_advertised = 3857 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3858 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3859 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3860 break; 3861 } /* switch */ 3862 } 3863 3864 /* 3865 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3866 * 3867 * This function reads MaxFrameSize from e1000g.conf 3868 */ 3869 static void 3870 e1000g_get_max_frame_size(struct e1000g *Adapter) 3871 { 3872 int max_frame; 3873 struct e1000_mac_info *mac = &Adapter->shared.mac; 3874 struct e1000_phy_info *phy = &Adapter->shared.phy; 3875 3876 /* 3877 * get value out of config file 3878 */ 3879 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3880 3881 switch (max_frame) { 3882 case 0: 3883 Adapter->default_mtu = ETHERMTU; 3884 break; 3885 /* 3886 * To avoid excessive memory allocation for rx buffers, 3887 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3888 */ 3889 case 1: 3890 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3891 sizeof (struct ether_vlan_header) - ETHERFCSL - 3892 E1000G_IPALIGNPRESERVEROOM; 3893 break; 3894 case 2: 3895 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3896 sizeof (struct ether_vlan_header) - ETHERFCSL - 3897 E1000G_IPALIGNPRESERVEROOM; 3898 break; 3899 case 3: 3900 if (mac->type >= e1000_82571) 3901 Adapter->default_mtu = MAXIMUM_MTU; 3902 else 3903 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3904 sizeof (struct ether_vlan_header) - ETHERFCSL - 3905 E1000G_IPALIGNPRESERVEROOM; 3906 break; 3907 default: 3908 Adapter->default_mtu = ETHERMTU; 3909 break; 3910 } /* switch */ 3911 3912 Adapter->max_frame_size = Adapter->default_mtu + 3913 sizeof (struct ether_vlan_header) + ETHERFCSL; 3914 3915 /* ich8 does not do jumbo frames */ 3916 if (mac->type == e1000_ich8lan) { 3917 Adapter->default_mtu = ETHERMTU; 3918 Adapter->max_frame_size = ETHERMTU + 3919 sizeof (struct ether_vlan_header) + ETHERFCSL; 3920 } 3921 3922 /* ich9 does not do jumbo frames on one phy type */ 3923 if ((mac->type == e1000_ich9lan) && 3924 (phy->type == e1000_phy_ife)) { 3925 Adapter->default_mtu = ETHERMTU; 3926 Adapter->max_frame_size = ETHERMTU + 3927 sizeof (struct ether_vlan_header) + ETHERFCSL; 3928 } 3929 } 3930 3931 static void 3932 arm_watchdog_timer(struct e1000g *Adapter) 3933 { 3934 Adapter->watchdog_tid = 3935 timeout(e1000g_local_timer, 3936 (void *)Adapter, 1 * drv_usectohz(1000000)); 3937 } 3938 #pragma inline(arm_watchdog_timer) 3939 3940 static void 3941 enable_watchdog_timer(struct e1000g *Adapter) 3942 { 3943 mutex_enter(&Adapter->watchdog_lock); 3944 3945 if (!Adapter->watchdog_timer_enabled) { 3946 Adapter->watchdog_timer_enabled = B_TRUE; 3947 Adapter->watchdog_timer_started = B_TRUE; 3948 arm_watchdog_timer(Adapter); 3949 } 3950 3951 mutex_exit(&Adapter->watchdog_lock); 3952 } 3953 3954 static void 3955 disable_watchdog_timer(struct e1000g *Adapter) 3956 { 3957 timeout_id_t tid; 3958 3959 mutex_enter(&Adapter->watchdog_lock); 3960 3961 Adapter->watchdog_timer_enabled = B_FALSE; 3962 Adapter->watchdog_timer_started = B_FALSE; 3963 tid = Adapter->watchdog_tid; 3964 Adapter->watchdog_tid = 0; 3965 3966 mutex_exit(&Adapter->watchdog_lock); 3967 3968 if (tid != 0) 3969 (void) untimeout(tid); 3970 } 3971 3972 static void 3973 start_watchdog_timer(struct e1000g *Adapter) 3974 { 3975 mutex_enter(&Adapter->watchdog_lock); 3976 3977 if (Adapter->watchdog_timer_enabled) { 3978 if (!Adapter->watchdog_timer_started) { 3979 Adapter->watchdog_timer_started = B_TRUE; 3980 arm_watchdog_timer(Adapter); 3981 } 3982 } 3983 3984 mutex_exit(&Adapter->watchdog_lock); 3985 } 3986 3987 static void 3988 restart_watchdog_timer(struct e1000g *Adapter) 3989 { 3990 mutex_enter(&Adapter->watchdog_lock); 3991 3992 if (Adapter->watchdog_timer_started) 3993 arm_watchdog_timer(Adapter); 3994 3995 mutex_exit(&Adapter->watchdog_lock); 3996 } 3997 3998 static void 3999 stop_watchdog_timer(struct e1000g *Adapter) 4000 { 4001 timeout_id_t tid; 4002 4003 mutex_enter(&Adapter->watchdog_lock); 4004 4005 Adapter->watchdog_timer_started = B_FALSE; 4006 tid = Adapter->watchdog_tid; 4007 Adapter->watchdog_tid = 0; 4008 4009 mutex_exit(&Adapter->watchdog_lock); 4010 4011 if (tid != 0) 4012 (void) untimeout(tid); 4013 } 4014 4015 static void 4016 stop_link_timer(struct e1000g *Adapter) 4017 { 4018 timeout_id_t tid; 4019 4020 /* Disable the link timer */ 4021 mutex_enter(&Adapter->link_lock); 4022 4023 tid = Adapter->link_tid; 4024 Adapter->link_tid = 0; 4025 4026 mutex_exit(&Adapter->link_lock); 4027 4028 if (tid != 0) 4029 (void) untimeout(tid); 4030 } 4031 4032 static void 4033 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4034 { 4035 timeout_id_t tid; 4036 4037 /* Disable the tx timer for 82547 chipset */ 4038 mutex_enter(&tx_ring->tx_lock); 4039 4040 tx_ring->timer_enable_82547 = B_FALSE; 4041 tid = tx_ring->timer_id_82547; 4042 tx_ring->timer_id_82547 = 0; 4043 4044 mutex_exit(&tx_ring->tx_lock); 4045 4046 if (tid != 0) 4047 (void) untimeout(tid); 4048 } 4049 4050 void 4051 e1000g_clear_interrupt(struct e1000g *Adapter) 4052 { 4053 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4054 0xffffffff & ~E1000_IMS_RXSEQ); 4055 } 4056 4057 void 4058 e1000g_mask_interrupt(struct e1000g *Adapter) 4059 { 4060 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4061 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4062 4063 if (Adapter->tx_intr_enable) 4064 e1000g_mask_tx_interrupt(Adapter); 4065 } 4066 4067 /* 4068 * This routine is called by e1000g_quiesce(), therefore must not block. 4069 */ 4070 void 4071 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4072 { 4073 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4074 } 4075 4076 void 4077 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4078 { 4079 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4080 } 4081 4082 void 4083 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4084 { 4085 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4086 } 4087 4088 static void 4089 e1000g_smartspeed(struct e1000g *Adapter) 4090 { 4091 struct e1000_hw *hw = &Adapter->shared; 4092 uint16_t phy_status; 4093 uint16_t phy_ctrl; 4094 4095 /* 4096 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4097 * advertising 1000Full, we don't even use the workaround 4098 */ 4099 if ((hw->phy.type != e1000_phy_igp) || 4100 !hw->mac.autoneg || 4101 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4102 return; 4103 4104 /* 4105 * True if this is the first call of this function or after every 4106 * 30 seconds of not having link 4107 */ 4108 if (Adapter->smartspeed == 0) { 4109 /* 4110 * If Master/Slave config fault is asserted twice, we 4111 * assume back-to-back 4112 */ 4113 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4114 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4115 return; 4116 4117 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4118 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4119 return; 4120 /* 4121 * We're assuming back-2-back because our status register 4122 * insists! there's a fault in the master/slave 4123 * relationship that was "negotiated" 4124 */ 4125 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4126 /* 4127 * Is the phy configured for manual configuration of 4128 * master/slave? 4129 */ 4130 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4131 /* 4132 * Yes. Then disable manual configuration (enable 4133 * auto configuration) of master/slave 4134 */ 4135 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4136 (void) e1000_write_phy_reg(hw, 4137 PHY_1000T_CTRL, phy_ctrl); 4138 /* 4139 * Effectively starting the clock 4140 */ 4141 Adapter->smartspeed++; 4142 /* 4143 * Restart autonegotiation 4144 */ 4145 if (!e1000_phy_setup_autoneg(hw) && 4146 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4147 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4148 MII_CR_RESTART_AUTO_NEG); 4149 (void) e1000_write_phy_reg(hw, 4150 PHY_CONTROL, phy_ctrl); 4151 } 4152 } 4153 return; 4154 /* 4155 * Has 6 seconds transpired still without link? Remember, 4156 * you should reset the smartspeed counter once you obtain 4157 * link 4158 */ 4159 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4160 /* 4161 * Yes. Remember, we did at the start determine that 4162 * there's a master/slave configuration fault, so we're 4163 * still assuming there's someone on the other end, but we 4164 * just haven't yet been able to talk to it. We then 4165 * re-enable auto configuration of master/slave to see if 4166 * we're running 2/3 pair cables. 4167 */ 4168 /* 4169 * If still no link, perhaps using 2/3 pair cable 4170 */ 4171 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4172 phy_ctrl |= CR_1000T_MS_ENABLE; 4173 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4174 /* 4175 * Restart autoneg with phy enabled for manual 4176 * configuration of master/slave 4177 */ 4178 if (!e1000_phy_setup_autoneg(hw) && 4179 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4180 phy_ctrl |= 4181 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4182 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4183 } 4184 /* 4185 * Hopefully, there are no more faults and we've obtained 4186 * link as a result. 4187 */ 4188 } 4189 /* 4190 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4191 * seconds) 4192 */ 4193 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4194 Adapter->smartspeed = 0; 4195 } 4196 4197 static boolean_t 4198 is_valid_mac_addr(uint8_t *mac_addr) 4199 { 4200 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4201 const uint8_t addr_test2[6] = 4202 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4203 4204 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4205 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4206 return (B_FALSE); 4207 4208 return (B_TRUE); 4209 } 4210 4211 /* 4212 * e1000g_stall_check - check for tx stall 4213 * 4214 * This function checks if the adapter is stalled (in transmit). 4215 * 4216 * It is called each time the watchdog timeout is invoked. 4217 * If the transmit descriptor reclaim continuously fails, 4218 * the watchdog value will increment by 1. If the watchdog 4219 * value exceeds the threshold, the adapter is assumed to 4220 * have stalled and need to be reset. 4221 */ 4222 static boolean_t 4223 e1000g_stall_check(struct e1000g *Adapter) 4224 { 4225 e1000g_tx_ring_t *tx_ring; 4226 4227 tx_ring = Adapter->tx_ring; 4228 4229 if (Adapter->link_state != LINK_STATE_UP) 4230 return (B_FALSE); 4231 4232 if (tx_ring->recycle_fail > 0) 4233 tx_ring->stall_watchdog++; 4234 else 4235 tx_ring->stall_watchdog = 0; 4236 4237 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4238 return (B_FALSE); 4239 4240 tx_ring->stall_watchdog = 0; 4241 tx_ring->recycle_fail = 0; 4242 4243 return (B_TRUE); 4244 } 4245 4246 #ifdef E1000G_DEBUG 4247 static enum ioc_reply 4248 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4249 { 4250 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4251 e1000g_peekpoke_t *ppd; 4252 uint64_t mem_va; 4253 uint64_t maxoff; 4254 boolean_t peek; 4255 4256 switch (iocp->ioc_cmd) { 4257 4258 case E1000G_IOC_REG_PEEK: 4259 peek = B_TRUE; 4260 break; 4261 4262 case E1000G_IOC_REG_POKE: 4263 peek = B_FALSE; 4264 break; 4265 4266 deault: 4267 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4268 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4269 iocp->ioc_cmd); 4270 return (IOC_INVAL); 4271 } 4272 4273 /* 4274 * Validate format of ioctl 4275 */ 4276 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4277 return (IOC_INVAL); 4278 if (mp->b_cont == NULL) 4279 return (IOC_INVAL); 4280 4281 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4282 4283 /* 4284 * Validate request parameters 4285 */ 4286 switch (ppd->pp_acc_space) { 4287 4288 default: 4289 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4290 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4291 ppd->pp_acc_space); 4292 return (IOC_INVAL); 4293 4294 case E1000G_PP_SPACE_REG: 4295 /* 4296 * Memory-mapped I/O space 4297 */ 4298 ASSERT(ppd->pp_acc_size == 4); 4299 if (ppd->pp_acc_size != 4) 4300 return (IOC_INVAL); 4301 4302 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4303 return (IOC_INVAL); 4304 4305 mem_va = 0; 4306 maxoff = 0x10000; 4307 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4308 break; 4309 4310 case E1000G_PP_SPACE_E1000G: 4311 /* 4312 * E1000g data structure! 4313 */ 4314 mem_va = (uintptr_t)e1000gp; 4315 maxoff = sizeof (struct e1000g); 4316 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4317 break; 4318 4319 } 4320 4321 if (ppd->pp_acc_offset >= maxoff) 4322 return (IOC_INVAL); 4323 4324 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4325 return (IOC_INVAL); 4326 4327 /* 4328 * All OK - go! 4329 */ 4330 ppd->pp_acc_offset += mem_va; 4331 (*ppfn)(e1000gp, ppd); 4332 return (peek ? IOC_REPLY : IOC_ACK); 4333 } 4334 4335 static void 4336 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4337 { 4338 ddi_acc_handle_t handle; 4339 uint32_t *regaddr; 4340 4341 handle = e1000gp->osdep.reg_handle; 4342 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4343 (uintptr_t)ppd->pp_acc_offset); 4344 4345 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4346 } 4347 4348 static void 4349 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4350 { 4351 ddi_acc_handle_t handle; 4352 uint32_t *regaddr; 4353 uint32_t value; 4354 4355 handle = e1000gp->osdep.reg_handle; 4356 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4357 (uintptr_t)ppd->pp_acc_offset); 4358 value = (uint32_t)ppd->pp_acc_data; 4359 4360 ddi_put32(handle, regaddr, value); 4361 } 4362 4363 static void 4364 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4365 { 4366 uint64_t value; 4367 void *vaddr; 4368 4369 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4370 4371 switch (ppd->pp_acc_size) { 4372 case 1: 4373 value = *(uint8_t *)vaddr; 4374 break; 4375 4376 case 2: 4377 value = *(uint16_t *)vaddr; 4378 break; 4379 4380 case 4: 4381 value = *(uint32_t *)vaddr; 4382 break; 4383 4384 case 8: 4385 value = *(uint64_t *)vaddr; 4386 break; 4387 } 4388 4389 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4390 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4391 (void *)e1000gp, (void *)ppd, value, vaddr); 4392 4393 ppd->pp_acc_data = value; 4394 } 4395 4396 static void 4397 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4398 { 4399 uint64_t value; 4400 void *vaddr; 4401 4402 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4403 value = ppd->pp_acc_data; 4404 4405 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4406 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4407 (void *)e1000gp, (void *)ppd, value, vaddr); 4408 4409 switch (ppd->pp_acc_size) { 4410 case 1: 4411 *(uint8_t *)vaddr = (uint8_t)value; 4412 break; 4413 4414 case 2: 4415 *(uint16_t *)vaddr = (uint16_t)value; 4416 break; 4417 4418 case 4: 4419 *(uint32_t *)vaddr = (uint32_t)value; 4420 break; 4421 4422 case 8: 4423 *(uint64_t *)vaddr = (uint64_t)value; 4424 break; 4425 } 4426 } 4427 #endif 4428 4429 /* 4430 * Loopback Support 4431 */ 4432 static lb_property_t lb_normal = 4433 { normal, "normal", E1000G_LB_NONE }; 4434 static lb_property_t lb_external1000 = 4435 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4436 static lb_property_t lb_external100 = 4437 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4438 static lb_property_t lb_external10 = 4439 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4440 static lb_property_t lb_phy = 4441 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4442 4443 static enum ioc_reply 4444 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4445 { 4446 lb_info_sz_t *lbsp; 4447 lb_property_t *lbpp; 4448 struct e1000_hw *hw; 4449 uint32_t *lbmp; 4450 uint32_t size; 4451 uint32_t value; 4452 4453 hw = &Adapter->shared; 4454 4455 if (mp->b_cont == NULL) 4456 return (IOC_INVAL); 4457 4458 if (!e1000g_check_loopback_support(hw)) { 4459 e1000g_log(NULL, CE_WARN, 4460 "Loopback is not supported on e1000g%d", Adapter->instance); 4461 return (IOC_INVAL); 4462 } 4463 4464 switch (iocp->ioc_cmd) { 4465 default: 4466 return (IOC_INVAL); 4467 4468 case LB_GET_INFO_SIZE: 4469 size = sizeof (lb_info_sz_t); 4470 if (iocp->ioc_count != size) 4471 return (IOC_INVAL); 4472 4473 rw_enter(&Adapter->chip_lock, RW_WRITER); 4474 e1000g_get_phy_state(Adapter); 4475 4476 /* 4477 * Workaround for hardware faults. In order to get a stable 4478 * state of phy, we will wait for a specific interval and 4479 * try again. The time delay is an experiential value based 4480 * on our testing. 4481 */ 4482 msec_delay(100); 4483 e1000g_get_phy_state(Adapter); 4484 rw_exit(&Adapter->chip_lock); 4485 4486 value = sizeof (lb_normal); 4487 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4488 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4489 (hw->phy.media_type == e1000_media_type_fiber) || 4490 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4491 value += sizeof (lb_phy); 4492 switch (hw->mac.type) { 4493 case e1000_82571: 4494 case e1000_82572: 4495 case e1000_80003es2lan: 4496 value += sizeof (lb_external1000); 4497 break; 4498 } 4499 } 4500 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4501 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4502 value += sizeof (lb_external100); 4503 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4504 value += sizeof (lb_external10); 4505 4506 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4507 *lbsp = value; 4508 break; 4509 4510 case LB_GET_INFO: 4511 value = sizeof (lb_normal); 4512 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4513 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4514 (hw->phy.media_type == e1000_media_type_fiber) || 4515 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4516 value += sizeof (lb_phy); 4517 switch (hw->mac.type) { 4518 case e1000_82571: 4519 case e1000_82572: 4520 case e1000_80003es2lan: 4521 value += sizeof (lb_external1000); 4522 break; 4523 } 4524 } 4525 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4526 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4527 value += sizeof (lb_external100); 4528 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4529 value += sizeof (lb_external10); 4530 4531 size = value; 4532 if (iocp->ioc_count != size) 4533 return (IOC_INVAL); 4534 4535 value = 0; 4536 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4537 lbpp[value++] = lb_normal; 4538 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4539 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4540 (hw->phy.media_type == e1000_media_type_fiber) || 4541 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4542 lbpp[value++] = lb_phy; 4543 switch (hw->mac.type) { 4544 case e1000_82571: 4545 case e1000_82572: 4546 case e1000_80003es2lan: 4547 lbpp[value++] = lb_external1000; 4548 break; 4549 } 4550 } 4551 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4552 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4553 lbpp[value++] = lb_external100; 4554 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4555 lbpp[value++] = lb_external10; 4556 break; 4557 4558 case LB_GET_MODE: 4559 size = sizeof (uint32_t); 4560 if (iocp->ioc_count != size) 4561 return (IOC_INVAL); 4562 4563 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4564 *lbmp = Adapter->loopback_mode; 4565 break; 4566 4567 case LB_SET_MODE: 4568 size = 0; 4569 if (iocp->ioc_count != sizeof (uint32_t)) 4570 return (IOC_INVAL); 4571 4572 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4573 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4574 return (IOC_INVAL); 4575 break; 4576 } 4577 4578 iocp->ioc_count = size; 4579 iocp->ioc_error = 0; 4580 4581 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4582 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4583 return (IOC_INVAL); 4584 } 4585 4586 return (IOC_REPLY); 4587 } 4588 4589 static boolean_t 4590 e1000g_check_loopback_support(struct e1000_hw *hw) 4591 { 4592 switch (hw->mac.type) { 4593 case e1000_82540: 4594 case e1000_82545: 4595 case e1000_82545_rev_3: 4596 case e1000_82546: 4597 case e1000_82546_rev_3: 4598 case e1000_82541: 4599 case e1000_82541_rev_2: 4600 case e1000_82547: 4601 case e1000_82547_rev_2: 4602 case e1000_82571: 4603 case e1000_82572: 4604 case e1000_82573: 4605 case e1000_80003es2lan: 4606 return (B_TRUE); 4607 } 4608 return (B_FALSE); 4609 } 4610 4611 static boolean_t 4612 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4613 { 4614 struct e1000_hw *hw; 4615 int i, times; 4616 boolean_t link_up; 4617 4618 if (mode == Adapter->loopback_mode) 4619 return (B_TRUE); 4620 4621 hw = &Adapter->shared; 4622 times = 0; 4623 4624 Adapter->loopback_mode = mode; 4625 4626 if (mode == E1000G_LB_NONE) { 4627 /* Reset the chip */ 4628 hw->phy.autoneg_wait_to_complete = B_TRUE; 4629 (void) e1000g_reset_adapter(Adapter); 4630 hw->phy.autoneg_wait_to_complete = B_FALSE; 4631 return (B_TRUE); 4632 } 4633 4634 again: 4635 4636 rw_enter(&Adapter->chip_lock, RW_WRITER); 4637 4638 switch (mode) { 4639 default: 4640 rw_exit(&Adapter->chip_lock); 4641 return (B_FALSE); 4642 4643 case E1000G_LB_EXTERNAL_1000: 4644 e1000g_set_external_loopback_1000(Adapter); 4645 break; 4646 4647 case E1000G_LB_EXTERNAL_100: 4648 e1000g_set_external_loopback_100(Adapter); 4649 break; 4650 4651 case E1000G_LB_EXTERNAL_10: 4652 e1000g_set_external_loopback_10(Adapter); 4653 break; 4654 4655 case E1000G_LB_INTERNAL_PHY: 4656 e1000g_set_internal_loopback(Adapter); 4657 break; 4658 } 4659 4660 times++; 4661 4662 rw_exit(&Adapter->chip_lock); 4663 4664 /* Wait for link up */ 4665 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4666 msec_delay(100); 4667 4668 rw_enter(&Adapter->chip_lock, RW_WRITER); 4669 4670 link_up = e1000g_link_up(Adapter); 4671 4672 rw_exit(&Adapter->chip_lock); 4673 4674 if (!link_up) { 4675 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4676 "Failed to get the link up"); 4677 if (times < 2) { 4678 /* Reset the link */ 4679 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4680 "Reset the link ..."); 4681 (void) e1000g_reset_adapter(Adapter); 4682 goto again; 4683 } 4684 } 4685 4686 return (B_TRUE); 4687 } 4688 4689 /* 4690 * The following loopback settings are from Intel's technical 4691 * document - "How To Loopback". All the register settings and 4692 * time delay values are directly inherited from the document 4693 * without more explanations available. 4694 */ 4695 static void 4696 e1000g_set_internal_loopback(struct e1000g *Adapter) 4697 { 4698 struct e1000_hw *hw; 4699 uint32_t ctrl; 4700 uint32_t status; 4701 uint16_t phy_ctrl; 4702 uint32_t txcw; 4703 4704 hw = &Adapter->shared; 4705 4706 /* Disable Smart Power Down */ 4707 phy_spd_state(hw, B_FALSE); 4708 4709 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4710 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4711 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4712 4713 switch (hw->mac.type) { 4714 case e1000_82540: 4715 case e1000_82545: 4716 case e1000_82545_rev_3: 4717 case e1000_82546: 4718 case e1000_82546_rev_3: 4719 case e1000_82573: 4720 /* Auto-MDI/MDIX off */ 4721 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4722 /* Reset PHY to update Auto-MDI/MDIX */ 4723 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4724 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4725 /* Reset PHY to auto-neg off and force 1000 */ 4726 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4727 phy_ctrl | MII_CR_RESET); 4728 /* 4729 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4730 * See comments above e1000g_set_internal_loopback() for the 4731 * background. 4732 */ 4733 (void) e1000_write_phy_reg(hw, 29, 0x001F); 4734 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 4735 (void) e1000_write_phy_reg(hw, 29, 0x001A); 4736 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 4737 break; 4738 case e1000_80003es2lan: 4739 /* Force Link Up */ 4740 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 4741 0x1CC); 4742 /* Sets PCS loopback at 1Gbs */ 4743 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 4744 0x1046); 4745 break; 4746 } 4747 4748 /* Set loopback */ 4749 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4750 4751 msec_delay(250); 4752 4753 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4754 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4755 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4756 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4757 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4758 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4759 E1000_CTRL_FD); /* Force Duplex to FULL */ 4760 4761 switch (hw->mac.type) { 4762 case e1000_82540: 4763 case e1000_82545: 4764 case e1000_82545_rev_3: 4765 case e1000_82546: 4766 case e1000_82546_rev_3: 4767 /* 4768 * For some serdes we'll need to commit the writes now 4769 * so that the status is updated on link 4770 */ 4771 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4772 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4773 msec_delay(100); 4774 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4775 } 4776 4777 if (hw->phy.media_type == e1000_media_type_copper) { 4778 /* Invert Loss of Signal */ 4779 ctrl |= E1000_CTRL_ILOS; 4780 } else { 4781 /* Set ILOS on fiber nic if half duplex is detected */ 4782 status = E1000_READ_REG(hw, E1000_STATUS); 4783 if ((status & E1000_STATUS_FD) == 0) 4784 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4785 } 4786 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4787 break; 4788 4789 case e1000_82571: 4790 case e1000_82572: 4791 /* 4792 * The fiber/SerDes versions of this adapter do not contain an 4793 * accessible PHY. Therefore, loopback beyond MAC must be done 4794 * using SerDes analog loopback. 4795 */ 4796 if (hw->phy.media_type != e1000_media_type_copper) { 4797 status = E1000_READ_REG(hw, E1000_STATUS); 4798 /* Set ILOS on fiber nic if half duplex is detected */ 4799 if (((status & E1000_STATUS_LU) == 0) || 4800 ((status & E1000_STATUS_FD) == 0) || 4801 (hw->phy.media_type == 4802 e1000_media_type_internal_serdes)) 4803 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4804 4805 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4806 txcw = E1000_READ_REG(hw, E1000_TXCW); 4807 txcw &= ~((uint32_t)1 << 31); 4808 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4809 4810 /* 4811 * Write 0x410 to Serdes Control register 4812 * to enable Serdes analog loopback 4813 */ 4814 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4815 msec_delay(10); 4816 } 4817 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4818 break; 4819 4820 case e1000_82573: 4821 ctrl |= E1000_CTRL_ILOS; 4822 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4823 break; 4824 } 4825 } 4826 4827 static void 4828 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4829 { 4830 struct e1000_hw *hw; 4831 uint32_t rctl; 4832 uint32_t ctrl_ext; 4833 uint32_t ctrl; 4834 uint32_t status; 4835 uint32_t txcw; 4836 uint16_t phydata; 4837 4838 hw = &Adapter->shared; 4839 4840 /* Disable Smart Power Down */ 4841 phy_spd_state(hw, B_FALSE); 4842 4843 switch (hw->mac.type) { 4844 case e1000_82571: 4845 case e1000_82572: 4846 switch (hw->phy.media_type) { 4847 case e1000_media_type_copper: 4848 /* Force link up (Must be done before the PHY writes) */ 4849 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4850 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4851 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4852 4853 rctl = E1000_READ_REG(hw, E1000_RCTL); 4854 rctl |= (E1000_RCTL_EN | 4855 E1000_RCTL_SBP | 4856 E1000_RCTL_UPE | 4857 E1000_RCTL_MPE | 4858 E1000_RCTL_LPE | 4859 E1000_RCTL_BAM); /* 0x803E */ 4860 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4861 4862 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4863 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4864 E1000_CTRL_EXT_SDP6_DATA | 4865 E1000_CTRL_EXT_SDP7_DATA | 4866 E1000_CTRL_EXT_SDP4_DIR | 4867 E1000_CTRL_EXT_SDP6_DIR | 4868 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4869 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4870 4871 /* 4872 * This sequence tunes the PHY's SDP and no customer 4873 * settable values. For background, see comments above 4874 * e1000g_set_internal_loopback(). 4875 */ 4876 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 4877 msec_delay(10); 4878 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 4879 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 4880 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 4881 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 4882 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 4883 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 4884 4885 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 4886 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4887 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4888 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4889 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4890 4891 msec_delay(50); 4892 break; 4893 case e1000_media_type_fiber: 4894 case e1000_media_type_internal_serdes: 4895 status = E1000_READ_REG(hw, E1000_STATUS); 4896 if (((status & E1000_STATUS_LU) == 0) || 4897 (hw->phy.media_type == 4898 e1000_media_type_internal_serdes)) { 4899 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4900 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4901 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4902 } 4903 4904 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4905 txcw = E1000_READ_REG(hw, E1000_TXCW); 4906 txcw &= ~((uint32_t)1 << 31); 4907 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4908 4909 /* 4910 * Write 0x410 to Serdes Control register 4911 * to enable Serdes analog loopback 4912 */ 4913 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4914 msec_delay(10); 4915 break; 4916 default: 4917 break; 4918 } 4919 break; 4920 case e1000_80003es2lan: 4921 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 4922 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 4923 phydata | (1 << 5)); 4924 Adapter->param_adv_autoneg = 1; 4925 Adapter->param_adv_1000fdx = 1; 4926 (void) e1000g_reset_link(Adapter); 4927 break; 4928 } 4929 } 4930 4931 static void 4932 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4933 { 4934 struct e1000_hw *hw; 4935 uint32_t ctrl; 4936 uint16_t phy_ctrl; 4937 4938 hw = &Adapter->shared; 4939 4940 /* Disable Smart Power Down */ 4941 phy_spd_state(hw, B_FALSE); 4942 4943 phy_ctrl = (MII_CR_FULL_DUPLEX | 4944 MII_CR_SPEED_100); 4945 4946 /* Force 100/FD, reset PHY */ 4947 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4948 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4949 msec_delay(10); 4950 4951 /* Force 100/FD */ 4952 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4953 phy_ctrl); /* 0x2100 */ 4954 msec_delay(10); 4955 4956 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4957 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4958 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4959 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4960 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4961 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4962 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4963 E1000_CTRL_FD); /* Force Duplex to FULL */ 4964 4965 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4966 } 4967 4968 static void 4969 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4970 { 4971 struct e1000_hw *hw; 4972 uint32_t ctrl; 4973 uint16_t phy_ctrl; 4974 4975 hw = &Adapter->shared; 4976 4977 /* Disable Smart Power Down */ 4978 phy_spd_state(hw, B_FALSE); 4979 4980 phy_ctrl = (MII_CR_FULL_DUPLEX | 4981 MII_CR_SPEED_10); 4982 4983 /* Force 10/FD, reset PHY */ 4984 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4985 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4986 msec_delay(10); 4987 4988 /* Force 10/FD */ 4989 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4990 phy_ctrl); /* 0x0100 */ 4991 msec_delay(10); 4992 4993 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4994 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4995 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4996 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4997 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4998 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4999 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5000 E1000_CTRL_FD); /* Force Duplex to FULL */ 5001 5002 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5003 } 5004 5005 #ifdef __sparc 5006 static boolean_t 5007 e1000g_find_mac_address(struct e1000g *Adapter) 5008 { 5009 struct e1000_hw *hw = &Adapter->shared; 5010 uchar_t *bytes; 5011 struct ether_addr sysaddr; 5012 uint_t nelts; 5013 int err; 5014 boolean_t found = B_FALSE; 5015 5016 /* 5017 * The "vendor's factory-set address" may already have 5018 * been extracted from the chip, but if the property 5019 * "local-mac-address" is set we use that instead. 5020 * 5021 * We check whether it looks like an array of 6 5022 * bytes (which it should, if OBP set it). If we can't 5023 * make sense of it this way, we'll ignore it. 5024 */ 5025 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5026 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5027 if (err == DDI_PROP_SUCCESS) { 5028 if (nelts == ETHERADDRL) { 5029 while (nelts--) 5030 hw->mac.addr[nelts] = bytes[nelts]; 5031 found = B_TRUE; 5032 } 5033 ddi_prop_free(bytes); 5034 } 5035 5036 /* 5037 * Look up the OBP property "local-mac-address?". If the user has set 5038 * 'local-mac-address? = false', use "the system address" instead. 5039 */ 5040 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5041 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5042 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5043 if (localetheraddr(NULL, &sysaddr) != 0) { 5044 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5045 found = B_TRUE; 5046 } 5047 } 5048 ddi_prop_free(bytes); 5049 } 5050 5051 /* 5052 * Finally(!), if there's a valid "mac-address" property (created 5053 * if we netbooted from this interface), we must use this instead 5054 * of any of the above to ensure that the NFS/install server doesn't 5055 * get confused by the address changing as Solaris takes over! 5056 */ 5057 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5058 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5059 if (err == DDI_PROP_SUCCESS) { 5060 if (nelts == ETHERADDRL) { 5061 while (nelts--) 5062 hw->mac.addr[nelts] = bytes[nelts]; 5063 found = B_TRUE; 5064 } 5065 ddi_prop_free(bytes); 5066 } 5067 5068 if (found) { 5069 bcopy(hw->mac.addr, hw->mac.perm_addr, 5070 ETHERADDRL); 5071 } 5072 5073 return (found); 5074 } 5075 #endif 5076 5077 static int 5078 e1000g_add_intrs(struct e1000g *Adapter) 5079 { 5080 dev_info_t *devinfo; 5081 int intr_types; 5082 int rc; 5083 5084 devinfo = Adapter->dip; 5085 5086 /* Get supported interrupt types */ 5087 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5088 5089 if (rc != DDI_SUCCESS) { 5090 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5091 "Get supported interrupt types failed: %d\n", rc); 5092 return (DDI_FAILURE); 5093 } 5094 5095 /* 5096 * Based on Intel Technical Advisory document (TA-160), there are some 5097 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5098 * that it supports MSI, but in fact has problems. 5099 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5100 * PCI/PCI-X NICs. 5101 */ 5102 if (Adapter->shared.mac.type < e1000_82571) 5103 Adapter->msi_enable = B_FALSE; 5104 5105 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5106 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5107 5108 if (rc != DDI_SUCCESS) { 5109 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5110 "Add MSI failed, trying Legacy interrupts\n"); 5111 } else { 5112 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5113 } 5114 } 5115 5116 if ((Adapter->intr_type == 0) && 5117 (intr_types & DDI_INTR_TYPE_FIXED)) { 5118 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5119 5120 if (rc != DDI_SUCCESS) { 5121 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5122 "Add Legacy interrupts failed\n"); 5123 return (DDI_FAILURE); 5124 } 5125 5126 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5127 } 5128 5129 if (Adapter->intr_type == 0) { 5130 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5131 "No interrupts registered\n"); 5132 return (DDI_FAILURE); 5133 } 5134 5135 return (DDI_SUCCESS); 5136 } 5137 5138 /* 5139 * e1000g_intr_add() handles MSI/Legacy interrupts 5140 */ 5141 static int 5142 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5143 { 5144 dev_info_t *devinfo; 5145 int count, avail, actual; 5146 int x, y, rc, inum = 0; 5147 int flag; 5148 ddi_intr_handler_t *intr_handler; 5149 5150 devinfo = Adapter->dip; 5151 5152 /* get number of interrupts */ 5153 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5154 if ((rc != DDI_SUCCESS) || (count == 0)) { 5155 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5156 "Get interrupt number failed. Return: %d, count: %d\n", 5157 rc, count); 5158 return (DDI_FAILURE); 5159 } 5160 5161 /* get number of available interrupts */ 5162 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5163 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5164 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5165 "Get interrupt available number failed. " 5166 "Return: %d, available: %d\n", rc, avail); 5167 return (DDI_FAILURE); 5168 } 5169 5170 if (avail < count) { 5171 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5172 "Interrupts count: %d, available: %d\n", 5173 count, avail); 5174 } 5175 5176 /* Allocate an array of interrupt handles */ 5177 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5178 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5179 5180 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5181 flag = DDI_INTR_ALLOC_NORMAL; 5182 5183 /* call ddi_intr_alloc() */ 5184 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5185 count, &actual, flag); 5186 5187 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5188 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5189 "Allocate interrupts failed: %d\n", rc); 5190 5191 kmem_free(Adapter->htable, Adapter->intr_size); 5192 return (DDI_FAILURE); 5193 } 5194 5195 if (actual < count) { 5196 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5197 "Interrupts requested: %d, received: %d\n", 5198 count, actual); 5199 } 5200 5201 Adapter->intr_cnt = actual; 5202 5203 /* Get priority for first msi, assume remaining are all the same */ 5204 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5205 5206 if (rc != DDI_SUCCESS) { 5207 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5208 "Get interrupt priority failed: %d\n", rc); 5209 5210 /* Free already allocated intr */ 5211 for (y = 0; y < actual; y++) 5212 (void) ddi_intr_free(Adapter->htable[y]); 5213 5214 kmem_free(Adapter->htable, Adapter->intr_size); 5215 return (DDI_FAILURE); 5216 } 5217 5218 /* 5219 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5220 * use the interrupt service routine e1000g_intr_pciexpress() 5221 * to avoid interrupt stealing when sharing interrupt with other 5222 * devices. 5223 */ 5224 if (Adapter->shared.mac.type < e1000_82571) 5225 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5226 else 5227 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5228 5229 /* Call ddi_intr_add_handler() */ 5230 for (x = 0; x < actual; x++) { 5231 rc = ddi_intr_add_handler(Adapter->htable[x], 5232 intr_handler, (caddr_t)Adapter, NULL); 5233 5234 if (rc != DDI_SUCCESS) { 5235 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5236 "Add interrupt handler failed: %d\n", rc); 5237 5238 /* Remove already added handler */ 5239 for (y = 0; y < x; y++) 5240 (void) ddi_intr_remove_handler( 5241 Adapter->htable[y]); 5242 5243 /* Free already allocated intr */ 5244 for (y = 0; y < actual; y++) 5245 (void) ddi_intr_free(Adapter->htable[y]); 5246 5247 kmem_free(Adapter->htable, Adapter->intr_size); 5248 return (DDI_FAILURE); 5249 } 5250 } 5251 5252 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5253 5254 if (rc != DDI_SUCCESS) { 5255 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5256 "Get interrupt cap failed: %d\n", rc); 5257 5258 /* Free already allocated intr */ 5259 for (y = 0; y < actual; y++) { 5260 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5261 (void) ddi_intr_free(Adapter->htable[y]); 5262 } 5263 5264 kmem_free(Adapter->htable, Adapter->intr_size); 5265 return (DDI_FAILURE); 5266 } 5267 5268 return (DDI_SUCCESS); 5269 } 5270 5271 static int 5272 e1000g_rem_intrs(struct e1000g *Adapter) 5273 { 5274 int x; 5275 int rc; 5276 5277 for (x = 0; x < Adapter->intr_cnt; x++) { 5278 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5279 if (rc != DDI_SUCCESS) { 5280 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5281 "Remove intr handler failed: %d\n", rc); 5282 return (DDI_FAILURE); 5283 } 5284 5285 rc = ddi_intr_free(Adapter->htable[x]); 5286 if (rc != DDI_SUCCESS) { 5287 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5288 "Free intr failed: %d\n", rc); 5289 return (DDI_FAILURE); 5290 } 5291 } 5292 5293 kmem_free(Adapter->htable, Adapter->intr_size); 5294 5295 return (DDI_SUCCESS); 5296 } 5297 5298 static int 5299 e1000g_enable_intrs(struct e1000g *Adapter) 5300 { 5301 int x; 5302 int rc; 5303 5304 /* Enable interrupts */ 5305 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5306 /* Call ddi_intr_block_enable() for MSI */ 5307 rc = ddi_intr_block_enable(Adapter->htable, 5308 Adapter->intr_cnt); 5309 if (rc != DDI_SUCCESS) { 5310 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5311 "Enable block intr failed: %d\n", rc); 5312 return (DDI_FAILURE); 5313 } 5314 } else { 5315 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5316 for (x = 0; x < Adapter->intr_cnt; x++) { 5317 rc = ddi_intr_enable(Adapter->htable[x]); 5318 if (rc != DDI_SUCCESS) { 5319 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5320 "Enable intr failed: %d\n", rc); 5321 return (DDI_FAILURE); 5322 } 5323 } 5324 } 5325 5326 return (DDI_SUCCESS); 5327 } 5328 5329 static int 5330 e1000g_disable_intrs(struct e1000g *Adapter) 5331 { 5332 int x; 5333 int rc; 5334 5335 /* Disable all interrupts */ 5336 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5337 rc = ddi_intr_block_disable(Adapter->htable, 5338 Adapter->intr_cnt); 5339 if (rc != DDI_SUCCESS) { 5340 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5341 "Disable block intr failed: %d\n", rc); 5342 return (DDI_FAILURE); 5343 } 5344 } else { 5345 for (x = 0; x < Adapter->intr_cnt; x++) { 5346 rc = ddi_intr_disable(Adapter->htable[x]); 5347 if (rc != DDI_SUCCESS) { 5348 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5349 "Disable intr failed: %d\n", rc); 5350 return (DDI_FAILURE); 5351 } 5352 } 5353 } 5354 5355 return (DDI_SUCCESS); 5356 } 5357 5358 /* 5359 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5360 */ 5361 static void 5362 e1000g_get_phy_state(struct e1000g *Adapter) 5363 { 5364 struct e1000_hw *hw = &Adapter->shared; 5365 5366 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5367 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5368 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5369 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5370 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5371 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5372 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5373 &Adapter->phy_1000t_status); 5374 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5375 5376 Adapter->param_autoneg_cap = 5377 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5378 Adapter->param_pause_cap = 5379 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5380 Adapter->param_asym_pause_cap = 5381 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5382 Adapter->param_1000fdx_cap = 5383 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5384 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5385 Adapter->param_1000hdx_cap = 5386 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5387 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5388 Adapter->param_100t4_cap = 5389 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5390 Adapter->param_100fdx_cap = 5391 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5392 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5393 Adapter->param_100hdx_cap = 5394 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5395 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5396 Adapter->param_10fdx_cap = 5397 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5398 Adapter->param_10hdx_cap = 5399 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5400 5401 Adapter->param_adv_autoneg = hw->mac.autoneg; 5402 Adapter->param_adv_pause = 5403 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5404 Adapter->param_adv_asym_pause = 5405 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5406 Adapter->param_adv_1000hdx = 5407 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5408 Adapter->param_adv_100t4 = 5409 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5410 if (Adapter->param_adv_autoneg == 1) { 5411 Adapter->param_adv_1000fdx = 5412 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5413 Adapter->param_adv_100fdx = 5414 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5415 Adapter->param_adv_100hdx = 5416 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5417 Adapter->param_adv_10fdx = 5418 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5419 Adapter->param_adv_10hdx = 5420 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5421 } 5422 5423 Adapter->param_lp_autoneg = 5424 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5425 Adapter->param_lp_pause = 5426 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5427 Adapter->param_lp_asym_pause = 5428 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5429 Adapter->param_lp_1000fdx = 5430 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5431 Adapter->param_lp_1000hdx = 5432 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5433 Adapter->param_lp_100t4 = 5434 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5435 Adapter->param_lp_100fdx = 5436 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5437 Adapter->param_lp_100hdx = 5438 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5439 Adapter->param_lp_10fdx = 5440 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5441 Adapter->param_lp_10hdx = 5442 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5443 } 5444 5445 /* 5446 * FMA support 5447 */ 5448 5449 int 5450 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5451 { 5452 ddi_fm_error_t de; 5453 5454 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5455 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5456 return (de.fme_status); 5457 } 5458 5459 int 5460 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5461 { 5462 ddi_fm_error_t de; 5463 5464 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5465 return (de.fme_status); 5466 } 5467 5468 /* 5469 * The IO fault service error handling callback function 5470 */ 5471 /* ARGSUSED2 */ 5472 static int 5473 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5474 { 5475 /* 5476 * as the driver can always deal with an error in any dma or 5477 * access handle, we can just return the fme_status value. 5478 */ 5479 pci_ereport_post(dip, err, NULL); 5480 return (err->fme_status); 5481 } 5482 5483 static void 5484 e1000g_fm_init(struct e1000g *Adapter) 5485 { 5486 ddi_iblock_cookie_t iblk; 5487 int fma_acc_flag, fma_dma_flag; 5488 5489 /* Only register with IO Fault Services if we have some capability */ 5490 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5491 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5492 fma_acc_flag = 1; 5493 } else { 5494 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5495 fma_acc_flag = 0; 5496 } 5497 5498 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5499 fma_dma_flag = 1; 5500 } else { 5501 fma_dma_flag = 0; 5502 } 5503 5504 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5505 5506 if (Adapter->fm_capabilities) { 5507 5508 /* Register capabilities with IO Fault Services */ 5509 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5510 5511 /* 5512 * Initialize pci ereport capabilities if ereport capable 5513 */ 5514 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5515 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5516 pci_ereport_setup(Adapter->dip); 5517 5518 /* 5519 * Register error callback if error callback capable 5520 */ 5521 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5522 ddi_fm_handler_register(Adapter->dip, 5523 e1000g_fm_error_cb, (void*) Adapter); 5524 } 5525 } 5526 5527 static void 5528 e1000g_fm_fini(struct e1000g *Adapter) 5529 { 5530 /* Only unregister FMA capabilities if we registered some */ 5531 if (Adapter->fm_capabilities) { 5532 5533 /* 5534 * Release any resources allocated by pci_ereport_setup() 5535 */ 5536 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5537 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5538 pci_ereport_teardown(Adapter->dip); 5539 5540 /* 5541 * Un-register error callback if error callback capable 5542 */ 5543 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5544 ddi_fm_handler_unregister(Adapter->dip); 5545 5546 /* Unregister from IO Fault Services */ 5547 ddi_fm_fini(Adapter->dip); 5548 } 5549 } 5550 5551 void 5552 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5553 { 5554 uint64_t ena; 5555 char buf[FM_MAX_CLASS]; 5556 5557 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5558 ena = fm_ena_generate(0, FM_ENA_FMT1); 5559 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5560 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5561 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5562 } 5563 } 5564 5565 /* 5566 * quiesce(9E) entry point. 5567 * 5568 * This function is called when the system is single-threaded at high 5569 * PIL with preemption disabled. Therefore, this function must not be 5570 * blocked. 5571 * 5572 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5573 * DDI_FAILURE indicates an error condition and should almost never happen. 5574 */ 5575 static int 5576 e1000g_quiesce(dev_info_t *devinfo) 5577 { 5578 struct e1000g *Adapter; 5579 5580 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 5581 5582 if (Adapter == NULL) 5583 return (DDI_FAILURE); 5584 5585 e1000g_clear_all_interrupts(Adapter); 5586 5587 (void) e1000_reset_hw(&Adapter->shared); 5588 5589 /* Setup our HW Tx Head & Tail descriptor pointers */ 5590 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 5591 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 5592 5593 /* Setup our HW Rx Head & Tail descriptor pointers */ 5594 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 5595 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 5596 5597 return (DDI_SUCCESS); 5598 } 5599 5600 static int 5601 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5602 uint_t pr_valsize, void *pr_val) 5603 { 5604 link_flowctrl_t fl; 5605 int err = 0; 5606 5607 ASSERT(pr_valsize > 0); 5608 switch (pr_num) { 5609 case MAC_PROP_AUTONEG: 5610 *(uint8_t *)pr_val = 5611 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5612 break; 5613 case MAC_PROP_FLOWCTRL: 5614 if (pr_valsize < sizeof (link_flowctrl_t)) 5615 return (EINVAL); 5616 fl = LINK_FLOWCTRL_BI; 5617 bcopy(&fl, pr_val, sizeof (fl)); 5618 break; 5619 case MAC_PROP_ADV_1000FDX_CAP: 5620 case MAC_PROP_EN_1000FDX_CAP: 5621 *(uint8_t *)pr_val = 5622 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5623 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5624 break; 5625 case MAC_PROP_ADV_1000HDX_CAP: 5626 case MAC_PROP_EN_1000HDX_CAP: 5627 *(uint8_t *)pr_val = 5628 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5629 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5630 break; 5631 case MAC_PROP_ADV_100FDX_CAP: 5632 case MAC_PROP_EN_100FDX_CAP: 5633 *(uint8_t *)pr_val = 5634 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5635 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5636 break; 5637 case MAC_PROP_ADV_100HDX_CAP: 5638 case MAC_PROP_EN_100HDX_CAP: 5639 *(uint8_t *)pr_val = 5640 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5641 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5642 break; 5643 case MAC_PROP_ADV_10FDX_CAP: 5644 case MAC_PROP_EN_10FDX_CAP: 5645 *(uint8_t *)pr_val = 5646 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5647 break; 5648 case MAC_PROP_ADV_10HDX_CAP: 5649 case MAC_PROP_EN_10HDX_CAP: 5650 *(uint8_t *)pr_val = 5651 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5652 break; 5653 default: 5654 err = ENOTSUP; 5655 break; 5656 } 5657 return (err); 5658 } 5659 5660 /* 5661 * synchronize the adv* and en* parameters. 5662 * 5663 * See comments in <sys/dld.h> for details of the *_en_* 5664 * parameters. The usage of ndd for setting adv parameters will 5665 * synchronize all the en parameters with the e1000g parameters, 5666 * implicitly disabling any settings made via dladm. 5667 */ 5668 static void 5669 e1000g_param_sync(struct e1000g *Adapter) 5670 { 5671 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5672 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5673 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5674 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5675 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5676 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5677 } 5678 5679 /* 5680 * e1000g_get_driver_control - tell manageability firmware that the driver 5681 * has control. 5682 */ 5683 static void 5684 e1000g_get_driver_control(struct e1000_hw *hw) 5685 { 5686 uint32_t ctrl_ext; 5687 uint32_t swsm; 5688 5689 /* tell manageability firmware the driver has taken over */ 5690 switch (hw->mac.type) { 5691 case e1000_82573: 5692 swsm = E1000_READ_REG(hw, E1000_SWSM); 5693 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 5694 break; 5695 case e1000_82571: 5696 case e1000_82572: 5697 case e1000_82574: 5698 case e1000_80003es2lan: 5699 case e1000_ich8lan: 5700 case e1000_ich9lan: 5701 case e1000_ich10lan: 5702 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5703 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5704 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 5705 break; 5706 default: 5707 /* no manageability firmware: do nothing */ 5708 break; 5709 } 5710 } 5711 5712 /* 5713 * e1000g_release_driver_control - tell manageability firmware that the driver 5714 * has released control. 5715 */ 5716 static void 5717 e1000g_release_driver_control(struct e1000_hw *hw) 5718 { 5719 uint32_t ctrl_ext; 5720 uint32_t swsm; 5721 5722 /* tell manageability firmware the driver has released control */ 5723 switch (hw->mac.type) { 5724 case e1000_82573: 5725 swsm = E1000_READ_REG(hw, E1000_SWSM); 5726 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 5727 break; 5728 case e1000_82571: 5729 case e1000_82572: 5730 case e1000_82574: 5731 case e1000_80003es2lan: 5732 case e1000_ich8lan: 5733 case e1000_ich9lan: 5734 case e1000_ich10lan: 5735 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5736 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5737 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 5738 break; 5739 default: 5740 /* no manageability firmware: do nothing */ 5741 break; 5742 } 5743 } 5744 5745 /* 5746 * Restore e1000g promiscuous mode. 5747 */ 5748 static void 5749 e1000g_restore_promisc(struct e1000g *Adapter) 5750 { 5751 if (Adapter->e1000g_promisc) { 5752 uint32_t rctl; 5753 5754 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 5755 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 5756 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 5757 } 5758 } 5759