1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include "e1000g_sw.h" 47 #include "e1000g_debug.h" 48 49 static char ident[] = "Intel PRO/1000 Ethernet 5.2.11"; 50 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 51 static char e1000g_version[] = "Driver Ver. 5.2.11"; 52 53 /* 54 * Proto types for DDI entry points 55 */ 56 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 57 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 58 59 /* 60 * init and intr routines prototype 61 */ 62 static int e1000g_resume(dev_info_t *); 63 static int e1000g_suspend(dev_info_t *); 64 static uint_t e1000g_intr_pciexpress(caddr_t); 65 static uint_t e1000g_intr(caddr_t); 66 static void e1000g_intr_work(struct e1000g *, uint32_t); 67 #pragma inline(e1000g_intr_work) 68 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 69 #pragma inline(e1000g_get_itr) 70 static int e1000g_init(struct e1000g *); 71 static int e1000g_start(struct e1000g *, boolean_t); 72 static void e1000g_stop(struct e1000g *, boolean_t); 73 static int e1000g_m_start(void *); 74 static void e1000g_m_stop(void *); 75 static int e1000g_m_promisc(void *, boolean_t); 76 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 77 static int e1000g_m_unicst(void *, const uint8_t *); 78 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 79 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 80 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 81 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 82 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 83 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 84 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 85 uint_t, const void *); 86 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 87 uint_t, uint_t, void *); 88 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 89 const void *); 90 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 91 uint_t, void *); 92 static void e1000g_init_locks(struct e1000g *); 93 static void e1000g_destroy_locks(struct e1000g *); 94 static int e1000g_identify_hardware(struct e1000g *); 95 static int e1000g_regs_map(struct e1000g *); 96 static int e1000g_set_driver_params(struct e1000g *); 97 static void e1000g_set_bufsize(struct e1000g *); 98 static int e1000g_register_mac(struct e1000g *); 99 static boolean_t e1000g_rx_drain(struct e1000g *); 100 static boolean_t e1000g_tx_drain(struct e1000g *); 101 static void e1000g_init_unicst(struct e1000g *); 102 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 103 104 /* 105 * Local routines 106 */ 107 static void e1000g_tx_clean(struct e1000g *); 108 static void e1000g_rx_clean(struct e1000g *); 109 static void e1000g_link_timer(void *); 110 static void e1000g_local_timer(void *); 111 static boolean_t e1000g_link_check(struct e1000g *); 112 static boolean_t e1000g_stall_check(struct e1000g *); 113 static void e1000g_smartspeed(struct e1000g *); 114 static void e1000g_get_conf(struct e1000g *); 115 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 116 static void enable_watchdog_timer(struct e1000g *); 117 static void disable_watchdog_timer(struct e1000g *); 118 static void start_watchdog_timer(struct e1000g *); 119 static void restart_watchdog_timer(struct e1000g *); 120 static void stop_watchdog_timer(struct e1000g *); 121 static void stop_link_timer(struct e1000g *); 122 static void stop_82547_timer(e1000g_tx_ring_t *); 123 static void e1000g_force_speed_duplex(struct e1000g *); 124 static void e1000g_get_max_frame_size(struct e1000g *); 125 static boolean_t is_valid_mac_addr(uint8_t *); 126 static void e1000g_unattach(dev_info_t *, struct e1000g *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 154 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 155 const void *impl_data); 156 static void e1000g_fm_init(struct e1000g *Adapter); 157 static void e1000g_fm_fini(struct e1000g *Adapter); 158 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 159 static void e1000g_param_sync(struct e1000g *); 160 161 mac_priv_prop_t e1000g_priv_props[] = { 162 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 164 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 167 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 168 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 169 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 170 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 171 {"_intr_adaptive", MAC_PROP_PERM_RW}, 172 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 173 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 174 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 175 {"_tx_recycle_num", MAC_PROP_PERM_RW} 176 }; 177 #define E1000G_MAX_PRIV_PROPS \ 178 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 179 180 181 static struct cb_ops cb_ws_ops = { 182 nulldev, /* cb_open */ 183 nulldev, /* cb_close */ 184 nodev, /* cb_strategy */ 185 nodev, /* cb_print */ 186 nodev, /* cb_dump */ 187 nodev, /* cb_read */ 188 nodev, /* cb_write */ 189 nodev, /* cb_ioctl */ 190 nodev, /* cb_devmap */ 191 nodev, /* cb_mmap */ 192 nodev, /* cb_segmap */ 193 nochpoll, /* cb_chpoll */ 194 ddi_prop_op, /* cb_prop_op */ 195 NULL, /* cb_stream */ 196 D_MP | D_HOTPLUG, /* cb_flag */ 197 CB_REV, /* cb_rev */ 198 nodev, /* cb_aread */ 199 nodev /* cb_awrite */ 200 }; 201 202 static struct dev_ops ws_ops = { 203 DEVO_REV, /* devo_rev */ 204 0, /* devo_refcnt */ 205 NULL, /* devo_getinfo */ 206 nulldev, /* devo_identify */ 207 nulldev, /* devo_probe */ 208 e1000g_attach, /* devo_attach */ 209 e1000g_detach, /* devo_detach */ 210 nodev, /* devo_reset */ 211 &cb_ws_ops, /* devo_cb_ops */ 212 NULL, /* devo_bus_ops */ 213 ddi_power /* devo_power */ 214 }; 215 216 static struct modldrv modldrv = { 217 &mod_driverops, /* Type of module. This one is a driver */ 218 ident, /* Discription string */ 219 &ws_ops, /* driver ops */ 220 }; 221 222 static struct modlinkage modlinkage = { 223 MODREV_1, &modldrv, NULL 224 }; 225 226 /* Access attributes for register mapping */ 227 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 228 DDI_DEVICE_ATTR_V0, 229 DDI_STRUCTURE_LE_ACC, 230 DDI_STRICTORDER_ACC, 231 DDI_FLAGERR_ACC 232 }; 233 234 #define E1000G_M_CALLBACK_FLAGS \ 235 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 236 237 static mac_callbacks_t e1000g_m_callbacks = { 238 E1000G_M_CALLBACK_FLAGS, 239 e1000g_m_stat, 240 e1000g_m_start, 241 e1000g_m_stop, 242 e1000g_m_promisc, 243 e1000g_m_multicst, 244 e1000g_m_unicst, 245 e1000g_m_tx, 246 NULL, 247 e1000g_m_ioctl, 248 e1000g_m_getcapab, 249 NULL, 250 NULL, 251 e1000g_m_setprop, 252 e1000g_m_getprop 253 }; 254 255 /* 256 * Global variables 257 */ 258 uint32_t e1000g_mblks_pending = 0; 259 /* 260 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 261 * Here we maintain a private dev_info list if e1000g_force_detach is 262 * enabled. If we force the driver to detach while there are still some 263 * rx buffers retained in the upper layer, we have to keep a copy of the 264 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 265 * structure will be freed after the driver is detached. However when we 266 * finally free those rx buffers released by the upper layer, we need to 267 * refer to the dev_info to free the dma buffers. So we save a copy of 268 * the dev_info for this purpose. On x86 platform, we assume this copy 269 * of dev_info is always valid, but on SPARC platform, it could be invalid 270 * after the system board level DR operation. For this reason, the global 271 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 272 */ 273 #ifdef __sparc 274 boolean_t e1000g_force_detach = B_FALSE; 275 #else 276 boolean_t e1000g_force_detach = B_TRUE; 277 #endif 278 private_devi_list_t *e1000g_private_devi_list = NULL; 279 280 /* 281 * The rwlock is defined to protect the whole processing of rx recycling 282 * and the rx packets release in detach processing to make them mutually 283 * exclusive. 284 * The rx recycling processes different rx packets in different threads, 285 * so it will be protected with RW_READER and it won't block any other rx 286 * recycling threads. 287 * While the detach processing will be protected with RW_WRITER to make 288 * it mutually exclusive with the rx recycling. 289 */ 290 krwlock_t e1000g_rx_detach_lock; 291 /* 292 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 293 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 294 * If there are many e1000g instances, the system may run out of DVMA 295 * resources during the initialization of the instances, then the flag will 296 * be changed to "USE_DMA". Because different e1000g instances are initialized 297 * in parallel, we need to use this lock to protect the flag. 298 */ 299 krwlock_t e1000g_dma_type_lock; 300 301 /* 302 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 303 * Based on the information from Intel, the 82546 chipset has some hardware 304 * problem. When one port is being reset and the other port is trying to 305 * access the eeprom, it could cause system hang or panic. To workaround this 306 * hardware problem, we use a global mutex to prevent such operations from 307 * happening simultaneously on different instances. This workaround is applied 308 * to all the devices supported by this driver. 309 */ 310 kmutex_t e1000g_nvm_lock; 311 312 /* 313 * Loadable module configuration entry points for the driver 314 */ 315 316 /* 317 * _init - module initialization 318 */ 319 int 320 _init(void) 321 { 322 int status; 323 324 mac_init_ops(&ws_ops, WSNAME); 325 status = mod_install(&modlinkage); 326 if (status != DDI_SUCCESS) 327 mac_fini_ops(&ws_ops); 328 else { 329 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 330 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 331 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 332 } 333 334 return (status); 335 } 336 337 /* 338 * _fini - module finalization 339 */ 340 int 341 _fini(void) 342 { 343 int status; 344 345 rw_enter(&e1000g_rx_detach_lock, RW_READER); 346 if (e1000g_mblks_pending != 0) { 347 rw_exit(&e1000g_rx_detach_lock); 348 return (EBUSY); 349 } 350 rw_exit(&e1000g_rx_detach_lock); 351 352 status = mod_remove(&modlinkage); 353 if (status == DDI_SUCCESS) { 354 mac_fini_ops(&ws_ops); 355 356 if (e1000g_force_detach) { 357 private_devi_list_t *devi_node; 358 359 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 360 while (e1000g_private_devi_list != NULL) { 361 devi_node = e1000g_private_devi_list; 362 e1000g_private_devi_list = 363 e1000g_private_devi_list->next; 364 365 kmem_free(devi_node->priv_dip, 366 sizeof (struct dev_info)); 367 kmem_free(devi_node, 368 sizeof (private_devi_list_t)); 369 } 370 rw_exit(&e1000g_rx_detach_lock); 371 } 372 373 rw_destroy(&e1000g_rx_detach_lock); 374 rw_destroy(&e1000g_dma_type_lock); 375 mutex_destroy(&e1000g_nvm_lock); 376 } 377 378 return (status); 379 } 380 381 /* 382 * _info - module information 383 */ 384 int 385 _info(struct modinfo *modinfop) 386 { 387 return (mod_info(&modlinkage, modinfop)); 388 } 389 390 /* 391 * e1000g_attach - driver attach 392 * 393 * This function is the device-specific initialization entry 394 * point. This entry point is required and must be written. 395 * The DDI_ATTACH command must be provided in the attach entry 396 * point. When attach() is called with cmd set to DDI_ATTACH, 397 * all normal kernel services (such as kmem_alloc(9F)) are 398 * available for use by the driver. 399 * 400 * The attach() function will be called once for each instance 401 * of the device on the system with cmd set to DDI_ATTACH. 402 * Until attach() succeeds, the only driver entry points which 403 * may be called are open(9E) and getinfo(9E). 404 */ 405 static int 406 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 407 { 408 struct e1000g *Adapter; 409 struct e1000_hw *hw; 410 struct e1000g_osdep *osdep; 411 int instance; 412 413 switch (cmd) { 414 default: 415 e1000g_log(NULL, CE_WARN, 416 "Unsupported command send to e1000g_attach... "); 417 return (DDI_FAILURE); 418 419 case DDI_RESUME: 420 return (e1000g_resume(devinfo)); 421 422 case DDI_ATTACH: 423 break; 424 } 425 426 /* 427 * get device instance number 428 */ 429 instance = ddi_get_instance(devinfo); 430 431 /* 432 * Allocate soft data structure 433 */ 434 Adapter = 435 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 436 437 Adapter->dip = devinfo; 438 Adapter->instance = instance; 439 Adapter->tx_ring->adapter = Adapter; 440 Adapter->rx_ring->adapter = Adapter; 441 442 hw = &Adapter->shared; 443 osdep = &Adapter->osdep; 444 hw->back = osdep; 445 osdep->adapter = Adapter; 446 447 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 448 449 /* 450 * Initialize for fma support 451 */ 452 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 453 0, 0x0f, 454 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 455 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 456 e1000g_fm_init(Adapter); 457 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 458 459 /* 460 * PCI Configure 461 */ 462 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 463 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 464 goto attach_fail; 465 } 466 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 467 468 /* 469 * Setup hardware 470 */ 471 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 472 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 473 goto attach_fail; 474 } 475 476 /* 477 * Map in the device registers. 478 */ 479 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 480 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 481 goto attach_fail; 482 } 483 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 484 485 /* 486 * Initialize driver parameters 487 */ 488 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 489 goto attach_fail; 490 } 491 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 492 493 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 494 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 495 goto attach_fail; 496 } 497 498 /* 499 * Initialize interrupts 500 */ 501 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 502 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 503 goto attach_fail; 504 } 505 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 506 507 /* 508 * Initialize mutex's for this device. 509 * Do this before enabling the interrupt handler and 510 * register the softint to avoid the condition where 511 * interrupt handler can try using uninitialized mutex 512 */ 513 e1000g_init_locks(Adapter); 514 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 515 516 /* 517 * Initialize Driver Counters 518 */ 519 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 520 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 521 goto attach_fail; 522 } 523 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 524 525 /* 526 * Initialize chip hardware and software structures 527 */ 528 if (e1000g_init(Adapter) != DDI_SUCCESS) { 529 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 530 goto attach_fail; 531 } 532 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 533 534 /* 535 * Register the driver to the MAC 536 */ 537 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 538 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 539 goto attach_fail; 540 } 541 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 542 543 /* 544 * Now that mutex locks are initialized, and the chip is also 545 * initialized, enable interrupts. 546 */ 547 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 548 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 549 goto attach_fail; 550 } 551 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 552 553 /* 554 * If e1000g_force_detach is enabled, in global private dip list, 555 * we will create a new entry, which maintains the priv_dip for DR 556 * supports after driver detached. 557 */ 558 if (e1000g_force_detach) { 559 private_devi_list_t *devi_node; 560 561 Adapter->priv_dip = 562 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 563 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 564 sizeof (struct dev_info)); 565 566 devi_node = 567 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 568 569 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 570 devi_node->priv_dip = Adapter->priv_dip; 571 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 572 devi_node->next = e1000g_private_devi_list; 573 e1000g_private_devi_list = devi_node; 574 rw_exit(&e1000g_rx_detach_lock); 575 } 576 577 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 578 579 return (DDI_SUCCESS); 580 581 attach_fail: 582 e1000g_unattach(devinfo, Adapter); 583 return (DDI_FAILURE); 584 } 585 586 static int 587 e1000g_register_mac(struct e1000g *Adapter) 588 { 589 struct e1000_hw *hw = &Adapter->shared; 590 mac_register_t *mac; 591 int err; 592 593 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 594 return (DDI_FAILURE); 595 596 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 597 mac->m_driver = Adapter; 598 mac->m_dip = Adapter->dip; 599 mac->m_src_addr = hw->mac.addr; 600 mac->m_callbacks = &e1000g_m_callbacks; 601 mac->m_min_sdu = 0; 602 mac->m_max_sdu = Adapter->default_mtu; 603 mac->m_margin = VLAN_TAGSZ; 604 mac->m_priv_props = e1000g_priv_props; 605 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 606 607 err = mac_register(mac, &Adapter->mh); 608 mac_free(mac); 609 610 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 611 } 612 613 static int 614 e1000g_identify_hardware(struct e1000g *Adapter) 615 { 616 struct e1000_hw *hw = &Adapter->shared; 617 struct e1000g_osdep *osdep = &Adapter->osdep; 618 619 /* Get the device id */ 620 hw->vendor_id = 621 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 622 hw->device_id = 623 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 624 hw->revision_id = 625 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 626 hw->subsystem_device_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 628 hw->subsystem_vendor_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 630 631 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 632 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 633 "MAC type could not be set properly."); 634 return (DDI_FAILURE); 635 } 636 637 return (DDI_SUCCESS); 638 } 639 640 static int 641 e1000g_regs_map(struct e1000g *Adapter) 642 { 643 dev_info_t *devinfo = Adapter->dip; 644 struct e1000_hw *hw = &Adapter->shared; 645 struct e1000g_osdep *osdep = &Adapter->osdep; 646 off_t mem_size; 647 648 /* 649 * first get the size of device register to be mapped. The 650 * second parameter is the register we are interested. I our 651 * wiseman 0 is for config registers and 1 is for memory mapped 652 * registers Mem size should have memory mapped region size 653 */ 654 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 655 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 656 "ddi_dev_regsize for registers failed"); 657 return (DDI_FAILURE); 658 } 659 660 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 661 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 662 &osdep->reg_handle)) != DDI_SUCCESS) { 663 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 664 "ddi_regs_map_setup for registers failed"); 665 goto regs_map_fail; 666 } 667 668 /* ICH needs to map flash memory */ 669 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 670 /* get flash size */ 671 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 672 &mem_size) != DDI_SUCCESS) { 673 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 674 "ddi_dev_regsize for ICH flash failed"); 675 goto regs_map_fail; 676 } 677 678 /* map flash in */ 679 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 680 (caddr_t *)&hw->flash_address, 0, 681 mem_size, &e1000g_regs_acc_attr, 682 &osdep->ich_flash_handle) != DDI_SUCCESS) { 683 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 684 "ddi_regs_map_setup for ICH flash failed"); 685 goto regs_map_fail; 686 } 687 } 688 689 return (DDI_SUCCESS); 690 691 regs_map_fail: 692 if (osdep->reg_handle != NULL) 693 ddi_regs_map_free(&osdep->reg_handle); 694 695 return (DDI_FAILURE); 696 } 697 698 static int 699 e1000g_set_driver_params(struct e1000g *Adapter) 700 { 701 struct e1000_hw *hw; 702 uint32_t mem_bar, io_bar, bar64; 703 704 hw = &Adapter->shared; 705 706 /* Set MAC type and initialize hardware functions */ 707 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 708 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 709 "Could not setup hardware functions"); 710 return (DDI_FAILURE); 711 } 712 713 /* Get bus information */ 714 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 715 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 716 "Could not get bus information"); 717 return (DDI_FAILURE); 718 } 719 720 /* get mem_base addr */ 721 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 722 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 723 724 /* get io_base addr */ 725 if (hw->mac.type >= e1000_82544) { 726 if (bar64) { 727 /* IO BAR is different for 64 bit BAR mode */ 728 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 729 PCI_CONF_BASE4); 730 } else { 731 /* normal 32-bit BAR mode */ 732 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 733 PCI_CONF_BASE2); 734 } 735 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 736 } else { 737 /* no I/O access for adapters prior to 82544 */ 738 hw->io_base = 0x0; 739 } 740 741 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 742 743 hw->mac.autoneg_failed = B_TRUE; 744 745 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 746 hw->phy.autoneg_wait_to_complete = B_FALSE; 747 748 /* Adaptive IFS related changes */ 749 hw->mac.adaptive_ifs = B_TRUE; 750 751 /* Enable phy init script for IGP phy of 82541/82547 */ 752 if ((hw->mac.type == e1000_82547) || 753 (hw->mac.type == e1000_82541) || 754 (hw->mac.type == e1000_82547_rev_2) || 755 (hw->mac.type == e1000_82541_rev_2)) 756 e1000_init_script_state_82541(hw, B_TRUE); 757 758 /* Enable the TTL workaround for 82541/82547 */ 759 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 760 761 #ifdef __sparc 762 Adapter->strip_crc = B_TRUE; 763 #else 764 Adapter->strip_crc = B_FALSE; 765 #endif 766 767 /* Get conf file properties */ 768 e1000g_get_conf(Adapter); 769 770 /* Get speed/duplex settings in conf file */ 771 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 772 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 773 e1000g_force_speed_duplex(Adapter); 774 775 /* Get Jumbo Frames settings in conf file */ 776 e1000g_get_max_frame_size(Adapter); 777 778 /* Set Rx/Tx buffer size */ 779 e1000g_set_bufsize(Adapter); 780 781 /* Master Latency Timer */ 782 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 783 784 /* copper options */ 785 if (hw->phy.media_type == e1000_media_type_copper) { 786 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 787 hw->phy.disable_polarity_correction = B_FALSE; 788 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 789 } 790 791 /* The initial link state should be "unknown" */ 792 Adapter->link_state = LINK_STATE_UNKNOWN; 793 794 /* Initialize rx parameters */ 795 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 796 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 797 798 /* Initialize tx parameters */ 799 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 800 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 801 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 802 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 803 804 /* Initialize rx parameters */ 805 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 806 807 return (DDI_SUCCESS); 808 } 809 810 static void 811 e1000g_set_bufsize(struct e1000g *Adapter) 812 { 813 struct e1000_mac_info *mac = &Adapter->shared.mac; 814 uint64_t rx_size; 815 uint64_t tx_size; 816 817 #ifdef __sparc 818 dev_info_t *devinfo = Adapter->dip; 819 ulong_t iommu_pagesize; 820 821 /* Get the system page size */ 822 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 823 iommu_pagesize = dvma_pagesize(devinfo); 824 if (iommu_pagesize != 0) { 825 if (Adapter->sys_page_sz == iommu_pagesize) { 826 if (iommu_pagesize > 0x4000) 827 Adapter->sys_page_sz = 0x4000; 828 } else { 829 if (Adapter->sys_page_sz > iommu_pagesize) 830 Adapter->sys_page_sz = iommu_pagesize; 831 } 832 } 833 if (Adapter->lso_enable) { 834 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 835 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 836 } else { 837 Adapter->dvma_page_num = Adapter->max_frame_size / 838 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 839 } 840 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 841 #endif 842 843 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 844 845 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 846 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 847 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 848 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 849 (rx_size <= FRAME_SIZE_UPTO_8K)) 850 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 851 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 852 (rx_size <= FRAME_SIZE_UPTO_16K)) 853 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 854 else 855 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 856 857 tx_size = Adapter->max_frame_size; 858 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 859 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 860 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 861 (tx_size <= FRAME_SIZE_UPTO_8K)) 862 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 863 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 864 (tx_size <= FRAME_SIZE_UPTO_16K)) 865 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 866 else 867 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 868 869 /* 870 * For Wiseman adapters we have an requirement of having receive 871 * buffers aligned at 256 byte boundary. Since Livengood does not 872 * require this and forcing it for all hardwares will have 873 * performance implications, I am making it applicable only for 874 * Wiseman and for Jumbo frames enabled mode as rest of the time, 875 * it is okay to have normal frames...but it does involve a 876 * potential risk where we may loose data if buffer is not 877 * aligned...so all wiseman boards to have 256 byte aligned 878 * buffers 879 */ 880 if (mac->type < e1000_82543) 881 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 882 else 883 Adapter->rx_buf_align = 1; 884 } 885 886 /* 887 * e1000g_detach - driver detach 888 * 889 * The detach() function is the complement of the attach routine. 890 * If cmd is set to DDI_DETACH, detach() is used to remove the 891 * state associated with a given instance of a device node 892 * prior to the removal of that instance from the system. 893 * 894 * The detach() function will be called once for each instance 895 * of the device for which there has been a successful attach() 896 * once there are no longer any opens on the device. 897 * 898 * Interrupts routine are disabled, All memory allocated by this 899 * driver are freed. 900 */ 901 static int 902 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 903 { 904 struct e1000g *Adapter; 905 boolean_t rx_drain; 906 907 switch (cmd) { 908 default: 909 return (DDI_FAILURE); 910 911 case DDI_SUSPEND: 912 return (e1000g_suspend(devinfo)); 913 914 case DDI_DETACH: 915 break; 916 } 917 918 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 919 if (Adapter == NULL) 920 return (DDI_FAILURE); 921 922 if (mac_unregister(Adapter->mh) != 0) { 923 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 924 return (DDI_FAILURE); 925 } 926 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 927 928 929 if (Adapter->chip_state != E1000G_STOP) 930 e1000g_stop(Adapter, B_TRUE); 931 932 rx_drain = e1000g_rx_drain(Adapter); 933 934 /* 935 * If e1000g_force_detach is enabled, driver detach is safe. 936 * We will let e1000g_free_priv_devi_node routine determine 937 * whether we need to free the priv_dip entry for current 938 * driver instance. 939 */ 940 if (e1000g_force_detach) { 941 e1000g_free_priv_devi_node(Adapter, rx_drain); 942 } else { 943 if (!rx_drain) 944 return (DDI_FAILURE); 945 } 946 947 e1000g_unattach(devinfo, Adapter); 948 949 return (DDI_SUCCESS); 950 } 951 952 /* 953 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 954 * 955 * If free_flag is true, that indicates the upper layer is not holding 956 * the rx buffers, we could free the priv_dip entry safely. 957 * 958 * Otherwise, we have to keep this entry even after driver detached, 959 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 960 * so that driver could free it while all of rx buffers are returned 961 * by upper layer later. 962 */ 963 static void 964 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 965 { 966 private_devi_list_t *devi_node, *devi_del; 967 968 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 969 ASSERT(e1000g_private_devi_list != NULL); 970 ASSERT(Adapter->priv_dip != NULL); 971 972 devi_node = e1000g_private_devi_list; 973 if (devi_node->priv_dip == Adapter->priv_dip) { 974 if (free_flag) { 975 e1000g_private_devi_list = 976 devi_node->next; 977 kmem_free(devi_node->priv_dip, 978 sizeof (struct dev_info)); 979 kmem_free(devi_node, 980 sizeof (private_devi_list_t)); 981 } else { 982 ASSERT(e1000g_mblks_pending != 0); 983 devi_node->flag = 984 E1000G_PRIV_DEVI_DETACH; 985 } 986 rw_exit(&e1000g_rx_detach_lock); 987 return; 988 } 989 990 devi_node = e1000g_private_devi_list; 991 while (devi_node->next != NULL) { 992 if (devi_node->next->priv_dip == Adapter->priv_dip) { 993 if (free_flag) { 994 devi_del = devi_node->next; 995 devi_node->next = devi_del->next; 996 kmem_free(devi_del->priv_dip, 997 sizeof (struct dev_info)); 998 kmem_free(devi_del, 999 sizeof (private_devi_list_t)); 1000 } else { 1001 ASSERT(e1000g_mblks_pending != 0); 1002 devi_node->next->flag = 1003 E1000G_PRIV_DEVI_DETACH; 1004 } 1005 break; 1006 } 1007 devi_node = devi_node->next; 1008 } 1009 rw_exit(&e1000g_rx_detach_lock); 1010 } 1011 1012 static void 1013 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1014 { 1015 int result; 1016 1017 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1018 (void) e1000g_disable_intrs(Adapter); 1019 } 1020 1021 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1022 (void) mac_unregister(Adapter->mh); 1023 } 1024 1025 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1026 (void) e1000g_rem_intrs(Adapter); 1027 } 1028 1029 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1030 (void) ddi_prop_remove_all(devinfo); 1031 } 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1034 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1035 } 1036 1037 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1038 stop_link_timer(Adapter); 1039 1040 mutex_enter(&e1000g_nvm_lock); 1041 result = e1000_reset_hw(&Adapter->shared); 1042 mutex_exit(&e1000g_nvm_lock); 1043 1044 if (result != E1000_SUCCESS) { 1045 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1046 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1047 } 1048 } 1049 1050 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1051 if (Adapter->osdep.reg_handle != NULL) 1052 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1053 if (Adapter->osdep.ich_flash_handle != NULL) 1054 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1055 } 1056 1057 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1058 if (Adapter->osdep.cfg_handle != NULL) 1059 pci_config_teardown(&Adapter->osdep.cfg_handle); 1060 } 1061 1062 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1063 e1000g_destroy_locks(Adapter); 1064 } 1065 1066 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1067 e1000g_fm_fini(Adapter); 1068 } 1069 1070 e1000_remove_device(&Adapter->shared); 1071 1072 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1073 1074 /* 1075 * Another hotplug spec requirement, 1076 * run ddi_set_driver_private(devinfo, null); 1077 */ 1078 ddi_set_driver_private(devinfo, NULL); 1079 } 1080 1081 static void 1082 e1000g_init_locks(struct e1000g *Adapter) 1083 { 1084 e1000g_tx_ring_t *tx_ring; 1085 e1000g_rx_ring_t *rx_ring; 1086 1087 rw_init(&Adapter->chip_lock, NULL, 1088 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1089 mutex_init(&Adapter->link_lock, NULL, 1090 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1091 mutex_init(&Adapter->watchdog_lock, NULL, 1092 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1093 1094 tx_ring = Adapter->tx_ring; 1095 1096 mutex_init(&tx_ring->tx_lock, NULL, 1097 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1098 mutex_init(&tx_ring->usedlist_lock, NULL, 1099 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1100 mutex_init(&tx_ring->freelist_lock, NULL, 1101 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1102 1103 rx_ring = Adapter->rx_ring; 1104 1105 mutex_init(&rx_ring->freelist_lock, NULL, 1106 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1107 } 1108 1109 static void 1110 e1000g_destroy_locks(struct e1000g *Adapter) 1111 { 1112 e1000g_tx_ring_t *tx_ring; 1113 e1000g_rx_ring_t *rx_ring; 1114 1115 tx_ring = Adapter->tx_ring; 1116 mutex_destroy(&tx_ring->tx_lock); 1117 mutex_destroy(&tx_ring->usedlist_lock); 1118 mutex_destroy(&tx_ring->freelist_lock); 1119 1120 rx_ring = Adapter->rx_ring; 1121 mutex_destroy(&rx_ring->freelist_lock); 1122 1123 mutex_destroy(&Adapter->link_lock); 1124 mutex_destroy(&Adapter->watchdog_lock); 1125 rw_destroy(&Adapter->chip_lock); 1126 } 1127 1128 static int 1129 e1000g_resume(dev_info_t *devinfo) 1130 { 1131 struct e1000g *Adapter; 1132 1133 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1134 if (Adapter == NULL) 1135 return (DDI_FAILURE); 1136 1137 if (e1000g_start(Adapter, B_TRUE)) 1138 return (DDI_FAILURE); 1139 1140 return (DDI_SUCCESS); 1141 } 1142 1143 static int 1144 e1000g_suspend(dev_info_t *devinfo) 1145 { 1146 struct e1000g *Adapter; 1147 1148 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1149 if (Adapter == NULL) 1150 return (DDI_FAILURE); 1151 1152 e1000g_stop(Adapter, B_TRUE); 1153 1154 return (DDI_SUCCESS); 1155 } 1156 1157 static int 1158 e1000g_init(struct e1000g *Adapter) 1159 { 1160 uint32_t pba; 1161 uint32_t high_water; 1162 struct e1000_hw *hw; 1163 clock_t link_timeout; 1164 int result; 1165 1166 hw = &Adapter->shared; 1167 1168 rw_enter(&Adapter->chip_lock, RW_WRITER); 1169 1170 /* 1171 * reset to put the hardware in a known state 1172 * before we try to do anything with the eeprom 1173 */ 1174 mutex_enter(&e1000g_nvm_lock); 1175 result = e1000_reset_hw(hw); 1176 mutex_exit(&e1000g_nvm_lock); 1177 1178 if (result != E1000_SUCCESS) { 1179 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1180 goto init_fail; 1181 } 1182 1183 mutex_enter(&e1000g_nvm_lock); 1184 result = e1000_validate_nvm_checksum(hw); 1185 if (result < E1000_SUCCESS) { 1186 /* 1187 * Some PCI-E parts fail the first check due to 1188 * the link being in sleep state. Call it again, 1189 * if it fails a second time its a real issue. 1190 */ 1191 result = e1000_validate_nvm_checksum(hw); 1192 } 1193 mutex_exit(&e1000g_nvm_lock); 1194 1195 if (result < E1000_SUCCESS) { 1196 e1000g_log(Adapter, CE_WARN, 1197 "Invalid NVM checksum. Please contact " 1198 "the vendor to update the NVM."); 1199 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1200 goto init_fail; 1201 } 1202 1203 result = 0; 1204 #ifdef __sparc 1205 /* 1206 * Firstly, we try to get the local ethernet address from OBP. If 1207 * failed, then we get it from the EEPROM of NIC card. 1208 */ 1209 result = e1000g_find_mac_address(Adapter); 1210 #endif 1211 /* Get the local ethernet address. */ 1212 if (!result) { 1213 mutex_enter(&e1000g_nvm_lock); 1214 e1000_read_mac_addr(hw); 1215 mutex_exit(&e1000g_nvm_lock); 1216 } 1217 1218 if (result < E1000_SUCCESS) { 1219 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1220 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1221 goto init_fail; 1222 } 1223 1224 /* check for valid mac address */ 1225 if (!is_valid_mac_addr(hw->mac.addr)) { 1226 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1227 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1228 goto init_fail; 1229 } 1230 1231 /* Set LAA state for 82571 chipset */ 1232 e1000_set_laa_state_82571(hw, B_TRUE); 1233 1234 /* Master Latency Timer implementation */ 1235 if (Adapter->master_latency_timer) { 1236 pci_config_put8(Adapter->osdep.cfg_handle, 1237 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1238 } 1239 1240 if (hw->mac.type < e1000_82547) { 1241 /* 1242 * Total FIFO is 64K 1243 */ 1244 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1245 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1246 else 1247 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1248 } else if (hw->mac.type >= e1000_82571 && 1249 hw->mac.type <= e1000_80003es2lan) { 1250 /* 1251 * Total FIFO is 48K 1252 */ 1253 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1254 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1255 else 1256 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1257 } else if (hw->mac.type == e1000_ich8lan) { 1258 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1259 } else if (hw->mac.type == e1000_ich9lan) { 1260 pba = E1000_PBA_12K; 1261 } else { 1262 /* 1263 * Total FIFO is 40K 1264 */ 1265 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1266 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1267 else 1268 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1269 } 1270 E1000_WRITE_REG(hw, E1000_PBA, pba); 1271 1272 /* 1273 * These parameters set thresholds for the adapter's generation(Tx) 1274 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1275 * settings. Flow control is enabled or disabled in the configuration 1276 * file. 1277 * High-water mark is set down from the top of the rx fifo (not 1278 * sensitive to max_frame_size) and low-water is set just below 1279 * high-water mark. 1280 * The high water mark must be low enough to fit one full frame above 1281 * it in the rx FIFO. Should be the lower of: 1282 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1283 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1284 * Rx FIFO size minus one full frame. 1285 */ 1286 high_water = min(((pba << 10) * 9 / 10), 1287 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1288 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1289 ((pba << 10) - Adapter->max_frame_size))); 1290 1291 hw->fc.high_water = high_water & 0xFFF8; 1292 hw->fc.low_water = hw->fc.high_water - 8; 1293 1294 if (hw->mac.type == e1000_80003es2lan) 1295 hw->fc.pause_time = 0xFFFF; 1296 else 1297 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1298 hw->fc.send_xon = B_TRUE; 1299 1300 /* 1301 * Reset the adapter hardware the second time. 1302 */ 1303 mutex_enter(&e1000g_nvm_lock); 1304 result = e1000_reset_hw(hw); 1305 mutex_exit(&e1000g_nvm_lock); 1306 1307 if (result != E1000_SUCCESS) { 1308 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1309 goto init_fail; 1310 } 1311 1312 /* disable wakeup control by default */ 1313 if (hw->mac.type >= e1000_82544) 1314 E1000_WRITE_REG(hw, E1000_WUC, 0); 1315 1316 /* MWI setup */ 1317 e1000_pci_set_mwi(hw); 1318 1319 /* 1320 * Configure/Initialize hardware 1321 */ 1322 mutex_enter(&e1000g_nvm_lock); 1323 result = e1000_init_hw(hw); 1324 mutex_exit(&e1000g_nvm_lock); 1325 1326 if (result < E1000_SUCCESS) { 1327 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1328 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1329 goto init_fail; 1330 } 1331 1332 /* Disable Smart Power Down */ 1333 phy_spd_state(hw, B_FALSE); 1334 1335 /* Make sure driver has control */ 1336 e1000g_get_driver_control(hw); 1337 1338 /* 1339 * Initialize unicast addresses. 1340 */ 1341 e1000g_init_unicst(Adapter); 1342 1343 /* 1344 * Setup and initialize the mctable structures. After this routine 1345 * completes Multicast table will be set 1346 */ 1347 e1000g_setup_multicast(Adapter); 1348 msec_delay(5); 1349 1350 /* 1351 * Implement Adaptive IFS 1352 */ 1353 e1000_reset_adaptive(hw); 1354 1355 /* Setup Interrupt Throttling Register */ 1356 if (hw->mac.type >= e1000_82540) { 1357 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1358 } else 1359 Adapter->intr_adaptive = B_FALSE; 1360 1361 /* Start the timer for link setup */ 1362 if (hw->mac.autoneg) 1363 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1364 else 1365 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1366 1367 mutex_enter(&Adapter->link_lock); 1368 if (hw->phy.autoneg_wait_to_complete) { 1369 Adapter->link_complete = B_TRUE; 1370 } else { 1371 Adapter->link_complete = B_FALSE; 1372 Adapter->link_tid = timeout(e1000g_link_timer, 1373 (void *)Adapter, link_timeout); 1374 } 1375 mutex_exit(&Adapter->link_lock); 1376 1377 /* Enable PCI-Ex master */ 1378 if (hw->bus.type == e1000_bus_type_pci_express) { 1379 e1000_enable_pciex_master(hw); 1380 } 1381 1382 /* Save the state of the phy */ 1383 e1000g_get_phy_state(Adapter); 1384 1385 e1000g_param_sync(Adapter); 1386 1387 Adapter->init_count++; 1388 1389 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1390 goto init_fail; 1391 } 1392 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1393 goto init_fail; 1394 } 1395 1396 rw_exit(&Adapter->chip_lock); 1397 1398 return (DDI_SUCCESS); 1399 1400 init_fail: 1401 rw_exit(&Adapter->chip_lock); 1402 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1403 return (DDI_FAILURE); 1404 } 1405 1406 /* 1407 * Check if the link is up 1408 */ 1409 static boolean_t 1410 e1000g_link_up(struct e1000g *Adapter) 1411 { 1412 struct e1000_hw *hw; 1413 boolean_t link_up; 1414 1415 hw = &Adapter->shared; 1416 1417 e1000_check_for_link(hw); 1418 1419 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1420 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1421 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1422 (hw->mac.serdes_has_link))) { 1423 link_up = B_TRUE; 1424 } else { 1425 link_up = B_FALSE; 1426 } 1427 1428 return (link_up); 1429 } 1430 1431 static void 1432 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1433 { 1434 struct iocblk *iocp; 1435 struct e1000g *e1000gp; 1436 enum ioc_reply status; 1437 int err; 1438 1439 iocp = (struct iocblk *)mp->b_rptr; 1440 iocp->ioc_error = 0; 1441 e1000gp = (struct e1000g *)arg; 1442 1443 ASSERT(e1000gp); 1444 if (e1000gp == NULL) { 1445 miocnak(q, mp, 0, EINVAL); 1446 return; 1447 } 1448 1449 switch (iocp->ioc_cmd) { 1450 1451 case LB_GET_INFO_SIZE: 1452 case LB_GET_INFO: 1453 case LB_GET_MODE: 1454 case LB_SET_MODE: 1455 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1456 break; 1457 1458 1459 #ifdef E1000G_DEBUG 1460 case E1000G_IOC_REG_PEEK: 1461 case E1000G_IOC_REG_POKE: 1462 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1463 break; 1464 case E1000G_IOC_CHIP_RESET: 1465 e1000gp->reset_count++; 1466 if (e1000g_reset(e1000gp)) 1467 status = IOC_ACK; 1468 else 1469 status = IOC_INVAL; 1470 break; 1471 #endif 1472 default: 1473 status = IOC_INVAL; 1474 break; 1475 } 1476 1477 /* 1478 * Decide how to reply 1479 */ 1480 switch (status) { 1481 default: 1482 case IOC_INVAL: 1483 /* 1484 * Error, reply with a NAK and EINVAL or the specified error 1485 */ 1486 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1487 EINVAL : iocp->ioc_error); 1488 break; 1489 1490 case IOC_DONE: 1491 /* 1492 * OK, reply already sent 1493 */ 1494 break; 1495 1496 case IOC_ACK: 1497 /* 1498 * OK, reply with an ACK 1499 */ 1500 miocack(q, mp, 0, 0); 1501 break; 1502 1503 case IOC_REPLY: 1504 /* 1505 * OK, send prepared reply as ACK or NAK 1506 */ 1507 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1508 M_IOCACK : M_IOCNAK; 1509 qreply(q, mp); 1510 break; 1511 } 1512 } 1513 1514 static int 1515 e1000g_m_start(void *arg) 1516 { 1517 struct e1000g *Adapter = (struct e1000g *)arg; 1518 1519 return (e1000g_start(Adapter, B_TRUE)); 1520 } 1521 1522 static int 1523 e1000g_start(struct e1000g *Adapter, boolean_t global) 1524 { 1525 if (global) { 1526 /* Allocate dma resources for descriptors and buffers */ 1527 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1528 e1000g_log(Adapter, CE_WARN, 1529 "Alloc DMA resources failed"); 1530 return (ENOTACTIVE); 1531 } 1532 Adapter->rx_buffer_setup = B_FALSE; 1533 } 1534 1535 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1536 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1537 e1000g_log(Adapter, CE_WARN, 1538 "Adapter initialization failed"); 1539 if (global) 1540 e1000g_release_dma_resources(Adapter); 1541 return (ENOTACTIVE); 1542 } 1543 } 1544 1545 rw_enter(&Adapter->chip_lock, RW_WRITER); 1546 1547 /* Setup and initialize the transmit structures */ 1548 e1000g_tx_setup(Adapter); 1549 msec_delay(5); 1550 1551 /* Setup and initialize the receive structures */ 1552 e1000g_rx_setup(Adapter); 1553 msec_delay(5); 1554 1555 e1000g_mask_interrupt(Adapter); 1556 1557 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1558 rw_exit(&Adapter->chip_lock); 1559 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1560 return (ENOTACTIVE); 1561 } 1562 1563 Adapter->chip_state = E1000G_START; 1564 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1565 1566 rw_exit(&Adapter->chip_lock); 1567 1568 /* Enable and start the watchdog timer */ 1569 enable_watchdog_timer(Adapter); 1570 1571 return (0); 1572 } 1573 1574 static void 1575 e1000g_m_stop(void *arg) 1576 { 1577 struct e1000g *Adapter = (struct e1000g *)arg; 1578 1579 e1000g_stop(Adapter, B_TRUE); 1580 } 1581 1582 static void 1583 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1584 { 1585 int result; 1586 1587 /* Set stop flags */ 1588 rw_enter(&Adapter->chip_lock, RW_WRITER); 1589 1590 Adapter->chip_state = E1000G_STOP; 1591 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1592 1593 rw_exit(&Adapter->chip_lock); 1594 1595 /* Drain tx sessions */ 1596 (void) e1000g_tx_drain(Adapter); 1597 1598 /* Disable and stop all the timers */ 1599 disable_watchdog_timer(Adapter); 1600 stop_link_timer(Adapter); 1601 stop_82547_timer(Adapter->tx_ring); 1602 1603 /* Stop the chip and release pending resources */ 1604 rw_enter(&Adapter->chip_lock, RW_WRITER); 1605 1606 e1000g_clear_all_interrupts(Adapter); 1607 1608 mutex_enter(&e1000g_nvm_lock); 1609 result = e1000_reset_hw(&Adapter->shared); 1610 mutex_exit(&e1000g_nvm_lock); 1611 1612 if (result != E1000_SUCCESS) { 1613 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1614 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1615 } 1616 1617 /* Release resources still held by the TX descriptors */ 1618 e1000g_tx_clean(Adapter); 1619 1620 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1621 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1622 1623 /* Clean the pending rx jumbo packet fragment */ 1624 e1000g_rx_clean(Adapter); 1625 1626 rw_exit(&Adapter->chip_lock); 1627 1628 if (global) 1629 e1000g_release_dma_resources(Adapter); 1630 } 1631 1632 static void 1633 e1000g_rx_clean(struct e1000g *Adapter) 1634 { 1635 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1636 1637 if (rx_ring->rx_mblk != NULL) { 1638 freemsg(rx_ring->rx_mblk); 1639 rx_ring->rx_mblk = NULL; 1640 rx_ring->rx_mblk_tail = NULL; 1641 rx_ring->rx_mblk_len = 0; 1642 } 1643 } 1644 1645 static void 1646 e1000g_tx_clean(struct e1000g *Adapter) 1647 { 1648 e1000g_tx_ring_t *tx_ring; 1649 p_tx_sw_packet_t packet; 1650 mblk_t *mp; 1651 mblk_t *nmp; 1652 uint32_t packet_count; 1653 1654 tx_ring = Adapter->tx_ring; 1655 1656 /* 1657 * Here we don't need to protect the lists using 1658 * the usedlist_lock and freelist_lock, for they 1659 * have been protected by the chip_lock. 1660 */ 1661 mp = NULL; 1662 nmp = NULL; 1663 packet_count = 0; 1664 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1665 while (packet != NULL) { 1666 if (packet->mp != NULL) { 1667 /* Assemble the message chain */ 1668 if (mp == NULL) { 1669 mp = packet->mp; 1670 nmp = packet->mp; 1671 } else { 1672 nmp->b_next = packet->mp; 1673 nmp = packet->mp; 1674 } 1675 /* Disconnect the message from the sw packet */ 1676 packet->mp = NULL; 1677 } 1678 1679 e1000g_free_tx_swpkt(packet); 1680 packet_count++; 1681 1682 packet = (p_tx_sw_packet_t) 1683 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1684 } 1685 1686 if (mp != NULL) 1687 freemsgchain(mp); 1688 1689 if (packet_count > 0) { 1690 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1691 QUEUE_INIT_LIST(&tx_ring->used_list); 1692 1693 /* Setup TX descriptor pointers */ 1694 tx_ring->tbd_next = tx_ring->tbd_first; 1695 tx_ring->tbd_oldest = tx_ring->tbd_first; 1696 1697 /* Setup our HW Tx Head & Tail descriptor pointers */ 1698 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1699 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1700 } 1701 } 1702 1703 static boolean_t 1704 e1000g_tx_drain(struct e1000g *Adapter) 1705 { 1706 int i; 1707 boolean_t done; 1708 e1000g_tx_ring_t *tx_ring; 1709 1710 tx_ring = Adapter->tx_ring; 1711 1712 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1713 for (i = 0; i < TX_DRAIN_TIME; i++) { 1714 mutex_enter(&tx_ring->usedlist_lock); 1715 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1716 mutex_exit(&tx_ring->usedlist_lock); 1717 1718 if (done) 1719 break; 1720 1721 msec_delay(1); 1722 } 1723 1724 return (done); 1725 } 1726 1727 static boolean_t 1728 e1000g_rx_drain(struct e1000g *Adapter) 1729 { 1730 e1000g_rx_ring_t *rx_ring; 1731 p_rx_sw_packet_t packet; 1732 boolean_t done; 1733 1734 rx_ring = Adapter->rx_ring; 1735 done = B_TRUE; 1736 1737 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1738 1739 while (rx_ring->pending_list != NULL) { 1740 packet = rx_ring->pending_list; 1741 rx_ring->pending_list = 1742 rx_ring->pending_list->next; 1743 1744 if (packet->flag == E1000G_RX_SW_STOP) { 1745 packet->flag = E1000G_RX_SW_DETACH; 1746 done = B_FALSE; 1747 } else { 1748 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1749 ASSERT(packet->mp == NULL); 1750 e1000g_free_rx_sw_packet(packet); 1751 } 1752 } 1753 1754 rw_exit(&e1000g_rx_detach_lock); 1755 1756 return (done); 1757 } 1758 1759 boolean_t 1760 e1000g_reset(struct e1000g *Adapter) 1761 { 1762 e1000g_stop(Adapter, B_FALSE); 1763 1764 if (e1000g_start(Adapter, B_FALSE)) { 1765 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1766 return (B_FALSE); 1767 } 1768 1769 return (B_TRUE); 1770 } 1771 1772 boolean_t 1773 e1000g_global_reset(struct e1000g *Adapter) 1774 { 1775 e1000g_stop(Adapter, B_TRUE); 1776 1777 Adapter->init_count = 0; 1778 1779 if (e1000g_start(Adapter, B_TRUE)) { 1780 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1781 return (B_FALSE); 1782 } 1783 1784 return (B_TRUE); 1785 } 1786 1787 /* 1788 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1789 * 1790 * This interrupt service routine is for PCI-Express adapters. 1791 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1792 * bit is set. 1793 */ 1794 static uint_t 1795 e1000g_intr_pciexpress(caddr_t arg) 1796 { 1797 struct e1000g *Adapter; 1798 uint32_t icr; 1799 1800 Adapter = (struct e1000g *)arg; 1801 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1802 1803 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1804 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1805 1806 if (icr & E1000_ICR_INT_ASSERTED) { 1807 /* 1808 * E1000_ICR_INT_ASSERTED bit was set: 1809 * Read(Clear) the ICR, claim this interrupt, 1810 * look for work to do. 1811 */ 1812 e1000g_intr_work(Adapter, icr); 1813 return (DDI_INTR_CLAIMED); 1814 } else { 1815 /* 1816 * E1000_ICR_INT_ASSERTED bit was not set: 1817 * Don't claim this interrupt, return immediately. 1818 */ 1819 return (DDI_INTR_UNCLAIMED); 1820 } 1821 } 1822 1823 /* 1824 * e1000g_intr - ISR for PCI/PCI-X chipsets 1825 * 1826 * This interrupt service routine is for PCI/PCI-X adapters. 1827 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1828 * bit is set or not. 1829 */ 1830 static uint_t 1831 e1000g_intr(caddr_t arg) 1832 { 1833 struct e1000g *Adapter; 1834 uint32_t icr; 1835 1836 Adapter = (struct e1000g *)arg; 1837 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1838 1839 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1840 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1841 1842 if (icr) { 1843 /* 1844 * Any bit was set in ICR: 1845 * Read(Clear) the ICR, claim this interrupt, 1846 * look for work to do. 1847 */ 1848 e1000g_intr_work(Adapter, icr); 1849 return (DDI_INTR_CLAIMED); 1850 } else { 1851 /* 1852 * No bit was set in ICR: 1853 * Don't claim this interrupt, return immediately. 1854 */ 1855 return (DDI_INTR_UNCLAIMED); 1856 } 1857 } 1858 1859 /* 1860 * e1000g_intr_work - actual processing of ISR 1861 * 1862 * Read(clear) the ICR contents and call appropriate interrupt 1863 * processing routines. 1864 */ 1865 static void 1866 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1867 { 1868 struct e1000_hw *hw; 1869 hw = &Adapter->shared; 1870 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1871 uint32_t itr; 1872 1873 Adapter->rx_pkt_cnt = 0; 1874 Adapter->tx_pkt_cnt = 0; 1875 1876 rw_enter(&Adapter->chip_lock, RW_READER); 1877 /* 1878 * Here we need to check the "chip_state" flag within the chip_lock to 1879 * ensure the receive routine will not execute when the adapter is 1880 * being reset. 1881 */ 1882 if (Adapter->chip_state != E1000G_START) { 1883 rw_exit(&Adapter->chip_lock); 1884 return; 1885 } 1886 1887 if (icr & E1000_ICR_RXT0) { 1888 mblk_t *mp; 1889 1890 mutex_enter(&Adapter->rx_ring->rx_lock); 1891 mp = e1000g_receive(Adapter); 1892 mutex_exit(&Adapter->rx_ring->rx_lock); 1893 1894 rw_exit(&Adapter->chip_lock); 1895 1896 if (mp != NULL) 1897 mac_rx(Adapter->mh, Adapter->mrh, mp); 1898 } else 1899 rw_exit(&Adapter->chip_lock); 1900 1901 if (icr & E1000_ICR_TXDW) { 1902 if (!Adapter->tx_intr_enable) 1903 e1000g_clear_tx_interrupt(Adapter); 1904 1905 /* Recycle the tx descriptors */ 1906 rw_enter(&Adapter->chip_lock, RW_READER); 1907 e1000g_recycle(tx_ring); 1908 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1909 rw_exit(&Adapter->chip_lock); 1910 1911 /* Schedule the re-transmit */ 1912 if (tx_ring->resched_needed && 1913 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1914 tx_ring->resched_needed = B_FALSE; 1915 mac_tx_update(Adapter->mh); 1916 E1000G_STAT(tx_ring->stat_reschedule); 1917 } 1918 } 1919 1920 if (Adapter->intr_adaptive) { 1921 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1922 Adapter->intr_throttling_rate); 1923 if (itr) { 1924 E1000_WRITE_REG(hw, E1000_ITR, itr); 1925 Adapter->intr_throttling_rate = itr; 1926 } 1927 } 1928 1929 /* 1930 * The Receive Sequence errors RXSEQ and the link status change LSC 1931 * are checked to detect that the cable has been pulled out. For 1932 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1933 * are an indication that cable is not connected. 1934 */ 1935 if ((icr & E1000_ICR_RXSEQ) || 1936 (icr & E1000_ICR_LSC) || 1937 (icr & E1000_ICR_GPI_EN1)) { 1938 boolean_t link_changed; 1939 timeout_id_t tid = 0; 1940 1941 stop_watchdog_timer(Adapter); 1942 1943 rw_enter(&Adapter->chip_lock, RW_WRITER); 1944 1945 /* 1946 * Because we got a link-status-change interrupt, force 1947 * e1000_check_for_link() to look at phy 1948 */ 1949 Adapter->shared.mac.get_link_status = B_TRUE; 1950 1951 /* e1000g_link_check takes care of link status change */ 1952 link_changed = e1000g_link_check(Adapter); 1953 1954 /* Get new phy state */ 1955 e1000g_get_phy_state(Adapter); 1956 1957 /* 1958 * If the link timer has not timed out, we'll not notify 1959 * the upper layer with any link state until the link is up. 1960 */ 1961 if (link_changed && !Adapter->link_complete) { 1962 if (Adapter->link_state == LINK_STATE_UP) { 1963 mutex_enter(&Adapter->link_lock); 1964 Adapter->link_complete = B_TRUE; 1965 tid = Adapter->link_tid; 1966 Adapter->link_tid = 0; 1967 mutex_exit(&Adapter->link_lock); 1968 } else { 1969 link_changed = B_FALSE; 1970 } 1971 } 1972 rw_exit(&Adapter->chip_lock); 1973 1974 if (link_changed) { 1975 if (tid != 0) 1976 (void) untimeout(tid); 1977 1978 /* 1979 * Workaround for esb2. Data stuck in fifo on a link 1980 * down event. Stop receiver here and reset in watchdog. 1981 */ 1982 if ((Adapter->link_state == LINK_STATE_DOWN) && 1983 (Adapter->shared.mac.type == e1000_80003es2lan)) { 1984 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 1985 E1000_WRITE_REG(hw, E1000_RCTL, 1986 rctl & ~E1000_RCTL_EN); 1987 e1000g_log(Adapter, CE_WARN, 1988 "ESB2 receiver disabled"); 1989 Adapter->esb2_workaround = B_TRUE; 1990 } 1991 1992 mac_link_update(Adapter->mh, Adapter->link_state); 1993 } 1994 1995 start_watchdog_timer(Adapter); 1996 } 1997 } 1998 1999 static uint32_t 2000 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 2001 { 2002 uint32_t new_itr; 2003 2004 /* 2005 * Determine a propper itr according to rx/tx packet count 2006 * per interrupt, the value of itr are based on document 2007 * and testing. 2008 */ 2009 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 2010 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 2011 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2012 goto itr_done; 2013 } 2014 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 2015 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 2016 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2017 goto itr_done; 2018 } 2019 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 2020 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 2021 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 2022 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2023 } else 2024 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2025 2026 itr_done: 2027 if (cur_itr == new_itr) 2028 return (0); 2029 else 2030 return (new_itr); 2031 } 2032 2033 static void 2034 e1000g_init_unicst(struct e1000g *Adapter) 2035 { 2036 struct e1000_hw *hw; 2037 int slot; 2038 2039 hw = &Adapter->shared; 2040 2041 if (!Adapter->unicst_init) { 2042 /* Initialize the multiple unicast addresses */ 2043 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2044 2045 if ((hw->mac.type == e1000_82571) && 2046 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2047 Adapter->unicst_total--; 2048 2049 Adapter->unicst_avail = Adapter->unicst_total - 1; 2050 2051 /* Store the default mac address */ 2052 e1000_rar_set(hw, hw->mac.addr, 0); 2053 if ((hw->mac.type == e1000_82571) && 2054 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2055 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2056 2057 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2058 ETHERADDRL); 2059 Adapter->unicst_addr[0].mac.set = 1; 2060 2061 for (slot = 1; slot < Adapter->unicst_total; slot++) 2062 Adapter->unicst_addr[slot].mac.set = 0; 2063 2064 Adapter->unicst_init = B_TRUE; 2065 } else { 2066 /* Recover the default mac address */ 2067 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2068 ETHERADDRL); 2069 2070 /* Store the default mac address */ 2071 e1000_rar_set(hw, hw->mac.addr, 0); 2072 if ((hw->mac.type == e1000_82571) && 2073 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2074 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2075 2076 /* Re-configure the RAR registers */ 2077 for (slot = 1; slot < Adapter->unicst_total; slot++) 2078 e1000_rar_set(hw, 2079 Adapter->unicst_addr[slot].mac.addr, slot); 2080 } 2081 2082 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2083 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2084 } 2085 2086 static int 2087 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2088 { 2089 struct e1000g *Adapter; 2090 2091 Adapter = (struct e1000g *)arg; 2092 2093 /* Store the default MAC address */ 2094 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2095 2096 /* Set MAC address in address slot 0, which is the default address */ 2097 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2098 } 2099 2100 static int 2101 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2102 mac_addr_slot_t slot) 2103 { 2104 struct e1000_hw *hw; 2105 2106 hw = &Adapter->shared; 2107 2108 rw_enter(&Adapter->chip_lock, RW_WRITER); 2109 2110 /* 2111 * The first revision of Wiseman silicon (rev 2.0) has an errata 2112 * that requires the receiver to be in reset when any of the 2113 * receive address registers (RAR regs) are accessed. The first 2114 * rev of Wiseman silicon also requires MWI to be disabled when 2115 * a global reset or a receive reset is issued. So before we 2116 * initialize the RARs, we check the rev of the Wiseman controller 2117 * and work around any necessary HW errata. 2118 */ 2119 if ((hw->mac.type == e1000_82542) && 2120 (hw->revision_id == E1000_REVISION_2)) { 2121 e1000_pci_clear_mwi(hw); 2122 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2123 msec_delay(5); 2124 } 2125 2126 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2127 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2128 2129 if (slot == 0) { 2130 if ((hw->mac.type == e1000_82571) && 2131 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2132 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2133 } 2134 2135 /* 2136 * If we are using Wiseman rev 2.0 silicon, we will have previously 2137 * put the receive in reset, and disabled MWI, to work around some 2138 * HW errata. Now we should take the receiver out of reset, and 2139 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2140 */ 2141 if ((hw->mac.type == e1000_82542) && 2142 (hw->revision_id == E1000_REVISION_2)) { 2143 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2144 msec_delay(1); 2145 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2146 e1000_pci_set_mwi(hw); 2147 e1000g_rx_setup(Adapter); 2148 } 2149 2150 rw_exit(&Adapter->chip_lock); 2151 2152 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2153 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2154 return (EIO); 2155 } 2156 2157 return (0); 2158 } 2159 2160 /* 2161 * e1000g_m_unicst_add() - will find an unused address slot, set the 2162 * address value to the one specified, reserve that slot and enable 2163 * the NIC to start filtering on the new MAC address. 2164 * Returns 0 on success. 2165 */ 2166 static int 2167 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2168 { 2169 struct e1000g *Adapter = (struct e1000g *)arg; 2170 mac_addr_slot_t slot; 2171 int err; 2172 2173 if (mac_unicst_verify(Adapter->mh, 2174 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2175 return (EINVAL); 2176 2177 rw_enter(&Adapter->chip_lock, RW_WRITER); 2178 if (Adapter->unicst_avail == 0) { 2179 /* no slots available */ 2180 rw_exit(&Adapter->chip_lock); 2181 return (ENOSPC); 2182 } 2183 2184 /* 2185 * Primary/default address is in slot 0. The next addresses 2186 * are the multiple MAC addresses. So multiple MAC address 0 2187 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2188 * MAC address resides in slot 1. 2189 */ 2190 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2191 if (Adapter->unicst_addr[slot].mac.set == 0) { 2192 Adapter->unicst_addr[slot].mac.set = 1; 2193 break; 2194 } 2195 } 2196 2197 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2198 2199 Adapter->unicst_avail--; 2200 rw_exit(&Adapter->chip_lock); 2201 2202 maddr->mma_slot = slot; 2203 2204 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2205 rw_enter(&Adapter->chip_lock, RW_WRITER); 2206 Adapter->unicst_addr[slot].mac.set = 0; 2207 Adapter->unicst_avail++; 2208 rw_exit(&Adapter->chip_lock); 2209 } 2210 2211 return (err); 2212 } 2213 2214 /* 2215 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2216 * call to e1000g_m_unicst_add(). The slot number that was returned in 2217 * e1000g_m_unicst_add() is passed in the call to remove the address. 2218 * Returns 0 on success. 2219 */ 2220 static int 2221 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2222 { 2223 struct e1000g *Adapter = (struct e1000g *)arg; 2224 int err; 2225 2226 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2227 return (EINVAL); 2228 2229 rw_enter(&Adapter->chip_lock, RW_WRITER); 2230 if (Adapter->unicst_addr[slot].mac.set == 1) { 2231 Adapter->unicst_addr[slot].mac.set = 0; 2232 Adapter->unicst_avail++; 2233 rw_exit(&Adapter->chip_lock); 2234 2235 /* Copy the default address to the passed slot */ 2236 if (err = e1000g_unicst_set(Adapter, 2237 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2238 rw_enter(&Adapter->chip_lock, RW_WRITER); 2239 Adapter->unicst_addr[slot].mac.set = 1; 2240 Adapter->unicst_avail--; 2241 rw_exit(&Adapter->chip_lock); 2242 } 2243 return (err); 2244 } 2245 rw_exit(&Adapter->chip_lock); 2246 2247 return (EINVAL); 2248 } 2249 2250 /* 2251 * e1000g_m_unicst_modify() - modifies the value of an address that 2252 * has been added by e1000g_m_unicst_add(). The new address, address 2253 * length and the slot number that was returned in the call to add 2254 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2255 * set to 0. Returns 0 on success. 2256 */ 2257 static int 2258 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2259 { 2260 struct e1000g *Adapter = (struct e1000g *)arg; 2261 mac_addr_slot_t slot; 2262 2263 if (mac_unicst_verify(Adapter->mh, 2264 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2265 return (EINVAL); 2266 2267 slot = maddr->mma_slot; 2268 2269 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2270 return (EINVAL); 2271 2272 rw_enter(&Adapter->chip_lock, RW_WRITER); 2273 if (Adapter->unicst_addr[slot].mac.set == 1) { 2274 rw_exit(&Adapter->chip_lock); 2275 2276 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2277 } 2278 rw_exit(&Adapter->chip_lock); 2279 2280 return (EINVAL); 2281 } 2282 2283 /* 2284 * e1000g_m_unicst_get() - will get the MAC address and all other 2285 * information related to the address slot passed in mac_multi_addr_t. 2286 * mma_flags should be set to 0 in the call. 2287 * On return, mma_flags can take the following values: 2288 * 1) MMAC_SLOT_UNUSED 2289 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2290 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2291 * 4) MMAC_SLOT_USED 2292 */ 2293 static int 2294 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2295 { 2296 struct e1000g *Adapter = (struct e1000g *)arg; 2297 mac_addr_slot_t slot; 2298 2299 slot = maddr->mma_slot; 2300 2301 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2302 return (EINVAL); 2303 2304 rw_enter(&Adapter->chip_lock, RW_WRITER); 2305 if (Adapter->unicst_addr[slot].mac.set == 1) { 2306 bcopy(Adapter->unicst_addr[slot].mac.addr, 2307 maddr->mma_addr, ETHERADDRL); 2308 maddr->mma_flags = MMAC_SLOT_USED; 2309 } else { 2310 maddr->mma_flags = MMAC_SLOT_UNUSED; 2311 } 2312 rw_exit(&Adapter->chip_lock); 2313 2314 return (0); 2315 } 2316 2317 static int 2318 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2319 { 2320 struct e1000_hw *hw = &Adapter->shared; 2321 unsigned i; 2322 int res = 0; 2323 2324 rw_enter(&Adapter->chip_lock, RW_WRITER); 2325 2326 if ((multiaddr[0] & 01) == 0) { 2327 res = EINVAL; 2328 goto done; 2329 } 2330 2331 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2332 res = ENOENT; 2333 goto done; 2334 } 2335 2336 bcopy(multiaddr, 2337 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2338 Adapter->mcast_count++; 2339 2340 /* 2341 * Update the MC table in the hardware 2342 */ 2343 e1000g_clear_interrupt(Adapter); 2344 2345 e1000g_setup_multicast(Adapter); 2346 2347 if ((hw->mac.type == e1000_82542) && 2348 (hw->revision_id == E1000_REVISION_2)) 2349 e1000g_rx_setup(Adapter); 2350 2351 e1000g_mask_interrupt(Adapter); 2352 2353 done: 2354 rw_exit(&Adapter->chip_lock); 2355 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2356 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2357 res = EIO; 2358 } 2359 2360 return (res); 2361 } 2362 2363 static int 2364 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2365 { 2366 struct e1000_hw *hw = &Adapter->shared; 2367 unsigned i; 2368 2369 rw_enter(&Adapter->chip_lock, RW_WRITER); 2370 2371 for (i = 0; i < Adapter->mcast_count; i++) { 2372 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2373 ETHERADDRL) == 0) { 2374 for (i++; i < Adapter->mcast_count; i++) { 2375 Adapter->mcast_table[i - 1] = 2376 Adapter->mcast_table[i]; 2377 } 2378 Adapter->mcast_count--; 2379 break; 2380 } 2381 } 2382 2383 /* 2384 * Update the MC table in the hardware 2385 */ 2386 e1000g_clear_interrupt(Adapter); 2387 2388 e1000g_setup_multicast(Adapter); 2389 2390 if ((hw->mac.type == e1000_82542) && 2391 (hw->revision_id == E1000_REVISION_2)) 2392 e1000g_rx_setup(Adapter); 2393 2394 e1000g_mask_interrupt(Adapter); 2395 2396 done: 2397 rw_exit(&Adapter->chip_lock); 2398 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2399 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2400 return (EIO); 2401 } 2402 2403 return (0); 2404 } 2405 2406 /* 2407 * e1000g_setup_multicast - setup multicast data structures 2408 * 2409 * This routine initializes all of the multicast related structures. 2410 */ 2411 void 2412 e1000g_setup_multicast(struct e1000g *Adapter) 2413 { 2414 uint8_t *mc_addr_list; 2415 uint32_t mc_addr_count; 2416 uint32_t rctl; 2417 struct e1000_hw *hw; 2418 2419 hw = &Adapter->shared; 2420 2421 /* 2422 * The e1000g has the ability to do perfect filtering of 16 2423 * addresses. The driver uses one of the e1000g's 16 receive 2424 * address registers for its node/network/mac/individual address. 2425 * So, we have room for up to 15 multicast addresses in the CAM, 2426 * additional MC addresses are handled by the MTA (Multicast Table 2427 * Array) 2428 */ 2429 2430 rctl = E1000_READ_REG(hw, E1000_RCTL); 2431 2432 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2433 2434 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2435 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2436 "Adapter requested more than %d MC Addresses.\n", 2437 MAX_NUM_MULTICAST_ADDRESSES); 2438 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2439 } else { 2440 /* 2441 * Set the number of MC addresses that we are being 2442 * requested to use 2443 */ 2444 mc_addr_count = Adapter->mcast_count; 2445 } 2446 /* 2447 * The Wiseman 2.0 silicon has an errata by which the receiver will 2448 * hang while writing to the receive address registers if the receiver 2449 * is not in reset before writing to the registers. Updating the RAR 2450 * is done during the setting up of the multicast table, hence the 2451 * receiver has to be put in reset before updating the multicast table 2452 * and then taken out of reset at the end 2453 */ 2454 /* 2455 * if WMI was enabled then dis able it before issueing the global 2456 * reset to the hardware. 2457 */ 2458 /* 2459 * Only required for WISEMAN_2_0 2460 */ 2461 if ((hw->mac.type == e1000_82542) && 2462 (hw->revision_id == E1000_REVISION_2)) { 2463 e1000_pci_clear_mwi(hw); 2464 /* 2465 * The e1000g must be in reset before changing any RA 2466 * registers. Reset receive unit. The chip will remain in 2467 * the reset state until software explicitly restarts it. 2468 */ 2469 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2470 /* Allow receiver time to go in to reset */ 2471 msec_delay(5); 2472 } 2473 2474 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2475 Adapter->unicst_total, hw->mac.rar_entry_count); 2476 2477 /* 2478 * Only for Wiseman_2_0 2479 * If MWI was enabled then re-enable it after issueing (as we 2480 * disabled it up there) the receive reset command. 2481 * Wainwright does not have a receive reset command and only thing 2482 * close to it is global reset which will require tx setup also 2483 */ 2484 if ((hw->mac.type == e1000_82542) && 2485 (hw->revision_id == E1000_REVISION_2)) { 2486 /* 2487 * if WMI was enabled then reenable it after issueing the 2488 * global or receive reset to the hardware. 2489 */ 2490 2491 /* 2492 * Take receiver out of reset 2493 * clear E1000_RCTL_RST bit (and all others) 2494 */ 2495 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2496 msec_delay(5); 2497 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2498 e1000_pci_set_mwi(hw); 2499 } 2500 2501 /* 2502 * Restore original value 2503 */ 2504 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2505 } 2506 2507 int 2508 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2509 { 2510 struct e1000g *Adapter = (struct e1000g *)arg; 2511 2512 return ((add) ? multicst_add(Adapter, addr) 2513 : multicst_remove(Adapter, addr)); 2514 } 2515 2516 int 2517 e1000g_m_promisc(void *arg, boolean_t on) 2518 { 2519 struct e1000g *Adapter = (struct e1000g *)arg; 2520 uint32_t rctl; 2521 2522 rw_enter(&Adapter->chip_lock, RW_WRITER); 2523 2524 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2525 2526 if (on) 2527 rctl |= 2528 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2529 else 2530 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2531 2532 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2533 2534 Adapter->e1000g_promisc = on; 2535 2536 rw_exit(&Adapter->chip_lock); 2537 2538 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2539 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2540 return (EIO); 2541 } 2542 2543 return (0); 2544 } 2545 2546 static boolean_t 2547 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2548 { 2549 struct e1000g *Adapter = (struct e1000g *)arg; 2550 struct e1000_hw *hw = &Adapter->shared; 2551 2552 switch (cap) { 2553 case MAC_CAPAB_HCKSUM: { 2554 uint32_t *txflags = cap_data; 2555 2556 if (Adapter->tx_hcksum_enable) 2557 *txflags = HCKSUM_IPHDRCKSUM | 2558 HCKSUM_INET_PARTIAL; 2559 else 2560 return (B_FALSE); 2561 break; 2562 } 2563 case MAC_CAPAB_POLL: 2564 /* 2565 * There's nothing for us to fill in, simply returning 2566 * B_TRUE stating that we support polling is sufficient. 2567 */ 2568 break; 2569 2570 case MAC_CAPAB_MULTIADDRESS: { 2571 multiaddress_capab_t *mmacp = cap_data; 2572 2573 /* 2574 * The number of MAC addresses made available by 2575 * this capability is one less than the total as 2576 * the primary address in slot 0 is counted in 2577 * the total. 2578 */ 2579 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2580 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2581 /* No multiple factory addresses, set mma_flag to 0 */ 2582 mmacp->maddr_flag = 0; 2583 mmacp->maddr_handle = Adapter; 2584 mmacp->maddr_add = e1000g_m_unicst_add; 2585 mmacp->maddr_remove = e1000g_m_unicst_remove; 2586 mmacp->maddr_modify = e1000g_m_unicst_modify; 2587 mmacp->maddr_get = e1000g_m_unicst_get; 2588 mmacp->maddr_reserve = NULL; 2589 break; 2590 } 2591 2592 case MAC_CAPAB_LSO: { 2593 mac_capab_lso_t *cap_lso = cap_data; 2594 2595 if (Adapter->lso_enable) { 2596 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2597 cap_lso->lso_basic_tcp_ipv4.lso_max = 2598 E1000_LSO_MAXLEN; 2599 } else 2600 return (B_FALSE); 2601 break; 2602 } 2603 2604 default: 2605 return (B_FALSE); 2606 } 2607 return (B_TRUE); 2608 } 2609 2610 static boolean_t 2611 e1000g_param_locked(mac_prop_id_t pr_num) 2612 { 2613 /* 2614 * All en_* parameters are locked (read-only) while 2615 * the device is in any sort of loopback mode ... 2616 */ 2617 switch (pr_num) { 2618 case MAC_PROP_EN_1000FDX_CAP: 2619 case MAC_PROP_EN_1000HDX_CAP: 2620 case MAC_PROP_EN_100FDX_CAP: 2621 case MAC_PROP_EN_100HDX_CAP: 2622 case MAC_PROP_EN_10FDX_CAP: 2623 case MAC_PROP_EN_10HDX_CAP: 2624 case MAC_PROP_AUTONEG: 2625 case MAC_PROP_FLOWCTRL: 2626 return (B_TRUE); 2627 } 2628 return (B_FALSE); 2629 } 2630 2631 /* 2632 * callback function for set/get of properties 2633 */ 2634 static int 2635 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2636 uint_t pr_valsize, const void *pr_val) 2637 { 2638 struct e1000g *Adapter = arg; 2639 struct e1000_mac_info *mac = &Adapter->shared.mac; 2640 struct e1000_phy_info *phy = &Adapter->shared.phy; 2641 struct e1000_fc_info *fc = &Adapter->shared.fc; 2642 int err = 0; 2643 link_flowctrl_t flowctrl; 2644 uint32_t cur_mtu, new_mtu; 2645 uint64_t tmp = 0; 2646 2647 rw_enter(&Adapter->chip_lock, RW_WRITER); 2648 if (Adapter->loopback_mode != E1000G_LB_NONE && 2649 e1000g_param_locked(pr_num)) { 2650 /* 2651 * All en_* parameters are locked (read-only) 2652 * while the device is in any sort of loopback mode. 2653 */ 2654 rw_exit(&Adapter->chip_lock); 2655 return (EBUSY); 2656 } 2657 2658 switch (pr_num) { 2659 case MAC_PROP_EN_1000FDX_CAP: 2660 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2661 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2662 goto reset; 2663 case MAC_PROP_EN_1000HDX_CAP: 2664 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2665 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2666 goto reset; 2667 case MAC_PROP_EN_100FDX_CAP: 2668 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2669 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2670 goto reset; 2671 case MAC_PROP_EN_100HDX_CAP: 2672 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2673 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2674 goto reset; 2675 case MAC_PROP_EN_10FDX_CAP: 2676 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2677 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2678 goto reset; 2679 case MAC_PROP_EN_10HDX_CAP: 2680 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2681 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2682 goto reset; 2683 case MAC_PROP_AUTONEG: 2684 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2685 goto reset; 2686 case MAC_PROP_FLOWCTRL: 2687 fc->send_xon = B_TRUE; 2688 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2689 2690 switch (flowctrl) { 2691 default: 2692 err = EINVAL; 2693 break; 2694 case LINK_FLOWCTRL_NONE: 2695 fc->type = e1000_fc_none; 2696 break; 2697 case LINK_FLOWCTRL_RX: 2698 fc->type = e1000_fc_rx_pause; 2699 break; 2700 case LINK_FLOWCTRL_TX: 2701 fc->type = e1000_fc_tx_pause; 2702 break; 2703 case LINK_FLOWCTRL_BI: 2704 fc->type = e1000_fc_full; 2705 break; 2706 } 2707 reset: 2708 if (err == 0) { 2709 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2710 err = EINVAL; 2711 } 2712 break; 2713 case MAC_PROP_ADV_1000FDX_CAP: 2714 case MAC_PROP_ADV_1000HDX_CAP: 2715 case MAC_PROP_ADV_100FDX_CAP: 2716 case MAC_PROP_ADV_100HDX_CAP: 2717 case MAC_PROP_ADV_10FDX_CAP: 2718 case MAC_PROP_ADV_10HDX_CAP: 2719 case MAC_PROP_STATUS: 2720 case MAC_PROP_SPEED: 2721 case MAC_PROP_DUPLEX: 2722 err = ENOTSUP; /* read-only prop. Can't set this. */ 2723 break; 2724 case MAC_PROP_MTU: 2725 cur_mtu = Adapter->default_mtu; 2726 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2727 if (new_mtu == cur_mtu) { 2728 err = 0; 2729 break; 2730 } 2731 2732 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2733 ETHERFCSL; 2734 if ((tmp < DEFAULT_FRAME_SIZE) || 2735 (tmp > MAXIMUM_FRAME_SIZE)) { 2736 err = EINVAL; 2737 break; 2738 } 2739 2740 /* ich8 doed not support jumbo frames */ 2741 if ((mac->type == e1000_ich8lan) && 2742 (tmp > DEFAULT_FRAME_SIZE)) { 2743 err = EINVAL; 2744 break; 2745 } 2746 /* ich9 does not do jumbo frames on one phy type */ 2747 if ((mac->type == e1000_ich9lan) && 2748 (phy->type == e1000_phy_ife) && 2749 (tmp > DEFAULT_FRAME_SIZE)) { 2750 err = EINVAL; 2751 break; 2752 } 2753 if (Adapter->chip_state != E1000G_STOP) { 2754 err = EBUSY; 2755 break; 2756 } 2757 2758 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2759 if (err == 0) { 2760 Adapter->max_frame_size = tmp; 2761 Adapter->default_mtu = new_mtu; 2762 e1000g_set_bufsize(Adapter); 2763 } 2764 break; 2765 case MAC_PROP_PRIVATE: 2766 err = e1000g_set_priv_prop(Adapter, pr_name, 2767 pr_valsize, pr_val); 2768 break; 2769 default: 2770 err = ENOTSUP; 2771 break; 2772 } 2773 rw_exit(&Adapter->chip_lock); 2774 return (err); 2775 } 2776 2777 static int 2778 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2779 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2780 { 2781 struct e1000g *Adapter = arg; 2782 struct e1000_mac_info *mac = &Adapter->shared.mac; 2783 struct e1000_fc_info *fc = &Adapter->shared.fc; 2784 int err = 0; 2785 link_flowctrl_t flowctrl; 2786 uint64_t tmp = 0; 2787 2788 if (pr_valsize == 0) 2789 return (EINVAL); 2790 2791 bzero(pr_val, pr_valsize); 2792 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2793 return (e1000g_get_def_val(Adapter, pr_num, 2794 pr_valsize, pr_val)); 2795 } 2796 2797 switch (pr_num) { 2798 case MAC_PROP_DUPLEX: 2799 if (pr_valsize >= sizeof (link_duplex_t)) { 2800 bcopy(&Adapter->link_duplex, pr_val, 2801 sizeof (link_duplex_t)); 2802 } else 2803 err = EINVAL; 2804 break; 2805 case MAC_PROP_SPEED: 2806 if (pr_valsize >= sizeof (uint64_t)) { 2807 tmp = Adapter->link_speed * 1000000ull; 2808 bcopy(&tmp, pr_val, sizeof (tmp)); 2809 } else 2810 err = EINVAL; 2811 break; 2812 case MAC_PROP_AUTONEG: 2813 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2814 break; 2815 case MAC_PROP_FLOWCTRL: 2816 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2817 switch (fc->type) { 2818 case e1000_fc_none: 2819 flowctrl = LINK_FLOWCTRL_NONE; 2820 break; 2821 case e1000_fc_rx_pause: 2822 flowctrl = LINK_FLOWCTRL_RX; 2823 break; 2824 case e1000_fc_tx_pause: 2825 flowctrl = LINK_FLOWCTRL_TX; 2826 break; 2827 case e1000_fc_full: 2828 flowctrl = LINK_FLOWCTRL_BI; 2829 break; 2830 } 2831 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2832 } else 2833 err = EINVAL; 2834 break; 2835 case MAC_PROP_ADV_1000FDX_CAP: 2836 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2837 break; 2838 case MAC_PROP_EN_1000FDX_CAP: 2839 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2840 break; 2841 case MAC_PROP_ADV_1000HDX_CAP: 2842 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2843 break; 2844 case MAC_PROP_EN_1000HDX_CAP: 2845 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2846 break; 2847 case MAC_PROP_ADV_100FDX_CAP: 2848 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2849 break; 2850 case MAC_PROP_EN_100FDX_CAP: 2851 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2852 break; 2853 case MAC_PROP_ADV_100HDX_CAP: 2854 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2855 break; 2856 case MAC_PROP_EN_100HDX_CAP: 2857 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2858 break; 2859 case MAC_PROP_ADV_10FDX_CAP: 2860 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2861 break; 2862 case MAC_PROP_EN_10FDX_CAP: 2863 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2864 break; 2865 case MAC_PROP_ADV_10HDX_CAP: 2866 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2867 break; 2868 case MAC_PROP_EN_10HDX_CAP: 2869 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2870 break; 2871 case MAC_PROP_ADV_100T4_CAP: 2872 case MAC_PROP_EN_100T4_CAP: 2873 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2874 break; 2875 case MAC_PROP_PRIVATE: 2876 err = e1000g_get_priv_prop(Adapter, pr_name, 2877 pr_flags, pr_valsize, pr_val); 2878 break; 2879 default: 2880 err = ENOTSUP; 2881 break; 2882 } 2883 return (err); 2884 } 2885 2886 /* ARGUSED */ 2887 static int 2888 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2889 uint_t pr_valsize, const void *pr_val) 2890 { 2891 int err = 0; 2892 long result; 2893 struct e1000_hw *hw = &Adapter->shared; 2894 2895 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2896 if (pr_val == NULL) { 2897 err = EINVAL; 2898 return (err); 2899 } 2900 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2901 if (result < MIN_TX_BCOPY_THRESHOLD || 2902 result > MAX_TX_BCOPY_THRESHOLD) 2903 err = EINVAL; 2904 else { 2905 Adapter->tx_bcopy_thresh = (uint32_t)result; 2906 } 2907 return (err); 2908 } 2909 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2910 if (pr_val == NULL) { 2911 err = EINVAL; 2912 return (err); 2913 } 2914 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2915 if (result < 0 || result > 1) 2916 err = EINVAL; 2917 else { 2918 Adapter->tx_intr_enable = (result == 1) ? 2919 B_TRUE: B_FALSE; 2920 if (Adapter->tx_intr_enable) 2921 e1000g_mask_tx_interrupt(Adapter); 2922 else 2923 e1000g_clear_tx_interrupt(Adapter); 2924 if (e1000g_check_acc_handle( 2925 Adapter->osdep.reg_handle) != DDI_FM_OK) 2926 ddi_fm_service_impact(Adapter->dip, 2927 DDI_SERVICE_DEGRADED); 2928 } 2929 return (err); 2930 } 2931 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2932 if (pr_val == NULL) { 2933 err = EINVAL; 2934 return (err); 2935 } 2936 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2937 if (result < MIN_TX_INTR_DELAY || 2938 result > MAX_TX_INTR_DELAY) 2939 err = EINVAL; 2940 else { 2941 Adapter->tx_intr_delay = (uint32_t)result; 2942 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2943 if (e1000g_check_acc_handle( 2944 Adapter->osdep.reg_handle) != DDI_FM_OK) 2945 ddi_fm_service_impact(Adapter->dip, 2946 DDI_SERVICE_DEGRADED); 2947 } 2948 return (err); 2949 } 2950 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2951 if (pr_val == NULL) { 2952 err = EINVAL; 2953 return (err); 2954 } 2955 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2956 if (result < MIN_TX_INTR_ABS_DELAY || 2957 result > MAX_TX_INTR_ABS_DELAY) 2958 err = EINVAL; 2959 else { 2960 Adapter->tx_intr_abs_delay = (uint32_t)result; 2961 E1000_WRITE_REG(hw, E1000_TADV, 2962 Adapter->tx_intr_abs_delay); 2963 if (e1000g_check_acc_handle( 2964 Adapter->osdep.reg_handle) != DDI_FM_OK) 2965 ddi_fm_service_impact(Adapter->dip, 2966 DDI_SERVICE_DEGRADED); 2967 } 2968 return (err); 2969 } 2970 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2971 if (pr_val == NULL) { 2972 err = EINVAL; 2973 return (err); 2974 } 2975 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2976 if (result < MIN_RX_BCOPY_THRESHOLD || 2977 result > MAX_RX_BCOPY_THRESHOLD) 2978 err = EINVAL; 2979 else 2980 Adapter->rx_bcopy_thresh = (uint32_t)result; 2981 return (err); 2982 } 2983 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 2984 if (pr_val == NULL) { 2985 err = EINVAL; 2986 return (err); 2987 } 2988 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2989 if (result < MIN_RX_LIMIT_ON_INTR || 2990 result > MAX_RX_LIMIT_ON_INTR) 2991 err = EINVAL; 2992 else 2993 Adapter->rx_limit_onintr = (uint32_t)result; 2994 return (err); 2995 } 2996 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 2997 if (pr_val == NULL) { 2998 err = EINVAL; 2999 return (err); 3000 } 3001 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3002 if (result < MIN_RX_INTR_DELAY || 3003 result > MAX_RX_INTR_DELAY) 3004 err = EINVAL; 3005 else { 3006 Adapter->rx_intr_delay = (uint32_t)result; 3007 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3008 if (e1000g_check_acc_handle( 3009 Adapter->osdep.reg_handle) != DDI_FM_OK) 3010 ddi_fm_service_impact(Adapter->dip, 3011 DDI_SERVICE_DEGRADED); 3012 } 3013 return (err); 3014 } 3015 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3016 if (pr_val == NULL) { 3017 err = EINVAL; 3018 return (err); 3019 } 3020 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3021 if (result < MIN_RX_INTR_ABS_DELAY || 3022 result > MAX_RX_INTR_ABS_DELAY) 3023 err = EINVAL; 3024 else { 3025 Adapter->rx_intr_abs_delay = (uint32_t)result; 3026 E1000_WRITE_REG(hw, E1000_RADV, 3027 Adapter->rx_intr_abs_delay); 3028 if (e1000g_check_acc_handle( 3029 Adapter->osdep.reg_handle) != DDI_FM_OK) 3030 ddi_fm_service_impact(Adapter->dip, 3031 DDI_SERVICE_DEGRADED); 3032 } 3033 return (err); 3034 } 3035 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3036 if (pr_val == NULL) { 3037 err = EINVAL; 3038 return (err); 3039 } 3040 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3041 if (result < MIN_INTR_THROTTLING || 3042 result > MAX_INTR_THROTTLING) 3043 err = EINVAL; 3044 else { 3045 if (hw->mac.type >= e1000_82540) { 3046 Adapter->intr_throttling_rate = 3047 (uint32_t)result; 3048 E1000_WRITE_REG(hw, E1000_ITR, 3049 Adapter->intr_throttling_rate); 3050 if (e1000g_check_acc_handle( 3051 Adapter->osdep.reg_handle) != DDI_FM_OK) 3052 ddi_fm_service_impact(Adapter->dip, 3053 DDI_SERVICE_DEGRADED); 3054 } else 3055 err = EINVAL; 3056 } 3057 return (err); 3058 } 3059 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3060 if (pr_val == NULL) { 3061 err = EINVAL; 3062 return (err); 3063 } 3064 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3065 if (result < 0 || result > 1) 3066 err = EINVAL; 3067 else { 3068 if (hw->mac.type >= e1000_82540) { 3069 Adapter->intr_adaptive = (result == 1) ? 3070 B_TRUE : B_FALSE; 3071 } else { 3072 err = EINVAL; 3073 } 3074 } 3075 return (err); 3076 } 3077 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3078 if (pr_val == NULL) { 3079 err = EINVAL; 3080 return (err); 3081 } 3082 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3083 if (result < MIN_TX_RECYCLE_THRESHOLD || 3084 result > MAX_TX_RECYCLE_THRESHOLD) 3085 err = EINVAL; 3086 else 3087 Adapter->tx_recycle_thresh = (uint32_t)result; 3088 return (err); 3089 } 3090 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3091 if (pr_val == NULL) { 3092 err = EINVAL; 3093 return (err); 3094 } 3095 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3096 if (result < MIN_TX_RECYCLE_NUM || 3097 result > MAX_TX_RECYCLE_NUM) 3098 err = EINVAL; 3099 else 3100 Adapter->tx_recycle_num = (uint32_t)result; 3101 return (err); 3102 } 3103 return (ENOTSUP); 3104 } 3105 3106 static int 3107 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3108 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3109 { 3110 char valstr[MAXNAMELEN]; 3111 int err = ENOTSUP; 3112 uint_t strsize; 3113 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3114 int value; 3115 3116 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3117 if (is_default) 3118 goto done; 3119 value = Adapter->param_adv_pause; 3120 err = 0; 3121 goto done; 3122 } 3123 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3124 if (is_default) 3125 goto done; 3126 value = Adapter->param_adv_asym_pause; 3127 err = 0; 3128 goto done; 3129 } 3130 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3131 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3132 Adapter->tx_bcopy_thresh); 3133 err = 0; 3134 goto done; 3135 } 3136 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3137 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3138 Adapter->tx_intr_enable); 3139 err = 0; 3140 goto done; 3141 } 3142 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3143 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3144 Adapter->tx_intr_delay); 3145 err = 0; 3146 goto done; 3147 } 3148 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3149 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3150 Adapter->tx_intr_abs_delay); 3151 err = 0; 3152 goto done; 3153 } 3154 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3155 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3156 Adapter->rx_bcopy_thresh); 3157 err = 0; 3158 goto done; 3159 } 3160 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3161 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3162 Adapter->rx_limit_onintr); 3163 err = 0; 3164 goto done; 3165 } 3166 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3167 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3168 Adapter->rx_intr_delay); 3169 err = 0; 3170 goto done; 3171 } 3172 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3173 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3174 Adapter->rx_intr_abs_delay); 3175 err = 0; 3176 goto done; 3177 } 3178 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3179 value = (is_default ? DEFAULT_INTR_THROTTLING : 3180 Adapter->intr_throttling_rate); 3181 err = 0; 3182 goto done; 3183 } 3184 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3185 value = (is_default ? 1 : Adapter->intr_adaptive); 3186 err = 0; 3187 goto done; 3188 } 3189 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3190 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3191 Adapter->tx_recycle_thresh); 3192 err = 0; 3193 goto done; 3194 } 3195 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3196 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3197 Adapter->tx_recycle_num); 3198 err = 0; 3199 goto done; 3200 } 3201 done: 3202 if (err == 0) { 3203 (void) snprintf(pr_val, pr_valsize, "%d", value); 3204 } 3205 return (err); 3206 } 3207 3208 /* 3209 * e1000g_get_conf - get configurations set in e1000g.conf 3210 * This routine gets user-configured values out of the configuration 3211 * file e1000g.conf. 3212 * 3213 * For each configurable value, there is a minimum, a maximum, and a 3214 * default. 3215 * If user does not configure a value, use the default. 3216 * If user configures below the minimum, use the minumum. 3217 * If user configures above the maximum, use the maxumum. 3218 */ 3219 static void 3220 e1000g_get_conf(struct e1000g *Adapter) 3221 { 3222 struct e1000_hw *hw = &Adapter->shared; 3223 boolean_t tbi_compatibility = B_FALSE; 3224 3225 /* 3226 * get each configurable property from e1000g.conf 3227 */ 3228 3229 /* 3230 * NumTxDescriptors 3231 */ 3232 Adapter->tx_desc_num = 3233 e1000g_get_prop(Adapter, "NumTxDescriptors", 3234 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3235 DEFAULT_NUM_TX_DESCRIPTOR); 3236 3237 /* 3238 * NumRxDescriptors 3239 */ 3240 Adapter->rx_desc_num = 3241 e1000g_get_prop(Adapter, "NumRxDescriptors", 3242 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3243 DEFAULT_NUM_RX_DESCRIPTOR); 3244 3245 /* 3246 * NumRxFreeList 3247 */ 3248 Adapter->rx_freelist_num = 3249 e1000g_get_prop(Adapter, "NumRxFreeList", 3250 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3251 DEFAULT_NUM_RX_FREELIST); 3252 3253 /* 3254 * NumTxPacketList 3255 */ 3256 Adapter->tx_freelist_num = 3257 e1000g_get_prop(Adapter, "NumTxPacketList", 3258 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3259 DEFAULT_NUM_TX_FREELIST); 3260 3261 /* 3262 * FlowControl 3263 */ 3264 hw->fc.send_xon = B_TRUE; 3265 hw->fc.type = 3266 e1000g_get_prop(Adapter, "FlowControl", 3267 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3268 /* 4 is the setting that says "let the eeprom decide" */ 3269 if (hw->fc.type == 4) 3270 hw->fc.type = e1000_fc_default; 3271 3272 /* 3273 * Max Num Receive Packets on Interrupt 3274 */ 3275 Adapter->rx_limit_onintr = 3276 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3277 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3278 DEFAULT_RX_LIMIT_ON_INTR); 3279 3280 /* 3281 * PHY master slave setting 3282 */ 3283 hw->phy.ms_type = 3284 e1000g_get_prop(Adapter, "SetMasterSlave", 3285 e1000_ms_hw_default, e1000_ms_auto, 3286 e1000_ms_hw_default); 3287 3288 /* 3289 * Parameter which controls TBI mode workaround, which is only 3290 * needed on certain switches such as Cisco 6500/Foundry 3291 */ 3292 tbi_compatibility = 3293 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3294 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3295 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3296 3297 /* 3298 * MSI Enable 3299 */ 3300 Adapter->msi_enable = 3301 e1000g_get_prop(Adapter, "MSIEnable", 3302 0, 1, DEFAULT_MSI_ENABLE); 3303 3304 /* 3305 * Interrupt Throttling Rate 3306 */ 3307 Adapter->intr_throttling_rate = 3308 e1000g_get_prop(Adapter, "intr_throttling_rate", 3309 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3310 DEFAULT_INTR_THROTTLING); 3311 3312 /* 3313 * Adaptive Interrupt Blanking Enable/Disable 3314 * It is enabled by default 3315 */ 3316 Adapter->intr_adaptive = 3317 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3318 B_TRUE : B_FALSE; 3319 3320 /* 3321 * Tx recycle threshold 3322 */ 3323 Adapter->tx_recycle_thresh = 3324 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3325 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3326 DEFAULT_TX_RECYCLE_THRESHOLD); 3327 3328 /* 3329 * Tx recycle descriptor number 3330 */ 3331 Adapter->tx_recycle_num = 3332 e1000g_get_prop(Adapter, "tx_recycle_num", 3333 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3334 DEFAULT_TX_RECYCLE_NUM); 3335 3336 /* 3337 * Hardware checksum enable/disable parameter 3338 */ 3339 Adapter->tx_hcksum_enable = 3340 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3341 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3342 /* 3343 * Checksum on/off selection via global parameters. 3344 * 3345 * If the chip is flagged as not capable of (correctly) 3346 * handling checksumming, we don't enable it on either 3347 * Rx or Tx side. Otherwise, we take this chip's settings 3348 * from the patchable global defaults. 3349 * 3350 * We advertise our capabilities only if TX offload is 3351 * enabled. On receive, the stack will accept checksummed 3352 * packets anyway, even if we haven't said we can deliver 3353 * them. 3354 */ 3355 switch (hw->mac.type) { 3356 case e1000_82540: 3357 case e1000_82544: 3358 case e1000_82545: 3359 case e1000_82545_rev_3: 3360 case e1000_82546: 3361 case e1000_82546_rev_3: 3362 case e1000_82571: 3363 case e1000_82572: 3364 case e1000_82573: 3365 case e1000_80003es2lan: 3366 break; 3367 /* 3368 * For the following Intel PRO/1000 chipsets, we have not 3369 * tested the hardware checksum offload capability, so we 3370 * disable the capability for them. 3371 * e1000_82542, 3372 * e1000_82543, 3373 * e1000_82541, 3374 * e1000_82541_rev_2, 3375 * e1000_82547, 3376 * e1000_82547_rev_2, 3377 */ 3378 default: 3379 Adapter->tx_hcksum_enable = B_FALSE; 3380 } 3381 3382 /* 3383 * Large Send Offloading(LSO) Enable/Disable 3384 * If the tx hardware checksum is not enabled, LSO should be 3385 * disabled. 3386 */ 3387 Adapter->lso_enable = 3388 e1000g_get_prop(Adapter, "lso_enable", 3389 0, 1, DEFAULT_LSO_ENABLE); 3390 3391 switch (hw->mac.type) { 3392 case e1000_82546: 3393 case e1000_82546_rev_3: 3394 if (Adapter->lso_enable) 3395 Adapter->lso_premature_issue = B_TRUE; 3396 case e1000_82571: 3397 case e1000_82572: 3398 case e1000_82573: 3399 break; 3400 default: 3401 Adapter->lso_enable = B_FALSE; 3402 } 3403 3404 if (!Adapter->tx_hcksum_enable) { 3405 Adapter->lso_premature_issue = B_FALSE; 3406 Adapter->lso_enable = B_FALSE; 3407 } 3408 } 3409 3410 /* 3411 * e1000g_get_prop - routine to read properties 3412 * 3413 * Get a user-configure property value out of the configuration 3414 * file e1000g.conf. 3415 * 3416 * Caller provides name of the property, a default value, a minimum 3417 * value, and a maximum value. 3418 * 3419 * Return configured value of the property, with default, minimum and 3420 * maximum properly applied. 3421 */ 3422 static int 3423 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3424 char *propname, /* name of the property */ 3425 int minval, /* minimum acceptable value */ 3426 int maxval, /* maximim acceptable value */ 3427 int defval) /* default value */ 3428 { 3429 int propval; /* value returned for requested property */ 3430 int *props; /* point to array of properties returned */ 3431 uint_t nprops; /* number of property value returned */ 3432 3433 /* 3434 * get the array of properties from the config file 3435 */ 3436 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3437 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3438 /* got some properties, test if we got enough */ 3439 if (Adapter->instance < nprops) { 3440 propval = props[Adapter->instance]; 3441 } else { 3442 /* not enough properties configured */ 3443 propval = defval; 3444 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3445 "Not Enough %s values found in e1000g.conf" 3446 " - set to %d\n", 3447 propname, propval); 3448 } 3449 3450 /* free memory allocated for properties */ 3451 ddi_prop_free(props); 3452 3453 } else { 3454 propval = defval; 3455 } 3456 3457 /* 3458 * enforce limits 3459 */ 3460 if (propval > maxval) { 3461 propval = maxval; 3462 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3463 "Too High %s value in e1000g.conf - set to %d\n", 3464 propname, propval); 3465 } 3466 3467 if (propval < minval) { 3468 propval = minval; 3469 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3470 "Too Low %s value in e1000g.conf - set to %d\n", 3471 propname, propval); 3472 } 3473 3474 return (propval); 3475 } 3476 3477 static boolean_t 3478 e1000g_link_check(struct e1000g *Adapter) 3479 { 3480 uint16_t speed, duplex, phydata; 3481 boolean_t link_changed = B_FALSE; 3482 struct e1000_hw *hw; 3483 uint32_t reg_tarc; 3484 3485 hw = &Adapter->shared; 3486 3487 if (e1000g_link_up(Adapter)) { 3488 /* 3489 * The Link is up, check whether it was marked as down earlier 3490 */ 3491 if (Adapter->link_state != LINK_STATE_UP) { 3492 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3493 Adapter->link_speed = speed; 3494 Adapter->link_duplex = duplex; 3495 Adapter->link_state = LINK_STATE_UP; 3496 link_changed = B_TRUE; 3497 3498 Adapter->tx_link_down_timeout = 0; 3499 3500 if ((hw->mac.type == e1000_82571) || 3501 (hw->mac.type == e1000_82572)) { 3502 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3503 if (speed == SPEED_1000) 3504 reg_tarc |= (1 << 21); 3505 else 3506 reg_tarc &= ~(1 << 21); 3507 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3508 } 3509 } 3510 Adapter->smartspeed = 0; 3511 } else { 3512 if (Adapter->link_state != LINK_STATE_DOWN) { 3513 Adapter->link_speed = 0; 3514 Adapter->link_duplex = 0; 3515 Adapter->link_state = LINK_STATE_DOWN; 3516 link_changed = B_TRUE; 3517 3518 /* 3519 * SmartSpeed workaround for Tabor/TanaX, When the 3520 * driver loses link disable auto master/slave 3521 * resolution. 3522 */ 3523 if (hw->phy.type == e1000_phy_igp) { 3524 e1000_read_phy_reg(hw, 3525 PHY_1000T_CTRL, &phydata); 3526 phydata |= CR_1000T_MS_ENABLE; 3527 e1000_write_phy_reg(hw, 3528 PHY_1000T_CTRL, phydata); 3529 } 3530 } else { 3531 e1000g_smartspeed(Adapter); 3532 } 3533 3534 if (Adapter->chip_state == E1000G_START) { 3535 if (Adapter->tx_link_down_timeout < 3536 MAX_TX_LINK_DOWN_TIMEOUT) { 3537 Adapter->tx_link_down_timeout++; 3538 } else if (Adapter->tx_link_down_timeout == 3539 MAX_TX_LINK_DOWN_TIMEOUT) { 3540 e1000g_tx_clean(Adapter); 3541 Adapter->tx_link_down_timeout++; 3542 } 3543 } 3544 } 3545 3546 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3547 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3548 3549 return (link_changed); 3550 } 3551 3552 /* 3553 * e1000g_reset_link - Using the link properties to setup the link 3554 */ 3555 int 3556 e1000g_reset_link(struct e1000g *Adapter) 3557 { 3558 struct e1000_mac_info *mac; 3559 struct e1000_phy_info *phy; 3560 boolean_t invalid; 3561 3562 mac = &Adapter->shared.mac; 3563 phy = &Adapter->shared.phy; 3564 invalid = B_FALSE; 3565 3566 if (Adapter->param_adv_autoneg == 1) { 3567 mac->autoneg = B_TRUE; 3568 phy->autoneg_advertised = 0; 3569 3570 /* 3571 * 1000hdx is not supported for autonegotiation 3572 */ 3573 if (Adapter->param_adv_1000fdx == 1) 3574 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3575 3576 if (Adapter->param_adv_100fdx == 1) 3577 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3578 3579 if (Adapter->param_adv_100hdx == 1) 3580 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3581 3582 if (Adapter->param_adv_10fdx == 1) 3583 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3584 3585 if (Adapter->param_adv_10hdx == 1) 3586 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3587 3588 if (phy->autoneg_advertised == 0) 3589 invalid = B_TRUE; 3590 } else { 3591 mac->autoneg = B_FALSE; 3592 3593 /* 3594 * 1000fdx and 1000hdx are not supported for forced link 3595 */ 3596 if (Adapter->param_adv_100fdx == 1) 3597 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3598 else if (Adapter->param_adv_100hdx == 1) 3599 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3600 else if (Adapter->param_adv_10fdx == 1) 3601 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3602 else if (Adapter->param_adv_10hdx == 1) 3603 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3604 else 3605 invalid = B_TRUE; 3606 3607 } 3608 3609 if (invalid) { 3610 e1000g_log(Adapter, CE_WARN, 3611 "Invalid link sets. Setup link to" 3612 "support autonegotiation with all link capabilities."); 3613 mac->autoneg = B_TRUE; 3614 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3615 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3616 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3617 } 3618 3619 return (e1000_setup_link(&Adapter->shared)); 3620 } 3621 3622 static void 3623 e1000g_local_timer(void *ws) 3624 { 3625 struct e1000g *Adapter = (struct e1000g *)ws; 3626 struct e1000_hw *hw; 3627 e1000g_ether_addr_t ether_addr; 3628 boolean_t link_changed; 3629 3630 hw = &Adapter->shared; 3631 3632 if (Adapter->chip_state == E1000G_ERROR) { 3633 Adapter->reset_count++; 3634 if (e1000g_global_reset(Adapter)) 3635 ddi_fm_service_impact(Adapter->dip, 3636 DDI_SERVICE_RESTORED); 3637 else 3638 ddi_fm_service_impact(Adapter->dip, 3639 DDI_SERVICE_LOST); 3640 return; 3641 } 3642 3643 if (e1000g_stall_check(Adapter)) { 3644 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3645 "Tx stall detected. Activate automatic recovery.\n"); 3646 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3647 Adapter->reset_count++; 3648 if (e1000g_reset(Adapter)) 3649 ddi_fm_service_impact(Adapter->dip, 3650 DDI_SERVICE_RESTORED); 3651 else 3652 ddi_fm_service_impact(Adapter->dip, 3653 DDI_SERVICE_LOST); 3654 return; 3655 } 3656 3657 link_changed = B_FALSE; 3658 rw_enter(&Adapter->chip_lock, RW_READER); 3659 if (Adapter->link_complete) 3660 link_changed = e1000g_link_check(Adapter); 3661 rw_exit(&Adapter->chip_lock); 3662 3663 if (link_changed) 3664 mac_link_update(Adapter->mh, Adapter->link_state); 3665 3666 /* 3667 * Workaround for esb2. Data stuck in fifo on a link 3668 * down event. Reset the adapter to recover it. 3669 */ 3670 if (Adapter->esb2_workaround) { 3671 Adapter->esb2_workaround = B_FALSE; 3672 (void) e1000g_reset(Adapter); 3673 } 3674 3675 /* 3676 * With 82571 controllers, any locally administered address will 3677 * be overwritten when there is a reset on the other port. 3678 * Detect this circumstance and correct it. 3679 */ 3680 if ((hw->mac.type == e1000_82571) && 3681 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3682 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3683 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3684 3685 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3686 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3687 3688 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3689 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3690 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3691 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3692 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3693 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3694 e1000_rar_set(hw, hw->mac.addr, 0); 3695 } 3696 } 3697 3698 /* 3699 * Long TTL workaround for 82541/82547 3700 */ 3701 e1000_igp_ttl_workaround_82547(hw); 3702 3703 /* 3704 * Check for Adaptive IFS settings If there are lots of collisions 3705 * change the value in steps... 3706 * These properties should only be set for 10/100 3707 */ 3708 if ((hw->phy.media_type == e1000_media_type_copper) && 3709 ((Adapter->link_speed == SPEED_100) || 3710 (Adapter->link_speed == SPEED_10))) { 3711 e1000_update_adaptive(hw); 3712 } 3713 /* 3714 * Set Timer Interrupts 3715 */ 3716 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3717 3718 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3719 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3720 3721 restart_watchdog_timer(Adapter); 3722 } 3723 3724 /* 3725 * The function e1000g_link_timer() is called when the timer for link setup 3726 * is expired, which indicates the completion of the link setup. The link 3727 * state will not be updated until the link setup is completed. And the 3728 * link state will not be sent to the upper layer through mac_link_update() 3729 * in this function. It will be updated in the local timer routine or the 3730 * interrupt service routine after the interface is started (plumbed). 3731 */ 3732 static void 3733 e1000g_link_timer(void *arg) 3734 { 3735 struct e1000g *Adapter = (struct e1000g *)arg; 3736 3737 mutex_enter(&Adapter->link_lock); 3738 Adapter->link_complete = B_TRUE; 3739 Adapter->link_tid = 0; 3740 mutex_exit(&Adapter->link_lock); 3741 } 3742 3743 /* 3744 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3745 * 3746 * This function read the forced speed and duplex for 10/100 Mbps speeds 3747 * and also for 1000 Mbps speeds from the e1000g.conf file 3748 */ 3749 static void 3750 e1000g_force_speed_duplex(struct e1000g *Adapter) 3751 { 3752 int forced; 3753 struct e1000_mac_info *mac = &Adapter->shared.mac; 3754 struct e1000_phy_info *phy = &Adapter->shared.phy; 3755 3756 /* 3757 * get value out of config file 3758 */ 3759 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3760 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3761 3762 switch (forced) { 3763 case GDIAG_10_HALF: 3764 /* 3765 * Disable Auto Negotiation 3766 */ 3767 mac->autoneg = B_FALSE; 3768 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3769 break; 3770 case GDIAG_10_FULL: 3771 /* 3772 * Disable Auto Negotiation 3773 */ 3774 mac->autoneg = B_FALSE; 3775 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3776 break; 3777 case GDIAG_100_HALF: 3778 /* 3779 * Disable Auto Negotiation 3780 */ 3781 mac->autoneg = B_FALSE; 3782 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3783 break; 3784 case GDIAG_100_FULL: 3785 /* 3786 * Disable Auto Negotiation 3787 */ 3788 mac->autoneg = B_FALSE; 3789 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3790 break; 3791 case GDIAG_1000_FULL: 3792 /* 3793 * The gigabit spec requires autonegotiation. Therefore, 3794 * when the user wants to force the speed to 1000Mbps, we 3795 * enable AutoNeg, but only allow the harware to advertise 3796 * 1000Mbps. This is different from 10/100 operation, where 3797 * we are allowed to link without any negotiation. 3798 */ 3799 mac->autoneg = B_TRUE; 3800 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3801 break; 3802 default: /* obey the setting of AutoNegAdvertised */ 3803 mac->autoneg = B_TRUE; 3804 phy->autoneg_advertised = 3805 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3806 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3807 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3808 break; 3809 } /* switch */ 3810 } 3811 3812 /* 3813 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3814 * 3815 * This function reads MaxFrameSize from e1000g.conf 3816 */ 3817 static void 3818 e1000g_get_max_frame_size(struct e1000g *Adapter) 3819 { 3820 int max_frame; 3821 struct e1000_mac_info *mac = &Adapter->shared.mac; 3822 struct e1000_phy_info *phy = &Adapter->shared.phy; 3823 3824 /* 3825 * get value out of config file 3826 */ 3827 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3828 3829 switch (max_frame) { 3830 case 0: 3831 Adapter->default_mtu = ETHERMTU; 3832 break; 3833 /* 3834 * To avoid excessive memory allocation for rx buffers, 3835 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3836 */ 3837 case 1: 3838 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3839 sizeof (struct ether_vlan_header) - ETHERFCSL - 3840 E1000G_IPALIGNPRESERVEROOM; 3841 break; 3842 case 2: 3843 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3844 sizeof (struct ether_vlan_header) - ETHERFCSL - 3845 E1000G_IPALIGNPRESERVEROOM; 3846 break; 3847 case 3: 3848 if (mac->type >= e1000_82571) 3849 Adapter->default_mtu = MAXIMUM_MTU; 3850 else 3851 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3852 sizeof (struct ether_vlan_header) - ETHERFCSL - 3853 E1000G_IPALIGNPRESERVEROOM; 3854 break; 3855 default: 3856 Adapter->default_mtu = ETHERMTU; 3857 break; 3858 } /* switch */ 3859 3860 Adapter->max_frame_size = Adapter->default_mtu + 3861 sizeof (struct ether_vlan_header) + ETHERFCSL; 3862 3863 /* ich8 does not do jumbo frames */ 3864 if (mac->type == e1000_ich8lan) { 3865 Adapter->max_frame_size = ETHERMTU + 3866 sizeof (struct ether_vlan_header) + ETHERFCSL; 3867 } 3868 3869 /* ich9 does not do jumbo frames on one phy type */ 3870 if ((mac->type == e1000_ich9lan) && 3871 (phy->type == e1000_phy_ife)) { 3872 Adapter->max_frame_size = ETHERMTU + 3873 sizeof (struct ether_vlan_header) + ETHERFCSL; 3874 } 3875 } 3876 3877 static void 3878 arm_watchdog_timer(struct e1000g *Adapter) 3879 { 3880 Adapter->watchdog_tid = 3881 timeout(e1000g_local_timer, 3882 (void *)Adapter, 1 * drv_usectohz(1000000)); 3883 } 3884 #pragma inline(arm_watchdog_timer) 3885 3886 static void 3887 enable_watchdog_timer(struct e1000g *Adapter) 3888 { 3889 mutex_enter(&Adapter->watchdog_lock); 3890 3891 if (!Adapter->watchdog_timer_enabled) { 3892 Adapter->watchdog_timer_enabled = B_TRUE; 3893 Adapter->watchdog_timer_started = B_TRUE; 3894 arm_watchdog_timer(Adapter); 3895 } 3896 3897 mutex_exit(&Adapter->watchdog_lock); 3898 } 3899 3900 static void 3901 disable_watchdog_timer(struct e1000g *Adapter) 3902 { 3903 timeout_id_t tid; 3904 3905 mutex_enter(&Adapter->watchdog_lock); 3906 3907 Adapter->watchdog_timer_enabled = B_FALSE; 3908 Adapter->watchdog_timer_started = B_FALSE; 3909 tid = Adapter->watchdog_tid; 3910 Adapter->watchdog_tid = 0; 3911 3912 mutex_exit(&Adapter->watchdog_lock); 3913 3914 if (tid != 0) 3915 (void) untimeout(tid); 3916 } 3917 3918 static void 3919 start_watchdog_timer(struct e1000g *Adapter) 3920 { 3921 mutex_enter(&Adapter->watchdog_lock); 3922 3923 if (Adapter->watchdog_timer_enabled) { 3924 if (!Adapter->watchdog_timer_started) { 3925 Adapter->watchdog_timer_started = B_TRUE; 3926 arm_watchdog_timer(Adapter); 3927 } 3928 } 3929 3930 mutex_exit(&Adapter->watchdog_lock); 3931 } 3932 3933 static void 3934 restart_watchdog_timer(struct e1000g *Adapter) 3935 { 3936 mutex_enter(&Adapter->watchdog_lock); 3937 3938 if (Adapter->watchdog_timer_started) 3939 arm_watchdog_timer(Adapter); 3940 3941 mutex_exit(&Adapter->watchdog_lock); 3942 } 3943 3944 static void 3945 stop_watchdog_timer(struct e1000g *Adapter) 3946 { 3947 timeout_id_t tid; 3948 3949 mutex_enter(&Adapter->watchdog_lock); 3950 3951 Adapter->watchdog_timer_started = B_FALSE; 3952 tid = Adapter->watchdog_tid; 3953 Adapter->watchdog_tid = 0; 3954 3955 mutex_exit(&Adapter->watchdog_lock); 3956 3957 if (tid != 0) 3958 (void) untimeout(tid); 3959 } 3960 3961 static void 3962 stop_link_timer(struct e1000g *Adapter) 3963 { 3964 timeout_id_t tid; 3965 3966 /* Disable the link timer */ 3967 mutex_enter(&Adapter->link_lock); 3968 3969 tid = Adapter->link_tid; 3970 Adapter->link_tid = 0; 3971 3972 mutex_exit(&Adapter->link_lock); 3973 3974 if (tid != 0) 3975 (void) untimeout(tid); 3976 } 3977 3978 static void 3979 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3980 { 3981 timeout_id_t tid; 3982 3983 /* Disable the tx timer for 82547 chipset */ 3984 mutex_enter(&tx_ring->tx_lock); 3985 3986 tx_ring->timer_enable_82547 = B_FALSE; 3987 tid = tx_ring->timer_id_82547; 3988 tx_ring->timer_id_82547 = 0; 3989 3990 mutex_exit(&tx_ring->tx_lock); 3991 3992 if (tid != 0) 3993 (void) untimeout(tid); 3994 } 3995 3996 void 3997 e1000g_clear_interrupt(struct e1000g *Adapter) 3998 { 3999 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4000 0xffffffff & ~E1000_IMS_RXSEQ); 4001 } 4002 4003 void 4004 e1000g_mask_interrupt(struct e1000g *Adapter) 4005 { 4006 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4007 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4008 4009 if (Adapter->tx_intr_enable) 4010 e1000g_mask_tx_interrupt(Adapter); 4011 } 4012 4013 void 4014 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4015 { 4016 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4017 } 4018 4019 void 4020 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4021 { 4022 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4023 } 4024 4025 void 4026 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4027 { 4028 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4029 } 4030 4031 static void 4032 e1000g_smartspeed(struct e1000g *Adapter) 4033 { 4034 struct e1000_hw *hw = &Adapter->shared; 4035 uint16_t phy_status; 4036 uint16_t phy_ctrl; 4037 4038 /* 4039 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4040 * advertising 1000Full, we don't even use the workaround 4041 */ 4042 if ((hw->phy.type != e1000_phy_igp) || 4043 !hw->mac.autoneg || 4044 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4045 return; 4046 4047 /* 4048 * True if this is the first call of this function or after every 4049 * 30 seconds of not having link 4050 */ 4051 if (Adapter->smartspeed == 0) { 4052 /* 4053 * If Master/Slave config fault is asserted twice, we 4054 * assume back-to-back 4055 */ 4056 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4057 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4058 return; 4059 4060 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4061 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4062 return; 4063 /* 4064 * We're assuming back-2-back because our status register 4065 * insists! there's a fault in the master/slave 4066 * relationship that was "negotiated" 4067 */ 4068 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4069 /* 4070 * Is the phy configured for manual configuration of 4071 * master/slave? 4072 */ 4073 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4074 /* 4075 * Yes. Then disable manual configuration (enable 4076 * auto configuration) of master/slave 4077 */ 4078 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4079 e1000_write_phy_reg(hw, 4080 PHY_1000T_CTRL, phy_ctrl); 4081 /* 4082 * Effectively starting the clock 4083 */ 4084 Adapter->smartspeed++; 4085 /* 4086 * Restart autonegotiation 4087 */ 4088 if (!e1000_phy_setup_autoneg(hw) && 4089 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4090 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4091 MII_CR_RESTART_AUTO_NEG); 4092 e1000_write_phy_reg(hw, 4093 PHY_CONTROL, phy_ctrl); 4094 } 4095 } 4096 return; 4097 /* 4098 * Has 6 seconds transpired still without link? Remember, 4099 * you should reset the smartspeed counter once you obtain 4100 * link 4101 */ 4102 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4103 /* 4104 * Yes. Remember, we did at the start determine that 4105 * there's a master/slave configuration fault, so we're 4106 * still assuming there's someone on the other end, but we 4107 * just haven't yet been able to talk to it. We then 4108 * re-enable auto configuration of master/slave to see if 4109 * we're running 2/3 pair cables. 4110 */ 4111 /* 4112 * If still no link, perhaps using 2/3 pair cable 4113 */ 4114 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4115 phy_ctrl |= CR_1000T_MS_ENABLE; 4116 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4117 /* 4118 * Restart autoneg with phy enabled for manual 4119 * configuration of master/slave 4120 */ 4121 if (!e1000_phy_setup_autoneg(hw) && 4122 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4123 phy_ctrl |= 4124 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4125 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4126 } 4127 /* 4128 * Hopefully, there are no more faults and we've obtained 4129 * link as a result. 4130 */ 4131 } 4132 /* 4133 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4134 * seconds) 4135 */ 4136 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4137 Adapter->smartspeed = 0; 4138 } 4139 4140 static boolean_t 4141 is_valid_mac_addr(uint8_t *mac_addr) 4142 { 4143 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4144 const uint8_t addr_test2[6] = 4145 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4146 4147 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4148 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4149 return (B_FALSE); 4150 4151 return (B_TRUE); 4152 } 4153 4154 /* 4155 * e1000g_stall_check - check for tx stall 4156 * 4157 * This function checks if the adapter is stalled (in transmit). 4158 * 4159 * It is called each time the watchdog timeout is invoked. 4160 * If the transmit descriptor reclaim continuously fails, 4161 * the watchdog value will increment by 1. If the watchdog 4162 * value exceeds the threshold, the adapter is assumed to 4163 * have stalled and need to be reset. 4164 */ 4165 static boolean_t 4166 e1000g_stall_check(struct e1000g *Adapter) 4167 { 4168 e1000g_tx_ring_t *tx_ring; 4169 4170 tx_ring = Adapter->tx_ring; 4171 4172 if (Adapter->link_state != LINK_STATE_UP) 4173 return (B_FALSE); 4174 4175 if (tx_ring->recycle_fail > 0) 4176 tx_ring->stall_watchdog++; 4177 else 4178 tx_ring->stall_watchdog = 0; 4179 4180 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4181 return (B_FALSE); 4182 4183 tx_ring->stall_watchdog = 0; 4184 tx_ring->recycle_fail = 0; 4185 4186 return (B_TRUE); 4187 } 4188 4189 #ifdef E1000G_DEBUG 4190 static enum ioc_reply 4191 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4192 { 4193 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4194 e1000g_peekpoke_t *ppd; 4195 uint64_t mem_va; 4196 uint64_t maxoff; 4197 boolean_t peek; 4198 4199 switch (iocp->ioc_cmd) { 4200 4201 case E1000G_IOC_REG_PEEK: 4202 peek = B_TRUE; 4203 break; 4204 4205 case E1000G_IOC_REG_POKE: 4206 peek = B_FALSE; 4207 break; 4208 4209 deault: 4210 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4211 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4212 iocp->ioc_cmd); 4213 return (IOC_INVAL); 4214 } 4215 4216 /* 4217 * Validate format of ioctl 4218 */ 4219 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4220 return (IOC_INVAL); 4221 if (mp->b_cont == NULL) 4222 return (IOC_INVAL); 4223 4224 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 4225 4226 /* 4227 * Validate request parameters 4228 */ 4229 switch (ppd->pp_acc_space) { 4230 4231 default: 4232 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4233 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4234 ppd->pp_acc_space); 4235 return (IOC_INVAL); 4236 4237 case E1000G_PP_SPACE_REG: 4238 /* 4239 * Memory-mapped I/O space 4240 */ 4241 ASSERT(ppd->pp_acc_size == 4); 4242 if (ppd->pp_acc_size != 4) 4243 return (IOC_INVAL); 4244 4245 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4246 return (IOC_INVAL); 4247 4248 mem_va = 0; 4249 maxoff = 0x10000; 4250 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4251 break; 4252 4253 case E1000G_PP_SPACE_E1000G: 4254 /* 4255 * E1000g data structure! 4256 */ 4257 mem_va = (uintptr_t)e1000gp; 4258 maxoff = sizeof (struct e1000g); 4259 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4260 break; 4261 4262 } 4263 4264 if (ppd->pp_acc_offset >= maxoff) 4265 return (IOC_INVAL); 4266 4267 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4268 return (IOC_INVAL); 4269 4270 /* 4271 * All OK - go! 4272 */ 4273 ppd->pp_acc_offset += mem_va; 4274 (*ppfn)(e1000gp, ppd); 4275 return (peek ? IOC_REPLY : IOC_ACK); 4276 } 4277 4278 static void 4279 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4280 { 4281 ddi_acc_handle_t handle; 4282 uint32_t *regaddr; 4283 4284 handle = e1000gp->osdep.reg_handle; 4285 regaddr = 4286 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4287 4288 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4289 } 4290 4291 static void 4292 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4293 { 4294 ddi_acc_handle_t handle; 4295 uint32_t *regaddr; 4296 uint32_t value; 4297 4298 handle = e1000gp->osdep.reg_handle; 4299 regaddr = 4300 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4301 value = (uint32_t)ppd->pp_acc_data; 4302 4303 ddi_put32(handle, regaddr, value); 4304 } 4305 4306 static void 4307 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4308 { 4309 uint64_t value; 4310 void *vaddr; 4311 4312 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4313 4314 switch (ppd->pp_acc_size) { 4315 case 1: 4316 value = *(uint8_t *)vaddr; 4317 break; 4318 4319 case 2: 4320 value = *(uint16_t *)vaddr; 4321 break; 4322 4323 case 4: 4324 value = *(uint32_t *)vaddr; 4325 break; 4326 4327 case 8: 4328 value = *(uint64_t *)vaddr; 4329 break; 4330 } 4331 4332 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4333 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4334 (void *)e1000gp, (void *)ppd, value, vaddr); 4335 4336 ppd->pp_acc_data = value; 4337 } 4338 4339 static void 4340 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4341 { 4342 uint64_t value; 4343 void *vaddr; 4344 4345 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4346 value = ppd->pp_acc_data; 4347 4348 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4349 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4350 (void *)e1000gp, (void *)ppd, value, vaddr); 4351 4352 switch (ppd->pp_acc_size) { 4353 case 1: 4354 *(uint8_t *)vaddr = (uint8_t)value; 4355 break; 4356 4357 case 2: 4358 *(uint16_t *)vaddr = (uint16_t)value; 4359 break; 4360 4361 case 4: 4362 *(uint32_t *)vaddr = (uint32_t)value; 4363 break; 4364 4365 case 8: 4366 *(uint64_t *)vaddr = (uint64_t)value; 4367 break; 4368 } 4369 } 4370 #endif 4371 4372 /* 4373 * Loopback Support 4374 */ 4375 static lb_property_t lb_normal = 4376 { normal, "normal", E1000G_LB_NONE }; 4377 static lb_property_t lb_external1000 = 4378 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4379 static lb_property_t lb_external100 = 4380 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4381 static lb_property_t lb_external10 = 4382 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4383 static lb_property_t lb_phy = 4384 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4385 4386 static enum ioc_reply 4387 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4388 { 4389 lb_info_sz_t *lbsp; 4390 lb_property_t *lbpp; 4391 struct e1000_hw *hw; 4392 uint32_t *lbmp; 4393 uint32_t size; 4394 uint32_t value; 4395 4396 hw = &Adapter->shared; 4397 4398 if (mp->b_cont == NULL) 4399 return (IOC_INVAL); 4400 4401 if (!e1000g_check_loopback_support(hw)) { 4402 e1000g_log(NULL, CE_WARN, 4403 "Loopback is not supported on e1000g%d", Adapter->instance); 4404 return (IOC_INVAL); 4405 } 4406 4407 switch (iocp->ioc_cmd) { 4408 default: 4409 return (IOC_INVAL); 4410 4411 case LB_GET_INFO_SIZE: 4412 size = sizeof (lb_info_sz_t); 4413 if (iocp->ioc_count != size) 4414 return (IOC_INVAL); 4415 4416 rw_enter(&Adapter->chip_lock, RW_WRITER); 4417 e1000g_get_phy_state(Adapter); 4418 4419 /* 4420 * Workaround for hardware faults. In order to get a stable 4421 * state of phy, we will wait for a specific interval and 4422 * try again. The time delay is an experiential value based 4423 * on our testing. 4424 */ 4425 msec_delay(100); 4426 e1000g_get_phy_state(Adapter); 4427 rw_exit(&Adapter->chip_lock); 4428 4429 value = sizeof (lb_normal); 4430 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4431 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4432 (hw->phy.media_type == e1000_media_type_fiber) || 4433 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4434 value += sizeof (lb_phy); 4435 switch (hw->mac.type) { 4436 case e1000_82571: 4437 case e1000_82572: 4438 case e1000_80003es2lan: 4439 value += sizeof (lb_external1000); 4440 break; 4441 } 4442 } 4443 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4444 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4445 value += sizeof (lb_external100); 4446 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4447 value += sizeof (lb_external10); 4448 4449 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 4450 *lbsp = value; 4451 break; 4452 4453 case LB_GET_INFO: 4454 value = sizeof (lb_normal); 4455 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4456 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4457 (hw->phy.media_type == e1000_media_type_fiber) || 4458 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4459 value += sizeof (lb_phy); 4460 switch (hw->mac.type) { 4461 case e1000_82571: 4462 case e1000_82572: 4463 case e1000_80003es2lan: 4464 value += sizeof (lb_external1000); 4465 break; 4466 } 4467 } 4468 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4469 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4470 value += sizeof (lb_external100); 4471 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4472 value += sizeof (lb_external10); 4473 4474 size = value; 4475 if (iocp->ioc_count != size) 4476 return (IOC_INVAL); 4477 4478 value = 0; 4479 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 4480 lbpp[value++] = lb_normal; 4481 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4482 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4483 (hw->phy.media_type == e1000_media_type_fiber) || 4484 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4485 lbpp[value++] = lb_phy; 4486 switch (hw->mac.type) { 4487 case e1000_82571: 4488 case e1000_82572: 4489 case e1000_80003es2lan: 4490 lbpp[value++] = lb_external1000; 4491 break; 4492 } 4493 } 4494 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4495 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4496 lbpp[value++] = lb_external100; 4497 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4498 lbpp[value++] = lb_external10; 4499 break; 4500 4501 case LB_GET_MODE: 4502 size = sizeof (uint32_t); 4503 if (iocp->ioc_count != size) 4504 return (IOC_INVAL); 4505 4506 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4507 *lbmp = Adapter->loopback_mode; 4508 break; 4509 4510 case LB_SET_MODE: 4511 size = 0; 4512 if (iocp->ioc_count != sizeof (uint32_t)) 4513 return (IOC_INVAL); 4514 4515 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4516 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4517 return (IOC_INVAL); 4518 break; 4519 } 4520 4521 iocp->ioc_count = size; 4522 iocp->ioc_error = 0; 4523 4524 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4525 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4526 return (IOC_INVAL); 4527 } 4528 4529 return (IOC_REPLY); 4530 } 4531 4532 static boolean_t 4533 e1000g_check_loopback_support(struct e1000_hw *hw) 4534 { 4535 switch (hw->mac.type) { 4536 case e1000_82540: 4537 case e1000_82545: 4538 case e1000_82545_rev_3: 4539 case e1000_82546: 4540 case e1000_82546_rev_3: 4541 case e1000_82541: 4542 case e1000_82541_rev_2: 4543 case e1000_82547: 4544 case e1000_82547_rev_2: 4545 case e1000_82571: 4546 case e1000_82572: 4547 case e1000_82573: 4548 case e1000_80003es2lan: 4549 return (B_TRUE); 4550 } 4551 return (B_FALSE); 4552 } 4553 4554 static boolean_t 4555 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4556 { 4557 struct e1000_hw *hw; 4558 int i, times; 4559 boolean_t link_up; 4560 4561 if (mode == Adapter->loopback_mode) 4562 return (B_TRUE); 4563 4564 hw = &Adapter->shared; 4565 times = 0; 4566 4567 Adapter->loopback_mode = mode; 4568 4569 if (mode == E1000G_LB_NONE) { 4570 /* Reset the chip */ 4571 hw->phy.autoneg_wait_to_complete = B_TRUE; 4572 (void) e1000g_reset(Adapter); 4573 hw->phy.autoneg_wait_to_complete = B_FALSE; 4574 return (B_TRUE); 4575 } 4576 4577 again: 4578 4579 rw_enter(&Adapter->chip_lock, RW_WRITER); 4580 4581 switch (mode) { 4582 default: 4583 rw_exit(&Adapter->chip_lock); 4584 return (B_FALSE); 4585 4586 case E1000G_LB_EXTERNAL_1000: 4587 e1000g_set_external_loopback_1000(Adapter); 4588 break; 4589 4590 case E1000G_LB_EXTERNAL_100: 4591 e1000g_set_external_loopback_100(Adapter); 4592 break; 4593 4594 case E1000G_LB_EXTERNAL_10: 4595 e1000g_set_external_loopback_10(Adapter); 4596 break; 4597 4598 case E1000G_LB_INTERNAL_PHY: 4599 e1000g_set_internal_loopback(Adapter); 4600 break; 4601 } 4602 4603 times++; 4604 4605 rw_exit(&Adapter->chip_lock); 4606 4607 /* Wait for link up */ 4608 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4609 msec_delay(100); 4610 4611 rw_enter(&Adapter->chip_lock, RW_WRITER); 4612 4613 link_up = e1000g_link_up(Adapter); 4614 4615 rw_exit(&Adapter->chip_lock); 4616 4617 if (!link_up) { 4618 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4619 "Failed to get the link up"); 4620 if (times < 2) { 4621 /* Reset the link */ 4622 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4623 "Reset the link ..."); 4624 (void) e1000g_reset(Adapter); 4625 goto again; 4626 } 4627 } 4628 4629 return (B_TRUE); 4630 } 4631 4632 /* 4633 * The following loopback settings are from Intel's technical 4634 * document - "How To Loopback". All the register settings and 4635 * time delay values are directly inherited from the document 4636 * without more explanations available. 4637 */ 4638 static void 4639 e1000g_set_internal_loopback(struct e1000g *Adapter) 4640 { 4641 struct e1000_hw *hw; 4642 uint32_t ctrl; 4643 uint32_t status; 4644 uint16_t phy_ctrl; 4645 uint32_t txcw; 4646 4647 hw = &Adapter->shared; 4648 4649 /* Disable Smart Power Down */ 4650 phy_spd_state(hw, B_FALSE); 4651 4652 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4653 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4654 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4655 4656 switch (hw->mac.type) { 4657 case e1000_82540: 4658 case e1000_82545: 4659 case e1000_82545_rev_3: 4660 case e1000_82546: 4661 case e1000_82546_rev_3: 4662 case e1000_82573: 4663 /* Auto-MDI/MDIX off */ 4664 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4665 /* Reset PHY to update Auto-MDI/MDIX */ 4666 e1000_write_phy_reg(hw, PHY_CONTROL, 4667 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4668 /* Reset PHY to auto-neg off and force 1000 */ 4669 e1000_write_phy_reg(hw, PHY_CONTROL, 4670 phy_ctrl | MII_CR_RESET); 4671 /* 4672 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4673 * See comments above e1000g_set_internal_loopback() for the 4674 * background. 4675 */ 4676 e1000_write_phy_reg(hw, 29, 0x001F); 4677 e1000_write_phy_reg(hw, 30, 0x8FFC); 4678 e1000_write_phy_reg(hw, 29, 0x001A); 4679 e1000_write_phy_reg(hw, 30, 0x8FF0); 4680 break; 4681 case e1000_80003es2lan: 4682 /* Force Link Up */ 4683 e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC); 4684 /* Sets PCS loopback at 1Gbs */ 4685 e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 0x1046); 4686 break; 4687 } 4688 4689 /* Set loopback */ 4690 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4691 4692 msec_delay(250); 4693 4694 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4695 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4696 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4697 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4698 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4699 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4700 E1000_CTRL_FD); /* Force Duplex to FULL */ 4701 4702 switch (hw->mac.type) { 4703 case e1000_82540: 4704 case e1000_82545: 4705 case e1000_82545_rev_3: 4706 case e1000_82546: 4707 case e1000_82546_rev_3: 4708 /* 4709 * For some serdes we'll need to commit the writes now 4710 * so that the status is updated on link 4711 */ 4712 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4713 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4714 msec_delay(100); 4715 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4716 } 4717 4718 if (hw->phy.media_type == e1000_media_type_copper) { 4719 /* Invert Loss of Signal */ 4720 ctrl |= E1000_CTRL_ILOS; 4721 } else { 4722 /* Set ILOS on fiber nic if half duplex is detected */ 4723 status = E1000_READ_REG(hw, E1000_STATUS); 4724 if ((status & E1000_STATUS_FD) == 0) 4725 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4726 } 4727 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4728 break; 4729 4730 case e1000_82571: 4731 case e1000_82572: 4732 /* 4733 * The fiber/SerDes versions of this adapter do not contain an 4734 * accessible PHY. Therefore, loopback beyond MAC must be done 4735 * using SerDes analog loopback. 4736 */ 4737 if (hw->phy.media_type != e1000_media_type_copper) { 4738 status = E1000_READ_REG(hw, E1000_STATUS); 4739 /* Set ILOS on fiber nic if half duplex is detected */ 4740 if (((status & E1000_STATUS_LU) == 0) || 4741 ((status & E1000_STATUS_FD) == 0) || 4742 (hw->phy.media_type == 4743 e1000_media_type_internal_serdes)) 4744 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4745 4746 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4747 txcw = E1000_READ_REG(hw, E1000_TXCW); 4748 txcw &= ~((uint32_t)1 << 31); 4749 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4750 4751 /* 4752 * Write 0x410 to Serdes Control register 4753 * to enable Serdes analog loopback 4754 */ 4755 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4756 msec_delay(10); 4757 } 4758 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4759 break; 4760 4761 case e1000_82573: 4762 ctrl |= E1000_CTRL_ILOS; 4763 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4764 break; 4765 } 4766 } 4767 4768 static void 4769 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4770 { 4771 struct e1000_hw *hw; 4772 uint32_t rctl; 4773 uint32_t ctrl_ext; 4774 uint32_t ctrl; 4775 uint32_t status; 4776 uint32_t txcw; 4777 uint16_t phydata; 4778 4779 hw = &Adapter->shared; 4780 4781 /* Disable Smart Power Down */ 4782 phy_spd_state(hw, B_FALSE); 4783 4784 switch (hw->mac.type) { 4785 case e1000_82571: 4786 case e1000_82572: 4787 switch (hw->phy.media_type) { 4788 case e1000_media_type_copper: 4789 /* Force link up (Must be done before the PHY writes) */ 4790 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4791 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4792 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4793 4794 rctl = E1000_READ_REG(hw, E1000_RCTL); 4795 rctl |= (E1000_RCTL_EN | 4796 E1000_RCTL_SBP | 4797 E1000_RCTL_UPE | 4798 E1000_RCTL_MPE | 4799 E1000_RCTL_LPE | 4800 E1000_RCTL_BAM); /* 0x803E */ 4801 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4802 4803 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4804 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4805 E1000_CTRL_EXT_SDP6_DATA | 4806 E1000_CTRL_EXT_SDP7_DATA | 4807 E1000_CTRL_EXT_SDP4_DIR | 4808 E1000_CTRL_EXT_SDP6_DIR | 4809 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4810 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4811 4812 /* 4813 * This sequence tunes the PHY's SDP and no customer 4814 * settable values. For background, see comments above 4815 * e1000g_set_internal_loopback(). 4816 */ 4817 e1000_write_phy_reg(hw, 0x0, 0x140); 4818 msec_delay(10); 4819 e1000_write_phy_reg(hw, 0x9, 0x1A00); 4820 e1000_write_phy_reg(hw, 0x12, 0xC10); 4821 e1000_write_phy_reg(hw, 0x12, 0x1C10); 4822 e1000_write_phy_reg(hw, 0x1F37, 0x76); 4823 e1000_write_phy_reg(hw, 0x1F33, 0x1); 4824 e1000_write_phy_reg(hw, 0x1F33, 0x0); 4825 4826 e1000_write_phy_reg(hw, 0x1F35, 0x65); 4827 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4828 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4829 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4830 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4831 4832 msec_delay(50); 4833 break; 4834 case e1000_media_type_fiber: 4835 case e1000_media_type_internal_serdes: 4836 status = E1000_READ_REG(hw, E1000_STATUS); 4837 if (((status & E1000_STATUS_LU) == 0) || 4838 (hw->phy.media_type == 4839 e1000_media_type_internal_serdes)) { 4840 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4841 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4842 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4843 } 4844 4845 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4846 txcw = E1000_READ_REG(hw, E1000_TXCW); 4847 txcw &= ~((uint32_t)1 << 31); 4848 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4849 4850 /* 4851 * Write 0x410 to Serdes Control register 4852 * to enable Serdes analog loopback 4853 */ 4854 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4855 msec_delay(10); 4856 break; 4857 default: 4858 break; 4859 } 4860 break; 4861 case e1000_80003es2lan: 4862 e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 4863 e1000_write_phy_reg(hw, GG82563_REG(6, 16), phydata | (1 << 5)); 4864 Adapter->param_adv_autoneg = 1; 4865 Adapter->param_adv_1000fdx = 1; 4866 e1000g_reset_link(Adapter); 4867 break; 4868 } 4869 } 4870 4871 static void 4872 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4873 { 4874 struct e1000_hw *hw; 4875 uint32_t ctrl; 4876 uint16_t phy_ctrl; 4877 4878 hw = &Adapter->shared; 4879 4880 /* Disable Smart Power Down */ 4881 phy_spd_state(hw, B_FALSE); 4882 4883 phy_ctrl = (MII_CR_FULL_DUPLEX | 4884 MII_CR_SPEED_100); 4885 4886 /* Force 100/FD, reset PHY */ 4887 e1000_write_phy_reg(hw, PHY_CONTROL, 4888 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4889 msec_delay(10); 4890 4891 /* Force 100/FD */ 4892 e1000_write_phy_reg(hw, PHY_CONTROL, 4893 phy_ctrl); /* 0x2100 */ 4894 msec_delay(10); 4895 4896 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4897 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4898 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4899 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4900 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4901 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4902 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4903 E1000_CTRL_FD); /* Force Duplex to FULL */ 4904 4905 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4906 } 4907 4908 static void 4909 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4910 { 4911 struct e1000_hw *hw; 4912 uint32_t ctrl; 4913 uint16_t phy_ctrl; 4914 4915 hw = &Adapter->shared; 4916 4917 /* Disable Smart Power Down */ 4918 phy_spd_state(hw, B_FALSE); 4919 4920 phy_ctrl = (MII_CR_FULL_DUPLEX | 4921 MII_CR_SPEED_10); 4922 4923 /* Force 10/FD, reset PHY */ 4924 e1000_write_phy_reg(hw, PHY_CONTROL, 4925 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4926 msec_delay(10); 4927 4928 /* Force 10/FD */ 4929 e1000_write_phy_reg(hw, PHY_CONTROL, 4930 phy_ctrl); /* 0x0100 */ 4931 msec_delay(10); 4932 4933 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4934 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4935 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4936 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4937 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4938 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4939 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4940 E1000_CTRL_FD); /* Force Duplex to FULL */ 4941 4942 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4943 } 4944 4945 #ifdef __sparc 4946 static boolean_t 4947 e1000g_find_mac_address(struct e1000g *Adapter) 4948 { 4949 struct e1000_hw *hw = &Adapter->shared; 4950 uchar_t *bytes; 4951 struct ether_addr sysaddr; 4952 uint_t nelts; 4953 int err; 4954 boolean_t found = B_FALSE; 4955 4956 /* 4957 * The "vendor's factory-set address" may already have 4958 * been extracted from the chip, but if the property 4959 * "local-mac-address" is set we use that instead. 4960 * 4961 * We check whether it looks like an array of 6 4962 * bytes (which it should, if OBP set it). If we can't 4963 * make sense of it this way, we'll ignore it. 4964 */ 4965 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4966 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4967 if (err == DDI_PROP_SUCCESS) { 4968 if (nelts == ETHERADDRL) { 4969 while (nelts--) 4970 hw->mac.addr[nelts] = bytes[nelts]; 4971 found = B_TRUE; 4972 } 4973 ddi_prop_free(bytes); 4974 } 4975 4976 /* 4977 * Look up the OBP property "local-mac-address?". If the user has set 4978 * 'local-mac-address? = false', use "the system address" instead. 4979 */ 4980 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4981 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4982 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4983 if (localetheraddr(NULL, &sysaddr) != 0) { 4984 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4985 found = B_TRUE; 4986 } 4987 } 4988 ddi_prop_free(bytes); 4989 } 4990 4991 /* 4992 * Finally(!), if there's a valid "mac-address" property (created 4993 * if we netbooted from this interface), we must use this instead 4994 * of any of the above to ensure that the NFS/install server doesn't 4995 * get confused by the address changing as Solaris takes over! 4996 */ 4997 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4998 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 4999 if (err == DDI_PROP_SUCCESS) { 5000 if (nelts == ETHERADDRL) { 5001 while (nelts--) 5002 hw->mac.addr[nelts] = bytes[nelts]; 5003 found = B_TRUE; 5004 } 5005 ddi_prop_free(bytes); 5006 } 5007 5008 if (found) { 5009 bcopy(hw->mac.addr, hw->mac.perm_addr, 5010 ETHERADDRL); 5011 } 5012 5013 return (found); 5014 } 5015 #endif 5016 5017 static int 5018 e1000g_add_intrs(struct e1000g *Adapter) 5019 { 5020 dev_info_t *devinfo; 5021 int intr_types; 5022 int rc; 5023 5024 devinfo = Adapter->dip; 5025 5026 /* Get supported interrupt types */ 5027 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5028 5029 if (rc != DDI_SUCCESS) { 5030 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5031 "Get supported interrupt types failed: %d\n", rc); 5032 return (DDI_FAILURE); 5033 } 5034 5035 /* 5036 * Based on Intel Technical Advisory document (TA-160), there are some 5037 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5038 * that it supports MSI, but in fact has problems. 5039 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5040 * PCI/PCI-X NICs. 5041 */ 5042 if (Adapter->shared.mac.type < e1000_82571) 5043 Adapter->msi_enable = B_FALSE; 5044 5045 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5046 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5047 5048 if (rc != DDI_SUCCESS) { 5049 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5050 "Add MSI failed, trying Legacy interrupts\n"); 5051 } else { 5052 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5053 } 5054 } 5055 5056 if ((Adapter->intr_type == 0) && 5057 (intr_types & DDI_INTR_TYPE_FIXED)) { 5058 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5059 5060 if (rc != DDI_SUCCESS) { 5061 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5062 "Add Legacy interrupts failed\n"); 5063 return (DDI_FAILURE); 5064 } 5065 5066 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5067 } 5068 5069 if (Adapter->intr_type == 0) { 5070 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5071 "No interrupts registered\n"); 5072 return (DDI_FAILURE); 5073 } 5074 5075 return (DDI_SUCCESS); 5076 } 5077 5078 /* 5079 * e1000g_intr_add() handles MSI/Legacy interrupts 5080 */ 5081 static int 5082 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5083 { 5084 dev_info_t *devinfo; 5085 int count, avail, actual; 5086 int x, y, rc, inum = 0; 5087 int flag; 5088 ddi_intr_handler_t *intr_handler; 5089 5090 devinfo = Adapter->dip; 5091 5092 /* get number of interrupts */ 5093 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5094 if ((rc != DDI_SUCCESS) || (count == 0)) { 5095 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5096 "Get interrupt number failed. Return: %d, count: %d\n", 5097 rc, count); 5098 return (DDI_FAILURE); 5099 } 5100 5101 /* get number of available interrupts */ 5102 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5103 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5104 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5105 "Get interrupt available number failed. " 5106 "Return: %d, available: %d\n", rc, avail); 5107 return (DDI_FAILURE); 5108 } 5109 5110 if (avail < count) { 5111 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5112 "Interrupts count: %d, available: %d\n", 5113 count, avail); 5114 } 5115 5116 /* Allocate an array of interrupt handles */ 5117 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5118 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5119 5120 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5121 flag = DDI_INTR_ALLOC_NORMAL; 5122 5123 /* call ddi_intr_alloc() */ 5124 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5125 count, &actual, flag); 5126 5127 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5128 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5129 "Allocate interrupts failed: %d\n", rc); 5130 5131 kmem_free(Adapter->htable, Adapter->intr_size); 5132 return (DDI_FAILURE); 5133 } 5134 5135 if (actual < count) { 5136 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5137 "Interrupts requested: %d, received: %d\n", 5138 count, actual); 5139 } 5140 5141 Adapter->intr_cnt = actual; 5142 5143 /* Get priority for first msi, assume remaining are all the same */ 5144 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5145 5146 if (rc != DDI_SUCCESS) { 5147 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5148 "Get interrupt priority failed: %d\n", rc); 5149 5150 /* Free already allocated intr */ 5151 for (y = 0; y < actual; y++) 5152 (void) ddi_intr_free(Adapter->htable[y]); 5153 5154 kmem_free(Adapter->htable, Adapter->intr_size); 5155 return (DDI_FAILURE); 5156 } 5157 5158 /* 5159 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5160 * use the interrupt service routine e1000g_intr_pciexpress() 5161 * to avoid interrupt stealing when sharing interrupt with other 5162 * devices. 5163 */ 5164 if (Adapter->shared.mac.type < e1000_82571) 5165 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5166 else 5167 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5168 5169 /* Call ddi_intr_add_handler() */ 5170 for (x = 0; x < actual; x++) { 5171 rc = ddi_intr_add_handler(Adapter->htable[x], 5172 intr_handler, (caddr_t)Adapter, NULL); 5173 5174 if (rc != DDI_SUCCESS) { 5175 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5176 "Add interrupt handler failed: %d\n", rc); 5177 5178 /* Remove already added handler */ 5179 for (y = 0; y < x; y++) 5180 (void) ddi_intr_remove_handler( 5181 Adapter->htable[y]); 5182 5183 /* Free already allocated intr */ 5184 for (y = 0; y < actual; y++) 5185 (void) ddi_intr_free(Adapter->htable[y]); 5186 5187 kmem_free(Adapter->htable, Adapter->intr_size); 5188 return (DDI_FAILURE); 5189 } 5190 } 5191 5192 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5193 5194 if (rc != DDI_SUCCESS) { 5195 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5196 "Get interrupt cap failed: %d\n", rc); 5197 5198 /* Free already allocated intr */ 5199 for (y = 0; y < actual; y++) { 5200 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5201 (void) ddi_intr_free(Adapter->htable[y]); 5202 } 5203 5204 kmem_free(Adapter->htable, Adapter->intr_size); 5205 return (DDI_FAILURE); 5206 } 5207 5208 return (DDI_SUCCESS); 5209 } 5210 5211 static int 5212 e1000g_rem_intrs(struct e1000g *Adapter) 5213 { 5214 int x; 5215 int rc; 5216 5217 for (x = 0; x < Adapter->intr_cnt; x++) { 5218 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5219 if (rc != DDI_SUCCESS) { 5220 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5221 "Remove intr handler failed: %d\n", rc); 5222 return (DDI_FAILURE); 5223 } 5224 5225 rc = ddi_intr_free(Adapter->htable[x]); 5226 if (rc != DDI_SUCCESS) { 5227 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5228 "Free intr failed: %d\n", rc); 5229 return (DDI_FAILURE); 5230 } 5231 } 5232 5233 kmem_free(Adapter->htable, Adapter->intr_size); 5234 5235 return (DDI_SUCCESS); 5236 } 5237 5238 static int 5239 e1000g_enable_intrs(struct e1000g *Adapter) 5240 { 5241 int x; 5242 int rc; 5243 5244 /* Enable interrupts */ 5245 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5246 /* Call ddi_intr_block_enable() for MSI */ 5247 rc = ddi_intr_block_enable(Adapter->htable, 5248 Adapter->intr_cnt); 5249 if (rc != DDI_SUCCESS) { 5250 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5251 "Enable block intr failed: %d\n", rc); 5252 return (DDI_FAILURE); 5253 } 5254 } else { 5255 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5256 for (x = 0; x < Adapter->intr_cnt; x++) { 5257 rc = ddi_intr_enable(Adapter->htable[x]); 5258 if (rc != DDI_SUCCESS) { 5259 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5260 "Enable intr failed: %d\n", rc); 5261 return (DDI_FAILURE); 5262 } 5263 } 5264 } 5265 5266 return (DDI_SUCCESS); 5267 } 5268 5269 static int 5270 e1000g_disable_intrs(struct e1000g *Adapter) 5271 { 5272 int x; 5273 int rc; 5274 5275 /* Disable all interrupts */ 5276 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5277 rc = ddi_intr_block_disable(Adapter->htable, 5278 Adapter->intr_cnt); 5279 if (rc != DDI_SUCCESS) { 5280 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5281 "Disable block intr failed: %d\n", rc); 5282 return (DDI_FAILURE); 5283 } 5284 } else { 5285 for (x = 0; x < Adapter->intr_cnt; x++) { 5286 rc = ddi_intr_disable(Adapter->htable[x]); 5287 if (rc != DDI_SUCCESS) { 5288 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5289 "Disable intr failed: %d\n", rc); 5290 return (DDI_FAILURE); 5291 } 5292 } 5293 } 5294 5295 return (DDI_SUCCESS); 5296 } 5297 5298 /* 5299 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5300 */ 5301 static void 5302 e1000g_get_phy_state(struct e1000g *Adapter) 5303 { 5304 struct e1000_hw *hw = &Adapter->shared; 5305 5306 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5307 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5308 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5309 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5310 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5311 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5312 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 5313 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5314 5315 Adapter->param_autoneg_cap = 5316 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5317 Adapter->param_pause_cap = 5318 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5319 Adapter->param_asym_pause_cap = 5320 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5321 Adapter->param_1000fdx_cap = 5322 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5323 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5324 Adapter->param_1000hdx_cap = 5325 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5326 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5327 Adapter->param_100t4_cap = 5328 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5329 Adapter->param_100fdx_cap = 5330 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5331 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5332 Adapter->param_100hdx_cap = 5333 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5334 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5335 Adapter->param_10fdx_cap = 5336 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5337 Adapter->param_10hdx_cap = 5338 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5339 5340 Adapter->param_adv_autoneg = hw->mac.autoneg; 5341 Adapter->param_adv_pause = 5342 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5343 Adapter->param_adv_asym_pause = 5344 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5345 Adapter->param_adv_1000hdx = 5346 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5347 Adapter->param_adv_100t4 = 5348 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5349 if (Adapter->param_adv_autoneg == 1) { 5350 Adapter->param_adv_1000fdx = 5351 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5352 Adapter->param_adv_100fdx = 5353 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5354 Adapter->param_adv_100hdx = 5355 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5356 Adapter->param_adv_10fdx = 5357 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5358 Adapter->param_adv_10hdx = 5359 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5360 } 5361 5362 Adapter->param_lp_autoneg = 5363 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5364 Adapter->param_lp_pause = 5365 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5366 Adapter->param_lp_asym_pause = 5367 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5368 Adapter->param_lp_1000fdx = 5369 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5370 Adapter->param_lp_1000hdx = 5371 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5372 Adapter->param_lp_100t4 = 5373 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5374 Adapter->param_lp_100fdx = 5375 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5376 Adapter->param_lp_100hdx = 5377 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5378 Adapter->param_lp_10fdx = 5379 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5380 Adapter->param_lp_10hdx = 5381 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5382 } 5383 5384 /* 5385 * FMA support 5386 */ 5387 5388 int 5389 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5390 { 5391 ddi_fm_error_t de; 5392 5393 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5394 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5395 return (de.fme_status); 5396 } 5397 5398 int 5399 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5400 { 5401 ddi_fm_error_t de; 5402 5403 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5404 return (de.fme_status); 5405 } 5406 5407 /* 5408 * The IO fault service error handling callback function 5409 */ 5410 static int 5411 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5412 { 5413 /* 5414 * as the driver can always deal with an error in any dma or 5415 * access handle, we can just return the fme_status value. 5416 */ 5417 pci_ereport_post(dip, err, NULL); 5418 return (err->fme_status); 5419 } 5420 5421 static void 5422 e1000g_fm_init(struct e1000g *Adapter) 5423 { 5424 ddi_iblock_cookie_t iblk; 5425 int fma_acc_flag, fma_dma_flag; 5426 5427 /* Only register with IO Fault Services if we have some capability */ 5428 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5429 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5430 fma_acc_flag = 1; 5431 } else { 5432 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5433 fma_acc_flag = 0; 5434 } 5435 5436 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5437 fma_dma_flag = 1; 5438 } else { 5439 fma_dma_flag = 0; 5440 } 5441 5442 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5443 5444 if (Adapter->fm_capabilities) { 5445 5446 /* Register capabilities with IO Fault Services */ 5447 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5448 5449 /* 5450 * Initialize pci ereport capabilities if ereport capable 5451 */ 5452 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5453 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5454 pci_ereport_setup(Adapter->dip); 5455 5456 /* 5457 * Register error callback if error callback capable 5458 */ 5459 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5460 ddi_fm_handler_register(Adapter->dip, 5461 e1000g_fm_error_cb, (void*) Adapter); 5462 } 5463 } 5464 5465 static void 5466 e1000g_fm_fini(struct e1000g *Adapter) 5467 { 5468 /* Only unregister FMA capabilities if we registered some */ 5469 if (Adapter->fm_capabilities) { 5470 5471 /* 5472 * Release any resources allocated by pci_ereport_setup() 5473 */ 5474 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5475 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5476 pci_ereport_teardown(Adapter->dip); 5477 5478 /* 5479 * Un-register error callback if error callback capable 5480 */ 5481 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5482 ddi_fm_handler_unregister(Adapter->dip); 5483 5484 /* Unregister from IO Fault Services */ 5485 ddi_fm_fini(Adapter->dip); 5486 } 5487 } 5488 5489 void 5490 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5491 { 5492 uint64_t ena; 5493 char buf[FM_MAX_CLASS]; 5494 5495 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5496 ena = fm_ena_generate(0, FM_ENA_FMT1); 5497 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5498 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5499 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5500 } 5501 } 5502 5503 static int 5504 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5505 uint_t pr_valsize, void *pr_val) 5506 { 5507 link_flowctrl_t fl; 5508 uint32_t fc; 5509 int err = 0; 5510 5511 ASSERT(pr_valsize > 0); 5512 switch (pr_num) { 5513 case MAC_PROP_AUTONEG: 5514 *(uint8_t *)pr_val = 5515 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5516 break; 5517 case MAC_PROP_FLOWCTRL: 5518 if (pr_valsize < sizeof (link_flowctrl_t)) 5519 return (EINVAL); 5520 fl = LINK_FLOWCTRL_BI; 5521 bcopy(&fl, pr_val, sizeof (fl)); 5522 break; 5523 case MAC_PROP_ADV_1000FDX_CAP: 5524 case MAC_PROP_EN_1000FDX_CAP: 5525 *(uint8_t *)pr_val = 5526 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5527 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5528 break; 5529 case MAC_PROP_ADV_1000HDX_CAP: 5530 case MAC_PROP_EN_1000HDX_CAP: 5531 *(uint8_t *)pr_val = 5532 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5533 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5534 break; 5535 case MAC_PROP_ADV_100FDX_CAP: 5536 case MAC_PROP_EN_100FDX_CAP: 5537 *(uint8_t *)pr_val = 5538 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5539 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5540 case MAC_PROP_ADV_100HDX_CAP: 5541 case MAC_PROP_EN_100HDX_CAP: 5542 *(uint8_t *)pr_val = 5543 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5544 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5545 break; 5546 case MAC_PROP_ADV_10FDX_CAP: 5547 case MAC_PROP_EN_10FDX_CAP: 5548 *(uint8_t *)pr_val = 5549 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5550 break; 5551 case MAC_PROP_ADV_10HDX_CAP: 5552 case MAC_PROP_EN_10HDX_CAP: 5553 *(uint8_t *)pr_val = 5554 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5555 break; 5556 default: 5557 err = ENOTSUP; 5558 break; 5559 } 5560 return (err); 5561 } 5562 5563 /* 5564 * synchronize the adv* and en* parameters. 5565 * 5566 * See comments in <sys/dld.h> for details of the *_en_* 5567 * parameters. The usage of ndd for setting adv parameters will 5568 * synchronize all the en parameters with the e1000g parameters, 5569 * implicity disalbing any settings made via dladm. 5570 */ 5571 static void 5572 e1000g_param_sync(struct e1000g *Adapter) 5573 { 5574 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5575 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5576 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5577 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5578 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5579 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5580 } 5581