1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 /* 26 * Copyright 2011 Nexenta Systems, Inc. All rights reserved. 27 * Copyright 2012 DEY Storage Systems, Inc. All rights reserved. 28 */ 29 30 /* 31 * ********************************************************************** 32 * * 33 * Module Name: * 34 * e1000g_main.c * 35 * * 36 * Abstract: * 37 * This file contains the interface routines for the solaris OS. * 38 * It has all DDI entry point routines and GLD entry point routines. * 39 * * 40 * This file also contains routines that take care of initialization * 41 * uninit routine and interrupt routine. * 42 * * 43 * ********************************************************************** 44 */ 45 46 #include <sys/dlpi.h> 47 #include <sys/mac.h> 48 #include "e1000g_sw.h" 49 #include "e1000g_debug.h" 50 51 static char ident[] = "Intel PRO/1000 Ethernet"; 52 /* LINTED E_STATIC_UNUSED */ 53 static char e1000g_version[] = "Driver Ver. 5.3.24"; 54 55 /* 56 * Proto types for DDI entry points 57 */ 58 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 59 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 60 static int e1000g_quiesce(dev_info_t *); 61 62 /* 63 * init and intr routines prototype 64 */ 65 static int e1000g_resume(dev_info_t *); 66 static int e1000g_suspend(dev_info_t *); 67 static uint_t e1000g_intr_pciexpress(caddr_t); 68 static uint_t e1000g_intr(caddr_t); 69 static void e1000g_intr_work(struct e1000g *, uint32_t); 70 #pragma inline(e1000g_intr_work) 71 static int e1000g_init(struct e1000g *); 72 static int e1000g_start(struct e1000g *, boolean_t); 73 static void e1000g_stop(struct e1000g *, boolean_t); 74 static int e1000g_m_start(void *); 75 static void e1000g_m_stop(void *); 76 static int e1000g_m_promisc(void *, boolean_t); 77 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 78 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 79 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 80 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 81 uint_t, const void *); 82 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 83 uint_t, void *); 84 static void e1000g_m_propinfo(void *, const char *, mac_prop_id_t, 85 mac_prop_info_handle_t); 86 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 87 const void *); 88 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, void *); 89 static void e1000g_init_locks(struct e1000g *); 90 static void e1000g_destroy_locks(struct e1000g *); 91 static int e1000g_identify_hardware(struct e1000g *); 92 static int e1000g_regs_map(struct e1000g *); 93 static int e1000g_set_driver_params(struct e1000g *); 94 static void e1000g_set_bufsize(struct e1000g *); 95 static int e1000g_register_mac(struct e1000g *); 96 static boolean_t e1000g_rx_drain(struct e1000g *); 97 static boolean_t e1000g_tx_drain(struct e1000g *); 98 static void e1000g_init_unicst(struct e1000g *); 99 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 100 static int e1000g_alloc_rx_data(struct e1000g *); 101 static void e1000g_release_multicast(struct e1000g *); 102 static void e1000g_pch_limits(struct e1000g *); 103 static uint32_t e1000g_mtu2maxframe(uint32_t); 104 105 /* 106 * Local routines 107 */ 108 static boolean_t e1000g_reset_adapter(struct e1000g *); 109 static void e1000g_tx_clean(struct e1000g *); 110 static void e1000g_rx_clean(struct e1000g *); 111 static void e1000g_link_timer(void *); 112 static void e1000g_local_timer(void *); 113 static boolean_t e1000g_link_check(struct e1000g *); 114 static boolean_t e1000g_stall_check(struct e1000g *); 115 static void e1000g_smartspeed(struct e1000g *); 116 static void e1000g_get_conf(struct e1000g *); 117 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 118 int *); 119 static void enable_watchdog_timer(struct e1000g *); 120 static void disable_watchdog_timer(struct e1000g *); 121 static void start_watchdog_timer(struct e1000g *); 122 static void restart_watchdog_timer(struct e1000g *); 123 static void stop_watchdog_timer(struct e1000g *); 124 static void stop_link_timer(struct e1000g *); 125 static void stop_82547_timer(e1000g_tx_ring_t *); 126 static void e1000g_force_speed_duplex(struct e1000g *); 127 static void e1000g_setup_max_mtu(struct e1000g *); 128 static void e1000g_get_max_frame_size(struct e1000g *); 129 static boolean_t is_valid_mac_addr(uint8_t *); 130 static void e1000g_unattach(dev_info_t *, struct e1000g *); 131 static int e1000g_get_bar_info(dev_info_t *, int, bar_info_t *); 132 #ifdef E1000G_DEBUG 133 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 134 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 135 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 136 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 137 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 138 struct iocblk *, mblk_t *); 139 #endif 140 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 141 struct iocblk *, mblk_t *); 142 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 143 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 144 static void e1000g_set_internal_loopback(struct e1000g *); 145 static void e1000g_set_external_loopback_1000(struct e1000g *); 146 static void e1000g_set_external_loopback_100(struct e1000g *); 147 static void e1000g_set_external_loopback_10(struct e1000g *); 148 static int e1000g_add_intrs(struct e1000g *); 149 static int e1000g_intr_add(struct e1000g *, int); 150 static int e1000g_rem_intrs(struct e1000g *); 151 static int e1000g_enable_intrs(struct e1000g *); 152 static int e1000g_disable_intrs(struct e1000g *); 153 static boolean_t e1000g_link_up(struct e1000g *); 154 #ifdef __sparc 155 static boolean_t e1000g_find_mac_address(struct e1000g *); 156 #endif 157 static void e1000g_get_phy_state(struct e1000g *); 158 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 159 const void *impl_data); 160 static void e1000g_fm_init(struct e1000g *Adapter); 161 static void e1000g_fm_fini(struct e1000g *Adapter); 162 static void e1000g_param_sync(struct e1000g *); 163 static void e1000g_get_driver_control(struct e1000_hw *); 164 static void e1000g_release_driver_control(struct e1000_hw *); 165 static void e1000g_restore_promisc(struct e1000g *Adapter); 166 167 char *e1000g_priv_props[] = { 168 "_tx_bcopy_threshold", 169 "_tx_interrupt_enable", 170 "_tx_intr_delay", 171 "_tx_intr_abs_delay", 172 "_rx_bcopy_threshold", 173 "_max_num_rcv_packets", 174 "_rx_intr_delay", 175 "_rx_intr_abs_delay", 176 "_intr_throttling_rate", 177 "_intr_adaptive", 178 "_adv_pause_cap", 179 "_adv_asym_pause_cap", 180 NULL 181 }; 182 183 static struct cb_ops cb_ws_ops = { 184 nulldev, /* cb_open */ 185 nulldev, /* cb_close */ 186 nodev, /* cb_strategy */ 187 nodev, /* cb_print */ 188 nodev, /* cb_dump */ 189 nodev, /* cb_read */ 190 nodev, /* cb_write */ 191 nodev, /* cb_ioctl */ 192 nodev, /* cb_devmap */ 193 nodev, /* cb_mmap */ 194 nodev, /* cb_segmap */ 195 nochpoll, /* cb_chpoll */ 196 ddi_prop_op, /* cb_prop_op */ 197 NULL, /* cb_stream */ 198 D_MP | D_HOTPLUG, /* cb_flag */ 199 CB_REV, /* cb_rev */ 200 nodev, /* cb_aread */ 201 nodev /* cb_awrite */ 202 }; 203 204 static struct dev_ops ws_ops = { 205 DEVO_REV, /* devo_rev */ 206 0, /* devo_refcnt */ 207 NULL, /* devo_getinfo */ 208 nulldev, /* devo_identify */ 209 nulldev, /* devo_probe */ 210 e1000g_attach, /* devo_attach */ 211 e1000g_detach, /* devo_detach */ 212 nodev, /* devo_reset */ 213 &cb_ws_ops, /* devo_cb_ops */ 214 NULL, /* devo_bus_ops */ 215 ddi_power, /* devo_power */ 216 e1000g_quiesce /* devo_quiesce */ 217 }; 218 219 static struct modldrv modldrv = { 220 &mod_driverops, /* Type of module. This one is a driver */ 221 ident, /* Discription string */ 222 &ws_ops, /* driver ops */ 223 }; 224 225 static struct modlinkage modlinkage = { 226 MODREV_1, &modldrv, NULL 227 }; 228 229 /* Access attributes for register mapping */ 230 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 231 DDI_DEVICE_ATTR_V1, 232 DDI_STRUCTURE_LE_ACC, 233 DDI_STRICTORDER_ACC, 234 DDI_FLAGERR_ACC 235 }; 236 237 #define E1000G_M_CALLBACK_FLAGS \ 238 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 239 240 static mac_callbacks_t e1000g_m_callbacks = { 241 E1000G_M_CALLBACK_FLAGS, 242 e1000g_m_stat, 243 e1000g_m_start, 244 e1000g_m_stop, 245 e1000g_m_promisc, 246 e1000g_m_multicst, 247 NULL, 248 e1000g_m_tx, 249 NULL, 250 e1000g_m_ioctl, 251 e1000g_m_getcapab, 252 NULL, 253 NULL, 254 e1000g_m_setprop, 255 e1000g_m_getprop, 256 e1000g_m_propinfo 257 }; 258 259 /* 260 * Global variables 261 */ 262 uint32_t e1000g_jumbo_mtu = MAXIMUM_MTU_9K; 263 uint32_t e1000g_mblks_pending = 0; 264 /* 265 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 266 * Here we maintain a private dev_info list if e1000g_force_detach is 267 * enabled. If we force the driver to detach while there are still some 268 * rx buffers retained in the upper layer, we have to keep a copy of the 269 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 270 * structure will be freed after the driver is detached. However when we 271 * finally free those rx buffers released by the upper layer, we need to 272 * refer to the dev_info to free the dma buffers. So we save a copy of 273 * the dev_info for this purpose. On x86 platform, we assume this copy 274 * of dev_info is always valid, but on SPARC platform, it could be invalid 275 * after the system board level DR operation. For this reason, the global 276 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 277 */ 278 #ifdef __sparc 279 boolean_t e1000g_force_detach = B_FALSE; 280 #else 281 boolean_t e1000g_force_detach = B_TRUE; 282 #endif 283 private_devi_list_t *e1000g_private_devi_list = NULL; 284 285 /* 286 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 287 * the private dev_info list, and to serialize the processing of rx buffer 288 * freeing and rx buffer recycling. 289 */ 290 kmutex_t e1000g_rx_detach_lock; 291 /* 292 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 293 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 294 * If there are many e1000g instances, the system may run out of DVMA 295 * resources during the initialization of the instances, then the flag will 296 * be changed to "USE_DMA". Because different e1000g instances are initialized 297 * in parallel, we need to use this lock to protect the flag. 298 */ 299 krwlock_t e1000g_dma_type_lock; 300 301 /* 302 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 303 * Based on the information from Intel, the 82546 chipset has some hardware 304 * problem. When one port is being reset and the other port is trying to 305 * access the eeprom, it could cause system hang or panic. To workaround this 306 * hardware problem, we use a global mutex to prevent such operations from 307 * happening simultaneously on different instances. This workaround is applied 308 * to all the devices supported by this driver. 309 */ 310 kmutex_t e1000g_nvm_lock; 311 312 /* 313 * Loadable module configuration entry points for the driver 314 */ 315 316 /* 317 * _init - module initialization 318 */ 319 int 320 _init(void) 321 { 322 int status; 323 324 mac_init_ops(&ws_ops, WSNAME); 325 status = mod_install(&modlinkage); 326 if (status != DDI_SUCCESS) 327 mac_fini_ops(&ws_ops); 328 else { 329 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 330 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 331 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 332 } 333 334 return (status); 335 } 336 337 /* 338 * _fini - module finalization 339 */ 340 int 341 _fini(void) 342 { 343 int status; 344 345 if (e1000g_mblks_pending != 0) 346 return (EBUSY); 347 348 status = mod_remove(&modlinkage); 349 if (status == DDI_SUCCESS) { 350 mac_fini_ops(&ws_ops); 351 352 if (e1000g_force_detach) { 353 private_devi_list_t *devi_node; 354 355 mutex_enter(&e1000g_rx_detach_lock); 356 while (e1000g_private_devi_list != NULL) { 357 devi_node = e1000g_private_devi_list; 358 e1000g_private_devi_list = 359 e1000g_private_devi_list->next; 360 361 kmem_free(devi_node->priv_dip, 362 sizeof (struct dev_info)); 363 kmem_free(devi_node, 364 sizeof (private_devi_list_t)); 365 } 366 mutex_exit(&e1000g_rx_detach_lock); 367 } 368 369 mutex_destroy(&e1000g_rx_detach_lock); 370 rw_destroy(&e1000g_dma_type_lock); 371 mutex_destroy(&e1000g_nvm_lock); 372 } 373 374 return (status); 375 } 376 377 /* 378 * _info - module information 379 */ 380 int 381 _info(struct modinfo *modinfop) 382 { 383 return (mod_info(&modlinkage, modinfop)); 384 } 385 386 /* 387 * e1000g_attach - driver attach 388 * 389 * This function is the device-specific initialization entry 390 * point. This entry point is required and must be written. 391 * The DDI_ATTACH command must be provided in the attach entry 392 * point. When attach() is called with cmd set to DDI_ATTACH, 393 * all normal kernel services (such as kmem_alloc(9F)) are 394 * available for use by the driver. 395 * 396 * The attach() function will be called once for each instance 397 * of the device on the system with cmd set to DDI_ATTACH. 398 * Until attach() succeeds, the only driver entry points which 399 * may be called are open(9E) and getinfo(9E). 400 */ 401 static int 402 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 403 { 404 struct e1000g *Adapter; 405 struct e1000_hw *hw; 406 struct e1000g_osdep *osdep; 407 int instance; 408 409 switch (cmd) { 410 default: 411 e1000g_log(NULL, CE_WARN, 412 "Unsupported command send to e1000g_attach... "); 413 return (DDI_FAILURE); 414 415 case DDI_RESUME: 416 return (e1000g_resume(devinfo)); 417 418 case DDI_ATTACH: 419 break; 420 } 421 422 /* 423 * get device instance number 424 */ 425 instance = ddi_get_instance(devinfo); 426 427 /* 428 * Allocate soft data structure 429 */ 430 Adapter = 431 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 432 433 Adapter->dip = devinfo; 434 Adapter->instance = instance; 435 Adapter->tx_ring->adapter = Adapter; 436 Adapter->rx_ring->adapter = Adapter; 437 438 hw = &Adapter->shared; 439 osdep = &Adapter->osdep; 440 hw->back = osdep; 441 osdep->adapter = Adapter; 442 443 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 444 445 /* 446 * Initialize for fma support 447 */ 448 (void) e1000g_get_prop(Adapter, "fm-capable", 449 0, 0x0f, 450 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 451 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 452 &Adapter->fm_capabilities); 453 e1000g_fm_init(Adapter); 454 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 455 456 /* 457 * PCI Configure 458 */ 459 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 460 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 461 goto attach_fail; 462 } 463 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 464 465 /* 466 * Setup hardware 467 */ 468 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 469 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 470 goto attach_fail; 471 } 472 473 /* 474 * Map in the device registers. 475 */ 476 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 477 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 478 goto attach_fail; 479 } 480 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 481 482 /* 483 * Initialize driver parameters 484 */ 485 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 486 goto attach_fail; 487 } 488 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 489 490 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 491 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 492 goto attach_fail; 493 } 494 495 /* 496 * Initialize interrupts 497 */ 498 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 499 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 500 goto attach_fail; 501 } 502 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 503 504 /* 505 * Initialize mutex's for this device. 506 * Do this before enabling the interrupt handler and 507 * register the softint to avoid the condition where 508 * interrupt handler can try using uninitialized mutex 509 */ 510 e1000g_init_locks(Adapter); 511 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 512 513 /* 514 * Initialize Driver Counters 515 */ 516 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 517 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 518 goto attach_fail; 519 } 520 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 521 522 /* 523 * Initialize chip hardware and software structures 524 */ 525 rw_enter(&Adapter->chip_lock, RW_WRITER); 526 if (e1000g_init(Adapter) != DDI_SUCCESS) { 527 rw_exit(&Adapter->chip_lock); 528 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 529 goto attach_fail; 530 } 531 rw_exit(&Adapter->chip_lock); 532 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 533 534 /* 535 * Register the driver to the MAC 536 */ 537 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 538 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 539 goto attach_fail; 540 } 541 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 542 543 /* 544 * Now that mutex locks are initialized, and the chip is also 545 * initialized, enable interrupts. 546 */ 547 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 548 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 549 goto attach_fail; 550 } 551 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 552 553 /* 554 * If e1000g_force_detach is enabled, in global private dip list, 555 * we will create a new entry, which maintains the priv_dip for DR 556 * supports after driver detached. 557 */ 558 if (e1000g_force_detach) { 559 private_devi_list_t *devi_node; 560 561 Adapter->priv_dip = 562 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 563 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 564 sizeof (struct dev_info)); 565 566 devi_node = 567 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 568 569 mutex_enter(&e1000g_rx_detach_lock); 570 devi_node->priv_dip = Adapter->priv_dip; 571 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 572 devi_node->pending_rx_count = 0; 573 574 Adapter->priv_devi_node = devi_node; 575 576 if (e1000g_private_devi_list == NULL) { 577 devi_node->prev = NULL; 578 devi_node->next = NULL; 579 e1000g_private_devi_list = devi_node; 580 } else { 581 devi_node->prev = NULL; 582 devi_node->next = e1000g_private_devi_list; 583 e1000g_private_devi_list->prev = devi_node; 584 e1000g_private_devi_list = devi_node; 585 } 586 mutex_exit(&e1000g_rx_detach_lock); 587 } 588 589 Adapter->e1000g_state = E1000G_INITIALIZED; 590 return (DDI_SUCCESS); 591 592 attach_fail: 593 e1000g_unattach(devinfo, Adapter); 594 return (DDI_FAILURE); 595 } 596 597 static int 598 e1000g_register_mac(struct e1000g *Adapter) 599 { 600 struct e1000_hw *hw = &Adapter->shared; 601 mac_register_t *mac; 602 int err; 603 604 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 605 return (DDI_FAILURE); 606 607 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 608 mac->m_driver = Adapter; 609 mac->m_dip = Adapter->dip; 610 mac->m_src_addr = hw->mac.addr; 611 mac->m_callbacks = &e1000g_m_callbacks; 612 mac->m_min_sdu = 0; 613 mac->m_max_sdu = Adapter->default_mtu; 614 mac->m_margin = VLAN_TAGSZ; 615 mac->m_priv_props = e1000g_priv_props; 616 mac->m_v12n = MAC_VIRT_LEVEL1; 617 618 err = mac_register(mac, &Adapter->mh); 619 mac_free(mac); 620 621 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 622 } 623 624 static int 625 e1000g_identify_hardware(struct e1000g *Adapter) 626 { 627 struct e1000_hw *hw = &Adapter->shared; 628 struct e1000g_osdep *osdep = &Adapter->osdep; 629 630 /* Get the device id */ 631 hw->vendor_id = 632 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 633 hw->device_id = 634 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 635 hw->revision_id = 636 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 637 hw->subsystem_device_id = 638 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 639 hw->subsystem_vendor_id = 640 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 641 642 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 643 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 644 "MAC type could not be set properly."); 645 return (DDI_FAILURE); 646 } 647 648 return (DDI_SUCCESS); 649 } 650 651 static int 652 e1000g_regs_map(struct e1000g *Adapter) 653 { 654 dev_info_t *devinfo = Adapter->dip; 655 struct e1000_hw *hw = &Adapter->shared; 656 struct e1000g_osdep *osdep = &Adapter->osdep; 657 off_t mem_size; 658 bar_info_t bar_info; 659 int offset, rnumber; 660 661 rnumber = ADAPTER_REG_SET; 662 /* Get size of adapter register memory */ 663 if (ddi_dev_regsize(devinfo, rnumber, &mem_size) != 664 DDI_SUCCESS) { 665 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 666 "ddi_dev_regsize for registers failed"); 667 return (DDI_FAILURE); 668 } 669 670 /* Map adapter register memory */ 671 if ((ddi_regs_map_setup(devinfo, rnumber, 672 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 673 &osdep->reg_handle)) != DDI_SUCCESS) { 674 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 675 "ddi_regs_map_setup for registers failed"); 676 goto regs_map_fail; 677 } 678 679 /* ICH needs to map flash memory */ 680 switch (hw->mac.type) { 681 case e1000_ich8lan: 682 case e1000_ich9lan: 683 case e1000_ich10lan: 684 case e1000_pchlan: 685 case e1000_pch2lan: 686 rnumber = ICH_FLASH_REG_SET; 687 688 /* get flash size */ 689 if (ddi_dev_regsize(devinfo, rnumber, 690 &mem_size) != DDI_SUCCESS) { 691 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 692 "ddi_dev_regsize for ICH flash failed"); 693 goto regs_map_fail; 694 } 695 696 /* map flash in */ 697 if (ddi_regs_map_setup(devinfo, rnumber, 698 (caddr_t *)&hw->flash_address, 0, 699 mem_size, &e1000g_regs_acc_attr, 700 &osdep->ich_flash_handle) != DDI_SUCCESS) { 701 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 702 "ddi_regs_map_setup for ICH flash failed"); 703 goto regs_map_fail; 704 } 705 break; 706 default: 707 break; 708 } 709 710 /* map io space */ 711 switch (hw->mac.type) { 712 case e1000_82544: 713 case e1000_82540: 714 case e1000_82545: 715 case e1000_82546: 716 case e1000_82541: 717 case e1000_82541_rev_2: 718 /* find the IO bar */ 719 rnumber = -1; 720 for (offset = PCI_CONF_BASE1; 721 offset <= PCI_CONF_BASE5; offset += 4) { 722 if (e1000g_get_bar_info(devinfo, offset, &bar_info) 723 != DDI_SUCCESS) 724 continue; 725 if (bar_info.type == E1000G_BAR_IO) { 726 rnumber = bar_info.rnumber; 727 break; 728 } 729 } 730 731 if (rnumber < 0) { 732 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 733 "No io space is found"); 734 goto regs_map_fail; 735 } 736 737 /* get io space size */ 738 if (ddi_dev_regsize(devinfo, rnumber, 739 &mem_size) != DDI_SUCCESS) { 740 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 741 "ddi_dev_regsize for io space failed"); 742 goto regs_map_fail; 743 } 744 745 /* map io space */ 746 if ((ddi_regs_map_setup(devinfo, rnumber, 747 (caddr_t *)&hw->io_base, 0, mem_size, 748 &e1000g_regs_acc_attr, 749 &osdep->io_reg_handle)) != DDI_SUCCESS) { 750 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 751 "ddi_regs_map_setup for io space failed"); 752 goto regs_map_fail; 753 } 754 break; 755 default: 756 hw->io_base = 0; 757 break; 758 } 759 760 return (DDI_SUCCESS); 761 762 regs_map_fail: 763 if (osdep->reg_handle != NULL) 764 ddi_regs_map_free(&osdep->reg_handle); 765 if (osdep->ich_flash_handle != NULL) 766 ddi_regs_map_free(&osdep->ich_flash_handle); 767 return (DDI_FAILURE); 768 } 769 770 static int 771 e1000g_set_driver_params(struct e1000g *Adapter) 772 { 773 struct e1000_hw *hw; 774 775 hw = &Adapter->shared; 776 777 /* Set MAC type and initialize hardware functions */ 778 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 779 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 780 "Could not setup hardware functions"); 781 return (DDI_FAILURE); 782 } 783 784 /* Get bus information */ 785 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 786 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 787 "Could not get bus information"); 788 return (DDI_FAILURE); 789 } 790 791 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 792 793 hw->mac.autoneg_failed = B_TRUE; 794 795 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 796 hw->phy.autoneg_wait_to_complete = B_FALSE; 797 798 /* Adaptive IFS related changes */ 799 hw->mac.adaptive_ifs = B_TRUE; 800 801 /* Enable phy init script for IGP phy of 82541/82547 */ 802 if ((hw->mac.type == e1000_82547) || 803 (hw->mac.type == e1000_82541) || 804 (hw->mac.type == e1000_82547_rev_2) || 805 (hw->mac.type == e1000_82541_rev_2)) 806 e1000_init_script_state_82541(hw, B_TRUE); 807 808 /* Enable the TTL workaround for 82541/82547 */ 809 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 810 811 #ifdef __sparc 812 Adapter->strip_crc = B_TRUE; 813 #else 814 Adapter->strip_crc = B_FALSE; 815 #endif 816 817 /* setup the maximum MTU size of the chip */ 818 e1000g_setup_max_mtu(Adapter); 819 820 /* Get speed/duplex settings in conf file */ 821 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 822 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 823 e1000g_force_speed_duplex(Adapter); 824 825 /* Get Jumbo Frames settings in conf file */ 826 e1000g_get_max_frame_size(Adapter); 827 828 /* Get conf file properties */ 829 e1000g_get_conf(Adapter); 830 831 /* enforce PCH limits */ 832 e1000g_pch_limits(Adapter); 833 834 /* Set Rx/Tx buffer size */ 835 e1000g_set_bufsize(Adapter); 836 837 /* Master Latency Timer */ 838 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 839 840 /* copper options */ 841 if (hw->phy.media_type == e1000_media_type_copper) { 842 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 843 hw->phy.disable_polarity_correction = B_FALSE; 844 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 845 } 846 847 /* The initial link state should be "unknown" */ 848 Adapter->link_state = LINK_STATE_UNKNOWN; 849 850 /* Initialize rx parameters */ 851 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 852 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 853 854 /* Initialize tx parameters */ 855 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 856 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 857 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 858 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 859 860 /* Initialize rx parameters */ 861 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 862 863 return (DDI_SUCCESS); 864 } 865 866 static void 867 e1000g_setup_max_mtu(struct e1000g *Adapter) 868 { 869 struct e1000_mac_info *mac = &Adapter->shared.mac; 870 struct e1000_phy_info *phy = &Adapter->shared.phy; 871 872 switch (mac->type) { 873 /* types that do not support jumbo frames */ 874 case e1000_ich8lan: 875 case e1000_82573: 876 case e1000_82583: 877 Adapter->max_mtu = ETHERMTU; 878 break; 879 /* ich9 supports jumbo frames except on one phy type */ 880 case e1000_ich9lan: 881 if (phy->type == e1000_phy_ife) 882 Adapter->max_mtu = ETHERMTU; 883 else 884 Adapter->max_mtu = MAXIMUM_MTU_9K; 885 break; 886 /* pch can do jumbo frames up to 4K */ 887 case e1000_pchlan: 888 Adapter->max_mtu = MAXIMUM_MTU_4K; 889 break; 890 /* pch2 can do jumbo frames up to 9K */ 891 case e1000_pch2lan: 892 Adapter->max_mtu = MAXIMUM_MTU_9K; 893 break; 894 /* types with a special limit */ 895 case e1000_82571: 896 case e1000_82572: 897 case e1000_82574: 898 case e1000_80003es2lan: 899 case e1000_ich10lan: 900 if (e1000g_jumbo_mtu >= ETHERMTU && 901 e1000g_jumbo_mtu <= MAXIMUM_MTU_9K) { 902 Adapter->max_mtu = e1000g_jumbo_mtu; 903 } else { 904 Adapter->max_mtu = MAXIMUM_MTU_9K; 905 } 906 break; 907 /* default limit is 16K */ 908 default: 909 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 910 sizeof (struct ether_vlan_header) - ETHERFCSL; 911 break; 912 } 913 } 914 915 static void 916 e1000g_set_bufsize(struct e1000g *Adapter) 917 { 918 struct e1000_mac_info *mac = &Adapter->shared.mac; 919 uint64_t rx_size; 920 uint64_t tx_size; 921 922 dev_info_t *devinfo = Adapter->dip; 923 #ifdef __sparc 924 ulong_t iommu_pagesize; 925 #endif 926 /* Get the system page size */ 927 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 928 929 #ifdef __sparc 930 iommu_pagesize = dvma_pagesize(devinfo); 931 if (iommu_pagesize != 0) { 932 if (Adapter->sys_page_sz == iommu_pagesize) { 933 if (iommu_pagesize > 0x4000) 934 Adapter->sys_page_sz = 0x4000; 935 } else { 936 if (Adapter->sys_page_sz > iommu_pagesize) 937 Adapter->sys_page_sz = iommu_pagesize; 938 } 939 } 940 if (Adapter->lso_enable) { 941 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 942 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 943 } else { 944 Adapter->dvma_page_num = Adapter->max_frame_size / 945 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 946 } 947 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 948 #endif 949 950 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 951 952 if (Adapter->mem_workaround_82546 && 953 ((mac->type == e1000_82545) || 954 (mac->type == e1000_82546) || 955 (mac->type == e1000_82546_rev_3))) { 956 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 957 } else { 958 rx_size = Adapter->max_frame_size; 959 if ((rx_size > FRAME_SIZE_UPTO_2K) && 960 (rx_size <= FRAME_SIZE_UPTO_4K)) 961 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 962 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 963 (rx_size <= FRAME_SIZE_UPTO_8K)) 964 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 965 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 966 (rx_size <= FRAME_SIZE_UPTO_16K)) 967 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 968 else 969 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 970 } 971 Adapter->rx_buffer_size += E1000G_IPALIGNROOM; 972 973 tx_size = Adapter->max_frame_size; 974 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 975 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 976 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 977 (tx_size <= FRAME_SIZE_UPTO_8K)) 978 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 979 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 980 (tx_size <= FRAME_SIZE_UPTO_16K)) 981 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 982 else 983 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 984 985 /* 986 * For Wiseman adapters we have an requirement of having receive 987 * buffers aligned at 256 byte boundary. Since Livengood does not 988 * require this and forcing it for all hardwares will have 989 * performance implications, I am making it applicable only for 990 * Wiseman and for Jumbo frames enabled mode as rest of the time, 991 * it is okay to have normal frames...but it does involve a 992 * potential risk where we may loose data if buffer is not 993 * aligned...so all wiseman boards to have 256 byte aligned 994 * buffers 995 */ 996 if (mac->type < e1000_82543) 997 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 998 else 999 Adapter->rx_buf_align = 1; 1000 } 1001 1002 /* 1003 * e1000g_detach - driver detach 1004 * 1005 * The detach() function is the complement of the attach routine. 1006 * If cmd is set to DDI_DETACH, detach() is used to remove the 1007 * state associated with a given instance of a device node 1008 * prior to the removal of that instance from the system. 1009 * 1010 * The detach() function will be called once for each instance 1011 * of the device for which there has been a successful attach() 1012 * once there are no longer any opens on the device. 1013 * 1014 * Interrupts routine are disabled, All memory allocated by this 1015 * driver are freed. 1016 */ 1017 static int 1018 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 1019 { 1020 struct e1000g *Adapter; 1021 boolean_t rx_drain; 1022 1023 switch (cmd) { 1024 default: 1025 return (DDI_FAILURE); 1026 1027 case DDI_SUSPEND: 1028 return (e1000g_suspend(devinfo)); 1029 1030 case DDI_DETACH: 1031 break; 1032 } 1033 1034 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1035 if (Adapter == NULL) 1036 return (DDI_FAILURE); 1037 1038 rx_drain = e1000g_rx_drain(Adapter); 1039 if (!rx_drain && !e1000g_force_detach) 1040 return (DDI_FAILURE); 1041 1042 if (mac_unregister(Adapter->mh) != 0) { 1043 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 1044 return (DDI_FAILURE); 1045 } 1046 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 1047 1048 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 1049 1050 if (!e1000g_force_detach && !rx_drain) 1051 return (DDI_FAILURE); 1052 1053 e1000g_unattach(devinfo, Adapter); 1054 1055 return (DDI_SUCCESS); 1056 } 1057 1058 /* 1059 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1060 */ 1061 void 1062 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1063 { 1064 ASSERT(e1000g_private_devi_list != NULL); 1065 ASSERT(devi_node != NULL); 1066 1067 if (devi_node->prev != NULL) 1068 devi_node->prev->next = devi_node->next; 1069 if (devi_node->next != NULL) 1070 devi_node->next->prev = devi_node->prev; 1071 if (devi_node == e1000g_private_devi_list) 1072 e1000g_private_devi_list = devi_node->next; 1073 1074 kmem_free(devi_node->priv_dip, 1075 sizeof (struct dev_info)); 1076 kmem_free(devi_node, 1077 sizeof (private_devi_list_t)); 1078 } 1079 1080 static void 1081 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1082 { 1083 private_devi_list_t *devi_node; 1084 int result; 1085 1086 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1087 (void) e1000g_disable_intrs(Adapter); 1088 } 1089 1090 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1091 (void) mac_unregister(Adapter->mh); 1092 } 1093 1094 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1095 (void) e1000g_rem_intrs(Adapter); 1096 } 1097 1098 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1099 (void) ddi_prop_remove_all(devinfo); 1100 } 1101 1102 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1103 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1104 } 1105 1106 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1107 stop_link_timer(Adapter); 1108 1109 mutex_enter(&e1000g_nvm_lock); 1110 result = e1000_reset_hw(&Adapter->shared); 1111 mutex_exit(&e1000g_nvm_lock); 1112 1113 if (result != E1000_SUCCESS) { 1114 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1115 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1116 } 1117 } 1118 1119 e1000g_release_multicast(Adapter); 1120 1121 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1122 if (Adapter->osdep.reg_handle != NULL) 1123 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1124 if (Adapter->osdep.ich_flash_handle != NULL) 1125 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1126 if (Adapter->osdep.io_reg_handle != NULL) 1127 ddi_regs_map_free(&Adapter->osdep.io_reg_handle); 1128 } 1129 1130 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1131 if (Adapter->osdep.cfg_handle != NULL) 1132 pci_config_teardown(&Adapter->osdep.cfg_handle); 1133 } 1134 1135 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1136 e1000g_destroy_locks(Adapter); 1137 } 1138 1139 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1140 e1000g_fm_fini(Adapter); 1141 } 1142 1143 mutex_enter(&e1000g_rx_detach_lock); 1144 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1145 devi_node = Adapter->priv_devi_node; 1146 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1147 1148 if (devi_node->pending_rx_count == 0) { 1149 e1000g_free_priv_devi_node(devi_node); 1150 } 1151 } 1152 mutex_exit(&e1000g_rx_detach_lock); 1153 1154 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1155 1156 /* 1157 * Another hotplug spec requirement, 1158 * run ddi_set_driver_private(devinfo, null); 1159 */ 1160 ddi_set_driver_private(devinfo, NULL); 1161 } 1162 1163 /* 1164 * Get the BAR type and rnumber for a given PCI BAR offset 1165 */ 1166 static int 1167 e1000g_get_bar_info(dev_info_t *dip, int bar_offset, bar_info_t *bar_info) 1168 { 1169 pci_regspec_t *regs; 1170 uint_t regs_length; 1171 int type, rnumber, rcount; 1172 1173 ASSERT((bar_offset >= PCI_CONF_BASE0) && 1174 (bar_offset <= PCI_CONF_BASE5)); 1175 1176 /* 1177 * Get the DDI "reg" property 1178 */ 1179 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 1180 DDI_PROP_DONTPASS, "reg", (int **)®s, 1181 ®s_length) != DDI_PROP_SUCCESS) { 1182 return (DDI_FAILURE); 1183 } 1184 1185 rcount = regs_length * sizeof (int) / sizeof (pci_regspec_t); 1186 /* 1187 * Check the BAR offset 1188 */ 1189 for (rnumber = 0; rnumber < rcount; ++rnumber) { 1190 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) { 1191 type = regs[rnumber].pci_phys_hi & PCI_ADDR_MASK; 1192 break; 1193 } 1194 } 1195 1196 ddi_prop_free(regs); 1197 1198 if (rnumber >= rcount) 1199 return (DDI_FAILURE); 1200 1201 switch (type) { 1202 case PCI_ADDR_CONFIG: 1203 bar_info->type = E1000G_BAR_CONFIG; 1204 break; 1205 case PCI_ADDR_IO: 1206 bar_info->type = E1000G_BAR_IO; 1207 break; 1208 case PCI_ADDR_MEM32: 1209 bar_info->type = E1000G_BAR_MEM32; 1210 break; 1211 case PCI_ADDR_MEM64: 1212 bar_info->type = E1000G_BAR_MEM64; 1213 break; 1214 default: 1215 return (DDI_FAILURE); 1216 } 1217 bar_info->rnumber = rnumber; 1218 return (DDI_SUCCESS); 1219 } 1220 1221 static void 1222 e1000g_init_locks(struct e1000g *Adapter) 1223 { 1224 e1000g_tx_ring_t *tx_ring; 1225 e1000g_rx_ring_t *rx_ring; 1226 1227 rw_init(&Adapter->chip_lock, NULL, 1228 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1229 mutex_init(&Adapter->link_lock, NULL, 1230 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1231 mutex_init(&Adapter->watchdog_lock, NULL, 1232 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1233 1234 tx_ring = Adapter->tx_ring; 1235 1236 mutex_init(&tx_ring->tx_lock, NULL, 1237 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1238 mutex_init(&tx_ring->usedlist_lock, NULL, 1239 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1240 mutex_init(&tx_ring->freelist_lock, NULL, 1241 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1242 1243 rx_ring = Adapter->rx_ring; 1244 1245 mutex_init(&rx_ring->rx_lock, NULL, 1246 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1247 } 1248 1249 static void 1250 e1000g_destroy_locks(struct e1000g *Adapter) 1251 { 1252 e1000g_tx_ring_t *tx_ring; 1253 e1000g_rx_ring_t *rx_ring; 1254 1255 tx_ring = Adapter->tx_ring; 1256 mutex_destroy(&tx_ring->tx_lock); 1257 mutex_destroy(&tx_ring->usedlist_lock); 1258 mutex_destroy(&tx_ring->freelist_lock); 1259 1260 rx_ring = Adapter->rx_ring; 1261 mutex_destroy(&rx_ring->rx_lock); 1262 1263 mutex_destroy(&Adapter->link_lock); 1264 mutex_destroy(&Adapter->watchdog_lock); 1265 rw_destroy(&Adapter->chip_lock); 1266 1267 /* destory mutex initialized in shared code */ 1268 e1000_destroy_hw_mutex(&Adapter->shared); 1269 } 1270 1271 static int 1272 e1000g_resume(dev_info_t *devinfo) 1273 { 1274 struct e1000g *Adapter; 1275 1276 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1277 if (Adapter == NULL) 1278 e1000g_log(Adapter, CE_PANIC, 1279 "Instance pointer is null\n"); 1280 1281 if (Adapter->dip != devinfo) 1282 e1000g_log(Adapter, CE_PANIC, 1283 "Devinfo is not the same as saved devinfo\n"); 1284 1285 rw_enter(&Adapter->chip_lock, RW_WRITER); 1286 1287 if (Adapter->e1000g_state & E1000G_STARTED) { 1288 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1289 rw_exit(&Adapter->chip_lock); 1290 /* 1291 * We note the failure, but return success, as the 1292 * system is still usable without this controller. 1293 */ 1294 e1000g_log(Adapter, CE_WARN, 1295 "e1000g_resume: failed to restart controller\n"); 1296 return (DDI_SUCCESS); 1297 } 1298 /* Enable and start the watchdog timer */ 1299 enable_watchdog_timer(Adapter); 1300 } 1301 1302 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1303 1304 rw_exit(&Adapter->chip_lock); 1305 1306 return (DDI_SUCCESS); 1307 } 1308 1309 static int 1310 e1000g_suspend(dev_info_t *devinfo) 1311 { 1312 struct e1000g *Adapter; 1313 1314 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1315 if (Adapter == NULL) 1316 return (DDI_FAILURE); 1317 1318 rw_enter(&Adapter->chip_lock, RW_WRITER); 1319 1320 Adapter->e1000g_state |= E1000G_SUSPENDED; 1321 1322 /* if the port isn't plumbed, we can simply return */ 1323 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1324 rw_exit(&Adapter->chip_lock); 1325 return (DDI_SUCCESS); 1326 } 1327 1328 e1000g_stop(Adapter, B_FALSE); 1329 1330 rw_exit(&Adapter->chip_lock); 1331 1332 /* Disable and stop all the timers */ 1333 disable_watchdog_timer(Adapter); 1334 stop_link_timer(Adapter); 1335 stop_82547_timer(Adapter->tx_ring); 1336 1337 return (DDI_SUCCESS); 1338 } 1339 1340 static int 1341 e1000g_init(struct e1000g *Adapter) 1342 { 1343 uint32_t pba; 1344 uint32_t high_water; 1345 struct e1000_hw *hw; 1346 clock_t link_timeout; 1347 int result; 1348 1349 hw = &Adapter->shared; 1350 1351 /* 1352 * reset to put the hardware in a known state 1353 * before we try to do anything with the eeprom 1354 */ 1355 mutex_enter(&e1000g_nvm_lock); 1356 result = e1000_reset_hw(hw); 1357 mutex_exit(&e1000g_nvm_lock); 1358 1359 if (result != E1000_SUCCESS) { 1360 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1361 goto init_fail; 1362 } 1363 1364 mutex_enter(&e1000g_nvm_lock); 1365 result = e1000_validate_nvm_checksum(hw); 1366 if (result < E1000_SUCCESS) { 1367 /* 1368 * Some PCI-E parts fail the first check due to 1369 * the link being in sleep state. Call it again, 1370 * if it fails a second time its a real issue. 1371 */ 1372 result = e1000_validate_nvm_checksum(hw); 1373 } 1374 mutex_exit(&e1000g_nvm_lock); 1375 1376 if (result < E1000_SUCCESS) { 1377 e1000g_log(Adapter, CE_WARN, 1378 "Invalid NVM checksum. Please contact " 1379 "the vendor to update the NVM."); 1380 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1381 goto init_fail; 1382 } 1383 1384 result = 0; 1385 #ifdef __sparc 1386 /* 1387 * First, we try to get the local ethernet address from OBP. If 1388 * failed, then we get it from the EEPROM of NIC card. 1389 */ 1390 result = e1000g_find_mac_address(Adapter); 1391 #endif 1392 /* Get the local ethernet address. */ 1393 if (!result) { 1394 mutex_enter(&e1000g_nvm_lock); 1395 result = e1000_read_mac_addr(hw); 1396 mutex_exit(&e1000g_nvm_lock); 1397 } 1398 1399 if (result < E1000_SUCCESS) { 1400 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1401 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1402 goto init_fail; 1403 } 1404 1405 /* check for valid mac address */ 1406 if (!is_valid_mac_addr(hw->mac.addr)) { 1407 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1408 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1409 goto init_fail; 1410 } 1411 1412 /* Set LAA state for 82571 chipset */ 1413 e1000_set_laa_state_82571(hw, B_TRUE); 1414 1415 /* Master Latency Timer implementation */ 1416 if (Adapter->master_latency_timer) { 1417 pci_config_put8(Adapter->osdep.cfg_handle, 1418 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1419 } 1420 1421 if (hw->mac.type < e1000_82547) { 1422 /* 1423 * Total FIFO is 64K 1424 */ 1425 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1426 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1427 else 1428 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1429 } else if ((hw->mac.type == e1000_82571) || 1430 (hw->mac.type == e1000_82572) || 1431 (hw->mac.type == e1000_80003es2lan)) { 1432 /* 1433 * Total FIFO is 48K 1434 */ 1435 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1436 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1437 else 1438 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1439 } else if (hw->mac.type == e1000_82573) { 1440 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1441 } else if (hw->mac.type == e1000_82574) { 1442 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1443 pba = E1000_READ_REG(hw, E1000_PBA); 1444 } else if (hw->mac.type == e1000_ich8lan) { 1445 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1446 } else if (hw->mac.type == e1000_ich9lan) { 1447 pba = E1000_PBA_10K; 1448 } else if (hw->mac.type == e1000_ich10lan) { 1449 pba = E1000_PBA_10K; 1450 } else if (hw->mac.type == e1000_pchlan) { 1451 pba = E1000_PBA_26K; 1452 } else if (hw->mac.type == e1000_pch2lan) { 1453 pba = E1000_PBA_26K; 1454 } else { 1455 /* 1456 * Total FIFO is 40K 1457 */ 1458 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1459 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1460 else 1461 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1462 } 1463 E1000_WRITE_REG(hw, E1000_PBA, pba); 1464 1465 /* 1466 * These parameters set thresholds for the adapter's generation(Tx) 1467 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1468 * settings. Flow control is enabled or disabled in the configuration 1469 * file. 1470 * High-water mark is set down from the top of the rx fifo (not 1471 * sensitive to max_frame_size) and low-water is set just below 1472 * high-water mark. 1473 * The high water mark must be low enough to fit one full frame above 1474 * it in the rx FIFO. Should be the lower of: 1475 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1476 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1477 * Rx FIFO size minus one full frame. 1478 */ 1479 high_water = min(((pba << 10) * 9 / 10), 1480 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1481 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1482 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1483 ((pba << 10) - Adapter->max_frame_size))); 1484 1485 hw->fc.high_water = high_water & 0xFFF8; 1486 hw->fc.low_water = hw->fc.high_water - 8; 1487 1488 if (hw->mac.type == e1000_80003es2lan) 1489 hw->fc.pause_time = 0xFFFF; 1490 else 1491 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1492 hw->fc.send_xon = B_TRUE; 1493 1494 /* 1495 * Reset the adapter hardware the second time. 1496 */ 1497 mutex_enter(&e1000g_nvm_lock); 1498 result = e1000_reset_hw(hw); 1499 mutex_exit(&e1000g_nvm_lock); 1500 1501 if (result != E1000_SUCCESS) { 1502 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1503 goto init_fail; 1504 } 1505 1506 /* disable wakeup control by default */ 1507 if (hw->mac.type >= e1000_82544) 1508 E1000_WRITE_REG(hw, E1000_WUC, 0); 1509 1510 /* 1511 * MWI should be disabled on 82546. 1512 */ 1513 if (hw->mac.type == e1000_82546) 1514 e1000_pci_clear_mwi(hw); 1515 else 1516 e1000_pci_set_mwi(hw); 1517 1518 /* 1519 * Configure/Initialize hardware 1520 */ 1521 mutex_enter(&e1000g_nvm_lock); 1522 result = e1000_init_hw(hw); 1523 mutex_exit(&e1000g_nvm_lock); 1524 1525 if (result < E1000_SUCCESS) { 1526 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1527 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1528 goto init_fail; 1529 } 1530 1531 /* 1532 * Restore LED settings to the default from EEPROM 1533 * to meet the standard for Sun platforms. 1534 */ 1535 (void) e1000_cleanup_led(hw); 1536 1537 /* Disable Smart Power Down */ 1538 phy_spd_state(hw, B_FALSE); 1539 1540 /* Make sure driver has control */ 1541 e1000g_get_driver_control(hw); 1542 1543 /* 1544 * Initialize unicast addresses. 1545 */ 1546 e1000g_init_unicst(Adapter); 1547 1548 /* 1549 * Setup and initialize the mctable structures. After this routine 1550 * completes Multicast table will be set 1551 */ 1552 e1000_update_mc_addr_list(hw, 1553 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1554 msec_delay(5); 1555 1556 /* 1557 * Implement Adaptive IFS 1558 */ 1559 e1000_reset_adaptive(hw); 1560 1561 /* Setup Interrupt Throttling Register */ 1562 if (hw->mac.type >= e1000_82540) { 1563 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1564 } else 1565 Adapter->intr_adaptive = B_FALSE; 1566 1567 /* Start the timer for link setup */ 1568 if (hw->mac.autoneg) 1569 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1570 else 1571 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1572 1573 mutex_enter(&Adapter->link_lock); 1574 if (hw->phy.autoneg_wait_to_complete) { 1575 Adapter->link_complete = B_TRUE; 1576 } else { 1577 Adapter->link_complete = B_FALSE; 1578 Adapter->link_tid = timeout(e1000g_link_timer, 1579 (void *)Adapter, link_timeout); 1580 } 1581 mutex_exit(&Adapter->link_lock); 1582 1583 /* Save the state of the phy */ 1584 e1000g_get_phy_state(Adapter); 1585 1586 e1000g_param_sync(Adapter); 1587 1588 Adapter->init_count++; 1589 1590 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1591 goto init_fail; 1592 } 1593 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1594 goto init_fail; 1595 } 1596 1597 Adapter->poll_mode = e1000g_poll_mode; 1598 1599 return (DDI_SUCCESS); 1600 1601 init_fail: 1602 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1603 return (DDI_FAILURE); 1604 } 1605 1606 static int 1607 e1000g_alloc_rx_data(struct e1000g *Adapter) 1608 { 1609 e1000g_rx_ring_t *rx_ring; 1610 e1000g_rx_data_t *rx_data; 1611 1612 rx_ring = Adapter->rx_ring; 1613 1614 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1615 1616 if (rx_data == NULL) 1617 return (DDI_FAILURE); 1618 1619 rx_data->priv_devi_node = Adapter->priv_devi_node; 1620 rx_data->rx_ring = rx_ring; 1621 1622 mutex_init(&rx_data->freelist_lock, NULL, 1623 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1624 mutex_init(&rx_data->recycle_lock, NULL, 1625 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1626 1627 rx_ring->rx_data = rx_data; 1628 1629 return (DDI_SUCCESS); 1630 } 1631 1632 void 1633 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1634 { 1635 rx_sw_packet_t *packet, *next_packet; 1636 1637 if (rx_data == NULL) 1638 return; 1639 1640 packet = rx_data->packet_area; 1641 while (packet != NULL) { 1642 next_packet = packet->next; 1643 e1000g_free_rx_sw_packet(packet, B_TRUE); 1644 packet = next_packet; 1645 } 1646 rx_data->packet_area = NULL; 1647 } 1648 1649 void 1650 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1651 { 1652 if (rx_data == NULL) 1653 return; 1654 1655 mutex_destroy(&rx_data->freelist_lock); 1656 mutex_destroy(&rx_data->recycle_lock); 1657 1658 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1659 } 1660 1661 /* 1662 * Check if the link is up 1663 */ 1664 static boolean_t 1665 e1000g_link_up(struct e1000g *Adapter) 1666 { 1667 struct e1000_hw *hw = &Adapter->shared; 1668 boolean_t link_up = B_FALSE; 1669 1670 /* 1671 * get_link_status is set in the interrupt handler on link-status-change 1672 * or rx sequence error interrupt. get_link_status will stay 1673 * false until the e1000_check_for_link establishes link only 1674 * for copper adapters. 1675 */ 1676 switch (hw->phy.media_type) { 1677 case e1000_media_type_copper: 1678 if (hw->mac.get_link_status) { 1679 (void) e1000_check_for_link(hw); 1680 if ((E1000_READ_REG(hw, E1000_STATUS) & 1681 E1000_STATUS_LU)) { 1682 link_up = B_TRUE; 1683 } else { 1684 link_up = !hw->mac.get_link_status; 1685 } 1686 } else { 1687 link_up = B_TRUE; 1688 } 1689 break; 1690 case e1000_media_type_fiber: 1691 (void) e1000_check_for_link(hw); 1692 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1693 E1000_STATUS_LU); 1694 break; 1695 case e1000_media_type_internal_serdes: 1696 (void) e1000_check_for_link(hw); 1697 link_up = hw->mac.serdes_has_link; 1698 break; 1699 } 1700 1701 return (link_up); 1702 } 1703 1704 static void 1705 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1706 { 1707 struct iocblk *iocp; 1708 struct e1000g *e1000gp; 1709 enum ioc_reply status; 1710 1711 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1712 iocp->ioc_error = 0; 1713 e1000gp = (struct e1000g *)arg; 1714 1715 ASSERT(e1000gp); 1716 if (e1000gp == NULL) { 1717 miocnak(q, mp, 0, EINVAL); 1718 return; 1719 } 1720 1721 rw_enter(&e1000gp->chip_lock, RW_READER); 1722 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1723 rw_exit(&e1000gp->chip_lock); 1724 miocnak(q, mp, 0, EINVAL); 1725 return; 1726 } 1727 rw_exit(&e1000gp->chip_lock); 1728 1729 switch (iocp->ioc_cmd) { 1730 1731 case LB_GET_INFO_SIZE: 1732 case LB_GET_INFO: 1733 case LB_GET_MODE: 1734 case LB_SET_MODE: 1735 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1736 break; 1737 1738 1739 #ifdef E1000G_DEBUG 1740 case E1000G_IOC_REG_PEEK: 1741 case E1000G_IOC_REG_POKE: 1742 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1743 break; 1744 case E1000G_IOC_CHIP_RESET: 1745 e1000gp->reset_count++; 1746 if (e1000g_reset_adapter(e1000gp)) 1747 status = IOC_ACK; 1748 else 1749 status = IOC_INVAL; 1750 break; 1751 #endif 1752 default: 1753 status = IOC_INVAL; 1754 break; 1755 } 1756 1757 /* 1758 * Decide how to reply 1759 */ 1760 switch (status) { 1761 default: 1762 case IOC_INVAL: 1763 /* 1764 * Error, reply with a NAK and EINVAL or the specified error 1765 */ 1766 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1767 EINVAL : iocp->ioc_error); 1768 break; 1769 1770 case IOC_DONE: 1771 /* 1772 * OK, reply already sent 1773 */ 1774 break; 1775 1776 case IOC_ACK: 1777 /* 1778 * OK, reply with an ACK 1779 */ 1780 miocack(q, mp, 0, 0); 1781 break; 1782 1783 case IOC_REPLY: 1784 /* 1785 * OK, send prepared reply as ACK or NAK 1786 */ 1787 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1788 M_IOCACK : M_IOCNAK; 1789 qreply(q, mp); 1790 break; 1791 } 1792 } 1793 1794 /* 1795 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1796 * capable of supporting only one interrupt and we shouldn't disable 1797 * the physical interrupt. In this case we let the interrupt come and 1798 * we queue the packets in the rx ring itself in case we are in polling 1799 * mode (better latency but slightly lower performance and a very 1800 * high intrrupt count in mpstat which is harmless). 1801 * 1802 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1803 * which can be disabled in poll mode. This gives better overall 1804 * throughput (compared to the mode above), shows very low interrupt 1805 * count but has slightly higher latency since we pick the packets when 1806 * the poll thread does polling. 1807 * 1808 * Currently, this flag should be enabled only while doing performance 1809 * measurement or when it can be guaranteed that entire NIC going 1810 * in poll mode will not harm any traffic like cluster heartbeat etc. 1811 */ 1812 int e1000g_poll_mode = 0; 1813 1814 /* 1815 * Called from the upper layers when driver is in polling mode to 1816 * pick up any queued packets. Care should be taken to not block 1817 * this thread. 1818 */ 1819 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1820 { 1821 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1822 mblk_t *mp = NULL; 1823 mblk_t *tail; 1824 struct e1000g *adapter; 1825 1826 adapter = rx_ring->adapter; 1827 1828 rw_enter(&adapter->chip_lock, RW_READER); 1829 1830 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1831 rw_exit(&adapter->chip_lock); 1832 return (NULL); 1833 } 1834 1835 mutex_enter(&rx_ring->rx_lock); 1836 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1837 mutex_exit(&rx_ring->rx_lock); 1838 rw_exit(&adapter->chip_lock); 1839 return (mp); 1840 } 1841 1842 static int 1843 e1000g_m_start(void *arg) 1844 { 1845 struct e1000g *Adapter = (struct e1000g *)arg; 1846 1847 rw_enter(&Adapter->chip_lock, RW_WRITER); 1848 1849 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1850 rw_exit(&Adapter->chip_lock); 1851 return (ECANCELED); 1852 } 1853 1854 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1855 rw_exit(&Adapter->chip_lock); 1856 return (ENOTACTIVE); 1857 } 1858 1859 Adapter->e1000g_state |= E1000G_STARTED; 1860 1861 rw_exit(&Adapter->chip_lock); 1862 1863 /* Enable and start the watchdog timer */ 1864 enable_watchdog_timer(Adapter); 1865 1866 return (0); 1867 } 1868 1869 static int 1870 e1000g_start(struct e1000g *Adapter, boolean_t global) 1871 { 1872 e1000g_rx_data_t *rx_data; 1873 1874 if (global) { 1875 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1876 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1877 goto start_fail; 1878 } 1879 1880 /* Allocate dma resources for descriptors and buffers */ 1881 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1882 e1000g_log(Adapter, CE_WARN, 1883 "Alloc DMA resources failed"); 1884 goto start_fail; 1885 } 1886 Adapter->rx_buffer_setup = B_FALSE; 1887 } 1888 1889 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1890 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1891 e1000g_log(Adapter, CE_WARN, 1892 "Adapter initialization failed"); 1893 goto start_fail; 1894 } 1895 } 1896 1897 /* Setup and initialize the transmit structures */ 1898 e1000g_tx_setup(Adapter); 1899 msec_delay(5); 1900 1901 /* Setup and initialize the receive structures */ 1902 e1000g_rx_setup(Adapter); 1903 msec_delay(5); 1904 1905 /* Restore the e1000g promiscuous mode */ 1906 e1000g_restore_promisc(Adapter); 1907 1908 e1000g_mask_interrupt(Adapter); 1909 1910 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1911 1912 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1913 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1914 goto start_fail; 1915 } 1916 1917 return (DDI_SUCCESS); 1918 1919 start_fail: 1920 rx_data = Adapter->rx_ring->rx_data; 1921 1922 if (global) { 1923 e1000g_release_dma_resources(Adapter); 1924 e1000g_free_rx_pending_buffers(rx_data); 1925 e1000g_free_rx_data(rx_data); 1926 } 1927 1928 mutex_enter(&e1000g_nvm_lock); 1929 (void) e1000_reset_hw(&Adapter->shared); 1930 mutex_exit(&e1000g_nvm_lock); 1931 1932 return (DDI_FAILURE); 1933 } 1934 1935 static void 1936 e1000g_m_stop(void *arg) 1937 { 1938 struct e1000g *Adapter = (struct e1000g *)arg; 1939 1940 /* Drain tx sessions */ 1941 (void) e1000g_tx_drain(Adapter); 1942 1943 rw_enter(&Adapter->chip_lock, RW_WRITER); 1944 1945 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1946 rw_exit(&Adapter->chip_lock); 1947 return; 1948 } 1949 Adapter->e1000g_state &= ~E1000G_STARTED; 1950 e1000g_stop(Adapter, B_TRUE); 1951 1952 rw_exit(&Adapter->chip_lock); 1953 1954 /* Disable and stop all the timers */ 1955 disable_watchdog_timer(Adapter); 1956 stop_link_timer(Adapter); 1957 stop_82547_timer(Adapter->tx_ring); 1958 } 1959 1960 static void 1961 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1962 { 1963 private_devi_list_t *devi_node; 1964 e1000g_rx_data_t *rx_data; 1965 int result; 1966 1967 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1968 1969 /* Stop the chip and release pending resources */ 1970 1971 /* Tell firmware driver is no longer in control */ 1972 e1000g_release_driver_control(&Adapter->shared); 1973 1974 e1000g_clear_all_interrupts(Adapter); 1975 1976 mutex_enter(&e1000g_nvm_lock); 1977 result = e1000_reset_hw(&Adapter->shared); 1978 mutex_exit(&e1000g_nvm_lock); 1979 1980 if (result != E1000_SUCCESS) { 1981 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1982 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1983 } 1984 1985 mutex_enter(&Adapter->link_lock); 1986 Adapter->link_complete = B_FALSE; 1987 mutex_exit(&Adapter->link_lock); 1988 1989 /* Release resources still held by the TX descriptors */ 1990 e1000g_tx_clean(Adapter); 1991 1992 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1993 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1994 1995 /* Clean the pending rx jumbo packet fragment */ 1996 e1000g_rx_clean(Adapter); 1997 1998 if (global) { 1999 e1000g_release_dma_resources(Adapter); 2000 2001 mutex_enter(&e1000g_rx_detach_lock); 2002 rx_data = Adapter->rx_ring->rx_data; 2003 rx_data->flag |= E1000G_RX_STOPPED; 2004 2005 if (rx_data->pending_count == 0) { 2006 e1000g_free_rx_pending_buffers(rx_data); 2007 e1000g_free_rx_data(rx_data); 2008 } else { 2009 devi_node = rx_data->priv_devi_node; 2010 if (devi_node != NULL) 2011 atomic_inc_32(&devi_node->pending_rx_count); 2012 else 2013 atomic_inc_32(&Adapter->pending_rx_count); 2014 } 2015 mutex_exit(&e1000g_rx_detach_lock); 2016 } 2017 2018 if (Adapter->link_state != LINK_STATE_UNKNOWN) { 2019 Adapter->link_state = LINK_STATE_UNKNOWN; 2020 if (!Adapter->reset_flag) 2021 mac_link_update(Adapter->mh, Adapter->link_state); 2022 } 2023 } 2024 2025 static void 2026 e1000g_rx_clean(struct e1000g *Adapter) 2027 { 2028 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 2029 2030 if (rx_data == NULL) 2031 return; 2032 2033 if (rx_data->rx_mblk != NULL) { 2034 freemsg(rx_data->rx_mblk); 2035 rx_data->rx_mblk = NULL; 2036 rx_data->rx_mblk_tail = NULL; 2037 rx_data->rx_mblk_len = 0; 2038 } 2039 } 2040 2041 static void 2042 e1000g_tx_clean(struct e1000g *Adapter) 2043 { 2044 e1000g_tx_ring_t *tx_ring; 2045 p_tx_sw_packet_t packet; 2046 mblk_t *mp; 2047 mblk_t *nmp; 2048 uint32_t packet_count; 2049 2050 tx_ring = Adapter->tx_ring; 2051 2052 /* 2053 * Here we don't need to protect the lists using 2054 * the usedlist_lock and freelist_lock, for they 2055 * have been protected by the chip_lock. 2056 */ 2057 mp = NULL; 2058 nmp = NULL; 2059 packet_count = 0; 2060 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 2061 while (packet != NULL) { 2062 if (packet->mp != NULL) { 2063 /* Assemble the message chain */ 2064 if (mp == NULL) { 2065 mp = packet->mp; 2066 nmp = packet->mp; 2067 } else { 2068 nmp->b_next = packet->mp; 2069 nmp = packet->mp; 2070 } 2071 /* Disconnect the message from the sw packet */ 2072 packet->mp = NULL; 2073 } 2074 2075 e1000g_free_tx_swpkt(packet); 2076 packet_count++; 2077 2078 packet = (p_tx_sw_packet_t) 2079 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 2080 } 2081 2082 if (mp != NULL) 2083 freemsgchain(mp); 2084 2085 if (packet_count > 0) { 2086 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 2087 QUEUE_INIT_LIST(&tx_ring->used_list); 2088 2089 /* Setup TX descriptor pointers */ 2090 tx_ring->tbd_next = tx_ring->tbd_first; 2091 tx_ring->tbd_oldest = tx_ring->tbd_first; 2092 2093 /* Setup our HW Tx Head & Tail descriptor pointers */ 2094 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 2095 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 2096 } 2097 } 2098 2099 static boolean_t 2100 e1000g_tx_drain(struct e1000g *Adapter) 2101 { 2102 int i; 2103 boolean_t done; 2104 e1000g_tx_ring_t *tx_ring; 2105 2106 tx_ring = Adapter->tx_ring; 2107 2108 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 2109 for (i = 0; i < TX_DRAIN_TIME; i++) { 2110 mutex_enter(&tx_ring->usedlist_lock); 2111 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 2112 mutex_exit(&tx_ring->usedlist_lock); 2113 2114 if (done) 2115 break; 2116 2117 msec_delay(1); 2118 } 2119 2120 return (done); 2121 } 2122 2123 static boolean_t 2124 e1000g_rx_drain(struct e1000g *Adapter) 2125 { 2126 int i; 2127 boolean_t done; 2128 2129 /* 2130 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2131 */ 2132 for (i = 0; i < RX_DRAIN_TIME; i++) { 2133 done = (Adapter->pending_rx_count == 0); 2134 2135 if (done) 2136 break; 2137 2138 msec_delay(1); 2139 } 2140 2141 return (done); 2142 } 2143 2144 static boolean_t 2145 e1000g_reset_adapter(struct e1000g *Adapter) 2146 { 2147 /* Disable and stop all the timers */ 2148 disable_watchdog_timer(Adapter); 2149 stop_link_timer(Adapter); 2150 stop_82547_timer(Adapter->tx_ring); 2151 2152 rw_enter(&Adapter->chip_lock, RW_WRITER); 2153 2154 if (Adapter->stall_flag) { 2155 Adapter->stall_flag = B_FALSE; 2156 Adapter->reset_flag = B_TRUE; 2157 } 2158 2159 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2160 rw_exit(&Adapter->chip_lock); 2161 return (B_TRUE); 2162 } 2163 2164 e1000g_stop(Adapter, B_FALSE); 2165 2166 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2167 rw_exit(&Adapter->chip_lock); 2168 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2169 return (B_FALSE); 2170 } 2171 2172 rw_exit(&Adapter->chip_lock); 2173 2174 /* Enable and start the watchdog timer */ 2175 enable_watchdog_timer(Adapter); 2176 2177 return (B_TRUE); 2178 } 2179 2180 boolean_t 2181 e1000g_global_reset(struct e1000g *Adapter) 2182 { 2183 /* Disable and stop all the timers */ 2184 disable_watchdog_timer(Adapter); 2185 stop_link_timer(Adapter); 2186 stop_82547_timer(Adapter->tx_ring); 2187 2188 rw_enter(&Adapter->chip_lock, RW_WRITER); 2189 2190 e1000g_stop(Adapter, B_TRUE); 2191 2192 Adapter->init_count = 0; 2193 2194 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2195 rw_exit(&Adapter->chip_lock); 2196 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2197 return (B_FALSE); 2198 } 2199 2200 rw_exit(&Adapter->chip_lock); 2201 2202 /* Enable and start the watchdog timer */ 2203 enable_watchdog_timer(Adapter); 2204 2205 return (B_TRUE); 2206 } 2207 2208 /* 2209 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2210 * 2211 * This interrupt service routine is for PCI-Express adapters. 2212 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2213 * bit is set. 2214 */ 2215 static uint_t 2216 e1000g_intr_pciexpress(caddr_t arg) 2217 { 2218 struct e1000g *Adapter; 2219 uint32_t icr; 2220 2221 Adapter = (struct e1000g *)(uintptr_t)arg; 2222 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2223 2224 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2225 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2226 return (DDI_INTR_CLAIMED); 2227 } 2228 2229 if (icr & E1000_ICR_INT_ASSERTED) { 2230 /* 2231 * E1000_ICR_INT_ASSERTED bit was set: 2232 * Read(Clear) the ICR, claim this interrupt, 2233 * look for work to do. 2234 */ 2235 e1000g_intr_work(Adapter, icr); 2236 return (DDI_INTR_CLAIMED); 2237 } else { 2238 /* 2239 * E1000_ICR_INT_ASSERTED bit was not set: 2240 * Don't claim this interrupt, return immediately. 2241 */ 2242 return (DDI_INTR_UNCLAIMED); 2243 } 2244 } 2245 2246 /* 2247 * e1000g_intr - ISR for PCI/PCI-X chipsets 2248 * 2249 * This interrupt service routine is for PCI/PCI-X adapters. 2250 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2251 * bit is set or not. 2252 */ 2253 static uint_t 2254 e1000g_intr(caddr_t arg) 2255 { 2256 struct e1000g *Adapter; 2257 uint32_t icr; 2258 2259 Adapter = (struct e1000g *)(uintptr_t)arg; 2260 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2261 2262 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2263 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2264 return (DDI_INTR_CLAIMED); 2265 } 2266 2267 if (icr) { 2268 /* 2269 * Any bit was set in ICR: 2270 * Read(Clear) the ICR, claim this interrupt, 2271 * look for work to do. 2272 */ 2273 e1000g_intr_work(Adapter, icr); 2274 return (DDI_INTR_CLAIMED); 2275 } else { 2276 /* 2277 * No bit was set in ICR: 2278 * Don't claim this interrupt, return immediately. 2279 */ 2280 return (DDI_INTR_UNCLAIMED); 2281 } 2282 } 2283 2284 /* 2285 * e1000g_intr_work - actual processing of ISR 2286 * 2287 * Read(clear) the ICR contents and call appropriate interrupt 2288 * processing routines. 2289 */ 2290 static void 2291 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2292 { 2293 struct e1000_hw *hw; 2294 hw = &Adapter->shared; 2295 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2296 2297 Adapter->rx_pkt_cnt = 0; 2298 Adapter->tx_pkt_cnt = 0; 2299 2300 rw_enter(&Adapter->chip_lock, RW_READER); 2301 2302 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2303 rw_exit(&Adapter->chip_lock); 2304 return; 2305 } 2306 /* 2307 * Here we need to check the "e1000g_state" flag within the chip_lock to 2308 * ensure the receive routine will not execute when the adapter is 2309 * being reset. 2310 */ 2311 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2312 rw_exit(&Adapter->chip_lock); 2313 return; 2314 } 2315 2316 if (icr & E1000_ICR_RXT0) { 2317 mblk_t *mp = NULL; 2318 mblk_t *tail = NULL; 2319 e1000g_rx_ring_t *rx_ring; 2320 2321 rx_ring = Adapter->rx_ring; 2322 mutex_enter(&rx_ring->rx_lock); 2323 /* 2324 * Sometimes with legacy interrupts, it possible that 2325 * there is a single interrupt for Rx/Tx. In which 2326 * case, if poll flag is set, we shouldn't really 2327 * be doing Rx processing. 2328 */ 2329 if (!rx_ring->poll_flag) 2330 mp = e1000g_receive(rx_ring, &tail, 2331 E1000G_CHAIN_NO_LIMIT); 2332 mutex_exit(&rx_ring->rx_lock); 2333 rw_exit(&Adapter->chip_lock); 2334 if (mp != NULL) 2335 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2336 mp, rx_ring->ring_gen_num); 2337 } else 2338 rw_exit(&Adapter->chip_lock); 2339 2340 if (icr & E1000_ICR_TXDW) { 2341 if (!Adapter->tx_intr_enable) 2342 e1000g_clear_tx_interrupt(Adapter); 2343 2344 /* Recycle the tx descriptors */ 2345 rw_enter(&Adapter->chip_lock, RW_READER); 2346 (void) e1000g_recycle(tx_ring); 2347 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2348 rw_exit(&Adapter->chip_lock); 2349 2350 if (tx_ring->resched_needed && 2351 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2352 tx_ring->resched_needed = B_FALSE; 2353 mac_tx_update(Adapter->mh); 2354 E1000G_STAT(tx_ring->stat_reschedule); 2355 } 2356 } 2357 2358 /* 2359 * The Receive Sequence errors RXSEQ and the link status change LSC 2360 * are checked to detect that the cable has been pulled out. For 2361 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2362 * are an indication that cable is not connected. 2363 */ 2364 if ((icr & E1000_ICR_RXSEQ) || 2365 (icr & E1000_ICR_LSC) || 2366 (icr & E1000_ICR_GPI_EN1)) { 2367 boolean_t link_changed; 2368 timeout_id_t tid = 0; 2369 2370 stop_watchdog_timer(Adapter); 2371 2372 rw_enter(&Adapter->chip_lock, RW_WRITER); 2373 2374 /* 2375 * Because we got a link-status-change interrupt, force 2376 * e1000_check_for_link() to look at phy 2377 */ 2378 Adapter->shared.mac.get_link_status = B_TRUE; 2379 2380 /* e1000g_link_check takes care of link status change */ 2381 link_changed = e1000g_link_check(Adapter); 2382 2383 /* Get new phy state */ 2384 e1000g_get_phy_state(Adapter); 2385 2386 /* 2387 * If the link timer has not timed out, we'll not notify 2388 * the upper layer with any link state until the link is up. 2389 */ 2390 if (link_changed && !Adapter->link_complete) { 2391 if (Adapter->link_state == LINK_STATE_UP) { 2392 mutex_enter(&Adapter->link_lock); 2393 Adapter->link_complete = B_TRUE; 2394 tid = Adapter->link_tid; 2395 Adapter->link_tid = 0; 2396 mutex_exit(&Adapter->link_lock); 2397 } else { 2398 link_changed = B_FALSE; 2399 } 2400 } 2401 rw_exit(&Adapter->chip_lock); 2402 2403 if (link_changed) { 2404 if (tid != 0) 2405 (void) untimeout(tid); 2406 2407 /* 2408 * Workaround for esb2. Data stuck in fifo on a link 2409 * down event. Stop receiver here and reset in watchdog. 2410 */ 2411 if ((Adapter->link_state == LINK_STATE_DOWN) && 2412 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2413 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2414 E1000_WRITE_REG(hw, E1000_RCTL, 2415 rctl & ~E1000_RCTL_EN); 2416 e1000g_log(Adapter, CE_WARN, 2417 "ESB2 receiver disabled"); 2418 Adapter->esb2_workaround = B_TRUE; 2419 } 2420 if (!Adapter->reset_flag) 2421 mac_link_update(Adapter->mh, 2422 Adapter->link_state); 2423 if (Adapter->link_state == LINK_STATE_UP) 2424 Adapter->reset_flag = B_FALSE; 2425 } 2426 2427 start_watchdog_timer(Adapter); 2428 } 2429 } 2430 2431 static void 2432 e1000g_init_unicst(struct e1000g *Adapter) 2433 { 2434 struct e1000_hw *hw; 2435 int slot; 2436 2437 hw = &Adapter->shared; 2438 2439 if (Adapter->init_count == 0) { 2440 /* Initialize the multiple unicast addresses */ 2441 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2442 2443 /* Workaround for an erratum of 82571 chipst */ 2444 if ((hw->mac.type == e1000_82571) && 2445 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2446 Adapter->unicst_total--; 2447 2448 /* VMware doesn't support multiple mac addresses properly */ 2449 if (hw->subsystem_vendor_id == 0x15ad) 2450 Adapter->unicst_total = 1; 2451 2452 Adapter->unicst_avail = Adapter->unicst_total; 2453 2454 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2455 /* Clear both the flag and MAC address */ 2456 Adapter->unicst_addr[slot].reg.high = 0; 2457 Adapter->unicst_addr[slot].reg.low = 0; 2458 } 2459 } else { 2460 /* Workaround for an erratum of 82571 chipst */ 2461 if ((hw->mac.type == e1000_82571) && 2462 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2463 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2464 2465 /* Re-configure the RAR registers */ 2466 for (slot = 0; slot < Adapter->unicst_total; slot++) 2467 if (Adapter->unicst_addr[slot].mac.set == 1) 2468 e1000_rar_set(hw, 2469 Adapter->unicst_addr[slot].mac.addr, slot); 2470 } 2471 2472 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2473 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2474 } 2475 2476 static int 2477 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2478 int slot) 2479 { 2480 struct e1000_hw *hw; 2481 2482 hw = &Adapter->shared; 2483 2484 /* 2485 * The first revision of Wiseman silicon (rev 2.0) has an errata 2486 * that requires the receiver to be in reset when any of the 2487 * receive address registers (RAR regs) are accessed. The first 2488 * rev of Wiseman silicon also requires MWI to be disabled when 2489 * a global reset or a receive reset is issued. So before we 2490 * initialize the RARs, we check the rev of the Wiseman controller 2491 * and work around any necessary HW errata. 2492 */ 2493 if ((hw->mac.type == e1000_82542) && 2494 (hw->revision_id == E1000_REVISION_2)) { 2495 e1000_pci_clear_mwi(hw); 2496 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2497 msec_delay(5); 2498 } 2499 if (mac_addr == NULL) { 2500 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2501 E1000_WRITE_FLUSH(hw); 2502 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2503 E1000_WRITE_FLUSH(hw); 2504 /* Clear both the flag and MAC address */ 2505 Adapter->unicst_addr[slot].reg.high = 0; 2506 Adapter->unicst_addr[slot].reg.low = 0; 2507 } else { 2508 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2509 ETHERADDRL); 2510 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2511 Adapter->unicst_addr[slot].mac.set = 1; 2512 } 2513 2514 /* Workaround for an erratum of 82571 chipst */ 2515 if (slot == 0) { 2516 if ((hw->mac.type == e1000_82571) && 2517 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2518 if (mac_addr == NULL) { 2519 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2520 slot << 1, 0); 2521 E1000_WRITE_FLUSH(hw); 2522 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2523 (slot << 1) + 1, 0); 2524 E1000_WRITE_FLUSH(hw); 2525 } else { 2526 e1000_rar_set(hw, (uint8_t *)mac_addr, 2527 LAST_RAR_ENTRY); 2528 } 2529 } 2530 2531 /* 2532 * If we are using Wiseman rev 2.0 silicon, we will have previously 2533 * put the receive in reset, and disabled MWI, to work around some 2534 * HW errata. Now we should take the receiver out of reset, and 2535 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2536 */ 2537 if ((hw->mac.type == e1000_82542) && 2538 (hw->revision_id == E1000_REVISION_2)) { 2539 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2540 msec_delay(1); 2541 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2542 e1000_pci_set_mwi(hw); 2543 e1000g_rx_setup(Adapter); 2544 } 2545 2546 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2547 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2548 return (EIO); 2549 } 2550 2551 return (0); 2552 } 2553 2554 static int 2555 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2556 { 2557 struct e1000_hw *hw = &Adapter->shared; 2558 struct ether_addr *newtable; 2559 size_t new_len; 2560 size_t old_len; 2561 int res = 0; 2562 2563 if ((multiaddr[0] & 01) == 0) { 2564 res = EINVAL; 2565 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2566 goto done; 2567 } 2568 2569 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2570 res = ENOENT; 2571 e1000g_log(Adapter, CE_WARN, 2572 "Adapter requested more than %d mcast addresses", 2573 Adapter->mcast_max_num); 2574 goto done; 2575 } 2576 2577 2578 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2579 old_len = Adapter->mcast_alloc_count * 2580 sizeof (struct ether_addr); 2581 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2582 sizeof (struct ether_addr); 2583 2584 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2585 if (newtable == NULL) { 2586 res = ENOMEM; 2587 e1000g_log(Adapter, CE_WARN, 2588 "Not enough memory to alloc mcast table"); 2589 goto done; 2590 } 2591 2592 if (Adapter->mcast_table != NULL) { 2593 bcopy(Adapter->mcast_table, newtable, old_len); 2594 kmem_free(Adapter->mcast_table, old_len); 2595 } 2596 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2597 Adapter->mcast_table = newtable; 2598 } 2599 2600 bcopy(multiaddr, 2601 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2602 Adapter->mcast_count++; 2603 2604 /* 2605 * Update the MC table in the hardware 2606 */ 2607 e1000g_clear_interrupt(Adapter); 2608 2609 e1000_update_mc_addr_list(hw, 2610 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2611 2612 e1000g_mask_interrupt(Adapter); 2613 2614 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2615 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2616 res = EIO; 2617 } 2618 2619 done: 2620 return (res); 2621 } 2622 2623 static int 2624 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2625 { 2626 struct e1000_hw *hw = &Adapter->shared; 2627 struct ether_addr *newtable; 2628 size_t new_len; 2629 size_t old_len; 2630 unsigned i; 2631 2632 for (i = 0; i < Adapter->mcast_count; i++) { 2633 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2634 ETHERADDRL) == 0) { 2635 for (i++; i < Adapter->mcast_count; i++) { 2636 Adapter->mcast_table[i - 1] = 2637 Adapter->mcast_table[i]; 2638 } 2639 Adapter->mcast_count--; 2640 break; 2641 } 2642 } 2643 2644 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2645 MCAST_ALLOC_SIZE) { 2646 old_len = Adapter->mcast_alloc_count * 2647 sizeof (struct ether_addr); 2648 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2649 sizeof (struct ether_addr); 2650 2651 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2652 if (newtable != NULL) { 2653 bcopy(Adapter->mcast_table, newtable, new_len); 2654 kmem_free(Adapter->mcast_table, old_len); 2655 2656 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2657 Adapter->mcast_table = newtable; 2658 } 2659 } 2660 2661 /* 2662 * Update the MC table in the hardware 2663 */ 2664 e1000g_clear_interrupt(Adapter); 2665 2666 e1000_update_mc_addr_list(hw, 2667 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2668 2669 e1000g_mask_interrupt(Adapter); 2670 2671 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2672 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2673 return (EIO); 2674 } 2675 2676 return (0); 2677 } 2678 2679 static void 2680 e1000g_release_multicast(struct e1000g *Adapter) 2681 { 2682 if (Adapter->mcast_table != NULL) { 2683 kmem_free(Adapter->mcast_table, 2684 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2685 Adapter->mcast_table = NULL; 2686 } 2687 } 2688 2689 int 2690 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2691 { 2692 struct e1000g *Adapter = (struct e1000g *)arg; 2693 int result; 2694 2695 rw_enter(&Adapter->chip_lock, RW_WRITER); 2696 2697 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2698 result = ECANCELED; 2699 goto done; 2700 } 2701 2702 result = (add) ? multicst_add(Adapter, addr) 2703 : multicst_remove(Adapter, addr); 2704 2705 done: 2706 rw_exit(&Adapter->chip_lock); 2707 return (result); 2708 2709 } 2710 2711 int 2712 e1000g_m_promisc(void *arg, boolean_t on) 2713 { 2714 struct e1000g *Adapter = (struct e1000g *)arg; 2715 uint32_t rctl; 2716 2717 rw_enter(&Adapter->chip_lock, RW_WRITER); 2718 2719 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2720 rw_exit(&Adapter->chip_lock); 2721 return (ECANCELED); 2722 } 2723 2724 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2725 2726 if (on) 2727 rctl |= 2728 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2729 else 2730 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2731 2732 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2733 2734 Adapter->e1000g_promisc = on; 2735 2736 rw_exit(&Adapter->chip_lock); 2737 2738 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2739 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2740 return (EIO); 2741 } 2742 2743 return (0); 2744 } 2745 2746 /* 2747 * Entry points to enable and disable interrupts at the granularity of 2748 * a group. 2749 * Turns the poll_mode for the whole adapter on and off to enable or 2750 * override the ring level polling control over the hardware interrupts. 2751 */ 2752 static int 2753 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2754 { 2755 struct e1000g *adapter = (struct e1000g *)arg; 2756 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2757 2758 /* 2759 * Later interrupts at the granularity of the this ring will 2760 * invoke mac_rx() with NULL, indicating the need for another 2761 * software classification. 2762 * We have a single ring usable per adapter now, so we only need to 2763 * reset the rx handle for that one. 2764 * When more RX rings can be used, we should update each one of them. 2765 */ 2766 mutex_enter(&rx_ring->rx_lock); 2767 rx_ring->mrh = NULL; 2768 adapter->poll_mode = B_FALSE; 2769 mutex_exit(&rx_ring->rx_lock); 2770 return (0); 2771 } 2772 2773 static int 2774 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2775 { 2776 struct e1000g *adapter = (struct e1000g *)arg; 2777 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2778 2779 mutex_enter(&rx_ring->rx_lock); 2780 2781 /* 2782 * Later interrupts at the granularity of the this ring will 2783 * invoke mac_rx() with the handle for this ring; 2784 */ 2785 adapter->poll_mode = B_TRUE; 2786 rx_ring->mrh = rx_ring->mrh_init; 2787 mutex_exit(&rx_ring->rx_lock); 2788 return (0); 2789 } 2790 2791 /* 2792 * Entry points to enable and disable interrupts at the granularity of 2793 * a ring. 2794 * adapter poll_mode controls whether we actually proceed with hardware 2795 * interrupt toggling. 2796 */ 2797 static int 2798 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2799 { 2800 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2801 struct e1000g *adapter = rx_ring->adapter; 2802 struct e1000_hw *hw = &adapter->shared; 2803 uint32_t intr_mask; 2804 2805 rw_enter(&adapter->chip_lock, RW_READER); 2806 2807 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2808 rw_exit(&adapter->chip_lock); 2809 return (0); 2810 } 2811 2812 mutex_enter(&rx_ring->rx_lock); 2813 rx_ring->poll_flag = 0; 2814 mutex_exit(&rx_ring->rx_lock); 2815 2816 /* Rx interrupt enabling for MSI and legacy */ 2817 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2818 intr_mask |= E1000_IMS_RXT0; 2819 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2820 E1000_WRITE_FLUSH(hw); 2821 2822 /* Trigger a Rx interrupt to check Rx ring */ 2823 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2824 E1000_WRITE_FLUSH(hw); 2825 2826 rw_exit(&adapter->chip_lock); 2827 return (0); 2828 } 2829 2830 static int 2831 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2832 { 2833 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2834 struct e1000g *adapter = rx_ring->adapter; 2835 struct e1000_hw *hw = &adapter->shared; 2836 2837 rw_enter(&adapter->chip_lock, RW_READER); 2838 2839 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2840 rw_exit(&adapter->chip_lock); 2841 return (0); 2842 } 2843 mutex_enter(&rx_ring->rx_lock); 2844 rx_ring->poll_flag = 1; 2845 mutex_exit(&rx_ring->rx_lock); 2846 2847 /* Rx interrupt disabling for MSI and legacy */ 2848 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2849 E1000_WRITE_FLUSH(hw); 2850 2851 rw_exit(&adapter->chip_lock); 2852 return (0); 2853 } 2854 2855 /* 2856 * e1000g_unicst_find - Find the slot for the specified unicast address 2857 */ 2858 static int 2859 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2860 { 2861 int slot; 2862 2863 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2864 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2865 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2866 mac_addr, ETHERADDRL) == 0)) 2867 return (slot); 2868 } 2869 2870 return (-1); 2871 } 2872 2873 /* 2874 * Entry points to add and remove a MAC address to a ring group. 2875 * The caller takes care of adding and removing the MAC addresses 2876 * to the filter via these two routines. 2877 */ 2878 2879 static int 2880 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2881 { 2882 struct e1000g *Adapter = (struct e1000g *)arg; 2883 int slot, err; 2884 2885 rw_enter(&Adapter->chip_lock, RW_WRITER); 2886 2887 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2888 rw_exit(&Adapter->chip_lock); 2889 return (ECANCELED); 2890 } 2891 2892 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2893 /* The same address is already in slot */ 2894 rw_exit(&Adapter->chip_lock); 2895 return (0); 2896 } 2897 2898 if (Adapter->unicst_avail == 0) { 2899 /* no slots available */ 2900 rw_exit(&Adapter->chip_lock); 2901 return (ENOSPC); 2902 } 2903 2904 /* Search for a free slot */ 2905 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2906 if (Adapter->unicst_addr[slot].mac.set == 0) 2907 break; 2908 } 2909 ASSERT(slot < Adapter->unicst_total); 2910 2911 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2912 if (err == 0) 2913 Adapter->unicst_avail--; 2914 2915 rw_exit(&Adapter->chip_lock); 2916 2917 return (err); 2918 } 2919 2920 static int 2921 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2922 { 2923 struct e1000g *Adapter = (struct e1000g *)arg; 2924 int slot, err; 2925 2926 rw_enter(&Adapter->chip_lock, RW_WRITER); 2927 2928 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2929 rw_exit(&Adapter->chip_lock); 2930 return (ECANCELED); 2931 } 2932 2933 slot = e1000g_unicst_find(Adapter, mac_addr); 2934 if (slot == -1) { 2935 rw_exit(&Adapter->chip_lock); 2936 return (EINVAL); 2937 } 2938 2939 ASSERT(Adapter->unicst_addr[slot].mac.set); 2940 2941 /* Clear this slot */ 2942 err = e1000g_unicst_set(Adapter, NULL, slot); 2943 if (err == 0) 2944 Adapter->unicst_avail++; 2945 2946 rw_exit(&Adapter->chip_lock); 2947 2948 return (err); 2949 } 2950 2951 static int 2952 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2953 { 2954 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2955 2956 mutex_enter(&rx_ring->rx_lock); 2957 rx_ring->ring_gen_num = mr_gen_num; 2958 mutex_exit(&rx_ring->rx_lock); 2959 return (0); 2960 } 2961 2962 /* 2963 * Callback funtion for MAC layer to register all rings. 2964 * 2965 * The hardware supports a single group with currently only one ring 2966 * available. 2967 * Though not offering virtualization ability per se, exposing the 2968 * group/ring still enables the polling and interrupt toggling. 2969 */ 2970 /* ARGSUSED */ 2971 void 2972 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2973 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2974 { 2975 struct e1000g *Adapter = (struct e1000g *)arg; 2976 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2977 mac_intr_t *mintr; 2978 2979 /* 2980 * We advertised only RX group/rings, so the MAC framework shouldn't 2981 * ask for any thing else. 2982 */ 2983 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2984 2985 rx_ring->mrh = rx_ring->mrh_init = rh; 2986 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2987 infop->mri_start = e1000g_ring_start; 2988 infop->mri_stop = NULL; 2989 infop->mri_poll = e1000g_poll_ring; 2990 infop->mri_stat = e1000g_rx_ring_stat; 2991 2992 /* Ring level interrupts */ 2993 mintr = &infop->mri_intr; 2994 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2995 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2996 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2997 if (Adapter->msi_enable) 2998 mintr->mi_ddi_handle = Adapter->htable[0]; 2999 } 3000 3001 /* ARGSUSED */ 3002 static void 3003 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 3004 mac_group_info_t *infop, mac_group_handle_t gh) 3005 { 3006 struct e1000g *Adapter = (struct e1000g *)arg; 3007 mac_intr_t *mintr; 3008 3009 /* 3010 * We advertised a single RX ring. Getting a request for anything else 3011 * signifies a bug in the MAC framework. 3012 */ 3013 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 3014 3015 Adapter->rx_group = gh; 3016 3017 infop->mgi_driver = (mac_group_driver_t)Adapter; 3018 infop->mgi_start = NULL; 3019 infop->mgi_stop = NULL; 3020 infop->mgi_addmac = e1000g_addmac; 3021 infop->mgi_remmac = e1000g_remmac; 3022 infop->mgi_count = 1; 3023 3024 /* Group level interrupts */ 3025 mintr = &infop->mgi_intr; 3026 mintr->mi_handle = (mac_intr_handle_t)Adapter; 3027 mintr->mi_enable = e1000g_rx_group_intr_enable; 3028 mintr->mi_disable = e1000g_rx_group_intr_disable; 3029 } 3030 3031 static boolean_t 3032 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 3033 { 3034 struct e1000g *Adapter = (struct e1000g *)arg; 3035 3036 switch (cap) { 3037 case MAC_CAPAB_HCKSUM: { 3038 uint32_t *txflags = cap_data; 3039 3040 if (Adapter->tx_hcksum_enable) 3041 *txflags = HCKSUM_IPHDRCKSUM | 3042 HCKSUM_INET_PARTIAL; 3043 else 3044 return (B_FALSE); 3045 break; 3046 } 3047 3048 case MAC_CAPAB_LSO: { 3049 mac_capab_lso_t *cap_lso = cap_data; 3050 3051 if (Adapter->lso_enable) { 3052 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 3053 cap_lso->lso_basic_tcp_ipv4.lso_max = 3054 E1000_LSO_MAXLEN; 3055 } else 3056 return (B_FALSE); 3057 break; 3058 } 3059 case MAC_CAPAB_RINGS: { 3060 mac_capab_rings_t *cap_rings = cap_data; 3061 3062 /* No TX rings exposed yet */ 3063 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 3064 return (B_FALSE); 3065 3066 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 3067 cap_rings->mr_rnum = 1; 3068 cap_rings->mr_gnum = 1; 3069 cap_rings->mr_rget = e1000g_fill_ring; 3070 cap_rings->mr_gget = e1000g_fill_group; 3071 break; 3072 } 3073 default: 3074 return (B_FALSE); 3075 } 3076 return (B_TRUE); 3077 } 3078 3079 static boolean_t 3080 e1000g_param_locked(mac_prop_id_t pr_num) 3081 { 3082 /* 3083 * All en_* parameters are locked (read-only) while 3084 * the device is in any sort of loopback mode ... 3085 */ 3086 switch (pr_num) { 3087 case MAC_PROP_EN_1000FDX_CAP: 3088 case MAC_PROP_EN_1000HDX_CAP: 3089 case MAC_PROP_EN_100FDX_CAP: 3090 case MAC_PROP_EN_100HDX_CAP: 3091 case MAC_PROP_EN_10FDX_CAP: 3092 case MAC_PROP_EN_10HDX_CAP: 3093 case MAC_PROP_AUTONEG: 3094 case MAC_PROP_FLOWCTRL: 3095 return (B_TRUE); 3096 } 3097 return (B_FALSE); 3098 } 3099 3100 /* 3101 * callback function for set/get of properties 3102 */ 3103 static int 3104 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3105 uint_t pr_valsize, const void *pr_val) 3106 { 3107 struct e1000g *Adapter = arg; 3108 struct e1000_hw *hw = &Adapter->shared; 3109 struct e1000_fc_info *fc = &Adapter->shared.fc; 3110 int err = 0; 3111 link_flowctrl_t flowctrl; 3112 uint32_t cur_mtu, new_mtu; 3113 3114 rw_enter(&Adapter->chip_lock, RW_WRITER); 3115 3116 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3117 rw_exit(&Adapter->chip_lock); 3118 return (ECANCELED); 3119 } 3120 3121 if (Adapter->loopback_mode != E1000G_LB_NONE && 3122 e1000g_param_locked(pr_num)) { 3123 /* 3124 * All en_* parameters are locked (read-only) 3125 * while the device is in any sort of loopback mode. 3126 */ 3127 rw_exit(&Adapter->chip_lock); 3128 return (EBUSY); 3129 } 3130 3131 switch (pr_num) { 3132 case MAC_PROP_EN_1000FDX_CAP: 3133 if (hw->phy.media_type != e1000_media_type_copper) { 3134 err = ENOTSUP; 3135 break; 3136 } 3137 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3138 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3139 goto reset; 3140 case MAC_PROP_EN_100FDX_CAP: 3141 if (hw->phy.media_type != e1000_media_type_copper) { 3142 err = ENOTSUP; 3143 break; 3144 } 3145 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3146 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3147 goto reset; 3148 case MAC_PROP_EN_100HDX_CAP: 3149 if (hw->phy.media_type != e1000_media_type_copper) { 3150 err = ENOTSUP; 3151 break; 3152 } 3153 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3154 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3155 goto reset; 3156 case MAC_PROP_EN_10FDX_CAP: 3157 if (hw->phy.media_type != e1000_media_type_copper) { 3158 err = ENOTSUP; 3159 break; 3160 } 3161 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3162 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3163 goto reset; 3164 case MAC_PROP_EN_10HDX_CAP: 3165 if (hw->phy.media_type != e1000_media_type_copper) { 3166 err = ENOTSUP; 3167 break; 3168 } 3169 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3170 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3171 goto reset; 3172 case MAC_PROP_AUTONEG: 3173 if (hw->phy.media_type != e1000_media_type_copper) { 3174 err = ENOTSUP; 3175 break; 3176 } 3177 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3178 goto reset; 3179 case MAC_PROP_FLOWCTRL: 3180 fc->send_xon = B_TRUE; 3181 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3182 3183 switch (flowctrl) { 3184 default: 3185 err = EINVAL; 3186 break; 3187 case LINK_FLOWCTRL_NONE: 3188 fc->requested_mode = e1000_fc_none; 3189 break; 3190 case LINK_FLOWCTRL_RX: 3191 fc->requested_mode = e1000_fc_rx_pause; 3192 break; 3193 case LINK_FLOWCTRL_TX: 3194 fc->requested_mode = e1000_fc_tx_pause; 3195 break; 3196 case LINK_FLOWCTRL_BI: 3197 fc->requested_mode = e1000_fc_full; 3198 break; 3199 } 3200 reset: 3201 if (err == 0) { 3202 /* check PCH limits & reset the link */ 3203 e1000g_pch_limits(Adapter); 3204 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3205 err = EINVAL; 3206 } 3207 break; 3208 case MAC_PROP_ADV_1000FDX_CAP: 3209 case MAC_PROP_ADV_1000HDX_CAP: 3210 case MAC_PROP_ADV_100FDX_CAP: 3211 case MAC_PROP_ADV_100HDX_CAP: 3212 case MAC_PROP_ADV_10FDX_CAP: 3213 case MAC_PROP_ADV_10HDX_CAP: 3214 case MAC_PROP_EN_1000HDX_CAP: 3215 case MAC_PROP_STATUS: 3216 case MAC_PROP_SPEED: 3217 case MAC_PROP_DUPLEX: 3218 err = ENOTSUP; /* read-only prop. Can't set this. */ 3219 break; 3220 case MAC_PROP_MTU: 3221 /* adapter must be stopped for an MTU change */ 3222 if (Adapter->e1000g_state & E1000G_STARTED) { 3223 err = EBUSY; 3224 break; 3225 } 3226 3227 cur_mtu = Adapter->default_mtu; 3228 3229 /* get new requested MTU */ 3230 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3231 if (new_mtu == cur_mtu) { 3232 err = 0; 3233 break; 3234 } 3235 3236 if ((new_mtu < DEFAULT_MTU) || 3237 (new_mtu > Adapter->max_mtu)) { 3238 err = EINVAL; 3239 break; 3240 } 3241 3242 /* inform MAC framework of new MTU */ 3243 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3244 3245 if (err == 0) { 3246 Adapter->default_mtu = new_mtu; 3247 Adapter->max_frame_size = 3248 e1000g_mtu2maxframe(new_mtu); 3249 3250 /* 3251 * check PCH limits & set buffer sizes to 3252 * match new MTU 3253 */ 3254 e1000g_pch_limits(Adapter); 3255 e1000g_set_bufsize(Adapter); 3256 3257 /* 3258 * decrease the number of descriptors and free 3259 * packets for jumbo frames to reduce tx/rx 3260 * resource consumption 3261 */ 3262 if (Adapter->max_frame_size >= 3263 (FRAME_SIZE_UPTO_4K)) { 3264 if (Adapter->tx_desc_num_flag == 0) 3265 Adapter->tx_desc_num = 3266 DEFAULT_JUMBO_NUM_TX_DESC; 3267 3268 if (Adapter->rx_desc_num_flag == 0) 3269 Adapter->rx_desc_num = 3270 DEFAULT_JUMBO_NUM_RX_DESC; 3271 3272 if (Adapter->tx_buf_num_flag == 0) 3273 Adapter->tx_freelist_num = 3274 DEFAULT_JUMBO_NUM_TX_BUF; 3275 3276 if (Adapter->rx_buf_num_flag == 0) 3277 Adapter->rx_freelist_limit = 3278 DEFAULT_JUMBO_NUM_RX_BUF; 3279 } else { 3280 if (Adapter->tx_desc_num_flag == 0) 3281 Adapter->tx_desc_num = 3282 DEFAULT_NUM_TX_DESCRIPTOR; 3283 3284 if (Adapter->rx_desc_num_flag == 0) 3285 Adapter->rx_desc_num = 3286 DEFAULT_NUM_RX_DESCRIPTOR; 3287 3288 if (Adapter->tx_buf_num_flag == 0) 3289 Adapter->tx_freelist_num = 3290 DEFAULT_NUM_TX_FREELIST; 3291 3292 if (Adapter->rx_buf_num_flag == 0) 3293 Adapter->rx_freelist_limit = 3294 DEFAULT_NUM_RX_FREELIST; 3295 } 3296 } 3297 break; 3298 case MAC_PROP_PRIVATE: 3299 err = e1000g_set_priv_prop(Adapter, pr_name, 3300 pr_valsize, pr_val); 3301 break; 3302 default: 3303 err = ENOTSUP; 3304 break; 3305 } 3306 rw_exit(&Adapter->chip_lock); 3307 return (err); 3308 } 3309 3310 static int 3311 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3312 uint_t pr_valsize, void *pr_val) 3313 { 3314 struct e1000g *Adapter = arg; 3315 struct e1000_fc_info *fc = &Adapter->shared.fc; 3316 int err = 0; 3317 link_flowctrl_t flowctrl; 3318 uint64_t tmp = 0; 3319 3320 switch (pr_num) { 3321 case MAC_PROP_DUPLEX: 3322 ASSERT(pr_valsize >= sizeof (link_duplex_t)); 3323 bcopy(&Adapter->link_duplex, pr_val, 3324 sizeof (link_duplex_t)); 3325 break; 3326 case MAC_PROP_SPEED: 3327 ASSERT(pr_valsize >= sizeof (uint64_t)); 3328 tmp = Adapter->link_speed * 1000000ull; 3329 bcopy(&tmp, pr_val, sizeof (tmp)); 3330 break; 3331 case MAC_PROP_AUTONEG: 3332 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3333 break; 3334 case MAC_PROP_FLOWCTRL: 3335 ASSERT(pr_valsize >= sizeof (link_flowctrl_t)); 3336 switch (fc->current_mode) { 3337 case e1000_fc_none: 3338 flowctrl = LINK_FLOWCTRL_NONE; 3339 break; 3340 case e1000_fc_rx_pause: 3341 flowctrl = LINK_FLOWCTRL_RX; 3342 break; 3343 case e1000_fc_tx_pause: 3344 flowctrl = LINK_FLOWCTRL_TX; 3345 break; 3346 case e1000_fc_full: 3347 flowctrl = LINK_FLOWCTRL_BI; 3348 break; 3349 } 3350 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3351 break; 3352 case MAC_PROP_ADV_1000FDX_CAP: 3353 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3354 break; 3355 case MAC_PROP_EN_1000FDX_CAP: 3356 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3357 break; 3358 case MAC_PROP_ADV_1000HDX_CAP: 3359 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3360 break; 3361 case MAC_PROP_EN_1000HDX_CAP: 3362 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3363 break; 3364 case MAC_PROP_ADV_100FDX_CAP: 3365 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3366 break; 3367 case MAC_PROP_EN_100FDX_CAP: 3368 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3369 break; 3370 case MAC_PROP_ADV_100HDX_CAP: 3371 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3372 break; 3373 case MAC_PROP_EN_100HDX_CAP: 3374 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3375 break; 3376 case MAC_PROP_ADV_10FDX_CAP: 3377 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3378 break; 3379 case MAC_PROP_EN_10FDX_CAP: 3380 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3381 break; 3382 case MAC_PROP_ADV_10HDX_CAP: 3383 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3384 break; 3385 case MAC_PROP_EN_10HDX_CAP: 3386 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3387 break; 3388 case MAC_PROP_ADV_100T4_CAP: 3389 case MAC_PROP_EN_100T4_CAP: 3390 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3391 break; 3392 case MAC_PROP_PRIVATE: 3393 err = e1000g_get_priv_prop(Adapter, pr_name, 3394 pr_valsize, pr_val); 3395 break; 3396 default: 3397 err = ENOTSUP; 3398 break; 3399 } 3400 3401 return (err); 3402 } 3403 3404 static void 3405 e1000g_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3406 mac_prop_info_handle_t prh) 3407 { 3408 struct e1000g *Adapter = arg; 3409 struct e1000_hw *hw = &Adapter->shared; 3410 3411 switch (pr_num) { 3412 case MAC_PROP_DUPLEX: 3413 case MAC_PROP_SPEED: 3414 case MAC_PROP_ADV_1000FDX_CAP: 3415 case MAC_PROP_ADV_1000HDX_CAP: 3416 case MAC_PROP_ADV_100FDX_CAP: 3417 case MAC_PROP_ADV_100HDX_CAP: 3418 case MAC_PROP_ADV_10FDX_CAP: 3419 case MAC_PROP_ADV_10HDX_CAP: 3420 case MAC_PROP_ADV_100T4_CAP: 3421 case MAC_PROP_EN_100T4_CAP: 3422 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3423 break; 3424 3425 case MAC_PROP_EN_1000FDX_CAP: 3426 if (hw->phy.media_type != e1000_media_type_copper) { 3427 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3428 } else { 3429 mac_prop_info_set_default_uint8(prh, 3430 ((Adapter->phy_ext_status & 3431 IEEE_ESR_1000T_FD_CAPS) || 3432 (Adapter->phy_ext_status & 3433 IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0); 3434 } 3435 break; 3436 3437 case MAC_PROP_EN_100FDX_CAP: 3438 if (hw->phy.media_type != e1000_media_type_copper) { 3439 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3440 } else { 3441 mac_prop_info_set_default_uint8(prh, 3442 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3443 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3444 ? 1 : 0); 3445 } 3446 break; 3447 3448 case MAC_PROP_EN_100HDX_CAP: 3449 if (hw->phy.media_type != e1000_media_type_copper) { 3450 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3451 } else { 3452 mac_prop_info_set_default_uint8(prh, 3453 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 3454 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 3455 ? 1 : 0); 3456 } 3457 break; 3458 3459 case MAC_PROP_EN_10FDX_CAP: 3460 if (hw->phy.media_type != e1000_media_type_copper) { 3461 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3462 } else { 3463 mac_prop_info_set_default_uint8(prh, 3464 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0); 3465 } 3466 break; 3467 3468 case MAC_PROP_EN_10HDX_CAP: 3469 if (hw->phy.media_type != e1000_media_type_copper) { 3470 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3471 } else { 3472 mac_prop_info_set_default_uint8(prh, 3473 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0); 3474 } 3475 break; 3476 3477 case MAC_PROP_EN_1000HDX_CAP: 3478 if (hw->phy.media_type != e1000_media_type_copper) 3479 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3480 break; 3481 3482 case MAC_PROP_AUTONEG: 3483 if (hw->phy.media_type != e1000_media_type_copper) { 3484 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3485 } else { 3486 mac_prop_info_set_default_uint8(prh, 3487 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) 3488 ? 1 : 0); 3489 } 3490 break; 3491 3492 case MAC_PROP_FLOWCTRL: 3493 mac_prop_info_set_default_link_flowctrl(prh, LINK_FLOWCTRL_BI); 3494 break; 3495 3496 case MAC_PROP_MTU: { 3497 struct e1000_mac_info *mac = &Adapter->shared.mac; 3498 struct e1000_phy_info *phy = &Adapter->shared.phy; 3499 uint32_t max; 3500 3501 /* some MAC types do not support jumbo frames */ 3502 if ((mac->type == e1000_ich8lan) || 3503 ((mac->type == e1000_ich9lan) && (phy->type == 3504 e1000_phy_ife))) { 3505 max = DEFAULT_MTU; 3506 } else { 3507 max = Adapter->max_mtu; 3508 } 3509 3510 mac_prop_info_set_range_uint32(prh, DEFAULT_MTU, max); 3511 break; 3512 } 3513 case MAC_PROP_PRIVATE: { 3514 char valstr[64]; 3515 int value; 3516 3517 if (strcmp(pr_name, "_adv_pause_cap") == 0 || 3518 strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3519 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3520 return; 3521 } else if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3522 value = DEFAULT_TX_BCOPY_THRESHOLD; 3523 } else if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3524 value = DEFAULT_TX_INTR_ENABLE; 3525 } else if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3526 value = DEFAULT_TX_INTR_DELAY; 3527 } else if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3528 value = DEFAULT_TX_INTR_ABS_DELAY; 3529 } else if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3530 value = DEFAULT_RX_BCOPY_THRESHOLD; 3531 } else if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3532 value = DEFAULT_RX_LIMIT_ON_INTR; 3533 } else if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3534 value = DEFAULT_RX_INTR_DELAY; 3535 } else if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3536 value = DEFAULT_RX_INTR_ABS_DELAY; 3537 } else if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3538 value = DEFAULT_INTR_THROTTLING; 3539 } else if (strcmp(pr_name, "_intr_adaptive") == 0) { 3540 value = 1; 3541 } else { 3542 return; 3543 } 3544 3545 (void) snprintf(valstr, sizeof (valstr), "%d", value); 3546 mac_prop_info_set_default_str(prh, valstr); 3547 break; 3548 } 3549 } 3550 } 3551 3552 /* ARGSUSED2 */ 3553 static int 3554 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3555 uint_t pr_valsize, const void *pr_val) 3556 { 3557 int err = 0; 3558 long result; 3559 struct e1000_hw *hw = &Adapter->shared; 3560 3561 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3562 if (pr_val == NULL) { 3563 err = EINVAL; 3564 return (err); 3565 } 3566 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3567 if (result < MIN_TX_BCOPY_THRESHOLD || 3568 result > MAX_TX_BCOPY_THRESHOLD) 3569 err = EINVAL; 3570 else { 3571 Adapter->tx_bcopy_thresh = (uint32_t)result; 3572 } 3573 return (err); 3574 } 3575 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3576 if (pr_val == NULL) { 3577 err = EINVAL; 3578 return (err); 3579 } 3580 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3581 if (result < 0 || result > 1) 3582 err = EINVAL; 3583 else { 3584 Adapter->tx_intr_enable = (result == 1) ? 3585 B_TRUE: B_FALSE; 3586 if (Adapter->tx_intr_enable) 3587 e1000g_mask_tx_interrupt(Adapter); 3588 else 3589 e1000g_clear_tx_interrupt(Adapter); 3590 if (e1000g_check_acc_handle( 3591 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3592 ddi_fm_service_impact(Adapter->dip, 3593 DDI_SERVICE_DEGRADED); 3594 err = EIO; 3595 } 3596 } 3597 return (err); 3598 } 3599 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3600 if (pr_val == NULL) { 3601 err = EINVAL; 3602 return (err); 3603 } 3604 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3605 if (result < MIN_TX_INTR_DELAY || 3606 result > MAX_TX_INTR_DELAY) 3607 err = EINVAL; 3608 else { 3609 Adapter->tx_intr_delay = (uint32_t)result; 3610 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3611 if (e1000g_check_acc_handle( 3612 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3613 ddi_fm_service_impact(Adapter->dip, 3614 DDI_SERVICE_DEGRADED); 3615 err = EIO; 3616 } 3617 } 3618 return (err); 3619 } 3620 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3621 if (pr_val == NULL) { 3622 err = EINVAL; 3623 return (err); 3624 } 3625 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3626 if (result < MIN_TX_INTR_ABS_DELAY || 3627 result > MAX_TX_INTR_ABS_DELAY) 3628 err = EINVAL; 3629 else { 3630 Adapter->tx_intr_abs_delay = (uint32_t)result; 3631 E1000_WRITE_REG(hw, E1000_TADV, 3632 Adapter->tx_intr_abs_delay); 3633 if (e1000g_check_acc_handle( 3634 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3635 ddi_fm_service_impact(Adapter->dip, 3636 DDI_SERVICE_DEGRADED); 3637 err = EIO; 3638 } 3639 } 3640 return (err); 3641 } 3642 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3643 if (pr_val == NULL) { 3644 err = EINVAL; 3645 return (err); 3646 } 3647 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3648 if (result < MIN_RX_BCOPY_THRESHOLD || 3649 result > MAX_RX_BCOPY_THRESHOLD) 3650 err = EINVAL; 3651 else 3652 Adapter->rx_bcopy_thresh = (uint32_t)result; 3653 return (err); 3654 } 3655 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3656 if (pr_val == NULL) { 3657 err = EINVAL; 3658 return (err); 3659 } 3660 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3661 if (result < MIN_RX_LIMIT_ON_INTR || 3662 result > MAX_RX_LIMIT_ON_INTR) 3663 err = EINVAL; 3664 else 3665 Adapter->rx_limit_onintr = (uint32_t)result; 3666 return (err); 3667 } 3668 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3669 if (pr_val == NULL) { 3670 err = EINVAL; 3671 return (err); 3672 } 3673 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3674 if (result < MIN_RX_INTR_DELAY || 3675 result > MAX_RX_INTR_DELAY) 3676 err = EINVAL; 3677 else { 3678 Adapter->rx_intr_delay = (uint32_t)result; 3679 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3680 if (e1000g_check_acc_handle( 3681 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3682 ddi_fm_service_impact(Adapter->dip, 3683 DDI_SERVICE_DEGRADED); 3684 err = EIO; 3685 } 3686 } 3687 return (err); 3688 } 3689 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3690 if (pr_val == NULL) { 3691 err = EINVAL; 3692 return (err); 3693 } 3694 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3695 if (result < MIN_RX_INTR_ABS_DELAY || 3696 result > MAX_RX_INTR_ABS_DELAY) 3697 err = EINVAL; 3698 else { 3699 Adapter->rx_intr_abs_delay = (uint32_t)result; 3700 E1000_WRITE_REG(hw, E1000_RADV, 3701 Adapter->rx_intr_abs_delay); 3702 if (e1000g_check_acc_handle( 3703 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3704 ddi_fm_service_impact(Adapter->dip, 3705 DDI_SERVICE_DEGRADED); 3706 err = EIO; 3707 } 3708 } 3709 return (err); 3710 } 3711 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3712 if (pr_val == NULL) { 3713 err = EINVAL; 3714 return (err); 3715 } 3716 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3717 if (result < MIN_INTR_THROTTLING || 3718 result > MAX_INTR_THROTTLING) 3719 err = EINVAL; 3720 else { 3721 if (hw->mac.type >= e1000_82540) { 3722 Adapter->intr_throttling_rate = 3723 (uint32_t)result; 3724 E1000_WRITE_REG(hw, E1000_ITR, 3725 Adapter->intr_throttling_rate); 3726 if (e1000g_check_acc_handle( 3727 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3728 ddi_fm_service_impact(Adapter->dip, 3729 DDI_SERVICE_DEGRADED); 3730 err = EIO; 3731 } 3732 } else 3733 err = EINVAL; 3734 } 3735 return (err); 3736 } 3737 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3738 if (pr_val == NULL) { 3739 err = EINVAL; 3740 return (err); 3741 } 3742 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3743 if (result < 0 || result > 1) 3744 err = EINVAL; 3745 else { 3746 if (hw->mac.type >= e1000_82540) { 3747 Adapter->intr_adaptive = (result == 1) ? 3748 B_TRUE : B_FALSE; 3749 } else { 3750 err = EINVAL; 3751 } 3752 } 3753 return (err); 3754 } 3755 return (ENOTSUP); 3756 } 3757 3758 static int 3759 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3760 uint_t pr_valsize, void *pr_val) 3761 { 3762 int err = ENOTSUP; 3763 int value; 3764 3765 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3766 value = Adapter->param_adv_pause; 3767 err = 0; 3768 goto done; 3769 } 3770 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3771 value = Adapter->param_adv_asym_pause; 3772 err = 0; 3773 goto done; 3774 } 3775 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3776 value = Adapter->tx_bcopy_thresh; 3777 err = 0; 3778 goto done; 3779 } 3780 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3781 value = Adapter->tx_intr_enable; 3782 err = 0; 3783 goto done; 3784 } 3785 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3786 value = Adapter->tx_intr_delay; 3787 err = 0; 3788 goto done; 3789 } 3790 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3791 value = Adapter->tx_intr_abs_delay; 3792 err = 0; 3793 goto done; 3794 } 3795 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3796 value = Adapter->rx_bcopy_thresh; 3797 err = 0; 3798 goto done; 3799 } 3800 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3801 value = Adapter->rx_limit_onintr; 3802 err = 0; 3803 goto done; 3804 } 3805 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3806 value = Adapter->rx_intr_delay; 3807 err = 0; 3808 goto done; 3809 } 3810 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3811 value = Adapter->rx_intr_abs_delay; 3812 err = 0; 3813 goto done; 3814 } 3815 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3816 value = Adapter->intr_throttling_rate; 3817 err = 0; 3818 goto done; 3819 } 3820 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3821 value = Adapter->intr_adaptive; 3822 err = 0; 3823 goto done; 3824 } 3825 done: 3826 if (err == 0) { 3827 (void) snprintf(pr_val, pr_valsize, "%d", value); 3828 } 3829 return (err); 3830 } 3831 3832 /* 3833 * e1000g_get_conf - get configurations set in e1000g.conf 3834 * This routine gets user-configured values out of the configuration 3835 * file e1000g.conf. 3836 * 3837 * For each configurable value, there is a minimum, a maximum, and a 3838 * default. 3839 * If user does not configure a value, use the default. 3840 * If user configures below the minimum, use the minumum. 3841 * If user configures above the maximum, use the maxumum. 3842 */ 3843 static void 3844 e1000g_get_conf(struct e1000g *Adapter) 3845 { 3846 struct e1000_hw *hw = &Adapter->shared; 3847 boolean_t tbi_compatibility = B_FALSE; 3848 boolean_t is_jumbo = B_FALSE; 3849 int propval; 3850 /* 3851 * decrease the number of descriptors and free packets 3852 * for jumbo frames to reduce tx/rx resource consumption 3853 */ 3854 if (Adapter->max_frame_size >= FRAME_SIZE_UPTO_4K) { 3855 is_jumbo = B_TRUE; 3856 } 3857 3858 /* 3859 * get each configurable property from e1000g.conf 3860 */ 3861 3862 /* 3863 * NumTxDescriptors 3864 */ 3865 Adapter->tx_desc_num_flag = 3866 e1000g_get_prop(Adapter, "NumTxDescriptors", 3867 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3868 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 3869 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 3870 Adapter->tx_desc_num = propval; 3871 3872 /* 3873 * NumRxDescriptors 3874 */ 3875 Adapter->rx_desc_num_flag = 3876 e1000g_get_prop(Adapter, "NumRxDescriptors", 3877 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3878 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 3879 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 3880 Adapter->rx_desc_num = propval; 3881 3882 /* 3883 * NumRxFreeList 3884 */ 3885 Adapter->rx_buf_num_flag = 3886 e1000g_get_prop(Adapter, "NumRxFreeList", 3887 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3888 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 3889 : DEFAULT_NUM_RX_FREELIST, &propval); 3890 Adapter->rx_freelist_limit = propval; 3891 3892 /* 3893 * NumTxPacketList 3894 */ 3895 Adapter->tx_buf_num_flag = 3896 e1000g_get_prop(Adapter, "NumTxPacketList", 3897 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3898 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 3899 : DEFAULT_NUM_TX_FREELIST, &propval); 3900 Adapter->tx_freelist_num = propval; 3901 3902 /* 3903 * FlowControl 3904 */ 3905 hw->fc.send_xon = B_TRUE; 3906 (void) e1000g_get_prop(Adapter, "FlowControl", 3907 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 3908 hw->fc.requested_mode = propval; 3909 /* 4 is the setting that says "let the eeprom decide" */ 3910 if (hw->fc.requested_mode == 4) 3911 hw->fc.requested_mode = e1000_fc_default; 3912 3913 /* 3914 * Max Num Receive Packets on Interrupt 3915 */ 3916 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3917 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3918 DEFAULT_RX_LIMIT_ON_INTR, &propval); 3919 Adapter->rx_limit_onintr = propval; 3920 3921 /* 3922 * PHY master slave setting 3923 */ 3924 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 3925 e1000_ms_hw_default, e1000_ms_auto, 3926 e1000_ms_hw_default, &propval); 3927 hw->phy.ms_type = propval; 3928 3929 /* 3930 * Parameter which controls TBI mode workaround, which is only 3931 * needed on certain switches such as Cisco 6500/Foundry 3932 */ 3933 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3934 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 3935 tbi_compatibility = (propval == 1); 3936 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3937 3938 /* 3939 * MSI Enable 3940 */ 3941 (void) e1000g_get_prop(Adapter, "MSIEnable", 3942 0, 1, DEFAULT_MSI_ENABLE, &propval); 3943 Adapter->msi_enable = (propval == 1); 3944 3945 /* 3946 * Interrupt Throttling Rate 3947 */ 3948 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 3949 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3950 DEFAULT_INTR_THROTTLING, &propval); 3951 Adapter->intr_throttling_rate = propval; 3952 3953 /* 3954 * Adaptive Interrupt Blanking Enable/Disable 3955 * It is enabled by default 3956 */ 3957 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 3958 &propval); 3959 Adapter->intr_adaptive = (propval == 1); 3960 3961 /* 3962 * Hardware checksum enable/disable parameter 3963 */ 3964 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 3965 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 3966 Adapter->tx_hcksum_enable = (propval == 1); 3967 /* 3968 * Checksum on/off selection via global parameters. 3969 * 3970 * If the chip is flagged as not capable of (correctly) 3971 * handling checksumming, we don't enable it on either 3972 * Rx or Tx side. Otherwise, we take this chip's settings 3973 * from the patchable global defaults. 3974 * 3975 * We advertise our capabilities only if TX offload is 3976 * enabled. On receive, the stack will accept checksummed 3977 * packets anyway, even if we haven't said we can deliver 3978 * them. 3979 */ 3980 switch (hw->mac.type) { 3981 case e1000_82540: 3982 case e1000_82544: 3983 case e1000_82545: 3984 case e1000_82545_rev_3: 3985 case e1000_82546: 3986 case e1000_82546_rev_3: 3987 case e1000_82571: 3988 case e1000_82572: 3989 case e1000_82573: 3990 case e1000_80003es2lan: 3991 break; 3992 /* 3993 * For the following Intel PRO/1000 chipsets, we have not 3994 * tested the hardware checksum offload capability, so we 3995 * disable the capability for them. 3996 * e1000_82542, 3997 * e1000_82543, 3998 * e1000_82541, 3999 * e1000_82541_rev_2, 4000 * e1000_82547, 4001 * e1000_82547_rev_2, 4002 */ 4003 default: 4004 Adapter->tx_hcksum_enable = B_FALSE; 4005 } 4006 4007 /* 4008 * Large Send Offloading(LSO) Enable/Disable 4009 * If the tx hardware checksum is not enabled, LSO should be 4010 * disabled. 4011 */ 4012 (void) e1000g_get_prop(Adapter, "lso_enable", 4013 0, 1, DEFAULT_LSO_ENABLE, &propval); 4014 Adapter->lso_enable = (propval == 1); 4015 4016 switch (hw->mac.type) { 4017 case e1000_82546: 4018 case e1000_82546_rev_3: 4019 if (Adapter->lso_enable) 4020 Adapter->lso_premature_issue = B_TRUE; 4021 /* FALLTHRU */ 4022 case e1000_82571: 4023 case e1000_82572: 4024 case e1000_82573: 4025 case e1000_80003es2lan: 4026 break; 4027 default: 4028 Adapter->lso_enable = B_FALSE; 4029 } 4030 4031 if (!Adapter->tx_hcksum_enable) { 4032 Adapter->lso_premature_issue = B_FALSE; 4033 Adapter->lso_enable = B_FALSE; 4034 } 4035 4036 /* 4037 * If mem_workaround_82546 is enabled, the rx buffer allocated by 4038 * e1000_82545, e1000_82546 and e1000_82546_rev_3 4039 * will not cross 64k boundary. 4040 */ 4041 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 4042 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 4043 Adapter->mem_workaround_82546 = (propval == 1); 4044 4045 /* 4046 * Max number of multicast addresses 4047 */ 4048 (void) e1000g_get_prop(Adapter, "mcast_max_num", 4049 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 4050 &propval); 4051 Adapter->mcast_max_num = propval; 4052 } 4053 4054 /* 4055 * e1000g_get_prop - routine to read properties 4056 * 4057 * Get a user-configure property value out of the configuration 4058 * file e1000g.conf. 4059 * 4060 * Caller provides name of the property, a default value, a minimum 4061 * value, a maximum value and a pointer to the returned property 4062 * value. 4063 * 4064 * Return B_TRUE if the configured value of the property is not a default 4065 * value, otherwise return B_FALSE. 4066 */ 4067 static boolean_t 4068 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 4069 char *propname, /* name of the property */ 4070 int minval, /* minimum acceptable value */ 4071 int maxval, /* maximim acceptable value */ 4072 int defval, /* default value */ 4073 int *propvalue) /* property value return to caller */ 4074 { 4075 int propval; /* value returned for requested property */ 4076 int *props; /* point to array of properties returned */ 4077 uint_t nprops; /* number of property value returned */ 4078 boolean_t ret = B_TRUE; 4079 4080 /* 4081 * get the array of properties from the config file 4082 */ 4083 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 4084 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 4085 /* got some properties, test if we got enough */ 4086 if (Adapter->instance < nprops) { 4087 propval = props[Adapter->instance]; 4088 } else { 4089 /* not enough properties configured */ 4090 propval = defval; 4091 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4092 "Not Enough %s values found in e1000g.conf" 4093 " - set to %d\n", 4094 propname, propval); 4095 ret = B_FALSE; 4096 } 4097 4098 /* free memory allocated for properties */ 4099 ddi_prop_free(props); 4100 4101 } else { 4102 propval = defval; 4103 ret = B_FALSE; 4104 } 4105 4106 /* 4107 * enforce limits 4108 */ 4109 if (propval > maxval) { 4110 propval = maxval; 4111 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4112 "Too High %s value in e1000g.conf - set to %d\n", 4113 propname, propval); 4114 } 4115 4116 if (propval < minval) { 4117 propval = minval; 4118 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4119 "Too Low %s value in e1000g.conf - set to %d\n", 4120 propname, propval); 4121 } 4122 4123 *propvalue = propval; 4124 return (ret); 4125 } 4126 4127 static boolean_t 4128 e1000g_link_check(struct e1000g *Adapter) 4129 { 4130 uint16_t speed, duplex, phydata; 4131 boolean_t link_changed = B_FALSE; 4132 struct e1000_hw *hw; 4133 uint32_t reg_tarc; 4134 4135 hw = &Adapter->shared; 4136 4137 if (e1000g_link_up(Adapter)) { 4138 /* 4139 * The Link is up, check whether it was marked as down earlier 4140 */ 4141 if (Adapter->link_state != LINK_STATE_UP) { 4142 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 4143 Adapter->link_speed = speed; 4144 Adapter->link_duplex = duplex; 4145 Adapter->link_state = LINK_STATE_UP; 4146 link_changed = B_TRUE; 4147 4148 if (Adapter->link_speed == SPEED_1000) 4149 Adapter->stall_threshold = TX_STALL_TIME_2S; 4150 else 4151 Adapter->stall_threshold = TX_STALL_TIME_8S; 4152 4153 Adapter->tx_link_down_timeout = 0; 4154 4155 if ((hw->mac.type == e1000_82571) || 4156 (hw->mac.type == e1000_82572)) { 4157 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 4158 if (speed == SPEED_1000) 4159 reg_tarc |= (1 << 21); 4160 else 4161 reg_tarc &= ~(1 << 21); 4162 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 4163 } 4164 } 4165 Adapter->smartspeed = 0; 4166 } else { 4167 if (Adapter->link_state != LINK_STATE_DOWN) { 4168 Adapter->link_speed = 0; 4169 Adapter->link_duplex = 0; 4170 Adapter->link_state = LINK_STATE_DOWN; 4171 link_changed = B_TRUE; 4172 4173 /* 4174 * SmartSpeed workaround for Tabor/TanaX, When the 4175 * driver loses link disable auto master/slave 4176 * resolution. 4177 */ 4178 if (hw->phy.type == e1000_phy_igp) { 4179 (void) e1000_read_phy_reg(hw, 4180 PHY_1000T_CTRL, &phydata); 4181 phydata |= CR_1000T_MS_ENABLE; 4182 (void) e1000_write_phy_reg(hw, 4183 PHY_1000T_CTRL, phydata); 4184 } 4185 } else { 4186 e1000g_smartspeed(Adapter); 4187 } 4188 4189 if (Adapter->e1000g_state & E1000G_STARTED) { 4190 if (Adapter->tx_link_down_timeout < 4191 MAX_TX_LINK_DOWN_TIMEOUT) { 4192 Adapter->tx_link_down_timeout++; 4193 } else if (Adapter->tx_link_down_timeout == 4194 MAX_TX_LINK_DOWN_TIMEOUT) { 4195 e1000g_tx_clean(Adapter); 4196 Adapter->tx_link_down_timeout++; 4197 } 4198 } 4199 } 4200 4201 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4202 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4203 4204 return (link_changed); 4205 } 4206 4207 /* 4208 * e1000g_reset_link - Using the link properties to setup the link 4209 */ 4210 int 4211 e1000g_reset_link(struct e1000g *Adapter) 4212 { 4213 struct e1000_mac_info *mac; 4214 struct e1000_phy_info *phy; 4215 struct e1000_hw *hw; 4216 boolean_t invalid; 4217 4218 mac = &Adapter->shared.mac; 4219 phy = &Adapter->shared.phy; 4220 hw = &Adapter->shared; 4221 invalid = B_FALSE; 4222 4223 if (hw->phy.media_type != e1000_media_type_copper) 4224 goto out; 4225 4226 if (Adapter->param_adv_autoneg == 1) { 4227 mac->autoneg = B_TRUE; 4228 phy->autoneg_advertised = 0; 4229 4230 /* 4231 * 1000hdx is not supported for autonegotiation 4232 */ 4233 if (Adapter->param_adv_1000fdx == 1) 4234 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4235 4236 if (Adapter->param_adv_100fdx == 1) 4237 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4238 4239 if (Adapter->param_adv_100hdx == 1) 4240 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4241 4242 if (Adapter->param_adv_10fdx == 1) 4243 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4244 4245 if (Adapter->param_adv_10hdx == 1) 4246 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4247 4248 if (phy->autoneg_advertised == 0) 4249 invalid = B_TRUE; 4250 } else { 4251 mac->autoneg = B_FALSE; 4252 4253 /* 4254 * For Intel copper cards, 1000fdx and 1000hdx are not 4255 * supported for forced link 4256 */ 4257 if (Adapter->param_adv_100fdx == 1) 4258 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4259 else if (Adapter->param_adv_100hdx == 1) 4260 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4261 else if (Adapter->param_adv_10fdx == 1) 4262 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4263 else if (Adapter->param_adv_10hdx == 1) 4264 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4265 else 4266 invalid = B_TRUE; 4267 4268 } 4269 4270 if (invalid) { 4271 e1000g_log(Adapter, CE_WARN, 4272 "Invalid link settings. Setup link to " 4273 "support autonegotiation with all link capabilities."); 4274 mac->autoneg = B_TRUE; 4275 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4276 } 4277 4278 out: 4279 return (e1000_setup_link(&Adapter->shared)); 4280 } 4281 4282 static void 4283 e1000g_timer_tx_resched(struct e1000g *Adapter) 4284 { 4285 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4286 4287 rw_enter(&Adapter->chip_lock, RW_READER); 4288 4289 if (tx_ring->resched_needed && 4290 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4291 drv_usectohz(1000000)) && 4292 (Adapter->e1000g_state & E1000G_STARTED) && 4293 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4294 tx_ring->resched_needed = B_FALSE; 4295 mac_tx_update(Adapter->mh); 4296 E1000G_STAT(tx_ring->stat_reschedule); 4297 E1000G_STAT(tx_ring->stat_timer_reschedule); 4298 } 4299 4300 rw_exit(&Adapter->chip_lock); 4301 } 4302 4303 static void 4304 e1000g_local_timer(void *ws) 4305 { 4306 struct e1000g *Adapter = (struct e1000g *)ws; 4307 struct e1000_hw *hw; 4308 e1000g_ether_addr_t ether_addr; 4309 boolean_t link_changed; 4310 4311 hw = &Adapter->shared; 4312 4313 if (Adapter->e1000g_state & E1000G_ERROR) { 4314 rw_enter(&Adapter->chip_lock, RW_WRITER); 4315 Adapter->e1000g_state &= ~E1000G_ERROR; 4316 rw_exit(&Adapter->chip_lock); 4317 4318 Adapter->reset_count++; 4319 if (e1000g_global_reset(Adapter)) { 4320 ddi_fm_service_impact(Adapter->dip, 4321 DDI_SERVICE_RESTORED); 4322 e1000g_timer_tx_resched(Adapter); 4323 } else 4324 ddi_fm_service_impact(Adapter->dip, 4325 DDI_SERVICE_LOST); 4326 return; 4327 } 4328 4329 if (e1000g_stall_check(Adapter)) { 4330 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4331 "Tx stall detected. Activate automatic recovery.\n"); 4332 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4333 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4334 Adapter->reset_count++; 4335 if (e1000g_reset_adapter(Adapter)) { 4336 ddi_fm_service_impact(Adapter->dip, 4337 DDI_SERVICE_RESTORED); 4338 e1000g_timer_tx_resched(Adapter); 4339 } 4340 return; 4341 } 4342 4343 link_changed = B_FALSE; 4344 rw_enter(&Adapter->chip_lock, RW_READER); 4345 if (Adapter->link_complete) 4346 link_changed = e1000g_link_check(Adapter); 4347 rw_exit(&Adapter->chip_lock); 4348 4349 if (link_changed) { 4350 if (!Adapter->reset_flag && 4351 (Adapter->e1000g_state & E1000G_STARTED) && 4352 !(Adapter->e1000g_state & E1000G_SUSPENDED)) 4353 mac_link_update(Adapter->mh, Adapter->link_state); 4354 if (Adapter->link_state == LINK_STATE_UP) 4355 Adapter->reset_flag = B_FALSE; 4356 } 4357 /* 4358 * Workaround for esb2. Data stuck in fifo on a link 4359 * down event. Reset the adapter to recover it. 4360 */ 4361 if (Adapter->esb2_workaround) { 4362 Adapter->esb2_workaround = B_FALSE; 4363 (void) e1000g_reset_adapter(Adapter); 4364 return; 4365 } 4366 4367 /* 4368 * With 82571 controllers, any locally administered address will 4369 * be overwritten when there is a reset on the other port. 4370 * Detect this circumstance and correct it. 4371 */ 4372 if ((hw->mac.type == e1000_82571) && 4373 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4374 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4375 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4376 4377 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4378 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4379 4380 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4381 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4382 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4383 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4384 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4385 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4386 e1000_rar_set(hw, hw->mac.addr, 0); 4387 } 4388 } 4389 4390 /* 4391 * Long TTL workaround for 82541/82547 4392 */ 4393 (void) e1000_igp_ttl_workaround_82547(hw); 4394 4395 /* 4396 * Check for Adaptive IFS settings If there are lots of collisions 4397 * change the value in steps... 4398 * These properties should only be set for 10/100 4399 */ 4400 if ((hw->phy.media_type == e1000_media_type_copper) && 4401 ((Adapter->link_speed == SPEED_100) || 4402 (Adapter->link_speed == SPEED_10))) { 4403 e1000_update_adaptive(hw); 4404 } 4405 /* 4406 * Set Timer Interrupts 4407 */ 4408 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4409 4410 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4411 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4412 else 4413 e1000g_timer_tx_resched(Adapter); 4414 4415 restart_watchdog_timer(Adapter); 4416 } 4417 4418 /* 4419 * The function e1000g_link_timer() is called when the timer for link setup 4420 * is expired, which indicates the completion of the link setup. The link 4421 * state will not be updated until the link setup is completed. And the 4422 * link state will not be sent to the upper layer through mac_link_update() 4423 * in this function. It will be updated in the local timer routine or the 4424 * interrupt service routine after the interface is started (plumbed). 4425 */ 4426 static void 4427 e1000g_link_timer(void *arg) 4428 { 4429 struct e1000g *Adapter = (struct e1000g *)arg; 4430 4431 mutex_enter(&Adapter->link_lock); 4432 Adapter->link_complete = B_TRUE; 4433 Adapter->link_tid = 0; 4434 mutex_exit(&Adapter->link_lock); 4435 } 4436 4437 /* 4438 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4439 * 4440 * This function read the forced speed and duplex for 10/100 Mbps speeds 4441 * and also for 1000 Mbps speeds from the e1000g.conf file 4442 */ 4443 static void 4444 e1000g_force_speed_duplex(struct e1000g *Adapter) 4445 { 4446 int forced; 4447 int propval; 4448 struct e1000_mac_info *mac = &Adapter->shared.mac; 4449 struct e1000_phy_info *phy = &Adapter->shared.phy; 4450 4451 /* 4452 * get value out of config file 4453 */ 4454 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4455 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4456 4457 switch (forced) { 4458 case GDIAG_10_HALF: 4459 /* 4460 * Disable Auto Negotiation 4461 */ 4462 mac->autoneg = B_FALSE; 4463 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4464 break; 4465 case GDIAG_10_FULL: 4466 /* 4467 * Disable Auto Negotiation 4468 */ 4469 mac->autoneg = B_FALSE; 4470 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4471 break; 4472 case GDIAG_100_HALF: 4473 /* 4474 * Disable Auto Negotiation 4475 */ 4476 mac->autoneg = B_FALSE; 4477 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4478 break; 4479 case GDIAG_100_FULL: 4480 /* 4481 * Disable Auto Negotiation 4482 */ 4483 mac->autoneg = B_FALSE; 4484 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4485 break; 4486 case GDIAG_1000_FULL: 4487 /* 4488 * The gigabit spec requires autonegotiation. Therefore, 4489 * when the user wants to force the speed to 1000Mbps, we 4490 * enable AutoNeg, but only allow the harware to advertise 4491 * 1000Mbps. This is different from 10/100 operation, where 4492 * we are allowed to link without any negotiation. 4493 */ 4494 mac->autoneg = B_TRUE; 4495 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4496 break; 4497 default: /* obey the setting of AutoNegAdvertised */ 4498 mac->autoneg = B_TRUE; 4499 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4500 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4501 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4502 phy->autoneg_advertised = (uint16_t)propval; 4503 break; 4504 } /* switch */ 4505 } 4506 4507 /* 4508 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4509 * 4510 * This function reads MaxFrameSize from e1000g.conf 4511 */ 4512 static void 4513 e1000g_get_max_frame_size(struct e1000g *Adapter) 4514 { 4515 int max_frame; 4516 4517 /* 4518 * get value out of config file 4519 */ 4520 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4521 &max_frame); 4522 4523 switch (max_frame) { 4524 case 0: 4525 Adapter->default_mtu = ETHERMTU; 4526 break; 4527 case 1: 4528 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4529 sizeof (struct ether_vlan_header) - ETHERFCSL; 4530 break; 4531 case 2: 4532 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4533 sizeof (struct ether_vlan_header) - ETHERFCSL; 4534 break; 4535 case 3: 4536 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4537 sizeof (struct ether_vlan_header) - ETHERFCSL; 4538 break; 4539 default: 4540 Adapter->default_mtu = ETHERMTU; 4541 break; 4542 } /* switch */ 4543 4544 /* 4545 * If the user configed MTU is larger than the deivce's maximum MTU, 4546 * the MTU is set to the deivce's maximum value. 4547 */ 4548 if (Adapter->default_mtu > Adapter->max_mtu) 4549 Adapter->default_mtu = Adapter->max_mtu; 4550 4551 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4552 } 4553 4554 /* 4555 * e1000g_pch_limits - Apply limits of the PCH silicon type 4556 * 4557 * At any frame size larger than the ethernet default, 4558 * prevent linking at 10/100 speeds. 4559 */ 4560 static void 4561 e1000g_pch_limits(struct e1000g *Adapter) 4562 { 4563 struct e1000_hw *hw = &Adapter->shared; 4564 4565 /* only applies to PCH silicon type */ 4566 if (hw->mac.type != e1000_pchlan && hw->mac.type != e1000_pch2lan) 4567 return; 4568 4569 /* only applies to frames larger than ethernet default */ 4570 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4571 hw->mac.autoneg = B_TRUE; 4572 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4573 4574 Adapter->param_adv_autoneg = 1; 4575 Adapter->param_adv_1000fdx = 1; 4576 4577 Adapter->param_adv_100fdx = 0; 4578 Adapter->param_adv_100hdx = 0; 4579 Adapter->param_adv_10fdx = 0; 4580 Adapter->param_adv_10hdx = 0; 4581 4582 e1000g_param_sync(Adapter); 4583 } 4584 } 4585 4586 /* 4587 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4588 */ 4589 static uint32_t 4590 e1000g_mtu2maxframe(uint32_t mtu) 4591 { 4592 uint32_t maxframe; 4593 4594 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4595 4596 return (maxframe); 4597 } 4598 4599 static void 4600 arm_watchdog_timer(struct e1000g *Adapter) 4601 { 4602 Adapter->watchdog_tid = 4603 timeout(e1000g_local_timer, 4604 (void *)Adapter, 1 * drv_usectohz(1000000)); 4605 } 4606 #pragma inline(arm_watchdog_timer) 4607 4608 static void 4609 enable_watchdog_timer(struct e1000g *Adapter) 4610 { 4611 mutex_enter(&Adapter->watchdog_lock); 4612 4613 if (!Adapter->watchdog_timer_enabled) { 4614 Adapter->watchdog_timer_enabled = B_TRUE; 4615 Adapter->watchdog_timer_started = B_TRUE; 4616 arm_watchdog_timer(Adapter); 4617 } 4618 4619 mutex_exit(&Adapter->watchdog_lock); 4620 } 4621 4622 static void 4623 disable_watchdog_timer(struct e1000g *Adapter) 4624 { 4625 timeout_id_t tid; 4626 4627 mutex_enter(&Adapter->watchdog_lock); 4628 4629 Adapter->watchdog_timer_enabled = B_FALSE; 4630 Adapter->watchdog_timer_started = B_FALSE; 4631 tid = Adapter->watchdog_tid; 4632 Adapter->watchdog_tid = 0; 4633 4634 mutex_exit(&Adapter->watchdog_lock); 4635 4636 if (tid != 0) 4637 (void) untimeout(tid); 4638 } 4639 4640 static void 4641 start_watchdog_timer(struct e1000g *Adapter) 4642 { 4643 mutex_enter(&Adapter->watchdog_lock); 4644 4645 if (Adapter->watchdog_timer_enabled) { 4646 if (!Adapter->watchdog_timer_started) { 4647 Adapter->watchdog_timer_started = B_TRUE; 4648 arm_watchdog_timer(Adapter); 4649 } 4650 } 4651 4652 mutex_exit(&Adapter->watchdog_lock); 4653 } 4654 4655 static void 4656 restart_watchdog_timer(struct e1000g *Adapter) 4657 { 4658 mutex_enter(&Adapter->watchdog_lock); 4659 4660 if (Adapter->watchdog_timer_started) 4661 arm_watchdog_timer(Adapter); 4662 4663 mutex_exit(&Adapter->watchdog_lock); 4664 } 4665 4666 static void 4667 stop_watchdog_timer(struct e1000g *Adapter) 4668 { 4669 timeout_id_t tid; 4670 4671 mutex_enter(&Adapter->watchdog_lock); 4672 4673 Adapter->watchdog_timer_started = B_FALSE; 4674 tid = Adapter->watchdog_tid; 4675 Adapter->watchdog_tid = 0; 4676 4677 mutex_exit(&Adapter->watchdog_lock); 4678 4679 if (tid != 0) 4680 (void) untimeout(tid); 4681 } 4682 4683 static void 4684 stop_link_timer(struct e1000g *Adapter) 4685 { 4686 timeout_id_t tid; 4687 4688 /* Disable the link timer */ 4689 mutex_enter(&Adapter->link_lock); 4690 4691 tid = Adapter->link_tid; 4692 Adapter->link_tid = 0; 4693 4694 mutex_exit(&Adapter->link_lock); 4695 4696 if (tid != 0) 4697 (void) untimeout(tid); 4698 } 4699 4700 static void 4701 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4702 { 4703 timeout_id_t tid; 4704 4705 /* Disable the tx timer for 82547 chipset */ 4706 mutex_enter(&tx_ring->tx_lock); 4707 4708 tx_ring->timer_enable_82547 = B_FALSE; 4709 tid = tx_ring->timer_id_82547; 4710 tx_ring->timer_id_82547 = 0; 4711 4712 mutex_exit(&tx_ring->tx_lock); 4713 4714 if (tid != 0) 4715 (void) untimeout(tid); 4716 } 4717 4718 void 4719 e1000g_clear_interrupt(struct e1000g *Adapter) 4720 { 4721 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4722 0xffffffff & ~E1000_IMS_RXSEQ); 4723 } 4724 4725 void 4726 e1000g_mask_interrupt(struct e1000g *Adapter) 4727 { 4728 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4729 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4730 4731 if (Adapter->tx_intr_enable) 4732 e1000g_mask_tx_interrupt(Adapter); 4733 } 4734 4735 /* 4736 * This routine is called by e1000g_quiesce(), therefore must not block. 4737 */ 4738 void 4739 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4740 { 4741 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4742 } 4743 4744 void 4745 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4746 { 4747 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4748 } 4749 4750 void 4751 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4752 { 4753 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4754 } 4755 4756 static void 4757 e1000g_smartspeed(struct e1000g *Adapter) 4758 { 4759 struct e1000_hw *hw = &Adapter->shared; 4760 uint16_t phy_status; 4761 uint16_t phy_ctrl; 4762 4763 /* 4764 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4765 * advertising 1000Full, we don't even use the workaround 4766 */ 4767 if ((hw->phy.type != e1000_phy_igp) || 4768 !hw->mac.autoneg || 4769 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4770 return; 4771 4772 /* 4773 * True if this is the first call of this function or after every 4774 * 30 seconds of not having link 4775 */ 4776 if (Adapter->smartspeed == 0) { 4777 /* 4778 * If Master/Slave config fault is asserted twice, we 4779 * assume back-to-back 4780 */ 4781 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4782 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4783 return; 4784 4785 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4786 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4787 return; 4788 /* 4789 * We're assuming back-2-back because our status register 4790 * insists! there's a fault in the master/slave 4791 * relationship that was "negotiated" 4792 */ 4793 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4794 /* 4795 * Is the phy configured for manual configuration of 4796 * master/slave? 4797 */ 4798 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4799 /* 4800 * Yes. Then disable manual configuration (enable 4801 * auto configuration) of master/slave 4802 */ 4803 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4804 (void) e1000_write_phy_reg(hw, 4805 PHY_1000T_CTRL, phy_ctrl); 4806 /* 4807 * Effectively starting the clock 4808 */ 4809 Adapter->smartspeed++; 4810 /* 4811 * Restart autonegotiation 4812 */ 4813 if (!e1000_phy_setup_autoneg(hw) && 4814 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4815 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4816 MII_CR_RESTART_AUTO_NEG); 4817 (void) e1000_write_phy_reg(hw, 4818 PHY_CONTROL, phy_ctrl); 4819 } 4820 } 4821 return; 4822 /* 4823 * Has 6 seconds transpired still without link? Remember, 4824 * you should reset the smartspeed counter once you obtain 4825 * link 4826 */ 4827 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4828 /* 4829 * Yes. Remember, we did at the start determine that 4830 * there's a master/slave configuration fault, so we're 4831 * still assuming there's someone on the other end, but we 4832 * just haven't yet been able to talk to it. We then 4833 * re-enable auto configuration of master/slave to see if 4834 * we're running 2/3 pair cables. 4835 */ 4836 /* 4837 * If still no link, perhaps using 2/3 pair cable 4838 */ 4839 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4840 phy_ctrl |= CR_1000T_MS_ENABLE; 4841 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4842 /* 4843 * Restart autoneg with phy enabled for manual 4844 * configuration of master/slave 4845 */ 4846 if (!e1000_phy_setup_autoneg(hw) && 4847 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4848 phy_ctrl |= 4849 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4850 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4851 } 4852 /* 4853 * Hopefully, there are no more faults and we've obtained 4854 * link as a result. 4855 */ 4856 } 4857 /* 4858 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4859 * seconds) 4860 */ 4861 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4862 Adapter->smartspeed = 0; 4863 } 4864 4865 static boolean_t 4866 is_valid_mac_addr(uint8_t *mac_addr) 4867 { 4868 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4869 const uint8_t addr_test2[6] = 4870 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4871 4872 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4873 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4874 return (B_FALSE); 4875 4876 return (B_TRUE); 4877 } 4878 4879 /* 4880 * e1000g_stall_check - check for tx stall 4881 * 4882 * This function checks if the adapter is stalled (in transmit). 4883 * 4884 * It is called each time the watchdog timeout is invoked. 4885 * If the transmit descriptor reclaim continuously fails, 4886 * the watchdog value will increment by 1. If the watchdog 4887 * value exceeds the threshold, the adapter is assumed to 4888 * have stalled and need to be reset. 4889 */ 4890 static boolean_t 4891 e1000g_stall_check(struct e1000g *Adapter) 4892 { 4893 e1000g_tx_ring_t *tx_ring; 4894 4895 tx_ring = Adapter->tx_ring; 4896 4897 if (Adapter->link_state != LINK_STATE_UP) 4898 return (B_FALSE); 4899 4900 (void) e1000g_recycle(tx_ring); 4901 4902 if (Adapter->stall_flag) 4903 return (B_TRUE); 4904 4905 return (B_FALSE); 4906 } 4907 4908 #ifdef E1000G_DEBUG 4909 static enum ioc_reply 4910 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4911 { 4912 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4913 e1000g_peekpoke_t *ppd; 4914 uint64_t mem_va; 4915 uint64_t maxoff; 4916 boolean_t peek; 4917 4918 switch (iocp->ioc_cmd) { 4919 4920 case E1000G_IOC_REG_PEEK: 4921 peek = B_TRUE; 4922 break; 4923 4924 case E1000G_IOC_REG_POKE: 4925 peek = B_FALSE; 4926 break; 4927 4928 deault: 4929 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4930 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4931 iocp->ioc_cmd); 4932 return (IOC_INVAL); 4933 } 4934 4935 /* 4936 * Validate format of ioctl 4937 */ 4938 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4939 return (IOC_INVAL); 4940 if (mp->b_cont == NULL) 4941 return (IOC_INVAL); 4942 4943 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4944 4945 /* 4946 * Validate request parameters 4947 */ 4948 switch (ppd->pp_acc_space) { 4949 4950 default: 4951 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4952 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4953 ppd->pp_acc_space); 4954 return (IOC_INVAL); 4955 4956 case E1000G_PP_SPACE_REG: 4957 /* 4958 * Memory-mapped I/O space 4959 */ 4960 ASSERT(ppd->pp_acc_size == 4); 4961 if (ppd->pp_acc_size != 4) 4962 return (IOC_INVAL); 4963 4964 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4965 return (IOC_INVAL); 4966 4967 mem_va = 0; 4968 maxoff = 0x10000; 4969 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4970 break; 4971 4972 case E1000G_PP_SPACE_E1000G: 4973 /* 4974 * E1000g data structure! 4975 */ 4976 mem_va = (uintptr_t)e1000gp; 4977 maxoff = sizeof (struct e1000g); 4978 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4979 break; 4980 4981 } 4982 4983 if (ppd->pp_acc_offset >= maxoff) 4984 return (IOC_INVAL); 4985 4986 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4987 return (IOC_INVAL); 4988 4989 /* 4990 * All OK - go! 4991 */ 4992 ppd->pp_acc_offset += mem_va; 4993 (*ppfn)(e1000gp, ppd); 4994 return (peek ? IOC_REPLY : IOC_ACK); 4995 } 4996 4997 static void 4998 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4999 { 5000 ddi_acc_handle_t handle; 5001 uint32_t *regaddr; 5002 5003 handle = e1000gp->osdep.reg_handle; 5004 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5005 (uintptr_t)ppd->pp_acc_offset); 5006 5007 ppd->pp_acc_data = ddi_get32(handle, regaddr); 5008 } 5009 5010 static void 5011 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5012 { 5013 ddi_acc_handle_t handle; 5014 uint32_t *regaddr; 5015 uint32_t value; 5016 5017 handle = e1000gp->osdep.reg_handle; 5018 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5019 (uintptr_t)ppd->pp_acc_offset); 5020 value = (uint32_t)ppd->pp_acc_data; 5021 5022 ddi_put32(handle, regaddr, value); 5023 } 5024 5025 static void 5026 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5027 { 5028 uint64_t value; 5029 void *vaddr; 5030 5031 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5032 5033 switch (ppd->pp_acc_size) { 5034 case 1: 5035 value = *(uint8_t *)vaddr; 5036 break; 5037 5038 case 2: 5039 value = *(uint16_t *)vaddr; 5040 break; 5041 5042 case 4: 5043 value = *(uint32_t *)vaddr; 5044 break; 5045 5046 case 8: 5047 value = *(uint64_t *)vaddr; 5048 break; 5049 } 5050 5051 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5052 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 5053 (void *)e1000gp, (void *)ppd, value, vaddr); 5054 5055 ppd->pp_acc_data = value; 5056 } 5057 5058 static void 5059 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5060 { 5061 uint64_t value; 5062 void *vaddr; 5063 5064 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5065 value = ppd->pp_acc_data; 5066 5067 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5068 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 5069 (void *)e1000gp, (void *)ppd, value, vaddr); 5070 5071 switch (ppd->pp_acc_size) { 5072 case 1: 5073 *(uint8_t *)vaddr = (uint8_t)value; 5074 break; 5075 5076 case 2: 5077 *(uint16_t *)vaddr = (uint16_t)value; 5078 break; 5079 5080 case 4: 5081 *(uint32_t *)vaddr = (uint32_t)value; 5082 break; 5083 5084 case 8: 5085 *(uint64_t *)vaddr = (uint64_t)value; 5086 break; 5087 } 5088 } 5089 #endif 5090 5091 /* 5092 * Loopback Support 5093 */ 5094 static lb_property_t lb_normal = 5095 { normal, "normal", E1000G_LB_NONE }; 5096 static lb_property_t lb_external1000 = 5097 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 5098 static lb_property_t lb_external100 = 5099 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 5100 static lb_property_t lb_external10 = 5101 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 5102 static lb_property_t lb_phy = 5103 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 5104 5105 static enum ioc_reply 5106 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 5107 { 5108 lb_info_sz_t *lbsp; 5109 lb_property_t *lbpp; 5110 struct e1000_hw *hw; 5111 uint32_t *lbmp; 5112 uint32_t size; 5113 uint32_t value; 5114 5115 hw = &Adapter->shared; 5116 5117 if (mp->b_cont == NULL) 5118 return (IOC_INVAL); 5119 5120 if (!e1000g_check_loopback_support(hw)) { 5121 e1000g_log(NULL, CE_WARN, 5122 "Loopback is not supported on e1000g%d", Adapter->instance); 5123 return (IOC_INVAL); 5124 } 5125 5126 switch (iocp->ioc_cmd) { 5127 default: 5128 return (IOC_INVAL); 5129 5130 case LB_GET_INFO_SIZE: 5131 size = sizeof (lb_info_sz_t); 5132 if (iocp->ioc_count != size) 5133 return (IOC_INVAL); 5134 5135 rw_enter(&Adapter->chip_lock, RW_WRITER); 5136 e1000g_get_phy_state(Adapter); 5137 5138 /* 5139 * Workaround for hardware faults. In order to get a stable 5140 * state of phy, we will wait for a specific interval and 5141 * try again. The time delay is an experiential value based 5142 * on our testing. 5143 */ 5144 msec_delay(100); 5145 e1000g_get_phy_state(Adapter); 5146 rw_exit(&Adapter->chip_lock); 5147 5148 value = sizeof (lb_normal); 5149 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5150 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5151 (hw->phy.media_type == e1000_media_type_fiber) || 5152 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5153 value += sizeof (lb_phy); 5154 switch (hw->mac.type) { 5155 case e1000_82571: 5156 case e1000_82572: 5157 case e1000_80003es2lan: 5158 value += sizeof (lb_external1000); 5159 break; 5160 } 5161 } 5162 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5163 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5164 value += sizeof (lb_external100); 5165 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5166 value += sizeof (lb_external10); 5167 5168 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 5169 *lbsp = value; 5170 break; 5171 5172 case LB_GET_INFO: 5173 value = sizeof (lb_normal); 5174 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5175 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5176 (hw->phy.media_type == e1000_media_type_fiber) || 5177 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5178 value += sizeof (lb_phy); 5179 switch (hw->mac.type) { 5180 case e1000_82571: 5181 case e1000_82572: 5182 case e1000_80003es2lan: 5183 value += sizeof (lb_external1000); 5184 break; 5185 } 5186 } 5187 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5188 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5189 value += sizeof (lb_external100); 5190 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5191 value += sizeof (lb_external10); 5192 5193 size = value; 5194 if (iocp->ioc_count != size) 5195 return (IOC_INVAL); 5196 5197 value = 0; 5198 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5199 lbpp[value++] = lb_normal; 5200 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5201 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5202 (hw->phy.media_type == e1000_media_type_fiber) || 5203 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5204 lbpp[value++] = lb_phy; 5205 switch (hw->mac.type) { 5206 case e1000_82571: 5207 case e1000_82572: 5208 case e1000_80003es2lan: 5209 lbpp[value++] = lb_external1000; 5210 break; 5211 } 5212 } 5213 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5214 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5215 lbpp[value++] = lb_external100; 5216 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5217 lbpp[value++] = lb_external10; 5218 break; 5219 5220 case LB_GET_MODE: 5221 size = sizeof (uint32_t); 5222 if (iocp->ioc_count != size) 5223 return (IOC_INVAL); 5224 5225 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5226 *lbmp = Adapter->loopback_mode; 5227 break; 5228 5229 case LB_SET_MODE: 5230 size = 0; 5231 if (iocp->ioc_count != sizeof (uint32_t)) 5232 return (IOC_INVAL); 5233 5234 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5235 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5236 return (IOC_INVAL); 5237 break; 5238 } 5239 5240 iocp->ioc_count = size; 5241 iocp->ioc_error = 0; 5242 5243 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5244 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5245 return (IOC_INVAL); 5246 } 5247 5248 return (IOC_REPLY); 5249 } 5250 5251 static boolean_t 5252 e1000g_check_loopback_support(struct e1000_hw *hw) 5253 { 5254 switch (hw->mac.type) { 5255 case e1000_82540: 5256 case e1000_82545: 5257 case e1000_82545_rev_3: 5258 case e1000_82546: 5259 case e1000_82546_rev_3: 5260 case e1000_82541: 5261 case e1000_82541_rev_2: 5262 case e1000_82547: 5263 case e1000_82547_rev_2: 5264 case e1000_82571: 5265 case e1000_82572: 5266 case e1000_82573: 5267 case e1000_82574: 5268 case e1000_80003es2lan: 5269 case e1000_ich9lan: 5270 case e1000_ich10lan: 5271 return (B_TRUE); 5272 } 5273 return (B_FALSE); 5274 } 5275 5276 static boolean_t 5277 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5278 { 5279 struct e1000_hw *hw; 5280 int i, times; 5281 boolean_t link_up; 5282 5283 if (mode == Adapter->loopback_mode) 5284 return (B_TRUE); 5285 5286 hw = &Adapter->shared; 5287 times = 0; 5288 5289 Adapter->loopback_mode = mode; 5290 5291 if (mode == E1000G_LB_NONE) { 5292 /* Reset the chip */ 5293 hw->phy.autoneg_wait_to_complete = B_TRUE; 5294 (void) e1000g_reset_adapter(Adapter); 5295 hw->phy.autoneg_wait_to_complete = B_FALSE; 5296 return (B_TRUE); 5297 } 5298 5299 again: 5300 5301 rw_enter(&Adapter->chip_lock, RW_WRITER); 5302 5303 switch (mode) { 5304 default: 5305 rw_exit(&Adapter->chip_lock); 5306 return (B_FALSE); 5307 5308 case E1000G_LB_EXTERNAL_1000: 5309 e1000g_set_external_loopback_1000(Adapter); 5310 break; 5311 5312 case E1000G_LB_EXTERNAL_100: 5313 e1000g_set_external_loopback_100(Adapter); 5314 break; 5315 5316 case E1000G_LB_EXTERNAL_10: 5317 e1000g_set_external_loopback_10(Adapter); 5318 break; 5319 5320 case E1000G_LB_INTERNAL_PHY: 5321 e1000g_set_internal_loopback(Adapter); 5322 break; 5323 } 5324 5325 times++; 5326 5327 rw_exit(&Adapter->chip_lock); 5328 5329 /* Wait for link up */ 5330 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5331 msec_delay(100); 5332 5333 rw_enter(&Adapter->chip_lock, RW_WRITER); 5334 5335 link_up = e1000g_link_up(Adapter); 5336 5337 rw_exit(&Adapter->chip_lock); 5338 5339 if (!link_up) { 5340 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5341 "Failed to get the link up"); 5342 if (times < 2) { 5343 /* Reset the link */ 5344 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5345 "Reset the link ..."); 5346 (void) e1000g_reset_adapter(Adapter); 5347 goto again; 5348 } 5349 5350 /* 5351 * Reset driver to loopback none when set loopback failed 5352 * for the second time. 5353 */ 5354 Adapter->loopback_mode = E1000G_LB_NONE; 5355 5356 /* Reset the chip */ 5357 hw->phy.autoneg_wait_to_complete = B_TRUE; 5358 (void) e1000g_reset_adapter(Adapter); 5359 hw->phy.autoneg_wait_to_complete = B_FALSE; 5360 5361 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5362 "Set loopback mode failed, reset to loopback none"); 5363 5364 return (B_FALSE); 5365 } 5366 5367 return (B_TRUE); 5368 } 5369 5370 /* 5371 * The following loopback settings are from Intel's technical 5372 * document - "How To Loopback". All the register settings and 5373 * time delay values are directly inherited from the document 5374 * without more explanations available. 5375 */ 5376 static void 5377 e1000g_set_internal_loopback(struct e1000g *Adapter) 5378 { 5379 struct e1000_hw *hw; 5380 uint32_t ctrl; 5381 uint32_t status; 5382 uint16_t phy_ctrl; 5383 uint16_t phy_reg; 5384 uint32_t txcw; 5385 5386 hw = &Adapter->shared; 5387 5388 /* Disable Smart Power Down */ 5389 phy_spd_state(hw, B_FALSE); 5390 5391 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5392 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5393 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5394 5395 switch (hw->mac.type) { 5396 case e1000_82540: 5397 case e1000_82545: 5398 case e1000_82545_rev_3: 5399 case e1000_82546: 5400 case e1000_82546_rev_3: 5401 case e1000_82573: 5402 /* Auto-MDI/MDIX off */ 5403 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5404 /* Reset PHY to update Auto-MDI/MDIX */ 5405 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5406 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5407 /* Reset PHY to auto-neg off and force 1000 */ 5408 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5409 phy_ctrl | MII_CR_RESET); 5410 /* 5411 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5412 * See comments above e1000g_set_internal_loopback() for the 5413 * background. 5414 */ 5415 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5416 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5417 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5418 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5419 break; 5420 case e1000_80003es2lan: 5421 /* Force Link Up */ 5422 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5423 0x1CC); 5424 /* Sets PCS loopback at 1Gbs */ 5425 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5426 0x1046); 5427 break; 5428 } 5429 5430 /* 5431 * The following registers should be set for e1000_phy_bm phy type. 5432 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5433 * For others, we do not need to set these registers. 5434 */ 5435 if (hw->phy.type == e1000_phy_bm) { 5436 /* Set Default MAC Interface speed to 1GB */ 5437 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5438 phy_reg &= ~0x0007; 5439 phy_reg |= 0x006; 5440 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5441 /* Assert SW reset for above settings to take effect */ 5442 (void) e1000_phy_commit(hw); 5443 msec_delay(1); 5444 /* Force Full Duplex */ 5445 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5446 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5447 phy_reg | 0x000C); 5448 /* Set Link Up (in force link) */ 5449 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5450 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5451 phy_reg | 0x0040); 5452 /* Force Link */ 5453 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5454 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5455 phy_reg | 0x0040); 5456 /* Set Early Link Enable */ 5457 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5458 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5459 phy_reg | 0x0400); 5460 } 5461 5462 /* Set loopback */ 5463 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5464 5465 msec_delay(250); 5466 5467 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5468 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5469 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5470 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5471 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5472 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5473 E1000_CTRL_FD); /* Force Duplex to FULL */ 5474 5475 switch (hw->mac.type) { 5476 case e1000_82540: 5477 case e1000_82545: 5478 case e1000_82545_rev_3: 5479 case e1000_82546: 5480 case e1000_82546_rev_3: 5481 /* 5482 * For some serdes we'll need to commit the writes now 5483 * so that the status is updated on link 5484 */ 5485 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5486 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5487 msec_delay(100); 5488 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5489 } 5490 5491 if (hw->phy.media_type == e1000_media_type_copper) { 5492 /* Invert Loss of Signal */ 5493 ctrl |= E1000_CTRL_ILOS; 5494 } else { 5495 /* Set ILOS on fiber nic if half duplex is detected */ 5496 status = E1000_READ_REG(hw, E1000_STATUS); 5497 if ((status & E1000_STATUS_FD) == 0) 5498 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5499 } 5500 break; 5501 5502 case e1000_82571: 5503 case e1000_82572: 5504 /* 5505 * The fiber/SerDes versions of this adapter do not contain an 5506 * accessible PHY. Therefore, loopback beyond MAC must be done 5507 * using SerDes analog loopback. 5508 */ 5509 if (hw->phy.media_type != e1000_media_type_copper) { 5510 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5511 txcw = E1000_READ_REG(hw, E1000_TXCW); 5512 txcw &= ~((uint32_t)1 << 31); 5513 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5514 5515 /* 5516 * Write 0x410 to Serdes Control register 5517 * to enable Serdes analog loopback 5518 */ 5519 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5520 msec_delay(10); 5521 } 5522 5523 status = E1000_READ_REG(hw, E1000_STATUS); 5524 /* Set ILOS on fiber nic if half duplex is detected */ 5525 if ((hw->phy.media_type == e1000_media_type_fiber) && 5526 ((status & E1000_STATUS_FD) == 0 || 5527 (status & E1000_STATUS_LU) == 0)) 5528 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5529 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5530 ctrl |= E1000_CTRL_SLU; 5531 break; 5532 5533 case e1000_82573: 5534 ctrl |= E1000_CTRL_ILOS; 5535 break; 5536 case e1000_ich9lan: 5537 case e1000_ich10lan: 5538 ctrl |= E1000_CTRL_SLU; 5539 break; 5540 } 5541 if (hw->phy.type == e1000_phy_bm) 5542 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5543 5544 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5545 } 5546 5547 static void 5548 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5549 { 5550 struct e1000_hw *hw; 5551 uint32_t rctl; 5552 uint32_t ctrl_ext; 5553 uint32_t ctrl; 5554 uint32_t status; 5555 uint32_t txcw; 5556 uint16_t phydata; 5557 5558 hw = &Adapter->shared; 5559 5560 /* Disable Smart Power Down */ 5561 phy_spd_state(hw, B_FALSE); 5562 5563 switch (hw->mac.type) { 5564 case e1000_82571: 5565 case e1000_82572: 5566 switch (hw->phy.media_type) { 5567 case e1000_media_type_copper: 5568 /* Force link up (Must be done before the PHY writes) */ 5569 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5570 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5571 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5572 5573 rctl = E1000_READ_REG(hw, E1000_RCTL); 5574 rctl |= (E1000_RCTL_EN | 5575 E1000_RCTL_SBP | 5576 E1000_RCTL_UPE | 5577 E1000_RCTL_MPE | 5578 E1000_RCTL_LPE | 5579 E1000_RCTL_BAM); /* 0x803E */ 5580 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5581 5582 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5583 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5584 E1000_CTRL_EXT_SDP6_DATA | 5585 E1000_CTRL_EXT_SDP3_DATA | 5586 E1000_CTRL_EXT_SDP4_DIR | 5587 E1000_CTRL_EXT_SDP6_DIR | 5588 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5589 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5590 5591 /* 5592 * This sequence tunes the PHY's SDP and no customer 5593 * settable values. For background, see comments above 5594 * e1000g_set_internal_loopback(). 5595 */ 5596 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5597 msec_delay(10); 5598 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5599 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5600 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5601 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5602 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5603 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5604 5605 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5606 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5607 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5608 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5609 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5610 5611 msec_delay(50); 5612 break; 5613 case e1000_media_type_fiber: 5614 case e1000_media_type_internal_serdes: 5615 status = E1000_READ_REG(hw, E1000_STATUS); 5616 if (((status & E1000_STATUS_LU) == 0) || 5617 (hw->phy.media_type == 5618 e1000_media_type_internal_serdes)) { 5619 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5620 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5621 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5622 } 5623 5624 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5625 txcw = E1000_READ_REG(hw, E1000_TXCW); 5626 txcw &= ~((uint32_t)1 << 31); 5627 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5628 5629 /* 5630 * Write 0x410 to Serdes Control register 5631 * to enable Serdes analog loopback 5632 */ 5633 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5634 msec_delay(10); 5635 break; 5636 default: 5637 break; 5638 } 5639 break; 5640 case e1000_82574: 5641 case e1000_80003es2lan: 5642 case e1000_ich9lan: 5643 case e1000_ich10lan: 5644 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5645 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5646 phydata | (1 << 5)); 5647 Adapter->param_adv_autoneg = 1; 5648 Adapter->param_adv_1000fdx = 1; 5649 (void) e1000g_reset_link(Adapter); 5650 break; 5651 } 5652 } 5653 5654 static void 5655 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5656 { 5657 struct e1000_hw *hw; 5658 uint32_t ctrl; 5659 uint16_t phy_ctrl; 5660 5661 hw = &Adapter->shared; 5662 5663 /* Disable Smart Power Down */ 5664 phy_spd_state(hw, B_FALSE); 5665 5666 phy_ctrl = (MII_CR_FULL_DUPLEX | 5667 MII_CR_SPEED_100); 5668 5669 /* Force 100/FD, reset PHY */ 5670 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5671 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5672 msec_delay(10); 5673 5674 /* Force 100/FD */ 5675 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5676 phy_ctrl); /* 0x2100 */ 5677 msec_delay(10); 5678 5679 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5680 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5681 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5682 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5683 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5684 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5685 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5686 E1000_CTRL_FD); /* Force Duplex to FULL */ 5687 5688 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5689 } 5690 5691 static void 5692 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5693 { 5694 struct e1000_hw *hw; 5695 uint32_t ctrl; 5696 uint16_t phy_ctrl; 5697 5698 hw = &Adapter->shared; 5699 5700 /* Disable Smart Power Down */ 5701 phy_spd_state(hw, B_FALSE); 5702 5703 phy_ctrl = (MII_CR_FULL_DUPLEX | 5704 MII_CR_SPEED_10); 5705 5706 /* Force 10/FD, reset PHY */ 5707 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5708 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5709 msec_delay(10); 5710 5711 /* Force 10/FD */ 5712 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5713 phy_ctrl); /* 0x0100 */ 5714 msec_delay(10); 5715 5716 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5717 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5718 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5719 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5720 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5721 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5722 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5723 E1000_CTRL_FD); /* Force Duplex to FULL */ 5724 5725 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5726 } 5727 5728 #ifdef __sparc 5729 static boolean_t 5730 e1000g_find_mac_address(struct e1000g *Adapter) 5731 { 5732 struct e1000_hw *hw = &Adapter->shared; 5733 uchar_t *bytes; 5734 struct ether_addr sysaddr; 5735 uint_t nelts; 5736 int err; 5737 boolean_t found = B_FALSE; 5738 5739 /* 5740 * The "vendor's factory-set address" may already have 5741 * been extracted from the chip, but if the property 5742 * "local-mac-address" is set we use that instead. 5743 * 5744 * We check whether it looks like an array of 6 5745 * bytes (which it should, if OBP set it). If we can't 5746 * make sense of it this way, we'll ignore it. 5747 */ 5748 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5749 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5750 if (err == DDI_PROP_SUCCESS) { 5751 if (nelts == ETHERADDRL) { 5752 while (nelts--) 5753 hw->mac.addr[nelts] = bytes[nelts]; 5754 found = B_TRUE; 5755 } 5756 ddi_prop_free(bytes); 5757 } 5758 5759 /* 5760 * Look up the OBP property "local-mac-address?". If the user has set 5761 * 'local-mac-address? = false', use "the system address" instead. 5762 */ 5763 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5764 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5765 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5766 if (localetheraddr(NULL, &sysaddr) != 0) { 5767 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5768 found = B_TRUE; 5769 } 5770 } 5771 ddi_prop_free(bytes); 5772 } 5773 5774 /* 5775 * Finally(!), if there's a valid "mac-address" property (created 5776 * if we netbooted from this interface), we must use this instead 5777 * of any of the above to ensure that the NFS/install server doesn't 5778 * get confused by the address changing as Solaris takes over! 5779 */ 5780 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5781 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5782 if (err == DDI_PROP_SUCCESS) { 5783 if (nelts == ETHERADDRL) { 5784 while (nelts--) 5785 hw->mac.addr[nelts] = bytes[nelts]; 5786 found = B_TRUE; 5787 } 5788 ddi_prop_free(bytes); 5789 } 5790 5791 if (found) { 5792 bcopy(hw->mac.addr, hw->mac.perm_addr, 5793 ETHERADDRL); 5794 } 5795 5796 return (found); 5797 } 5798 #endif 5799 5800 static int 5801 e1000g_add_intrs(struct e1000g *Adapter) 5802 { 5803 dev_info_t *devinfo; 5804 int intr_types; 5805 int rc; 5806 5807 devinfo = Adapter->dip; 5808 5809 /* Get supported interrupt types */ 5810 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5811 5812 if (rc != DDI_SUCCESS) { 5813 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5814 "Get supported interrupt types failed: %d\n", rc); 5815 return (DDI_FAILURE); 5816 } 5817 5818 /* 5819 * Based on Intel Technical Advisory document (TA-160), there are some 5820 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5821 * that it supports MSI, but in fact has problems. 5822 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5823 * PCI/PCI-X NICs. 5824 */ 5825 if (Adapter->shared.mac.type < e1000_82571) 5826 Adapter->msi_enable = B_FALSE; 5827 5828 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5829 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5830 5831 if (rc != DDI_SUCCESS) { 5832 /* EMPTY */ 5833 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5834 "Add MSI failed, trying Legacy interrupts\n"); 5835 } else { 5836 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5837 } 5838 } 5839 5840 if ((Adapter->intr_type == 0) && 5841 (intr_types & DDI_INTR_TYPE_FIXED)) { 5842 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5843 5844 if (rc != DDI_SUCCESS) { 5845 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5846 "Add Legacy interrupts failed\n"); 5847 return (DDI_FAILURE); 5848 } 5849 5850 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5851 } 5852 5853 if (Adapter->intr_type == 0) { 5854 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5855 "No interrupts registered\n"); 5856 return (DDI_FAILURE); 5857 } 5858 5859 return (DDI_SUCCESS); 5860 } 5861 5862 /* 5863 * e1000g_intr_add() handles MSI/Legacy interrupts 5864 */ 5865 static int 5866 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5867 { 5868 dev_info_t *devinfo; 5869 int count, avail, actual; 5870 int x, y, rc, inum = 0; 5871 int flag; 5872 ddi_intr_handler_t *intr_handler; 5873 5874 devinfo = Adapter->dip; 5875 5876 /* get number of interrupts */ 5877 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5878 if ((rc != DDI_SUCCESS) || (count == 0)) { 5879 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5880 "Get interrupt number failed. Return: %d, count: %d\n", 5881 rc, count); 5882 return (DDI_FAILURE); 5883 } 5884 5885 /* get number of available interrupts */ 5886 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5887 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5888 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5889 "Get interrupt available number failed. " 5890 "Return: %d, available: %d\n", rc, avail); 5891 return (DDI_FAILURE); 5892 } 5893 5894 if (avail < count) { 5895 /* EMPTY */ 5896 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5897 "Interrupts count: %d, available: %d\n", 5898 count, avail); 5899 } 5900 5901 /* Allocate an array of interrupt handles */ 5902 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5903 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5904 5905 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5906 flag = DDI_INTR_ALLOC_NORMAL; 5907 5908 /* call ddi_intr_alloc() */ 5909 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5910 count, &actual, flag); 5911 5912 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5913 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5914 "Allocate interrupts failed: %d\n", rc); 5915 5916 kmem_free(Adapter->htable, Adapter->intr_size); 5917 return (DDI_FAILURE); 5918 } 5919 5920 if (actual < count) { 5921 /* EMPTY */ 5922 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5923 "Interrupts requested: %d, received: %d\n", 5924 count, actual); 5925 } 5926 5927 Adapter->intr_cnt = actual; 5928 5929 /* Get priority for first msi, assume remaining are all the same */ 5930 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5931 5932 if (rc != DDI_SUCCESS) { 5933 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5934 "Get interrupt priority failed: %d\n", rc); 5935 5936 /* Free already allocated intr */ 5937 for (y = 0; y < actual; y++) 5938 (void) ddi_intr_free(Adapter->htable[y]); 5939 5940 kmem_free(Adapter->htable, Adapter->intr_size); 5941 return (DDI_FAILURE); 5942 } 5943 5944 /* 5945 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5946 * use the interrupt service routine e1000g_intr_pciexpress() 5947 * to avoid interrupt stealing when sharing interrupt with other 5948 * devices. 5949 */ 5950 if (Adapter->shared.mac.type < e1000_82571) 5951 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5952 else 5953 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5954 5955 /* Call ddi_intr_add_handler() */ 5956 for (x = 0; x < actual; x++) { 5957 rc = ddi_intr_add_handler(Adapter->htable[x], 5958 intr_handler, (caddr_t)Adapter, NULL); 5959 5960 if (rc != DDI_SUCCESS) { 5961 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5962 "Add interrupt handler failed: %d\n", rc); 5963 5964 /* Remove already added handler */ 5965 for (y = 0; y < x; y++) 5966 (void) ddi_intr_remove_handler( 5967 Adapter->htable[y]); 5968 5969 /* Free already allocated intr */ 5970 for (y = 0; y < actual; y++) 5971 (void) ddi_intr_free(Adapter->htable[y]); 5972 5973 kmem_free(Adapter->htable, Adapter->intr_size); 5974 return (DDI_FAILURE); 5975 } 5976 } 5977 5978 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5979 5980 if (rc != DDI_SUCCESS) { 5981 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5982 "Get interrupt cap failed: %d\n", rc); 5983 5984 /* Free already allocated intr */ 5985 for (y = 0; y < actual; y++) { 5986 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5987 (void) ddi_intr_free(Adapter->htable[y]); 5988 } 5989 5990 kmem_free(Adapter->htable, Adapter->intr_size); 5991 return (DDI_FAILURE); 5992 } 5993 5994 return (DDI_SUCCESS); 5995 } 5996 5997 static int 5998 e1000g_rem_intrs(struct e1000g *Adapter) 5999 { 6000 int x; 6001 int rc; 6002 6003 for (x = 0; x < Adapter->intr_cnt; x++) { 6004 rc = ddi_intr_remove_handler(Adapter->htable[x]); 6005 if (rc != DDI_SUCCESS) { 6006 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6007 "Remove intr handler failed: %d\n", rc); 6008 return (DDI_FAILURE); 6009 } 6010 6011 rc = ddi_intr_free(Adapter->htable[x]); 6012 if (rc != DDI_SUCCESS) { 6013 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6014 "Free intr failed: %d\n", rc); 6015 return (DDI_FAILURE); 6016 } 6017 } 6018 6019 kmem_free(Adapter->htable, Adapter->intr_size); 6020 6021 return (DDI_SUCCESS); 6022 } 6023 6024 static int 6025 e1000g_enable_intrs(struct e1000g *Adapter) 6026 { 6027 int x; 6028 int rc; 6029 6030 /* Enable interrupts */ 6031 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6032 /* Call ddi_intr_block_enable() for MSI */ 6033 rc = ddi_intr_block_enable(Adapter->htable, 6034 Adapter->intr_cnt); 6035 if (rc != DDI_SUCCESS) { 6036 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6037 "Enable block intr failed: %d\n", rc); 6038 return (DDI_FAILURE); 6039 } 6040 } else { 6041 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 6042 for (x = 0; x < Adapter->intr_cnt; x++) { 6043 rc = ddi_intr_enable(Adapter->htable[x]); 6044 if (rc != DDI_SUCCESS) { 6045 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6046 "Enable intr failed: %d\n", rc); 6047 return (DDI_FAILURE); 6048 } 6049 } 6050 } 6051 6052 return (DDI_SUCCESS); 6053 } 6054 6055 static int 6056 e1000g_disable_intrs(struct e1000g *Adapter) 6057 { 6058 int x; 6059 int rc; 6060 6061 /* Disable all interrupts */ 6062 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6063 rc = ddi_intr_block_disable(Adapter->htable, 6064 Adapter->intr_cnt); 6065 if (rc != DDI_SUCCESS) { 6066 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6067 "Disable block intr failed: %d\n", rc); 6068 return (DDI_FAILURE); 6069 } 6070 } else { 6071 for (x = 0; x < Adapter->intr_cnt; x++) { 6072 rc = ddi_intr_disable(Adapter->htable[x]); 6073 if (rc != DDI_SUCCESS) { 6074 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6075 "Disable intr failed: %d\n", rc); 6076 return (DDI_FAILURE); 6077 } 6078 } 6079 } 6080 6081 return (DDI_SUCCESS); 6082 } 6083 6084 /* 6085 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 6086 */ 6087 static void 6088 e1000g_get_phy_state(struct e1000g *Adapter) 6089 { 6090 struct e1000_hw *hw = &Adapter->shared; 6091 6092 if (hw->phy.media_type == e1000_media_type_copper) { 6093 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 6094 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 6095 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 6096 &Adapter->phy_an_adv); 6097 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 6098 &Adapter->phy_an_exp); 6099 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 6100 &Adapter->phy_ext_status); 6101 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 6102 &Adapter->phy_1000t_ctrl); 6103 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 6104 &Adapter->phy_1000t_status); 6105 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 6106 &Adapter->phy_lp_able); 6107 6108 Adapter->param_autoneg_cap = 6109 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 6110 Adapter->param_pause_cap = 6111 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6112 Adapter->param_asym_pause_cap = 6113 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6114 Adapter->param_1000fdx_cap = 6115 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 6116 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 6117 Adapter->param_1000hdx_cap = 6118 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 6119 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 6120 Adapter->param_100t4_cap = 6121 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 6122 Adapter->param_100fdx_cap = 6123 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6124 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 6125 Adapter->param_100hdx_cap = 6126 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6127 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6128 Adapter->param_10fdx_cap = 6129 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6130 Adapter->param_10hdx_cap = 6131 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6132 6133 Adapter->param_adv_autoneg = hw->mac.autoneg; 6134 Adapter->param_adv_pause = 6135 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6136 Adapter->param_adv_asym_pause = 6137 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6138 Adapter->param_adv_1000hdx = 6139 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 6140 Adapter->param_adv_100t4 = 6141 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 6142 if (Adapter->param_adv_autoneg == 1) { 6143 Adapter->param_adv_1000fdx = 6144 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 6145 ? 1 : 0; 6146 Adapter->param_adv_100fdx = 6147 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 6148 ? 1 : 0; 6149 Adapter->param_adv_100hdx = 6150 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 6151 ? 1 : 0; 6152 Adapter->param_adv_10fdx = 6153 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 6154 Adapter->param_adv_10hdx = 6155 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 6156 } 6157 6158 Adapter->param_lp_autoneg = 6159 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 6160 Adapter->param_lp_pause = 6161 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 6162 Adapter->param_lp_asym_pause = 6163 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 6164 Adapter->param_lp_1000fdx = 6165 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 6166 Adapter->param_lp_1000hdx = 6167 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 6168 Adapter->param_lp_100t4 = 6169 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 6170 Adapter->param_lp_100fdx = 6171 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 6172 Adapter->param_lp_100hdx = 6173 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 6174 Adapter->param_lp_10fdx = 6175 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 6176 Adapter->param_lp_10hdx = 6177 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 6178 } else { 6179 /* 6180 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 6181 * it can only work with 1Gig Full Duplex Link Partner. 6182 */ 6183 Adapter->param_autoneg_cap = 0; 6184 Adapter->param_pause_cap = 1; 6185 Adapter->param_asym_pause_cap = 1; 6186 Adapter->param_1000fdx_cap = 1; 6187 Adapter->param_1000hdx_cap = 0; 6188 Adapter->param_100t4_cap = 0; 6189 Adapter->param_100fdx_cap = 0; 6190 Adapter->param_100hdx_cap = 0; 6191 Adapter->param_10fdx_cap = 0; 6192 Adapter->param_10hdx_cap = 0; 6193 6194 Adapter->param_adv_autoneg = 0; 6195 Adapter->param_adv_pause = 1; 6196 Adapter->param_adv_asym_pause = 1; 6197 Adapter->param_adv_1000fdx = 1; 6198 Adapter->param_adv_1000hdx = 0; 6199 Adapter->param_adv_100t4 = 0; 6200 Adapter->param_adv_100fdx = 0; 6201 Adapter->param_adv_100hdx = 0; 6202 Adapter->param_adv_10fdx = 0; 6203 Adapter->param_adv_10hdx = 0; 6204 6205 Adapter->param_lp_autoneg = 0; 6206 Adapter->param_lp_pause = 0; 6207 Adapter->param_lp_asym_pause = 0; 6208 Adapter->param_lp_1000fdx = 0; 6209 Adapter->param_lp_1000hdx = 0; 6210 Adapter->param_lp_100t4 = 0; 6211 Adapter->param_lp_100fdx = 0; 6212 Adapter->param_lp_100hdx = 0; 6213 Adapter->param_lp_10fdx = 0; 6214 Adapter->param_lp_10hdx = 0; 6215 } 6216 } 6217 6218 /* 6219 * FMA support 6220 */ 6221 6222 int 6223 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6224 { 6225 ddi_fm_error_t de; 6226 6227 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6228 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6229 return (de.fme_status); 6230 } 6231 6232 int 6233 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6234 { 6235 ddi_fm_error_t de; 6236 6237 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6238 return (de.fme_status); 6239 } 6240 6241 /* 6242 * The IO fault service error handling callback function 6243 */ 6244 /* ARGSUSED2 */ 6245 static int 6246 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6247 { 6248 /* 6249 * as the driver can always deal with an error in any dma or 6250 * access handle, we can just return the fme_status value. 6251 */ 6252 pci_ereport_post(dip, err, NULL); 6253 return (err->fme_status); 6254 } 6255 6256 static void 6257 e1000g_fm_init(struct e1000g *Adapter) 6258 { 6259 ddi_iblock_cookie_t iblk; 6260 int fma_dma_flag; 6261 6262 /* Only register with IO Fault Services if we have some capability */ 6263 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6264 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6265 } else { 6266 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6267 } 6268 6269 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6270 fma_dma_flag = 1; 6271 } else { 6272 fma_dma_flag = 0; 6273 } 6274 6275 (void) e1000g_set_fma_flags(fma_dma_flag); 6276 6277 if (Adapter->fm_capabilities) { 6278 6279 /* Register capabilities with IO Fault Services */ 6280 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6281 6282 /* 6283 * Initialize pci ereport capabilities if ereport capable 6284 */ 6285 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6286 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6287 pci_ereport_setup(Adapter->dip); 6288 6289 /* 6290 * Register error callback if error callback capable 6291 */ 6292 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6293 ddi_fm_handler_register(Adapter->dip, 6294 e1000g_fm_error_cb, (void*) Adapter); 6295 } 6296 } 6297 6298 static void 6299 e1000g_fm_fini(struct e1000g *Adapter) 6300 { 6301 /* Only unregister FMA capabilities if we registered some */ 6302 if (Adapter->fm_capabilities) { 6303 6304 /* 6305 * Release any resources allocated by pci_ereport_setup() 6306 */ 6307 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6308 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6309 pci_ereport_teardown(Adapter->dip); 6310 6311 /* 6312 * Un-register error callback if error callback capable 6313 */ 6314 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6315 ddi_fm_handler_unregister(Adapter->dip); 6316 6317 /* Unregister from IO Fault Services */ 6318 mutex_enter(&e1000g_rx_detach_lock); 6319 ddi_fm_fini(Adapter->dip); 6320 if (Adapter->priv_dip != NULL) { 6321 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6322 } 6323 mutex_exit(&e1000g_rx_detach_lock); 6324 } 6325 } 6326 6327 void 6328 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6329 { 6330 uint64_t ena; 6331 char buf[FM_MAX_CLASS]; 6332 6333 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6334 ena = fm_ena_generate(0, FM_ENA_FMT1); 6335 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6336 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6337 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6338 } 6339 } 6340 6341 /* 6342 * quiesce(9E) entry point. 6343 * 6344 * This function is called when the system is single-threaded at high 6345 * PIL with preemption disabled. Therefore, this function must not be 6346 * blocked. 6347 * 6348 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6349 * DDI_FAILURE indicates an error condition and should almost never happen. 6350 */ 6351 static int 6352 e1000g_quiesce(dev_info_t *devinfo) 6353 { 6354 struct e1000g *Adapter; 6355 6356 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6357 6358 if (Adapter == NULL) 6359 return (DDI_FAILURE); 6360 6361 e1000g_clear_all_interrupts(Adapter); 6362 6363 (void) e1000_reset_hw(&Adapter->shared); 6364 6365 /* Setup our HW Tx Head & Tail descriptor pointers */ 6366 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6367 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6368 6369 /* Setup our HW Rx Head & Tail descriptor pointers */ 6370 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6371 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6372 6373 return (DDI_SUCCESS); 6374 } 6375 6376 /* 6377 * synchronize the adv* and en* parameters. 6378 * 6379 * See comments in <sys/dld.h> for details of the *_en_* 6380 * parameters. The usage of ndd for setting adv parameters will 6381 * synchronize all the en parameters with the e1000g parameters, 6382 * implicitly disabling any settings made via dladm. 6383 */ 6384 static void 6385 e1000g_param_sync(struct e1000g *Adapter) 6386 { 6387 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6388 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6389 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6390 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6391 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6392 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6393 } 6394 6395 /* 6396 * e1000g_get_driver_control - tell manageability firmware that the driver 6397 * has control. 6398 */ 6399 static void 6400 e1000g_get_driver_control(struct e1000_hw *hw) 6401 { 6402 uint32_t ctrl_ext; 6403 uint32_t swsm; 6404 6405 /* tell manageability firmware the driver has taken over */ 6406 switch (hw->mac.type) { 6407 case e1000_82573: 6408 swsm = E1000_READ_REG(hw, E1000_SWSM); 6409 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6410 break; 6411 case e1000_82571: 6412 case e1000_82572: 6413 case e1000_82574: 6414 case e1000_80003es2lan: 6415 case e1000_ich8lan: 6416 case e1000_ich9lan: 6417 case e1000_ich10lan: 6418 case e1000_pchlan: 6419 case e1000_pch2lan: 6420 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6421 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6422 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6423 break; 6424 default: 6425 /* no manageability firmware: do nothing */ 6426 break; 6427 } 6428 } 6429 6430 /* 6431 * e1000g_release_driver_control - tell manageability firmware that the driver 6432 * has released control. 6433 */ 6434 static void 6435 e1000g_release_driver_control(struct e1000_hw *hw) 6436 { 6437 uint32_t ctrl_ext; 6438 uint32_t swsm; 6439 6440 /* tell manageability firmware the driver has released control */ 6441 switch (hw->mac.type) { 6442 case e1000_82573: 6443 swsm = E1000_READ_REG(hw, E1000_SWSM); 6444 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6445 break; 6446 case e1000_82571: 6447 case e1000_82572: 6448 case e1000_82574: 6449 case e1000_80003es2lan: 6450 case e1000_ich8lan: 6451 case e1000_ich9lan: 6452 case e1000_ich10lan: 6453 case e1000_pchlan: 6454 case e1000_pch2lan: 6455 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6456 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6457 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6458 break; 6459 default: 6460 /* no manageability firmware: do nothing */ 6461 break; 6462 } 6463 } 6464 6465 /* 6466 * Restore e1000g promiscuous mode. 6467 */ 6468 static void 6469 e1000g_restore_promisc(struct e1000g *Adapter) 6470 { 6471 if (Adapter->e1000g_promisc) { 6472 uint32_t rctl; 6473 6474 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6475 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6476 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6477 } 6478 } 6479