1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 49 /* 50 * Proto types for DDI entry points 51 */ 52 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 53 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 54 static int e1000g_quiesce(dev_info_t *); 55 56 /* 57 * init and intr routines prototype 58 */ 59 static int e1000g_resume(dev_info_t *); 60 static int e1000g_suspend(dev_info_t *); 61 static uint_t e1000g_intr_pciexpress(caddr_t); 62 static uint_t e1000g_intr(caddr_t); 63 static void e1000g_intr_work(struct e1000g *, uint32_t); 64 #pragma inline(e1000g_intr_work) 65 static int e1000g_init(struct e1000g *); 66 static int e1000g_start(struct e1000g *, boolean_t); 67 static void e1000g_stop(struct e1000g *, boolean_t); 68 static int e1000g_m_start(void *); 69 static void e1000g_m_stop(void *); 70 static int e1000g_m_promisc(void *, boolean_t); 71 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 72 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 73 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 74 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 75 uint_t, const void *); 76 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 77 uint_t, void *); 78 static void e1000g_m_propinfo(void *, const char *, mac_prop_id_t, 79 mac_prop_info_handle_t); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, void *); 83 static void e1000g_init_locks(struct e1000g *); 84 static void e1000g_destroy_locks(struct e1000g *); 85 static int e1000g_identify_hardware(struct e1000g *); 86 static int e1000g_regs_map(struct e1000g *); 87 static int e1000g_set_driver_params(struct e1000g *); 88 static void e1000g_set_bufsize(struct e1000g *); 89 static int e1000g_register_mac(struct e1000g *); 90 static boolean_t e1000g_rx_drain(struct e1000g *); 91 static boolean_t e1000g_tx_drain(struct e1000g *); 92 static void e1000g_init_unicst(struct e1000g *); 93 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 94 static int e1000g_alloc_rx_data(struct e1000g *); 95 static void e1000g_release_multicast(struct e1000g *); 96 static void e1000g_pch_limits(struct e1000g *); 97 static uint32_t e1000g_mtu2maxframe(uint32_t); 98 99 /* 100 * Local routines 101 */ 102 static boolean_t e1000g_reset_adapter(struct e1000g *); 103 static void e1000g_tx_clean(struct e1000g *); 104 static void e1000g_rx_clean(struct e1000g *); 105 static void e1000g_link_timer(void *); 106 static void e1000g_local_timer(void *); 107 static boolean_t e1000g_link_check(struct e1000g *); 108 static boolean_t e1000g_stall_check(struct e1000g *); 109 static void e1000g_smartspeed(struct e1000g *); 110 static void e1000g_get_conf(struct e1000g *); 111 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 112 int *); 113 static void enable_watchdog_timer(struct e1000g *); 114 static void disable_watchdog_timer(struct e1000g *); 115 static void start_watchdog_timer(struct e1000g *); 116 static void restart_watchdog_timer(struct e1000g *); 117 static void stop_watchdog_timer(struct e1000g *); 118 static void stop_link_timer(struct e1000g *); 119 static void stop_82547_timer(e1000g_tx_ring_t *); 120 static void e1000g_force_speed_duplex(struct e1000g *); 121 static void e1000g_setup_max_mtu(struct e1000g *); 122 static void e1000g_get_max_frame_size(struct e1000g *); 123 static boolean_t is_valid_mac_addr(uint8_t *); 124 static void e1000g_unattach(dev_info_t *, struct e1000g *); 125 static int e1000g_get_bar_info(dev_info_t *, int, bar_info_t *); 126 #ifdef E1000G_DEBUG 127 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 128 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 132 struct iocblk *, mblk_t *); 133 #endif 134 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 135 struct iocblk *, mblk_t *); 136 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 137 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 138 static void e1000g_set_internal_loopback(struct e1000g *); 139 static void e1000g_set_external_loopback_1000(struct e1000g *); 140 static void e1000g_set_external_loopback_100(struct e1000g *); 141 static void e1000g_set_external_loopback_10(struct e1000g *); 142 static int e1000g_add_intrs(struct e1000g *); 143 static int e1000g_intr_add(struct e1000g *, int); 144 static int e1000g_rem_intrs(struct e1000g *); 145 static int e1000g_enable_intrs(struct e1000g *); 146 static int e1000g_disable_intrs(struct e1000g *); 147 static boolean_t e1000g_link_up(struct e1000g *); 148 #ifdef __sparc 149 static boolean_t e1000g_find_mac_address(struct e1000g *); 150 #endif 151 static void e1000g_get_phy_state(struct e1000g *); 152 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 153 const void *impl_data); 154 static void e1000g_fm_init(struct e1000g *Adapter); 155 static void e1000g_fm_fini(struct e1000g *Adapter); 156 static void e1000g_param_sync(struct e1000g *); 157 static void e1000g_get_driver_control(struct e1000_hw *); 158 static void e1000g_release_driver_control(struct e1000_hw *); 159 static void e1000g_restore_promisc(struct e1000g *Adapter); 160 161 char *e1000g_priv_props[] = { 162 "_tx_bcopy_threshold", 163 "_tx_interrupt_enable", 164 "_tx_intr_delay", 165 "_tx_intr_abs_delay", 166 "_rx_bcopy_threshold", 167 "_max_num_rcv_packets", 168 "_rx_intr_delay", 169 "_rx_intr_abs_delay", 170 "_intr_throttling_rate", 171 "_intr_adaptive", 172 "_adv_pause_cap", 173 "_adv_asym_pause_cap", 174 NULL 175 }; 176 177 static struct cb_ops cb_ws_ops = { 178 nulldev, /* cb_open */ 179 nulldev, /* cb_close */ 180 nodev, /* cb_strategy */ 181 nodev, /* cb_print */ 182 nodev, /* cb_dump */ 183 nodev, /* cb_read */ 184 nodev, /* cb_write */ 185 nodev, /* cb_ioctl */ 186 nodev, /* cb_devmap */ 187 nodev, /* cb_mmap */ 188 nodev, /* cb_segmap */ 189 nochpoll, /* cb_chpoll */ 190 ddi_prop_op, /* cb_prop_op */ 191 NULL, /* cb_stream */ 192 D_MP | D_HOTPLUG, /* cb_flag */ 193 CB_REV, /* cb_rev */ 194 nodev, /* cb_aread */ 195 nodev /* cb_awrite */ 196 }; 197 198 static struct dev_ops ws_ops = { 199 DEVO_REV, /* devo_rev */ 200 0, /* devo_refcnt */ 201 NULL, /* devo_getinfo */ 202 nulldev, /* devo_identify */ 203 nulldev, /* devo_probe */ 204 e1000g_attach, /* devo_attach */ 205 e1000g_detach, /* devo_detach */ 206 nodev, /* devo_reset */ 207 &cb_ws_ops, /* devo_cb_ops */ 208 NULL, /* devo_bus_ops */ 209 ddi_power, /* devo_power */ 210 e1000g_quiesce /* devo_quiesce */ 211 }; 212 213 static struct modldrv modldrv = { 214 &mod_driverops, /* Type of module. This one is a driver */ 215 ident, /* Discription string */ 216 &ws_ops, /* driver ops */ 217 }; 218 219 static struct modlinkage modlinkage = { 220 MODREV_1, &modldrv, NULL 221 }; 222 223 /* Access attributes for register mapping */ 224 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 225 DDI_DEVICE_ATTR_V1, 226 DDI_STRUCTURE_LE_ACC, 227 DDI_STRICTORDER_ACC, 228 DDI_FLAGERR_ACC 229 }; 230 231 #define E1000G_M_CALLBACK_FLAGS \ 232 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 233 234 static mac_callbacks_t e1000g_m_callbacks = { 235 E1000G_M_CALLBACK_FLAGS, 236 e1000g_m_stat, 237 e1000g_m_start, 238 e1000g_m_stop, 239 e1000g_m_promisc, 240 e1000g_m_multicst, 241 NULL, 242 e1000g_m_tx, 243 NULL, 244 e1000g_m_ioctl, 245 e1000g_m_getcapab, 246 NULL, 247 NULL, 248 e1000g_m_setprop, 249 e1000g_m_getprop, 250 e1000g_m_propinfo 251 }; 252 253 /* 254 * Global variables 255 */ 256 uint32_t e1000g_mblks_pending = 0; 257 /* 258 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 259 * Here we maintain a private dev_info list if e1000g_force_detach is 260 * enabled. If we force the driver to detach while there are still some 261 * rx buffers retained in the upper layer, we have to keep a copy of the 262 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 263 * structure will be freed after the driver is detached. However when we 264 * finally free those rx buffers released by the upper layer, we need to 265 * refer to the dev_info to free the dma buffers. So we save a copy of 266 * the dev_info for this purpose. On x86 platform, we assume this copy 267 * of dev_info is always valid, but on SPARC platform, it could be invalid 268 * after the system board level DR operation. For this reason, the global 269 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 270 */ 271 #ifdef __sparc 272 boolean_t e1000g_force_detach = B_FALSE; 273 #else 274 boolean_t e1000g_force_detach = B_TRUE; 275 #endif 276 private_devi_list_t *e1000g_private_devi_list = NULL; 277 278 /* 279 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 280 * the private dev_info list, and to serialize the processing of rx buffer 281 * freeing and rx buffer recycling. 282 */ 283 kmutex_t e1000g_rx_detach_lock; 284 /* 285 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 286 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 287 * If there are many e1000g instances, the system may run out of DVMA 288 * resources during the initialization of the instances, then the flag will 289 * be changed to "USE_DMA". Because different e1000g instances are initialized 290 * in parallel, we need to use this lock to protect the flag. 291 */ 292 krwlock_t e1000g_dma_type_lock; 293 294 /* 295 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 296 * Based on the information from Intel, the 82546 chipset has some hardware 297 * problem. When one port is being reset and the other port is trying to 298 * access the eeprom, it could cause system hang or panic. To workaround this 299 * hardware problem, we use a global mutex to prevent such operations from 300 * happening simultaneously on different instances. This workaround is applied 301 * to all the devices supported by this driver. 302 */ 303 kmutex_t e1000g_nvm_lock; 304 305 /* 306 * Loadable module configuration entry points for the driver 307 */ 308 309 /* 310 * _init - module initialization 311 */ 312 int 313 _init(void) 314 { 315 int status; 316 317 mac_init_ops(&ws_ops, WSNAME); 318 status = mod_install(&modlinkage); 319 if (status != DDI_SUCCESS) 320 mac_fini_ops(&ws_ops); 321 else { 322 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 323 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 324 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 325 } 326 327 return (status); 328 } 329 330 /* 331 * _fini - module finalization 332 */ 333 int 334 _fini(void) 335 { 336 int status; 337 338 if (e1000g_mblks_pending != 0) 339 return (EBUSY); 340 341 status = mod_remove(&modlinkage); 342 if (status == DDI_SUCCESS) { 343 mac_fini_ops(&ws_ops); 344 345 if (e1000g_force_detach) { 346 private_devi_list_t *devi_node; 347 348 mutex_enter(&e1000g_rx_detach_lock); 349 while (e1000g_private_devi_list != NULL) { 350 devi_node = e1000g_private_devi_list; 351 e1000g_private_devi_list = 352 e1000g_private_devi_list->next; 353 354 kmem_free(devi_node->priv_dip, 355 sizeof (struct dev_info)); 356 kmem_free(devi_node, 357 sizeof (private_devi_list_t)); 358 } 359 mutex_exit(&e1000g_rx_detach_lock); 360 } 361 362 mutex_destroy(&e1000g_rx_detach_lock); 363 rw_destroy(&e1000g_dma_type_lock); 364 mutex_destroy(&e1000g_nvm_lock); 365 } 366 367 return (status); 368 } 369 370 /* 371 * _info - module information 372 */ 373 int 374 _info(struct modinfo *modinfop) 375 { 376 return (mod_info(&modlinkage, modinfop)); 377 } 378 379 /* 380 * e1000g_attach - driver attach 381 * 382 * This function is the device-specific initialization entry 383 * point. This entry point is required and must be written. 384 * The DDI_ATTACH command must be provided in the attach entry 385 * point. When attach() is called with cmd set to DDI_ATTACH, 386 * all normal kernel services (such as kmem_alloc(9F)) are 387 * available for use by the driver. 388 * 389 * The attach() function will be called once for each instance 390 * of the device on the system with cmd set to DDI_ATTACH. 391 * Until attach() succeeds, the only driver entry points which 392 * may be called are open(9E) and getinfo(9E). 393 */ 394 static int 395 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 396 { 397 struct e1000g *Adapter; 398 struct e1000_hw *hw; 399 struct e1000g_osdep *osdep; 400 int instance; 401 402 switch (cmd) { 403 default: 404 e1000g_log(NULL, CE_WARN, 405 "Unsupported command send to e1000g_attach... "); 406 return (DDI_FAILURE); 407 408 case DDI_RESUME: 409 return (e1000g_resume(devinfo)); 410 411 case DDI_ATTACH: 412 break; 413 } 414 415 /* 416 * get device instance number 417 */ 418 instance = ddi_get_instance(devinfo); 419 420 /* 421 * Allocate soft data structure 422 */ 423 Adapter = 424 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 425 426 Adapter->dip = devinfo; 427 Adapter->instance = instance; 428 Adapter->tx_ring->adapter = Adapter; 429 Adapter->rx_ring->adapter = Adapter; 430 431 hw = &Adapter->shared; 432 osdep = &Adapter->osdep; 433 hw->back = osdep; 434 osdep->adapter = Adapter; 435 436 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 437 438 /* 439 * Initialize for fma support 440 */ 441 (void) e1000g_get_prop(Adapter, "fm-capable", 442 0, 0x0f, 443 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 444 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 445 &Adapter->fm_capabilities); 446 e1000g_fm_init(Adapter); 447 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 448 449 /* 450 * PCI Configure 451 */ 452 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 453 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 454 goto attach_fail; 455 } 456 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 457 458 /* 459 * Setup hardware 460 */ 461 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 462 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 463 goto attach_fail; 464 } 465 466 /* 467 * Map in the device registers. 468 */ 469 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 470 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 471 goto attach_fail; 472 } 473 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 474 475 /* 476 * Initialize driver parameters 477 */ 478 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 479 goto attach_fail; 480 } 481 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 482 483 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 484 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 485 goto attach_fail; 486 } 487 488 /* 489 * Initialize interrupts 490 */ 491 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 492 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 493 goto attach_fail; 494 } 495 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 496 497 /* 498 * Initialize mutex's for this device. 499 * Do this before enabling the interrupt handler and 500 * register the softint to avoid the condition where 501 * interrupt handler can try using uninitialized mutex 502 */ 503 e1000g_init_locks(Adapter); 504 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 505 506 /* 507 * Initialize Driver Counters 508 */ 509 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 510 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 511 goto attach_fail; 512 } 513 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 514 515 /* 516 * Initialize chip hardware and software structures 517 */ 518 rw_enter(&Adapter->chip_lock, RW_WRITER); 519 if (e1000g_init(Adapter) != DDI_SUCCESS) { 520 rw_exit(&Adapter->chip_lock); 521 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 522 goto attach_fail; 523 } 524 rw_exit(&Adapter->chip_lock); 525 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 526 527 /* 528 * Register the driver to the MAC 529 */ 530 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 531 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 532 goto attach_fail; 533 } 534 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 535 536 /* 537 * Now that mutex locks are initialized, and the chip is also 538 * initialized, enable interrupts. 539 */ 540 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 541 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 542 goto attach_fail; 543 } 544 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 545 546 /* 547 * If e1000g_force_detach is enabled, in global private dip list, 548 * we will create a new entry, which maintains the priv_dip for DR 549 * supports after driver detached. 550 */ 551 if (e1000g_force_detach) { 552 private_devi_list_t *devi_node; 553 554 Adapter->priv_dip = 555 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 556 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 557 sizeof (struct dev_info)); 558 559 devi_node = 560 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 561 562 mutex_enter(&e1000g_rx_detach_lock); 563 devi_node->priv_dip = Adapter->priv_dip; 564 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 565 devi_node->pending_rx_count = 0; 566 567 Adapter->priv_devi_node = devi_node; 568 569 if (e1000g_private_devi_list == NULL) { 570 devi_node->prev = NULL; 571 devi_node->next = NULL; 572 e1000g_private_devi_list = devi_node; 573 } else { 574 devi_node->prev = NULL; 575 devi_node->next = e1000g_private_devi_list; 576 e1000g_private_devi_list->prev = devi_node; 577 e1000g_private_devi_list = devi_node; 578 } 579 mutex_exit(&e1000g_rx_detach_lock); 580 } 581 582 Adapter->e1000g_state = E1000G_INITIALIZED; 583 584 return (DDI_SUCCESS); 585 586 attach_fail: 587 e1000g_unattach(devinfo, Adapter); 588 return (DDI_FAILURE); 589 } 590 591 static int 592 e1000g_register_mac(struct e1000g *Adapter) 593 { 594 struct e1000_hw *hw = &Adapter->shared; 595 mac_register_t *mac; 596 int err; 597 598 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 599 return (DDI_FAILURE); 600 601 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 602 mac->m_driver = Adapter; 603 mac->m_dip = Adapter->dip; 604 mac->m_src_addr = hw->mac.addr; 605 mac->m_callbacks = &e1000g_m_callbacks; 606 mac->m_min_sdu = 0; 607 mac->m_max_sdu = Adapter->default_mtu; 608 mac->m_margin = VLAN_TAGSZ; 609 mac->m_priv_props = e1000g_priv_props; 610 mac->m_v12n = MAC_VIRT_LEVEL1; 611 612 err = mac_register(mac, &Adapter->mh); 613 mac_free(mac); 614 615 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 616 } 617 618 static int 619 e1000g_identify_hardware(struct e1000g *Adapter) 620 { 621 struct e1000_hw *hw = &Adapter->shared; 622 struct e1000g_osdep *osdep = &Adapter->osdep; 623 624 /* Get the device id */ 625 hw->vendor_id = 626 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 627 hw->device_id = 628 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 629 hw->revision_id = 630 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 631 hw->subsystem_device_id = 632 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 633 hw->subsystem_vendor_id = 634 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 635 636 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 637 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 638 "MAC type could not be set properly."); 639 return (DDI_FAILURE); 640 } 641 642 return (DDI_SUCCESS); 643 } 644 645 static int 646 e1000g_regs_map(struct e1000g *Adapter) 647 { 648 dev_info_t *devinfo = Adapter->dip; 649 struct e1000_hw *hw = &Adapter->shared; 650 struct e1000g_osdep *osdep = &Adapter->osdep; 651 off_t mem_size; 652 bar_info_t bar_info; 653 int offset, rnumber; 654 655 rnumber = ADAPTER_REG_SET; 656 /* Get size of adapter register memory */ 657 if (ddi_dev_regsize(devinfo, rnumber, &mem_size) != 658 DDI_SUCCESS) { 659 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 660 "ddi_dev_regsize for registers failed"); 661 return (DDI_FAILURE); 662 } 663 664 /* Map adapter register memory */ 665 if ((ddi_regs_map_setup(devinfo, rnumber, 666 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 667 &osdep->reg_handle)) != DDI_SUCCESS) { 668 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 669 "ddi_regs_map_setup for registers failed"); 670 goto regs_map_fail; 671 } 672 673 /* ICH needs to map flash memory */ 674 switch (hw->mac.type) { 675 case e1000_ich8lan: 676 case e1000_ich9lan: 677 case e1000_ich10lan: 678 case e1000_pchlan: 679 rnumber = ICH_FLASH_REG_SET; 680 681 /* get flash size */ 682 if (ddi_dev_regsize(devinfo, rnumber, 683 &mem_size) != DDI_SUCCESS) { 684 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 685 "ddi_dev_regsize for ICH flash failed"); 686 goto regs_map_fail; 687 } 688 689 /* map flash in */ 690 if (ddi_regs_map_setup(devinfo, rnumber, 691 (caddr_t *)&hw->flash_address, 0, 692 mem_size, &e1000g_regs_acc_attr, 693 &osdep->ich_flash_handle) != DDI_SUCCESS) { 694 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 695 "ddi_regs_map_setup for ICH flash failed"); 696 goto regs_map_fail; 697 } 698 break; 699 default: 700 break; 701 } 702 703 /* map io space */ 704 switch (hw->mac.type) { 705 case e1000_82544: 706 case e1000_82540: 707 case e1000_82545: 708 case e1000_82546: 709 case e1000_82541: 710 case e1000_82541_rev_2: 711 /* find the IO bar */ 712 rnumber = -1; 713 for (offset = PCI_CONF_BASE1; 714 offset <= PCI_CONF_BASE5; offset += 4) { 715 if (e1000g_get_bar_info(devinfo, offset, &bar_info) 716 != DDI_SUCCESS) 717 continue; 718 if (bar_info.type == E1000G_BAR_IO) { 719 rnumber = bar_info.rnumber; 720 break; 721 } 722 } 723 724 if (rnumber < 0) { 725 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 726 "No io space is found"); 727 goto regs_map_fail; 728 } 729 730 /* get io space size */ 731 if (ddi_dev_regsize(devinfo, rnumber, 732 &mem_size) != DDI_SUCCESS) { 733 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 734 "ddi_dev_regsize for io space failed"); 735 goto regs_map_fail; 736 } 737 738 /* map io space */ 739 if ((ddi_regs_map_setup(devinfo, rnumber, 740 (caddr_t *)&hw->io_base, 0, mem_size, 741 &e1000g_regs_acc_attr, 742 &osdep->io_reg_handle)) != DDI_SUCCESS) { 743 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 744 "ddi_regs_map_setup for io space failed"); 745 goto regs_map_fail; 746 } 747 break; 748 default: 749 hw->io_base = 0; 750 break; 751 } 752 753 return (DDI_SUCCESS); 754 755 regs_map_fail: 756 if (osdep->reg_handle != NULL) 757 ddi_regs_map_free(&osdep->reg_handle); 758 if (osdep->ich_flash_handle != NULL) 759 ddi_regs_map_free(&osdep->ich_flash_handle); 760 return (DDI_FAILURE); 761 } 762 763 static int 764 e1000g_set_driver_params(struct e1000g *Adapter) 765 { 766 struct e1000_hw *hw; 767 768 hw = &Adapter->shared; 769 770 /* Set MAC type and initialize hardware functions */ 771 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 772 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 773 "Could not setup hardware functions"); 774 return (DDI_FAILURE); 775 } 776 777 /* Get bus information */ 778 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 779 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 780 "Could not get bus information"); 781 return (DDI_FAILURE); 782 } 783 784 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 785 786 hw->mac.autoneg_failed = B_TRUE; 787 788 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 789 hw->phy.autoneg_wait_to_complete = B_FALSE; 790 791 /* Adaptive IFS related changes */ 792 hw->mac.adaptive_ifs = B_TRUE; 793 794 /* Enable phy init script for IGP phy of 82541/82547 */ 795 if ((hw->mac.type == e1000_82547) || 796 (hw->mac.type == e1000_82541) || 797 (hw->mac.type == e1000_82547_rev_2) || 798 (hw->mac.type == e1000_82541_rev_2)) 799 e1000_init_script_state_82541(hw, B_TRUE); 800 801 /* Enable the TTL workaround for 82541/82547 */ 802 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 803 804 #ifdef __sparc 805 Adapter->strip_crc = B_TRUE; 806 #else 807 Adapter->strip_crc = B_FALSE; 808 #endif 809 810 /* setup the maximum MTU size of the chip */ 811 e1000g_setup_max_mtu(Adapter); 812 813 /* Get speed/duplex settings in conf file */ 814 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 815 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 816 e1000g_force_speed_duplex(Adapter); 817 818 /* Get Jumbo Frames settings in conf file */ 819 e1000g_get_max_frame_size(Adapter); 820 821 /* Get conf file properties */ 822 e1000g_get_conf(Adapter); 823 824 /* enforce PCH limits */ 825 e1000g_pch_limits(Adapter); 826 827 /* Set Rx/Tx buffer size */ 828 e1000g_set_bufsize(Adapter); 829 830 /* Master Latency Timer */ 831 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 832 833 /* copper options */ 834 if (hw->phy.media_type == e1000_media_type_copper) { 835 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 836 hw->phy.disable_polarity_correction = B_FALSE; 837 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 838 } 839 840 /* The initial link state should be "unknown" */ 841 Adapter->link_state = LINK_STATE_UNKNOWN; 842 843 /* Initialize rx parameters */ 844 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 845 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 846 847 /* Initialize tx parameters */ 848 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 849 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 850 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 851 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 852 853 /* Initialize rx parameters */ 854 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 855 856 return (DDI_SUCCESS); 857 } 858 859 static void 860 e1000g_setup_max_mtu(struct e1000g *Adapter) 861 { 862 struct e1000_mac_info *mac = &Adapter->shared.mac; 863 struct e1000_phy_info *phy = &Adapter->shared.phy; 864 865 switch (mac->type) { 866 /* types that do not support jumbo frames */ 867 case e1000_ich8lan: 868 case e1000_82573: 869 case e1000_82583: 870 Adapter->max_mtu = ETHERMTU; 871 break; 872 /* ich9 supports jumbo frames except on one phy type */ 873 case e1000_ich9lan: 874 if (phy->type == e1000_phy_ife) 875 Adapter->max_mtu = ETHERMTU; 876 else 877 Adapter->max_mtu = MAXIMUM_MTU_9K; 878 break; 879 /* pch can do jumbo frames up to 4K */ 880 case e1000_pchlan: 881 Adapter->max_mtu = MAXIMUM_MTU_4K; 882 break; 883 /* types with a special limit */ 884 case e1000_82571: 885 case e1000_82572: 886 case e1000_82574: 887 case e1000_80003es2lan: 888 case e1000_ich10lan: 889 Adapter->max_mtu = MAXIMUM_MTU_9K; 890 break; 891 /* default limit is 16K */ 892 default: 893 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 894 sizeof (struct ether_vlan_header) - ETHERFCSL - 895 E1000G_IPALIGNPRESERVEROOM; 896 break; 897 } 898 } 899 900 static void 901 e1000g_set_bufsize(struct e1000g *Adapter) 902 { 903 struct e1000_mac_info *mac = &Adapter->shared.mac; 904 uint64_t rx_size; 905 uint64_t tx_size; 906 907 dev_info_t *devinfo = Adapter->dip; 908 #ifdef __sparc 909 ulong_t iommu_pagesize; 910 #endif 911 /* Get the system page size */ 912 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 913 914 #ifdef __sparc 915 iommu_pagesize = dvma_pagesize(devinfo); 916 if (iommu_pagesize != 0) { 917 if (Adapter->sys_page_sz == iommu_pagesize) { 918 if (iommu_pagesize > 0x4000) 919 Adapter->sys_page_sz = 0x4000; 920 } else { 921 if (Adapter->sys_page_sz > iommu_pagesize) 922 Adapter->sys_page_sz = iommu_pagesize; 923 } 924 } 925 if (Adapter->lso_enable) { 926 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 927 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 928 } else { 929 Adapter->dvma_page_num = Adapter->max_frame_size / 930 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 931 } 932 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 933 #endif 934 935 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 936 937 if (Adapter->mem_workaround_82546 && 938 ((mac->type == e1000_82545) || 939 (mac->type == e1000_82546) || 940 (mac->type == e1000_82546_rev_3))) { 941 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K + 942 E1000G_IPALIGNROOM; 943 } else { 944 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 945 if ((rx_size > FRAME_SIZE_UPTO_2K) && 946 (rx_size <= FRAME_SIZE_UPTO_4K)) 947 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 948 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 949 (rx_size <= FRAME_SIZE_UPTO_8K)) 950 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 951 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 952 (rx_size <= FRAME_SIZE_UPTO_16K)) 953 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 954 else 955 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 956 } 957 958 tx_size = Adapter->max_frame_size; 959 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 960 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 961 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 962 (tx_size <= FRAME_SIZE_UPTO_8K)) 963 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 964 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 965 (tx_size <= FRAME_SIZE_UPTO_16K)) 966 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 967 else 968 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 969 970 /* 971 * For Wiseman adapters we have an requirement of having receive 972 * buffers aligned at 256 byte boundary. Since Livengood does not 973 * require this and forcing it for all hardwares will have 974 * performance implications, I am making it applicable only for 975 * Wiseman and for Jumbo frames enabled mode as rest of the time, 976 * it is okay to have normal frames...but it does involve a 977 * potential risk where we may loose data if buffer is not 978 * aligned...so all wiseman boards to have 256 byte aligned 979 * buffers 980 */ 981 if (mac->type < e1000_82543) 982 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 983 else 984 Adapter->rx_buf_align = 1; 985 } 986 987 /* 988 * e1000g_detach - driver detach 989 * 990 * The detach() function is the complement of the attach routine. 991 * If cmd is set to DDI_DETACH, detach() is used to remove the 992 * state associated with a given instance of a device node 993 * prior to the removal of that instance from the system. 994 * 995 * The detach() function will be called once for each instance 996 * of the device for which there has been a successful attach() 997 * once there are no longer any opens on the device. 998 * 999 * Interrupts routine are disabled, All memory allocated by this 1000 * driver are freed. 1001 */ 1002 static int 1003 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 1004 { 1005 struct e1000g *Adapter; 1006 boolean_t rx_drain; 1007 1008 switch (cmd) { 1009 default: 1010 return (DDI_FAILURE); 1011 1012 case DDI_SUSPEND: 1013 return (e1000g_suspend(devinfo)); 1014 1015 case DDI_DETACH: 1016 break; 1017 } 1018 1019 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1020 if (Adapter == NULL) 1021 return (DDI_FAILURE); 1022 1023 rx_drain = e1000g_rx_drain(Adapter); 1024 if (!rx_drain && !e1000g_force_detach) 1025 return (DDI_FAILURE); 1026 1027 if (mac_unregister(Adapter->mh) != 0) { 1028 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 1029 return (DDI_FAILURE); 1030 } 1031 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 1032 1033 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 1034 1035 if (!e1000g_force_detach && !rx_drain) 1036 return (DDI_FAILURE); 1037 1038 e1000g_unattach(devinfo, Adapter); 1039 1040 return (DDI_SUCCESS); 1041 } 1042 1043 /* 1044 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1045 */ 1046 void 1047 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1048 { 1049 ASSERT(e1000g_private_devi_list != NULL); 1050 ASSERT(devi_node != NULL); 1051 1052 if (devi_node->prev != NULL) 1053 devi_node->prev->next = devi_node->next; 1054 if (devi_node->next != NULL) 1055 devi_node->next->prev = devi_node->prev; 1056 if (devi_node == e1000g_private_devi_list) 1057 e1000g_private_devi_list = devi_node->next; 1058 1059 kmem_free(devi_node->priv_dip, 1060 sizeof (struct dev_info)); 1061 kmem_free(devi_node, 1062 sizeof (private_devi_list_t)); 1063 } 1064 1065 static void 1066 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1067 { 1068 private_devi_list_t *devi_node; 1069 int result; 1070 1071 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1072 (void) e1000g_disable_intrs(Adapter); 1073 } 1074 1075 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1076 (void) mac_unregister(Adapter->mh); 1077 } 1078 1079 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1080 (void) e1000g_rem_intrs(Adapter); 1081 } 1082 1083 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1084 (void) ddi_prop_remove_all(devinfo); 1085 } 1086 1087 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1088 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1089 } 1090 1091 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1092 stop_link_timer(Adapter); 1093 1094 mutex_enter(&e1000g_nvm_lock); 1095 result = e1000_reset_hw(&Adapter->shared); 1096 mutex_exit(&e1000g_nvm_lock); 1097 1098 if (result != E1000_SUCCESS) { 1099 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1100 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1101 } 1102 } 1103 1104 e1000g_release_multicast(Adapter); 1105 1106 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1107 if (Adapter->osdep.reg_handle != NULL) 1108 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1109 if (Adapter->osdep.ich_flash_handle != NULL) 1110 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1111 if (Adapter->osdep.io_reg_handle != NULL) 1112 ddi_regs_map_free(&Adapter->osdep.io_reg_handle); 1113 } 1114 1115 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1116 if (Adapter->osdep.cfg_handle != NULL) 1117 pci_config_teardown(&Adapter->osdep.cfg_handle); 1118 } 1119 1120 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1121 e1000g_destroy_locks(Adapter); 1122 } 1123 1124 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1125 e1000g_fm_fini(Adapter); 1126 } 1127 1128 mutex_enter(&e1000g_rx_detach_lock); 1129 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1130 devi_node = Adapter->priv_devi_node; 1131 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1132 1133 if (devi_node->pending_rx_count == 0) { 1134 e1000g_free_priv_devi_node(devi_node); 1135 } 1136 } 1137 mutex_exit(&e1000g_rx_detach_lock); 1138 1139 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1140 1141 /* 1142 * Another hotplug spec requirement, 1143 * run ddi_set_driver_private(devinfo, null); 1144 */ 1145 ddi_set_driver_private(devinfo, NULL); 1146 } 1147 1148 /* 1149 * Get the BAR type and rnumber for a given PCI BAR offset 1150 */ 1151 static int 1152 e1000g_get_bar_info(dev_info_t *dip, int bar_offset, bar_info_t *bar_info) 1153 { 1154 pci_regspec_t *regs; 1155 uint_t regs_length; 1156 int type, rnumber, rcount; 1157 1158 ASSERT((bar_offset >= PCI_CONF_BASE0) && 1159 (bar_offset <= PCI_CONF_BASE5)); 1160 1161 /* 1162 * Get the DDI "reg" property 1163 */ 1164 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 1165 DDI_PROP_DONTPASS, "reg", (int **)®s, 1166 ®s_length) != DDI_PROP_SUCCESS) { 1167 return (DDI_FAILURE); 1168 } 1169 1170 rcount = regs_length * sizeof (int) / sizeof (pci_regspec_t); 1171 /* 1172 * Check the BAR offset 1173 */ 1174 for (rnumber = 0; rnumber < rcount; ++rnumber) { 1175 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) { 1176 type = regs[rnumber].pci_phys_hi & PCI_ADDR_MASK; 1177 break; 1178 } 1179 } 1180 1181 ddi_prop_free(regs); 1182 1183 if (rnumber >= rcount) 1184 return (DDI_FAILURE); 1185 1186 switch (type) { 1187 case PCI_ADDR_CONFIG: 1188 bar_info->type = E1000G_BAR_CONFIG; 1189 break; 1190 case PCI_ADDR_IO: 1191 bar_info->type = E1000G_BAR_IO; 1192 break; 1193 case PCI_ADDR_MEM32: 1194 bar_info->type = E1000G_BAR_MEM32; 1195 break; 1196 case PCI_ADDR_MEM64: 1197 bar_info->type = E1000G_BAR_MEM64; 1198 break; 1199 default: 1200 return (DDI_FAILURE); 1201 } 1202 bar_info->rnumber = rnumber; 1203 return (DDI_SUCCESS); 1204 } 1205 1206 static void 1207 e1000g_init_locks(struct e1000g *Adapter) 1208 { 1209 e1000g_tx_ring_t *tx_ring; 1210 e1000g_rx_ring_t *rx_ring; 1211 1212 rw_init(&Adapter->chip_lock, NULL, 1213 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1214 mutex_init(&Adapter->link_lock, NULL, 1215 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1216 mutex_init(&Adapter->watchdog_lock, NULL, 1217 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1218 1219 tx_ring = Adapter->tx_ring; 1220 1221 mutex_init(&tx_ring->tx_lock, NULL, 1222 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1223 mutex_init(&tx_ring->usedlist_lock, NULL, 1224 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1225 mutex_init(&tx_ring->freelist_lock, NULL, 1226 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1227 1228 rx_ring = Adapter->rx_ring; 1229 1230 mutex_init(&rx_ring->rx_lock, NULL, 1231 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1232 } 1233 1234 static void 1235 e1000g_destroy_locks(struct e1000g *Adapter) 1236 { 1237 e1000g_tx_ring_t *tx_ring; 1238 e1000g_rx_ring_t *rx_ring; 1239 1240 tx_ring = Adapter->tx_ring; 1241 mutex_destroy(&tx_ring->tx_lock); 1242 mutex_destroy(&tx_ring->usedlist_lock); 1243 mutex_destroy(&tx_ring->freelist_lock); 1244 1245 rx_ring = Adapter->rx_ring; 1246 mutex_destroy(&rx_ring->rx_lock); 1247 1248 mutex_destroy(&Adapter->link_lock); 1249 mutex_destroy(&Adapter->watchdog_lock); 1250 rw_destroy(&Adapter->chip_lock); 1251 1252 /* destory mutex initialized in shared code */ 1253 e1000_destroy_hw_mutex(&Adapter->shared); 1254 } 1255 1256 static int 1257 e1000g_resume(dev_info_t *devinfo) 1258 { 1259 struct e1000g *Adapter; 1260 1261 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1262 if (Adapter == NULL) 1263 e1000g_log(Adapter, CE_PANIC, 1264 "Instance pointer is null\n"); 1265 1266 if (Adapter->dip != devinfo) 1267 e1000g_log(Adapter, CE_PANIC, 1268 "Devinfo is not the same as saved devinfo\n"); 1269 1270 rw_enter(&Adapter->chip_lock, RW_WRITER); 1271 1272 if (Adapter->e1000g_state & E1000G_STARTED) { 1273 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1274 rw_exit(&Adapter->chip_lock); 1275 /* 1276 * We note the failure, but return success, as the 1277 * system is still usable without this controller. 1278 */ 1279 e1000g_log(Adapter, CE_WARN, 1280 "e1000g_resume: failed to restart controller\n"); 1281 return (DDI_SUCCESS); 1282 } 1283 /* Enable and start the watchdog timer */ 1284 enable_watchdog_timer(Adapter); 1285 } 1286 1287 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1288 1289 rw_exit(&Adapter->chip_lock); 1290 1291 return (DDI_SUCCESS); 1292 } 1293 1294 static int 1295 e1000g_suspend(dev_info_t *devinfo) 1296 { 1297 struct e1000g *Adapter; 1298 1299 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1300 if (Adapter == NULL) 1301 return (DDI_FAILURE); 1302 1303 rw_enter(&Adapter->chip_lock, RW_WRITER); 1304 1305 Adapter->e1000g_state |= E1000G_SUSPENDED; 1306 1307 /* if the port isn't plumbed, we can simply return */ 1308 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1309 rw_exit(&Adapter->chip_lock); 1310 return (DDI_SUCCESS); 1311 } 1312 1313 e1000g_stop(Adapter, B_FALSE); 1314 1315 rw_exit(&Adapter->chip_lock); 1316 1317 /* Disable and stop all the timers */ 1318 disable_watchdog_timer(Adapter); 1319 stop_link_timer(Adapter); 1320 stop_82547_timer(Adapter->tx_ring); 1321 1322 return (DDI_SUCCESS); 1323 } 1324 1325 static int 1326 e1000g_init(struct e1000g *Adapter) 1327 { 1328 uint32_t pba; 1329 uint32_t high_water; 1330 struct e1000_hw *hw; 1331 clock_t link_timeout; 1332 int result; 1333 1334 hw = &Adapter->shared; 1335 1336 /* 1337 * reset to put the hardware in a known state 1338 * before we try to do anything with the eeprom 1339 */ 1340 mutex_enter(&e1000g_nvm_lock); 1341 result = e1000_reset_hw(hw); 1342 mutex_exit(&e1000g_nvm_lock); 1343 1344 if (result != E1000_SUCCESS) { 1345 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1346 goto init_fail; 1347 } 1348 1349 mutex_enter(&e1000g_nvm_lock); 1350 result = e1000_validate_nvm_checksum(hw); 1351 if (result < E1000_SUCCESS) { 1352 /* 1353 * Some PCI-E parts fail the first check due to 1354 * the link being in sleep state. Call it again, 1355 * if it fails a second time its a real issue. 1356 */ 1357 result = e1000_validate_nvm_checksum(hw); 1358 } 1359 mutex_exit(&e1000g_nvm_lock); 1360 1361 if (result < E1000_SUCCESS) { 1362 e1000g_log(Adapter, CE_WARN, 1363 "Invalid NVM checksum. Please contact " 1364 "the vendor to update the NVM."); 1365 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1366 goto init_fail; 1367 } 1368 1369 result = 0; 1370 #ifdef __sparc 1371 /* 1372 * First, we try to get the local ethernet address from OBP. If 1373 * failed, then we get it from the EEPROM of NIC card. 1374 */ 1375 result = e1000g_find_mac_address(Adapter); 1376 #endif 1377 /* Get the local ethernet address. */ 1378 if (!result) { 1379 mutex_enter(&e1000g_nvm_lock); 1380 result = e1000_read_mac_addr(hw); 1381 mutex_exit(&e1000g_nvm_lock); 1382 } 1383 1384 if (result < E1000_SUCCESS) { 1385 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1386 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1387 goto init_fail; 1388 } 1389 1390 /* check for valid mac address */ 1391 if (!is_valid_mac_addr(hw->mac.addr)) { 1392 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1393 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1394 goto init_fail; 1395 } 1396 1397 /* Set LAA state for 82571 chipset */ 1398 e1000_set_laa_state_82571(hw, B_TRUE); 1399 1400 /* Master Latency Timer implementation */ 1401 if (Adapter->master_latency_timer) { 1402 pci_config_put8(Adapter->osdep.cfg_handle, 1403 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1404 } 1405 1406 if (hw->mac.type < e1000_82547) { 1407 /* 1408 * Total FIFO is 64K 1409 */ 1410 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1411 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1412 else 1413 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1414 } else if ((hw->mac.type == e1000_82571) || 1415 (hw->mac.type == e1000_82572) || 1416 (hw->mac.type == e1000_80003es2lan)) { 1417 /* 1418 * Total FIFO is 48K 1419 */ 1420 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1421 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1422 else 1423 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1424 } else if (hw->mac.type == e1000_82573) { 1425 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1426 } else if (hw->mac.type == e1000_82574) { 1427 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1428 pba = E1000_READ_REG(hw, E1000_PBA); 1429 } else if (hw->mac.type == e1000_ich8lan) { 1430 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1431 } else if (hw->mac.type == e1000_ich9lan) { 1432 pba = E1000_PBA_10K; 1433 } else if (hw->mac.type == e1000_ich10lan) { 1434 pba = E1000_PBA_10K; 1435 } else if (hw->mac.type == e1000_pchlan) { 1436 pba = E1000_PBA_26K; 1437 } else { 1438 /* 1439 * Total FIFO is 40K 1440 */ 1441 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1442 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1443 else 1444 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1445 } 1446 E1000_WRITE_REG(hw, E1000_PBA, pba); 1447 1448 /* 1449 * These parameters set thresholds for the adapter's generation(Tx) 1450 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1451 * settings. Flow control is enabled or disabled in the configuration 1452 * file. 1453 * High-water mark is set down from the top of the rx fifo (not 1454 * sensitive to max_frame_size) and low-water is set just below 1455 * high-water mark. 1456 * The high water mark must be low enough to fit one full frame above 1457 * it in the rx FIFO. Should be the lower of: 1458 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1459 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1460 * Rx FIFO size minus one full frame. 1461 */ 1462 high_water = min(((pba << 10) * 9 / 10), 1463 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1464 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1465 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1466 ((pba << 10) - Adapter->max_frame_size))); 1467 1468 hw->fc.high_water = high_water & 0xFFF8; 1469 hw->fc.low_water = hw->fc.high_water - 8; 1470 1471 if (hw->mac.type == e1000_80003es2lan) 1472 hw->fc.pause_time = 0xFFFF; 1473 else 1474 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1475 hw->fc.send_xon = B_TRUE; 1476 1477 /* 1478 * Reset the adapter hardware the second time. 1479 */ 1480 mutex_enter(&e1000g_nvm_lock); 1481 result = e1000_reset_hw(hw); 1482 mutex_exit(&e1000g_nvm_lock); 1483 1484 if (result != E1000_SUCCESS) { 1485 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1486 goto init_fail; 1487 } 1488 1489 /* disable wakeup control by default */ 1490 if (hw->mac.type >= e1000_82544) 1491 E1000_WRITE_REG(hw, E1000_WUC, 0); 1492 1493 /* 1494 * MWI should be disabled on 82546. 1495 */ 1496 if (hw->mac.type == e1000_82546) 1497 e1000_pci_clear_mwi(hw); 1498 else 1499 e1000_pci_set_mwi(hw); 1500 1501 /* 1502 * Configure/Initialize hardware 1503 */ 1504 mutex_enter(&e1000g_nvm_lock); 1505 result = e1000_init_hw(hw); 1506 mutex_exit(&e1000g_nvm_lock); 1507 1508 if (result < E1000_SUCCESS) { 1509 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1510 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1511 goto init_fail; 1512 } 1513 1514 /* 1515 * Restore LED settings to the default from EEPROM 1516 * to meet the standard for Sun platforms. 1517 */ 1518 (void) e1000_cleanup_led(hw); 1519 1520 /* Disable Smart Power Down */ 1521 phy_spd_state(hw, B_FALSE); 1522 1523 /* Make sure driver has control */ 1524 e1000g_get_driver_control(hw); 1525 1526 /* 1527 * Initialize unicast addresses. 1528 */ 1529 e1000g_init_unicst(Adapter); 1530 1531 /* 1532 * Setup and initialize the mctable structures. After this routine 1533 * completes Multicast table will be set 1534 */ 1535 e1000_update_mc_addr_list(hw, 1536 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1537 msec_delay(5); 1538 1539 /* 1540 * Implement Adaptive IFS 1541 */ 1542 e1000_reset_adaptive(hw); 1543 1544 /* Setup Interrupt Throttling Register */ 1545 if (hw->mac.type >= e1000_82540) { 1546 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1547 } else 1548 Adapter->intr_adaptive = B_FALSE; 1549 1550 /* Start the timer for link setup */ 1551 if (hw->mac.autoneg) 1552 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1553 else 1554 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1555 1556 mutex_enter(&Adapter->link_lock); 1557 if (hw->phy.autoneg_wait_to_complete) { 1558 Adapter->link_complete = B_TRUE; 1559 } else { 1560 Adapter->link_complete = B_FALSE; 1561 Adapter->link_tid = timeout(e1000g_link_timer, 1562 (void *)Adapter, link_timeout); 1563 } 1564 mutex_exit(&Adapter->link_lock); 1565 1566 /* Save the state of the phy */ 1567 e1000g_get_phy_state(Adapter); 1568 1569 e1000g_param_sync(Adapter); 1570 1571 Adapter->init_count++; 1572 1573 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1574 goto init_fail; 1575 } 1576 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1577 goto init_fail; 1578 } 1579 1580 Adapter->poll_mode = e1000g_poll_mode; 1581 1582 return (DDI_SUCCESS); 1583 1584 init_fail: 1585 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1586 return (DDI_FAILURE); 1587 } 1588 1589 static int 1590 e1000g_alloc_rx_data(struct e1000g *Adapter) 1591 { 1592 e1000g_rx_ring_t *rx_ring; 1593 e1000g_rx_data_t *rx_data; 1594 1595 rx_ring = Adapter->rx_ring; 1596 1597 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1598 1599 if (rx_data == NULL) 1600 return (DDI_FAILURE); 1601 1602 rx_data->priv_devi_node = Adapter->priv_devi_node; 1603 rx_data->rx_ring = rx_ring; 1604 1605 mutex_init(&rx_data->freelist_lock, NULL, 1606 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1607 mutex_init(&rx_data->recycle_lock, NULL, 1608 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1609 1610 rx_ring->rx_data = rx_data; 1611 1612 return (DDI_SUCCESS); 1613 } 1614 1615 void 1616 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1617 { 1618 rx_sw_packet_t *packet, *next_packet; 1619 1620 if (rx_data == NULL) 1621 return; 1622 1623 packet = rx_data->packet_area; 1624 while (packet != NULL) { 1625 next_packet = packet->next; 1626 e1000g_free_rx_sw_packet(packet, B_TRUE); 1627 packet = next_packet; 1628 } 1629 rx_data->packet_area = NULL; 1630 } 1631 1632 void 1633 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1634 { 1635 if (rx_data == NULL) 1636 return; 1637 1638 mutex_destroy(&rx_data->freelist_lock); 1639 mutex_destroy(&rx_data->recycle_lock); 1640 1641 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1642 } 1643 1644 /* 1645 * Check if the link is up 1646 */ 1647 static boolean_t 1648 e1000g_link_up(struct e1000g *Adapter) 1649 { 1650 struct e1000_hw *hw = &Adapter->shared; 1651 boolean_t link_up = B_FALSE; 1652 1653 /* 1654 * get_link_status is set in the interrupt handler on link-status-change 1655 * or rx sequence error interrupt. get_link_status will stay 1656 * false until the e1000_check_for_link establishes link only 1657 * for copper adapters. 1658 */ 1659 switch (hw->phy.media_type) { 1660 case e1000_media_type_copper: 1661 if (hw->mac.get_link_status) { 1662 (void) e1000_check_for_link(hw); 1663 link_up = !hw->mac.get_link_status; 1664 } else { 1665 link_up = B_TRUE; 1666 } 1667 break; 1668 case e1000_media_type_fiber: 1669 (void) e1000_check_for_link(hw); 1670 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1671 E1000_STATUS_LU); 1672 break; 1673 case e1000_media_type_internal_serdes: 1674 (void) e1000_check_for_link(hw); 1675 link_up = hw->mac.serdes_has_link; 1676 break; 1677 } 1678 1679 return (link_up); 1680 } 1681 1682 static void 1683 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1684 { 1685 struct iocblk *iocp; 1686 struct e1000g *e1000gp; 1687 enum ioc_reply status; 1688 1689 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1690 iocp->ioc_error = 0; 1691 e1000gp = (struct e1000g *)arg; 1692 1693 ASSERT(e1000gp); 1694 if (e1000gp == NULL) { 1695 miocnak(q, mp, 0, EINVAL); 1696 return; 1697 } 1698 1699 rw_enter(&e1000gp->chip_lock, RW_READER); 1700 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1701 rw_exit(&e1000gp->chip_lock); 1702 miocnak(q, mp, 0, EINVAL); 1703 return; 1704 } 1705 rw_exit(&e1000gp->chip_lock); 1706 1707 switch (iocp->ioc_cmd) { 1708 1709 case LB_GET_INFO_SIZE: 1710 case LB_GET_INFO: 1711 case LB_GET_MODE: 1712 case LB_SET_MODE: 1713 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1714 break; 1715 1716 1717 #ifdef E1000G_DEBUG 1718 case E1000G_IOC_REG_PEEK: 1719 case E1000G_IOC_REG_POKE: 1720 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1721 break; 1722 case E1000G_IOC_CHIP_RESET: 1723 e1000gp->reset_count++; 1724 if (e1000g_reset_adapter(e1000gp)) 1725 status = IOC_ACK; 1726 else 1727 status = IOC_INVAL; 1728 break; 1729 #endif 1730 default: 1731 status = IOC_INVAL; 1732 break; 1733 } 1734 1735 /* 1736 * Decide how to reply 1737 */ 1738 switch (status) { 1739 default: 1740 case IOC_INVAL: 1741 /* 1742 * Error, reply with a NAK and EINVAL or the specified error 1743 */ 1744 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1745 EINVAL : iocp->ioc_error); 1746 break; 1747 1748 case IOC_DONE: 1749 /* 1750 * OK, reply already sent 1751 */ 1752 break; 1753 1754 case IOC_ACK: 1755 /* 1756 * OK, reply with an ACK 1757 */ 1758 miocack(q, mp, 0, 0); 1759 break; 1760 1761 case IOC_REPLY: 1762 /* 1763 * OK, send prepared reply as ACK or NAK 1764 */ 1765 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1766 M_IOCACK : M_IOCNAK; 1767 qreply(q, mp); 1768 break; 1769 } 1770 } 1771 1772 /* 1773 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1774 * capable of supporting only one interrupt and we shouldn't disable 1775 * the physical interrupt. In this case we let the interrupt come and 1776 * we queue the packets in the rx ring itself in case we are in polling 1777 * mode (better latency but slightly lower performance and a very 1778 * high intrrupt count in mpstat which is harmless). 1779 * 1780 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1781 * which can be disabled in poll mode. This gives better overall 1782 * throughput (compared to the mode above), shows very low interrupt 1783 * count but has slightly higher latency since we pick the packets when 1784 * the poll thread does polling. 1785 * 1786 * Currently, this flag should be enabled only while doing performance 1787 * measurement or when it can be guaranteed that entire NIC going 1788 * in poll mode will not harm any traffic like cluster heartbeat etc. 1789 */ 1790 int e1000g_poll_mode = 0; 1791 1792 /* 1793 * Called from the upper layers when driver is in polling mode to 1794 * pick up any queued packets. Care should be taken to not block 1795 * this thread. 1796 */ 1797 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1798 { 1799 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1800 mblk_t *mp = NULL; 1801 mblk_t *tail; 1802 struct e1000g *adapter; 1803 1804 adapter = rx_ring->adapter; 1805 1806 rw_enter(&adapter->chip_lock, RW_READER); 1807 1808 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1809 rw_exit(&adapter->chip_lock); 1810 return (NULL); 1811 } 1812 1813 mutex_enter(&rx_ring->rx_lock); 1814 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1815 mutex_exit(&rx_ring->rx_lock); 1816 rw_exit(&adapter->chip_lock); 1817 return (mp); 1818 } 1819 1820 static int 1821 e1000g_m_start(void *arg) 1822 { 1823 struct e1000g *Adapter = (struct e1000g *)arg; 1824 1825 rw_enter(&Adapter->chip_lock, RW_WRITER); 1826 1827 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1828 rw_exit(&Adapter->chip_lock); 1829 return (ECANCELED); 1830 } 1831 1832 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1833 rw_exit(&Adapter->chip_lock); 1834 return (ENOTACTIVE); 1835 } 1836 1837 Adapter->e1000g_state |= E1000G_STARTED; 1838 1839 rw_exit(&Adapter->chip_lock); 1840 1841 /* Enable and start the watchdog timer */ 1842 enable_watchdog_timer(Adapter); 1843 1844 return (0); 1845 } 1846 1847 static int 1848 e1000g_start(struct e1000g *Adapter, boolean_t global) 1849 { 1850 e1000g_rx_data_t *rx_data; 1851 1852 if (global) { 1853 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1854 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1855 goto start_fail; 1856 } 1857 1858 /* Allocate dma resources for descriptors and buffers */ 1859 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1860 e1000g_log(Adapter, CE_WARN, 1861 "Alloc DMA resources failed"); 1862 goto start_fail; 1863 } 1864 Adapter->rx_buffer_setup = B_FALSE; 1865 } 1866 1867 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1868 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1869 e1000g_log(Adapter, CE_WARN, 1870 "Adapter initialization failed"); 1871 goto start_fail; 1872 } 1873 } 1874 1875 /* Setup and initialize the transmit structures */ 1876 e1000g_tx_setup(Adapter); 1877 msec_delay(5); 1878 1879 /* Setup and initialize the receive structures */ 1880 e1000g_rx_setup(Adapter); 1881 msec_delay(5); 1882 1883 /* Restore the e1000g promiscuous mode */ 1884 e1000g_restore_promisc(Adapter); 1885 1886 e1000g_mask_interrupt(Adapter); 1887 1888 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1889 1890 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1891 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1892 goto start_fail; 1893 } 1894 1895 return (DDI_SUCCESS); 1896 1897 start_fail: 1898 rx_data = Adapter->rx_ring->rx_data; 1899 1900 if (global) { 1901 e1000g_release_dma_resources(Adapter); 1902 e1000g_free_rx_pending_buffers(rx_data); 1903 e1000g_free_rx_data(rx_data); 1904 } 1905 1906 mutex_enter(&e1000g_nvm_lock); 1907 (void) e1000_reset_hw(&Adapter->shared); 1908 mutex_exit(&e1000g_nvm_lock); 1909 1910 return (DDI_FAILURE); 1911 } 1912 1913 static void 1914 e1000g_m_stop(void *arg) 1915 { 1916 struct e1000g *Adapter = (struct e1000g *)arg; 1917 1918 /* Drain tx sessions */ 1919 (void) e1000g_tx_drain(Adapter); 1920 1921 rw_enter(&Adapter->chip_lock, RW_WRITER); 1922 1923 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1924 rw_exit(&Adapter->chip_lock); 1925 return; 1926 } 1927 Adapter->e1000g_state &= ~E1000G_STARTED; 1928 e1000g_stop(Adapter, B_TRUE); 1929 1930 rw_exit(&Adapter->chip_lock); 1931 1932 /* Disable and stop all the timers */ 1933 disable_watchdog_timer(Adapter); 1934 stop_link_timer(Adapter); 1935 stop_82547_timer(Adapter->tx_ring); 1936 } 1937 1938 static void 1939 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1940 { 1941 private_devi_list_t *devi_node; 1942 e1000g_rx_data_t *rx_data; 1943 int result; 1944 1945 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1946 1947 /* Stop the chip and release pending resources */ 1948 1949 /* Tell firmware driver is no longer in control */ 1950 e1000g_release_driver_control(&Adapter->shared); 1951 1952 e1000g_clear_all_interrupts(Adapter); 1953 1954 mutex_enter(&e1000g_nvm_lock); 1955 result = e1000_reset_hw(&Adapter->shared); 1956 mutex_exit(&e1000g_nvm_lock); 1957 1958 if (result != E1000_SUCCESS) { 1959 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1960 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1961 } 1962 1963 mutex_enter(&Adapter->link_lock); 1964 Adapter->link_complete = B_FALSE; 1965 mutex_exit(&Adapter->link_lock); 1966 1967 /* Release resources still held by the TX descriptors */ 1968 e1000g_tx_clean(Adapter); 1969 1970 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1971 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1972 1973 /* Clean the pending rx jumbo packet fragment */ 1974 e1000g_rx_clean(Adapter); 1975 1976 if (global) { 1977 e1000g_release_dma_resources(Adapter); 1978 1979 mutex_enter(&e1000g_rx_detach_lock); 1980 rx_data = Adapter->rx_ring->rx_data; 1981 rx_data->flag |= E1000G_RX_STOPPED; 1982 1983 if (rx_data->pending_count == 0) { 1984 e1000g_free_rx_pending_buffers(rx_data); 1985 e1000g_free_rx_data(rx_data); 1986 } else { 1987 devi_node = rx_data->priv_devi_node; 1988 if (devi_node != NULL) 1989 atomic_inc_32(&devi_node->pending_rx_count); 1990 else 1991 atomic_inc_32(&Adapter->pending_rx_count); 1992 } 1993 mutex_exit(&e1000g_rx_detach_lock); 1994 } 1995 1996 if (Adapter->link_state == LINK_STATE_UP) { 1997 Adapter->link_state = LINK_STATE_UNKNOWN; 1998 if (!Adapter->reset_flag) 1999 mac_link_update(Adapter->mh, Adapter->link_state); 2000 } 2001 } 2002 2003 static void 2004 e1000g_rx_clean(struct e1000g *Adapter) 2005 { 2006 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 2007 2008 if (rx_data == NULL) 2009 return; 2010 2011 if (rx_data->rx_mblk != NULL) { 2012 freemsg(rx_data->rx_mblk); 2013 rx_data->rx_mblk = NULL; 2014 rx_data->rx_mblk_tail = NULL; 2015 rx_data->rx_mblk_len = 0; 2016 } 2017 } 2018 2019 static void 2020 e1000g_tx_clean(struct e1000g *Adapter) 2021 { 2022 e1000g_tx_ring_t *tx_ring; 2023 p_tx_sw_packet_t packet; 2024 mblk_t *mp; 2025 mblk_t *nmp; 2026 uint32_t packet_count; 2027 2028 tx_ring = Adapter->tx_ring; 2029 2030 /* 2031 * Here we don't need to protect the lists using 2032 * the usedlist_lock and freelist_lock, for they 2033 * have been protected by the chip_lock. 2034 */ 2035 mp = NULL; 2036 nmp = NULL; 2037 packet_count = 0; 2038 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 2039 while (packet != NULL) { 2040 if (packet->mp != NULL) { 2041 /* Assemble the message chain */ 2042 if (mp == NULL) { 2043 mp = packet->mp; 2044 nmp = packet->mp; 2045 } else { 2046 nmp->b_next = packet->mp; 2047 nmp = packet->mp; 2048 } 2049 /* Disconnect the message from the sw packet */ 2050 packet->mp = NULL; 2051 } 2052 2053 e1000g_free_tx_swpkt(packet); 2054 packet_count++; 2055 2056 packet = (p_tx_sw_packet_t) 2057 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 2058 } 2059 2060 if (mp != NULL) 2061 freemsgchain(mp); 2062 2063 if (packet_count > 0) { 2064 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 2065 QUEUE_INIT_LIST(&tx_ring->used_list); 2066 2067 /* Setup TX descriptor pointers */ 2068 tx_ring->tbd_next = tx_ring->tbd_first; 2069 tx_ring->tbd_oldest = tx_ring->tbd_first; 2070 2071 /* Setup our HW Tx Head & Tail descriptor pointers */ 2072 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 2073 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 2074 } 2075 } 2076 2077 static boolean_t 2078 e1000g_tx_drain(struct e1000g *Adapter) 2079 { 2080 int i; 2081 boolean_t done; 2082 e1000g_tx_ring_t *tx_ring; 2083 2084 tx_ring = Adapter->tx_ring; 2085 2086 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 2087 for (i = 0; i < TX_DRAIN_TIME; i++) { 2088 mutex_enter(&tx_ring->usedlist_lock); 2089 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 2090 mutex_exit(&tx_ring->usedlist_lock); 2091 2092 if (done) 2093 break; 2094 2095 msec_delay(1); 2096 } 2097 2098 return (done); 2099 } 2100 2101 static boolean_t 2102 e1000g_rx_drain(struct e1000g *Adapter) 2103 { 2104 int i; 2105 boolean_t done; 2106 2107 /* 2108 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2109 */ 2110 for (i = 0; i < RX_DRAIN_TIME; i++) { 2111 done = (Adapter->pending_rx_count == 0); 2112 2113 if (done) 2114 break; 2115 2116 msec_delay(1); 2117 } 2118 2119 return (done); 2120 } 2121 2122 static boolean_t 2123 e1000g_reset_adapter(struct e1000g *Adapter) 2124 { 2125 /* Disable and stop all the timers */ 2126 disable_watchdog_timer(Adapter); 2127 stop_link_timer(Adapter); 2128 stop_82547_timer(Adapter->tx_ring); 2129 2130 rw_enter(&Adapter->chip_lock, RW_WRITER); 2131 2132 if (Adapter->stall_flag) { 2133 Adapter->stall_flag = B_FALSE; 2134 Adapter->reset_flag = B_TRUE; 2135 } 2136 2137 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2138 rw_exit(&Adapter->chip_lock); 2139 return (B_TRUE); 2140 } 2141 2142 e1000g_stop(Adapter, B_FALSE); 2143 2144 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2145 rw_exit(&Adapter->chip_lock); 2146 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2147 return (B_FALSE); 2148 } 2149 2150 rw_exit(&Adapter->chip_lock); 2151 2152 /* Enable and start the watchdog timer */ 2153 enable_watchdog_timer(Adapter); 2154 2155 return (B_TRUE); 2156 } 2157 2158 boolean_t 2159 e1000g_global_reset(struct e1000g *Adapter) 2160 { 2161 /* Disable and stop all the timers */ 2162 disable_watchdog_timer(Adapter); 2163 stop_link_timer(Adapter); 2164 stop_82547_timer(Adapter->tx_ring); 2165 2166 rw_enter(&Adapter->chip_lock, RW_WRITER); 2167 2168 e1000g_stop(Adapter, B_TRUE); 2169 2170 Adapter->init_count = 0; 2171 2172 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2173 rw_exit(&Adapter->chip_lock); 2174 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2175 return (B_FALSE); 2176 } 2177 2178 rw_exit(&Adapter->chip_lock); 2179 2180 /* Enable and start the watchdog timer */ 2181 enable_watchdog_timer(Adapter); 2182 2183 return (B_TRUE); 2184 } 2185 2186 /* 2187 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2188 * 2189 * This interrupt service routine is for PCI-Express adapters. 2190 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2191 * bit is set. 2192 */ 2193 static uint_t 2194 e1000g_intr_pciexpress(caddr_t arg) 2195 { 2196 struct e1000g *Adapter; 2197 uint32_t icr; 2198 2199 Adapter = (struct e1000g *)(uintptr_t)arg; 2200 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2201 2202 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2203 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2204 return (DDI_INTR_CLAIMED); 2205 } 2206 2207 if (icr & E1000_ICR_INT_ASSERTED) { 2208 /* 2209 * E1000_ICR_INT_ASSERTED bit was set: 2210 * Read(Clear) the ICR, claim this interrupt, 2211 * look for work to do. 2212 */ 2213 e1000g_intr_work(Adapter, icr); 2214 return (DDI_INTR_CLAIMED); 2215 } else { 2216 /* 2217 * E1000_ICR_INT_ASSERTED bit was not set: 2218 * Don't claim this interrupt, return immediately. 2219 */ 2220 return (DDI_INTR_UNCLAIMED); 2221 } 2222 } 2223 2224 /* 2225 * e1000g_intr - ISR for PCI/PCI-X chipsets 2226 * 2227 * This interrupt service routine is for PCI/PCI-X adapters. 2228 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2229 * bit is set or not. 2230 */ 2231 static uint_t 2232 e1000g_intr(caddr_t arg) 2233 { 2234 struct e1000g *Adapter; 2235 uint32_t icr; 2236 2237 Adapter = (struct e1000g *)(uintptr_t)arg; 2238 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2239 2240 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2241 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2242 return (DDI_INTR_CLAIMED); 2243 } 2244 2245 if (icr) { 2246 /* 2247 * Any bit was set in ICR: 2248 * Read(Clear) the ICR, claim this interrupt, 2249 * look for work to do. 2250 */ 2251 e1000g_intr_work(Adapter, icr); 2252 return (DDI_INTR_CLAIMED); 2253 } else { 2254 /* 2255 * No bit was set in ICR: 2256 * Don't claim this interrupt, return immediately. 2257 */ 2258 return (DDI_INTR_UNCLAIMED); 2259 } 2260 } 2261 2262 /* 2263 * e1000g_intr_work - actual processing of ISR 2264 * 2265 * Read(clear) the ICR contents and call appropriate interrupt 2266 * processing routines. 2267 */ 2268 static void 2269 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2270 { 2271 struct e1000_hw *hw; 2272 hw = &Adapter->shared; 2273 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2274 2275 Adapter->rx_pkt_cnt = 0; 2276 Adapter->tx_pkt_cnt = 0; 2277 2278 rw_enter(&Adapter->chip_lock, RW_READER); 2279 2280 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2281 rw_exit(&Adapter->chip_lock); 2282 return; 2283 } 2284 /* 2285 * Here we need to check the "e1000g_state" flag within the chip_lock to 2286 * ensure the receive routine will not execute when the adapter is 2287 * being reset. 2288 */ 2289 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2290 rw_exit(&Adapter->chip_lock); 2291 return; 2292 } 2293 2294 if (icr & E1000_ICR_RXT0) { 2295 mblk_t *mp = NULL; 2296 mblk_t *tail = NULL; 2297 e1000g_rx_ring_t *rx_ring; 2298 2299 rx_ring = Adapter->rx_ring; 2300 mutex_enter(&rx_ring->rx_lock); 2301 /* 2302 * Sometimes with legacy interrupts, it possible that 2303 * there is a single interrupt for Rx/Tx. In which 2304 * case, if poll flag is set, we shouldn't really 2305 * be doing Rx processing. 2306 */ 2307 if (!rx_ring->poll_flag) 2308 mp = e1000g_receive(rx_ring, &tail, 2309 E1000G_CHAIN_NO_LIMIT); 2310 mutex_exit(&rx_ring->rx_lock); 2311 rw_exit(&Adapter->chip_lock); 2312 if (mp != NULL) 2313 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2314 mp, rx_ring->ring_gen_num); 2315 } else 2316 rw_exit(&Adapter->chip_lock); 2317 2318 if (icr & E1000_ICR_TXDW) { 2319 if (!Adapter->tx_intr_enable) 2320 e1000g_clear_tx_interrupt(Adapter); 2321 2322 /* Recycle the tx descriptors */ 2323 rw_enter(&Adapter->chip_lock, RW_READER); 2324 (void) e1000g_recycle(tx_ring); 2325 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2326 rw_exit(&Adapter->chip_lock); 2327 2328 if (tx_ring->resched_needed && 2329 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2330 tx_ring->resched_needed = B_FALSE; 2331 mac_tx_update(Adapter->mh); 2332 E1000G_STAT(tx_ring->stat_reschedule); 2333 } 2334 } 2335 2336 /* 2337 * The Receive Sequence errors RXSEQ and the link status change LSC 2338 * are checked to detect that the cable has been pulled out. For 2339 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2340 * are an indication that cable is not connected. 2341 */ 2342 if ((icr & E1000_ICR_RXSEQ) || 2343 (icr & E1000_ICR_LSC) || 2344 (icr & E1000_ICR_GPI_EN1)) { 2345 boolean_t link_changed; 2346 timeout_id_t tid = 0; 2347 2348 stop_watchdog_timer(Adapter); 2349 2350 rw_enter(&Adapter->chip_lock, RW_WRITER); 2351 2352 /* 2353 * Because we got a link-status-change interrupt, force 2354 * e1000_check_for_link() to look at phy 2355 */ 2356 Adapter->shared.mac.get_link_status = B_TRUE; 2357 2358 /* e1000g_link_check takes care of link status change */ 2359 link_changed = e1000g_link_check(Adapter); 2360 2361 /* Get new phy state */ 2362 e1000g_get_phy_state(Adapter); 2363 2364 /* 2365 * If the link timer has not timed out, we'll not notify 2366 * the upper layer with any link state until the link is up. 2367 */ 2368 if (link_changed && !Adapter->link_complete) { 2369 if (Adapter->link_state == LINK_STATE_UP) { 2370 mutex_enter(&Adapter->link_lock); 2371 Adapter->link_complete = B_TRUE; 2372 tid = Adapter->link_tid; 2373 Adapter->link_tid = 0; 2374 mutex_exit(&Adapter->link_lock); 2375 } else { 2376 link_changed = B_FALSE; 2377 } 2378 } 2379 rw_exit(&Adapter->chip_lock); 2380 2381 if (link_changed) { 2382 if (tid != 0) 2383 (void) untimeout(tid); 2384 2385 /* 2386 * Workaround for esb2. Data stuck in fifo on a link 2387 * down event. Stop receiver here and reset in watchdog. 2388 */ 2389 if ((Adapter->link_state == LINK_STATE_DOWN) && 2390 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2391 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2392 E1000_WRITE_REG(hw, E1000_RCTL, 2393 rctl & ~E1000_RCTL_EN); 2394 e1000g_log(Adapter, CE_WARN, 2395 "ESB2 receiver disabled"); 2396 Adapter->esb2_workaround = B_TRUE; 2397 } 2398 if (!Adapter->reset_flag) 2399 mac_link_update(Adapter->mh, 2400 Adapter->link_state); 2401 if (Adapter->link_state == LINK_STATE_UP) 2402 Adapter->reset_flag = B_FALSE; 2403 } 2404 2405 start_watchdog_timer(Adapter); 2406 } 2407 } 2408 2409 static void 2410 e1000g_init_unicst(struct e1000g *Adapter) 2411 { 2412 struct e1000_hw *hw; 2413 int slot; 2414 2415 hw = &Adapter->shared; 2416 2417 if (Adapter->init_count == 0) { 2418 /* Initialize the multiple unicast addresses */ 2419 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2420 2421 /* Workaround for an erratum of 82571 chipst */ 2422 if ((hw->mac.type == e1000_82571) && 2423 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2424 Adapter->unicst_total--; 2425 2426 Adapter->unicst_avail = Adapter->unicst_total; 2427 2428 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2429 /* Clear both the flag and MAC address */ 2430 Adapter->unicst_addr[slot].reg.high = 0; 2431 Adapter->unicst_addr[slot].reg.low = 0; 2432 } 2433 } else { 2434 /* Workaround for an erratum of 82571 chipst */ 2435 if ((hw->mac.type == e1000_82571) && 2436 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2437 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2438 2439 /* Re-configure the RAR registers */ 2440 for (slot = 0; slot < Adapter->unicst_total; slot++) 2441 if (Adapter->unicst_addr[slot].mac.set == 1) 2442 e1000_rar_set(hw, 2443 Adapter->unicst_addr[slot].mac.addr, slot); 2444 } 2445 2446 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2447 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2448 } 2449 2450 static int 2451 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2452 int slot) 2453 { 2454 struct e1000_hw *hw; 2455 2456 hw = &Adapter->shared; 2457 2458 /* 2459 * The first revision of Wiseman silicon (rev 2.0) has an errata 2460 * that requires the receiver to be in reset when any of the 2461 * receive address registers (RAR regs) are accessed. The first 2462 * rev of Wiseman silicon also requires MWI to be disabled when 2463 * a global reset or a receive reset is issued. So before we 2464 * initialize the RARs, we check the rev of the Wiseman controller 2465 * and work around any necessary HW errata. 2466 */ 2467 if ((hw->mac.type == e1000_82542) && 2468 (hw->revision_id == E1000_REVISION_2)) { 2469 e1000_pci_clear_mwi(hw); 2470 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2471 msec_delay(5); 2472 } 2473 if (mac_addr == NULL) { 2474 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2475 E1000_WRITE_FLUSH(hw); 2476 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2477 E1000_WRITE_FLUSH(hw); 2478 /* Clear both the flag and MAC address */ 2479 Adapter->unicst_addr[slot].reg.high = 0; 2480 Adapter->unicst_addr[slot].reg.low = 0; 2481 } else { 2482 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2483 ETHERADDRL); 2484 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2485 Adapter->unicst_addr[slot].mac.set = 1; 2486 } 2487 2488 /* Workaround for an erratum of 82571 chipst */ 2489 if (slot == 0) { 2490 if ((hw->mac.type == e1000_82571) && 2491 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2492 if (mac_addr == NULL) { 2493 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2494 slot << 1, 0); 2495 E1000_WRITE_FLUSH(hw); 2496 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2497 (slot << 1) + 1, 0); 2498 E1000_WRITE_FLUSH(hw); 2499 } else { 2500 e1000_rar_set(hw, (uint8_t *)mac_addr, 2501 LAST_RAR_ENTRY); 2502 } 2503 } 2504 2505 /* 2506 * If we are using Wiseman rev 2.0 silicon, we will have previously 2507 * put the receive in reset, and disabled MWI, to work around some 2508 * HW errata. Now we should take the receiver out of reset, and 2509 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2510 */ 2511 if ((hw->mac.type == e1000_82542) && 2512 (hw->revision_id == E1000_REVISION_2)) { 2513 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2514 msec_delay(1); 2515 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2516 e1000_pci_set_mwi(hw); 2517 e1000g_rx_setup(Adapter); 2518 } 2519 2520 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2521 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2522 return (EIO); 2523 } 2524 2525 return (0); 2526 } 2527 2528 static int 2529 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2530 { 2531 struct e1000_hw *hw = &Adapter->shared; 2532 struct ether_addr *newtable; 2533 size_t new_len; 2534 size_t old_len; 2535 int res = 0; 2536 2537 if ((multiaddr[0] & 01) == 0) { 2538 res = EINVAL; 2539 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2540 goto done; 2541 } 2542 2543 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2544 res = ENOENT; 2545 e1000g_log(Adapter, CE_WARN, 2546 "Adapter requested more than %d mcast addresses", 2547 Adapter->mcast_max_num); 2548 goto done; 2549 } 2550 2551 2552 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2553 old_len = Adapter->mcast_alloc_count * 2554 sizeof (struct ether_addr); 2555 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2556 sizeof (struct ether_addr); 2557 2558 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2559 if (newtable == NULL) { 2560 res = ENOMEM; 2561 e1000g_log(Adapter, CE_WARN, 2562 "Not enough memory to alloc mcast table"); 2563 goto done; 2564 } 2565 2566 if (Adapter->mcast_table != NULL) { 2567 bcopy(Adapter->mcast_table, newtable, old_len); 2568 kmem_free(Adapter->mcast_table, old_len); 2569 } 2570 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2571 Adapter->mcast_table = newtable; 2572 } 2573 2574 bcopy(multiaddr, 2575 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2576 Adapter->mcast_count++; 2577 2578 /* 2579 * Update the MC table in the hardware 2580 */ 2581 e1000g_clear_interrupt(Adapter); 2582 2583 e1000_update_mc_addr_list(hw, 2584 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2585 2586 e1000g_mask_interrupt(Adapter); 2587 2588 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2589 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2590 res = EIO; 2591 } 2592 2593 done: 2594 return (res); 2595 } 2596 2597 static int 2598 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2599 { 2600 struct e1000_hw *hw = &Adapter->shared; 2601 struct ether_addr *newtable; 2602 size_t new_len; 2603 size_t old_len; 2604 unsigned i; 2605 2606 for (i = 0; i < Adapter->mcast_count; i++) { 2607 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2608 ETHERADDRL) == 0) { 2609 for (i++; i < Adapter->mcast_count; i++) { 2610 Adapter->mcast_table[i - 1] = 2611 Adapter->mcast_table[i]; 2612 } 2613 Adapter->mcast_count--; 2614 break; 2615 } 2616 } 2617 2618 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2619 MCAST_ALLOC_SIZE) { 2620 old_len = Adapter->mcast_alloc_count * 2621 sizeof (struct ether_addr); 2622 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2623 sizeof (struct ether_addr); 2624 2625 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2626 if (newtable != NULL) { 2627 bcopy(Adapter->mcast_table, newtable, new_len); 2628 kmem_free(Adapter->mcast_table, old_len); 2629 2630 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2631 Adapter->mcast_table = newtable; 2632 } 2633 } 2634 2635 /* 2636 * Update the MC table in the hardware 2637 */ 2638 e1000g_clear_interrupt(Adapter); 2639 2640 e1000_update_mc_addr_list(hw, 2641 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2642 2643 e1000g_mask_interrupt(Adapter); 2644 2645 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2646 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2647 return (EIO); 2648 } 2649 2650 return (0); 2651 } 2652 2653 static void 2654 e1000g_release_multicast(struct e1000g *Adapter) 2655 { 2656 if (Adapter->mcast_table != NULL) { 2657 kmem_free(Adapter->mcast_table, 2658 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2659 Adapter->mcast_table = NULL; 2660 } 2661 } 2662 2663 int 2664 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2665 { 2666 struct e1000g *Adapter = (struct e1000g *)arg; 2667 int result; 2668 2669 rw_enter(&Adapter->chip_lock, RW_WRITER); 2670 2671 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2672 result = ECANCELED; 2673 goto done; 2674 } 2675 2676 result = (add) ? multicst_add(Adapter, addr) 2677 : multicst_remove(Adapter, addr); 2678 2679 done: 2680 rw_exit(&Adapter->chip_lock); 2681 return (result); 2682 2683 } 2684 2685 int 2686 e1000g_m_promisc(void *arg, boolean_t on) 2687 { 2688 struct e1000g *Adapter = (struct e1000g *)arg; 2689 uint32_t rctl; 2690 2691 rw_enter(&Adapter->chip_lock, RW_WRITER); 2692 2693 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2694 rw_exit(&Adapter->chip_lock); 2695 return (ECANCELED); 2696 } 2697 2698 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2699 2700 if (on) 2701 rctl |= 2702 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2703 else 2704 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2705 2706 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2707 2708 Adapter->e1000g_promisc = on; 2709 2710 rw_exit(&Adapter->chip_lock); 2711 2712 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2713 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2714 return (EIO); 2715 } 2716 2717 return (0); 2718 } 2719 2720 /* 2721 * Entry points to enable and disable interrupts at the granularity of 2722 * a group. 2723 * Turns the poll_mode for the whole adapter on and off to enable or 2724 * override the ring level polling control over the hardware interrupts. 2725 */ 2726 static int 2727 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2728 { 2729 struct e1000g *adapter = (struct e1000g *)arg; 2730 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2731 2732 /* 2733 * Later interrupts at the granularity of the this ring will 2734 * invoke mac_rx() with NULL, indicating the need for another 2735 * software classification. 2736 * We have a single ring usable per adapter now, so we only need to 2737 * reset the rx handle for that one. 2738 * When more RX rings can be used, we should update each one of them. 2739 */ 2740 mutex_enter(&rx_ring->rx_lock); 2741 rx_ring->mrh = NULL; 2742 adapter->poll_mode = B_FALSE; 2743 mutex_exit(&rx_ring->rx_lock); 2744 return (0); 2745 } 2746 2747 static int 2748 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2749 { 2750 struct e1000g *adapter = (struct e1000g *)arg; 2751 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2752 2753 mutex_enter(&rx_ring->rx_lock); 2754 2755 /* 2756 * Later interrupts at the granularity of the this ring will 2757 * invoke mac_rx() with the handle for this ring; 2758 */ 2759 adapter->poll_mode = B_TRUE; 2760 rx_ring->mrh = rx_ring->mrh_init; 2761 mutex_exit(&rx_ring->rx_lock); 2762 return (0); 2763 } 2764 2765 /* 2766 * Entry points to enable and disable interrupts at the granularity of 2767 * a ring. 2768 * adapter poll_mode controls whether we actually proceed with hardware 2769 * interrupt toggling. 2770 */ 2771 static int 2772 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2773 { 2774 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2775 struct e1000g *adapter = rx_ring->adapter; 2776 struct e1000_hw *hw = &adapter->shared; 2777 uint32_t intr_mask; 2778 2779 rw_enter(&adapter->chip_lock, RW_READER); 2780 2781 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2782 rw_exit(&adapter->chip_lock); 2783 return (0); 2784 } 2785 2786 mutex_enter(&rx_ring->rx_lock); 2787 rx_ring->poll_flag = 0; 2788 mutex_exit(&rx_ring->rx_lock); 2789 2790 /* Rx interrupt enabling for MSI and legacy */ 2791 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2792 intr_mask |= E1000_IMS_RXT0; 2793 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2794 E1000_WRITE_FLUSH(hw); 2795 2796 /* Trigger a Rx interrupt to check Rx ring */ 2797 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2798 E1000_WRITE_FLUSH(hw); 2799 2800 rw_exit(&adapter->chip_lock); 2801 return (0); 2802 } 2803 2804 static int 2805 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2806 { 2807 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2808 struct e1000g *adapter = rx_ring->adapter; 2809 struct e1000_hw *hw = &adapter->shared; 2810 2811 rw_enter(&adapter->chip_lock, RW_READER); 2812 2813 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2814 rw_exit(&adapter->chip_lock); 2815 return (0); 2816 } 2817 mutex_enter(&rx_ring->rx_lock); 2818 rx_ring->poll_flag = 1; 2819 mutex_exit(&rx_ring->rx_lock); 2820 2821 /* Rx interrupt disabling for MSI and legacy */ 2822 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2823 E1000_WRITE_FLUSH(hw); 2824 2825 rw_exit(&adapter->chip_lock); 2826 return (0); 2827 } 2828 2829 /* 2830 * e1000g_unicst_find - Find the slot for the specified unicast address 2831 */ 2832 static int 2833 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2834 { 2835 int slot; 2836 2837 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2838 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2839 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2840 mac_addr, ETHERADDRL) == 0)) 2841 return (slot); 2842 } 2843 2844 return (-1); 2845 } 2846 2847 /* 2848 * Entry points to add and remove a MAC address to a ring group. 2849 * The caller takes care of adding and removing the MAC addresses 2850 * to the filter via these two routines. 2851 */ 2852 2853 static int 2854 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2855 { 2856 struct e1000g *Adapter = (struct e1000g *)arg; 2857 int slot, err; 2858 2859 rw_enter(&Adapter->chip_lock, RW_WRITER); 2860 2861 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2862 rw_exit(&Adapter->chip_lock); 2863 return (ECANCELED); 2864 } 2865 2866 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2867 /* The same address is already in slot */ 2868 rw_exit(&Adapter->chip_lock); 2869 return (0); 2870 } 2871 2872 if (Adapter->unicst_avail == 0) { 2873 /* no slots available */ 2874 rw_exit(&Adapter->chip_lock); 2875 return (ENOSPC); 2876 } 2877 2878 /* Search for a free slot */ 2879 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2880 if (Adapter->unicst_addr[slot].mac.set == 0) 2881 break; 2882 } 2883 ASSERT(slot < Adapter->unicst_total); 2884 2885 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2886 if (err == 0) 2887 Adapter->unicst_avail--; 2888 2889 rw_exit(&Adapter->chip_lock); 2890 2891 return (err); 2892 } 2893 2894 static int 2895 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2896 { 2897 struct e1000g *Adapter = (struct e1000g *)arg; 2898 int slot, err; 2899 2900 rw_enter(&Adapter->chip_lock, RW_WRITER); 2901 2902 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2903 rw_exit(&Adapter->chip_lock); 2904 return (ECANCELED); 2905 } 2906 2907 slot = e1000g_unicst_find(Adapter, mac_addr); 2908 if (slot == -1) { 2909 rw_exit(&Adapter->chip_lock); 2910 return (EINVAL); 2911 } 2912 2913 ASSERT(Adapter->unicst_addr[slot].mac.set); 2914 2915 /* Clear this slot */ 2916 err = e1000g_unicst_set(Adapter, NULL, slot); 2917 if (err == 0) 2918 Adapter->unicst_avail++; 2919 2920 rw_exit(&Adapter->chip_lock); 2921 2922 return (err); 2923 } 2924 2925 static int 2926 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2927 { 2928 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2929 2930 mutex_enter(&rx_ring->rx_lock); 2931 rx_ring->ring_gen_num = mr_gen_num; 2932 mutex_exit(&rx_ring->rx_lock); 2933 return (0); 2934 } 2935 2936 /* 2937 * Callback funtion for MAC layer to register all rings. 2938 * 2939 * The hardware supports a single group with currently only one ring 2940 * available. 2941 * Though not offering virtualization ability per se, exposing the 2942 * group/ring still enables the polling and interrupt toggling. 2943 */ 2944 /* ARGSUSED */ 2945 void 2946 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2947 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2948 { 2949 struct e1000g *Adapter = (struct e1000g *)arg; 2950 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2951 mac_intr_t *mintr; 2952 2953 /* 2954 * We advertised only RX group/rings, so the MAC framework shouldn't 2955 * ask for any thing else. 2956 */ 2957 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2958 2959 rx_ring->mrh = rx_ring->mrh_init = rh; 2960 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2961 infop->mri_start = e1000g_ring_start; 2962 infop->mri_stop = NULL; 2963 infop->mri_poll = e1000g_poll_ring; 2964 infop->mri_stat = e1000g_rx_ring_stat; 2965 2966 /* Ring level interrupts */ 2967 mintr = &infop->mri_intr; 2968 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2969 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2970 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2971 if (Adapter->msi_enable) 2972 mintr->mi_ddi_handle = Adapter->htable[0]; 2973 } 2974 2975 /* ARGSUSED */ 2976 static void 2977 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2978 mac_group_info_t *infop, mac_group_handle_t gh) 2979 { 2980 struct e1000g *Adapter = (struct e1000g *)arg; 2981 mac_intr_t *mintr; 2982 2983 /* 2984 * We advertised a single RX ring. Getting a request for anything else 2985 * signifies a bug in the MAC framework. 2986 */ 2987 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2988 2989 Adapter->rx_group = gh; 2990 2991 infop->mgi_driver = (mac_group_driver_t)Adapter; 2992 infop->mgi_start = NULL; 2993 infop->mgi_stop = NULL; 2994 infop->mgi_addmac = e1000g_addmac; 2995 infop->mgi_remmac = e1000g_remmac; 2996 infop->mgi_count = 1; 2997 2998 /* Group level interrupts */ 2999 mintr = &infop->mgi_intr; 3000 mintr->mi_handle = (mac_intr_handle_t)Adapter; 3001 mintr->mi_enable = e1000g_rx_group_intr_enable; 3002 mintr->mi_disable = e1000g_rx_group_intr_disable; 3003 } 3004 3005 static boolean_t 3006 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 3007 { 3008 struct e1000g *Adapter = (struct e1000g *)arg; 3009 3010 switch (cap) { 3011 case MAC_CAPAB_HCKSUM: { 3012 uint32_t *txflags = cap_data; 3013 3014 if (Adapter->tx_hcksum_enable) 3015 *txflags = HCKSUM_IPHDRCKSUM | 3016 HCKSUM_INET_PARTIAL; 3017 else 3018 return (B_FALSE); 3019 break; 3020 } 3021 3022 case MAC_CAPAB_LSO: { 3023 mac_capab_lso_t *cap_lso = cap_data; 3024 3025 if (Adapter->lso_enable) { 3026 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 3027 cap_lso->lso_basic_tcp_ipv4.lso_max = 3028 E1000_LSO_MAXLEN; 3029 } else 3030 return (B_FALSE); 3031 break; 3032 } 3033 case MAC_CAPAB_RINGS: { 3034 mac_capab_rings_t *cap_rings = cap_data; 3035 3036 /* No TX rings exposed yet */ 3037 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 3038 return (B_FALSE); 3039 3040 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 3041 cap_rings->mr_rnum = 1; 3042 cap_rings->mr_gnum = 1; 3043 cap_rings->mr_rget = e1000g_fill_ring; 3044 cap_rings->mr_gget = e1000g_fill_group; 3045 break; 3046 } 3047 default: 3048 return (B_FALSE); 3049 } 3050 return (B_TRUE); 3051 } 3052 3053 static boolean_t 3054 e1000g_param_locked(mac_prop_id_t pr_num) 3055 { 3056 /* 3057 * All en_* parameters are locked (read-only) while 3058 * the device is in any sort of loopback mode ... 3059 */ 3060 switch (pr_num) { 3061 case MAC_PROP_EN_1000FDX_CAP: 3062 case MAC_PROP_EN_1000HDX_CAP: 3063 case MAC_PROP_EN_100FDX_CAP: 3064 case MAC_PROP_EN_100HDX_CAP: 3065 case MAC_PROP_EN_10FDX_CAP: 3066 case MAC_PROP_EN_10HDX_CAP: 3067 case MAC_PROP_AUTONEG: 3068 case MAC_PROP_FLOWCTRL: 3069 return (B_TRUE); 3070 } 3071 return (B_FALSE); 3072 } 3073 3074 /* 3075 * callback function for set/get of properties 3076 */ 3077 static int 3078 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3079 uint_t pr_valsize, const void *pr_val) 3080 { 3081 struct e1000g *Adapter = arg; 3082 struct e1000_hw *hw = &Adapter->shared; 3083 struct e1000_fc_info *fc = &Adapter->shared.fc; 3084 int err = 0; 3085 link_flowctrl_t flowctrl; 3086 uint32_t cur_mtu, new_mtu; 3087 3088 rw_enter(&Adapter->chip_lock, RW_WRITER); 3089 3090 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3091 rw_exit(&Adapter->chip_lock); 3092 return (ECANCELED); 3093 } 3094 3095 if (Adapter->loopback_mode != E1000G_LB_NONE && 3096 e1000g_param_locked(pr_num)) { 3097 /* 3098 * All en_* parameters are locked (read-only) 3099 * while the device is in any sort of loopback mode. 3100 */ 3101 rw_exit(&Adapter->chip_lock); 3102 return (EBUSY); 3103 } 3104 3105 switch (pr_num) { 3106 case MAC_PROP_EN_1000FDX_CAP: 3107 if (hw->phy.media_type != e1000_media_type_copper) { 3108 err = ENOTSUP; 3109 break; 3110 } 3111 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3112 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3113 goto reset; 3114 case MAC_PROP_EN_100FDX_CAP: 3115 if (hw->phy.media_type != e1000_media_type_copper) { 3116 err = ENOTSUP; 3117 break; 3118 } 3119 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3120 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3121 goto reset; 3122 case MAC_PROP_EN_100HDX_CAP: 3123 if (hw->phy.media_type != e1000_media_type_copper) { 3124 err = ENOTSUP; 3125 break; 3126 } 3127 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3128 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3129 goto reset; 3130 case MAC_PROP_EN_10FDX_CAP: 3131 if (hw->phy.media_type != e1000_media_type_copper) { 3132 err = ENOTSUP; 3133 break; 3134 } 3135 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3136 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3137 goto reset; 3138 case MAC_PROP_EN_10HDX_CAP: 3139 if (hw->phy.media_type != e1000_media_type_copper) { 3140 err = ENOTSUP; 3141 break; 3142 } 3143 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3144 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3145 goto reset; 3146 case MAC_PROP_AUTONEG: 3147 if (hw->phy.media_type != e1000_media_type_copper) { 3148 err = ENOTSUP; 3149 break; 3150 } 3151 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3152 goto reset; 3153 case MAC_PROP_FLOWCTRL: 3154 fc->send_xon = B_TRUE; 3155 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3156 3157 switch (flowctrl) { 3158 default: 3159 err = EINVAL; 3160 break; 3161 case LINK_FLOWCTRL_NONE: 3162 fc->requested_mode = e1000_fc_none; 3163 break; 3164 case LINK_FLOWCTRL_RX: 3165 fc->requested_mode = e1000_fc_rx_pause; 3166 break; 3167 case LINK_FLOWCTRL_TX: 3168 fc->requested_mode = e1000_fc_tx_pause; 3169 break; 3170 case LINK_FLOWCTRL_BI: 3171 fc->requested_mode = e1000_fc_full; 3172 break; 3173 } 3174 reset: 3175 if (err == 0) { 3176 /* check PCH limits & reset the link */ 3177 e1000g_pch_limits(Adapter); 3178 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3179 err = EINVAL; 3180 } 3181 break; 3182 case MAC_PROP_ADV_1000FDX_CAP: 3183 case MAC_PROP_ADV_1000HDX_CAP: 3184 case MAC_PROP_ADV_100FDX_CAP: 3185 case MAC_PROP_ADV_100HDX_CAP: 3186 case MAC_PROP_ADV_10FDX_CAP: 3187 case MAC_PROP_ADV_10HDX_CAP: 3188 case MAC_PROP_EN_1000HDX_CAP: 3189 case MAC_PROP_STATUS: 3190 case MAC_PROP_SPEED: 3191 case MAC_PROP_DUPLEX: 3192 err = ENOTSUP; /* read-only prop. Can't set this. */ 3193 break; 3194 case MAC_PROP_MTU: 3195 /* adapter must be stopped for an MTU change */ 3196 if (Adapter->e1000g_state & E1000G_STARTED) { 3197 err = EBUSY; 3198 break; 3199 } 3200 3201 cur_mtu = Adapter->default_mtu; 3202 3203 /* get new requested MTU */ 3204 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3205 if (new_mtu == cur_mtu) { 3206 err = 0; 3207 break; 3208 } 3209 3210 if ((new_mtu < DEFAULT_MTU) || 3211 (new_mtu > Adapter->max_mtu)) { 3212 err = EINVAL; 3213 break; 3214 } 3215 3216 /* inform MAC framework of new MTU */ 3217 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3218 3219 if (err == 0) { 3220 Adapter->default_mtu = new_mtu; 3221 Adapter->max_frame_size = 3222 e1000g_mtu2maxframe(new_mtu); 3223 3224 /* 3225 * check PCH limits & set buffer sizes to 3226 * match new MTU 3227 */ 3228 e1000g_pch_limits(Adapter); 3229 e1000g_set_bufsize(Adapter); 3230 3231 /* 3232 * decrease the number of descriptors and free 3233 * packets for jumbo frames to reduce tx/rx 3234 * resource consumption 3235 */ 3236 if (Adapter->max_frame_size >= 3237 (FRAME_SIZE_UPTO_4K - 3238 E1000G_IPALIGNPRESERVEROOM)) { 3239 3240 if (Adapter->tx_desc_num_flag == 0) 3241 Adapter->tx_desc_num = 3242 DEFAULT_JUMBO_NUM_TX_DESC; 3243 3244 if (Adapter->rx_desc_num_flag == 0) 3245 Adapter->rx_desc_num = 3246 DEFAULT_JUMBO_NUM_RX_DESC; 3247 3248 if (Adapter->tx_buf_num_flag == 0) 3249 Adapter->tx_freelist_num = 3250 DEFAULT_JUMBO_NUM_TX_BUF; 3251 3252 if (Adapter->rx_buf_num_flag == 0) 3253 Adapter->rx_freelist_num = 3254 DEFAULT_JUMBO_NUM_RX_BUF; 3255 } else { 3256 if (Adapter->tx_desc_num_flag == 0) 3257 Adapter->tx_desc_num = 3258 DEFAULT_NUM_TX_DESCRIPTOR; 3259 3260 if (Adapter->rx_desc_num_flag == 0) 3261 Adapter->rx_desc_num = 3262 DEFAULT_NUM_RX_DESCRIPTOR; 3263 3264 if (Adapter->tx_buf_num_flag == 0) 3265 Adapter->tx_freelist_num = 3266 DEFAULT_NUM_TX_FREELIST; 3267 3268 if (Adapter->rx_buf_num_flag == 0) 3269 Adapter->rx_freelist_num = 3270 DEFAULT_NUM_RX_FREELIST; 3271 } 3272 } 3273 break; 3274 case MAC_PROP_PRIVATE: 3275 err = e1000g_set_priv_prop(Adapter, pr_name, 3276 pr_valsize, pr_val); 3277 break; 3278 default: 3279 err = ENOTSUP; 3280 break; 3281 } 3282 rw_exit(&Adapter->chip_lock); 3283 return (err); 3284 } 3285 3286 static int 3287 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3288 uint_t pr_valsize, void *pr_val) 3289 { 3290 struct e1000g *Adapter = arg; 3291 struct e1000_fc_info *fc = &Adapter->shared.fc; 3292 int err = 0; 3293 link_flowctrl_t flowctrl; 3294 uint64_t tmp = 0; 3295 3296 switch (pr_num) { 3297 case MAC_PROP_DUPLEX: 3298 ASSERT(pr_valsize >= sizeof (link_duplex_t)); 3299 bcopy(&Adapter->link_duplex, pr_val, 3300 sizeof (link_duplex_t)); 3301 break; 3302 case MAC_PROP_SPEED: 3303 ASSERT(pr_valsize >= sizeof (uint64_t)); 3304 tmp = Adapter->link_speed * 1000000ull; 3305 bcopy(&tmp, pr_val, sizeof (tmp)); 3306 break; 3307 case MAC_PROP_AUTONEG: 3308 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3309 break; 3310 case MAC_PROP_FLOWCTRL: 3311 ASSERT(pr_valsize >= sizeof (link_flowctrl_t)); 3312 switch (fc->current_mode) { 3313 case e1000_fc_none: 3314 flowctrl = LINK_FLOWCTRL_NONE; 3315 break; 3316 case e1000_fc_rx_pause: 3317 flowctrl = LINK_FLOWCTRL_RX; 3318 break; 3319 case e1000_fc_tx_pause: 3320 flowctrl = LINK_FLOWCTRL_TX; 3321 break; 3322 case e1000_fc_full: 3323 flowctrl = LINK_FLOWCTRL_BI; 3324 break; 3325 } 3326 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3327 break; 3328 case MAC_PROP_ADV_1000FDX_CAP: 3329 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3330 break; 3331 case MAC_PROP_EN_1000FDX_CAP: 3332 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3333 break; 3334 case MAC_PROP_ADV_1000HDX_CAP: 3335 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3336 break; 3337 case MAC_PROP_EN_1000HDX_CAP: 3338 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3339 break; 3340 case MAC_PROP_ADV_100FDX_CAP: 3341 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3342 break; 3343 case MAC_PROP_EN_100FDX_CAP: 3344 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3345 break; 3346 case MAC_PROP_ADV_100HDX_CAP: 3347 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3348 break; 3349 case MAC_PROP_EN_100HDX_CAP: 3350 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3351 break; 3352 case MAC_PROP_ADV_10FDX_CAP: 3353 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3354 break; 3355 case MAC_PROP_EN_10FDX_CAP: 3356 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3357 break; 3358 case MAC_PROP_ADV_10HDX_CAP: 3359 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3360 break; 3361 case MAC_PROP_EN_10HDX_CAP: 3362 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3363 break; 3364 case MAC_PROP_ADV_100T4_CAP: 3365 case MAC_PROP_EN_100T4_CAP: 3366 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3367 break; 3368 case MAC_PROP_PRIVATE: 3369 err = e1000g_get_priv_prop(Adapter, pr_name, 3370 pr_valsize, pr_val); 3371 break; 3372 default: 3373 err = ENOTSUP; 3374 break; 3375 } 3376 3377 return (err); 3378 } 3379 3380 static void 3381 e1000g_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3382 mac_prop_info_handle_t prh) 3383 { 3384 struct e1000g *Adapter = arg; 3385 struct e1000_hw *hw = &Adapter->shared; 3386 3387 switch (pr_num) { 3388 case MAC_PROP_DUPLEX: 3389 case MAC_PROP_SPEED: 3390 case MAC_PROP_ADV_1000FDX_CAP: 3391 case MAC_PROP_ADV_1000HDX_CAP: 3392 case MAC_PROP_ADV_100FDX_CAP: 3393 case MAC_PROP_ADV_100HDX_CAP: 3394 case MAC_PROP_ADV_10FDX_CAP: 3395 case MAC_PROP_ADV_10HDX_CAP: 3396 case MAC_PROP_ADV_100T4_CAP: 3397 case MAC_PROP_EN_100T4_CAP: 3398 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3399 break; 3400 3401 case MAC_PROP_EN_1000FDX_CAP: 3402 if (hw->phy.media_type != e1000_media_type_copper) { 3403 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3404 } else { 3405 mac_prop_info_set_default_uint8(prh, 3406 ((Adapter->phy_ext_status & 3407 IEEE_ESR_1000T_FD_CAPS) || 3408 (Adapter->phy_ext_status & 3409 IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0); 3410 } 3411 break; 3412 3413 case MAC_PROP_EN_100FDX_CAP: 3414 if (hw->phy.media_type != e1000_media_type_copper) { 3415 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3416 } else { 3417 mac_prop_info_set_default_uint8(prh, 3418 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3419 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3420 ? 1 : 0); 3421 } 3422 break; 3423 3424 case MAC_PROP_EN_100HDX_CAP: 3425 if (hw->phy.media_type != e1000_media_type_copper) { 3426 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3427 } else { 3428 mac_prop_info_set_default_uint8(prh, 3429 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 3430 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 3431 ? 1 : 0); 3432 } 3433 break; 3434 3435 case MAC_PROP_EN_10FDX_CAP: 3436 if (hw->phy.media_type != e1000_media_type_copper) { 3437 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3438 } else { 3439 mac_prop_info_set_default_uint8(prh, 3440 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0); 3441 } 3442 break; 3443 3444 case MAC_PROP_EN_10HDX_CAP: 3445 if (hw->phy.media_type != e1000_media_type_copper) { 3446 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3447 } else { 3448 mac_prop_info_set_default_uint8(prh, 3449 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0); 3450 } 3451 break; 3452 3453 case MAC_PROP_EN_1000HDX_CAP: 3454 if (hw->phy.media_type != e1000_media_type_copper) 3455 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3456 break; 3457 3458 case MAC_PROP_AUTONEG: 3459 if (hw->phy.media_type != e1000_media_type_copper) { 3460 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3461 } else { 3462 mac_prop_info_set_default_uint8(prh, 3463 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) 3464 ? 1 : 0); 3465 } 3466 break; 3467 3468 case MAC_PROP_FLOWCTRL: 3469 mac_prop_info_set_default_link_flowctrl(prh, LINK_FLOWCTRL_BI); 3470 break; 3471 3472 case MAC_PROP_MTU: { 3473 struct e1000_mac_info *mac = &Adapter->shared.mac; 3474 struct e1000_phy_info *phy = &Adapter->shared.phy; 3475 uint32_t max; 3476 3477 /* some MAC types do not support jumbo frames */ 3478 if ((mac->type == e1000_ich8lan) || 3479 ((mac->type == e1000_ich9lan) && (phy->type == 3480 e1000_phy_ife))) { 3481 max = DEFAULT_MTU; 3482 } else { 3483 max = Adapter->max_mtu; 3484 } 3485 3486 mac_prop_info_set_range_uint32(prh, DEFAULT_MTU, max); 3487 break; 3488 } 3489 case MAC_PROP_PRIVATE: { 3490 char valstr[64]; 3491 int value; 3492 3493 if (strcmp(pr_name, "_adv_pause_cap") == 0 || 3494 strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3495 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3496 return; 3497 } else if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3498 value = DEFAULT_TX_BCOPY_THRESHOLD; 3499 } else if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3500 value = DEFAULT_TX_INTR_ENABLE; 3501 } else if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3502 value = DEFAULT_TX_INTR_DELAY; 3503 } else if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3504 value = DEFAULT_TX_INTR_ABS_DELAY; 3505 } else if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3506 value = DEFAULT_RX_BCOPY_THRESHOLD; 3507 } else if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3508 value = DEFAULT_RX_LIMIT_ON_INTR; 3509 } else if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3510 value = DEFAULT_RX_INTR_DELAY; 3511 } else if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3512 value = DEFAULT_RX_INTR_ABS_DELAY; 3513 } else if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3514 value = DEFAULT_INTR_THROTTLING; 3515 } else if (strcmp(pr_name, "_intr_adaptive") == 0) { 3516 value = 1; 3517 } else { 3518 return; 3519 } 3520 3521 (void) snprintf(valstr, sizeof (valstr), "%d", value); 3522 mac_prop_info_set_default_str(prh, valstr); 3523 break; 3524 } 3525 } 3526 } 3527 3528 /* ARGSUSED2 */ 3529 static int 3530 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3531 uint_t pr_valsize, const void *pr_val) 3532 { 3533 int err = 0; 3534 long result; 3535 struct e1000_hw *hw = &Adapter->shared; 3536 3537 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3538 if (pr_val == NULL) { 3539 err = EINVAL; 3540 return (err); 3541 } 3542 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3543 if (result < MIN_TX_BCOPY_THRESHOLD || 3544 result > MAX_TX_BCOPY_THRESHOLD) 3545 err = EINVAL; 3546 else { 3547 Adapter->tx_bcopy_thresh = (uint32_t)result; 3548 } 3549 return (err); 3550 } 3551 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3552 if (pr_val == NULL) { 3553 err = EINVAL; 3554 return (err); 3555 } 3556 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3557 if (result < 0 || result > 1) 3558 err = EINVAL; 3559 else { 3560 Adapter->tx_intr_enable = (result == 1) ? 3561 B_TRUE: B_FALSE; 3562 if (Adapter->tx_intr_enable) 3563 e1000g_mask_tx_interrupt(Adapter); 3564 else 3565 e1000g_clear_tx_interrupt(Adapter); 3566 if (e1000g_check_acc_handle( 3567 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3568 ddi_fm_service_impact(Adapter->dip, 3569 DDI_SERVICE_DEGRADED); 3570 err = EIO; 3571 } 3572 } 3573 return (err); 3574 } 3575 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3576 if (pr_val == NULL) { 3577 err = EINVAL; 3578 return (err); 3579 } 3580 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3581 if (result < MIN_TX_INTR_DELAY || 3582 result > MAX_TX_INTR_DELAY) 3583 err = EINVAL; 3584 else { 3585 Adapter->tx_intr_delay = (uint32_t)result; 3586 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3587 if (e1000g_check_acc_handle( 3588 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3589 ddi_fm_service_impact(Adapter->dip, 3590 DDI_SERVICE_DEGRADED); 3591 err = EIO; 3592 } 3593 } 3594 return (err); 3595 } 3596 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3597 if (pr_val == NULL) { 3598 err = EINVAL; 3599 return (err); 3600 } 3601 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3602 if (result < MIN_TX_INTR_ABS_DELAY || 3603 result > MAX_TX_INTR_ABS_DELAY) 3604 err = EINVAL; 3605 else { 3606 Adapter->tx_intr_abs_delay = (uint32_t)result; 3607 E1000_WRITE_REG(hw, E1000_TADV, 3608 Adapter->tx_intr_abs_delay); 3609 if (e1000g_check_acc_handle( 3610 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3611 ddi_fm_service_impact(Adapter->dip, 3612 DDI_SERVICE_DEGRADED); 3613 err = EIO; 3614 } 3615 } 3616 return (err); 3617 } 3618 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3619 if (pr_val == NULL) { 3620 err = EINVAL; 3621 return (err); 3622 } 3623 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3624 if (result < MIN_RX_BCOPY_THRESHOLD || 3625 result > MAX_RX_BCOPY_THRESHOLD) 3626 err = EINVAL; 3627 else 3628 Adapter->rx_bcopy_thresh = (uint32_t)result; 3629 return (err); 3630 } 3631 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3632 if (pr_val == NULL) { 3633 err = EINVAL; 3634 return (err); 3635 } 3636 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3637 if (result < MIN_RX_LIMIT_ON_INTR || 3638 result > MAX_RX_LIMIT_ON_INTR) 3639 err = EINVAL; 3640 else 3641 Adapter->rx_limit_onintr = (uint32_t)result; 3642 return (err); 3643 } 3644 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3645 if (pr_val == NULL) { 3646 err = EINVAL; 3647 return (err); 3648 } 3649 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3650 if (result < MIN_RX_INTR_DELAY || 3651 result > MAX_RX_INTR_DELAY) 3652 err = EINVAL; 3653 else { 3654 Adapter->rx_intr_delay = (uint32_t)result; 3655 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3656 if (e1000g_check_acc_handle( 3657 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3658 ddi_fm_service_impact(Adapter->dip, 3659 DDI_SERVICE_DEGRADED); 3660 err = EIO; 3661 } 3662 } 3663 return (err); 3664 } 3665 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3666 if (pr_val == NULL) { 3667 err = EINVAL; 3668 return (err); 3669 } 3670 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3671 if (result < MIN_RX_INTR_ABS_DELAY || 3672 result > MAX_RX_INTR_ABS_DELAY) 3673 err = EINVAL; 3674 else { 3675 Adapter->rx_intr_abs_delay = (uint32_t)result; 3676 E1000_WRITE_REG(hw, E1000_RADV, 3677 Adapter->rx_intr_abs_delay); 3678 if (e1000g_check_acc_handle( 3679 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3680 ddi_fm_service_impact(Adapter->dip, 3681 DDI_SERVICE_DEGRADED); 3682 err = EIO; 3683 } 3684 } 3685 return (err); 3686 } 3687 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3688 if (pr_val == NULL) { 3689 err = EINVAL; 3690 return (err); 3691 } 3692 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3693 if (result < MIN_INTR_THROTTLING || 3694 result > MAX_INTR_THROTTLING) 3695 err = EINVAL; 3696 else { 3697 if (hw->mac.type >= e1000_82540) { 3698 Adapter->intr_throttling_rate = 3699 (uint32_t)result; 3700 E1000_WRITE_REG(hw, E1000_ITR, 3701 Adapter->intr_throttling_rate); 3702 if (e1000g_check_acc_handle( 3703 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3704 ddi_fm_service_impact(Adapter->dip, 3705 DDI_SERVICE_DEGRADED); 3706 err = EIO; 3707 } 3708 } else 3709 err = EINVAL; 3710 } 3711 return (err); 3712 } 3713 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3714 if (pr_val == NULL) { 3715 err = EINVAL; 3716 return (err); 3717 } 3718 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3719 if (result < 0 || result > 1) 3720 err = EINVAL; 3721 else { 3722 if (hw->mac.type >= e1000_82540) { 3723 Adapter->intr_adaptive = (result == 1) ? 3724 B_TRUE : B_FALSE; 3725 } else { 3726 err = EINVAL; 3727 } 3728 } 3729 return (err); 3730 } 3731 return (ENOTSUP); 3732 } 3733 3734 static int 3735 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3736 uint_t pr_valsize, void *pr_val) 3737 { 3738 int err = ENOTSUP; 3739 int value; 3740 3741 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3742 value = Adapter->param_adv_pause; 3743 err = 0; 3744 goto done; 3745 } 3746 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3747 value = Adapter->param_adv_asym_pause; 3748 err = 0; 3749 goto done; 3750 } 3751 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3752 value = Adapter->tx_bcopy_thresh; 3753 err = 0; 3754 goto done; 3755 } 3756 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3757 value = Adapter->tx_intr_enable; 3758 err = 0; 3759 goto done; 3760 } 3761 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3762 value = Adapter->tx_intr_delay; 3763 err = 0; 3764 goto done; 3765 } 3766 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3767 value = Adapter->tx_intr_abs_delay; 3768 err = 0; 3769 goto done; 3770 } 3771 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3772 value = Adapter->rx_bcopy_thresh; 3773 err = 0; 3774 goto done; 3775 } 3776 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3777 value = Adapter->rx_limit_onintr; 3778 err = 0; 3779 goto done; 3780 } 3781 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3782 value = Adapter->rx_intr_delay; 3783 err = 0; 3784 goto done; 3785 } 3786 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3787 value = Adapter->rx_intr_abs_delay; 3788 err = 0; 3789 goto done; 3790 } 3791 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3792 value = Adapter->intr_throttling_rate; 3793 err = 0; 3794 goto done; 3795 } 3796 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3797 value = Adapter->intr_adaptive; 3798 err = 0; 3799 goto done; 3800 } 3801 done: 3802 if (err == 0) { 3803 (void) snprintf(pr_val, pr_valsize, "%d", value); 3804 } 3805 return (err); 3806 } 3807 3808 /* 3809 * e1000g_get_conf - get configurations set in e1000g.conf 3810 * This routine gets user-configured values out of the configuration 3811 * file e1000g.conf. 3812 * 3813 * For each configurable value, there is a minimum, a maximum, and a 3814 * default. 3815 * If user does not configure a value, use the default. 3816 * If user configures below the minimum, use the minumum. 3817 * If user configures above the maximum, use the maxumum. 3818 */ 3819 static void 3820 e1000g_get_conf(struct e1000g *Adapter) 3821 { 3822 struct e1000_hw *hw = &Adapter->shared; 3823 boolean_t tbi_compatibility = B_FALSE; 3824 boolean_t is_jumbo = B_FALSE; 3825 int propval; 3826 /* 3827 * decrease the number of descriptors and free packets 3828 * for jumbo frames to reduce tx/rx resource consumption 3829 */ 3830 if (Adapter->max_frame_size >= 3831 (FRAME_SIZE_UPTO_4K - 3832 E1000G_IPALIGNPRESERVEROOM)) { 3833 is_jumbo = B_TRUE; 3834 } 3835 3836 /* 3837 * get each configurable property from e1000g.conf 3838 */ 3839 3840 /* 3841 * NumTxDescriptors 3842 */ 3843 Adapter->tx_desc_num_flag = 3844 e1000g_get_prop(Adapter, "NumTxDescriptors", 3845 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3846 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 3847 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 3848 Adapter->tx_desc_num = propval; 3849 3850 /* 3851 * NumRxDescriptors 3852 */ 3853 Adapter->rx_desc_num_flag = 3854 e1000g_get_prop(Adapter, "NumRxDescriptors", 3855 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3856 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 3857 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 3858 Adapter->rx_desc_num = propval; 3859 3860 /* 3861 * NumRxFreeList 3862 */ 3863 Adapter->rx_buf_num_flag = 3864 e1000g_get_prop(Adapter, "NumRxFreeList", 3865 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3866 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 3867 : DEFAULT_NUM_RX_FREELIST, &propval); 3868 Adapter->rx_freelist_num = propval; 3869 3870 /* 3871 * NumTxPacketList 3872 */ 3873 Adapter->tx_buf_num_flag = 3874 e1000g_get_prop(Adapter, "NumTxPacketList", 3875 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3876 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 3877 : DEFAULT_NUM_TX_FREELIST, &propval); 3878 Adapter->tx_freelist_num = propval; 3879 3880 /* 3881 * FlowControl 3882 */ 3883 hw->fc.send_xon = B_TRUE; 3884 (void) e1000g_get_prop(Adapter, "FlowControl", 3885 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 3886 hw->fc.requested_mode = propval; 3887 /* 4 is the setting that says "let the eeprom decide" */ 3888 if (hw->fc.requested_mode == 4) 3889 hw->fc.requested_mode = e1000_fc_default; 3890 3891 /* 3892 * Max Num Receive Packets on Interrupt 3893 */ 3894 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3895 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3896 DEFAULT_RX_LIMIT_ON_INTR, &propval); 3897 Adapter->rx_limit_onintr = propval; 3898 3899 /* 3900 * PHY master slave setting 3901 */ 3902 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 3903 e1000_ms_hw_default, e1000_ms_auto, 3904 e1000_ms_hw_default, &propval); 3905 hw->phy.ms_type = propval; 3906 3907 /* 3908 * Parameter which controls TBI mode workaround, which is only 3909 * needed on certain switches such as Cisco 6500/Foundry 3910 */ 3911 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3912 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 3913 tbi_compatibility = (propval == 1); 3914 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3915 3916 /* 3917 * MSI Enable 3918 */ 3919 (void) e1000g_get_prop(Adapter, "MSIEnable", 3920 0, 1, DEFAULT_MSI_ENABLE, &propval); 3921 Adapter->msi_enable = (propval == 1); 3922 3923 /* 3924 * Interrupt Throttling Rate 3925 */ 3926 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 3927 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3928 DEFAULT_INTR_THROTTLING, &propval); 3929 Adapter->intr_throttling_rate = propval; 3930 3931 /* 3932 * Adaptive Interrupt Blanking Enable/Disable 3933 * It is enabled by default 3934 */ 3935 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 3936 &propval); 3937 Adapter->intr_adaptive = (propval == 1); 3938 3939 /* 3940 * Hardware checksum enable/disable parameter 3941 */ 3942 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 3943 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 3944 Adapter->tx_hcksum_enable = (propval == 1); 3945 /* 3946 * Checksum on/off selection via global parameters. 3947 * 3948 * If the chip is flagged as not capable of (correctly) 3949 * handling checksumming, we don't enable it on either 3950 * Rx or Tx side. Otherwise, we take this chip's settings 3951 * from the patchable global defaults. 3952 * 3953 * We advertise our capabilities only if TX offload is 3954 * enabled. On receive, the stack will accept checksummed 3955 * packets anyway, even if we haven't said we can deliver 3956 * them. 3957 */ 3958 switch (hw->mac.type) { 3959 case e1000_82540: 3960 case e1000_82544: 3961 case e1000_82545: 3962 case e1000_82545_rev_3: 3963 case e1000_82546: 3964 case e1000_82546_rev_3: 3965 case e1000_82571: 3966 case e1000_82572: 3967 case e1000_82573: 3968 case e1000_80003es2lan: 3969 break; 3970 /* 3971 * For the following Intel PRO/1000 chipsets, we have not 3972 * tested the hardware checksum offload capability, so we 3973 * disable the capability for them. 3974 * e1000_82542, 3975 * e1000_82543, 3976 * e1000_82541, 3977 * e1000_82541_rev_2, 3978 * e1000_82547, 3979 * e1000_82547_rev_2, 3980 */ 3981 default: 3982 Adapter->tx_hcksum_enable = B_FALSE; 3983 } 3984 3985 /* 3986 * Large Send Offloading(LSO) Enable/Disable 3987 * If the tx hardware checksum is not enabled, LSO should be 3988 * disabled. 3989 */ 3990 (void) e1000g_get_prop(Adapter, "lso_enable", 3991 0, 1, DEFAULT_LSO_ENABLE, &propval); 3992 Adapter->lso_enable = (propval == 1); 3993 3994 switch (hw->mac.type) { 3995 case e1000_82546: 3996 case e1000_82546_rev_3: 3997 if (Adapter->lso_enable) 3998 Adapter->lso_premature_issue = B_TRUE; 3999 /* FALLTHRU */ 4000 case e1000_82571: 4001 case e1000_82572: 4002 case e1000_82573: 4003 case e1000_80003es2lan: 4004 break; 4005 default: 4006 Adapter->lso_enable = B_FALSE; 4007 } 4008 4009 if (!Adapter->tx_hcksum_enable) { 4010 Adapter->lso_premature_issue = B_FALSE; 4011 Adapter->lso_enable = B_FALSE; 4012 } 4013 4014 /* 4015 * If mem_workaround_82546 is enabled, the rx buffer allocated by 4016 * e1000_82545, e1000_82546 and e1000_82546_rev_3 4017 * will not cross 64k boundary. 4018 */ 4019 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 4020 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 4021 Adapter->mem_workaround_82546 = (propval == 1); 4022 4023 /* 4024 * Max number of multicast addresses 4025 */ 4026 (void) e1000g_get_prop(Adapter, "mcast_max_num", 4027 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 4028 &propval); 4029 Adapter->mcast_max_num = propval; 4030 } 4031 4032 /* 4033 * e1000g_get_prop - routine to read properties 4034 * 4035 * Get a user-configure property value out of the configuration 4036 * file e1000g.conf. 4037 * 4038 * Caller provides name of the property, a default value, a minimum 4039 * value, a maximum value and a pointer to the returned property 4040 * value. 4041 * 4042 * Return B_TRUE if the configured value of the property is not a default 4043 * value, otherwise return B_FALSE. 4044 */ 4045 static boolean_t 4046 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 4047 char *propname, /* name of the property */ 4048 int minval, /* minimum acceptable value */ 4049 int maxval, /* maximim acceptable value */ 4050 int defval, /* default value */ 4051 int *propvalue) /* property value return to caller */ 4052 { 4053 int propval; /* value returned for requested property */ 4054 int *props; /* point to array of properties returned */ 4055 uint_t nprops; /* number of property value returned */ 4056 boolean_t ret = B_TRUE; 4057 4058 /* 4059 * get the array of properties from the config file 4060 */ 4061 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 4062 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 4063 /* got some properties, test if we got enough */ 4064 if (Adapter->instance < nprops) { 4065 propval = props[Adapter->instance]; 4066 } else { 4067 /* not enough properties configured */ 4068 propval = defval; 4069 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4070 "Not Enough %s values found in e1000g.conf" 4071 " - set to %d\n", 4072 propname, propval); 4073 ret = B_FALSE; 4074 } 4075 4076 /* free memory allocated for properties */ 4077 ddi_prop_free(props); 4078 4079 } else { 4080 propval = defval; 4081 ret = B_FALSE; 4082 } 4083 4084 /* 4085 * enforce limits 4086 */ 4087 if (propval > maxval) { 4088 propval = maxval; 4089 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4090 "Too High %s value in e1000g.conf - set to %d\n", 4091 propname, propval); 4092 } 4093 4094 if (propval < minval) { 4095 propval = minval; 4096 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4097 "Too Low %s value in e1000g.conf - set to %d\n", 4098 propname, propval); 4099 } 4100 4101 *propvalue = propval; 4102 return (ret); 4103 } 4104 4105 static boolean_t 4106 e1000g_link_check(struct e1000g *Adapter) 4107 { 4108 uint16_t speed, duplex, phydata; 4109 boolean_t link_changed = B_FALSE; 4110 struct e1000_hw *hw; 4111 uint32_t reg_tarc; 4112 4113 hw = &Adapter->shared; 4114 4115 if (e1000g_link_up(Adapter)) { 4116 /* 4117 * The Link is up, check whether it was marked as down earlier 4118 */ 4119 if (Adapter->link_state != LINK_STATE_UP) { 4120 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 4121 Adapter->link_speed = speed; 4122 Adapter->link_duplex = duplex; 4123 Adapter->link_state = LINK_STATE_UP; 4124 link_changed = B_TRUE; 4125 4126 if (Adapter->link_speed == SPEED_1000) 4127 Adapter->stall_threshold = TX_STALL_TIME_2S; 4128 else 4129 Adapter->stall_threshold = TX_STALL_TIME_8S; 4130 4131 Adapter->tx_link_down_timeout = 0; 4132 4133 if ((hw->mac.type == e1000_82571) || 4134 (hw->mac.type == e1000_82572)) { 4135 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 4136 if (speed == SPEED_1000) 4137 reg_tarc |= (1 << 21); 4138 else 4139 reg_tarc &= ~(1 << 21); 4140 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 4141 } 4142 } 4143 Adapter->smartspeed = 0; 4144 } else { 4145 if (Adapter->link_state != LINK_STATE_DOWN) { 4146 Adapter->link_speed = 0; 4147 Adapter->link_duplex = 0; 4148 Adapter->link_state = LINK_STATE_DOWN; 4149 link_changed = B_TRUE; 4150 4151 /* 4152 * SmartSpeed workaround for Tabor/TanaX, When the 4153 * driver loses link disable auto master/slave 4154 * resolution. 4155 */ 4156 if (hw->phy.type == e1000_phy_igp) { 4157 (void) e1000_read_phy_reg(hw, 4158 PHY_1000T_CTRL, &phydata); 4159 phydata |= CR_1000T_MS_ENABLE; 4160 (void) e1000_write_phy_reg(hw, 4161 PHY_1000T_CTRL, phydata); 4162 } 4163 } else { 4164 e1000g_smartspeed(Adapter); 4165 } 4166 4167 if (Adapter->e1000g_state & E1000G_STARTED) { 4168 if (Adapter->tx_link_down_timeout < 4169 MAX_TX_LINK_DOWN_TIMEOUT) { 4170 Adapter->tx_link_down_timeout++; 4171 } else if (Adapter->tx_link_down_timeout == 4172 MAX_TX_LINK_DOWN_TIMEOUT) { 4173 e1000g_tx_clean(Adapter); 4174 Adapter->tx_link_down_timeout++; 4175 } 4176 } 4177 } 4178 4179 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4180 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4181 4182 return (link_changed); 4183 } 4184 4185 /* 4186 * e1000g_reset_link - Using the link properties to setup the link 4187 */ 4188 int 4189 e1000g_reset_link(struct e1000g *Adapter) 4190 { 4191 struct e1000_mac_info *mac; 4192 struct e1000_phy_info *phy; 4193 struct e1000_hw *hw; 4194 boolean_t invalid; 4195 4196 mac = &Adapter->shared.mac; 4197 phy = &Adapter->shared.phy; 4198 hw = &Adapter->shared; 4199 invalid = B_FALSE; 4200 4201 if (hw->phy.media_type != e1000_media_type_copper) 4202 goto out; 4203 4204 if (Adapter->param_adv_autoneg == 1) { 4205 mac->autoneg = B_TRUE; 4206 phy->autoneg_advertised = 0; 4207 4208 /* 4209 * 1000hdx is not supported for autonegotiation 4210 */ 4211 if (Adapter->param_adv_1000fdx == 1) 4212 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4213 4214 if (Adapter->param_adv_100fdx == 1) 4215 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4216 4217 if (Adapter->param_adv_100hdx == 1) 4218 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4219 4220 if (Adapter->param_adv_10fdx == 1) 4221 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4222 4223 if (Adapter->param_adv_10hdx == 1) 4224 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4225 4226 if (phy->autoneg_advertised == 0) 4227 invalid = B_TRUE; 4228 } else { 4229 mac->autoneg = B_FALSE; 4230 4231 /* 4232 * For Intel copper cards, 1000fdx and 1000hdx are not 4233 * supported for forced link 4234 */ 4235 if (Adapter->param_adv_100fdx == 1) 4236 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4237 else if (Adapter->param_adv_100hdx == 1) 4238 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4239 else if (Adapter->param_adv_10fdx == 1) 4240 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4241 else if (Adapter->param_adv_10hdx == 1) 4242 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4243 else 4244 invalid = B_TRUE; 4245 4246 } 4247 4248 if (invalid) { 4249 e1000g_log(Adapter, CE_WARN, 4250 "Invalid link settings. Setup link to " 4251 "support autonegotiation with all link capabilities."); 4252 mac->autoneg = B_TRUE; 4253 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4254 } 4255 4256 out: 4257 return (e1000_setup_link(&Adapter->shared)); 4258 } 4259 4260 static void 4261 e1000g_timer_tx_resched(struct e1000g *Adapter) 4262 { 4263 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4264 4265 rw_enter(&Adapter->chip_lock, RW_READER); 4266 4267 if (tx_ring->resched_needed && 4268 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4269 drv_usectohz(1000000)) && 4270 (Adapter->e1000g_state & E1000G_STARTED) && 4271 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4272 tx_ring->resched_needed = B_FALSE; 4273 mac_tx_update(Adapter->mh); 4274 E1000G_STAT(tx_ring->stat_reschedule); 4275 E1000G_STAT(tx_ring->stat_timer_reschedule); 4276 } 4277 4278 rw_exit(&Adapter->chip_lock); 4279 } 4280 4281 static void 4282 e1000g_local_timer(void *ws) 4283 { 4284 struct e1000g *Adapter = (struct e1000g *)ws; 4285 struct e1000_hw *hw; 4286 e1000g_ether_addr_t ether_addr; 4287 boolean_t link_changed; 4288 4289 hw = &Adapter->shared; 4290 4291 if (Adapter->e1000g_state & E1000G_ERROR) { 4292 rw_enter(&Adapter->chip_lock, RW_WRITER); 4293 Adapter->e1000g_state &= ~E1000G_ERROR; 4294 rw_exit(&Adapter->chip_lock); 4295 4296 Adapter->reset_count++; 4297 if (e1000g_global_reset(Adapter)) { 4298 ddi_fm_service_impact(Adapter->dip, 4299 DDI_SERVICE_RESTORED); 4300 e1000g_timer_tx_resched(Adapter); 4301 } else 4302 ddi_fm_service_impact(Adapter->dip, 4303 DDI_SERVICE_LOST); 4304 return; 4305 } 4306 4307 if (e1000g_stall_check(Adapter)) { 4308 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4309 "Tx stall detected. Activate automatic recovery.\n"); 4310 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4311 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4312 Adapter->reset_count++; 4313 if (e1000g_reset_adapter(Adapter)) { 4314 ddi_fm_service_impact(Adapter->dip, 4315 DDI_SERVICE_RESTORED); 4316 e1000g_timer_tx_resched(Adapter); 4317 } 4318 return; 4319 } 4320 4321 link_changed = B_FALSE; 4322 rw_enter(&Adapter->chip_lock, RW_READER); 4323 if (Adapter->link_complete) 4324 link_changed = e1000g_link_check(Adapter); 4325 rw_exit(&Adapter->chip_lock); 4326 4327 if (link_changed) { 4328 if (!Adapter->reset_flag && 4329 (Adapter->e1000g_state & E1000G_STARTED) && 4330 !(Adapter->e1000g_state & E1000G_SUSPENDED)) 4331 mac_link_update(Adapter->mh, Adapter->link_state); 4332 if (Adapter->link_state == LINK_STATE_UP) 4333 Adapter->reset_flag = B_FALSE; 4334 } 4335 /* 4336 * Workaround for esb2. Data stuck in fifo on a link 4337 * down event. Reset the adapter to recover it. 4338 */ 4339 if (Adapter->esb2_workaround) { 4340 Adapter->esb2_workaround = B_FALSE; 4341 (void) e1000g_reset_adapter(Adapter); 4342 return; 4343 } 4344 4345 /* 4346 * With 82571 controllers, any locally administered address will 4347 * be overwritten when there is a reset on the other port. 4348 * Detect this circumstance and correct it. 4349 */ 4350 if ((hw->mac.type == e1000_82571) && 4351 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4352 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4353 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4354 4355 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4356 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4357 4358 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4359 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4360 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4361 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4362 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4363 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4364 e1000_rar_set(hw, hw->mac.addr, 0); 4365 } 4366 } 4367 4368 /* 4369 * Long TTL workaround for 82541/82547 4370 */ 4371 (void) e1000_igp_ttl_workaround_82547(hw); 4372 4373 /* 4374 * Check for Adaptive IFS settings If there are lots of collisions 4375 * change the value in steps... 4376 * These properties should only be set for 10/100 4377 */ 4378 if ((hw->phy.media_type == e1000_media_type_copper) && 4379 ((Adapter->link_speed == SPEED_100) || 4380 (Adapter->link_speed == SPEED_10))) { 4381 e1000_update_adaptive(hw); 4382 } 4383 /* 4384 * Set Timer Interrupts 4385 */ 4386 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4387 4388 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4389 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4390 else 4391 e1000g_timer_tx_resched(Adapter); 4392 4393 restart_watchdog_timer(Adapter); 4394 } 4395 4396 /* 4397 * The function e1000g_link_timer() is called when the timer for link setup 4398 * is expired, which indicates the completion of the link setup. The link 4399 * state will not be updated until the link setup is completed. And the 4400 * link state will not be sent to the upper layer through mac_link_update() 4401 * in this function. It will be updated in the local timer routine or the 4402 * interrupt service routine after the interface is started (plumbed). 4403 */ 4404 static void 4405 e1000g_link_timer(void *arg) 4406 { 4407 struct e1000g *Adapter = (struct e1000g *)arg; 4408 4409 mutex_enter(&Adapter->link_lock); 4410 Adapter->link_complete = B_TRUE; 4411 Adapter->link_tid = 0; 4412 mutex_exit(&Adapter->link_lock); 4413 } 4414 4415 /* 4416 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4417 * 4418 * This function read the forced speed and duplex for 10/100 Mbps speeds 4419 * and also for 1000 Mbps speeds from the e1000g.conf file 4420 */ 4421 static void 4422 e1000g_force_speed_duplex(struct e1000g *Adapter) 4423 { 4424 int forced; 4425 int propval; 4426 struct e1000_mac_info *mac = &Adapter->shared.mac; 4427 struct e1000_phy_info *phy = &Adapter->shared.phy; 4428 4429 /* 4430 * get value out of config file 4431 */ 4432 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4433 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4434 4435 switch (forced) { 4436 case GDIAG_10_HALF: 4437 /* 4438 * Disable Auto Negotiation 4439 */ 4440 mac->autoneg = B_FALSE; 4441 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4442 break; 4443 case GDIAG_10_FULL: 4444 /* 4445 * Disable Auto Negotiation 4446 */ 4447 mac->autoneg = B_FALSE; 4448 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4449 break; 4450 case GDIAG_100_HALF: 4451 /* 4452 * Disable Auto Negotiation 4453 */ 4454 mac->autoneg = B_FALSE; 4455 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4456 break; 4457 case GDIAG_100_FULL: 4458 /* 4459 * Disable Auto Negotiation 4460 */ 4461 mac->autoneg = B_FALSE; 4462 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4463 break; 4464 case GDIAG_1000_FULL: 4465 /* 4466 * The gigabit spec requires autonegotiation. Therefore, 4467 * when the user wants to force the speed to 1000Mbps, we 4468 * enable AutoNeg, but only allow the harware to advertise 4469 * 1000Mbps. This is different from 10/100 operation, where 4470 * we are allowed to link without any negotiation. 4471 */ 4472 mac->autoneg = B_TRUE; 4473 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4474 break; 4475 default: /* obey the setting of AutoNegAdvertised */ 4476 mac->autoneg = B_TRUE; 4477 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4478 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4479 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4480 phy->autoneg_advertised = (uint16_t)propval; 4481 break; 4482 } /* switch */ 4483 } 4484 4485 /* 4486 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4487 * 4488 * This function reads MaxFrameSize from e1000g.conf 4489 */ 4490 static void 4491 e1000g_get_max_frame_size(struct e1000g *Adapter) 4492 { 4493 int max_frame; 4494 4495 /* 4496 * get value out of config file 4497 */ 4498 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4499 &max_frame); 4500 4501 switch (max_frame) { 4502 case 0: 4503 Adapter->default_mtu = ETHERMTU; 4504 break; 4505 /* 4506 * To avoid excessive memory allocation for rx buffers, 4507 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4508 */ 4509 case 1: 4510 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4511 sizeof (struct ether_vlan_header) - ETHERFCSL - 4512 E1000G_IPALIGNPRESERVEROOM; 4513 break; 4514 case 2: 4515 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4516 sizeof (struct ether_vlan_header) - ETHERFCSL - 4517 E1000G_IPALIGNPRESERVEROOM; 4518 break; 4519 case 3: 4520 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4521 sizeof (struct ether_vlan_header) - ETHERFCSL - 4522 E1000G_IPALIGNPRESERVEROOM; 4523 break; 4524 default: 4525 Adapter->default_mtu = ETHERMTU; 4526 break; 4527 } /* switch */ 4528 4529 /* 4530 * If the user configed MTU is larger than the deivce's maximum MTU, 4531 * the MTU is set to the deivce's maximum value. 4532 */ 4533 if (Adapter->default_mtu > Adapter->max_mtu) 4534 Adapter->default_mtu = Adapter->max_mtu; 4535 4536 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4537 } 4538 4539 /* 4540 * e1000g_pch_limits - Apply limits of the PCH silicon type 4541 * 4542 * At any frame size larger than the ethernet default, 4543 * prevent linking at 10/100 speeds. 4544 */ 4545 static void 4546 e1000g_pch_limits(struct e1000g *Adapter) 4547 { 4548 struct e1000_hw *hw = &Adapter->shared; 4549 4550 /* only applies to PCH silicon type */ 4551 if (hw->mac.type != e1000_pchlan) 4552 return; 4553 4554 /* only applies to frames larger than ethernet default */ 4555 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4556 hw->mac.autoneg = B_TRUE; 4557 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4558 4559 Adapter->param_adv_autoneg = 1; 4560 Adapter->param_adv_1000fdx = 1; 4561 4562 Adapter->param_adv_100fdx = 0; 4563 Adapter->param_adv_100hdx = 0; 4564 Adapter->param_adv_10fdx = 0; 4565 Adapter->param_adv_10hdx = 0; 4566 4567 e1000g_param_sync(Adapter); 4568 } 4569 } 4570 4571 /* 4572 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4573 */ 4574 static uint32_t 4575 e1000g_mtu2maxframe(uint32_t mtu) 4576 { 4577 uint32_t maxframe; 4578 4579 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4580 4581 return (maxframe); 4582 } 4583 4584 static void 4585 arm_watchdog_timer(struct e1000g *Adapter) 4586 { 4587 Adapter->watchdog_tid = 4588 timeout(e1000g_local_timer, 4589 (void *)Adapter, 1 * drv_usectohz(1000000)); 4590 } 4591 #pragma inline(arm_watchdog_timer) 4592 4593 static void 4594 enable_watchdog_timer(struct e1000g *Adapter) 4595 { 4596 mutex_enter(&Adapter->watchdog_lock); 4597 4598 if (!Adapter->watchdog_timer_enabled) { 4599 Adapter->watchdog_timer_enabled = B_TRUE; 4600 Adapter->watchdog_timer_started = B_TRUE; 4601 arm_watchdog_timer(Adapter); 4602 } 4603 4604 mutex_exit(&Adapter->watchdog_lock); 4605 } 4606 4607 static void 4608 disable_watchdog_timer(struct e1000g *Adapter) 4609 { 4610 timeout_id_t tid; 4611 4612 mutex_enter(&Adapter->watchdog_lock); 4613 4614 Adapter->watchdog_timer_enabled = B_FALSE; 4615 Adapter->watchdog_timer_started = B_FALSE; 4616 tid = Adapter->watchdog_tid; 4617 Adapter->watchdog_tid = 0; 4618 4619 mutex_exit(&Adapter->watchdog_lock); 4620 4621 if (tid != 0) 4622 (void) untimeout(tid); 4623 } 4624 4625 static void 4626 start_watchdog_timer(struct e1000g *Adapter) 4627 { 4628 mutex_enter(&Adapter->watchdog_lock); 4629 4630 if (Adapter->watchdog_timer_enabled) { 4631 if (!Adapter->watchdog_timer_started) { 4632 Adapter->watchdog_timer_started = B_TRUE; 4633 arm_watchdog_timer(Adapter); 4634 } 4635 } 4636 4637 mutex_exit(&Adapter->watchdog_lock); 4638 } 4639 4640 static void 4641 restart_watchdog_timer(struct e1000g *Adapter) 4642 { 4643 mutex_enter(&Adapter->watchdog_lock); 4644 4645 if (Adapter->watchdog_timer_started) 4646 arm_watchdog_timer(Adapter); 4647 4648 mutex_exit(&Adapter->watchdog_lock); 4649 } 4650 4651 static void 4652 stop_watchdog_timer(struct e1000g *Adapter) 4653 { 4654 timeout_id_t tid; 4655 4656 mutex_enter(&Adapter->watchdog_lock); 4657 4658 Adapter->watchdog_timer_started = B_FALSE; 4659 tid = Adapter->watchdog_tid; 4660 Adapter->watchdog_tid = 0; 4661 4662 mutex_exit(&Adapter->watchdog_lock); 4663 4664 if (tid != 0) 4665 (void) untimeout(tid); 4666 } 4667 4668 static void 4669 stop_link_timer(struct e1000g *Adapter) 4670 { 4671 timeout_id_t tid; 4672 4673 /* Disable the link timer */ 4674 mutex_enter(&Adapter->link_lock); 4675 4676 tid = Adapter->link_tid; 4677 Adapter->link_tid = 0; 4678 4679 mutex_exit(&Adapter->link_lock); 4680 4681 if (tid != 0) 4682 (void) untimeout(tid); 4683 } 4684 4685 static void 4686 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4687 { 4688 timeout_id_t tid; 4689 4690 /* Disable the tx timer for 82547 chipset */ 4691 mutex_enter(&tx_ring->tx_lock); 4692 4693 tx_ring->timer_enable_82547 = B_FALSE; 4694 tid = tx_ring->timer_id_82547; 4695 tx_ring->timer_id_82547 = 0; 4696 4697 mutex_exit(&tx_ring->tx_lock); 4698 4699 if (tid != 0) 4700 (void) untimeout(tid); 4701 } 4702 4703 void 4704 e1000g_clear_interrupt(struct e1000g *Adapter) 4705 { 4706 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4707 0xffffffff & ~E1000_IMS_RXSEQ); 4708 } 4709 4710 void 4711 e1000g_mask_interrupt(struct e1000g *Adapter) 4712 { 4713 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4714 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4715 4716 if (Adapter->tx_intr_enable) 4717 e1000g_mask_tx_interrupt(Adapter); 4718 } 4719 4720 /* 4721 * This routine is called by e1000g_quiesce(), therefore must not block. 4722 */ 4723 void 4724 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4725 { 4726 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4727 } 4728 4729 void 4730 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4731 { 4732 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4733 } 4734 4735 void 4736 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4737 { 4738 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4739 } 4740 4741 static void 4742 e1000g_smartspeed(struct e1000g *Adapter) 4743 { 4744 struct e1000_hw *hw = &Adapter->shared; 4745 uint16_t phy_status; 4746 uint16_t phy_ctrl; 4747 4748 /* 4749 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4750 * advertising 1000Full, we don't even use the workaround 4751 */ 4752 if ((hw->phy.type != e1000_phy_igp) || 4753 !hw->mac.autoneg || 4754 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4755 return; 4756 4757 /* 4758 * True if this is the first call of this function or after every 4759 * 30 seconds of not having link 4760 */ 4761 if (Adapter->smartspeed == 0) { 4762 /* 4763 * If Master/Slave config fault is asserted twice, we 4764 * assume back-to-back 4765 */ 4766 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4767 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4768 return; 4769 4770 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4771 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4772 return; 4773 /* 4774 * We're assuming back-2-back because our status register 4775 * insists! there's a fault in the master/slave 4776 * relationship that was "negotiated" 4777 */ 4778 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4779 /* 4780 * Is the phy configured for manual configuration of 4781 * master/slave? 4782 */ 4783 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4784 /* 4785 * Yes. Then disable manual configuration (enable 4786 * auto configuration) of master/slave 4787 */ 4788 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4789 (void) e1000_write_phy_reg(hw, 4790 PHY_1000T_CTRL, phy_ctrl); 4791 /* 4792 * Effectively starting the clock 4793 */ 4794 Adapter->smartspeed++; 4795 /* 4796 * Restart autonegotiation 4797 */ 4798 if (!e1000_phy_setup_autoneg(hw) && 4799 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4800 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4801 MII_CR_RESTART_AUTO_NEG); 4802 (void) e1000_write_phy_reg(hw, 4803 PHY_CONTROL, phy_ctrl); 4804 } 4805 } 4806 return; 4807 /* 4808 * Has 6 seconds transpired still without link? Remember, 4809 * you should reset the smartspeed counter once you obtain 4810 * link 4811 */ 4812 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4813 /* 4814 * Yes. Remember, we did at the start determine that 4815 * there's a master/slave configuration fault, so we're 4816 * still assuming there's someone on the other end, but we 4817 * just haven't yet been able to talk to it. We then 4818 * re-enable auto configuration of master/slave to see if 4819 * we're running 2/3 pair cables. 4820 */ 4821 /* 4822 * If still no link, perhaps using 2/3 pair cable 4823 */ 4824 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4825 phy_ctrl |= CR_1000T_MS_ENABLE; 4826 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4827 /* 4828 * Restart autoneg with phy enabled for manual 4829 * configuration of master/slave 4830 */ 4831 if (!e1000_phy_setup_autoneg(hw) && 4832 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4833 phy_ctrl |= 4834 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4835 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4836 } 4837 /* 4838 * Hopefully, there are no more faults and we've obtained 4839 * link as a result. 4840 */ 4841 } 4842 /* 4843 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4844 * seconds) 4845 */ 4846 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4847 Adapter->smartspeed = 0; 4848 } 4849 4850 static boolean_t 4851 is_valid_mac_addr(uint8_t *mac_addr) 4852 { 4853 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4854 const uint8_t addr_test2[6] = 4855 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4856 4857 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4858 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4859 return (B_FALSE); 4860 4861 return (B_TRUE); 4862 } 4863 4864 /* 4865 * e1000g_stall_check - check for tx stall 4866 * 4867 * This function checks if the adapter is stalled (in transmit). 4868 * 4869 * It is called each time the watchdog timeout is invoked. 4870 * If the transmit descriptor reclaim continuously fails, 4871 * the watchdog value will increment by 1. If the watchdog 4872 * value exceeds the threshold, the adapter is assumed to 4873 * have stalled and need to be reset. 4874 */ 4875 static boolean_t 4876 e1000g_stall_check(struct e1000g *Adapter) 4877 { 4878 e1000g_tx_ring_t *tx_ring; 4879 4880 tx_ring = Adapter->tx_ring; 4881 4882 if (Adapter->link_state != LINK_STATE_UP) 4883 return (B_FALSE); 4884 4885 (void) e1000g_recycle(tx_ring); 4886 4887 if (Adapter->stall_flag) 4888 return (B_TRUE); 4889 4890 return (B_FALSE); 4891 } 4892 4893 #ifdef E1000G_DEBUG 4894 static enum ioc_reply 4895 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4896 { 4897 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4898 e1000g_peekpoke_t *ppd; 4899 uint64_t mem_va; 4900 uint64_t maxoff; 4901 boolean_t peek; 4902 4903 switch (iocp->ioc_cmd) { 4904 4905 case E1000G_IOC_REG_PEEK: 4906 peek = B_TRUE; 4907 break; 4908 4909 case E1000G_IOC_REG_POKE: 4910 peek = B_FALSE; 4911 break; 4912 4913 deault: 4914 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4915 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4916 iocp->ioc_cmd); 4917 return (IOC_INVAL); 4918 } 4919 4920 /* 4921 * Validate format of ioctl 4922 */ 4923 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4924 return (IOC_INVAL); 4925 if (mp->b_cont == NULL) 4926 return (IOC_INVAL); 4927 4928 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4929 4930 /* 4931 * Validate request parameters 4932 */ 4933 switch (ppd->pp_acc_space) { 4934 4935 default: 4936 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4937 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4938 ppd->pp_acc_space); 4939 return (IOC_INVAL); 4940 4941 case E1000G_PP_SPACE_REG: 4942 /* 4943 * Memory-mapped I/O space 4944 */ 4945 ASSERT(ppd->pp_acc_size == 4); 4946 if (ppd->pp_acc_size != 4) 4947 return (IOC_INVAL); 4948 4949 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4950 return (IOC_INVAL); 4951 4952 mem_va = 0; 4953 maxoff = 0x10000; 4954 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4955 break; 4956 4957 case E1000G_PP_SPACE_E1000G: 4958 /* 4959 * E1000g data structure! 4960 */ 4961 mem_va = (uintptr_t)e1000gp; 4962 maxoff = sizeof (struct e1000g); 4963 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4964 break; 4965 4966 } 4967 4968 if (ppd->pp_acc_offset >= maxoff) 4969 return (IOC_INVAL); 4970 4971 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4972 return (IOC_INVAL); 4973 4974 /* 4975 * All OK - go! 4976 */ 4977 ppd->pp_acc_offset += mem_va; 4978 (*ppfn)(e1000gp, ppd); 4979 return (peek ? IOC_REPLY : IOC_ACK); 4980 } 4981 4982 static void 4983 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4984 { 4985 ddi_acc_handle_t handle; 4986 uint32_t *regaddr; 4987 4988 handle = e1000gp->osdep.reg_handle; 4989 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4990 (uintptr_t)ppd->pp_acc_offset); 4991 4992 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4993 } 4994 4995 static void 4996 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4997 { 4998 ddi_acc_handle_t handle; 4999 uint32_t *regaddr; 5000 uint32_t value; 5001 5002 handle = e1000gp->osdep.reg_handle; 5003 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5004 (uintptr_t)ppd->pp_acc_offset); 5005 value = (uint32_t)ppd->pp_acc_data; 5006 5007 ddi_put32(handle, regaddr, value); 5008 } 5009 5010 static void 5011 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5012 { 5013 uint64_t value; 5014 void *vaddr; 5015 5016 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5017 5018 switch (ppd->pp_acc_size) { 5019 case 1: 5020 value = *(uint8_t *)vaddr; 5021 break; 5022 5023 case 2: 5024 value = *(uint16_t *)vaddr; 5025 break; 5026 5027 case 4: 5028 value = *(uint32_t *)vaddr; 5029 break; 5030 5031 case 8: 5032 value = *(uint64_t *)vaddr; 5033 break; 5034 } 5035 5036 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5037 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 5038 (void *)e1000gp, (void *)ppd, value, vaddr); 5039 5040 ppd->pp_acc_data = value; 5041 } 5042 5043 static void 5044 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5045 { 5046 uint64_t value; 5047 void *vaddr; 5048 5049 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5050 value = ppd->pp_acc_data; 5051 5052 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5053 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 5054 (void *)e1000gp, (void *)ppd, value, vaddr); 5055 5056 switch (ppd->pp_acc_size) { 5057 case 1: 5058 *(uint8_t *)vaddr = (uint8_t)value; 5059 break; 5060 5061 case 2: 5062 *(uint16_t *)vaddr = (uint16_t)value; 5063 break; 5064 5065 case 4: 5066 *(uint32_t *)vaddr = (uint32_t)value; 5067 break; 5068 5069 case 8: 5070 *(uint64_t *)vaddr = (uint64_t)value; 5071 break; 5072 } 5073 } 5074 #endif 5075 5076 /* 5077 * Loopback Support 5078 */ 5079 static lb_property_t lb_normal = 5080 { normal, "normal", E1000G_LB_NONE }; 5081 static lb_property_t lb_external1000 = 5082 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 5083 static lb_property_t lb_external100 = 5084 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 5085 static lb_property_t lb_external10 = 5086 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 5087 static lb_property_t lb_phy = 5088 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 5089 5090 static enum ioc_reply 5091 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 5092 { 5093 lb_info_sz_t *lbsp; 5094 lb_property_t *lbpp; 5095 struct e1000_hw *hw; 5096 uint32_t *lbmp; 5097 uint32_t size; 5098 uint32_t value; 5099 5100 hw = &Adapter->shared; 5101 5102 if (mp->b_cont == NULL) 5103 return (IOC_INVAL); 5104 5105 if (!e1000g_check_loopback_support(hw)) { 5106 e1000g_log(NULL, CE_WARN, 5107 "Loopback is not supported on e1000g%d", Adapter->instance); 5108 return (IOC_INVAL); 5109 } 5110 5111 switch (iocp->ioc_cmd) { 5112 default: 5113 return (IOC_INVAL); 5114 5115 case LB_GET_INFO_SIZE: 5116 size = sizeof (lb_info_sz_t); 5117 if (iocp->ioc_count != size) 5118 return (IOC_INVAL); 5119 5120 rw_enter(&Adapter->chip_lock, RW_WRITER); 5121 e1000g_get_phy_state(Adapter); 5122 5123 /* 5124 * Workaround for hardware faults. In order to get a stable 5125 * state of phy, we will wait for a specific interval and 5126 * try again. The time delay is an experiential value based 5127 * on our testing. 5128 */ 5129 msec_delay(100); 5130 e1000g_get_phy_state(Adapter); 5131 rw_exit(&Adapter->chip_lock); 5132 5133 value = sizeof (lb_normal); 5134 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5135 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5136 (hw->phy.media_type == e1000_media_type_fiber) || 5137 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5138 value += sizeof (lb_phy); 5139 switch (hw->mac.type) { 5140 case e1000_82571: 5141 case e1000_82572: 5142 case e1000_80003es2lan: 5143 value += sizeof (lb_external1000); 5144 break; 5145 } 5146 } 5147 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5148 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5149 value += sizeof (lb_external100); 5150 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5151 value += sizeof (lb_external10); 5152 5153 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 5154 *lbsp = value; 5155 break; 5156 5157 case LB_GET_INFO: 5158 value = sizeof (lb_normal); 5159 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5160 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5161 (hw->phy.media_type == e1000_media_type_fiber) || 5162 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5163 value += sizeof (lb_phy); 5164 switch (hw->mac.type) { 5165 case e1000_82571: 5166 case e1000_82572: 5167 case e1000_80003es2lan: 5168 value += sizeof (lb_external1000); 5169 break; 5170 } 5171 } 5172 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5173 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5174 value += sizeof (lb_external100); 5175 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5176 value += sizeof (lb_external10); 5177 5178 size = value; 5179 if (iocp->ioc_count != size) 5180 return (IOC_INVAL); 5181 5182 value = 0; 5183 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5184 lbpp[value++] = lb_normal; 5185 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5186 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5187 (hw->phy.media_type == e1000_media_type_fiber) || 5188 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5189 lbpp[value++] = lb_phy; 5190 switch (hw->mac.type) { 5191 case e1000_82571: 5192 case e1000_82572: 5193 case e1000_80003es2lan: 5194 lbpp[value++] = lb_external1000; 5195 break; 5196 } 5197 } 5198 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5199 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5200 lbpp[value++] = lb_external100; 5201 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5202 lbpp[value++] = lb_external10; 5203 break; 5204 5205 case LB_GET_MODE: 5206 size = sizeof (uint32_t); 5207 if (iocp->ioc_count != size) 5208 return (IOC_INVAL); 5209 5210 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5211 *lbmp = Adapter->loopback_mode; 5212 break; 5213 5214 case LB_SET_MODE: 5215 size = 0; 5216 if (iocp->ioc_count != sizeof (uint32_t)) 5217 return (IOC_INVAL); 5218 5219 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5220 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5221 return (IOC_INVAL); 5222 break; 5223 } 5224 5225 iocp->ioc_count = size; 5226 iocp->ioc_error = 0; 5227 5228 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5229 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5230 return (IOC_INVAL); 5231 } 5232 5233 return (IOC_REPLY); 5234 } 5235 5236 static boolean_t 5237 e1000g_check_loopback_support(struct e1000_hw *hw) 5238 { 5239 switch (hw->mac.type) { 5240 case e1000_82540: 5241 case e1000_82545: 5242 case e1000_82545_rev_3: 5243 case e1000_82546: 5244 case e1000_82546_rev_3: 5245 case e1000_82541: 5246 case e1000_82541_rev_2: 5247 case e1000_82547: 5248 case e1000_82547_rev_2: 5249 case e1000_82571: 5250 case e1000_82572: 5251 case e1000_82573: 5252 case e1000_82574: 5253 case e1000_80003es2lan: 5254 case e1000_ich9lan: 5255 case e1000_ich10lan: 5256 return (B_TRUE); 5257 } 5258 return (B_FALSE); 5259 } 5260 5261 static boolean_t 5262 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5263 { 5264 struct e1000_hw *hw; 5265 int i, times; 5266 boolean_t link_up; 5267 5268 if (mode == Adapter->loopback_mode) 5269 return (B_TRUE); 5270 5271 hw = &Adapter->shared; 5272 times = 0; 5273 5274 Adapter->loopback_mode = mode; 5275 5276 if (mode == E1000G_LB_NONE) { 5277 /* Reset the chip */ 5278 hw->phy.autoneg_wait_to_complete = B_TRUE; 5279 (void) e1000g_reset_adapter(Adapter); 5280 hw->phy.autoneg_wait_to_complete = B_FALSE; 5281 return (B_TRUE); 5282 } 5283 5284 again: 5285 5286 rw_enter(&Adapter->chip_lock, RW_WRITER); 5287 5288 switch (mode) { 5289 default: 5290 rw_exit(&Adapter->chip_lock); 5291 return (B_FALSE); 5292 5293 case E1000G_LB_EXTERNAL_1000: 5294 e1000g_set_external_loopback_1000(Adapter); 5295 break; 5296 5297 case E1000G_LB_EXTERNAL_100: 5298 e1000g_set_external_loopback_100(Adapter); 5299 break; 5300 5301 case E1000G_LB_EXTERNAL_10: 5302 e1000g_set_external_loopback_10(Adapter); 5303 break; 5304 5305 case E1000G_LB_INTERNAL_PHY: 5306 e1000g_set_internal_loopback(Adapter); 5307 break; 5308 } 5309 5310 times++; 5311 5312 rw_exit(&Adapter->chip_lock); 5313 5314 /* Wait for link up */ 5315 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5316 msec_delay(100); 5317 5318 rw_enter(&Adapter->chip_lock, RW_WRITER); 5319 5320 link_up = e1000g_link_up(Adapter); 5321 5322 rw_exit(&Adapter->chip_lock); 5323 5324 if (!link_up) { 5325 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5326 "Failed to get the link up"); 5327 if (times < 2) { 5328 /* Reset the link */ 5329 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5330 "Reset the link ..."); 5331 (void) e1000g_reset_adapter(Adapter); 5332 goto again; 5333 } 5334 5335 /* 5336 * Reset driver to loopback none when set loopback failed 5337 * for the second time. 5338 */ 5339 Adapter->loopback_mode = E1000G_LB_NONE; 5340 5341 /* Reset the chip */ 5342 hw->phy.autoneg_wait_to_complete = B_TRUE; 5343 (void) e1000g_reset_adapter(Adapter); 5344 hw->phy.autoneg_wait_to_complete = B_FALSE; 5345 5346 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5347 "Set loopback mode failed, reset to loopback none"); 5348 5349 return (B_FALSE); 5350 } 5351 5352 return (B_TRUE); 5353 } 5354 5355 /* 5356 * The following loopback settings are from Intel's technical 5357 * document - "How To Loopback". All the register settings and 5358 * time delay values are directly inherited from the document 5359 * without more explanations available. 5360 */ 5361 static void 5362 e1000g_set_internal_loopback(struct e1000g *Adapter) 5363 { 5364 struct e1000_hw *hw; 5365 uint32_t ctrl; 5366 uint32_t status; 5367 uint16_t phy_ctrl; 5368 uint16_t phy_reg; 5369 uint32_t txcw; 5370 5371 hw = &Adapter->shared; 5372 5373 /* Disable Smart Power Down */ 5374 phy_spd_state(hw, B_FALSE); 5375 5376 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5377 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5378 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5379 5380 switch (hw->mac.type) { 5381 case e1000_82540: 5382 case e1000_82545: 5383 case e1000_82545_rev_3: 5384 case e1000_82546: 5385 case e1000_82546_rev_3: 5386 case e1000_82573: 5387 /* Auto-MDI/MDIX off */ 5388 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5389 /* Reset PHY to update Auto-MDI/MDIX */ 5390 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5391 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5392 /* Reset PHY to auto-neg off and force 1000 */ 5393 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5394 phy_ctrl | MII_CR_RESET); 5395 /* 5396 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5397 * See comments above e1000g_set_internal_loopback() for the 5398 * background. 5399 */ 5400 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5401 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5402 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5403 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5404 break; 5405 case e1000_80003es2lan: 5406 /* Force Link Up */ 5407 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5408 0x1CC); 5409 /* Sets PCS loopback at 1Gbs */ 5410 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5411 0x1046); 5412 break; 5413 } 5414 5415 /* 5416 * The following registers should be set for e1000_phy_bm phy type. 5417 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5418 * For others, we do not need to set these registers. 5419 */ 5420 if (hw->phy.type == e1000_phy_bm) { 5421 /* Set Default MAC Interface speed to 1GB */ 5422 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5423 phy_reg &= ~0x0007; 5424 phy_reg |= 0x006; 5425 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5426 /* Assert SW reset for above settings to take effect */ 5427 (void) e1000_phy_commit(hw); 5428 msec_delay(1); 5429 /* Force Full Duplex */ 5430 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5431 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5432 phy_reg | 0x000C); 5433 /* Set Link Up (in force link) */ 5434 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5435 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5436 phy_reg | 0x0040); 5437 /* Force Link */ 5438 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5439 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5440 phy_reg | 0x0040); 5441 /* Set Early Link Enable */ 5442 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5443 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5444 phy_reg | 0x0400); 5445 } 5446 5447 /* Set loopback */ 5448 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5449 5450 msec_delay(250); 5451 5452 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5453 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5454 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5455 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5456 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5457 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5458 E1000_CTRL_FD); /* Force Duplex to FULL */ 5459 5460 switch (hw->mac.type) { 5461 case e1000_82540: 5462 case e1000_82545: 5463 case e1000_82545_rev_3: 5464 case e1000_82546: 5465 case e1000_82546_rev_3: 5466 /* 5467 * For some serdes we'll need to commit the writes now 5468 * so that the status is updated on link 5469 */ 5470 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5471 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5472 msec_delay(100); 5473 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5474 } 5475 5476 if (hw->phy.media_type == e1000_media_type_copper) { 5477 /* Invert Loss of Signal */ 5478 ctrl |= E1000_CTRL_ILOS; 5479 } else { 5480 /* Set ILOS on fiber nic if half duplex is detected */ 5481 status = E1000_READ_REG(hw, E1000_STATUS); 5482 if ((status & E1000_STATUS_FD) == 0) 5483 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5484 } 5485 break; 5486 5487 case e1000_82571: 5488 case e1000_82572: 5489 /* 5490 * The fiber/SerDes versions of this adapter do not contain an 5491 * accessible PHY. Therefore, loopback beyond MAC must be done 5492 * using SerDes analog loopback. 5493 */ 5494 if (hw->phy.media_type != e1000_media_type_copper) { 5495 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5496 txcw = E1000_READ_REG(hw, E1000_TXCW); 5497 txcw &= ~((uint32_t)1 << 31); 5498 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5499 5500 /* 5501 * Write 0x410 to Serdes Control register 5502 * to enable Serdes analog loopback 5503 */ 5504 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5505 msec_delay(10); 5506 } 5507 5508 status = E1000_READ_REG(hw, E1000_STATUS); 5509 /* Set ILOS on fiber nic if half duplex is detected */ 5510 if ((hw->phy.media_type == e1000_media_type_fiber) && 5511 ((status & E1000_STATUS_FD) == 0 || 5512 (status & E1000_STATUS_LU) == 0)) 5513 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5514 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5515 ctrl |= E1000_CTRL_SLU; 5516 break; 5517 5518 case e1000_82573: 5519 ctrl |= E1000_CTRL_ILOS; 5520 break; 5521 case e1000_ich9lan: 5522 case e1000_ich10lan: 5523 ctrl |= E1000_CTRL_SLU; 5524 break; 5525 } 5526 if (hw->phy.type == e1000_phy_bm) 5527 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5528 5529 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5530 } 5531 5532 static void 5533 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5534 { 5535 struct e1000_hw *hw; 5536 uint32_t rctl; 5537 uint32_t ctrl_ext; 5538 uint32_t ctrl; 5539 uint32_t status; 5540 uint32_t txcw; 5541 uint16_t phydata; 5542 5543 hw = &Adapter->shared; 5544 5545 /* Disable Smart Power Down */ 5546 phy_spd_state(hw, B_FALSE); 5547 5548 switch (hw->mac.type) { 5549 case e1000_82571: 5550 case e1000_82572: 5551 switch (hw->phy.media_type) { 5552 case e1000_media_type_copper: 5553 /* Force link up (Must be done before the PHY writes) */ 5554 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5555 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5556 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5557 5558 rctl = E1000_READ_REG(hw, E1000_RCTL); 5559 rctl |= (E1000_RCTL_EN | 5560 E1000_RCTL_SBP | 5561 E1000_RCTL_UPE | 5562 E1000_RCTL_MPE | 5563 E1000_RCTL_LPE | 5564 E1000_RCTL_BAM); /* 0x803E */ 5565 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5566 5567 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5568 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5569 E1000_CTRL_EXT_SDP6_DATA | 5570 E1000_CTRL_EXT_SDP3_DATA | 5571 E1000_CTRL_EXT_SDP4_DIR | 5572 E1000_CTRL_EXT_SDP6_DIR | 5573 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5574 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5575 5576 /* 5577 * This sequence tunes the PHY's SDP and no customer 5578 * settable values. For background, see comments above 5579 * e1000g_set_internal_loopback(). 5580 */ 5581 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5582 msec_delay(10); 5583 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5584 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5585 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5586 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5587 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5588 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5589 5590 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5591 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5592 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5593 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5594 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5595 5596 msec_delay(50); 5597 break; 5598 case e1000_media_type_fiber: 5599 case e1000_media_type_internal_serdes: 5600 status = E1000_READ_REG(hw, E1000_STATUS); 5601 if (((status & E1000_STATUS_LU) == 0) || 5602 (hw->phy.media_type == 5603 e1000_media_type_internal_serdes)) { 5604 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5605 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5606 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5607 } 5608 5609 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5610 txcw = E1000_READ_REG(hw, E1000_TXCW); 5611 txcw &= ~((uint32_t)1 << 31); 5612 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5613 5614 /* 5615 * Write 0x410 to Serdes Control register 5616 * to enable Serdes analog loopback 5617 */ 5618 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5619 msec_delay(10); 5620 break; 5621 default: 5622 break; 5623 } 5624 break; 5625 case e1000_82574: 5626 case e1000_80003es2lan: 5627 case e1000_ich9lan: 5628 case e1000_ich10lan: 5629 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5630 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5631 phydata | (1 << 5)); 5632 Adapter->param_adv_autoneg = 1; 5633 Adapter->param_adv_1000fdx = 1; 5634 (void) e1000g_reset_link(Adapter); 5635 break; 5636 } 5637 } 5638 5639 static void 5640 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5641 { 5642 struct e1000_hw *hw; 5643 uint32_t ctrl; 5644 uint16_t phy_ctrl; 5645 5646 hw = &Adapter->shared; 5647 5648 /* Disable Smart Power Down */ 5649 phy_spd_state(hw, B_FALSE); 5650 5651 phy_ctrl = (MII_CR_FULL_DUPLEX | 5652 MII_CR_SPEED_100); 5653 5654 /* Force 100/FD, reset PHY */ 5655 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5656 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5657 msec_delay(10); 5658 5659 /* Force 100/FD */ 5660 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5661 phy_ctrl); /* 0x2100 */ 5662 msec_delay(10); 5663 5664 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5665 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5666 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5667 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5668 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5669 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5670 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5671 E1000_CTRL_FD); /* Force Duplex to FULL */ 5672 5673 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5674 } 5675 5676 static void 5677 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5678 { 5679 struct e1000_hw *hw; 5680 uint32_t ctrl; 5681 uint16_t phy_ctrl; 5682 5683 hw = &Adapter->shared; 5684 5685 /* Disable Smart Power Down */ 5686 phy_spd_state(hw, B_FALSE); 5687 5688 phy_ctrl = (MII_CR_FULL_DUPLEX | 5689 MII_CR_SPEED_10); 5690 5691 /* Force 10/FD, reset PHY */ 5692 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5693 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5694 msec_delay(10); 5695 5696 /* Force 10/FD */ 5697 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5698 phy_ctrl); /* 0x0100 */ 5699 msec_delay(10); 5700 5701 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5702 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5703 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5704 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5705 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5706 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5707 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5708 E1000_CTRL_FD); /* Force Duplex to FULL */ 5709 5710 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5711 } 5712 5713 #ifdef __sparc 5714 static boolean_t 5715 e1000g_find_mac_address(struct e1000g *Adapter) 5716 { 5717 struct e1000_hw *hw = &Adapter->shared; 5718 uchar_t *bytes; 5719 struct ether_addr sysaddr; 5720 uint_t nelts; 5721 int err; 5722 boolean_t found = B_FALSE; 5723 5724 /* 5725 * The "vendor's factory-set address" may already have 5726 * been extracted from the chip, but if the property 5727 * "local-mac-address" is set we use that instead. 5728 * 5729 * We check whether it looks like an array of 6 5730 * bytes (which it should, if OBP set it). If we can't 5731 * make sense of it this way, we'll ignore it. 5732 */ 5733 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5734 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5735 if (err == DDI_PROP_SUCCESS) { 5736 if (nelts == ETHERADDRL) { 5737 while (nelts--) 5738 hw->mac.addr[nelts] = bytes[nelts]; 5739 found = B_TRUE; 5740 } 5741 ddi_prop_free(bytes); 5742 } 5743 5744 /* 5745 * Look up the OBP property "local-mac-address?". If the user has set 5746 * 'local-mac-address? = false', use "the system address" instead. 5747 */ 5748 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5749 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5750 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5751 if (localetheraddr(NULL, &sysaddr) != 0) { 5752 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5753 found = B_TRUE; 5754 } 5755 } 5756 ddi_prop_free(bytes); 5757 } 5758 5759 /* 5760 * Finally(!), if there's a valid "mac-address" property (created 5761 * if we netbooted from this interface), we must use this instead 5762 * of any of the above to ensure that the NFS/install server doesn't 5763 * get confused by the address changing as Solaris takes over! 5764 */ 5765 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5766 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5767 if (err == DDI_PROP_SUCCESS) { 5768 if (nelts == ETHERADDRL) { 5769 while (nelts--) 5770 hw->mac.addr[nelts] = bytes[nelts]; 5771 found = B_TRUE; 5772 } 5773 ddi_prop_free(bytes); 5774 } 5775 5776 if (found) { 5777 bcopy(hw->mac.addr, hw->mac.perm_addr, 5778 ETHERADDRL); 5779 } 5780 5781 return (found); 5782 } 5783 #endif 5784 5785 static int 5786 e1000g_add_intrs(struct e1000g *Adapter) 5787 { 5788 dev_info_t *devinfo; 5789 int intr_types; 5790 int rc; 5791 5792 devinfo = Adapter->dip; 5793 5794 /* Get supported interrupt types */ 5795 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5796 5797 if (rc != DDI_SUCCESS) { 5798 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5799 "Get supported interrupt types failed: %d\n", rc); 5800 return (DDI_FAILURE); 5801 } 5802 5803 /* 5804 * Based on Intel Technical Advisory document (TA-160), there are some 5805 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5806 * that it supports MSI, but in fact has problems. 5807 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5808 * PCI/PCI-X NICs. 5809 */ 5810 if (Adapter->shared.mac.type < e1000_82571) 5811 Adapter->msi_enable = B_FALSE; 5812 5813 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5814 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5815 5816 if (rc != DDI_SUCCESS) { 5817 /* EMPTY */ 5818 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5819 "Add MSI failed, trying Legacy interrupts\n"); 5820 } else { 5821 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5822 } 5823 } 5824 5825 if ((Adapter->intr_type == 0) && 5826 (intr_types & DDI_INTR_TYPE_FIXED)) { 5827 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5828 5829 if (rc != DDI_SUCCESS) { 5830 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5831 "Add Legacy interrupts failed\n"); 5832 return (DDI_FAILURE); 5833 } 5834 5835 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5836 } 5837 5838 if (Adapter->intr_type == 0) { 5839 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5840 "No interrupts registered\n"); 5841 return (DDI_FAILURE); 5842 } 5843 5844 return (DDI_SUCCESS); 5845 } 5846 5847 /* 5848 * e1000g_intr_add() handles MSI/Legacy interrupts 5849 */ 5850 static int 5851 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5852 { 5853 dev_info_t *devinfo; 5854 int count, avail, actual; 5855 int x, y, rc, inum = 0; 5856 int flag; 5857 ddi_intr_handler_t *intr_handler; 5858 5859 devinfo = Adapter->dip; 5860 5861 /* get number of interrupts */ 5862 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5863 if ((rc != DDI_SUCCESS) || (count == 0)) { 5864 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5865 "Get interrupt number failed. Return: %d, count: %d\n", 5866 rc, count); 5867 return (DDI_FAILURE); 5868 } 5869 5870 /* get number of available interrupts */ 5871 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5872 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5873 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5874 "Get interrupt available number failed. " 5875 "Return: %d, available: %d\n", rc, avail); 5876 return (DDI_FAILURE); 5877 } 5878 5879 if (avail < count) { 5880 /* EMPTY */ 5881 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5882 "Interrupts count: %d, available: %d\n", 5883 count, avail); 5884 } 5885 5886 /* Allocate an array of interrupt handles */ 5887 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5888 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5889 5890 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5891 flag = DDI_INTR_ALLOC_NORMAL; 5892 5893 /* call ddi_intr_alloc() */ 5894 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5895 count, &actual, flag); 5896 5897 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5898 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5899 "Allocate interrupts failed: %d\n", rc); 5900 5901 kmem_free(Adapter->htable, Adapter->intr_size); 5902 return (DDI_FAILURE); 5903 } 5904 5905 if (actual < count) { 5906 /* EMPTY */ 5907 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5908 "Interrupts requested: %d, received: %d\n", 5909 count, actual); 5910 } 5911 5912 Adapter->intr_cnt = actual; 5913 5914 /* Get priority for first msi, assume remaining are all the same */ 5915 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5916 5917 if (rc != DDI_SUCCESS) { 5918 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5919 "Get interrupt priority failed: %d\n", rc); 5920 5921 /* Free already allocated intr */ 5922 for (y = 0; y < actual; y++) 5923 (void) ddi_intr_free(Adapter->htable[y]); 5924 5925 kmem_free(Adapter->htable, Adapter->intr_size); 5926 return (DDI_FAILURE); 5927 } 5928 5929 /* 5930 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5931 * use the interrupt service routine e1000g_intr_pciexpress() 5932 * to avoid interrupt stealing when sharing interrupt with other 5933 * devices. 5934 */ 5935 if (Adapter->shared.mac.type < e1000_82571) 5936 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5937 else 5938 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5939 5940 /* Call ddi_intr_add_handler() */ 5941 for (x = 0; x < actual; x++) { 5942 rc = ddi_intr_add_handler(Adapter->htable[x], 5943 intr_handler, (caddr_t)Adapter, NULL); 5944 5945 if (rc != DDI_SUCCESS) { 5946 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5947 "Add interrupt handler failed: %d\n", rc); 5948 5949 /* Remove already added handler */ 5950 for (y = 0; y < x; y++) 5951 (void) ddi_intr_remove_handler( 5952 Adapter->htable[y]); 5953 5954 /* Free already allocated intr */ 5955 for (y = 0; y < actual; y++) 5956 (void) ddi_intr_free(Adapter->htable[y]); 5957 5958 kmem_free(Adapter->htable, Adapter->intr_size); 5959 return (DDI_FAILURE); 5960 } 5961 } 5962 5963 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5964 5965 if (rc != DDI_SUCCESS) { 5966 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5967 "Get interrupt cap failed: %d\n", rc); 5968 5969 /* Free already allocated intr */ 5970 for (y = 0; y < actual; y++) { 5971 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5972 (void) ddi_intr_free(Adapter->htable[y]); 5973 } 5974 5975 kmem_free(Adapter->htable, Adapter->intr_size); 5976 return (DDI_FAILURE); 5977 } 5978 5979 return (DDI_SUCCESS); 5980 } 5981 5982 static int 5983 e1000g_rem_intrs(struct e1000g *Adapter) 5984 { 5985 int x; 5986 int rc; 5987 5988 for (x = 0; x < Adapter->intr_cnt; x++) { 5989 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5990 if (rc != DDI_SUCCESS) { 5991 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5992 "Remove intr handler failed: %d\n", rc); 5993 return (DDI_FAILURE); 5994 } 5995 5996 rc = ddi_intr_free(Adapter->htable[x]); 5997 if (rc != DDI_SUCCESS) { 5998 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5999 "Free intr failed: %d\n", rc); 6000 return (DDI_FAILURE); 6001 } 6002 } 6003 6004 kmem_free(Adapter->htable, Adapter->intr_size); 6005 6006 return (DDI_SUCCESS); 6007 } 6008 6009 static int 6010 e1000g_enable_intrs(struct e1000g *Adapter) 6011 { 6012 int x; 6013 int rc; 6014 6015 /* Enable interrupts */ 6016 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6017 /* Call ddi_intr_block_enable() for MSI */ 6018 rc = ddi_intr_block_enable(Adapter->htable, 6019 Adapter->intr_cnt); 6020 if (rc != DDI_SUCCESS) { 6021 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6022 "Enable block intr failed: %d\n", rc); 6023 return (DDI_FAILURE); 6024 } 6025 } else { 6026 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 6027 for (x = 0; x < Adapter->intr_cnt; x++) { 6028 rc = ddi_intr_enable(Adapter->htable[x]); 6029 if (rc != DDI_SUCCESS) { 6030 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6031 "Enable intr failed: %d\n", rc); 6032 return (DDI_FAILURE); 6033 } 6034 } 6035 } 6036 6037 return (DDI_SUCCESS); 6038 } 6039 6040 static int 6041 e1000g_disable_intrs(struct e1000g *Adapter) 6042 { 6043 int x; 6044 int rc; 6045 6046 /* Disable all interrupts */ 6047 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6048 rc = ddi_intr_block_disable(Adapter->htable, 6049 Adapter->intr_cnt); 6050 if (rc != DDI_SUCCESS) { 6051 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6052 "Disable block intr failed: %d\n", rc); 6053 return (DDI_FAILURE); 6054 } 6055 } else { 6056 for (x = 0; x < Adapter->intr_cnt; x++) { 6057 rc = ddi_intr_disable(Adapter->htable[x]); 6058 if (rc != DDI_SUCCESS) { 6059 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6060 "Disable intr failed: %d\n", rc); 6061 return (DDI_FAILURE); 6062 } 6063 } 6064 } 6065 6066 return (DDI_SUCCESS); 6067 } 6068 6069 /* 6070 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 6071 */ 6072 static void 6073 e1000g_get_phy_state(struct e1000g *Adapter) 6074 { 6075 struct e1000_hw *hw = &Adapter->shared; 6076 6077 if (hw->phy.media_type == e1000_media_type_copper) { 6078 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 6079 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 6080 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 6081 &Adapter->phy_an_adv); 6082 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 6083 &Adapter->phy_an_exp); 6084 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 6085 &Adapter->phy_ext_status); 6086 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 6087 &Adapter->phy_1000t_ctrl); 6088 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 6089 &Adapter->phy_1000t_status); 6090 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 6091 &Adapter->phy_lp_able); 6092 6093 Adapter->param_autoneg_cap = 6094 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 6095 Adapter->param_pause_cap = 6096 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6097 Adapter->param_asym_pause_cap = 6098 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6099 Adapter->param_1000fdx_cap = 6100 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 6101 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 6102 Adapter->param_1000hdx_cap = 6103 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 6104 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 6105 Adapter->param_100t4_cap = 6106 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 6107 Adapter->param_100fdx_cap = 6108 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6109 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 6110 Adapter->param_100hdx_cap = 6111 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6112 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6113 Adapter->param_10fdx_cap = 6114 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6115 Adapter->param_10hdx_cap = 6116 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6117 6118 Adapter->param_adv_autoneg = hw->mac.autoneg; 6119 Adapter->param_adv_pause = 6120 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6121 Adapter->param_adv_asym_pause = 6122 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6123 Adapter->param_adv_1000hdx = 6124 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 6125 Adapter->param_adv_100t4 = 6126 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 6127 if (Adapter->param_adv_autoneg == 1) { 6128 Adapter->param_adv_1000fdx = 6129 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 6130 ? 1 : 0; 6131 Adapter->param_adv_100fdx = 6132 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 6133 ? 1 : 0; 6134 Adapter->param_adv_100hdx = 6135 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 6136 ? 1 : 0; 6137 Adapter->param_adv_10fdx = 6138 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 6139 Adapter->param_adv_10hdx = 6140 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 6141 } 6142 6143 Adapter->param_lp_autoneg = 6144 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 6145 Adapter->param_lp_pause = 6146 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 6147 Adapter->param_lp_asym_pause = 6148 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 6149 Adapter->param_lp_1000fdx = 6150 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 6151 Adapter->param_lp_1000hdx = 6152 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 6153 Adapter->param_lp_100t4 = 6154 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 6155 Adapter->param_lp_100fdx = 6156 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 6157 Adapter->param_lp_100hdx = 6158 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 6159 Adapter->param_lp_10fdx = 6160 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 6161 Adapter->param_lp_10hdx = 6162 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 6163 } else { 6164 /* 6165 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 6166 * it can only work with 1Gig Full Duplex Link Partner. 6167 */ 6168 Adapter->param_autoneg_cap = 0; 6169 Adapter->param_pause_cap = 1; 6170 Adapter->param_asym_pause_cap = 1; 6171 Adapter->param_1000fdx_cap = 1; 6172 Adapter->param_1000hdx_cap = 0; 6173 Adapter->param_100t4_cap = 0; 6174 Adapter->param_100fdx_cap = 0; 6175 Adapter->param_100hdx_cap = 0; 6176 Adapter->param_10fdx_cap = 0; 6177 Adapter->param_10hdx_cap = 0; 6178 6179 Adapter->param_adv_autoneg = 0; 6180 Adapter->param_adv_pause = 1; 6181 Adapter->param_adv_asym_pause = 1; 6182 Adapter->param_adv_1000fdx = 1; 6183 Adapter->param_adv_1000hdx = 0; 6184 Adapter->param_adv_100t4 = 0; 6185 Adapter->param_adv_100fdx = 0; 6186 Adapter->param_adv_100hdx = 0; 6187 Adapter->param_adv_10fdx = 0; 6188 Adapter->param_adv_10hdx = 0; 6189 6190 Adapter->param_lp_autoneg = 0; 6191 Adapter->param_lp_pause = 0; 6192 Adapter->param_lp_asym_pause = 0; 6193 Adapter->param_lp_1000fdx = 0; 6194 Adapter->param_lp_1000hdx = 0; 6195 Adapter->param_lp_100t4 = 0; 6196 Adapter->param_lp_100fdx = 0; 6197 Adapter->param_lp_100hdx = 0; 6198 Adapter->param_lp_10fdx = 0; 6199 Adapter->param_lp_10hdx = 0; 6200 } 6201 } 6202 6203 /* 6204 * FMA support 6205 */ 6206 6207 int 6208 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6209 { 6210 ddi_fm_error_t de; 6211 6212 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6213 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6214 return (de.fme_status); 6215 } 6216 6217 int 6218 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6219 { 6220 ddi_fm_error_t de; 6221 6222 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6223 return (de.fme_status); 6224 } 6225 6226 /* 6227 * The IO fault service error handling callback function 6228 */ 6229 /* ARGSUSED2 */ 6230 static int 6231 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6232 { 6233 /* 6234 * as the driver can always deal with an error in any dma or 6235 * access handle, we can just return the fme_status value. 6236 */ 6237 pci_ereport_post(dip, err, NULL); 6238 return (err->fme_status); 6239 } 6240 6241 static void 6242 e1000g_fm_init(struct e1000g *Adapter) 6243 { 6244 ddi_iblock_cookie_t iblk; 6245 int fma_dma_flag; 6246 6247 /* Only register with IO Fault Services if we have some capability */ 6248 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6249 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6250 } else { 6251 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6252 } 6253 6254 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6255 fma_dma_flag = 1; 6256 } else { 6257 fma_dma_flag = 0; 6258 } 6259 6260 (void) e1000g_set_fma_flags(fma_dma_flag); 6261 6262 if (Adapter->fm_capabilities) { 6263 6264 /* Register capabilities with IO Fault Services */ 6265 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6266 6267 /* 6268 * Initialize pci ereport capabilities if ereport capable 6269 */ 6270 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6271 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6272 pci_ereport_setup(Adapter->dip); 6273 6274 /* 6275 * Register error callback if error callback capable 6276 */ 6277 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6278 ddi_fm_handler_register(Adapter->dip, 6279 e1000g_fm_error_cb, (void*) Adapter); 6280 } 6281 } 6282 6283 static void 6284 e1000g_fm_fini(struct e1000g *Adapter) 6285 { 6286 /* Only unregister FMA capabilities if we registered some */ 6287 if (Adapter->fm_capabilities) { 6288 6289 /* 6290 * Release any resources allocated by pci_ereport_setup() 6291 */ 6292 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6293 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6294 pci_ereport_teardown(Adapter->dip); 6295 6296 /* 6297 * Un-register error callback if error callback capable 6298 */ 6299 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6300 ddi_fm_handler_unregister(Adapter->dip); 6301 6302 /* Unregister from IO Fault Services */ 6303 mutex_enter(&e1000g_rx_detach_lock); 6304 ddi_fm_fini(Adapter->dip); 6305 if (Adapter->priv_dip != NULL) { 6306 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6307 } 6308 mutex_exit(&e1000g_rx_detach_lock); 6309 } 6310 } 6311 6312 void 6313 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6314 { 6315 uint64_t ena; 6316 char buf[FM_MAX_CLASS]; 6317 6318 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6319 ena = fm_ena_generate(0, FM_ENA_FMT1); 6320 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6321 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6322 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6323 } 6324 } 6325 6326 /* 6327 * quiesce(9E) entry point. 6328 * 6329 * This function is called when the system is single-threaded at high 6330 * PIL with preemption disabled. Therefore, this function must not be 6331 * blocked. 6332 * 6333 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6334 * DDI_FAILURE indicates an error condition and should almost never happen. 6335 */ 6336 static int 6337 e1000g_quiesce(dev_info_t *devinfo) 6338 { 6339 struct e1000g *Adapter; 6340 6341 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6342 6343 if (Adapter == NULL) 6344 return (DDI_FAILURE); 6345 6346 e1000g_clear_all_interrupts(Adapter); 6347 6348 (void) e1000_reset_hw(&Adapter->shared); 6349 6350 /* Setup our HW Tx Head & Tail descriptor pointers */ 6351 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6352 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6353 6354 /* Setup our HW Rx Head & Tail descriptor pointers */ 6355 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6356 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6357 6358 return (DDI_SUCCESS); 6359 } 6360 6361 /* 6362 * synchronize the adv* and en* parameters. 6363 * 6364 * See comments in <sys/dld.h> for details of the *_en_* 6365 * parameters. The usage of ndd for setting adv parameters will 6366 * synchronize all the en parameters with the e1000g parameters, 6367 * implicitly disabling any settings made via dladm. 6368 */ 6369 static void 6370 e1000g_param_sync(struct e1000g *Adapter) 6371 { 6372 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6373 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6374 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6375 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6376 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6377 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6378 } 6379 6380 /* 6381 * e1000g_get_driver_control - tell manageability firmware that the driver 6382 * has control. 6383 */ 6384 static void 6385 e1000g_get_driver_control(struct e1000_hw *hw) 6386 { 6387 uint32_t ctrl_ext; 6388 uint32_t swsm; 6389 6390 /* tell manageability firmware the driver has taken over */ 6391 switch (hw->mac.type) { 6392 case e1000_82573: 6393 swsm = E1000_READ_REG(hw, E1000_SWSM); 6394 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6395 break; 6396 case e1000_82571: 6397 case e1000_82572: 6398 case e1000_82574: 6399 case e1000_80003es2lan: 6400 case e1000_ich8lan: 6401 case e1000_ich9lan: 6402 case e1000_ich10lan: 6403 case e1000_pchlan: 6404 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6405 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6406 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6407 break; 6408 default: 6409 /* no manageability firmware: do nothing */ 6410 break; 6411 } 6412 } 6413 6414 /* 6415 * e1000g_release_driver_control - tell manageability firmware that the driver 6416 * has released control. 6417 */ 6418 static void 6419 e1000g_release_driver_control(struct e1000_hw *hw) 6420 { 6421 uint32_t ctrl_ext; 6422 uint32_t swsm; 6423 6424 /* tell manageability firmware the driver has released control */ 6425 switch (hw->mac.type) { 6426 case e1000_82573: 6427 swsm = E1000_READ_REG(hw, E1000_SWSM); 6428 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6429 break; 6430 case e1000_82571: 6431 case e1000_82572: 6432 case e1000_82574: 6433 case e1000_80003es2lan: 6434 case e1000_ich8lan: 6435 case e1000_ich9lan: 6436 case e1000_ich10lan: 6437 case e1000_pchlan: 6438 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6439 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6440 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6441 break; 6442 default: 6443 /* no manageability firmware: do nothing */ 6444 break; 6445 } 6446 } 6447 6448 /* 6449 * Restore e1000g promiscuous mode. 6450 */ 6451 static void 6452 e1000g_restore_promisc(struct e1000g *Adapter) 6453 { 6454 if (Adapter->e1000g_promisc) { 6455 uint32_t rctl; 6456 6457 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6458 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6459 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6460 } 6461 } 6462