1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include "e1000g_sw.h" 47 #include "e1000g_debug.h" 48 49 #define E1000_RX_INTPT_TIME 128 50 #define E1000_RX_PKT_CNT 8 51 52 static char ident[] = "Intel PRO/1000 Ethernet 5.2.0"; 53 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 54 static char e1000g_version[] = "Driver Ver. 5.2.0"; 55 56 /* 57 * Proto types for DDI entry points 58 */ 59 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 60 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 61 62 /* 63 * init and intr routines prototype 64 */ 65 static int e1000g_resume(dev_info_t *); 66 static int e1000g_suspend(dev_info_t *); 67 static uint_t e1000g_intr_pciexpress(caddr_t); 68 static uint_t e1000g_intr(caddr_t); 69 static void e1000g_intr_work(struct e1000g *, uint32_t); 70 #pragma inline(e1000g_intr_work) 71 static int e1000g_init(struct e1000g *); 72 static int e1000g_start(struct e1000g *, boolean_t); 73 static void e1000g_stop(struct e1000g *, boolean_t); 74 static int e1000g_m_start(void *); 75 static void e1000g_m_stop(void *); 76 static int e1000g_m_promisc(void *, boolean_t); 77 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 78 static int e1000g_m_unicst(void *, const uint8_t *); 79 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 80 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 81 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 82 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 83 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 84 static void e1000g_m_blank(void *, time_t, uint32_t); 85 static void e1000g_m_resources(void *); 86 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 87 static void e1000g_init_locks(struct e1000g *); 88 static void e1000g_destroy_locks(struct e1000g *); 89 static int e1000g_identify_hardware(struct e1000g *); 90 static int e1000g_regs_map(struct e1000g *); 91 static int e1000g_set_driver_params(struct e1000g *); 92 static int e1000g_register_mac(struct e1000g *); 93 static boolean_t e1000g_rx_drain(struct e1000g *); 94 static boolean_t e1000g_tx_drain(struct e1000g *); 95 static void e1000g_init_unicst(struct e1000g *); 96 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 97 98 /* 99 * Local routines 100 */ 101 static void e1000g_tx_clean(struct e1000g *); 102 static void e1000g_rx_clean(struct e1000g *); 103 static void e1000g_link_timer(void *); 104 static void e1000g_local_timer(void *); 105 static boolean_t e1000g_link_check(struct e1000g *); 106 static boolean_t e1000g_stall_check(struct e1000g *); 107 static void e1000g_smartspeed(struct e1000g *); 108 static void e1000g_get_conf(struct e1000g *); 109 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 110 static void enable_watchdog_timer(struct e1000g *); 111 static void disable_watchdog_timer(struct e1000g *); 112 static void start_watchdog_timer(struct e1000g *); 113 static void restart_watchdog_timer(struct e1000g *); 114 static void stop_watchdog_timer(struct e1000g *); 115 static void stop_link_timer(struct e1000g *); 116 static void stop_82547_timer(e1000g_tx_ring_t *); 117 static void e1000g_force_speed_duplex(struct e1000g *); 118 static void e1000g_get_max_frame_size(struct e1000g *); 119 static boolean_t is_valid_mac_addr(uint8_t *); 120 static void e1000g_unattach(dev_info_t *, struct e1000g *); 121 #ifdef E1000G_DEBUG 122 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 123 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 124 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 125 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 126 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 127 struct iocblk *, mblk_t *); 128 #endif 129 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 130 struct iocblk *, mblk_t *); 131 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 132 static void e1000g_set_internal_loopback(struct e1000g *); 133 static void e1000g_set_external_loopback_1000(struct e1000g *); 134 static void e1000g_set_external_loopback_100(struct e1000g *); 135 static void e1000g_set_external_loopback_10(struct e1000g *); 136 static int e1000g_add_intrs(struct e1000g *); 137 static int e1000g_intr_add(struct e1000g *, int); 138 static int e1000g_rem_intrs(struct e1000g *); 139 static int e1000g_enable_intrs(struct e1000g *); 140 static int e1000g_disable_intrs(struct e1000g *); 141 static boolean_t e1000g_link_up(struct e1000g *); 142 #ifdef __sparc 143 static boolean_t e1000g_find_mac_address(struct e1000g *); 144 #endif 145 146 static struct cb_ops cb_ws_ops = { 147 nulldev, /* cb_open */ 148 nulldev, /* cb_close */ 149 nodev, /* cb_strategy */ 150 nodev, /* cb_print */ 151 nodev, /* cb_dump */ 152 nodev, /* cb_read */ 153 nodev, /* cb_write */ 154 nodev, /* cb_ioctl */ 155 nodev, /* cb_devmap */ 156 nodev, /* cb_mmap */ 157 nodev, /* cb_segmap */ 158 nochpoll, /* cb_chpoll */ 159 ddi_prop_op, /* cb_prop_op */ 160 NULL, /* cb_stream */ 161 D_MP | D_HOTPLUG, /* cb_flag */ 162 CB_REV, /* cb_rev */ 163 nodev, /* cb_aread */ 164 nodev /* cb_awrite */ 165 }; 166 167 static struct dev_ops ws_ops = { 168 DEVO_REV, /* devo_rev */ 169 0, /* devo_refcnt */ 170 NULL, /* devo_getinfo */ 171 nulldev, /* devo_identify */ 172 nulldev, /* devo_probe */ 173 e1000g_attach, /* devo_attach */ 174 e1000g_detach, /* devo_detach */ 175 nodev, /* devo_reset */ 176 &cb_ws_ops, /* devo_cb_ops */ 177 NULL, /* devo_bus_ops */ 178 ddi_power /* devo_power */ 179 }; 180 181 static struct modldrv modldrv = { 182 &mod_driverops, /* Type of module. This one is a driver */ 183 ident, /* Discription string */ 184 &ws_ops, /* driver ops */ 185 }; 186 187 static struct modlinkage modlinkage = { 188 MODREV_1, &modldrv, NULL 189 }; 190 191 /* Access attributes for register mapping */ 192 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 193 DDI_DEVICE_ATTR_V0, 194 DDI_STRUCTURE_LE_ACC, 195 DDI_STRICTORDER_ACC, 196 }; 197 198 #define E1000G_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 199 200 static mac_callbacks_t e1000g_m_callbacks = { 201 E1000G_M_CALLBACK_FLAGS, 202 e1000g_m_stat, 203 e1000g_m_start, 204 e1000g_m_stop, 205 e1000g_m_promisc, 206 e1000g_m_multicst, 207 e1000g_m_unicst, 208 e1000g_m_tx, 209 e1000g_m_resources, 210 e1000g_m_ioctl, 211 e1000g_m_getcapab 212 }; 213 214 /* 215 * Global variables 216 */ 217 uint32_t e1000g_mblks_pending = 0; 218 /* 219 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 220 * Here we maintain a private dev_info list if e1000g_force_detach is 221 * enabled. If we force the driver to detach while there are still some 222 * rx buffers retained in the upper layer, we have to keep a copy of the 223 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 224 * structure will be freed after the driver is detached. However when we 225 * finally free those rx buffers released by the upper layer, we need to 226 * refer to the dev_info to free the dma buffers. So we save a copy of 227 * the dev_info for this purpose. On x86 platform, we assume this copy 228 * of dev_info is always valid, but on SPARC platform, it could be invalid 229 * after the system board level DR operation. For this reason, the global 230 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 231 */ 232 #ifdef __sparc 233 boolean_t e1000g_force_detach = B_FALSE; 234 #else 235 boolean_t e1000g_force_detach = B_TRUE; 236 #endif 237 private_devi_list_t *e1000g_private_devi_list = NULL; 238 239 /* 240 * The rwlock is defined to protect the whole processing of rx recycling 241 * and the rx packets release in detach processing to make them mutually 242 * exclusive. 243 * The rx recycling processes different rx packets in different threads, 244 * so it will be protected with RW_READER and it won't block any other rx 245 * recycling threads. 246 * While the detach processing will be protected with RW_WRITER to make 247 * it mutually exclusive with the rx recycling. 248 */ 249 krwlock_t e1000g_rx_detach_lock; 250 /* 251 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 252 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 253 * If there are many e1000g instances, the system may run out of DVMA 254 * resources during the initialization of the instances, then the flag will 255 * be changed to "USE_DMA". Because different e1000g instances are initialized 256 * in parallel, we need to use this lock to protect the flag. 257 */ 258 krwlock_t e1000g_dma_type_lock; 259 260 261 /* 262 * Loadable module configuration entry points for the driver 263 */ 264 265 /* 266 * _init - module initialization 267 */ 268 int 269 _init(void) 270 { 271 int status; 272 273 mac_init_ops(&ws_ops, WSNAME); 274 status = mod_install(&modlinkage); 275 if (status != DDI_SUCCESS) 276 mac_fini_ops(&ws_ops); 277 else { 278 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 279 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 280 } 281 282 return (status); 283 } 284 285 /* 286 * _fini - module finalization 287 */ 288 int 289 _fini(void) 290 { 291 int status; 292 293 rw_enter(&e1000g_rx_detach_lock, RW_READER); 294 if (e1000g_mblks_pending != 0) { 295 rw_exit(&e1000g_rx_detach_lock); 296 return (EBUSY); 297 } 298 rw_exit(&e1000g_rx_detach_lock); 299 300 status = mod_remove(&modlinkage); 301 if (status == DDI_SUCCESS) { 302 mac_fini_ops(&ws_ops); 303 304 if (e1000g_force_detach) { 305 private_devi_list_t *devi_node; 306 307 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 308 while (e1000g_private_devi_list != NULL) { 309 devi_node = e1000g_private_devi_list; 310 e1000g_private_devi_list = 311 e1000g_private_devi_list->next; 312 313 kmem_free(devi_node->priv_dip, 314 sizeof (struct dev_info)); 315 kmem_free(devi_node, 316 sizeof (private_devi_list_t)); 317 } 318 rw_exit(&e1000g_rx_detach_lock); 319 } 320 321 rw_destroy(&e1000g_rx_detach_lock); 322 rw_destroy(&e1000g_dma_type_lock); 323 } 324 325 return (status); 326 } 327 328 /* 329 * _info - module information 330 */ 331 int 332 _info(struct modinfo *modinfop) 333 { 334 return (mod_info(&modlinkage, modinfop)); 335 } 336 337 /* 338 * e1000g_attach - driver attach 339 * 340 * This function is the device-specific initialization entry 341 * point. This entry point is required and must be written. 342 * The DDI_ATTACH command must be provided in the attach entry 343 * point. When attach() is called with cmd set to DDI_ATTACH, 344 * all normal kernel services (such as kmem_alloc(9F)) are 345 * available for use by the driver. 346 * 347 * The attach() function will be called once for each instance 348 * of the device on the system with cmd set to DDI_ATTACH. 349 * Until attach() succeeds, the only driver entry points which 350 * may be called are open(9E) and getinfo(9E). 351 */ 352 static int 353 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 354 { 355 struct e1000g *Adapter; 356 struct e1000_hw *hw; 357 struct e1000g_osdep *osdep; 358 int instance; 359 360 switch (cmd) { 361 default: 362 e1000g_log(NULL, CE_WARN, 363 "Unsupported command send to e1000g_attach... "); 364 return (DDI_FAILURE); 365 366 case DDI_RESUME: 367 return (e1000g_resume(devinfo)); 368 369 case DDI_ATTACH: 370 break; 371 } 372 373 /* 374 * get device instance number 375 */ 376 instance = ddi_get_instance(devinfo); 377 378 /* 379 * Allocate soft data structure 380 */ 381 Adapter = 382 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 383 384 Adapter->dip = devinfo; 385 Adapter->instance = instance; 386 Adapter->tx_ring->adapter = Adapter; 387 Adapter->rx_ring->adapter = Adapter; 388 389 hw = &Adapter->shared; 390 osdep = &Adapter->osdep; 391 hw->back = osdep; 392 osdep->adapter = Adapter; 393 394 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 395 396 if (e1000g_force_detach) { 397 private_devi_list_t *devi_node; 398 399 Adapter->priv_dip = 400 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 401 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 402 sizeof (struct dev_info)); 403 404 devi_node = 405 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 406 407 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 408 devi_node->dip = devinfo; 409 devi_node->priv_dip = Adapter->priv_dip; 410 devi_node->next = e1000g_private_devi_list; 411 e1000g_private_devi_list = devi_node; 412 rw_exit(&e1000g_rx_detach_lock); 413 } 414 415 /* 416 * PCI Configure 417 */ 418 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 419 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 420 goto attach_fail; 421 } 422 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 423 424 /* 425 * Setup hardware 426 */ 427 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 428 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 429 goto attach_fail; 430 } 431 432 /* 433 * Map in the device registers. 434 */ 435 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 436 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 437 goto attach_fail; 438 } 439 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 440 441 /* 442 * Initialize driver parameters 443 */ 444 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 445 goto attach_fail; 446 } 447 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 448 449 /* 450 * Initialize interrupts 451 */ 452 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 453 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 454 goto attach_fail; 455 } 456 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 457 458 /* 459 * Initialize mutex's for this device. 460 * Do this before enabling the interrupt handler and 461 * register the softint to avoid the condition where 462 * interrupt handler can try using uninitialized mutex 463 */ 464 e1000g_init_locks(Adapter); 465 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 466 467 Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; 468 if (ddi_intr_add_softint(devinfo, 469 &Adapter->tx_softint_handle, Adapter->tx_softint_pri, 470 e1000g_tx_softint_worker, (caddr_t)Adapter) != DDI_SUCCESS) { 471 e1000g_log(Adapter, CE_WARN, "Add soft intr failed"); 472 goto attach_fail; 473 } 474 Adapter->attach_progress |= ATTACH_PROGRESS_SOFT_INTR; 475 476 /* 477 * Initialize Driver Counters 478 */ 479 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 480 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 481 goto attach_fail; 482 } 483 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 484 485 /* 486 * Initialize chip hardware and software structures 487 */ 488 if (e1000g_init(Adapter) != DDI_SUCCESS) { 489 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 490 goto attach_fail; 491 } 492 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 493 494 /* 495 * Initialize NDD parameters 496 */ 497 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 498 e1000g_log(Adapter, CE_WARN, "Init ndd failed"); 499 goto attach_fail; 500 } 501 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 502 503 /* 504 * Register the driver to the MAC 505 */ 506 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 507 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 508 goto attach_fail; 509 } 510 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 511 512 /* 513 * Now that mutex locks are initialized, and the chip is also 514 * initialized, enable interrupts. 515 */ 516 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 517 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 518 goto attach_fail; 519 } 520 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 521 522 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 523 524 return (DDI_SUCCESS); 525 526 attach_fail: 527 e1000g_unattach(devinfo, Adapter); 528 return (DDI_FAILURE); 529 } 530 531 static int 532 e1000g_register_mac(struct e1000g *Adapter) 533 { 534 struct e1000_hw *hw = &Adapter->shared; 535 mac_register_t *mac; 536 int err; 537 538 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 539 return (DDI_FAILURE); 540 541 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 542 mac->m_driver = Adapter; 543 mac->m_dip = Adapter->dip; 544 mac->m_src_addr = hw->mac.addr; 545 mac->m_callbacks = &e1000g_m_callbacks; 546 mac->m_min_sdu = 0; 547 mac->m_max_sdu = 548 (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) ? 549 hw->mac.max_frame_size - 256 : 550 (hw->mac.max_frame_size != ETHERMAX) ? 551 hw->mac.max_frame_size - 24 : ETHERMTU; 552 553 err = mac_register(mac, &Adapter->mh); 554 mac_free(mac); 555 556 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 557 } 558 559 static int 560 e1000g_identify_hardware(struct e1000g *Adapter) 561 { 562 struct e1000_hw *hw = &Adapter->shared; 563 struct e1000g_osdep *osdep = &Adapter->osdep; 564 565 /* Get the device id */ 566 hw->vendor_id = 567 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 568 hw->device_id = 569 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 570 hw->revision_id = 571 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 572 hw->subsystem_device_id = 573 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 574 hw->subsystem_vendor_id = 575 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 576 577 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 578 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 579 "MAC type could not be set properly."); 580 return (DDI_FAILURE); 581 } 582 583 return (DDI_SUCCESS); 584 } 585 586 static int 587 e1000g_regs_map(struct e1000g *Adapter) 588 { 589 dev_info_t *devinfo = Adapter->dip; 590 struct e1000_hw *hw = &Adapter->shared; 591 struct e1000g_osdep *osdep = &Adapter->osdep; 592 off_t mem_size; 593 594 /* 595 * first get the size of device register to be mapped. The 596 * second parameter is the register we are interested. I our 597 * wiseman 0 is for config registers and 1 is for memory mapped 598 * registers Mem size should have memory mapped region size 599 */ 600 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 601 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 602 "ddi_dev_regsize for registers failed"); 603 return (DDI_FAILURE); 604 } 605 606 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 607 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 608 &osdep->reg_handle)) != DDI_SUCCESS) { 609 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 610 "ddi_regs_map_setup for registers failed"); 611 goto regs_map_fail; 612 } 613 614 /* ICH needs to map flash memory */ 615 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 616 /* get flash size */ 617 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 618 &mem_size) != DDI_SUCCESS) { 619 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 620 "ddi_dev_regsize for ICH flash failed"); 621 goto regs_map_fail; 622 } 623 624 /* map flash in */ 625 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 626 (caddr_t *)&hw->flash_address, 0, 627 mem_size, &e1000g_regs_acc_attr, 628 &osdep->ich_flash_handle) != DDI_SUCCESS) { 629 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 630 "ddi_regs_map_setup for ICH flash failed"); 631 goto regs_map_fail; 632 } 633 } 634 635 return (DDI_SUCCESS); 636 637 regs_map_fail: 638 if (osdep->reg_handle != NULL) 639 ddi_regs_map_free(&osdep->reg_handle); 640 641 return (DDI_FAILURE); 642 } 643 644 static int 645 e1000g_set_driver_params(struct e1000g *Adapter) 646 { 647 struct e1000_hw *hw; 648 e1000g_tx_ring_t *tx_ring; 649 uint32_t mem_bar, io_bar, bar64; 650 #ifdef __sparc 651 dev_info_t *devinfo = Adapter->dip; 652 ulong_t iommu_pagesize; 653 #endif 654 655 hw = &Adapter->shared; 656 657 /* Set MAC type and initialize hardware functions */ 658 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 659 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 660 "Could not setup hardware functions"); 661 return (DDI_FAILURE); 662 } 663 664 /* Get bus information */ 665 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 666 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 667 "Could not get bus information"); 668 return (DDI_FAILURE); 669 } 670 671 /* get mem_base addr */ 672 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 673 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 674 675 /* get io_base addr */ 676 if (hw->mac.type >= e1000_82544) { 677 if (bar64) { 678 /* IO BAR is different for 64 bit BAR mode */ 679 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 680 PCI_CONF_BASE4); 681 } else { 682 /* normal 32-bit BAR mode */ 683 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 684 PCI_CONF_BASE2); 685 } 686 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 687 } else { 688 /* no I/O access for adapters prior to 82544 */ 689 hw->io_base = 0x0; 690 } 691 692 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 693 694 hw->mac.autoneg_failed = B_TRUE; 695 696 /* Set the wait_for_link flag to B_FALSE */ 697 hw->phy.wait_for_link = B_FALSE; 698 699 /* Adaptive IFS related changes */ 700 hw->mac.adaptive_ifs = B_TRUE; 701 702 /* Enable phy init script for IGP phy of 82541/82547 */ 703 if ((hw->mac.type == e1000_82547) || 704 (hw->mac.type == e1000_82541) || 705 (hw->mac.type == e1000_82547_rev_2) || 706 (hw->mac.type == e1000_82541_rev_2)) 707 e1000_init_script_state_82541(hw, B_TRUE); 708 709 /* Enable the TTL workaround for 82541/82547 */ 710 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 711 712 #ifdef __sparc 713 Adapter->strip_crc = B_TRUE; 714 #else 715 Adapter->strip_crc = B_FALSE; 716 #endif 717 718 /* Get conf file properties */ 719 e1000g_get_conf(Adapter); 720 721 /* Get speed/duplex settings in conf file */ 722 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 723 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 724 e1000g_force_speed_duplex(Adapter); 725 726 /* Get Jumbo Frames settings in conf file */ 727 e1000g_get_max_frame_size(Adapter); 728 hw->mac.min_frame_size = 729 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 730 731 #ifdef __sparc 732 /* Get the system page size */ 733 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 734 iommu_pagesize = dvma_pagesize(devinfo); 735 if (iommu_pagesize != 0) { 736 if (Adapter->sys_page_sz == iommu_pagesize) { 737 if (iommu_pagesize > 0x4000) 738 Adapter->sys_page_sz = 0x4000; 739 } else { 740 if (Adapter->sys_page_sz > iommu_pagesize) 741 Adapter->sys_page_sz = iommu_pagesize; 742 } 743 } 744 Adapter->dvma_page_num = hw->mac.max_frame_size / 745 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 746 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 747 #endif 748 749 /* Set Rx/Tx buffer size */ 750 switch (hw->mac.max_frame_size) { 751 case ETHERMAX: 752 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 753 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 754 break; 755 case FRAME_SIZE_UPTO_4K: 756 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 757 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 758 break; 759 case FRAME_SIZE_UPTO_8K: 760 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 761 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 762 break; 763 case FRAME_SIZE_UPTO_9K: 764 case FRAME_SIZE_UPTO_16K: 765 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 766 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 767 break; 768 default: 769 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 770 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 771 break; 772 } 773 Adapter->rx_buffer_size += E1000G_IPALIGNPRESERVEROOM; 774 775 #ifndef NO_82542_SUPPORT 776 /* 777 * For Wiseman adapters we have an requirement of having receive 778 * buffers aligned at 256 byte boundary. Since Livengood does not 779 * require this and forcing it for all hardwares will have 780 * performance implications, I am making it applicable only for 781 * Wiseman and for Jumbo frames enabled mode as rest of the time, 782 * it is okay to have normal frames...but it does involve a 783 * potential risk where we may loose data if buffer is not 784 * aligned...so all wiseman boards to have 256 byte aligned 785 * buffers 786 */ 787 if (hw->mac.type < e1000_82543) 788 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 789 else 790 Adapter->rx_buf_align = 1; 791 #endif 792 793 /* Master Latency Timer */ 794 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 795 796 /* copper options */ 797 if (hw->media_type == e1000_media_type_copper) { 798 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 799 hw->phy.disable_polarity_correction = B_FALSE; 800 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 801 } 802 803 /* The initial link state should be "unknown" */ 804 Adapter->link_state = LINK_STATE_UNKNOWN; 805 806 /* Initialize tx parameters */ 807 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 808 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 809 810 tx_ring = Adapter->tx_ring; 811 tx_ring->recycle_low_water = DEFAULT_TX_RECYCLE_LOW_WATER; 812 tx_ring->recycle_num = DEFAULT_TX_RECYCLE_NUM; 813 tx_ring->frags_limit = 814 (hw->mac.max_frame_size / Adapter->tx_bcopy_thresh) + 2; 815 if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) 816 tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); 817 818 /* Initialize rx parameters */ 819 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 820 821 return (DDI_SUCCESS); 822 } 823 824 /* 825 * e1000g_detach - driver detach 826 * 827 * The detach() function is the complement of the attach routine. 828 * If cmd is set to DDI_DETACH, detach() is used to remove the 829 * state associated with a given instance of a device node 830 * prior to the removal of that instance from the system. 831 * 832 * The detach() function will be called once for each instance 833 * of the device for which there has been a successful attach() 834 * once there are no longer any opens on the device. 835 * 836 * Interrupts routine are disabled, All memory allocated by this 837 * driver are freed. 838 */ 839 static int 840 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 841 { 842 struct e1000g *Adapter; 843 844 switch (cmd) { 845 default: 846 return (DDI_FAILURE); 847 848 case DDI_SUSPEND: 849 return (e1000g_suspend(devinfo)); 850 851 case DDI_DETACH: 852 break; 853 } 854 855 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 856 if (Adapter == NULL) 857 return (DDI_FAILURE); 858 859 if (mac_unregister(Adapter->mh) != 0) { 860 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 861 return (DDI_FAILURE); 862 } 863 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 864 865 if (Adapter->started) 866 e1000g_stop(Adapter, B_TRUE); 867 868 if (!e1000g_rx_drain(Adapter)) { 869 if (!e1000g_force_detach) 870 return (DDI_FAILURE); 871 } 872 873 e1000g_unattach(devinfo, Adapter); 874 875 return (DDI_SUCCESS); 876 } 877 878 static void 879 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 880 { 881 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 882 (void) e1000g_disable_intrs(Adapter); 883 } 884 885 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 886 (void) mac_unregister(Adapter->mh); 887 } 888 889 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 890 e1000g_nd_cleanup(Adapter); 891 } 892 893 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 894 (void) e1000g_rem_intrs(Adapter); 895 } 896 897 if (Adapter->attach_progress & ATTACH_PROGRESS_SOFT_INTR) { 898 (void) ddi_intr_remove_softint(Adapter->tx_softint_handle); 899 } 900 901 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 902 (void) ddi_prop_remove_all(devinfo); 903 } 904 905 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 906 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 907 } 908 909 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 910 stop_link_timer(Adapter); 911 e1000_reset_hw(&Adapter->shared); 912 } 913 914 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 915 if (Adapter->osdep.reg_handle != NULL) 916 ddi_regs_map_free(&Adapter->osdep.reg_handle); 917 if (Adapter->osdep.ich_flash_handle != NULL) 918 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 919 } 920 921 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 922 if (Adapter->osdep.cfg_handle != NULL) 923 pci_config_teardown(&Adapter->osdep.cfg_handle); 924 } 925 926 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 927 e1000g_destroy_locks(Adapter); 928 } 929 930 e1000_remove_device(&Adapter->shared); 931 932 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 933 934 /* 935 * Another hotplug spec requirement, 936 * run ddi_set_driver_private(devinfo, null); 937 */ 938 ddi_set_driver_private(devinfo, NULL); 939 } 940 941 static void 942 e1000g_init_locks(struct e1000g *Adapter) 943 { 944 e1000g_tx_ring_t *tx_ring; 945 e1000g_rx_ring_t *rx_ring; 946 947 rw_init(&Adapter->chip_lock, NULL, 948 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 949 mutex_init(&Adapter->link_lock, NULL, 950 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 951 mutex_init(&Adapter->watchdog_lock, NULL, 952 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 953 954 tx_ring = Adapter->tx_ring; 955 956 mutex_init(&tx_ring->tx_lock, NULL, 957 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 958 mutex_init(&tx_ring->usedlist_lock, NULL, 959 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 960 mutex_init(&tx_ring->freelist_lock, NULL, 961 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 962 mutex_init(&tx_ring->mblks_lock, NULL, 963 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 964 965 rx_ring = Adapter->rx_ring; 966 967 mutex_init(&rx_ring->rx_lock, NULL, 968 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 969 mutex_init(&rx_ring->freelist_lock, NULL, 970 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 971 } 972 973 static void 974 e1000g_destroy_locks(struct e1000g *Adapter) 975 { 976 e1000g_tx_ring_t *tx_ring; 977 e1000g_rx_ring_t *rx_ring; 978 979 tx_ring = Adapter->tx_ring; 980 mutex_destroy(&tx_ring->tx_lock); 981 mutex_destroy(&tx_ring->usedlist_lock); 982 mutex_destroy(&tx_ring->freelist_lock); 983 mutex_destroy(&tx_ring->mblks_lock); 984 985 rx_ring = Adapter->rx_ring; 986 mutex_destroy(&rx_ring->rx_lock); 987 mutex_destroy(&rx_ring->freelist_lock); 988 989 mutex_destroy(&Adapter->link_lock); 990 mutex_destroy(&Adapter->watchdog_lock); 991 rw_destroy(&Adapter->chip_lock); 992 } 993 994 static int 995 e1000g_resume(dev_info_t *devinfo) 996 { 997 struct e1000g *Adapter; 998 999 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1000 if (Adapter == NULL) 1001 return (DDI_FAILURE); 1002 1003 if (e1000g_start(Adapter, B_TRUE)) 1004 return (DDI_FAILURE); 1005 1006 return (DDI_SUCCESS); 1007 } 1008 1009 static int 1010 e1000g_suspend(dev_info_t *devinfo) 1011 { 1012 struct e1000g *Adapter; 1013 1014 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1015 if (Adapter == NULL) 1016 return (DDI_FAILURE); 1017 1018 e1000g_stop(Adapter, B_TRUE); 1019 1020 return (DDI_SUCCESS); 1021 } 1022 1023 static int 1024 e1000g_init(struct e1000g *Adapter) 1025 { 1026 uint32_t pba; 1027 uint32_t high_water; 1028 struct e1000_hw *hw; 1029 clock_t link_timeout; 1030 1031 hw = &Adapter->shared; 1032 1033 rw_enter(&Adapter->chip_lock, RW_WRITER); 1034 1035 /* 1036 * reset to put the hardware in a known state 1037 * before we try to do anything with the eeprom 1038 */ 1039 (void) e1000_reset_hw(hw); 1040 1041 if (e1000_validate_nvm_checksum(hw) < 0) { 1042 /* 1043 * Some PCI-E parts fail the first check due to 1044 * the link being in sleep state. Call it again, 1045 * if it fails a second time its a real issue. 1046 */ 1047 if (e1000_validate_nvm_checksum(hw) < 0) { 1048 e1000g_log(Adapter, CE_WARN, 1049 "Invalid NVM checksum. Please contact " 1050 "the vendor to update the NVM."); 1051 goto init_fail; 1052 } 1053 } 1054 1055 #ifdef __sparc 1056 /* 1057 * Firstly, we try to get the local ethernet address from OBP. If 1058 * fail, we get from EEPROM of NIC card. 1059 */ 1060 if (!e1000g_find_mac_address(Adapter)) { 1061 if (e1000_read_mac_addr(hw) < 0) { 1062 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1063 goto init_fail; 1064 } 1065 } 1066 #else 1067 /* Get the local ethernet address. */ 1068 if (e1000_read_mac_addr(hw) < 0) { 1069 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1070 goto init_fail; 1071 } 1072 #endif 1073 1074 /* check for valid mac address */ 1075 if (!is_valid_mac_addr(hw->mac.addr)) { 1076 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1077 goto init_fail; 1078 } 1079 1080 /* Set LAA state for 82571 chipset */ 1081 e1000_set_laa_state_82571(hw, B_TRUE); 1082 1083 /* Master Latency Timer implementation */ 1084 if (Adapter->master_latency_timer) { 1085 pci_config_put8(Adapter->osdep.cfg_handle, 1086 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1087 } 1088 1089 if (hw->mac.type < e1000_82547) { 1090 /* 1091 * Total FIFO is 64K 1092 */ 1093 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1094 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1095 else 1096 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1097 } else if (hw->mac.type >= e1000_82571 && 1098 hw->mac.type <= e1000_82572) { 1099 /* 1100 * Total FIFO is 48K 1101 */ 1102 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1103 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1104 else 1105 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1106 } else if (hw->mac.type == e1000_ich8lan) { 1107 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1108 } else if (hw->mac.type == e1000_ich9lan) { 1109 pba = E1000_PBA_12K; 1110 } else { 1111 /* 1112 * Total FIFO is 40K 1113 */ 1114 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1115 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1116 else 1117 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1118 } 1119 E1000_WRITE_REG(hw, E1000_PBA, pba); 1120 1121 /* 1122 * These parameters set thresholds for the adapter's generation(Tx) 1123 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1124 * settings. Flow control is enabled or disabled in the configuration 1125 * file. 1126 * High-water mark is set down from the top of the rx fifo (not 1127 * sensitive to max_frame_size) and low-water is set just below 1128 * high-water mark. 1129 * The high water mark must be low enough to fit one full frame above 1130 * it in the rx FIFO. Should be the lower of: 1131 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1132 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1133 * Rx FIFO size minus one full frame. 1134 */ 1135 high_water = min(((pba << 10) * 9 / 10), 1136 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1137 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1138 ((pba << 10) - hw->mac.max_frame_size))); 1139 1140 hw->mac.fc_high_water = high_water & 0xFFF8; 1141 hw->mac.fc_low_water = hw->mac.fc_high_water - 8; 1142 1143 if (hw->mac.type == e1000_80003es2lan) 1144 hw->mac.fc_pause_time = 0xFFFF; 1145 else 1146 hw->mac.fc_pause_time = E1000_FC_PAUSE_TIME; 1147 hw->mac.fc_send_xon = B_TRUE; 1148 hw->mac.fc = hw->mac.original_fc; 1149 1150 /* 1151 * Reset the adapter hardware the second time. 1152 */ 1153 (void) e1000_reset_hw(hw); 1154 1155 /* disable wakeup control by default */ 1156 if (hw->mac.type >= e1000_82544) 1157 E1000_WRITE_REG(hw, E1000_WUC, 0); 1158 1159 /* MWI setup */ 1160 e1000_pci_set_mwi(hw); 1161 1162 /* 1163 * Configure/Initialize hardware 1164 */ 1165 if (e1000_init_hw(hw) < 0) { 1166 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1167 goto init_fail; 1168 } 1169 1170 /* Disable Smart Power Down */ 1171 phy_spd_state(hw, B_FALSE); 1172 1173 /* 1174 * Initialize unicast addresses. 1175 */ 1176 e1000g_init_unicst(Adapter); 1177 1178 /* 1179 * Setup and initialize the mctable structures. After this routine 1180 * completes Multicast table will be set 1181 */ 1182 e1000g_setup_multicast(Adapter); 1183 msec_delay(5); 1184 1185 /* 1186 * Implement Adaptive IFS 1187 */ 1188 e1000_reset_adaptive(hw); 1189 1190 /* Setup Interrupt Throttling Register */ 1191 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1192 1193 /* Start the timer for link setup */ 1194 if (hw->mac.autoneg) 1195 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1196 else 1197 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1198 1199 mutex_enter(&Adapter->link_lock); 1200 if (hw->phy.wait_for_link) { 1201 Adapter->link_complete = B_TRUE; 1202 } else { 1203 Adapter->link_complete = B_FALSE; 1204 Adapter->link_tid = timeout(e1000g_link_timer, 1205 (void *)Adapter, link_timeout); 1206 } 1207 mutex_exit(&Adapter->link_lock); 1208 1209 /* Enable PCI-Ex master */ 1210 if (hw->bus.type == e1000_bus_type_pci_express) { 1211 e1000_enable_pciex_master(hw); 1212 } 1213 1214 Adapter->init_count++; 1215 1216 rw_exit(&Adapter->chip_lock); 1217 1218 return (DDI_SUCCESS); 1219 1220 init_fail: 1221 rw_exit(&Adapter->chip_lock); 1222 return (DDI_FAILURE); 1223 } 1224 1225 /* 1226 * Check if the link is up 1227 */ 1228 static boolean_t 1229 e1000g_link_up(struct e1000g *Adapter) 1230 { 1231 struct e1000_hw *hw; 1232 boolean_t link_up; 1233 1234 hw = &Adapter->shared; 1235 1236 /* Ensure this is set to get accurate copper link status */ 1237 hw->mac.get_link_status = B_TRUE; 1238 1239 e1000_check_for_link(hw); 1240 1241 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1242 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1243 ((hw->media_type == e1000_media_type_internal_serdes) && 1244 (hw->mac.serdes_has_link))) { 1245 link_up = B_TRUE; 1246 } else { 1247 link_up = B_FALSE; 1248 } 1249 1250 return (link_up); 1251 } 1252 1253 static void 1254 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1255 { 1256 struct iocblk *iocp; 1257 struct e1000g *e1000gp; 1258 enum ioc_reply status; 1259 int err; 1260 1261 iocp = (struct iocblk *)mp->b_rptr; 1262 iocp->ioc_error = 0; 1263 e1000gp = (struct e1000g *)arg; 1264 1265 ASSERT(e1000gp); 1266 if (e1000gp == NULL) { 1267 miocnak(q, mp, 0, EINVAL); 1268 return; 1269 } 1270 1271 switch (iocp->ioc_cmd) { 1272 1273 case LB_GET_INFO_SIZE: 1274 case LB_GET_INFO: 1275 case LB_GET_MODE: 1276 case LB_SET_MODE: 1277 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1278 break; 1279 1280 case ND_GET: 1281 case ND_SET: 1282 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1283 break; 1284 1285 #ifdef E1000G_DEBUG 1286 case E1000G_IOC_REG_PEEK: 1287 case E1000G_IOC_REG_POKE: 1288 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1289 break; 1290 case E1000G_IOC_CHIP_RESET: 1291 e1000gp->reset_count++; 1292 if (e1000g_reset(e1000gp)) 1293 status = IOC_ACK; 1294 else 1295 status = IOC_INVAL; 1296 break; 1297 #endif 1298 default: 1299 status = IOC_INVAL; 1300 break; 1301 } 1302 1303 /* 1304 * Decide how to reply 1305 */ 1306 switch (status) { 1307 default: 1308 case IOC_INVAL: 1309 /* 1310 * Error, reply with a NAK and EINVAL or the specified error 1311 */ 1312 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1313 EINVAL : iocp->ioc_error); 1314 break; 1315 1316 case IOC_DONE: 1317 /* 1318 * OK, reply already sent 1319 */ 1320 break; 1321 1322 case IOC_ACK: 1323 /* 1324 * OK, reply with an ACK 1325 */ 1326 miocack(q, mp, 0, 0); 1327 break; 1328 1329 case IOC_REPLY: 1330 /* 1331 * OK, send prepared reply as ACK or NAK 1332 */ 1333 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1334 M_IOCACK : M_IOCNAK; 1335 qreply(q, mp); 1336 break; 1337 } 1338 } 1339 1340 static void e1000g_m_blank(void *arg, time_t ticks, uint32_t count) 1341 { 1342 struct e1000g *Adapter; 1343 1344 Adapter = (struct e1000g *)arg; 1345 1346 /* 1347 * Adjust ITR (Interrupt Throttling Register) to coalesce 1348 * interrupts. This formula and its coefficient come from 1349 * our experiments. 1350 */ 1351 if (Adapter->intr_adaptive) { 1352 Adapter->intr_throttling_rate = count << 5; 1353 E1000_WRITE_REG(&Adapter->shared, E1000_ITR, 1354 Adapter->intr_throttling_rate); 1355 } 1356 } 1357 1358 static void 1359 e1000g_m_resources(void *arg) 1360 { 1361 struct e1000g *adapter = (struct e1000g *)arg; 1362 mac_rx_fifo_t mrf; 1363 1364 mrf.mrf_type = MAC_RX_FIFO; 1365 mrf.mrf_blank = e1000g_m_blank; 1366 mrf.mrf_arg = (void *)adapter; 1367 mrf.mrf_normal_blank_time = E1000_RX_INTPT_TIME; 1368 mrf.mrf_normal_pkt_count = E1000_RX_PKT_CNT; 1369 1370 adapter->mrh = mac_resource_add(adapter->mh, (mac_resource_t *)&mrf); 1371 } 1372 1373 static int 1374 e1000g_m_start(void *arg) 1375 { 1376 struct e1000g *Adapter = (struct e1000g *)arg; 1377 1378 return (e1000g_start(Adapter, B_TRUE)); 1379 } 1380 1381 static int 1382 e1000g_start(struct e1000g *Adapter, boolean_t global) 1383 { 1384 if (global) { 1385 /* Allocate dma resources for descriptors and buffers */ 1386 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1387 e1000g_log(Adapter, CE_WARN, 1388 "Alloc DMA resources failed"); 1389 return (ENOTACTIVE); 1390 } 1391 Adapter->rx_buffer_setup = B_FALSE; 1392 } 1393 1394 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1395 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1396 e1000g_log(Adapter, CE_WARN, 1397 "Adapter initialization failed"); 1398 if (global) 1399 e1000g_release_dma_resources(Adapter); 1400 return (ENOTACTIVE); 1401 } 1402 } 1403 1404 rw_enter(&Adapter->chip_lock, RW_WRITER); 1405 1406 /* Setup and initialize the transmit structures */ 1407 e1000g_tx_setup(Adapter); 1408 msec_delay(5); 1409 1410 /* Setup and initialize the receive structures */ 1411 e1000g_rx_setup(Adapter); 1412 msec_delay(5); 1413 1414 e1000g_mask_interrupt(Adapter); 1415 if (Adapter->tx_intr_enable) 1416 e1000g_mask_tx_interrupt(Adapter); 1417 1418 Adapter->started = B_TRUE; 1419 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1420 1421 rw_exit(&Adapter->chip_lock); 1422 1423 /* Enable and start the watchdog timer */ 1424 enable_watchdog_timer(Adapter); 1425 1426 return (0); 1427 } 1428 1429 static void 1430 e1000g_m_stop(void *arg) 1431 { 1432 struct e1000g *Adapter = (struct e1000g *)arg; 1433 1434 e1000g_stop(Adapter, B_TRUE); 1435 } 1436 1437 static void 1438 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1439 { 1440 /* Set stop flags */ 1441 rw_enter(&Adapter->chip_lock, RW_WRITER); 1442 1443 Adapter->started = B_FALSE; 1444 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1445 1446 rw_exit(&Adapter->chip_lock); 1447 1448 /* Drain tx sessions */ 1449 (void) e1000g_tx_drain(Adapter); 1450 1451 /* Disable and stop all the timers */ 1452 disable_watchdog_timer(Adapter); 1453 stop_link_timer(Adapter); 1454 stop_82547_timer(Adapter->tx_ring); 1455 1456 /* Stop the chip and release pending resources */ 1457 rw_enter(&Adapter->chip_lock, RW_WRITER); 1458 1459 e1000g_clear_all_interrupts(Adapter); 1460 e1000_reset_hw(&Adapter->shared); 1461 1462 /* Release resources still held by the TX descriptors */ 1463 e1000g_tx_clean(Adapter); 1464 1465 /* Clean the pending rx jumbo packet fragment */ 1466 e1000g_rx_clean(Adapter); 1467 1468 rw_exit(&Adapter->chip_lock); 1469 1470 if (global) 1471 e1000g_release_dma_resources(Adapter); 1472 } 1473 1474 static void 1475 e1000g_rx_clean(struct e1000g *Adapter) 1476 { 1477 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1478 1479 if (rx_ring->rx_mblk != NULL) { 1480 freemsg(rx_ring->rx_mblk); 1481 rx_ring->rx_mblk = NULL; 1482 rx_ring->rx_mblk_tail = NULL; 1483 rx_ring->rx_mblk_len = 0; 1484 } 1485 } 1486 1487 static void 1488 e1000g_tx_clean(struct e1000g *Adapter) 1489 { 1490 e1000g_tx_ring_t *tx_ring; 1491 p_tx_sw_packet_t packet; 1492 mblk_t *mp; 1493 mblk_t *nmp; 1494 uint32_t packet_count; 1495 1496 tx_ring = Adapter->tx_ring; 1497 1498 /* 1499 * Here we don't need to protect the lists using 1500 * the usedlist_lock and freelist_lock, for they 1501 * have been protected by the chip_lock. 1502 */ 1503 mp = NULL; 1504 nmp = NULL; 1505 packet_count = 0; 1506 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1507 while (packet != NULL) { 1508 if (packet->mp != NULL) { 1509 /* Assemble the message chain */ 1510 if (mp == NULL) { 1511 mp = packet->mp; 1512 nmp = packet->mp; 1513 } else { 1514 nmp->b_next = packet->mp; 1515 nmp = packet->mp; 1516 } 1517 /* Disconnect the message from the sw packet */ 1518 packet->mp = NULL; 1519 } 1520 1521 e1000g_free_tx_swpkt(packet); 1522 packet_count++; 1523 1524 packet = (p_tx_sw_packet_t) 1525 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1526 } 1527 1528 if (mp != NULL) { 1529 mutex_enter(&tx_ring->mblks_lock); 1530 if (tx_ring->mblks.head == NULL) { 1531 tx_ring->mblks.head = mp; 1532 tx_ring->mblks.tail = nmp; 1533 } else { 1534 tx_ring->mblks.tail->b_next = mp; 1535 tx_ring->mblks.tail = nmp; 1536 } 1537 mutex_exit(&tx_ring->mblks_lock); 1538 } 1539 1540 ddi_intr_trigger_softint(Adapter->tx_softint_handle, NULL); 1541 1542 if (packet_count > 0) { 1543 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1544 QUEUE_INIT_LIST(&tx_ring->used_list); 1545 1546 /* Setup TX descriptor pointers */ 1547 tx_ring->tbd_next = tx_ring->tbd_first; 1548 tx_ring->tbd_oldest = tx_ring->tbd_first; 1549 1550 /* Setup our HW Tx Head & Tail descriptor pointers */ 1551 E1000_WRITE_REG(&Adapter->shared, E1000_TDH, 0); 1552 E1000_WRITE_REG(&Adapter->shared, E1000_TDT, 0); 1553 } 1554 } 1555 1556 static boolean_t 1557 e1000g_tx_drain(struct e1000g *Adapter) 1558 { 1559 int i; 1560 boolean_t done; 1561 e1000g_tx_ring_t *tx_ring; 1562 1563 tx_ring = Adapter->tx_ring; 1564 1565 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1566 for (i = 0; i < TX_DRAIN_TIME; i++) { 1567 mutex_enter(&tx_ring->usedlist_lock); 1568 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1569 mutex_exit(&tx_ring->usedlist_lock); 1570 1571 if (done) 1572 break; 1573 1574 msec_delay(1); 1575 } 1576 1577 return (done); 1578 } 1579 1580 static boolean_t 1581 e1000g_rx_drain(struct e1000g *Adapter) 1582 { 1583 e1000g_rx_ring_t *rx_ring; 1584 p_rx_sw_packet_t packet; 1585 boolean_t done; 1586 1587 rx_ring = Adapter->rx_ring; 1588 done = B_TRUE; 1589 1590 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1591 1592 while (rx_ring->pending_list != NULL) { 1593 packet = rx_ring->pending_list; 1594 rx_ring->pending_list = 1595 rx_ring->pending_list->next; 1596 1597 if (packet->flag == E1000G_RX_SW_STOP) { 1598 packet->flag = E1000G_RX_SW_DETACH; 1599 done = B_FALSE; 1600 } else { 1601 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1602 ASSERT(packet->mp == NULL); 1603 e1000g_free_rx_sw_packet(packet); 1604 } 1605 } 1606 1607 rw_exit(&e1000g_rx_detach_lock); 1608 1609 return (done); 1610 } 1611 1612 boolean_t 1613 e1000g_reset(struct e1000g *Adapter) 1614 { 1615 e1000g_stop(Adapter, B_FALSE); 1616 1617 if (e1000g_start(Adapter, B_FALSE)) { 1618 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1619 return (B_FALSE); 1620 } 1621 1622 return (B_TRUE); 1623 } 1624 1625 /* 1626 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1627 * 1628 * This interrupt service routine is for PCI-Express adapters. 1629 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1630 * bit is set. 1631 */ 1632 static uint_t 1633 e1000g_intr_pciexpress(caddr_t arg) 1634 { 1635 struct e1000g *Adapter; 1636 uint32_t icr; 1637 1638 Adapter = (struct e1000g *)arg; 1639 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1640 1641 if (icr & E1000_ICR_INT_ASSERTED) { 1642 /* 1643 * E1000_ICR_INT_ASSERTED bit was set: 1644 * Read(Clear) the ICR, claim this interrupt, 1645 * look for work to do. 1646 */ 1647 e1000g_intr_work(Adapter, icr); 1648 return (DDI_INTR_CLAIMED); 1649 } else { 1650 /* 1651 * E1000_ICR_INT_ASSERTED bit was not set: 1652 * Don't claim this interrupt, return immediately. 1653 */ 1654 return (DDI_INTR_UNCLAIMED); 1655 } 1656 } 1657 1658 /* 1659 * e1000g_intr - ISR for PCI/PCI-X chipsets 1660 * 1661 * This interrupt service routine is for PCI/PCI-X adapters. 1662 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1663 * bit is set or not. 1664 */ 1665 static uint_t 1666 e1000g_intr(caddr_t arg) 1667 { 1668 struct e1000g *Adapter; 1669 uint32_t icr; 1670 1671 Adapter = (struct e1000g *)arg; 1672 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1673 1674 if (icr) { 1675 /* 1676 * Any bit was set in ICR: 1677 * Read(Clear) the ICR, claim this interrupt, 1678 * look for work to do. 1679 */ 1680 e1000g_intr_work(Adapter, icr); 1681 return (DDI_INTR_CLAIMED); 1682 } else { 1683 /* 1684 * No bit was set in ICR: 1685 * Don't claim this interrupt, return immediately. 1686 */ 1687 return (DDI_INTR_UNCLAIMED); 1688 } 1689 } 1690 1691 /* 1692 * e1000g_intr_work - actual processing of ISR 1693 * 1694 * Read(clear) the ICR contents and call appropriate interrupt 1695 * processing routines. 1696 */ 1697 static void 1698 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1699 { 1700 rw_enter(&Adapter->chip_lock, RW_READER); 1701 /* 1702 * Here we need to check the "started" flag within the chip_lock to 1703 * ensure the receive routine will not execute when the adapter is 1704 * being reset. 1705 */ 1706 if (!Adapter->started) { 1707 rw_exit(&Adapter->chip_lock); 1708 return; 1709 } 1710 1711 if (icr & E1000_ICR_RXT0) { 1712 mblk_t *mp; 1713 1714 mutex_enter(&Adapter->rx_ring->rx_lock); 1715 mp = e1000g_receive(Adapter); 1716 mutex_exit(&Adapter->rx_ring->rx_lock); 1717 1718 rw_exit(&Adapter->chip_lock); 1719 1720 if (mp != NULL) 1721 mac_rx(Adapter->mh, Adapter->mrh, mp); 1722 } else 1723 rw_exit(&Adapter->chip_lock); 1724 1725 /* 1726 * The Receive Sequence errors RXSEQ and the link status change LSC 1727 * are checked to detect that the cable has been pulled out. For 1728 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1729 * are an indication that cable is not connected. 1730 */ 1731 if ((icr & E1000_ICR_RXSEQ) || 1732 (icr & E1000_ICR_LSC) || 1733 (icr & E1000_ICR_GPI_EN1)) { 1734 boolean_t link_changed; 1735 timeout_id_t tid = 0; 1736 1737 stop_watchdog_timer(Adapter); 1738 1739 mutex_enter(&Adapter->link_lock); 1740 /* e1000g_link_check takes care of link status change */ 1741 link_changed = e1000g_link_check(Adapter); 1742 /* 1743 * If the link timer has not timed out, we'll not notify 1744 * the upper layer with any link state until the link is up. 1745 */ 1746 if (link_changed && !Adapter->link_complete) { 1747 if (Adapter->link_state == LINK_STATE_UP) { 1748 Adapter->link_complete = B_TRUE; 1749 tid = Adapter->link_tid; 1750 Adapter->link_tid = 0; 1751 } else { 1752 link_changed = B_FALSE; 1753 } 1754 } 1755 mutex_exit(&Adapter->link_lock); 1756 1757 if (link_changed) { 1758 if (tid != 0) 1759 (void) untimeout(tid); 1760 1761 /* 1762 * Workaround for esb2. Data stuck in fifo on a link 1763 * down event. Reset the adapter to recover it. 1764 */ 1765 if ((Adapter->link_state == LINK_STATE_DOWN) && 1766 (Adapter->shared.mac.type == e1000_80003es2lan)) 1767 (void) e1000g_reset(Adapter); 1768 1769 mac_link_update(Adapter->mh, Adapter->link_state); 1770 } 1771 1772 start_watchdog_timer(Adapter); 1773 } 1774 1775 if (icr & E1000G_ICR_TX_INTR) { 1776 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1777 1778 if (!Adapter->tx_intr_enable) 1779 e1000g_clear_tx_interrupt(Adapter); 1780 /* Schedule the re-transmit */ 1781 if (tx_ring->resched_needed) { 1782 E1000G_STAT(tx_ring->stat_reschedule); 1783 tx_ring->resched_needed = B_FALSE; 1784 mac_tx_update(Adapter->mh); 1785 } 1786 if (Adapter->tx_intr_enable) { 1787 /* Recycle the tx descriptors */ 1788 rw_enter(&Adapter->chip_lock, RW_READER); 1789 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1790 e1000g_recycle(tx_ring); 1791 rw_exit(&Adapter->chip_lock); 1792 /* Free the recycled messages */ 1793 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 1794 NULL); 1795 } 1796 } 1797 } 1798 1799 static void 1800 e1000g_init_unicst(struct e1000g *Adapter) 1801 { 1802 struct e1000_hw *hw; 1803 int slot; 1804 1805 hw = &Adapter->shared; 1806 1807 if (Adapter->init_count == 0) { 1808 /* Initialize the multiple unicast addresses */ 1809 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1810 1811 if ((hw->mac.type == e1000_82571) && 1812 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1813 Adapter->unicst_total--; 1814 1815 Adapter->unicst_avail = Adapter->unicst_total - 1; 1816 1817 /* Store the default mac address */ 1818 e1000_rar_set(hw, hw->mac.addr, 0); 1819 if ((hw->mac.type == e1000_82571) && 1820 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1821 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 1822 1823 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 1824 ETHERADDRL); 1825 Adapter->unicst_addr[0].mac.set = 1; 1826 1827 for (slot = 1; slot < Adapter->unicst_total; slot++) 1828 Adapter->unicst_addr[slot].mac.set = 0; 1829 } else { 1830 /* Recover the default mac address */ 1831 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 1832 ETHERADDRL); 1833 1834 /* Store the default mac address */ 1835 e1000_rar_set(hw, hw->mac.addr, 0); 1836 if ((hw->mac.type == e1000_82571) && 1837 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1838 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 1839 1840 /* Re-configure the RAR registers */ 1841 for (slot = 1; slot < Adapter->unicst_total; slot++) 1842 e1000_rar_set(hw, 1843 Adapter->unicst_addr[slot].mac.addr, slot); 1844 } 1845 } 1846 1847 static int 1848 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 1849 { 1850 struct e1000g *Adapter; 1851 1852 Adapter = (struct e1000g *)arg; 1853 1854 /* Store the default MAC address */ 1855 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 1856 1857 /* Set MAC address in address slot 0, which is the default address */ 1858 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 1859 } 1860 1861 static int 1862 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 1863 mac_addr_slot_t slot) 1864 { 1865 struct e1000_hw *hw; 1866 1867 hw = &Adapter->shared; 1868 1869 rw_enter(&Adapter->chip_lock, RW_WRITER); 1870 1871 #ifndef NO_82542_SUPPORT 1872 /* 1873 * The first revision of Wiseman silicon (rev 2.0) has an errata 1874 * that requires the receiver to be in reset when any of the 1875 * receive address registers (RAR regs) are accessed. The first 1876 * rev of Wiseman silicon also requires MWI to be disabled when 1877 * a global reset or a receive reset is issued. So before we 1878 * initialize the RARs, we check the rev of the Wiseman controller 1879 * and work around any necessary HW errata. 1880 */ 1881 if ((hw->mac.type == e1000_82542) && 1882 (hw->revision_id == E1000_REVISION_2)) { 1883 e1000_pci_clear_mwi(hw); 1884 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 1885 msec_delay(5); 1886 } 1887 #endif 1888 1889 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 1890 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 1891 1892 if (slot == 0) { 1893 if ((hw->mac.type == e1000_82571) && 1894 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1895 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 1896 } 1897 1898 #ifndef NO_82542_SUPPORT 1899 /* 1900 * If we are using Wiseman rev 2.0 silicon, we will have previously 1901 * put the receive in reset, and disabled MWI, to work around some 1902 * HW errata. Now we should take the receiver out of reset, and 1903 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 1904 */ 1905 if ((hw->mac.type == e1000_82542) && 1906 (hw->revision_id == E1000_REVISION_2)) { 1907 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1908 msec_delay(1); 1909 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1910 e1000_pci_set_mwi(hw); 1911 e1000g_rx_setup(Adapter); 1912 } 1913 #endif 1914 1915 rw_exit(&Adapter->chip_lock); 1916 1917 return (0); 1918 } 1919 1920 /* 1921 * e1000g_m_unicst_add() - will find an unused address slot, set the 1922 * address value to the one specified, reserve that slot and enable 1923 * the NIC to start filtering on the new MAC address. 1924 * Returns 0 on success. 1925 */ 1926 static int 1927 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 1928 { 1929 struct e1000g *Adapter = (struct e1000g *)arg; 1930 mac_addr_slot_t slot; 1931 int err; 1932 1933 if (mac_unicst_verify(Adapter->mh, 1934 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 1935 return (EINVAL); 1936 1937 rw_enter(&Adapter->chip_lock, RW_WRITER); 1938 if (Adapter->unicst_avail == 0) { 1939 /* no slots available */ 1940 rw_exit(&Adapter->chip_lock); 1941 return (ENOSPC); 1942 } 1943 1944 /* 1945 * Primary/default address is in slot 0. The next addresses 1946 * are the multiple MAC addresses. So multiple MAC address 0 1947 * is in slot 1, 1 in slot 2, and so on. So the first multiple 1948 * MAC address resides in slot 1. 1949 */ 1950 for (slot = 1; slot < Adapter->unicst_total; slot++) { 1951 if (Adapter->unicst_addr[slot].mac.set == 0) { 1952 Adapter->unicst_addr[slot].mac.set = 1; 1953 break; 1954 } 1955 } 1956 1957 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 1958 1959 Adapter->unicst_avail--; 1960 rw_exit(&Adapter->chip_lock); 1961 1962 maddr->mma_slot = slot; 1963 1964 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 1965 rw_enter(&Adapter->chip_lock, RW_WRITER); 1966 Adapter->unicst_addr[slot].mac.set = 0; 1967 Adapter->unicst_avail++; 1968 rw_exit(&Adapter->chip_lock); 1969 } 1970 1971 return (err); 1972 } 1973 1974 /* 1975 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 1976 * call to e1000g_m_unicst_add(). The slot number that was returned in 1977 * e1000g_m_unicst_add() is passed in the call to remove the address. 1978 * Returns 0 on success. 1979 */ 1980 static int 1981 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 1982 { 1983 struct e1000g *Adapter = (struct e1000g *)arg; 1984 int err; 1985 1986 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 1987 return (EINVAL); 1988 1989 rw_enter(&Adapter->chip_lock, RW_WRITER); 1990 if (Adapter->unicst_addr[slot].mac.set == 1) { 1991 Adapter->unicst_addr[slot].mac.set = 0; 1992 Adapter->unicst_avail++; 1993 rw_exit(&Adapter->chip_lock); 1994 1995 /* Copy the default address to the passed slot */ 1996 if (err = e1000g_unicst_set(Adapter, 1997 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 1998 rw_enter(&Adapter->chip_lock, RW_WRITER); 1999 Adapter->unicst_addr[slot].mac.set = 1; 2000 Adapter->unicst_avail--; 2001 rw_exit(&Adapter->chip_lock); 2002 } 2003 return (err); 2004 } 2005 rw_exit(&Adapter->chip_lock); 2006 2007 return (EINVAL); 2008 } 2009 2010 /* 2011 * e1000g_m_unicst_modify() - modifies the value of an address that 2012 * has been added by e1000g_m_unicst_add(). The new address, address 2013 * length and the slot number that was returned in the call to add 2014 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2015 * set to 0. Returns 0 on success. 2016 */ 2017 static int 2018 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2019 { 2020 struct e1000g *Adapter = (struct e1000g *)arg; 2021 mac_addr_slot_t slot; 2022 2023 if (mac_unicst_verify(Adapter->mh, 2024 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2025 return (EINVAL); 2026 2027 slot = maddr->mma_slot; 2028 2029 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2030 return (EINVAL); 2031 2032 rw_enter(&Adapter->chip_lock, RW_WRITER); 2033 if (Adapter->unicst_addr[slot].mac.set == 1) { 2034 rw_exit(&Adapter->chip_lock); 2035 2036 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2037 } 2038 rw_exit(&Adapter->chip_lock); 2039 2040 return (EINVAL); 2041 } 2042 2043 /* 2044 * e1000g_m_unicst_get() - will get the MAC address and all other 2045 * information related to the address slot passed in mac_multi_addr_t. 2046 * mma_flags should be set to 0 in the call. 2047 * On return, mma_flags can take the following values: 2048 * 1) MMAC_SLOT_UNUSED 2049 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2050 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2051 * 4) MMAC_SLOT_USED 2052 */ 2053 static int 2054 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2055 { 2056 struct e1000g *Adapter = (struct e1000g *)arg; 2057 mac_addr_slot_t slot; 2058 2059 slot = maddr->mma_slot; 2060 2061 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2062 return (EINVAL); 2063 2064 rw_enter(&Adapter->chip_lock, RW_WRITER); 2065 if (Adapter->unicst_addr[slot].mac.set == 1) { 2066 bcopy(Adapter->unicst_addr[slot].mac.addr, 2067 maddr->mma_addr, ETHERADDRL); 2068 maddr->mma_flags = MMAC_SLOT_USED; 2069 } else { 2070 maddr->mma_flags = MMAC_SLOT_UNUSED; 2071 } 2072 rw_exit(&Adapter->chip_lock); 2073 2074 return (0); 2075 } 2076 2077 static int 2078 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2079 { 2080 struct e1000_hw *hw = &Adapter->shared; 2081 unsigned i; 2082 int res = 0; 2083 2084 rw_enter(&Adapter->chip_lock, RW_WRITER); 2085 2086 if ((multiaddr[0] & 01) == 0) { 2087 res = EINVAL; 2088 goto done; 2089 } 2090 2091 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2092 res = ENOENT; 2093 goto done; 2094 } 2095 2096 bcopy(multiaddr, 2097 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2098 Adapter->mcast_count++; 2099 2100 /* 2101 * Update the MC table in the hardware 2102 */ 2103 e1000g_clear_interrupt(Adapter); 2104 2105 e1000g_setup_multicast(Adapter); 2106 2107 #ifndef NO_82542_SUPPORT 2108 if ((hw->mac.type == e1000_82542) && 2109 (hw->revision_id == E1000_REVISION_2)) 2110 e1000g_rx_setup(Adapter); 2111 #endif 2112 2113 e1000g_mask_interrupt(Adapter); 2114 2115 done: 2116 rw_exit(&Adapter->chip_lock); 2117 return (res); 2118 } 2119 2120 static int 2121 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2122 { 2123 struct e1000_hw *hw = &Adapter->shared; 2124 unsigned i; 2125 2126 rw_enter(&Adapter->chip_lock, RW_WRITER); 2127 2128 for (i = 0; i < Adapter->mcast_count; i++) { 2129 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2130 ETHERADDRL) == 0) { 2131 for (i++; i < Adapter->mcast_count; i++) { 2132 Adapter->mcast_table[i - 1] = 2133 Adapter->mcast_table[i]; 2134 } 2135 Adapter->mcast_count--; 2136 break; 2137 } 2138 } 2139 2140 /* 2141 * Update the MC table in the hardware 2142 */ 2143 e1000g_clear_interrupt(Adapter); 2144 2145 e1000g_setup_multicast(Adapter); 2146 2147 #ifndef NO_82542_SUPPORT 2148 if ((hw->mac.type == e1000_82542) && 2149 (hw->revision_id == E1000_REVISION_2)) 2150 e1000g_rx_setup(Adapter); 2151 #endif 2152 2153 e1000g_mask_interrupt(Adapter); 2154 2155 done: 2156 rw_exit(&Adapter->chip_lock); 2157 return (0); 2158 } 2159 2160 /* 2161 * e1000g_setup_multicast - setup multicast data structures 2162 * 2163 * This routine initializes all of the multicast related structures. 2164 */ 2165 void 2166 e1000g_setup_multicast(struct e1000g *Adapter) 2167 { 2168 uint8_t *mc_addr_list; 2169 uint32_t mc_addr_count; 2170 uint32_t rctl; 2171 struct e1000_hw *hw; 2172 2173 hw = &Adapter->shared; 2174 2175 /* 2176 * The e1000g has the ability to do perfect filtering of 16 2177 * addresses. The driver uses one of the e1000g's 16 receive 2178 * address registers for its node/network/mac/individual address. 2179 * So, we have room for up to 15 multicast addresses in the CAM, 2180 * additional MC addresses are handled by the MTA (Multicast Table 2181 * Array) 2182 */ 2183 2184 rctl = E1000_READ_REG(hw, E1000_RCTL); 2185 2186 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2187 2188 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2189 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2190 "Adapter requested more than %d MC Addresses.\n", 2191 MAX_NUM_MULTICAST_ADDRESSES); 2192 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2193 } else { 2194 /* 2195 * Set the number of MC addresses that we are being 2196 * requested to use 2197 */ 2198 mc_addr_count = Adapter->mcast_count; 2199 } 2200 #ifndef NO_82542_SUPPORT 2201 /* 2202 * The Wiseman 2.0 silicon has an errata by which the receiver will 2203 * hang while writing to the receive address registers if the receiver 2204 * is not in reset before writing to the registers. Updating the RAR 2205 * is done during the setting up of the multicast table, hence the 2206 * receiver has to be put in reset before updating the multicast table 2207 * and then taken out of reset at the end 2208 */ 2209 /* 2210 * if WMI was enabled then dis able it before issueing the global 2211 * reset to the hardware. 2212 */ 2213 /* 2214 * Only required for WISEMAN_2_0 2215 */ 2216 if ((hw->mac.type == e1000_82542) && 2217 (hw->revision_id == E1000_REVISION_2)) { 2218 e1000_pci_clear_mwi(hw); 2219 /* 2220 * The e1000g must be in reset before changing any RA 2221 * registers. Reset receive unit. The chip will remain in 2222 * the reset state until software explicitly restarts it. 2223 */ 2224 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2225 /* Allow receiver time to go in to reset */ 2226 msec_delay(5); 2227 } 2228 #endif 2229 2230 e1000_mc_addr_list_update(hw, mc_addr_list, mc_addr_count, 2231 Adapter->unicst_total, hw->mac.rar_entry_count); 2232 2233 #ifndef NO_82542_SUPPORT 2234 /* 2235 * Only for Wiseman_2_0 2236 * If MWI was enabled then re-enable it after issueing (as we 2237 * disabled it up there) the receive reset command. 2238 * Wainwright does not have a receive reset command and only thing 2239 * close to it is global reset which will require tx setup also 2240 */ 2241 if ((hw->mac.type == e1000_82542) && 2242 (hw->revision_id == E1000_REVISION_2)) { 2243 /* 2244 * if WMI was enabled then reenable it after issueing the 2245 * global or receive reset to the hardware. 2246 */ 2247 2248 /* 2249 * Take receiver out of reset 2250 * clear E1000_RCTL_RST bit (and all others) 2251 */ 2252 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2253 msec_delay(5); 2254 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2255 e1000_pci_set_mwi(hw); 2256 } 2257 #endif 2258 2259 /* 2260 * Restore original value 2261 */ 2262 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2263 } 2264 2265 int 2266 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2267 { 2268 struct e1000g *Adapter = (struct e1000g *)arg; 2269 2270 return ((add) ? multicst_add(Adapter, addr) 2271 : multicst_remove(Adapter, addr)); 2272 } 2273 2274 int 2275 e1000g_m_promisc(void *arg, boolean_t on) 2276 { 2277 struct e1000g *Adapter = (struct e1000g *)arg; 2278 uint32_t rctl; 2279 2280 rw_enter(&Adapter->chip_lock, RW_WRITER); 2281 2282 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2283 2284 if (on) 2285 rctl |= 2286 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2287 else 2288 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2289 2290 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2291 2292 Adapter->e1000g_promisc = on; 2293 2294 rw_exit(&Adapter->chip_lock); 2295 2296 return (0); 2297 } 2298 2299 static boolean_t 2300 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2301 { 2302 struct e1000g *Adapter = (struct e1000g *)arg; 2303 struct e1000_hw *hw = &Adapter->shared; 2304 2305 switch (cap) { 2306 case MAC_CAPAB_HCKSUM: { 2307 uint32_t *txflags = cap_data; 2308 /* 2309 * Checksum on/off selection via global parameters. 2310 * 2311 * If the chip is flagged as not capable of (correctly) 2312 * handling checksumming, we don't enable it on either 2313 * Rx or Tx side. Otherwise, we take this chip's settings 2314 * from the patchable global defaults. 2315 * 2316 * We advertise our capabilities only if TX offload is 2317 * enabled. On receive, the stack will accept checksummed 2318 * packets anyway, even if we haven't said we can deliver 2319 * them. 2320 */ 2321 switch (hw->mac.type) { 2322 case e1000_82540: 2323 case e1000_82544: 2324 case e1000_82545: 2325 case e1000_82545_rev_3: 2326 case e1000_82546: 2327 case e1000_82546_rev_3: 2328 case e1000_82571: 2329 case e1000_82572: 2330 case e1000_82573: 2331 case e1000_80003es2lan: 2332 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2333 break; 2334 2335 /* 2336 * For the following Intel PRO/1000 chipsets, we have not 2337 * tested the hardware checksum offload capability, so we 2338 * disable the capability for them. 2339 * e1000_82542, 2340 * e1000_82543, 2341 * e1000_82541, 2342 * e1000_82541_rev_2, 2343 * e1000_82547, 2344 * e1000_82547_rev_2, 2345 */ 2346 default: 2347 return (B_FALSE); 2348 } 2349 2350 break; 2351 } 2352 case MAC_CAPAB_POLL: 2353 /* 2354 * There's nothing for us to fill in, simply returning 2355 * B_TRUE stating that we support polling is sufficient. 2356 */ 2357 break; 2358 2359 case MAC_CAPAB_MULTIADDRESS: { 2360 multiaddress_capab_t *mmacp = cap_data; 2361 2362 /* 2363 * The number of MAC addresses made available by 2364 * this capability is one less than the total as 2365 * the primary address in slot 0 is counted in 2366 * the total. 2367 */ 2368 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2369 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2370 /* No multiple factory addresses, set mma_flag to 0 */ 2371 mmacp->maddr_flag = 0; 2372 mmacp->maddr_handle = Adapter; 2373 mmacp->maddr_add = e1000g_m_unicst_add; 2374 mmacp->maddr_remove = e1000g_m_unicst_remove; 2375 mmacp->maddr_modify = e1000g_m_unicst_modify; 2376 mmacp->maddr_get = e1000g_m_unicst_get; 2377 mmacp->maddr_reserve = NULL; 2378 break; 2379 } 2380 default: 2381 return (B_FALSE); 2382 } 2383 return (B_TRUE); 2384 } 2385 2386 /* 2387 * e1000g_get_conf - get configurations set in e1000g.conf 2388 * 2389 * This routine gets user-configured values out of the configuration 2390 * file e1000g.conf. 2391 * 2392 * For each configurable value, there is a minimum, a maximum, and a 2393 * default. 2394 * If user does not configure a value, use the default. 2395 * If user configures below the minimum, use the minumum. 2396 * If user configures above the maximum, use the maxumum. 2397 */ 2398 static void 2399 e1000g_get_conf(struct e1000g *Adapter) 2400 { 2401 struct e1000_hw *hw = &Adapter->shared; 2402 boolean_t tbi_compatibility = B_FALSE; 2403 2404 /* 2405 * get each configurable property from e1000g.conf 2406 */ 2407 2408 /* 2409 * NumTxDescriptors 2410 */ 2411 Adapter->tx_desc_num = 2412 e1000g_get_prop(Adapter, "NumTxDescriptors", 2413 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 2414 DEFAULT_NUM_TX_DESCRIPTOR); 2415 2416 /* 2417 * NumRxDescriptors 2418 */ 2419 Adapter->rx_desc_num = 2420 e1000g_get_prop(Adapter, "NumRxDescriptors", 2421 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 2422 DEFAULT_NUM_RX_DESCRIPTOR); 2423 2424 /* 2425 * NumRxFreeList 2426 */ 2427 Adapter->rx_freelist_num = 2428 e1000g_get_prop(Adapter, "NumRxFreeList", 2429 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 2430 DEFAULT_NUM_RX_FREELIST); 2431 2432 /* 2433 * NumTxPacketList 2434 */ 2435 Adapter->tx_freelist_num = 2436 e1000g_get_prop(Adapter, "NumTxPacketList", 2437 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 2438 DEFAULT_NUM_TX_FREELIST); 2439 2440 /* 2441 * FlowControl 2442 */ 2443 hw->mac.fc_send_xon = B_TRUE; 2444 hw->mac.fc = 2445 e1000g_get_prop(Adapter, "FlowControl", 2446 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 2447 /* 4 is the setting that says "let the eeprom decide" */ 2448 if (hw->mac.fc == 4) 2449 hw->mac.fc = e1000_fc_default; 2450 2451 /* 2452 * Max Num Receive Packets on Interrupt 2453 */ 2454 Adapter->rx_limit_onintr = 2455 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 2456 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 2457 DEFAULT_RX_LIMIT_ON_INTR); 2458 2459 /* 2460 * PHY master slave setting 2461 */ 2462 hw->phy.ms_type = 2463 e1000g_get_prop(Adapter, "SetMasterSlave", 2464 e1000_ms_hw_default, e1000_ms_auto, 2465 e1000_ms_hw_default); 2466 2467 /* 2468 * Parameter which controls TBI mode workaround, which is only 2469 * needed on certain switches such as Cisco 6500/Foundry 2470 */ 2471 tbi_compatibility = 2472 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 2473 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 2474 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 2475 2476 /* 2477 * MSI Enable 2478 */ 2479 Adapter->msi_enabled = 2480 e1000g_get_prop(Adapter, "MSIEnable", 2481 0, 1, DEFAULT_MSI_ENABLE); 2482 2483 /* 2484 * Interrupt Throttling Rate 2485 */ 2486 Adapter->intr_throttling_rate = 2487 e1000g_get_prop(Adapter, "intr_throttling_rate", 2488 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2489 DEFAULT_INTR_THROTTLING); 2490 2491 /* 2492 * Adaptive Interrupt Blanking Enable/Disable 2493 * It is enabled by default 2494 */ 2495 Adapter->intr_adaptive = 2496 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2497 B_TRUE : B_FALSE; 2498 } 2499 2500 /* 2501 * e1000g_get_prop - routine to read properties 2502 * 2503 * Get a user-configure property value out of the configuration 2504 * file e1000g.conf. 2505 * 2506 * Caller provides name of the property, a default value, a minimum 2507 * value, and a maximum value. 2508 * 2509 * Return configured value of the property, with default, minimum and 2510 * maximum properly applied. 2511 */ 2512 static int 2513 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 2514 char *propname, /* name of the property */ 2515 int minval, /* minimum acceptable value */ 2516 int maxval, /* maximim acceptable value */ 2517 int defval) /* default value */ 2518 { 2519 int propval; /* value returned for requested property */ 2520 int *props; /* point to array of properties returned */ 2521 uint_t nprops; /* number of property value returned */ 2522 2523 /* 2524 * get the array of properties from the config file 2525 */ 2526 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2527 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2528 /* got some properties, test if we got enough */ 2529 if (Adapter->instance < nprops) { 2530 propval = props[Adapter->instance]; 2531 } else { 2532 /* not enough properties configured */ 2533 propval = defval; 2534 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2535 "Not Enough %s values found in e1000g.conf" 2536 " - set to %d\n", 2537 propname, propval); 2538 } 2539 2540 /* free memory allocated for properties */ 2541 ddi_prop_free(props); 2542 2543 } else { 2544 propval = defval; 2545 } 2546 2547 /* 2548 * enforce limits 2549 */ 2550 if (propval > maxval) { 2551 propval = maxval; 2552 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2553 "Too High %s value in e1000g.conf - set to %d\n", 2554 propname, propval); 2555 } 2556 2557 if (propval < minval) { 2558 propval = minval; 2559 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 2560 "Too Low %s value in e1000g.conf - set to %d\n", 2561 propname, propval); 2562 } 2563 2564 return (propval); 2565 } 2566 2567 static boolean_t 2568 e1000g_link_check(struct e1000g *Adapter) 2569 { 2570 uint16_t speed, duplex, phydata; 2571 boolean_t link_changed = B_FALSE; 2572 struct e1000_hw *hw; 2573 uint32_t reg_tarc; 2574 2575 hw = &Adapter->shared; 2576 2577 if (e1000g_link_up(Adapter)) { 2578 /* 2579 * The Link is up, check whether it was marked as down earlier 2580 */ 2581 if (Adapter->link_state != LINK_STATE_UP) { 2582 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2583 Adapter->link_speed = speed; 2584 Adapter->link_duplex = duplex; 2585 Adapter->link_state = LINK_STATE_UP; 2586 link_changed = B_TRUE; 2587 2588 Adapter->tx_link_down_timeout = 0; 2589 2590 if ((hw->mac.type == e1000_82571) || 2591 (hw->mac.type == e1000_82572)) { 2592 reg_tarc = E1000_READ_REG(hw, E1000_TARC0); 2593 if (speed == SPEED_1000) 2594 reg_tarc |= (1 << 21); 2595 else 2596 reg_tarc &= ~(1 << 21); 2597 E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); 2598 } 2599 } 2600 Adapter->smartspeed = 0; 2601 } else { 2602 if (Adapter->link_state != LINK_STATE_DOWN) { 2603 Adapter->link_speed = 0; 2604 Adapter->link_duplex = 0; 2605 Adapter->link_state = LINK_STATE_DOWN; 2606 link_changed = B_TRUE; 2607 2608 /* 2609 * SmartSpeed workaround for Tabor/TanaX, When the 2610 * driver loses link disable auto master/slave 2611 * resolution. 2612 */ 2613 if (hw->phy.type == e1000_phy_igp) { 2614 e1000_read_phy_reg(hw, 2615 PHY_1000T_CTRL, &phydata); 2616 phydata |= CR_1000T_MS_ENABLE; 2617 e1000_write_phy_reg(hw, 2618 PHY_1000T_CTRL, phydata); 2619 } 2620 } else { 2621 e1000g_smartspeed(Adapter); 2622 } 2623 2624 if (Adapter->started) { 2625 if (Adapter->tx_link_down_timeout < 2626 MAX_TX_LINK_DOWN_TIMEOUT) { 2627 Adapter->tx_link_down_timeout++; 2628 } else if (Adapter->tx_link_down_timeout == 2629 MAX_TX_LINK_DOWN_TIMEOUT) { 2630 rw_enter(&Adapter->chip_lock, RW_WRITER); 2631 e1000g_tx_clean(Adapter); 2632 rw_exit(&Adapter->chip_lock); 2633 Adapter->tx_link_down_timeout++; 2634 } 2635 } 2636 } 2637 2638 return (link_changed); 2639 } 2640 2641 static void 2642 e1000g_local_timer(void *ws) 2643 { 2644 struct e1000g *Adapter = (struct e1000g *)ws; 2645 struct e1000_hw *hw; 2646 e1000g_ether_addr_t ether_addr; 2647 boolean_t link_changed; 2648 2649 hw = &Adapter->shared; 2650 2651 (void) e1000g_tx_freemsg(Adapter->tx_ring); 2652 2653 if (e1000g_stall_check(Adapter)) { 2654 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 2655 "Tx stall detected. Activate automatic recovery.\n"); 2656 Adapter->reset_count++; 2657 (void) e1000g_reset(Adapter); 2658 } 2659 2660 link_changed = B_FALSE; 2661 mutex_enter(&Adapter->link_lock); 2662 if (Adapter->link_complete) 2663 link_changed = e1000g_link_check(Adapter); 2664 mutex_exit(&Adapter->link_lock); 2665 2666 if (link_changed) { 2667 /* 2668 * Workaround for esb2. Data stuck in fifo on a link 2669 * down event. Reset the adapter to recover it. 2670 */ 2671 if ((Adapter->link_state == LINK_STATE_DOWN) && 2672 (hw->mac.type == e1000_80003es2lan)) 2673 (void) e1000g_reset(Adapter); 2674 2675 mac_link_update(Adapter->mh, Adapter->link_state); 2676 } 2677 2678 /* 2679 * With 82571 controllers, any locally administered address will 2680 * be overwritten when there is a reset on the other port. 2681 * Detect this circumstance and correct it. 2682 */ 2683 if ((hw->mac.type == e1000_82571) && 2684 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 2685 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 2686 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 2687 2688 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2689 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2690 2691 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 2692 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 2693 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 2694 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 2695 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 2696 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 2697 e1000_rar_set(hw, hw->mac.addr, 0); 2698 } 2699 } 2700 2701 /* 2702 * Long TTL workaround for 82541/82547 2703 */ 2704 e1000_igp_ttl_workaround_82547(hw); 2705 2706 /* 2707 * Check for Adaptive IFS settings If there are lots of collisions 2708 * change the value in steps... 2709 * These properties should only be set for 10/100 2710 */ 2711 if ((hw->media_type == e1000_media_type_copper) && 2712 ((Adapter->link_speed == SPEED_100) || 2713 (Adapter->link_speed == SPEED_10))) { 2714 e1000_update_adaptive(hw); 2715 } 2716 /* 2717 * Set Timer Interrupts 2718 */ 2719 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2720 2721 restart_watchdog_timer(Adapter); 2722 } 2723 2724 /* 2725 * The function e1000g_link_timer() is called when the timer for link setup 2726 * is expired, which indicates the completion of the link setup. The link 2727 * state will not be updated until the link setup is completed. And the 2728 * link state will not be sent to the upper layer through mac_link_update() 2729 * in this function. It will be updated in the local timer routine or the 2730 * interrupt service routine after the interface is started (plumbed). 2731 */ 2732 static void 2733 e1000g_link_timer(void *arg) 2734 { 2735 struct e1000g *Adapter = (struct e1000g *)arg; 2736 2737 mutex_enter(&Adapter->link_lock); 2738 Adapter->link_complete = B_TRUE; 2739 Adapter->link_tid = 0; 2740 mutex_exit(&Adapter->link_lock); 2741 } 2742 2743 /* 2744 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 2745 * 2746 * This function read the forced speed and duplex for 10/100 Mbps speeds 2747 * and also for 1000 Mbps speeds from the e1000g.conf file 2748 */ 2749 static void 2750 e1000g_force_speed_duplex(struct e1000g *Adapter) 2751 { 2752 int forced; 2753 struct e1000_mac_info *mac = &Adapter->shared.mac; 2754 struct e1000_phy_info *phy = &Adapter->shared.phy; 2755 2756 /* 2757 * get value out of config file 2758 */ 2759 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 2760 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2761 2762 switch (forced) { 2763 case GDIAG_10_HALF: 2764 /* 2765 * Disable Auto Negotiation 2766 */ 2767 mac->autoneg = B_FALSE; 2768 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2769 break; 2770 case GDIAG_10_FULL: 2771 /* 2772 * Disable Auto Negotiation 2773 */ 2774 mac->autoneg = B_FALSE; 2775 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2776 break; 2777 case GDIAG_100_HALF: 2778 /* 2779 * Disable Auto Negotiation 2780 */ 2781 mac->autoneg = B_FALSE; 2782 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2783 break; 2784 case GDIAG_100_FULL: 2785 /* 2786 * Disable Auto Negotiation 2787 */ 2788 mac->autoneg = B_FALSE; 2789 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2790 break; 2791 case GDIAG_1000_FULL: 2792 /* 2793 * The gigabit spec requires autonegotiation. Therefore, 2794 * when the user wants to force the speed to 1000Mbps, we 2795 * enable AutoNeg, but only allow the harware to advertise 2796 * 1000Mbps. This is different from 10/100 operation, where 2797 * we are allowed to link without any negotiation. 2798 */ 2799 mac->autoneg = B_TRUE; 2800 phy->autoneg_advertised = ADVERTISE_1000_FULL; 2801 break; 2802 default: /* obey the setting of AutoNegAdvertised */ 2803 mac->autoneg = B_TRUE; 2804 phy->autoneg_advertised = 2805 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 2806 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 2807 AUTONEG_ADVERTISE_SPEED_DEFAULT); 2808 break; 2809 } /* switch */ 2810 } 2811 2812 /* 2813 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 2814 * 2815 * This function reads MaxFrameSize from e1000g.conf 2816 */ 2817 static void 2818 e1000g_get_max_frame_size(struct e1000g *Adapter) 2819 { 2820 int max_frame; 2821 struct e1000_mac_info *mac = &Adapter->shared.mac; 2822 struct e1000_phy_info *phy = &Adapter->shared.phy; 2823 2824 /* 2825 * get value out of config file 2826 */ 2827 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 2828 2829 switch (max_frame) { 2830 case 0: 2831 mac->max_frame_size = ETHERMAX; 2832 break; 2833 case 1: 2834 mac->max_frame_size = FRAME_SIZE_UPTO_4K; 2835 break; 2836 case 2: 2837 mac->max_frame_size = FRAME_SIZE_UPTO_8K; 2838 break; 2839 case 3: 2840 if (mac->type < e1000_82571) 2841 mac->max_frame_size = FRAME_SIZE_UPTO_16K; 2842 else 2843 mac->max_frame_size = FRAME_SIZE_UPTO_9K; 2844 break; 2845 default: 2846 mac->max_frame_size = ETHERMAX; 2847 break; 2848 } /* switch */ 2849 2850 /* ich8 does not do jumbo frames */ 2851 if (mac->type == e1000_ich8lan) { 2852 mac->max_frame_size = ETHERMAX; 2853 } 2854 2855 /* ich9 does not do jumbo frames on one phy type */ 2856 if ((mac->type == e1000_ich9lan) && 2857 (phy->type == e1000_phy_ife)) { 2858 mac->max_frame_size = ETHERMAX; 2859 } 2860 } 2861 2862 static void 2863 arm_watchdog_timer(struct e1000g *Adapter) 2864 { 2865 Adapter->watchdog_tid = 2866 timeout(e1000g_local_timer, 2867 (void *)Adapter, 1 * drv_usectohz(1000000)); 2868 } 2869 #pragma inline(arm_watchdog_timer) 2870 2871 static void 2872 enable_watchdog_timer(struct e1000g *Adapter) 2873 { 2874 mutex_enter(&Adapter->watchdog_lock); 2875 2876 if (!Adapter->watchdog_timer_enabled) { 2877 Adapter->watchdog_timer_enabled = B_TRUE; 2878 Adapter->watchdog_timer_started = B_TRUE; 2879 arm_watchdog_timer(Adapter); 2880 } 2881 2882 mutex_exit(&Adapter->watchdog_lock); 2883 } 2884 2885 static void 2886 disable_watchdog_timer(struct e1000g *Adapter) 2887 { 2888 timeout_id_t tid; 2889 2890 mutex_enter(&Adapter->watchdog_lock); 2891 2892 Adapter->watchdog_timer_enabled = B_FALSE; 2893 Adapter->watchdog_timer_started = B_FALSE; 2894 tid = Adapter->watchdog_tid; 2895 Adapter->watchdog_tid = 0; 2896 2897 mutex_exit(&Adapter->watchdog_lock); 2898 2899 if (tid != 0) 2900 (void) untimeout(tid); 2901 } 2902 2903 static void 2904 start_watchdog_timer(struct e1000g *Adapter) 2905 { 2906 mutex_enter(&Adapter->watchdog_lock); 2907 2908 if (Adapter->watchdog_timer_enabled) { 2909 if (!Adapter->watchdog_timer_started) { 2910 Adapter->watchdog_timer_started = B_TRUE; 2911 arm_watchdog_timer(Adapter); 2912 } 2913 } 2914 2915 mutex_exit(&Adapter->watchdog_lock); 2916 } 2917 2918 static void 2919 restart_watchdog_timer(struct e1000g *Adapter) 2920 { 2921 mutex_enter(&Adapter->watchdog_lock); 2922 2923 if (Adapter->watchdog_timer_started) 2924 arm_watchdog_timer(Adapter); 2925 2926 mutex_exit(&Adapter->watchdog_lock); 2927 } 2928 2929 static void 2930 stop_watchdog_timer(struct e1000g *Adapter) 2931 { 2932 timeout_id_t tid; 2933 2934 mutex_enter(&Adapter->watchdog_lock); 2935 2936 Adapter->watchdog_timer_started = B_FALSE; 2937 tid = Adapter->watchdog_tid; 2938 Adapter->watchdog_tid = 0; 2939 2940 mutex_exit(&Adapter->watchdog_lock); 2941 2942 if (tid != 0) 2943 (void) untimeout(tid); 2944 } 2945 2946 static void 2947 stop_link_timer(struct e1000g *Adapter) 2948 { 2949 timeout_id_t tid; 2950 2951 /* Disable the link timer */ 2952 mutex_enter(&Adapter->link_lock); 2953 2954 tid = Adapter->link_tid; 2955 Adapter->link_tid = 0; 2956 2957 mutex_exit(&Adapter->link_lock); 2958 2959 if (tid != 0) 2960 (void) untimeout(tid); 2961 } 2962 2963 static void 2964 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 2965 { 2966 timeout_id_t tid; 2967 2968 /* Disable the tx timer for 82547 chipset */ 2969 mutex_enter(&tx_ring->tx_lock); 2970 2971 tx_ring->timer_enable_82547 = B_FALSE; 2972 tid = tx_ring->timer_id_82547; 2973 tx_ring->timer_id_82547 = 0; 2974 2975 mutex_exit(&tx_ring->tx_lock); 2976 2977 if (tid != 0) 2978 (void) untimeout(tid); 2979 } 2980 2981 void 2982 e1000g_clear_interrupt(struct e1000g *Adapter) 2983 { 2984 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 2985 0xffffffff & ~E1000_IMS_RXSEQ); 2986 } 2987 2988 void 2989 e1000g_mask_interrupt(struct e1000g *Adapter) 2990 { 2991 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 2992 IMS_ENABLE_MASK & ~E1000_IMS_TXDW & ~E1000_IMS_TXQE); 2993 } 2994 2995 void 2996 e1000g_clear_all_interrupts(struct e1000g *Adapter) 2997 { 2998 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 2999 } 3000 3001 void 3002 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 3003 { 3004 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000G_IMS_TX_INTR); 3005 } 3006 3007 void 3008 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 3009 { 3010 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000G_IMS_TX_INTR); 3011 } 3012 3013 static void 3014 e1000g_smartspeed(struct e1000g *Adapter) 3015 { 3016 struct e1000_hw *hw = &Adapter->shared; 3017 uint16_t phy_status; 3018 uint16_t phy_ctrl; 3019 3020 /* 3021 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3022 * advertising 1000Full, we don't even use the workaround 3023 */ 3024 if ((hw->phy.type != e1000_phy_igp) || 3025 !hw->mac.autoneg || 3026 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 3027 return; 3028 3029 /* 3030 * True if this is the first call of this function or after every 3031 * 30 seconds of not having link 3032 */ 3033 if (Adapter->smartspeed == 0) { 3034 /* 3035 * If Master/Slave config fault is asserted twice, we 3036 * assume back-to-back 3037 */ 3038 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3039 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3040 return; 3041 3042 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3043 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3044 return; 3045 /* 3046 * We're assuming back-2-back because our status register 3047 * insists! there's a fault in the master/slave 3048 * relationship that was "negotiated" 3049 */ 3050 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3051 /* 3052 * Is the phy configured for manual configuration of 3053 * master/slave? 3054 */ 3055 if (phy_ctrl & CR_1000T_MS_ENABLE) { 3056 /* 3057 * Yes. Then disable manual configuration (enable 3058 * auto configuration) of master/slave 3059 */ 3060 phy_ctrl &= ~CR_1000T_MS_ENABLE; 3061 e1000_write_phy_reg(hw, 3062 PHY_1000T_CTRL, phy_ctrl); 3063 /* 3064 * Effectively starting the clock 3065 */ 3066 Adapter->smartspeed++; 3067 /* 3068 * Restart autonegotiation 3069 */ 3070 if (!e1000_phy_setup_autoneg(hw) && 3071 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 3072 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 3073 MII_CR_RESTART_AUTO_NEG); 3074 e1000_write_phy_reg(hw, 3075 PHY_CONTROL, phy_ctrl); 3076 } 3077 } 3078 return; 3079 /* 3080 * Has 6 seconds transpired still without link? Remember, 3081 * you should reset the smartspeed counter once you obtain 3082 * link 3083 */ 3084 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 3085 /* 3086 * Yes. Remember, we did at the start determine that 3087 * there's a master/slave configuration fault, so we're 3088 * still assuming there's someone on the other end, but we 3089 * just haven't yet been able to talk to it. We then 3090 * re-enable auto configuration of master/slave to see if 3091 * we're running 2/3 pair cables. 3092 */ 3093 /* 3094 * If still no link, perhaps using 2/3 pair cable 3095 */ 3096 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 3097 phy_ctrl |= CR_1000T_MS_ENABLE; 3098 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 3099 /* 3100 * Restart autoneg with phy enabled for manual 3101 * configuration of master/slave 3102 */ 3103 if (!e1000_phy_setup_autoneg(hw) && 3104 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 3105 phy_ctrl |= 3106 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3107 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3108 } 3109 /* 3110 * Hopefully, there are no more faults and we've obtained 3111 * link as a result. 3112 */ 3113 } 3114 /* 3115 * Restart process after E1000_SMARTSPEED_MAX iterations (30 3116 * seconds) 3117 */ 3118 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 3119 Adapter->smartspeed = 0; 3120 } 3121 3122 static boolean_t 3123 is_valid_mac_addr(uint8_t *mac_addr) 3124 { 3125 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3126 const uint8_t addr_test2[6] = 3127 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3128 3129 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3130 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3131 return (B_FALSE); 3132 3133 return (B_TRUE); 3134 } 3135 3136 /* 3137 * e1000g_stall_check - check for tx stall 3138 * 3139 * This function checks if the adapter is stalled (in transmit). 3140 * 3141 * It is called each time the watchdog timeout is invoked. 3142 * If the transmit descriptor reclaim continuously fails, 3143 * the watchdog value will increment by 1. If the watchdog 3144 * value exceeds the threshold, the adapter is assumed to 3145 * have stalled and need to be reset. 3146 */ 3147 static boolean_t 3148 e1000g_stall_check(struct e1000g *Adapter) 3149 { 3150 e1000g_tx_ring_t *tx_ring; 3151 3152 tx_ring = Adapter->tx_ring; 3153 3154 if (Adapter->link_state != LINK_STATE_UP) 3155 return (B_FALSE); 3156 3157 if (tx_ring->recycle_fail > 0) 3158 tx_ring->stall_watchdog++; 3159 else 3160 tx_ring->stall_watchdog = 0; 3161 3162 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 3163 return (B_FALSE); 3164 3165 tx_ring->stall_watchdog = 0; 3166 tx_ring->recycle_fail = 0; 3167 3168 return (B_TRUE); 3169 } 3170 3171 #ifdef E1000G_DEBUG 3172 static enum ioc_reply 3173 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3174 { 3175 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3176 e1000g_peekpoke_t *ppd; 3177 uint64_t mem_va; 3178 uint64_t maxoff; 3179 boolean_t peek; 3180 3181 switch (iocp->ioc_cmd) { 3182 3183 case E1000G_IOC_REG_PEEK: 3184 peek = B_TRUE; 3185 break; 3186 3187 case E1000G_IOC_REG_POKE: 3188 peek = B_FALSE; 3189 break; 3190 3191 deault: 3192 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 3193 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3194 iocp->ioc_cmd); 3195 return (IOC_INVAL); 3196 } 3197 3198 /* 3199 * Validate format of ioctl 3200 */ 3201 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3202 return (IOC_INVAL); 3203 if (mp->b_cont == NULL) 3204 return (IOC_INVAL); 3205 3206 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3207 3208 /* 3209 * Validate request parameters 3210 */ 3211 switch (ppd->pp_acc_space) { 3212 3213 default: 3214 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 3215 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3216 ppd->pp_acc_space); 3217 return (IOC_INVAL); 3218 3219 case E1000G_PP_SPACE_REG: 3220 /* 3221 * Memory-mapped I/O space 3222 */ 3223 ASSERT(ppd->pp_acc_size == 4); 3224 if (ppd->pp_acc_size != 4) 3225 return (IOC_INVAL); 3226 3227 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3228 return (IOC_INVAL); 3229 3230 mem_va = 0; 3231 maxoff = 0x10000; 3232 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3233 break; 3234 3235 case E1000G_PP_SPACE_E1000G: 3236 /* 3237 * E1000g data structure! 3238 */ 3239 mem_va = (uintptr_t)e1000gp; 3240 maxoff = sizeof (struct e1000g); 3241 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3242 break; 3243 3244 } 3245 3246 if (ppd->pp_acc_offset >= maxoff) 3247 return (IOC_INVAL); 3248 3249 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3250 return (IOC_INVAL); 3251 3252 /* 3253 * All OK - go! 3254 */ 3255 ppd->pp_acc_offset += mem_va; 3256 (*ppfn)(e1000gp, ppd); 3257 return (peek ? IOC_REPLY : IOC_ACK); 3258 } 3259 3260 static void 3261 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3262 { 3263 ddi_acc_handle_t handle; 3264 uint32_t *regaddr; 3265 3266 handle = e1000gp->osdep.reg_handle; 3267 regaddr = 3268 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 3269 3270 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3271 } 3272 3273 static void 3274 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3275 { 3276 ddi_acc_handle_t handle; 3277 uint32_t *regaddr; 3278 uint32_t value; 3279 3280 handle = e1000gp->osdep.reg_handle; 3281 regaddr = 3282 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 3283 value = (uint32_t)ppd->pp_acc_data; 3284 3285 ddi_put32(handle, regaddr, value); 3286 } 3287 3288 static void 3289 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3290 { 3291 uint64_t value; 3292 void *vaddr; 3293 3294 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3295 3296 switch (ppd->pp_acc_size) { 3297 case 1: 3298 value = *(uint8_t *)vaddr; 3299 break; 3300 3301 case 2: 3302 value = *(uint16_t *)vaddr; 3303 break; 3304 3305 case 4: 3306 value = *(uint32_t *)vaddr; 3307 break; 3308 3309 case 8: 3310 value = *(uint64_t *)vaddr; 3311 break; 3312 } 3313 3314 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 3315 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3316 (void *)e1000gp, (void *)ppd, value, vaddr); 3317 3318 ppd->pp_acc_data = value; 3319 } 3320 3321 static void 3322 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3323 { 3324 uint64_t value; 3325 void *vaddr; 3326 3327 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3328 value = ppd->pp_acc_data; 3329 3330 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 3331 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3332 (void *)e1000gp, (void *)ppd, value, vaddr); 3333 3334 switch (ppd->pp_acc_size) { 3335 case 1: 3336 *(uint8_t *)vaddr = (uint8_t)value; 3337 break; 3338 3339 case 2: 3340 *(uint16_t *)vaddr = (uint16_t)value; 3341 break; 3342 3343 case 4: 3344 *(uint32_t *)vaddr = (uint32_t)value; 3345 break; 3346 3347 case 8: 3348 *(uint64_t *)vaddr = (uint64_t)value; 3349 break; 3350 } 3351 } 3352 #endif 3353 3354 /* 3355 * Loopback Support 3356 */ 3357 static lb_property_t lb_normal = 3358 { normal, "normal", E1000G_LB_NONE }; 3359 static lb_property_t lb_external1000 = 3360 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3361 static lb_property_t lb_external100 = 3362 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3363 static lb_property_t lb_external10 = 3364 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3365 static lb_property_t lb_phy = 3366 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3367 3368 static enum ioc_reply 3369 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3370 { 3371 lb_info_sz_t *lbsp; 3372 lb_property_t *lbpp; 3373 struct e1000_hw *hw; 3374 uint32_t *lbmp; 3375 uint32_t size; 3376 uint32_t value; 3377 uint16_t phy_status; 3378 uint16_t phy_ext_status; 3379 3380 hw = &Adapter->shared; 3381 3382 if (mp->b_cont == NULL) 3383 return (IOC_INVAL); 3384 3385 switch (iocp->ioc_cmd) { 3386 default: 3387 return (IOC_INVAL); 3388 3389 case LB_GET_INFO_SIZE: 3390 size = sizeof (lb_info_sz_t); 3391 if (iocp->ioc_count != size) 3392 return (IOC_INVAL); 3393 3394 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3395 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3396 3397 value = sizeof (lb_normal); 3398 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3399 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3400 (hw->media_type == e1000_media_type_fiber) || 3401 (hw->media_type == e1000_media_type_internal_serdes)) { 3402 value += sizeof (lb_phy); 3403 switch (hw->mac.type) { 3404 case e1000_82571: 3405 case e1000_82572: 3406 value += sizeof (lb_external1000); 3407 break; 3408 } 3409 } 3410 if ((phy_status & MII_SR_100X_FD_CAPS) || 3411 (phy_status & MII_SR_100T2_FD_CAPS)) 3412 value += sizeof (lb_external100); 3413 if (phy_status & MII_SR_10T_FD_CAPS) 3414 value += sizeof (lb_external10); 3415 3416 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3417 *lbsp = value; 3418 break; 3419 3420 case LB_GET_INFO: 3421 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3422 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3423 3424 value = sizeof (lb_normal); 3425 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3426 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3427 (hw->media_type == e1000_media_type_fiber) || 3428 (hw->media_type == e1000_media_type_internal_serdes)) { 3429 value += sizeof (lb_phy); 3430 switch (hw->mac.type) { 3431 case e1000_82571: 3432 case e1000_82572: 3433 value += sizeof (lb_external1000); 3434 break; 3435 } 3436 } 3437 if ((phy_status & MII_SR_100X_FD_CAPS) || 3438 (phy_status & MII_SR_100T2_FD_CAPS)) 3439 value += sizeof (lb_external100); 3440 if (phy_status & MII_SR_10T_FD_CAPS) 3441 value += sizeof (lb_external10); 3442 3443 size = value; 3444 if (iocp->ioc_count != size) 3445 return (IOC_INVAL); 3446 3447 value = 0; 3448 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3449 lbpp[value++] = lb_normal; 3450 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3451 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3452 (hw->media_type == e1000_media_type_fiber) || 3453 (hw->media_type == e1000_media_type_internal_serdes)) { 3454 lbpp[value++] = lb_phy; 3455 switch (hw->mac.type) { 3456 case e1000_82571: 3457 case e1000_82572: 3458 lbpp[value++] = lb_external1000; 3459 break; 3460 } 3461 } 3462 if ((phy_status & MII_SR_100X_FD_CAPS) || 3463 (phy_status & MII_SR_100T2_FD_CAPS)) 3464 lbpp[value++] = lb_external100; 3465 if (phy_status & MII_SR_10T_FD_CAPS) 3466 lbpp[value++] = lb_external10; 3467 break; 3468 3469 case LB_GET_MODE: 3470 size = sizeof (uint32_t); 3471 if (iocp->ioc_count != size) 3472 return (IOC_INVAL); 3473 3474 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3475 *lbmp = Adapter->loopback_mode; 3476 break; 3477 3478 case LB_SET_MODE: 3479 size = 0; 3480 if (iocp->ioc_count != sizeof (uint32_t)) 3481 return (IOC_INVAL); 3482 3483 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3484 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3485 return (IOC_INVAL); 3486 break; 3487 } 3488 3489 iocp->ioc_count = size; 3490 iocp->ioc_error = 0; 3491 3492 return (IOC_REPLY); 3493 } 3494 3495 static boolean_t 3496 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3497 { 3498 struct e1000_hw *hw; 3499 #ifndef __sparc 3500 uint32_t reg_rctl; 3501 #endif 3502 int i, times; 3503 3504 if (mode == Adapter->loopback_mode) 3505 return (B_TRUE); 3506 3507 hw = &Adapter->shared; 3508 times = 0; 3509 3510 again: 3511 switch (mode) { 3512 default: 3513 return (B_FALSE); 3514 3515 case E1000G_LB_NONE: 3516 /* Get original speed and duplex settings */ 3517 e1000g_force_speed_duplex(Adapter); 3518 /* Reset the chip */ 3519 hw->phy.wait_for_link = B_TRUE; 3520 (void) e1000g_reset(Adapter); 3521 hw->phy.wait_for_link = B_FALSE; 3522 break; 3523 3524 case E1000G_LB_EXTERNAL_1000: 3525 e1000g_set_external_loopback_1000(Adapter); 3526 break; 3527 3528 case E1000G_LB_EXTERNAL_100: 3529 e1000g_set_external_loopback_100(Adapter); 3530 break; 3531 3532 case E1000G_LB_EXTERNAL_10: 3533 e1000g_set_external_loopback_10(Adapter); 3534 break; 3535 3536 case E1000G_LB_INTERNAL_PHY: 3537 e1000g_set_internal_loopback(Adapter); 3538 break; 3539 } 3540 3541 times++; 3542 3543 switch (mode) { 3544 case E1000G_LB_EXTERNAL_1000: 3545 case E1000G_LB_EXTERNAL_100: 3546 case E1000G_LB_EXTERNAL_10: 3547 case E1000G_LB_INTERNAL_PHY: 3548 /* Wait for link up */ 3549 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 3550 msec_delay(100); 3551 3552 if (!e1000g_link_up(Adapter)) { 3553 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3554 "Failed to get the link up"); 3555 if (times < 2) { 3556 /* Reset the link */ 3557 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3558 "Reset the link ..."); 3559 (void) e1000g_reset(Adapter); 3560 goto again; 3561 } 3562 } 3563 break; 3564 } 3565 3566 Adapter->loopback_mode = mode; 3567 3568 return (B_TRUE); 3569 } 3570 3571 /* 3572 * The following loopback settings are from Intel's technical 3573 * document - "How To Loopback". All the register settings and 3574 * time delay values are directly inherited from the document 3575 * without more explanations available. 3576 */ 3577 static void 3578 e1000g_set_internal_loopback(struct e1000g *Adapter) 3579 { 3580 struct e1000_hw *hw; 3581 uint32_t ctrl; 3582 uint32_t status; 3583 uint16_t phy_ctrl; 3584 3585 hw = &Adapter->shared; 3586 3587 /* Disable Smart Power Down */ 3588 phy_spd_state(hw, B_FALSE); 3589 3590 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3591 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3592 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3593 3594 switch (hw->mac.type) { 3595 case e1000_82540: 3596 case e1000_82545: 3597 case e1000_82545_rev_3: 3598 case e1000_82546: 3599 case e1000_82546_rev_3: 3600 case e1000_82573: 3601 /* Auto-MDI/MDIX off */ 3602 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3603 /* Reset PHY to update Auto-MDI/MDIX */ 3604 e1000_write_phy_reg(hw, PHY_CONTROL, 3605 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3606 /* Reset PHY to auto-neg off and force 1000 */ 3607 e1000_write_phy_reg(hw, PHY_CONTROL, 3608 phy_ctrl | MII_CR_RESET); 3609 break; 3610 } 3611 3612 /* Set loopback */ 3613 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 3614 3615 msec_delay(250); 3616 3617 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3618 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3619 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3620 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3621 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3622 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3623 E1000_CTRL_FD); /* Force Duplex to FULL */ 3624 3625 switch (hw->mac.type) { 3626 case e1000_82540: 3627 case e1000_82545: 3628 case e1000_82545_rev_3: 3629 case e1000_82546: 3630 case e1000_82546_rev_3: 3631 /* 3632 * For some serdes we'll need to commit the writes now 3633 * so that the status is updated on link 3634 */ 3635 if (hw->media_type == e1000_media_type_internal_serdes) { 3636 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3637 msec_delay(100); 3638 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3639 } 3640 3641 if (hw->media_type == e1000_media_type_copper) { 3642 /* Invert Loss of Signal */ 3643 ctrl |= E1000_CTRL_ILOS; 3644 } else { 3645 /* Set ILOS on fiber nic if half duplex is detected */ 3646 status = E1000_READ_REG(hw, E1000_STATUS); 3647 if ((status & E1000_STATUS_FD) == 0) 3648 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3649 } 3650 break; 3651 3652 case e1000_82571: 3653 case e1000_82572: 3654 if (hw->media_type != e1000_media_type_copper) { 3655 /* Set ILOS on fiber nic if half duplex is detected */ 3656 status = E1000_READ_REG(hw, E1000_STATUS); 3657 if ((status & E1000_STATUS_FD) == 0) 3658 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3659 } 3660 break; 3661 3662 case e1000_82573: 3663 ctrl |= E1000_CTRL_ILOS; 3664 break; 3665 } 3666 3667 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3668 3669 /* 3670 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3671 * For background, see comments above e1000g_set_internal_loopback(). 3672 */ 3673 switch (hw->mac.type) { 3674 case e1000_82540: 3675 case e1000_82545: 3676 case e1000_82545_rev_3: 3677 case e1000_82546: 3678 case e1000_82546_rev_3: 3679 case e1000_82573: 3680 e1000_write_phy_reg(hw, 29, 0x001F); 3681 e1000_write_phy_reg(hw, 30, 0x8FFC); 3682 e1000_write_phy_reg(hw, 29, 0x001A); 3683 e1000_write_phy_reg(hw, 30, 0x8FF0); 3684 break; 3685 } 3686 } 3687 3688 static void 3689 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3690 { 3691 struct e1000_hw *hw; 3692 uint32_t rctl; 3693 uint32_t ctrl_ext; 3694 uint32_t ctrl; 3695 uint32_t status; 3696 uint32_t txcw; 3697 3698 hw = &Adapter->shared; 3699 3700 /* Disable Smart Power Down */ 3701 phy_spd_state(hw, B_FALSE); 3702 3703 switch (hw->media_type) { 3704 case e1000_media_type_copper: 3705 /* Force link up (Must be done before the PHY writes) */ 3706 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3707 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3708 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3709 3710 rctl = E1000_READ_REG(hw, E1000_RCTL); 3711 rctl |= (E1000_RCTL_EN | 3712 E1000_RCTL_SBP | 3713 E1000_RCTL_UPE | 3714 E1000_RCTL_MPE | 3715 E1000_RCTL_LPE | 3716 E1000_RCTL_BAM); /* 0x803E */ 3717 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3718 3719 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3720 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3721 E1000_CTRL_EXT_SDP6_DATA | 3722 E1000_CTRL_EXT_SDP7_DATA | 3723 E1000_CTRL_EXT_SDP4_DIR | 3724 E1000_CTRL_EXT_SDP6_DIR | 3725 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3726 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3727 3728 /* 3729 * This sequence tunes the PHY's SDP and no customer 3730 * settable values. For background, see comments above 3731 * e1000g_set_internal_loopback(). 3732 */ 3733 e1000_write_phy_reg(hw, 0x0, 0x140); 3734 msec_delay(10); 3735 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3736 e1000_write_phy_reg(hw, 0x12, 0xC10); 3737 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3738 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3739 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3740 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3741 3742 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3743 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3744 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3745 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3746 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3747 3748 msec_delay(50); 3749 break; 3750 case e1000_media_type_fiber: 3751 case e1000_media_type_internal_serdes: 3752 status = E1000_READ_REG(hw, E1000_STATUS); 3753 if (((status & E1000_STATUS_LU) == 0) || 3754 (hw->media_type == e1000_media_type_internal_serdes)) { 3755 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3756 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3757 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3758 } 3759 3760 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3761 txcw = E1000_READ_REG(hw, E1000_TXCW); 3762 txcw &= ~((uint32_t)1 << 31); 3763 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 3764 3765 /* 3766 * Write 0x410 to Serdes Control register 3767 * to enable Serdes analog loopback 3768 */ 3769 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 3770 msec_delay(10); 3771 break; 3772 default: 3773 break; 3774 } 3775 } 3776 3777 static void 3778 e1000g_set_external_loopback_100(struct e1000g *Adapter) 3779 { 3780 struct e1000_hw *hw; 3781 uint32_t ctrl; 3782 uint16_t phy_ctrl; 3783 3784 hw = &Adapter->shared; 3785 3786 /* Disable Smart Power Down */ 3787 phy_spd_state(hw, B_FALSE); 3788 3789 phy_ctrl = (MII_CR_FULL_DUPLEX | 3790 MII_CR_SPEED_100); 3791 3792 /* Force 100/FD, reset PHY */ 3793 e1000_write_phy_reg(hw, PHY_CONTROL, 3794 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 3795 msec_delay(10); 3796 3797 /* Force 100/FD */ 3798 e1000_write_phy_reg(hw, PHY_CONTROL, 3799 phy_ctrl); /* 0x2100 */ 3800 msec_delay(10); 3801 3802 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3803 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3804 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3805 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3806 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3807 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3808 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 3809 E1000_CTRL_FD); /* Force Duplex to FULL */ 3810 3811 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3812 } 3813 3814 static void 3815 e1000g_set_external_loopback_10(struct e1000g *Adapter) 3816 { 3817 struct e1000_hw *hw; 3818 uint32_t ctrl; 3819 uint16_t phy_ctrl; 3820 3821 hw = &Adapter->shared; 3822 3823 /* Disable Smart Power Down */ 3824 phy_spd_state(hw, B_FALSE); 3825 3826 phy_ctrl = (MII_CR_FULL_DUPLEX | 3827 MII_CR_SPEED_10); 3828 3829 /* Force 10/FD, reset PHY */ 3830 e1000_write_phy_reg(hw, PHY_CONTROL, 3831 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 3832 msec_delay(10); 3833 3834 /* Force 10/FD */ 3835 e1000_write_phy_reg(hw, PHY_CONTROL, 3836 phy_ctrl); /* 0x0100 */ 3837 msec_delay(10); 3838 3839 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3840 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3841 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3842 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3843 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3844 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3845 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 3846 E1000_CTRL_FD); /* Force Duplex to FULL */ 3847 3848 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3849 } 3850 3851 #ifdef __sparc 3852 static boolean_t 3853 e1000g_find_mac_address(struct e1000g *Adapter) 3854 { 3855 struct e1000_hw *hw = &Adapter->shared; 3856 uchar_t *bytes; 3857 struct ether_addr sysaddr; 3858 uint_t nelts; 3859 int err; 3860 boolean_t found = B_FALSE; 3861 3862 /* 3863 * The "vendor's factory-set address" may already have 3864 * been extracted from the chip, but if the property 3865 * "local-mac-address" is set we use that instead. 3866 * 3867 * We check whether it looks like an array of 6 3868 * bytes (which it should, if OBP set it). If we can't 3869 * make sense of it this way, we'll ignore it. 3870 */ 3871 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3872 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3873 if (err == DDI_PROP_SUCCESS) { 3874 if (nelts == ETHERADDRL) { 3875 while (nelts--) 3876 hw->mac.addr[nelts] = bytes[nelts]; 3877 found = B_TRUE; 3878 } 3879 ddi_prop_free(bytes); 3880 } 3881 3882 /* 3883 * Look up the OBP property "local-mac-address?". If the user has set 3884 * 'local-mac-address? = false', use "the system address" instead. 3885 */ 3886 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 3887 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3888 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3889 if (localetheraddr(NULL, &sysaddr) != 0) { 3890 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 3891 found = B_TRUE; 3892 } 3893 } 3894 ddi_prop_free(bytes); 3895 } 3896 3897 /* 3898 * Finally(!), if there's a valid "mac-address" property (created 3899 * if we netbooted from this interface), we must use this instead 3900 * of any of the above to ensure that the NFS/install server doesn't 3901 * get confused by the address changing as Solaris takes over! 3902 */ 3903 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3904 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3905 if (err == DDI_PROP_SUCCESS) { 3906 if (nelts == ETHERADDRL) { 3907 while (nelts--) 3908 hw->mac.addr[nelts] = bytes[nelts]; 3909 found = B_TRUE; 3910 } 3911 ddi_prop_free(bytes); 3912 } 3913 3914 if (found) { 3915 bcopy(hw->mac.addr, hw->mac.perm_addr, 3916 ETHERADDRL); 3917 } 3918 3919 return (found); 3920 } 3921 #endif 3922 3923 static int 3924 e1000g_add_intrs(struct e1000g *Adapter) 3925 { 3926 dev_info_t *devinfo; 3927 int intr_types; 3928 int rc; 3929 3930 devinfo = Adapter->dip; 3931 3932 /* Get supported interrupt types */ 3933 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3934 3935 if (rc != DDI_SUCCESS) { 3936 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 3937 "Get supported interrupt types failed: %d\n", rc); 3938 return (DDI_FAILURE); 3939 } 3940 3941 /* 3942 * Based on Intel Technical Advisory document (TA-160), there are some 3943 * cases where some older Intel PCI-X NICs may "advertise" to the OS 3944 * that it supports MSI, but in fact has problems. 3945 * So we should only enable MSI for PCI-E NICs and disable MSI for old 3946 * PCI/PCI-X NICs. 3947 */ 3948 if (Adapter->shared.mac.type < e1000_82571) 3949 Adapter->msi_enabled = B_FALSE; 3950 3951 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 3952 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 3953 3954 if (rc != DDI_SUCCESS) { 3955 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 3956 "Add MSI failed, trying Legacy interrupts\n"); 3957 } else { 3958 Adapter->intr_type = DDI_INTR_TYPE_MSI; 3959 } 3960 } 3961 3962 if ((Adapter->intr_type == 0) && 3963 (intr_types & DDI_INTR_TYPE_FIXED)) { 3964 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 3965 3966 if (rc != DDI_SUCCESS) { 3967 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 3968 "Add Legacy interrupts failed\n"); 3969 return (DDI_FAILURE); 3970 } 3971 3972 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 3973 } 3974 3975 if (Adapter->intr_type == 0) { 3976 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 3977 "No interrupts registered\n"); 3978 return (DDI_FAILURE); 3979 } 3980 3981 return (DDI_SUCCESS); 3982 } 3983 3984 /* 3985 * e1000g_intr_add() handles MSI/Legacy interrupts 3986 */ 3987 static int 3988 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 3989 { 3990 dev_info_t *devinfo; 3991 int count, avail, actual; 3992 int x, y, rc, inum = 0; 3993 int flag; 3994 ddi_intr_handler_t *intr_handler; 3995 3996 devinfo = Adapter->dip; 3997 3998 /* get number of interrupts */ 3999 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4000 if ((rc != DDI_SUCCESS) || (count == 0)) { 4001 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4002 "Get interrupt number failed. Return: %d, count: %d\n", 4003 rc, count); 4004 return (DDI_FAILURE); 4005 } 4006 4007 /* get number of available interrupts */ 4008 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4009 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4010 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4011 "Get interrupt available number failed. " 4012 "Return: %d, available: %d\n", rc, avail); 4013 return (DDI_FAILURE); 4014 } 4015 4016 if (avail < count) { 4017 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4018 "Interrupts count: %d, available: %d\n", 4019 count, avail); 4020 } 4021 4022 /* Allocate an array of interrupt handles */ 4023 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 4024 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 4025 4026 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 4027 flag = DDI_INTR_ALLOC_NORMAL; 4028 4029 /* call ddi_intr_alloc() */ 4030 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 4031 count, &actual, flag); 4032 4033 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4034 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4035 "Allocate interrupts failed: %d\n", rc); 4036 4037 kmem_free(Adapter->htable, Adapter->intr_size); 4038 return (DDI_FAILURE); 4039 } 4040 4041 if (actual < count) { 4042 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4043 "Interrupts requested: %d, received: %d\n", 4044 count, actual); 4045 } 4046 4047 Adapter->intr_cnt = actual; 4048 4049 /* Get priority for first msi, assume remaining are all the same */ 4050 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 4051 4052 if (rc != DDI_SUCCESS) { 4053 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4054 "Get interrupt priority failed: %d\n", rc); 4055 4056 /* Free already allocated intr */ 4057 for (y = 0; y < actual; y++) 4058 (void) ddi_intr_free(Adapter->htable[y]); 4059 4060 kmem_free(Adapter->htable, Adapter->intr_size); 4061 return (DDI_FAILURE); 4062 } 4063 4064 /* 4065 * In Legacy Interrupt mode, for PCI-Express adapters, we should 4066 * use the interrupt service routine e1000g_intr_pciexpress() 4067 * to avoid interrupt stealing when sharing interrupt with other 4068 * devices. 4069 */ 4070 if (Adapter->shared.mac.type < e1000_82571) 4071 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 4072 else 4073 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 4074 4075 /* Call ddi_intr_add_handler() */ 4076 for (x = 0; x < actual; x++) { 4077 rc = ddi_intr_add_handler(Adapter->htable[x], 4078 intr_handler, (caddr_t)Adapter, NULL); 4079 4080 if (rc != DDI_SUCCESS) { 4081 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4082 "Add interrupt handler failed: %d\n", rc); 4083 4084 /* Remove already added handler */ 4085 for (y = 0; y < x; y++) 4086 (void) ddi_intr_remove_handler( 4087 Adapter->htable[y]); 4088 4089 /* Free already allocated intr */ 4090 for (y = 0; y < actual; y++) 4091 (void) ddi_intr_free(Adapter->htable[y]); 4092 4093 kmem_free(Adapter->htable, Adapter->intr_size); 4094 return (DDI_FAILURE); 4095 } 4096 } 4097 4098 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 4099 4100 if (rc != DDI_SUCCESS) { 4101 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4102 "Get interrupt cap failed: %d\n", rc); 4103 4104 /* Free already allocated intr */ 4105 for (y = 0; y < actual; y++) { 4106 (void) ddi_intr_remove_handler(Adapter->htable[y]); 4107 (void) ddi_intr_free(Adapter->htable[y]); 4108 } 4109 4110 kmem_free(Adapter->htable, Adapter->intr_size); 4111 return (DDI_FAILURE); 4112 } 4113 4114 return (DDI_SUCCESS); 4115 } 4116 4117 static int 4118 e1000g_rem_intrs(struct e1000g *Adapter) 4119 { 4120 int x; 4121 int rc; 4122 4123 for (x = 0; x < Adapter->intr_cnt; x++) { 4124 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4125 if (rc != DDI_SUCCESS) { 4126 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4127 "Remove intr handler failed: %d\n", rc); 4128 return (DDI_FAILURE); 4129 } 4130 4131 rc = ddi_intr_free(Adapter->htable[x]); 4132 if (rc != DDI_SUCCESS) { 4133 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4134 "Free intr failed: %d\n", rc); 4135 return (DDI_FAILURE); 4136 } 4137 } 4138 4139 kmem_free(Adapter->htable, Adapter->intr_size); 4140 4141 return (DDI_SUCCESS); 4142 } 4143 4144 static int 4145 e1000g_enable_intrs(struct e1000g *Adapter) 4146 { 4147 int x; 4148 int rc; 4149 4150 /* Enable interrupts */ 4151 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4152 /* Call ddi_intr_block_enable() for MSI */ 4153 rc = ddi_intr_block_enable(Adapter->htable, 4154 Adapter->intr_cnt); 4155 if (rc != DDI_SUCCESS) { 4156 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4157 "Enable block intr failed: %d\n", rc); 4158 return (DDI_FAILURE); 4159 } 4160 } else { 4161 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4162 for (x = 0; x < Adapter->intr_cnt; x++) { 4163 rc = ddi_intr_enable(Adapter->htable[x]); 4164 if (rc != DDI_SUCCESS) { 4165 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4166 "Enable intr failed: %d\n", rc); 4167 return (DDI_FAILURE); 4168 } 4169 } 4170 } 4171 4172 return (DDI_SUCCESS); 4173 } 4174 4175 static int 4176 e1000g_disable_intrs(struct e1000g *Adapter) 4177 { 4178 int x; 4179 int rc; 4180 4181 /* Disable all interrupts */ 4182 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4183 rc = ddi_intr_block_disable(Adapter->htable, 4184 Adapter->intr_cnt); 4185 if (rc != DDI_SUCCESS) { 4186 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4187 "Disable block intr failed: %d\n", rc); 4188 return (DDI_FAILURE); 4189 } 4190 } else { 4191 for (x = 0; x < Adapter->intr_cnt; x++) { 4192 rc = ddi_intr_disable(Adapter->htable[x]); 4193 if (rc != DDI_SUCCESS) { 4194 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4195 "Disable intr failed: %d\n", rc); 4196 return (DDI_FAILURE); 4197 } 4198 } 4199 } 4200 4201 return (DDI_SUCCESS); 4202 } 4203