175eba5b6SRobert Mustacchi /****************************************************************************** 275eba5b6SRobert Mustacchi 3*7c5988f9SRobert Mustacchi Copyright (c) 2001-2015, Intel Corporation 475eba5b6SRobert Mustacchi All rights reserved. 575eba5b6SRobert Mustacchi 675eba5b6SRobert Mustacchi Redistribution and use in source and binary forms, with or without 775eba5b6SRobert Mustacchi modification, are permitted provided that the following conditions are met: 875eba5b6SRobert Mustacchi 975eba5b6SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 1075eba5b6SRobert Mustacchi this list of conditions and the following disclaimer. 1175eba5b6SRobert Mustacchi 1275eba5b6SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 1375eba5b6SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 1475eba5b6SRobert Mustacchi documentation and/or other materials provided with the distribution. 1575eba5b6SRobert Mustacchi 1675eba5b6SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 1775eba5b6SRobert Mustacchi contributors may be used to endorse or promote products derived from 1875eba5b6SRobert Mustacchi this software without specific prior written permission. 1975eba5b6SRobert Mustacchi 2075eba5b6SRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2175eba5b6SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2275eba5b6SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2375eba5b6SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2475eba5b6SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2575eba5b6SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2675eba5b6SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2775eba5b6SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2875eba5b6SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2975eba5b6SRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3075eba5b6SRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 3175eba5b6SRobert Mustacchi 3275eba5b6SRobert Mustacchi ******************************************************************************/ 3375eba5b6SRobert Mustacchi /*$FreeBSD$*/ 3475eba5b6SRobert Mustacchi 3575eba5b6SRobert Mustacchi #ifndef _E1000_MANAGE_H_ 3675eba5b6SRobert Mustacchi #define _E1000_MANAGE_H_ 3775eba5b6SRobert Mustacchi 3875eba5b6SRobert Mustacchi bool e1000_check_mng_mode_generic(struct e1000_hw *hw); 3975eba5b6SRobert Mustacchi bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw); 4075eba5b6SRobert Mustacchi s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw); 4175eba5b6SRobert Mustacchi s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, 4275eba5b6SRobert Mustacchi u16 length, u16 offset, u8 *sum); 4375eba5b6SRobert Mustacchi s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, 4475eba5b6SRobert Mustacchi struct e1000_host_mng_command_header *hdr); 4575eba5b6SRobert Mustacchi s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, 4675eba5b6SRobert Mustacchi u8 *buffer, u16 length); 4775eba5b6SRobert Mustacchi bool e1000_enable_mng_pass_thru(struct e1000_hw *hw); 4875eba5b6SRobert Mustacchi u8 e1000_calculate_checksum(u8 *buffer, u32 length); 4975eba5b6SRobert Mustacchi s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length); 5075eba5b6SRobert Mustacchi s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length); 5175eba5b6SRobert Mustacchi 5275eba5b6SRobert Mustacchi enum e1000_mng_mode { 5375eba5b6SRobert Mustacchi e1000_mng_mode_none = 0, 5475eba5b6SRobert Mustacchi e1000_mng_mode_asf, 5575eba5b6SRobert Mustacchi e1000_mng_mode_pt, 5675eba5b6SRobert Mustacchi e1000_mng_mode_ipmi, 5775eba5b6SRobert Mustacchi e1000_mng_mode_host_if_only 5875eba5b6SRobert Mustacchi }; 5975eba5b6SRobert Mustacchi 6075eba5b6SRobert Mustacchi #define E1000_FACTPS_MNGCG 0x20000000 6175eba5b6SRobert Mustacchi 6275eba5b6SRobert Mustacchi #define E1000_FWSM_MODE_MASK 0xE 6375eba5b6SRobert Mustacchi #define E1000_FWSM_MODE_SHIFT 1 6475eba5b6SRobert Mustacchi #define E1000_FWSM_FW_VALID 0x00008000 6575eba5b6SRobert Mustacchi #define E1000_FWSM_HI_EN_ONLY_MODE 0x4 6675eba5b6SRobert Mustacchi 6775eba5b6SRobert Mustacchi #define E1000_MNG_IAMT_MODE 0x3 6875eba5b6SRobert Mustacchi #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 6975eba5b6SRobert Mustacchi #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 7075eba5b6SRobert Mustacchi #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 7175eba5b6SRobert Mustacchi #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 7275eba5b6SRobert Mustacchi #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 7375eba5b6SRobert Mustacchi #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 7475eba5b6SRobert Mustacchi 7575eba5b6SRobert Mustacchi #define E1000_VFTA_ENTRY_SHIFT 5 7675eba5b6SRobert Mustacchi #define E1000_VFTA_ENTRY_MASK 0x7F 7775eba5b6SRobert Mustacchi #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 7875eba5b6SRobert Mustacchi 7975eba5b6SRobert Mustacchi #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 8075eba5b6SRobert Mustacchi #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 8175eba5b6SRobert Mustacchi #define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI cmd limit */ 8275eba5b6SRobert Mustacchi #define E1000_HI_FW_BASE_ADDRESS 0x10000 8375eba5b6SRobert Mustacchi #define E1000_HI_FW_MAX_LENGTH (64 * 1024) /* Num of bytes */ 8475eba5b6SRobert Mustacchi #define E1000_HI_FW_BLOCK_DWORD_LENGTH 256 /* Num of DWORDs per page */ 8575eba5b6SRobert Mustacchi #define E1000_HICR_MEMORY_BASE_EN 0x200 /* MB Enable bit - RO */ 8675eba5b6SRobert Mustacchi #define E1000_HICR_EN 0x01 /* Enable bit - RO */ 8775eba5b6SRobert Mustacchi /* Driver sets this bit when done to put command in RAM */ 8875eba5b6SRobert Mustacchi #define E1000_HICR_C 0x02 8975eba5b6SRobert Mustacchi #define E1000_HICR_SV 0x04 /* Status Validity */ 9075eba5b6SRobert Mustacchi #define E1000_HICR_FW_RESET_ENABLE 0x40 9175eba5b6SRobert Mustacchi #define E1000_HICR_FW_RESET 0x80 9275eba5b6SRobert Mustacchi 9375eba5b6SRobert Mustacchi /* Intel(R) Active Management Technology signature */ 9475eba5b6SRobert Mustacchi #define E1000_IAMT_SIGNATURE 0x544D4149 9575eba5b6SRobert Mustacchi 9675eba5b6SRobert Mustacchi #endif 97